| FAIRCHILD err prensa ree rereepearer SEMICONDUCTOR MM74HC595 September 1983 Revised February 1999 8-Bit Shift Registers with Output Latches General Description The MM74HC595 high speed shift register utilizes advanced silicon-gate CMOS technology. This device pos- sesses the high noise immunity and low power consump- tion of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. This device contains an 8-bit serial-in, parallel-out shift reg- ister that feeds an 8-bit D-type storage register. The stor- age register has 8 3-STATE outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output (standard) pins for cascading. Both the shift register and storage register use positive-edge trig- gered clocks. If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register. The 74HC logic family is speed, function, and pin-out com- patible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to Voc and ground. Features Hi Low quiescent current: 80 pA maximum (74HC Series) @ Low input current: 1 wA maximum lf 8-bit serial-in, parallel-out shift register with storage lf Wide operating voltage range: 2V-6V i Cascadable lf Shift register has direct clear lM Guaranteed shift frequency: DC to 30 MHz Ordering Code: Order Number | Package Number Package Description MM74HC595M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC595WM M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide MM74HC595SU M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC595MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC595N N16E 16-Lead Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Connection Diagram Truth Table Pin Assignments for DIP, SOIC, SOP and TSSOP RcK | sck | SCLR| G Function 1 Qe VY 16, Vee x x x H 1Qa thru Qy = 3-STATE or 5 on x x L L_ | Shift Register cleared 4 sep QH=0 ot Be x t H L_ | Shift Register clocked 4 aS 5 PP Qn = Qpy-1, Q9g = SER Qe P RCK 7 tT xX H L | Contents of Shift Q 4 Ho scx 8 Register transferred 7 oH p= SCLR to output latches eno O'y Top View 1999 Fairchild Semiconductor Corporation DS005342. prf www.fairchildsemi.com s9yoje7 3ndjnoO YUM Sie}sibey WINS Hg-8 S6SOHPZININMM74HC595 Logic Diagram (positive logic) . =d> 12 RCK 2 0>o.______ SER *h>f> > oa a) 5 on OD> or R 1 0 a D QPpo Og eoP Or> R 2 Da dD ab. Oc eop op R 3 po DD Ofo= Qo oop @e-op I a PARALLEL DATA OUTPUTS 4 L dD oa DD OfO4 Oe op or R 5 . 60 D Of Or O> or R Li. 6 doa DD 6ofo= Og eor- O> R 7 1 D Qa D Q Qu SCK >> Op L_of> R 10 9 .. SERIAL DATA ei #__P> >_> , OUTPUT No www.fairchildsemi.comAbsolute Maximum Ratingsinote 1) Recommended Operating (Note 2) Conditions Supply Voltage (Voc) 0.5 to +7.0V Min) Max Units DC Input Voltage (Vij) 1.5 to Veg +1.5V Supply Voltage (Voc) 2 6 Vv DC Output Voltage (Vout) -0.5 10 Veo +0.5V DC Input or Output Voltage Clamp Diode Current (Ik; lox) +20 mA (Vin, Vout) 0 Voc Vv DC Output Current, per pin (lout) 435A Operating Temperature Range (Ta) -40 +85 C DC Vgc or GND Current, Input Rise or Fall Times per pin (lec) 70 mA (tp t) Voo =2.0V 1000 ns Storage Temperature Range (Tstq) 65C to +150C Voc = 4.5V 500 ns Power Dissipation (Pp) Voc = 6.0V 400 ns (Note 3) 600 mW Note 1: Absolute Maximum Ratings are those values beyond which dam- Ss.oO. Package only 500 mw age to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Lead Temperature (T,) ee . aa Note 3: Power Dissipation temperature derating plastic N package: (Soldering 10 seconds) 260C - 12 mW/C from 65C to 85C. DC Electrical Characteristics (note 4) S6SOHPZNN Ta= 25C Ta =40 to 85C | T, =55 to 125C Symbol Parameter Conditions Veco Units Typ Guaranteed Limits Vin Minimum HIGH Level 2.0V 1.5 1.5 1.5 Vv Input Voltage 4.5V 3.15 3.15 3.15 Vv 6.0V 4.2 4.2 4.2 Vv Vit Maximum LOW Level 2.0V 0.5 0.5 0.5 Vv Input Voltage 4.5V 1.35 1.35 1.35 Vv 6.0V 1.8 1.8 1.8 Vv Vou Minimum HIGH Level Vin= Vin oF Vit Output Voltage lloutl < 20 pA 2.0V 2.0 1.9 1.9 1.9 Vv 4.5V 45 44 44 44 Vv 6.0V 6.0 5.9 5.9 5.9 Vv Qu Vin = Vin oF Vit llout| < 4.0 mA 4.5V 4.2 3.98 3.84 3.7 Vv llour| < 5.2 mA 6.0V 5.2 5.48 5.34 5.2 Vv Qa thru Qy Vin= Vin oF Vit llout| < 6.0 mA 4.5V 4.2 3.98 3.84 3.7 Vv llourl < 7-8 mA 6.0V 5.7 5.48 5.34 5.2 Vv VoL Maximum LOW Level Vin= Vin or Vit Output Voltage lloutl < 20 pA 2.0V 0 0.1 0.1 0.1 Vv 4.5V 0 0.1 0.1 0.1 Vv 6.0V 0 0.1 0.1 0.1 Vv Qu Vin = Vin oF Vit llourl < 4 mA 4.5V 0.2 0.26 0.33 0.4 Vv llout| < 5.2 mA 6.0V 0.2 0.26 0.33 0.4 Qa thru Qy Vin= Vin oF Vit llourl < 6.0 mA 4.5V 0.2 0.26 0.33 0.4 Vv llout| < 7-8 mA 6.0V 0.2 0.26 0.33 0.4 Vv lI Maximum Input Vin= Voc or GND 6.0V +0.1 +1.0 +1.0 pA Current loz Maximum 3-STATE Vout= Vec or GND 6.0V +0.5 +5.0 +10 pA Output Leakage G= Vin loc Maximum Quiescent Vin= Voc or GND 6.0V 8.0 80 160 pA Supply Current lout =0 pA Note 4: For a power supply of 5V +10% the worst case output voltages (Voy, and Vo_) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case Vj, and Vj, occur at Veg = 5.5V and 4.5V respectively. (The Vj, value at 5.5V is 3.85V.) The worst case leakage cur- rent (lj. Ice, and Iz) occur for CMOS at the higher voltage and so the 6.0V values should be used. www.fairchildsemi.comMM74HC595 AC Electrical Characteristics Voc= BV, Ta= 28C, t= = 6 ns Symbol Parameter Conditions Typ Guaranteed Units Limit fax Maximum Operating 50 30 MHz Frequency of SCK tpHL tpLH Maximum Propagation C_=45 pF 12 20 ns Delay, SCK to Qy tpHL tpLH Maximum Propagation C_=45 pF 18 30 ns Delay, RCK to Qa thru Qy tpzy, tpzL Maximum Output Enable Rp= 1 kQ Time from G to Qa thru Qy C_=45 pF 17 28 ns tpyz, tpLz Maximum Output Disable RL= kQ 15 25 ns Time from G to Qa thru Qy C_=5 pF ts Minimum Setup Time 20 ns from SER to SCK ts Minimum Setup Time 20 ns from SCLR to SCK ts Minimum Setup Time 40 ns from SCK to RCK (Note 5) ty Minimum Hold Time 0 ns from SER to SCK tw Minimum Pulse Width 16 ns of SCK or RCK Note 5: This setup time ensures the register will see stable data from the shift-register outputs. The clocks may be connected together in which case the stor- age register state will be one clock pulse behind the shift register. AC Electrical Characteristics Voc= 2.0-6.0V, C_ = 50 pF, t, = t}= 6 ns (unless otherwise specified) Ta= 25C Ta =40 to 85C | T, = 55 to 125C Symbol Parameter Conditions Veco Units Typ Guaranteed Limits fax Maximum Operating C= 50 pF 2.0V 10 6 4.8 4.0 MHz Frequency 4.5V 45 30 24 20 MHz 6.0V 50 35 28 24 MHz teu tp_y | Maximum Propagation C= 50 pF 2.0V 58 210 265 315 ns Delay from SCK to Qy C,_= 150 pF 2.0V 83 294 367 441 ns C_=50 pF 4.5V 14 42 53 63 ns C_ = 150 pF 4.5V 17 58 74 88 ns C,_ = 50 pF 6.0V 10 36 45 54 ns C_ = 150 pF 6.0V 14 50 63 76 ns teu tp_y | Maximum Propagation C= 50 pF 2.0V 70 175 220 265 ns Delay from RCK to Qg thru Qy | C_ = 150 pF 2.0V 105 245 306 368 ns C_=50 pF 4.5V 21 35 44 53 ns C_ = 150 pF 4.5V 28 49 61 74 ns C,_ = 50 pF 6.0V 18 30 37 45 ns C_ = 150 pF 6.0V 26 42 53 63 ns teu tp_y | Maximum Propagation 2.0V 175 221 261 ns Delay from SCLR to Quy 4.5V 35 44 52 ns 6.0V 30 37 44 ns www.fairchildsemi.com 4AC Electrical Characteristics (continued) Ty = 25C T, =40 to 85C | T, =55 to 125C Symbol Parameter Conditions Veco Units Typ Guaranteed Limits tpzy) tpz_ | Maximum Output Enable Rp= 1 kQ from G to Qa thru Qy C_= 50 pF 2.0V 75 175 220 265 ns C_= 150 pF 2.0V 100 245 306 368 ns C_=50 pF 4.5V 15 35 44 53 ns C_= 150 pF 4.5V 20 49 61 74 ns C_= 50 pF 6.0V 13 30 37 45 ns C_ = 150 pF 6.0V 17 42 53 63 ns tpyz, tp_z | Maximum Output Disable RL= 1 kQ 2.0V 75 175 220 265 ns Time from G to Qa thru Qy C,=50 pF 4.5V 15 35 44 53 ns 6.0V 13 30 37 45 ns ts Minimum Setup Time 2.0V 100 125 150 ns from SER to SCK 4.5V 20 25 30 ns 6.0V 17 21 25 ns ta Minimum Removal Time 2.0V 50 63 75 ns from SCLR to SCK 4.5V 10 13 15 ns 6.0V 9 abl 13 ns ts Minimum Setup Time 2.0V 100 125 150 ns from SCK to RCK 4.5V 20 25 30 ns 6.0V 17 21 26 ns ty Minimum Hold Time 2.0V 5 5 5 ns SER to SCK 4.5V 5 5 5 ns 6.0V 5 5 5 ns tw Minimum Pulse Width 2.0V 30 80 100 120 ns of SCK or SCLR 4.5V 9 16 20 24 ns 6.0V 8 14 18 22 ns tr, tt Maximum Input Rise and 2.0V 1000 1000 1000 ns Fall Time, Clock 4.5V 500 500 500 ns 6.0V 400 400 400 ns true trty | Maximum Output 2.0V 25 60 75 90 ns Rise and Fall Time 4.5V 7 12 15 18 ns Qa-Qu 6.0V 6 10 13 15 ns true trty | Maximum Output 2.0V 75 95 110 ns Rise & Fall Time 4.5V 15 19 22 ns Qu 6.0V 13 16 19 ns Cpp Power Dissipation G=Voo 90 pF Capacitance, Outputs G=GND 150 pF Enabled (Note 6) Cin Maximum Input 5 10 10 10 pF Capacitance Cout Maximum Output 15 20 20 20 pF Capacitance Note 6: Cpp determines the no load dynamic power consumption, Pp = Cpp Vecet + lee Vee, and the no load dynamic current consumption, Is = Cpp Vec f+ Ico. www.fairchildsemi.com S6SOHPZNNMM74HC595 Timing Diagram a IT 1 a L__ RCK | | TT G 1 a | KX] O% Xxx] Oc CX] 9 xxx] Lo Op EET L__ a | KX] Oe xxx] L OH KX] w | NOTE: [X585<] Implies that the output is in 3- STATE mode. www.fairchildsemi.com 6Physical DimensiONS$ inches (millimeters) unless otherwise noted 0.150 0.157 | ee (3.810 3.988) 0.010 0.02D (0.2540.508) Be MAX TYP { _"* ALL | i __ x 45) [~ ft 0.008 0.010 0.016 0.050 (0.203 0.284) (0.406 1.270) TYP ALL LEADS 0.004 TYP ALL LEADS (0.102) ALL LEAD TIPS 0.386 0.994 (9.804 10.00) 16 15 614013 A 6 6 120617 12 f 0.228-0.244 (5.791 6.198) | 30 L UoU LEAO NO.1 j'\ 2 a4 IDENT 0.053 0.069 (1.346 1.753) Ty 0.010 max (0.254) 0.0040.010 (0.102 0.254) > \ _ Fe SS Sc SEATING t ae 0355) | 0.050 (1.270) TYP 4 PLANE 0.014-0.020 yp mr! Is*~ 19 356- 0.508) < TrP a co) MIBA (REV Hy 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 0.3977-0.4133 10.10-10.50 PHAH ABAD LEAD NO 1 IDENTIFICATION a! 0.2914-0.2992 FAMT.! 0.3940-0.4190 10.00- 10.65 FECEGEEE eal 0.0138-0.0200 o.350-0.508 'YP y 0:010-0.029 0.0926-0.1043 49 x 9.25-0.75 2357265 0.0040-0.0118 0.1-0.5 SEATING -_{ PLANE tL oor 0.0091-0.0125 O.23-0.32_ TYP ALL a } [ope] <o04 eke LEAD TIPS 0.0160-0.0500 ~O.40-1.27 TYP ALL LEADS B MAX we ALL LEADS M16B (REV F) 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M16B www.fairchildsemi.com S6SOHPZNNMM74HC595 Physical DimensiONS inches (millimeters) unless otherwise noted (Continued) 16 9 0.295-0.319 (7.5-8.1) 0.205-0.213 (5.2-5.4) 1 8 - 0.394-0.402 0.71 (10.0-10.2) (ay? (1.7-2.1) \ 0.067-0.083 AAA AAA 0-8 TYP 0.006 (0.15) \ SEATING | | (0.049 PLANE TYP -< 0.000-0.010 (1.25) (0-9.25) 0.016-0.031 0.014-0.020 | Toacoay YP TYP | [= (0.4-0.8) {0.35-0.50) 16-Lead Small Outline Package (SOP), EIAJ TYPE Il, 5.3mm Wide Package Number M16D 0.006-0.010 70.15-0.25) 'YP | TYP) | M16D (REV B) www.fairchildsemi.com 8Physical DimensiONS inches (millimeters) unless otherwise noted (Continued) (00000007 ~~ 4.16 TYP. DIMENSIONS METRIC ONLY | se (M00 | 16 * 9 0.42 TYP ld | LULL ER EO | LAND PATTERN RECOMMENDATION GAGE PLANE fee SLE soa |_| \\ seat ie _ VU on 8 [ea] 0.2 [cB] A] TYPICAL, SCALE: 40X PIN #1 IDENT. ALL LEAD TIPS SEE DETAIL A oO p& 90) . ao a si ETT Ff (ose a ve TYP | | Lu / boa ~ 0.09-0.20 vet 0.10 + 0.05 TYP H# 0.19 - 0.30 TYP MIC16 (REV C) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 9 www.fairchildsemi.com S6SOHPZNNMM74HC595 8-Bit Shift Registers with Output Latches Physical DimensiONS inches (millimeters) unless otherwise noted (Continued) 0.740 = 0,780 (18.80 - 19.81) | se fe) (15) ff4) 3) 2) fi) (rol 9) INDEX AREA 0.250 40.010 (6.350 0.254) PIN NO. 1 + PIN NO. 1 IDENT IDENT OPTION 01 OPTION 02 os 0.130 0.005 0.060 te ei 4 TYP 0.300 - 0.320 , __ Gsoze0.127) - [> rszay MP | [> oprionaL 7 (7.620- 8.128) oe 0.145 = 0.200 (3.683-5.080) } C 95 5 0.008 = 0.016 Oo oO . i! 0.020 4) 900 4 TYP (0.203 0.406) (0508) 0.280 0.125 = 0.150 0.030 0.015 (7.112) (3.175 = 3.810) : (0.762 40.381) MIN 0.014 = 0.023 0.100 0.010 +0.040 (0.356 - 0.584) 0.050 0 oe (2.540 0.254) (0.525 -9'015 N16E (REV F) TYP eee TYP +1.016 (1.270 0.254) (6.2557 555) TYP 16-Lead Plastic Dual--Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. Accritical component in any component of a life support which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea- body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support to perform when properly used in accordance with device or system, or to affect its safety or effectiveness. instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.