19-5646; Rev 0; 12/10 TION KIT EVALUA BLE IL AVA A HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface The MAX9265 gigabit multimedia serial link (GMSL) serializer features an LVDS system interface and high-bandwidth digital content protection (HDCP) encryption for content protection of DVD and Blu-rayTM video and audio data. The serializer pairs with any HDCP GMSL deserializer to form a digital serial link for the transmission of control data and HDCP-encrypted video and audio data. GMSL is an HDCP technology approved by Digital Content Protection (DCP), LLC. The 3-channel mode serializes three lanes of LVDS data (21 bits), UART control signals, and three audio inputs. The 4-channel mode serializes four lanes of LVDS data (28 bits), UART control signals, three audio inputs, and auxiliary control inputs. The three audio inputs are for I2S audio, supporting a sampling frequency from 8kHz to 192kHz and a sample depth of 4 to 32 bits. The embedded control channel forms a full-duplex differential 9.6kbps to 1Mbps UART link between the serializer and deserializer. An electronic control unit (ECU), or microcontroller (FC), can be located on the serializer side of the link (typical for video display), on the deserializer side of the link (typical for image sensing), or on both sides. The control channel enables ECU/FC control of peripherals on the remote side, such as backlight control, touch screen, and perform HDCP-related operations. The serial link signaling is AC-coupled CML with 8b/10b coding. For driving longer cables, the serializer has programmable driver pre/deemphasis, and for reduced EMI, has programmable spread spectrum on the serial output. The serial output meets ISO 10605 and IEC 61000-4-2 ESD standards. The serializer operates with a 1.8V core supply, a 1.8V to 3.3V I/O supply, and a 3.3V LVDS supply. This device is available in a 48-pin TQFP package with an exposed pad and is specified over the -40NC to +105NC automotive temperature range. Applications Features S Pairs with Any GMSL Deserializer S HDCP Encryption Enable/Disable Programmable with the Control Channel S Control Channel Handles All HDCP Protocol Transactions--Separate Control Bus Not Required S HDCP Keys Preprogrammed in Secure Nonvolatile Memory S 2.5Gbps Payload Data Rate (3.125Gbps with Overhead) S AC-Coupled Serial Link with 8b/10b Line Coding S 8.33MHz to 104MHz (3-Channel LVDS) or 6.25MHz to 78MHz (4-Channel LVDS) Pixel Clock S 4-Bit to 32-Bit Sample Depth, 8kHz to 192kHz I2S Audio Channel Supports High-Definition Audio S Embedded Half-/Full-Duplex Bidirectional Control Channel Base Mode: 9.6kbps to 1Mbps Bypass Mode: 9.6kbps to 1Mbps S Two 3-Level Inputs Support 9 Slave Addresses S Interrupt Supports Touch-Screen Displays S Remote-End I2C Master for Peripherals S Programmable Pre/Deemphasis S Programmable Spread Spectrum on the Serial Link and Deserializer Outputs Reduce EMI S Auto Data-Rate Detection Allows "On-The-Fly" Data-Rate Change S Bypassable PLL on LVDS Clock Input for Jitter Attenuation S Built-In PRBS Generator for BER Testing of the Serial Link S Fault Detection of Serial Link Shorted Together, to Ground, to Battery, or Open S ISO 10605 and IEC 61000-4-2 ESD Tolerance Ordering Information High-Resolution Automotive Navigation Rear-Seat Infotainment Megapixel Camera Systems Blu-ray is a trademark of Blu-ray Disc Association. PART TEMP RANGE MAX9265GCM/V+ MAX9265GCM/V+T -40NC to +105NC -40NC to +105NC PIN-PACKAGE 48 TQFP-EP* 48 TQFP-EP* /V denotes an automotive qualified part. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. T = Tape and reel. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. MAX9265 General Description MAX9265 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface ABSOLUTE MAXIMUM RATINGS AVDD to AGND.....................................................-0.5V to +1.9V DVDD to GND.......................................................-0.5V to +1.9V IOVDD to GND......................................................-0.5V to +3.9V LVDSVDD to AGND...............................................-0.5V to +3.9V Any Ground to Any Ground..................................-0.5V to +0.5V RXIN__, RXCLKIN_ to AGND................................-0.5V to +3.9V OUT+, OUT- to AGND..........................................-0.5V to +1.9V LMN_ to AGND (15mA current limit).....................-0.5V to +3.9V All Other Pins to GND.........................-0.5V to (VIOVDD + 0.5V) Continuous Power Dissipation (TA = +70NC ) 48-Lead TQFP (derate 36.2mW/NC above +70NC)...2898.6mW Junction-to-Case Thermal Resistance (BJC) (Note 1) 48-Lead TQFP..................................................................2NC/W Junction-to-Ambient Thermal Resistance (BJA) (Note 1) 48-Lead TQFP.............................................................27.6NC/W Operating Temperature Range......................... -40NC to +105NC Junction Temperature......................................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VAVDD = VDVDD = 1.7V to 1.9V, VLVDSVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V |VID/2|. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SINGLE-ENDED INPUTS (SD/CNTL0, SCK, WS, CNTL1, CNTL2, SSEN, DRS, BWS, PWDN , CDS, MS, AUTOS) High-Level Input Voltage VIH1 PWDN, SSEN, BWS, DRS, MS, CDS, AUTOS 0.65 x VIOVDD SD/CNTL0, SCK, WS, CNTL_ 0.7 x VIOVDD Low-Level Input Voltage VIL1 Input Current IIN1 VIN = 0 to VIOVDD Input Clamp Voltage VCL ICL = -18mA High-Level Output Voltage VOH1 IOUT = -2mA Low-Level Output Voltage VOL1 IOUT = 2mA V -10 0.35 x VIOVDD V +10 FA -1.5 V SINGLE-ENDED OUTPUT (INT) Output Short-Circuit Current IOS VO = VGND VIOVDD - 0.2 V 0.2 VIOVDD = 3.0V to 3.6V 16 35 64 VIOVDD = 1.7V to 1.9V 3 12 21 V mA I2C/UART, I/O, AND OPEN-DRAIN OUTPUTS (RX/SDA, TX/SCL, LFLT) High-Level Input Voltage VIH2 Low-Level Input Voltage VIL2 Input Current IIN2 Low-Level Output Voltage VOL2 0.7 x VIOVDD VIN = 0 to VIOVDD (Note 2) IOUT = 3mA -110 V 0.3 x VIOVDD V +5 FA VIOVDD = 1.7V to 1.9V 0.4 VIOVDD = 3.0V to 3.6V 0.3 2 _______________________________________________________________________________________ V HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface (VAVDD = VDVDD = 1.7V to 1.9V, VLVDSVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V |VID/2|. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX Preemphasis off (Figure 1) 300 400 500 3.3dB preemphasis setting (Figure 2) 350 610 3.3dB deemphasis setting (Figure 2) 240 425 UNITS DIFFERENTIAL OUTPUTS (OUT+, OUT-) Differential Output Voltage Change in VOD Between Complementary Output States Output Offset Voltage (VOUT+ + VOUT-)/2 = VOS Change in VOS Between Complementary Output States Output Short-Circuit Current VOD DVOD VOS Preemphasis off 1.1 1.4 DVOS IOS Magnitude of Differential Output Short-Circuit Current IOSD Output Termination Resistance (Internal) RO VOUT+ or VOUT- = 0V mV 15 mV 1.56 V 15 mV -60 mA VOUT+ or VOUT- = 1.9V 25 VOD = 0V 25 mA 63 I 27 mV From OUT+, OUT- to VAVDD 45 54 REVERSE CONTROL-CHANNEL RECEIVER (OUT+, OUT-) High Switching Threshold VCHR Low Switching Threshold VCLR -27 mV LINE-FAULT-DETECTION INPUTS (LMN0, LMN1) Short-to-GND Threshold VTG Figure 3 Normal Thresholds VTN Figure 3 0.3 V 0.57 1.07 V V V VTO Figure 3 1.45 VIO + 60mV Open Input Voltage VIO Figure 3 1.47 1.75 Short-to-Battery Threshold VTE Figure 3 2.47 V 0.7 x VIOVDD V Open Thresholds THREE-LEVEL LOGIC INPUTS (ADD0, ADD1) High-Level Input Voltage VIH Low-Level Input Voltage VIL Mid-Level Input Current IINM Input Current IIN Input Clamp Voltage VCL Unconnected or connected to a driver with output in high-impedance state (Note 3) ICL = -18mA 0.3 x VIOVDD V -10 +10 FA -150 +150 FA -1.5 V _______________________________________________________________________________________ 3 MAX9265 DC ELECTRICAL CHARACTERISTICS (continued) MAX9265 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface DC ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VDVDD = 1.7V to 1.9V, VLVDSVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V |VID/2|. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 50 mV LVDS INPUTS (RXIN_+/-, RXCLKIN_) Differential Input High Threshold VTH Differential Input Low Threshold VTL -50 RTERM 85 Input Differential Termination Resistance Input Current Power-Off Input Current IIN+, IINIIN0+, IIN0- mV 110 135 I PWDN = high or low, IN+ and IN- are shorted -25 +25 FA VAVDD = VDVDD = VIOVDD = 0V -40 +40 FA POWER SUPPLY fRXCLKIN_ = 16.6MHz 137 178 HDCP enabled, fRXCLKIN_ = 33.3MHz BWS = low fRXCLKIN_ = 66.6MHz fRXCLKIN_ = 104MHz 146 186 166 206 Worst-Case Supply Current (Figure 4) IWCS 195 242 Sleep Mode Supply Current ICCS LVDS inputs are not driven 95 225 FA Power-Down Supply Current ICCZ PWDN = GND, LVDS inputs are not driven 60 180 FA Human Body Model, RD = 1.5kI, CS = 100pF (Note 4) Q8 mA ESD PROTECTION OUT+, OUT- VESD IEC 61000-4-2, RD = 330I, CS = 150pF (Note 5) Contact discharge Q10 Air discharge Q12 ISO 10605, RD = 2kI, CS = 330pF (Note 5) Contact discharge Q10 Air discharge Q20 kV RXIN_+, RXIN_-, RXCLKIN+, RXCLKIN- VESD Human Body Model, RD = 1.5kI, CS = 100pF (Note 4) Q8 kV All Other Pins VESD Human Body Model, RD = 1.5kI, CS = 100pF (Note 4) Q3.5 kV 4 _______________________________________________________________________________________ HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface (VDVDD = VAVDD = 1.7V to 1.9V, VLVDSVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Differential input voltage |VID| = 0.15V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|. Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX BWS = GND, VDRS = VIOVDD BWS = GND, DRS = GND 8.33 16.66 104 VBWS = VIOVDD, VDRS = VIOVDD 6.25 12.5 VBWS = VIOVDD, DRS = GND 12.5 78 UNITS CLOCK INPUTS (RXCLKIN_) Clock Frequency fRXCLKIN_ I2C/UART PORT TIMING I2C/UART Bit Rate 16.66 MHz 9.6 1000 kbps 20 150 ns 150 ns Output Rise Time tR 30% to 70%, CL = 10pF to 100pF, 1kI pullup to VIOVDD Output Fall Time tF 70% to 30%, CL = 10pF to 100pF, 1kI pullup to VIOVDD 20 Input Setup Time tSET I2C only (Figure 5, Note 6) 100 ns Input Hold Time tHOLD I2C only (Figure 5, Note 6) 0 ns tR, tF 20% to 80%, VOD R 400mV, RL = 100I, serial bit rate = 3.125Gbps (Note 6) SWITCHING CHARACTERISTICS Differential Output Rise/Fall Time Total Serial Output Jitter tTSOJ1 3.125Gbps PRBS signal, measured at VOD = 0V differential, preemphasis disabled (Figure 6) Deterministic Serial Output Jitter tDSOJ2 3.125Gbps PRBS signal 90 150 0.25 ps UI 0.15 UI CNTL_ Input Setup Time tSET CNTL_ (Figure 7) (Note 6) 3 ns CNTL_ Input Hold Time tHOLD CNTL_ (Figure 7) (Note 6) 1.5 ns RXIN__ Skew Margin tRSKM Figure 8 (Note 6) 0.3 UI Serializer Delay (Notes 6, 7) Spread spectrum enabled 2950 Spread spectrum disabled 550 tSD (Figure 9) Link Start Time tLOCK (Figure 10) 3.5 ms Power-Up Time tPU (Figure 11) 6 ms WS Frequency fWS See Table 4 8 192 kHz Sample Word Length nWS See Table 4 4 32 Bits SCK Frequency fSCK fSCK = fWS x nWS x 2 (8 x 4) x 2 (192 x 32) x 2 kHz I2S Bits INPUT TIMING _______________________________________________________________________________________ 5 MAX9265 AC ELECTRICAL CHARACTERISTICS MAX9265 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface AC ELECTRICAL CHARACTERISTICS (continued) (VDVDD = VAVDD = 1.7V to 1.9V, VLVDSVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Differential input voltage |VID| = 0.15V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|. Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCK Clock High Time tHC VSCK R VIH, tSCK = 1/fSCK (Note 6) 0.35 tSCK SCK Clock Low Time tLC VSCK P VIL, tSCK = 1/fSCK (Note 6) 0.35 tSCK ns SD, WS Setup Time tSET (Figure 12, Note 6) 2 ns SD, WS Hold Time tHOLD (Figure 12, Note 6) 2 ns ns Note 2: Minimum IIN due to voltage drop across the internal pullup resistor. Note 3: To provide a mid level, leave the input unconnected, or, if driven, put driver in high impedance. High-impedance leakage current must be less than Q10FA. Note 4: Tested terminal to all grounds. Note 5: Tested terminal to AGND. Note 6: Guaranteed by design and not production tested. Note 7: Measured in CML bit times. Bit time = 1/(30 x fRXCLKIN) for BWS = GND. Bit time = 1/(40 x fRXCLKIN) for VBWS = VIOVDD. 6 _______________________________________________________________________________________ HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface SUPPLY CURRENT vs. RXCLKIN_ FREQUENCY (32-BIT MODE) 170 160 PREEMPHASIS = 0x01 TO 0x04 150 190 PREEMPHASIS = 0x00 160 PREEMPHASIS = 0x01 TO 0x04 150 PREEMPHASIS = 0x00 5 25 45 65 85 5 105 20 35 50 65 fRXCLKIN = 33MHz -10 -20 -40 -50 -60 -70 2% SPREAD 4% SPREAD -90 80 0.5% SPREAD 0% SPREAD -30 -80 130 130 30 31 32 33 34 35 RXCLKIN FREQUENCY (MHz) RXCLKIN FREQUENCY (MHz) OUTPUT POWER SPECTRUM vs. RXCLKIN_ FREQUENCY (VARIOUS SPREAD) MAXIMUM RXCLKIN_ FREQUENCY vs. STP CABLE LENGTH (BER < 10-9) MAXIMUM RXCLKIN_ FREQUENCY vs. ADDITIONAL DIFFERENTIAL CL (BER < 10-9) -30 -40 -50 -60 -70 -80 2% SPREAD -90 61 63 65 4% SPREAD 67 69 RXCLKIN FREQUENCY (MHz) 80 OPTIMUM PE/EQ SETTINGS 60 NO PE, 10.7dB EQUALIZATION 40 NO PE, 5.2dB EQUALIZATION 20 BER CAN BE AS LOW AS 10-12 FOR CABLE LENGTHS LESS THAN 10m 0 71 0 5 10 15 STP CABLE LENGTH (m) 20 36 MAX9265 toc06 100 120 MAXIMUM RXCLKIN_ FREQUENCY (MHz) 0.5% SPREAD 0% SPREAD MAX9265 toc05 -10 120 MAXIMUM RXCLKIN_ FREQUENCY (MHz) fRXCLKIN = 66MHz MAX9265 toc04 RXCLKIN FREQUENCY (MHz) 0 OUTPUT POWER SPECTRUM (dBm) 170 140 140 -20 PREEMPHASIS = 0x0B TO 0x0F 180 0 MAX9265 toc03 PREEMPHASIS = 0x0B TO 0x0F SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 190 PRBS ON, HDCP ON OUTPUT POWER SPECTRUM (dBm) PRBS ON, HDCP ON 180 200 MAX9265 toc01 200 OUTPUT POWER SPECTRUM vs. RXCLKIN_ FREQUENCY (VARIOUS SPREAD) MAX9265 toc02 SUPPLY CURRENT vs. RXCLKIN_ FREQUENCY (24-BIT MODE) 10m STP CABLE 100 OPTIMUM PE/EQ SETTINGS 80 60 NO PE, 10.7dB EQUALIZATION 40 NO PE, 5.2dB EQUALIZATION 20 BER CAN BE AS LOW AS 10-12 FOR CL < 4pF FOR OPTIMUM PE/EQ SETTINGS 0 0 2 4 6 8 10 ADDITIONAL DIFFERENTIAL LOAD CAPACITANCE (pF) _______________________________________________________________________________________ 7 MAX9265 Typical Operating Characteristics (VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25C, unless otherwise noted.) HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface MAX9265 Pin Configuration DRS INT LFLT LMN0 AVDD OUT+ OUT- AGND LMN1 SSEN TX/SCL RX/SDA TOP VIEW 36 35 34 33 32 31 30 29 28 27 26 25 IOVDD 37 24 IOVDD GND 38 23 GND DVDD 39 22 DVDD ADD0 40 21 AGND BWS 41 20 CNTL2 PWDN 42 19 CNTL1 CDS 43 18 WS MS 44 17 SCK AUTOS 45 16 SD/CNTL0 ADD1 46 15 AVDD 14 LVDSVDD 13 AGND 6 7 8 9 10 11 12 RXIN2+ RXCLKIN+ RXIN3- RXIN3+ 5 RXCLKIN- RXIN1- 4 RXIN2- 3 AGND 2 LVDSVDD 1 RXIN1+ + RXIN0- 47 48 *EP RXIN0+ AVDD AGND MAX9265 TQFP *CONNECT EXPOSED PAD TO AGND Pin Description PIN NAME FUNCTION 1 RXIN0- Differential LVDS Data Input 0- 2 RXIN0+ Differential LVDS Data Input 0+ 3 RXIN1- Differential LVDS Data Input 1- 4 RXIN1+ Differential LVDS Data Input 1+ 5, 14 LVDSVDD 6, 13, 21, 29, 48 AGND Analog Ground 7 RXIN2- Differential LVDS Data Input 2- 8 RXIN2+ Differential LVDS Data Input 2+ 9, 10 RXCLKIN-, RXCLKIN+ LVDS Input for the LVDS Clock 11 RXIN3- 3.3V LVDS Power Supply. Bypass LVDSVDD to AGND with 0.1FF and 0.001FF capacitors as close as possible to the device with the smaller value capacitor closest to LVDSVDD. Differential LVDS Data Input 3-. RXIN3- is not available in 3-channel mode. To use RXIN3-, drive BWS high (4-channel mode) (see Table 3). 8 _______________________________________________________________________________________ HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface PIN NAME FUNCTION 12 RXIN3+ Differential LVDS Data Input 3+. RXIN3+ is not available in 3-channel mode. To use RXIN3+, drive BWS high (4-channel mode) (see Table 3). 15, 32, 47 AVDD 1.8V Analog Power Supply. Bypass AVDD to AGND with 0.1FF and 0.001FF capacitors as close as possible to the device with the smaller capacitor closest to AVDD. 16 SD/CNTL0 I2S Serial-Data Input with Internal Pulldown to GND. Disable I2S to use SD/CNTL0 as an additional control/data input latched every RXCLKIN_ cycle (Figure 7). Encrypted when HDCP is enabled. 17 SCK I2S Serial-Clock Input with Internal Pulldown to GND 18 WS I2S Word-Select Input with Internal Pulldown to GND 19 CNTL1 Control Input 1 with Internal Pulldown to GND. Data is latched every RXCLKIN cycle (Figure 7). CNTL1 is not available in 3-channel mode. To use CNTL1, drive BWS high (4-channel mode). CNTL1 or RES (RES from VESA Standard Panel Specification) is mapped to DIN27 (see the Reserved Bit (RES) section). CNTL1 is not encrypted when HDCP is enabled (see Table 3). 20 CNTL2 Control Input 2 with Internal Pulldown to GND. Data is latched every RXCLKIN cycle (Figure 7). CNTL2 is not available in 3-channel mode. To use CNTL2, drive BWS high (4-channel mode). CNTL2 is mapped to DIN28. CNTL2 is not encrypted when HDCP is enabled (see Table 3). 22, 39 DVDD 1.8V Digital Power Supply. Bypass DVDD to GND with 0.1FF and 0.001FF capacitors as close as possible to the device with the smaller value capacitor closest to DVDD. 23, 38 GND Digital and I/O Ground 24, 37 IOVDD I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to GND with 0.1FF and 0.001FF capacitors as close as possible to the device with the smallest value capacitor closest to IOVDD. 25 RX/SDA Receive/Serial Data. UART receive or I2C serial-data input/output with internal 30kI pullup to IOVDD. In UART mode, RX/SDA is the Rx input of the serializer's UART. In the I2C mode, RX/SDA is the SDA input/output of the MAX9265's I2C master. RX/SDA has an open-drain driver and requires a pullup resistor. 26 TX/SCL Transmit/Serial Clock. UART transmit or I2C serial-clock output with internal 30kI pullup to IOVDD. In UART mode, TX/SCL is the Tx output of the MAX9265's UART. In the I2C mode, TX/SCL is the SCL output of the serializer's I2C master. TX/SCL has an open-drain driver and requires a pullup resistor. 27 SSEN Spread-Spectrum Enable. Serial link spread-spectrum enable input requires external pulldown or pullup resistor. The state of SSEN latches upon power-up or when resuming from power-down mode (PWDN = low). Set SSEN = high for Q0.5% spread spectrum on the serial link. Set SSEN = low to use the serial link without spread spectrum. 28 LMN1 Line-Fault Monitor Input 1 (See Figure 3 for Details) 30, 31 OUT-, OUT+ Differential CML Output -/+. Differential outputs of the serial link. 33 LMN0 Line-Fault Monitor Input 0 (See Figure 3 for Details) 34 LFLT Line Fault. Active-low open-drain line-fault output. LFLT has a 60kI internal pullup resistor. LFLT = low indicates a line fault. LFLT is high impedance when PWDN = low. 35 INT Interrupt Output. INT indicates remote-side requests. INT = low upon power-up and when PWDN = low. A transition on the INT input of the GMSL deserializer toggles the MAX9265's INT output. _______________________________________________________________________________________ 9 MAX9265 Pin Description (continued) MAX9265 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface Pin Description (continued) PIN NAME FUNCTION Data-Rate Select. Data-rate range-selection input requires external pulldown or pullup resistor. The state of DRS latches upon power-up or when resuming from power-down mode (PWDN = low). Set DRS = high for RXCLKIN frequencies of 8.33MHz to 16.66MHz (3-channel mode) or 6.25MHz to 12.5MHz (4-channel mode). Set DRS = low for RXCLKIN frequencies of 16.66MHz to 104MHz (3-channel mode) or 12.5MHz to 78MHz (4-channel mode). 36 DRS 40 ADD0 Address Selection Input 0. Three-level input to select the MAX9265's device address (see Table 2). The state of ADD0 latches upon power-up or when resuming from power-down mode (PWDN = low). 41 BWS Bus-Width Select Input. BWS requires external pulldown or pullup resistor. Set BWS = low for 3-channel mode. Set BWS = high for 4-channel mode. 42 PWDN 43 CDS 44 MS 45 AUTOS Active-Low Autostart Setting. AUTOS requires external pulldown or pullup resistor. Set AUTOS = high to power up the device with no link active. Set AUTOS = low to have the serializer power up the serial link with autorange detection (see Tables 9 and 10). 46 ADD1 Address Selection Input 1. Three-level input to select the serializer's device address (see Table 2). The state of ADD1 latches upon power-up or when resuming from power-down mode (PWDN = low). -- EP Exposed Pad. EP internally is connected to AGND. MUST connect EP to the AGND plane for proper thermal and electrical performance. Active-Low Power-Down Input. PWDN requires external pulldown or pullup resistor. Control Direction Selection. Control link direction selection input requires external pulldown or pullup resistor. Set CDS = low for FC use on the MAX9265 side of the serial link. Set CDS = high for FC use on the GMSL deserializer side of the serial link. Mode Select. Control link mode selection input requires external pulldown or pullup resistor. Set MS = low to select base mode. Set MS = high to select bypass mode. 10 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface LFLT FILTER PLL RXCLKIN+/- SSPLL 7x PLL CLKDIV RGB RGB[17:0] VS LVDS TO PARALLEL VS VIDEO DE RES/CNTL1 (4-CH) RXIN3+/(4-CH) HDCP KEYS CNTL1/RES (4-CH) FIFO CML Tx SCRAMBLE/ PARITY/ 8b/10b ENCODE HDCP CONTROL Rx CNTL2 (4-CH) ACB CNTL1 (4-CH) OUT- DE RGB[23:18] (4-CH) RXIN2+/- OUT+ PARALLEL TO SERIAL HS HS LMN1 HDCP ENCRYPT RXIN0+/- RXIN1+/- LMN0 LINE FAULT DETECT AUDIO REVERSE CONTROL CHANNEL HDCP ENCRYPT FCC CNTL2 (4-CH) MAX9265 UART/I2C SD/ WS CNTLO TX/SCL SCK RX/SDA ADD0 ADD1 RL/2 OUT+ VOD VOS OUT- RL/2 GND ((OUT+) + (OUT-))/2 OUTVOS(-) VOS(+) VOS(-) OUT+ DVOS = |VOS(+) - VOS(-)| VOD(+) VOD = 0V VOD(-) DVOD = |VOD(+) - VOD(-)| VOD(-) (OUT+) - (OUT-) Figure 1. Serial-Output Parameters ______________________________________________________________________________________ 11 MAX9265 Functional Diagram MAX9265 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface OUT+ VOD(P) VOS VOD(D) OUT- SERIAL-BIT TIME Figure 2. Output Waveforms at OUT+, OUT- 1.7V TO 1.9V MAX9265 45kI* 45kI* LMN0 LMN1 5kI* OUTPUT LOGIC (OUT+) 5kI* TWISTED PAIR OUT+ OUT- 50kI* CONNECTORS LFLT REFERENCE VOLTAGE GENERATOR OUTPUT LOGIC (OUT-) *Q1% TOLERANCE Figure 3. Line-Fault Detector Circuit 12 50kI* HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface MAX9265 RXCLKIN+ RXCLKINRXIN0+ TO RXIN3+ RXIN0- TO RXIN3- CNTL_ Figure 4. Worst-Case Pattern Input tF tR TX/ SCL tHOLD tSET RX/ SDA P S S P Figure 5. I2C Timing Parameters RXCLKINRXCLKIN+ 800mVP-P RXIN_+/RXIN_tSET CNTL_ tHOLD VIHMIN VILMAX t TSOJ1 2 t TSOJ1 2 Figure 6. Differential Output Template Figure 7. Input Setup and Hold Times ______________________________________________________________________________________ 13 MAX9265 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface IDEAL SERIAL-BIT TIME tRSKM tRSKM IDEAL MIN MAX INTERNAL STROBE Figure 8. LVDS Receiver Input Skew Margin EXPANDED TIME SCALE N-1 N N+1 N+2 N+3 RXIN_+/RXIN_- RXCLKIN+ RXCLKINN-1 N OUT+/OUTFIRST BIT tSD Figure 9. Serializer Delay RXCLKINRXCLKIN+ tLOCK 350s SERIAL LINK INACTIVE REVERSE CONTROL CHANNEL ENABLED SERIAL LINK ACTIVE CHANNEL DISABLED REVERSE CONTROL CHANNEL ENABLED PWDN MUST BE HIGH Figure 10. Link Startup Time 14 LAST BIT HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface MAX9265 RXCLKIN+ RXCLKIN- PWDN VIH1 tPU POWERED UP, SERIAL LINK INACTIVE POWERED DOWN POWERED UP, SERIAL LINK ACTIVE 350s REVERSE CONTROL CHANNEL DISABLED REVERSE CONTROL CHANNEL ENABLED REVERSE CONTROL CHANNEL DISABLED REVERSE CONTROL CHANNEL ENABLED Figure 11. Power-Up Delay WS tHOLD tSCK tSET tLC SCK tHOLD tSET tHC SD/CNTL0 Figure 12. Input I2S Timing Parameters ______________________________________________________________________________________ 15 MAX9265 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface Detailed Description The MAX9265 GMSL serializer with LVDS interface utilizes Maxim's GMSL technology and HDCP. When HDCP is enabled, the serializer encrypts video and audio data on the serial link. When HDCP is disabled, the serializer is backward compatible with the MAX9249 LVDS input serializer. The serializer has a maximum serial payload data rate of 2.5Gbps for 15m or more of shielded twisted-pair (STP) cable. The serializer operates up to a maximum input clock of 104MHz for 3-channel mode, or 78MHz for 4-channel mode, respectively. This serial link supports a wide range of display panels from QVGA (320 x 240) up to WXGA (1280 x 800) and higher with 24-bit color. The 3-channel mode handles three lanes of LVDS data (21 bits), UART control signals, and three audio signals. The 4-channel mode handles four lanes of LVDS data (28 bits), UART control signals, three audio signals, and auxiliary parallel inputs. The three audio inputs form a standard I2S interface, supporting sample rates from 8kHz to 192kHz and audio word lengths of 4 to 32 bits. The embedded control channel forms a full-duplex, differential 9.6kbps to 1Mbps UART link between the serializer and deserializer for HDCP-related control operations. In addition, the control channel enables electronic control unit (ECU) or microcontroller (FC) control of peripherals in the remote side, such as backlight control, gray-scale Gamma correction, camera module, and touch screen. An ECU/FC can be located on the serializer side of the link (typical for video display), on the GMSL deserializer side of the link (typical for image sensing), or on both sides. Base-mode communication with peripherals uses either I2C or the GMSL UART for- mat. A bypass mode enables full-duplex communication using a user-defined UART format. The serializer pre/deemphasis, along with the GMSL deserializer channel equalizer, extends the link length and enhances the link reliability. Spread spectrum is available to reduce EMI on the serial output. The CML and LVDS connections comply with ISO 10605 and IEC 61000-4-2 ESD protection standards. Register Mapping The FC configures various operating conditions of the serializer and the GMSL deserializer through internal registers. Table 1 lists the default register values for the serializer. The device addresses are stored in registers 0x00 and 0x01 of both the serializer and the GMSL deserializer. Write to registers 0x00 and 0x01 in both devices to change the device address of the serializer or the GMSL deserializer. HDCP Bitmapping and Bus-Width Selection The LVDS input has two selectable modes, 3-channel mode and 4-channel mode. In 3-channel mode, RXIN3_ is not used. For both modes, the SD/CNTL0, SCK, and WS pins are for I2S audio. The serializer uses RXCLKIN rates from 8.33MHz to 104MHz for 3-channel mode and 6.25MHz to 78MHz for 4-channel mode. Table 3 lists the bit mapping for the LVDS input. The serializer has HDCP encryption on 18 RGB input bits and the I2S input. Four-channel mode has additional HDCP encryption on the additional RGB bits. The control signals (CNTL_) do not have HDCP encryption. SD/CNTL0, when used as an additional control input (AUDIOEN = 0), also does not have HDCP encryption. 16 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface REGISTER ADDRESS (hex) POWER-UP DEFAULT (hex) 0x00 0x40, 0x48, 0x48, 0x80, 0x84, 0x88, 0xC0, 0xC4, 0xC8 SERID = XX00XX0, serializer device address is determined by ADD0 and ADD1 (Table 2) CFGBLOCK = 0, registers 0x00 to 0x1F are read/write 0x01 0x50, 0x58, 0x58, 0x90, 0x94, 0x98, 0xD0, 0xD4, 0xD8 DESID = XX00XX0, deserializer device address is determined by ADD0 and ADD1 (Table 2) RESERVED = 0 0x02 0x1F, 0x3F SS = 000 (SSEN = low), SS = 001 (SSEN = high), spread-spectrum settings depend on SSEN pin state at power-up AUDIOEN = 1, I2S channel enabled PRNG = 11, automatically detect the pixel clock range SRNG = 11, automatically detect serial-data rate 0x03 0x00 0x04 0x03, 0x13, 0x83, or 0x93 POWER-UP DEFAULT SETTINGS (MSB FIRST) AUTOFM = 00, calibrate spread-modulation rate only once after locking SDIV = 000000, autocalibrate the sawtooth divider SEREN = 0 (AUTOS = high), SEREN = 1 (AUTOS = low), serial link enable default depends on AUTOS pin state at power-up CLINKEN = 0, configuration link disabled PRBSEN = 0, PRBS test disabled SLEEP = 0 or 1, sleep mode state depends on CDS and AUTOS pin state at power-up (see the Link Startup Procedure section) INTTYPE = 00, base mode uses I2C REVCCEN = 1, reverse control channel active (receiving) FWDCCEN = 1, forward control channel active (sending) 0x05 0x70 I2CMETHOD = 0, I2C packets include register address DISFPLL = 1, filter PLL disabled CMLLVL = 11, 400mV CML signal level PREEMP = 0000, preemphasis disabled 0x06 0x40 RESERVED = 01000000 0x07 0x22 RESERVED = 00100010 0x08 0x0A (read only) 0x0C 0x70 RESERVED = 01110000 0x0D 0x0F SETINT = 0, interrupt output set to low INVVSYNC = 0, serializer does not invert VSYNC INVHSYNC = 0, serializer does not invert HSYNC DISRES = 0, RES mapped to DIN27 SKEWADJ = 1111, No X7PLL clock skew adjust 0x1E 0x07 (read only) RESERVED = 0000 LFNEG = 10, no faults detected LFPOS = 10, no faults detected ID = 00000111, device ID is 0x07 ______________________________________________________________________________________ 17 MAX9265 Table 1. Power-Up Default Register Map (see Table 17 and Table 18) MAX9265 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface Table 1. Power-Up Default Register Map (see Table 17 and Table 18) (continued) REGISTER ADDRESS (hex) POWER-UP DEFAULT (hex) 0x1F 0x1X (read only) 0x80 to 0x84 0x0000000000 0x85 to 0x86 0x0000 0x87 0x00 0x88 to 0x8F 0x0000000000000000 (read only) 0x90 to 0x94 0xXXXXXXXXXX (read only) 0x95 0x00 POWER-UP DEFAULT SETTINGS (MSB FIRST) RESERVED = 000 CAPS = 1, serializer is HDCP capable REVISION = XXXX, revision number BKSV = 0x0000000000, HDCP receiver KSV is 0x0000000000 RI = 0x0000, RI of the transmitter is 0x0000 PJ = 0x00, PJ of the transmitter is 0x00 AN = 0000000000000000, session random number (read only) AKSV = 0xXXXXXXXXXXXXXXXX, HDCP transmitter KSV is 0xXXXXXXXXXX (read only) PD_HDCP = 0, HDCP circuits powered up EN_INT_COMP = 0, internal link verification disabled FORCE_AUDIO = 0, normal I2S audio operation FORCE_VIDEO = 0, normal video link operation RESET_HDCP = 0, normal HDCP operation START_AUTHENTICATION = 0, HDCP authentication not started VSYNC_DET = 0, VSYNC rising edge not detected ENCRYPTION_ENABLE = 0, HDCP encryption disabled RESERVED = 0000 V_MATCHED = 0, SHA-1 hash value not matched PJ_MATCHED = 0, enhanced link verification response not matched R0_RI_MATCHED = 0, link verification response not matched BKSV_INVALID = 0, invalid receiver KSV 0x96 0x00 (read only) 0x97 0x00 0x98 to 0x9C 0x0000000000 0x9D to 0x9F 0x000000 0xA0 to 0xA3 0x00000000 H0 part of SHA-1 hash value is 0x00000000 0xA4 to 0xA7 0x00000000 H1 part of SHA-1 hash value is 0x00000000 RESERVED = 0000000 REPEATER = 0, HDCP receiver is not a repeater ASEED = 0x0000000000, optional RNG seed value is 0x0000000000 DFORCE = 0x000000, video data forced to 0x000000 when FORCE_VIDEO = 1 0xA8 to 0xAB 0x00000000 H2 part of SHA-1 hash value is 0x00000000 0xAC to 0xAF 0x00000000 H3 part of SHA-1 hash value is 0x00000000 0xB0 to 0xB3 0x00000000 H4 part of SHA-1 hash value is 0x00000000 0xB4 0x00 Reserved = 0000 MAX_CASCADE_EXCEEDED = 0, less than 7 cascaded HDCP devices attached DEPTH = 000, device cascade depth is zero 0xB5 0x00 MAX_DEVS_EXCEEDED = 0, less than 127 HDCP devices attached DEVICE_COUNT = 0000000, zero attached devices GPMEM = 00000000, 0x00 stored in general-purpose memory 0xB6 0x00 0xB7 to 0xB9 0x000000 0xBA to 0xFF All zero Reserved = 0x000000 KSV_LIST = all zero, no KSVs stored X = Don't care. 18 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface DEVICE ADDRESS (bin) ADD0 D7 D6 D5 D4 D3 D2 D1 D0 SERIALIZER DEVICE ADDRESS (hex) Low Low 1 0 0 X* 0 0 0 R/W 80 90 Low High 1 0 0 X* 0 1 0 R/W 84 94 Low Open 1 0 0 X* 1 0 0 R/W 88 98 High Low 1 1 0 X* 0 0 0 R/W C0 D0 High High 1 1 0 X* 0 1 0 R/W C4 D4 High Open 1 1 0 X* 1 0 0 R/W C8 D8 Open Low 0 1 0 X* 0 0 0 R/W 40 50 Open High 0 1 0 X* 0 1 0 R/W 44 54 Open Open 0 1 0 X* 1 0 0 R/W 48 58 PIN ADD1 DESERIALIZER DEVICE ADDRESS (hex) *X = 0 for the serializer address, X = 1 for the deserializer address. Table 3. LVDS, HDCP Mapping and Bus Width Selection (see Figures 13 and 14) 3-CHANNEL MODE (BWS = LOW) INPUT BITS 4-CHANNEL MODE (BWS = HIGH) BITMAPPING AUXILIARY SIGNALS MAPPING HDCP ENCRYPTION CAPABILITY BITMAPPING AUXILIARY SIGNALS MAPPING HDCP ENCRYPTION CAPABILITY DIN[0:5] R[0:5] -- DIN[6:11] G[0:5] -- Yes R[0:5] -- Yes Yes G[0:5] -- Yes DIN[12:17] B[0:5] -- DIN[18:20] HS, VS, DE -- Yes B[0:5] -- Yes No HS, VS, DE -- DIN[21:22] Not available No -- -- R6, R7 -- Yes DIN[23:24] Not available -- -- G6, G7 -- Yes DIN[25:26] DIN27 Not available -- -- B6, B7 -- Yes Not available Not available -- RES* CNTL1* No DIN28 -- Not available -- -- CNTL2 No SD -- SD/CNTL0 I2S** -- SD/CNTL0 I2S** *See the Reserved Bit (RES) section for details. **HDCP encryption on SD when used as an I2S signal. ______________________________________________________________________________________ 19 MAX9265 Table 2. Device Address Defaults (Register 0x00, 0x01) MAX9265 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface RXCLKINRXCLKIN+ CYCLE N-1 CYCLE N RXIN0+/RXIN0- DIN1 DIN0 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 RXIN1+/RXIN1- DIN8 DIN7 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 RXIN2+/RXIN2- DIN15 DIN14 DIN20 DIN19 DIN18 DIN17 DIN16 DIN15 DIN14 RXIN3+/RXIN3- DIN22 DIN21 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 CNTL1 DIN27 CNTL2 DIN28 SD/CNTL0* SD* *WITH I2S ENABLED; OTHERWISE CNTL0 Figure 13. LVDS Input Timing RXCLKINRXCLKIN+ CYCLE N-1 CYCLE N RXIN0+/RXIN0- R1 R0 G0 R5 R4 R3 R2 R1 R0 RXIN1+/RXIN1- G2 G1 B1 B0 G5 G4 G3 G2 G1 RXIN2+/RXIN2- B3 B2 DE VS HS B5 B4 B3 B2 RXIN3+/RXIN3- R7 R6 RES B7 B6 G7 G6 R7 R6 Figure 14. Panel Clock and Bit Assignment 20 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface Reserved Bit (RES) In 4-channel mode, the serializer serializes all bits of all four lanes, including RES, by default. Set DISRES (D4 of register 0x0D) to 1 to map CNTL1 to DIN27 instead of RES. Reverse Control Channel The serializer uses the reverse control channel to receive I2C/UART and interrupt signals from the GMSL deserializer in the opposite direction of the video stream. The reverse control channel and forward video data coexist on the same twisted pair forming a bidirectional link. The reverse control channel operates independently from the forward control channel. The reverse control channel is available 500Fs after power-up. The serializer temporarily disables the reverse control channel for 350Fs after starting/stopping the forward serial link. In addition to HDCP encryption (when enabled), the serializer scrambles and encodes the input data and sends the 8b/10b coded signal through the serial link. Figures 15 and 16 show the serial-data packet format before HDCP encryption, scrambling and 8b/10b encoding. In 3-channel or 4-channel mode, 21 or 29 bits map from the LVDS input. The audio channel bit (ACB) contains an encoded audio signal derived from the three I2S signals (SD, SCK, and WS). The forward control-channel (FCC) bit carries the forward control data. The last bit (PCB) is the parity bit of the previous 23 or 31 bits. 24 BITS DIN0 DIN1 R0 R1 DIN17 DIN18 DIN19 DIN20 ACB B5 RGB DATA HS VS FCC PCB DE CONTROL BITS AUDIO CHANNEL OR CNTL0 BIT LVDS DATA (3 CHANNELS) FORWARD CONTROLCHANNEL BIT NOTE: VS/HS MUST BE SET AT DIN[19:18] FOR HDCP FUNCTIONALITY. ONLY DIN[17:0] AND ACB HAVE HDCP ENCRYPTION. PACKET PARITY CHECK BIT Figure 15. 3-Channel Mode Serial Link Data Format 32 BITS DIN0 DIN1 R0 R1 DIN17 DIN18 DIN19 DIN20 DIN21 DIN22 DIN23 DIN24 DIN25 DIN26 DIN27 DIN28 B5 RGB DATA HS VS DE CONTROL BITS LVDS DATA (RXIN[2:0]_) NOTE: VS/HS MUST BE SET AT DIN[19:18] FOR HDCP FUNCTIONALITY. ONLY DIN[17:0], DIN[26:21] AND ACB HAVE HDCP ENCRYPTION. *DIN27 FROM LVDS DATA (RXIN3_) OR EXTERNAL PIN (CNTL1). R6 R7 G6 G7 B6 RGB DATA LVDS DATA (RXIN3_) B7 ACB FCC PCB RES/ CNTL2 CNTL1* AUX CONTROL BITS AUDIO CHANNEL OR CNTL0 BIT FORWARD CONTROLCHANNEL BIT PACKET PARITY CHECK BIT Figure 16. 4-Channel Mode Serial Link Data Format ______________________________________________________________________________________ 21 MAX9265 Serial Link Signaling and Data Format The serializer uses CML signaling with programmable preemphasis and AC-coupling. The GMSL deserializer uses AC-coupling and programmable channel equalization. Together, the GMSL link can operate at full speed over STP cable lengths to 15m or more. MAX9265 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface Data-Rate Selection The serializer uses the DRS input to set the RXCLKIN_ frequency range. Set DRS high for an RXCLKIN_ frequency range of 6.25MHz to 12.5MHz (4-channel mode) or 8.33MHz to 16.66MHz (3-channel mode). Set DRS low for normal operation with an RXCLKIN_ frequency range of 12.5MHz to 78MHz (4-channel mode) or 16.66MHz to 104MHz (3-channel mode). Audio Channel The I2S audio channel supports audio sampling rates from 8kHz to 192kHz, and audio word lengths from 4 bits to 32 bits. The audio bit clock (SCK) does not have to be synchronized with RXCLKIN_. The serializer automatically encodes audio data into a single bit stream synchronous with RXCLKIN_. The GMSL deserializer decodes the audio stream and stores audio words in a FIFO. Audio rate detection uses an internal oscillator to continuously determine the audio data rate and output the audio in I2S format. The audio channel is enabled by default. When the audio channel is disabled, SD/CNTL0 on the serializer and GMSL deserializer is treated as an additional control signal (CNTL0). Since the audio data sent through the serial link is synchronized with RXCLKIN, low RXCLKIN_ frequencies limit the maximum audio sampling rate. Table 4 lists the maximum audio sampling rate for various RXCLKIN_ frequencies. Spread-spectrum settings do not affect the I2S data rate or WS clock frequency. Control Channel and Register Programming The control channel is available for the FC to send and receive control data over the serial link simultaneously with the high-speed data. Configuring the CDS pin allows the FC to control the link from either the serializer or the GMSL deserializer side to support video-display or image-sensing applications. The control channel between the FC and serializer or GMSL deserializer runs in base mode or bypass mode according to the mode selection (MS) input of the device connected to the FC. Base mode is a half-duplex control channel and the bypass mode is a full-duplex control channel. Base Mode In base mode, the FC is the host and can access the core and HDCP registers of both the serializer and GMSL deserializer from either side of the link by using the GMSL UART protocol. The FC can also program the peripherals on the remote side by sending the UART packets to the serializer or GMSL deserializer, with the UART packets converted to I2C by the device on the remote side of the link (GMSL deserializer for LCD or serializer for image-sensing applications). The FC communicates with a UART peripheral in base mode (through INTTYPE register settings), using the half-duplex default GMSL UART protocol of the serializer/GMSL deserializer. The device addresses of the serializer and GMSL deserializer in base mode are programmable. The default value is determined by the pin settings of ADD0 and ADD1 (Table 2). When the peripheral interface uses I2C (default), the serializer/GMSL deserializer convert packets to I2C that have device addresses different from those of the serializer or GMSL deserializer. The converted I2C bit rate is the same as the original UART bit rate. The GMSL deserializer uses a proprietary differential line coding to send signals back towards the serializer. The speed of the control channel ranges from 9.6kbps to 1Mbps in both directions. The serializer and GMSL deserializer automatically detect the control-channel bit rate in base mode. Packet bit rates can vary up to 3.5x from the previous bit rate (see the Changing the Clock Frequency section). Figure 17 shows the UART protocol for writing and reading in base mode between the FC and the serializer/GMSL deserializer. Figure 18 shows the UART data format. Figure 19 and Figure 20 detail the formats of the SYNC byte (0x79) and the ACK byte (0xC3). The FC and the connected slave chip generate the SYNC byte and ACK byte, respectively. Events such as device wake-up and interrupt generate transitions on the control channel that should be ignored by the FC. Data written to the serializer/GMSL deserializer registers do not take effect until after the acknowledge byte is sent. This allows the FC to verify write commands received without error, even if the result of the write command directly affects the serial link. The slave uses the SYNC byte to synchronize with the host UART data rate automatically. If the INT or MS inputs of the GMSL deserializer toggles while there is control-channel communication, the control-channel communication can be corrupted. In the event of a missed acknowledge, the FC should assume there was an error in the packet when the slave device receives it, or that an error occurred during the response from the slave device. In base mode, the FC must keep the UART Tx/Rx lines high for 16 bit-times before starting to send a new packet. 22 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface RXCLKIN_ FREQUENCY (DRS = LOW) (MHz) WORD LENGTH (bits) RXCLKIN_ FREQUENCY (DRS = HIGH) (MHz) 12.5 15 16.6 > 20 6.25 7.5 8.33 > 10 8 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 16 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 18 185.5 > 192 > 192 > 192 185.5 > 192 > 192 > 192 20 174.6 > 192 > 192 > 192 174.6 > 192 > 192 > 192 24 152.2 182.7 > 192 > 192 152.2 182.7 > 192 > 192 32 123.7 148.4 164.3 > 192 123.7 148.4 164.3 > 192 WRITE DATA FORMAT SYNC DEV ADDR + R/W REG ADDR NUMBER OF BYTES BYTE 1 BYTE N ACK MASTER WRITES TO SLAVE MASTER READS FROM SLAVE READ DATA FORMAT SYNC DEV ADDR + R/W REG ADDR NUMBER OF BYTES MASTER WRITES TO SLAVE ACK BYTE 1 BYTE N MASTER READS FROM SLAVE Figure 17. GMSL UART Protocol for Base Mode 1 UART FRAME START D0 D1 D2 D3 FRAME 1 D4 D5 D6 D7 PARITY FRAME 2 STOP STOP FRAME 3 START STOP START Figure 18. GMSL UART Data Format for Base Mode START D0 D1 D2 D3 D4 D5 D6 D7 1 0 0 1 1 1 1 0 Figure 19. Sync Byte (0x79) PARITY STOP START D0 D1 D2 D3 D4 D5 D6 D7 1 1 0 0 0 0 1 1 PARITY STOP Figure 20. ACK Byte (0xC3) ______________________________________________________________________________________ 23 MAX9265 Table 4. LVDS, HDCP Mapping and Bus Width Selection (see Figures 13 and 14) MAX9265 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface As shown in Figure 21, the remote-side device converts the packets going to or coming from the peripherals from the UART format to the I2C format and vice versa. The remote device removes the byte number count and adds or receives the ACK between the data bytes of I2C. The I2C's data rate is the same as the UART data rate. the serializer by writing to the SETINT register bit. In normal operation, the state of the interrupt output changes when the interrupt input on the GMSL deserializer toggles. Do not send a logic-low value longer than 100Fs in either base or bypass mode to ensure proper interrupt functionality. Interfacing Command-Byte-Only I2C Devices The serializer and GMSL deserializer UART-to-I2C conversion interfaces with devices that do not require register addresses, such as the MAX7324 GPIO expander. In this mode, the I2C master ignores the register address byte and directly reads/writes the subsequent data bytes (Figure 22). Change the communication method of the I2C master using the I2CMETHOD bit. I2CMETHOD = 1 sets command-byteonly mode, while I2CMETHOD = 0 sets normal mode where the first byte in the data stream is the register address. The serial line driver in the serializer employs current-mode logic (CML) signaling. The driver can generate an adjustable preemphasized waveform according to the cable length and characteristics. There are 13 preemphasis settings as shown in Table 5. Negative preemphasis levels are deemphasis levels in which the preemphasized swing level is the same as normal swing, but the no-transition data is deemphasized. Program the preemphasis levels through register 0x05 D[3:0] of the serializer. This preemphasis function compensates the high frequency loss of the cable and enables reliable transmission over longer link distances. Additionally, a lower power drive mode can be entered by programming CMLLVL bits (0x05 D[5:4]) to reduce the driver strength down to 75% (CMLLVL = 10) or 50% (CMLLVL = 01) from 100% (CMLLVL = 11, default). Bypass Mode In bypass mode, the serializer/GMSL deserializer ignore UART commands from the FC and the FC communicates with the peripherals directly using its own defined UART protocol. The FC cannot access the serializer/GMSL deserializer's registers in this mode. Peripherals accessed through the forward control channel using the UART interface need to handle at least one RXCLKIN_ period 10ns of jitter due to the asynchronous sampling of the UART signal by RXCLKIN_. Set MS = high to put the control channel into bypass mode. For applications with the FC connected to the deserializer (CDS is high), there is a 1ms wait time between setting MS high and the bypass control channel being active. There is no delay time in switching to bypass mode when the FC is connected to the serializer (CDS = low). Bypass mode accepts bit rates down to 9.6kbps in either direction. See the Interrupt Control section for interrupt functionality limitations. The control-channel data pattern should not be held low longer than 100Fs in either base or bypass mode to ensure proper interrupt functionality. Interrupt Control The INT pin of the serializer is the interrupt output and the INT pin of the GMSL deserializer is the interrupt input. The interrupt output on the serializer follows the transitions at the interrupt input. This interrupt function supports remote-side functions such as touch-screen peripherals, remote powerup, or remote monitoring. Interrupts that occur during periods where the reverse control channel is disabled, such as link startup/shutdown, are automatically resent once the reverse control channel becomes available again. Bit D4 of register 0x06 in the GMSL deserializer also stores the interrupt input state. The INT output of the serializer is low after power-up. In addition, the FC can set the INT output of Pre/Deemphasis Driver Spread Spectrum To reduce the EMI generated by the transitions on the serial link, the serializer supports spread spectrum. Turning on spread spectrum on the serializer spreads the serial link, which is tracked by the serializer deserializer. The six selectable spread-spectrum rates at the serial output are Q0.5%, Q1%, Q1.5%, Q2%, Q3%, and Q4% (Table 6). Some spread-spectrum rates can only be used at lower RXCLKIN_ frequencies (Table 7). There is no RXCLKIN_ frequency limit for the 0.5% spread rate. Set the serializer's SSEN input high to select 0.5% spread at power-up and SSEN input low to select no spread at power-up. The state of SSEN is latched upon power-up or when resuming from power-down mode. Whenever the serializer's spread spectrum is turned on or off, the serial link automatically restarts and remains unavailable while the GMSL deserializer relocks to the serial data. Turning on spread spectrum on the serializer or GMSL deserializer does not affect the audio data stream. The serializer includes a sawtooth divider to control the spread-modulation rate. Autodetection or manual programming of the RXCLKIN_ operation range guarantees a spread-spectrum modulation frequency within 20kHz to 40kHz. Additionally, manual configuration of the sawtooth divider (SDIV, 0x03 D[5:0]) allows the user to set a modulation frequency according to the RXCLKIN_ frequency. Always keep the modulation frequency between 20kHz to 40kHz to ensure proper operation. 24 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface SERIALIZER/GMSL DESERIALIZER 11 SYNC FRAME 11 DEVICE ID + WR SERIALIZER/GMSL DESERIALIZER 11 REGISTER ADDRESS 11 NUMBER OF BYTES 11 DATA 0 11 DATA N 11 ACK FRAME PERIPHERAL 1 S 7 DEV ID 1 1 W A 8 REG ADDR 8 DATA 0 1 A 1 A 8 DATA N 1 1 A P UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 0) FC SERIALIZER/GMSL DESERIALIZER 11 SYNC FRAME 11 DEVICE ID + RD SERIALIZER/GMSL DESERIALIZER 11 REGISTER ADDRESS PERIPHERAL 1 S 7 DEV ID 11 NUMBER OF BYTES 8 REG ADDR 1 1 W A 1 1 A S : SLAVE TO MASTER : MASTER TO SLAVE 11 ACK FRAME 7 DEV ID 1 1 R A S: START 8 DATA 0 P: STOP 11 DATA 0 1 A 8 DATA N 11 DATA N 1 1 A P A: ACKNOWLEDGE Figure 21. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0) UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 1) FC 11 SYNC FRAME SERIALIZER/GMSL DESERIALIZER 11 11 DEVICE ID + WR REGISTER ADDRESS SERIALIZER/GMSL DESERIALIZER FC PERIPHERAL 1 7 S DEV ID 11 NUMBER OF BYTES 11 DATA N 1 1 W A 8 DATA 0 UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 1) SERIALIZER/GMSL DESERIALIZER 11 11 11 SYNC FRAME DEVICE ID + RD REGISTER ADDRESS SERIALIZER/GMSL DESERIALIZER 11 DATA 0 11 NUMBER OF BYTES 11 ACK FRAME 11 ACK FRAME 1 A 8 DATA N 11 DATA 0 1 1 A P 11 DATA N PERIPHERAL 1 S : MASTER TO SLAVE : SLAVE TO MASTER 7 DEV ID S: START 1 1 R A 8 DATA 0 P: STOP 1 A 8 DATA N 1 1 A P A: ACKNOWLEDGE Figure 22. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 1) ______________________________________________________________________________________ 25 MAX9265 UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 0) FC MAX9265 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface Table 5. CML Driver Strength (Default Level, CMLLVL = 11) PREEMPHASIS LEVEL (dB)* PREEMPHASIS SETTING (0x05, D[3:0]) ICML (mA) IPRE (mA) -6.0 0100 12 -4.1 0011 13 -2.5 0010 -1.2 SINGLE-ENDED VOLTAGE SWING MAX (mV) MIN (mV) 4 400 200 3 400 250 14 2 400 300 0001 15 1 400 350 0 0000 16 0 400 400 1.1 1000 16 1 425 375 2.2 1001 16 2 450 350 3.3 1010 16 3 475 325 4.4 1011 16 4 500 300 6.0 1100 15 5 500 250 8.0 1101 14 6 500 200 10.5 1110 13 7 500 150 14.0 1111 12 8 500 100 *Negative preemphasis levels denote deemphasis. Table 6. Serial Output Spread SS SPREAD (%) 000 No spread spectrum. Power-up default when SSEN = low. 001 Q0.5% spread spectrum. Power-up default when SSEN = high. 010 Q1.5% spread spectrum. 011 Q2% spread spectrum. 100 No spread spectrum. 101 Q1% spread spectrum. 110 Q3% spread spectrum. 111 Q4% spread spectrum. Table 7. Spread-Spectrum Rate Limitations 3-CHANNEL MODE RXCLKIN_ FREQUENCY (MHz) 4-CHANNEL MODE RXCLKIN_ FREQUENCY (MHz) SERIAL LINK BIT-RATE (Mbps) AVAILABLE SPREAD RATES < 33.3 < 25 < 1000 All rates available 33.3 to < 66.7 20 to <50 1000 to < 2000 1.5%, 1%, 0.5% 66.7+ 50+ 2000+ 0.5% 26 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface The modulation rate for the serializer relates to the RXCLKIN_ frequency as follows: f fM = (1 + DRS) RXCLKIN_ MOD x SDIV where: fM = Modulation frequency DRS = DRS pin input value (0 or 1) fRXCLKIN_ = RXCLKIN_ frequency MOD = Modulation coefficient given in Table 8 SDIV = 6-bit SDIV setting, manually programmed by the FC To program the SDIV setting, first look up the modulation coefficient according to the part number and desired bus-width and spread-spectrum settings. Solve the above equation for SDIV using the desired pixel clock and modulation frequencies. If the calculated SDIV value is larger than the maximum allowed SDIV value in Table 8, set SDIV to the maximum value. Sleep Mode The serializer includes a low-power sleep mode to reduce power consumption. Set the SLEEP bit to 1 to initiate sleep mode. The serializer sleeps immediately after setting its SLEEP = 1. See the Link Startup Procedure section for details on waking up the device for different FC and starting conditions. The FC can only put the remote-side device to sleep. Use the PWDN input pin to bring the FC-side device into a low-power state. Entering sleep mode resets the HDCP registers but not the configuration registers. Power-Down Mode The serializer includes a shutdown mode to further reduce power consumption. Set PWDN low to enter power-down mode. While in power-down mode, the outputs of the device remain high impedance. Entering power-down mode resets the internal registers of the device. In addition, upon exiting power-down mode, the serializer relatches the state of SSEN, DRS, AUTOS, and ADD_. Configuration Link Mode The GMSL includes a low-speed configuration link to allow control-data connection between the two devices in the absence of a valid clock input. In either display or camera applications, the configuration link can be used to program equalizer/preemphasis or other registers before establishing the video link. An internal oscillator provides RXCLKIN_ for establishing the serial configuration link between the serializer and GMSL deserializer. Set CLINKEN = 1 on the serializer to turn on the configuration link. The configuration link remains active as long as the video link has not been enabled. The video link overrides the configuration link and attempts to lock when SEREN = 1. Link Startup Procedure Table 9 lists four startup cases for video-display applications. Table 10 lists two startup cases for image-sensing applications. In either video-display or image-sensing applications, the control link is always available after the high-speed data link or the configuration link is Table 8. Modulation Coefficients and Maximum SDIV Settings BIT-WIDTH MODE 4-Channel 3-Channel SPREAD-SPECTRUM SETTING (%) MODULATION COEFFICIENT MOD (decimal) SDIV UPPER LIMIT (decimal) 1 104 40 0.5 104 63 3 152 27 1.5 152 54 4 204 15 2 204 30 1 80 52 0.5 80 63 3 112 37 1.5 112 63 4 152 21 2 152 42 ______________________________________________________________________________________ 27 MAX9265 Manual Programming of the Spread-Spectrum Divider MAX9265 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface established and the serializer/GMSL deserializer registers or the peripherals are ready for programming. Video-Display Applications For the video-display application with a remote display unit, connect the FC to the serializer and set CDS = low for both the serializer and GMSL deserializer. Table 9 summarizes the four startup cases based on the settings of AUTOS and MS. Case 1: Autostart Mode After power-up or when PWDN transitions from low to high for both the serializer and GMSL deserializer, the serial link establishes if a stable clock is present. The serializer locks to the clock and sends the serial data to the GMSL deserializer. The GMSL deserializer then detects activity on the serial link and locks to the input serial data. Case 2: Standby Start Mode After power-up or when PWDN transitions from low to high for both the serializer and GMSL deserializer, the GMSL deserializer starts up in sleep mode and the serializer stays in standby mode (does not send serial data). Use the FC and program the serializer to set SEREN = 1 to establish a video link, or CLINKEN = 1 to establish the configuration link. After locking to a stable clock (for SEREN = 1) or the internal oscillator (for CLINKEN = 1), the serializer sends a wake-up signal to the GMSL deserializer. The GMSL deserializer exits sleep mode after locking to the serial data and sets SLEEP = 0. If after 8ms the GMSL deserializer does not lock to the input serial data, the GMSL deserializer goes back to sleep and the internal sleep bit remains set (SLEEP = 1). Case 3: Remote-Side Autostart Mode After power-up or when PWDN transitions from low to high, the remote device (GMSL deserializer) starts up and tries to lock to an incoming serial signal with sufficient power. The host side (serializer) is in standby mode and does not try to establish a link. Use the FC and program the serializer to set SEREN = 1 (and apply a stable clock signal) to establish a video link, or CLINKEN = 1 to establish the configuration link. In this case, the GMSL deserializer ignores the short wake-up signal sent from the serializer. Case 4: Remote Side in Sleep Mode After power-up or when PWDN transitions from low to high, the remote device (GMSL deserializer) starts up in sleep mode. The high-speed link establishes automatically after the serializer powers up with a stable clock signal and sends a wake-up signal to the GMSL deserializer. Use this mode in applications where the GMSL deserializer powers up before the serializer. Table 9. Start Mode Selection for Display Applications (CDS = Low) CASE AUTOS (SERIALIZER) SERIALIZER POWER-UP STATE MS (GMSL DESERIALIZER) GMSL DESERIALIZER POWER-UP STATE 1 Low Serialization enabled Low Normal (SLEEP = 0) Both devices power up with serial link active (autostart). High Sleep mode (SLEEP = 1) The serial link is disabled and the GMSL deserializer powers up in sleep mode. Set SEREN = 1 or CLINKEN = 1 in the serializer to start the serial link and wake up the GMSL deserializer. Low Normal (SLEEP = 0) Both devices power up in normal mode with the serial link disabled. Set SEREN = 1 or CLINKEN = 1 in the serializer to start the serial link. Sleep mode (SLEEP = 1) The GMSL deserializer starts in sleep mode. Link autostarts upon serializer power-up. Use this case when the GMSL deserializer powers up before the serializer. 2 3 4 High Serialization disabled High Serialization disabled Low Serialization enabled High LINK STARTUP MODE 28 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface CLINKEN = 0 OR SEREN = 1 SEREN BIT POWER-UP VALUE 1 0 POWER-DOWN OR POWER-OFF CLINKEN = 0 OR SEREN = 1 PWDN = HIGH, POWER-ON POWER-ON IDLE AUTOS = LOW CLINKEN = 1 CONFIG LINK STARTING CONFIG LINK UNLOCKED CONFIG LINK OPERATING CONFIG LINK PROGRAM REGISTERS LOCKED PWDN = LOW OR POWER-OFF ALL STATES SEREN = 0, NO RXCLKIN_ SEREN = 1, RXCLKIN_ RUNNING PWDN = HIGH POWER-ON, AUTOS = LOW SEREN = 0, OR NO RXCLKIN_ VIDEO LINK LOCKING VIDEO LINK LOCKED PRBSEN = 0 VIDEO LINK OPERATING PRBSEN = 1 VIDEO LINK PRBS TEST VIDEO LINK UNLOCKED Figure 23. State Diagram, CDS = Low (LCD Application) Image-Sensing Applications For image-sensing applications, connect the FC to the GMSL deserializer and set CDS = high for both the serializer and GMSL deserializer. The GMSL deserializer powers up normally (SLEEP = 0) and continuously tries to lock to a valid serial input. Table 10 summarizes both startup cases, based on the state of the serializer's AUTOS pin. Case 1: Autostart Mode After power-up, or when PWDN transitions from low to high, the serializer locks to a stable input clock and sends the high-speed data to the GMSL deserializer. The GMSL deserializer locks to the serial data and outputs the video data and clock. Case 2: Sleep Mode After power-up or when PWDN transitions from low to high, the serializer starts up in sleep mode. To wake up the serializer, use the FC to send a GMSL-protocol UART frame containing at least three rising edges (e.g., 0x66), at a bit rate no greater than 1Mbps. The low-power wakeup receiver of the serializer detects the wake-up frame over the reverse control channel and powers up. Reset the sleep bit (SLEEP = 0) of the serializer using a regular control-channel write packet to power up the device fully. Send the sleep bit write packet at least 500Fs after the wake-up frame. The serializer goes back to sleep mode if its sleep bit is not cleared within 5ms (min) after detecting a wake-up frame. HDCP The explanation of HDCP operation in this data sheet is given as a guide for general understanding. Implementation of HDCP in a product must meet the requirements given in the "HDCP System v1.3 Amendment for GMSL," which is available from DCP, LLC. HDCP uses two main phases of operation: authentication and the link integrity check. The FC starts authentication by writing to the START_AUTHENTICATION bit in the serializer. The serializer generates a 64-bit random number. The host FC first reads the 64-bit random number from the serializer and writes it to the GMSL deserializer. The FC then reads the serializer public key selection vector (AKSV) and writes it to the GMSL deserializer. The FC then reads the GMSL deserializer KSV (AKSV) ______________________________________________________________________________________ 29 MAX9265 AUTOS PIN SETTING LOW HIGH MAX9265 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface Table 10. Start Mode Selection for Image-Sensing Applications (CDS = High) CASE AUTOS (SERIALIZER) SERIALIZER POWERUP STATE GMSL DESERIALIZER POWER-UP STATE 1 Low Serialization enabled Normal (SLEEP = 0) Autostart. 2 High Sleep mode (SLEEP = 1) Normal (SLEEP = 0) The serializer is in sleep mode. Wake up the serializer through the control channel (FC attached to GMSL deserializer). AUTOS PIN SETTING LOW HIGH SLEEP LINK STARTUP MODE POWER-UP VALUE SEREN SLEEP 1 0 0 1 SLEEP = 1 FOR > 8ms REVERSE LINK CLINKEN = 0 OR SEREN = 1 CLINKEN = 0 OR SEREN = 1 WAKE-UP SLEEP = 0, SEREN = 0 POWER-ON IDLE CLINKEN = 1 CONFIG LINK STARTED WAKE-UP SIGNAL PWDN = HIGH, POWER-ON, AUTOS = HIGH SLEEP = 1 ALL STATES PWDN = LOW OR POWER-OFF POWER-DOWN OR POWER-OFF SLEEP = 0, SLEEP = 1 PWDN = HIGH, POWER-ON AUTOS = LOW SEREN = 1, RXCLKIN_ RUNNING CONFIG LINK LOCKED CONFIG LINK OPERATING PROGRAM REGISTERS SEREN = 0 OR NO RXCLKIN_ SEREN = 0 OR NO RXCLKIN_ VIDEO LINK LOCKING CONFIG LINK UNLOCKED VIDEO LINK LOCKED PRBSEN = 0 VIDEO LINK OPERATING PRBSEN = 1 VIDEO LINK PRBS TEST VIDEO LINK UNLOCKED Figure 24. State Diagram, CDS = High (Camera Application) and writes it to the serializer. The FC begins checking the receiver BKSV against the revocation list. Using the cipher, the serializer and GMSL deserializer calculate a 16-bit response value (R0 and R0', respectively). The GMSL amendment for HDCP reduces the 100ms minimum wait time allowed the receiver to generate R0' (specified in HDCP rev 1.3) to 128 pixel clock cycles in the GMSL amendment. There are two response value comparison modes: internal comparison and FC comparison. Set EN_INT_COMP = 1 to select internal comparison mode. Set EN_INT_COMP = 0 to select FC comparison mode. In internal comparison mode, the FC reads the GMSL deserializer response R0' and writes it to the serializer. The serializer compares R0' to its internally generated response value R0, and sets R0_RI_MATCHED. In FC comparison mode, the FC reads and compares the R0/R0' values from the serializer/GMSL deserializer. During response value generation and checking, the host FC checks for a valid BKSV against the revocation list. If BKSV is not on the list and the response values match, the host authenticates the link. If the response values do not match, the FC resamples the response values (as described in HDCP rev 1.3 Appendix C). If resampling fails, the FC restarts authentication. If BKSV appears on the revocation list, the host cannot transmit data that requires protection. The host knows when the link is authenticated and decides when to output data requiring protection. The FC performs a link integrity check every 128 frames or every 2s Q0.5s. The serializer/ GMSL deserializer generate response values every 128 frames. These values are compared internally (internal comparison mode) or can be compared in the host FC. 30 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface Encryption Enable The GMSL link transfers either encrypted or nonencrypted data. For encrypted data, the host FC sets the encryption enable (ENCRYPTION_ENABLE) bit in both the serializer and GMSL deserializer. The FC must set ENCRYPTION_ENABLE in the same VSYNC cycle in both the serializer and GMSL deserializer (no VSYNC falling edges between the two writes). The same timing applies when clearing ENCRYPTION_ENABLE to disable encryption. Note: ENCRYPTION_ENABLE enables/disables encryption on the GMSL irrespective of the content. To comply with HDCP, the FC must not allow content requiring encryption to cross the GMSL unencrypted. See the Force Video/Force Audio for Unencrypted Data section. The FC must complete the authentication process before enabling encryption. In addition, encryption must be disabled before starting a new authentication session. VSYNC Detection If the FC cannot detect the video vertical sync (VSYNC) falling edge, it can use the serializer's VSYNC_DET register bit. The host FC first writes 0 to the VSYNC_DET bit. The serializer then sets VSYNC_DET = 1 once it detects an internal VSYNC falling edge (which may correspond to an external VSYNC rising edge if INVVSYNC of the serializer is set). The FC continuously reads VSYNC_DET and waits for the next internal VSYNC falling edge before setting ENCRYPTION_ ENABLE. Poll VSYNC_DET fast enough to allow time to set ENCRYPTION_ENABLE in both the serializer/GMSL deserializer within the same VSYNC cycle. Synchronization of Encryption The VSYNC synchronizes the start of encryption. Once encryption has started, the GMSL generates a new encryption key for each frame and each line, with the internal falling edge of VSYNC and HSYNC. Rekeying is transparent to data and does not disrupt the encryption of video or audio data. Repeater Support The serializer has features to build an HDCP repeater. An HDCP repeater receives and decrypts HDCP content and then encrypts and transmits on one or more downstream links. A repeater can also use decrypted HDCP content (e.g., to display on a screen). To support HDCP repeater authentication protocol, the GMSL deserializer has a REPEATER register bit. This register bit must be set to 1 by the FC (most likely on repeater module). Both the serializer and GMSL deserializer use SHA-1 hash-value calculation over the assembled KSV lists. HDCP GMSL links support a maximum of 15 receivers (total number including the ones in repeater modules). If the total number of receiver devices exceed 14, the FC must set the MAX_DEVS_EXCEEDED register bit when it assembles the KSV list. Force Video/Force Audio for Unencrypted Data The serializer masks audio and video data through two control bits: FORCE_AUDIO and FORCE_VIDEO. Set FORCE_VIDEO = 1 to transmit the 24-bit data word in the DFORCE register instead of the video data received at the LVDS input. Set FORCE_AUDIO = 0 to transmit 0 instead of the SD input (SCK and WS continue to be output from the deserializer). Use these features to blank out the screen and mute the audio. HDCP Authentication Procedures The serializer generates a 64-bit random number exceeding the HDCP requirement. The serializer/GMSL deserializer internal one-time programmable (OTP) memories contain unique HDCP keyset programmed at the factory. The host FC initiates and controls the HDCP authentication procedure. The serializer and GMSL deserializer generate HDCP authentication response values for the verification of authentication. Use the following procedures to authenticate the HDCP GMSL encryption (refer to the HDCP 1.3 Amendment for GMSL for details). The FC must perform link integrity checks while encryption is enabled (see Tables 12 and 13). Any event that indicates that the GMSL deserializer has lost link synchronization should retrigger authentication. The FC must first write 1 to the RESET_HDCP bit in the serializer before starting a new authentication attempt. HDCP Protocol Summary Tables 11, 12, and 13 list the summaries of the HDCP protocol. These tables serve as an implementation guide only. Meet the requirements in the GMSL amendment for HDCP to be in full compliance. ______________________________________________________________________________________ 31 MAX9265 In addition, the serializer/GMSL deserializer provide response values for the enhanced link verification feature. Enhanced link verification is an optional method of link verification for faster detection of loss-ofsynchronization. For this option, the serializer and GMSL deserializer generate 16-bit values (Pj and Pj') every 16 frames. The host must detect three consecutive Pj/Pj' mismatches before going to the resampling. MAX9265 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface Table 11. Startup, HDCP Authentication and Normal Operation (GMSL DESERIALIZER is not a Repeater)--First Part of the HDCP Authentication Protocol NO. C SERIALIZER GMSL DESERIALIZER 1 Initial state after power-up. Powers up waiting for HDCP authentication. Powers up waiting for HDCP authentication. 2 Ensures that A/V data not requiring protection (low-value content) is available at the serializer inputs (such as blue or informative screen). Alternatively, use the FORCE_VIDEO and FORCE_AUDIO bits of the serializer to mask the A/V data at the input of the serializer. Starts the link by writing SEREN = H or link starts automatically if AUTOS is low. -- -- 3 -- Starts serialization and transmits low-value content A/V data. Locks to incoming data stream and outputs lowvalue content A/V data. 4 Reads the locked bit of the GMSL deserializer and makes sure link is established. -- -- 5 Optionally writes a random-number seed to the serializer. Combines seed with internally generated random number. If no seed is provided, only internal random number is used. -- 6 If HDCP encryption is required, starts authentication by writing 1 to the START_AUTHENTICATION bit of the serializer. Generates (stores) AN and resets the START_ AUTHENTICATION bit to 0. -- 7 Reads AN and AKSV from the serializer and writes to the GMSL deserializer. -- Generates R0' triggered by the FC's write of AKSV. 8 Reads the BKSV and REPEATER bit from the GMSL deserializer and writes to the serializer. Generates R0, triggered by the FC's write of BKSV. -- 9 Reads the INVALID_BKSV bit of the serializer and continues with authentication if it is 0. Authentication can be restarted if it fails (set RESET_HDCP = 1 before restarting authentication). -- -- 10 Reads R0' from the GMSL deserializer and reads R0 from the serializer. If they match, continues with authentication; otherwise retries up to two more times (optionally, the serializer comparison can be used to detect if R0/R0' match). Authentication can be restarted if it fails (set RESET_HDCP = 1 before restarting authentication). -- -- 11 Waits for the VSYNC falling edge (internal to the serializer) and then sets the ENCRYPTION_ENABLE bit to 1 in the GMSL deserializer and serializer (if the FC is not able to monitor VSYNC, it can utilize the VSYNC_DET bit in the serializer). Encryption is enabled after the next VSYNC falling edge. Decryption is enabled after the next VSYNC falling edge. 32 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface NO. C SERIALIZER GMSL DESERIALIZER 12 Checks that BKSV is not in the Key Revocation List and continues if it is not. Authentication can be restarted if it fails. Note: Revocation list check can start after BKSV is read in step 8. -- -- 13 Starts transmission of the A/V content that needs protection. Performs HDCP encryption on high-value content A/V data. Performs HDCP decryption on high-value content A/V data. Table 12. Link Integrity Check (Normal)--Performed Every 128 Frames After Encryption is Enabled NO. C SERIALIZER GMSL DESERIALIZER 1 -- Generates Ri and updates the RI register every 128 VSYNC cycles. Generates Ri' and updates the RI' register every 128 VSYNC cycles. 2 -- Continues to encrypt and transmit A/V data. Continues to receive, decrypt, and output A/V data. 3 Every 128 video frames (VSYNC cycles) or every 2s. -- -- 4 Reads RI from the serializer. -- -- 5 Reads RI' from the GMSL deserializer. -- -- 6 Reads RI again from the serializer and ensures it is stable (matches the previous RI that it has read from the serializer). If RI is not stable, go back to step 5. -- -- 7 If RI matches RI', the link integrity check is successful; go back to step 3. -- -- 8 If RI does not match RI', the link integrity check fails. After the detection of failure of link integrity check, the FC ensures that A/V data not requiring protection (low-value content) is available at the serializer's inputs (such as blue or informative screen). Alternatively, the FORCE_VIDEO and FORCE_AUDIO bits of the serializer can be used to mask the A/V data input of the serializer. -- -- 9 Writes 0 to the ENCRYPTION_ENABLE bit of the serializer and GMSL deserializer. Disables encryption and transmits low-value content A/V data. Disables decryption and outputs low-value content A/V data. 10 Restarts authentication by writing 1 to the RESET_HDCP bit, followed by writing 1 to the START_AUTHENTICATION bit in the serializer. -- -- ______________________________________________________________________________________ 33 MAX9265 Table 11. Startup, HDCP Authentication and Normal Operation (GMSL DESERIALIZER is not a Repeater)--First Part of the HDCP Authentication Protocol (continued) MAX9265 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface Table 13. Optional Enhanced Link Integrity Check--Performed Every 16 Frames After Encryption is Enabled NO. C SERIALIZER GMSL DESERIALIZER 1 -- Generates Pj and updates the PJ register every 16 VSYNC cycles. Generates Pj' and updates the PJ' register every 16 VSYNC cycles. 2 -- Continues to encrypt and transmit the A/V data. Continues to receive, decrypt, and output the A/V data. 3 Every 16 video frames: reads PJ from the serializer and PJ' from the GMSL deserializer. -- -- 4 If PJ matches PJ', enhanced link integrity check is successful; go back to step 3. -- -- 5 If there is a mismatch, retry up to two more times from step 3. Enhanced link integrity check fails after three mismatches. After the detection of failure of enhanced link integrity check, the FC ensures that A/V data not requiring protection (low-value content) is available at the serializer inputs (such as blue or informative screen). Alternatively, the FORCE_VIDEO and FORCE_AUDIO bits of the serializer can be used to mask the A/V data input of the serializer. -- -- 6 Writes 0 to the ENCRYPTION_ENABLE bit of the serializer and GMSL deserializer. Disables encryption and transmits low-value content A/V data. Disables decryption and outputs low-value content A/V data. 7 Restarts authentication by writing 1 to the RESET_HDCP bit, followed by writing 1 to the START_AUTHENTICATION bit in the serializer. -- -- Example Repeater Network--Two Cs The example shown in Figure 25 has one repeater and two FCs. Table 14 summarizes the authentication operation. Use the following procedure to notify downstream links of the start of a new authentication request: Detection and Action Upon New Device Connection 2) When AKSV is written to HDCP repeater's input receiver, its AUTH_STARTED bit is automatically set and its GPIO1 goes high (if GPIO1_FUNCTION is set to high). When a new device is connected to the system, the device must be authenticated and the device's KSV is checked against the revocation list. The downstream FCs can set the NEW_DEV_CONN bit of the upstream receiver and invoke an interrupt to notify upstream FCs. Notification of Start of Authentication and Enable of Encryption to Downstream Links HDCP repeaters do not immediately begin authentication upon startup or detection of a new device, but instead wait for an authentication request from the upstream transmitter/repeaters. 1) Host FC begins authentication with HDCP repeater's input receiver. 3) HDCP repeater's FC waits for a low-to-high transition on HDCP repeater input receiver's AUTH_STARTED bit and/or GPIO1 (if configured) and starts authentication downstream. 4) HDCP repeater's FC resets AUTH_STARTED bit. Set GPIO0_FUNCTION to high to have GPIO0 follow the ENCRYPTION_ENABLE bit of the receiver. The repeater FC can use this function to be notified when encryption is enabled/disabled by an upstream FC. 34 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface TX_B1 DISPLAY 1 RX_R1 TX_R1 RX_D1 TX_R2 RX_D2 VIDEO ROUTING C_B MEMORY WITH SRM RX_R2 MAX9265 REPEATER BD-DRIVE C_R DISPLAY 2 VIDEO CONNECTION CONTROL CONNECTION 1 (C_B IN BD-DRIVE IS MASTER) CONTROL CONNECTION 2 (C_R IN REPEATER IS MASTER) Figure 25. Example Network with One Repeater and Two Cs (TXs are for the Serializer and RXs are for the GMSL Deserializer) Table 14. HDCP Authenticaion and Normal Operation (One Repeater, Two Cs)--First and Second Parts of the HDCP Authentication Protocol NO. C_B C_R SERIALIZER (TX_B1, TX_R1, TX_R2) GMSL DESERIALIZER (RX_R1, RX_D1, RX_D2) -- -- -- TX_B1 CDS = 0 TX_R1 CDS = 0 TX_R2 CDS = 0 RX_R1 CDS = 1 RX_D1 CDS = 0 RX_D2 CDS = 0 1 Initial state after power-up. Initial state after power-up. All: Power-up waiting for HDCP authentication. All: Power-up waiting for HDCP authentication. -- Writes REPEATER = 1 in RX_R1. Retries until a proper acknowledge frame is received. Note: This step must be completed before the first part of the authentication is started between TX_B1 and RX_R1 by FC_B (step 7). For example, to satisfy this requirement, RX_R1 can be held at power-down until FC_R is ready to write the REPEATER bit. Alternatively, FC_B can poll FC_R before starting authentication. -- -- 2 ______________________________________________________________________________________ 35 MAX9265 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface Table 14. HDCP Authenticaion and Normal Operation (One Repeater, Two Cs)--First and Second Parts of the HDCP Authentication Protocol (continued) NO. C_B 3 Ensures that the A/V data not requiring protection (low-value content) is available at TX_B1 inputs (such as blue or informative screen). Alternatively, the FORCE_VIDEO and FORCE_AUDIO bits of TX_B1 can be used to mask the A/V data input of TX_B1. Starts the link between TX_B1 and RX_R1 by writing SEREN = H to TX_B1 or link starts automatically if AUTOS is low. C_R SERIALIZER (TX_B1, TX_R1, TX_R2) GMSL DESERIALIZER (RX_R1, RX_D1, RX_D2) -- TX_B1: Starts serialization and transmits low-value content A/V data. RX_R1: Locks to incoming data stream and outputs low-value content A/V data. -- Starts all downstream links by writing SEREN = H to TX_R1, TX_R2, or links start automatically if AUTOS of the transmitters are low. TX_R1, TX_R2: Starts serialization and transmits lowvalue content A/V data. RX_D1, RX_D2: Locks to incoming data stream and outputs low-value content A/V data. Reads the locked bit of RX_R1 and ensures link between TX_B1 and RX_R1 is established. Reads the locked bit of RX_D1 and ensures link between TX_R1 and RX_D1 is established. Reads the locked bit of RX_D2 and ensures link between TX_R2 and RX_D2 is established. -- -- 6 Optionally, writes a random-number seed to TX_B1. Writes 1 to the GPIO_0_FUNCTION and GPIO_1_FUNCTION bits in RX_R1 to change GPIO functionality to be used for HDCP purpose. Optionally, writes a random-number seed to TX_R1 and TX_R2. -- -- 7 Starts and completes first part of the authentication protocol between TX_B1, RX_R1 (see steps 6-10 in Table 11). -- TX_B1: According to the commands from FC_B, generates AN, computes R0. RX_R1: According to the commands from FC_B, computes R0'. -- When GPIO_1 = 1 is detected, starts and completes first part of the authentication protocol between (TX_R1, RX_D1) and (TX_R2, RX_D2) links (see steps 6-10 in Table 11). TX_R1, TX_R2: According to the commands from FC_R, generates AN, computes R0. RX_D1, RX_D2: According to the commands from FC_R, computes R0'. 4 5 8 36 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface GMSL DESERIALIZER (RX_R1, RX_D1, RX_D2) RX_R1: Decryption is enabled after the next VSYNC falling edge. NO. C_B 9 Waits for the VSYNC falling edge and then enables encryption on the (TX_B1, RX_R1) link. Full authentication is not complete yet so it ensures A/V content that needs protection is not transmitted. Since REPEATER = 1 was read from RX_R1, the second part of authentication is required. -- TX_B1: Encryption is enabled after the next VSYNC falling edge. -- When GPIO_0 = 1 is detected, enables encryption on the (TX_R1, RX_D1) and (TX_R2, RX_D2) links. TX_R1, TX_R2: Encryption is enabled after the next VSYNC falling edge. RX_D1, RX_D2: Decryption is enabled after the next VSYNC falling edge. -- RX_R1: Control channel from the serializer side (TX_B1) is blocked after FWDCCEN = REVCCEN = 0 is written. -- RX_R1: Triggered by FC_R's write of BINFO, calculates hash value (V') on the KSV list, BINFO, and the secret value M0'. -- RX_R1: Control channel from the serializer side (TX_ B1) is unblocked after FWDCCEN = REVCCEN = 1 is written. 10 Blocks control channel from FC_B side by setting REVCCEN = FWDCCEN = 0 in RX_R1. Retries until the proper acknowledge frame is received. 11 12 13 C_R SERIALIZER (TX_B1, TX_R1, TX_R2) Waits for some time to allow FC_R to make the KSV List ready in RX_R1. Then polls (reads) the KSV_LIST_ READY bit of RX_R1 regularly until the proper acknowledge frame is received and bit is read as 1. Writes BKSVs of RX_D1 and RX_D2 to KSV List in RX_R1. Then calculates and writes BINFO register of RX_R1. Writes 1 to the KSV_LIST_READY bit of RX_R1 and then unblocks control channel from FC_B side by setting REVCCEN = FWDCCEN = 1 in RX_R1. ______________________________________________________________________________________ 37 MAX9265 Table 14. HDCP Authenticaion and Normal Operation (One Repeater, Two Cs)--First and Second Parts of the HDCP Authentication Protocol (continued) MAX9265 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface Table 14. HDCP Authenticaion and Normal Operation (One Repeater, Two Cs)--First and Second Parts of the HDCP Authentication Protocol (continued) NO. C_B C_R 14 Reads the KSV List and BINFO from RX_R1 and writes them to TX_B1. If any of the MAX_DEVS_EXCEEDED or MAX_CASCADE_EXCEEDED bits is 1, then authentication fails. Note: BINFO must be written after the KSV List. SERIALIZER (TX_B1, TX_R1, TX_R2) GMSL DESERIALIZER (RX_R1, RX_D1, RX_D2) -- TX_B1: Triggered by FC_B's write of BINFO, calculates hash value (V) on the KSV list, BINFO, and the secret value M0. -- 15 Reads V from TX_B1 and V' from RX_R1. If they match, continues with authentication; otherwise, retries up to two more times. -- -- -- 16 Searches for each KSV in the KSV List and BKSV of RX_R1 in the Key Revocation List. -- -- -- 17 If keys are not revoked, second part of authentication protocol is completed. -- -- -- 18 Starts transmission of the A/V content that needs protection. -- All: Perform HDCP encryption on highvalue A/V data. All: Perform HDCP decryption on highvalue A/V data. Applications Information Self PRBS Test The serializer/GMSL deserializer link includes a PRBS pattern generator and bit-error verification function. First, disable the glitch filters (set DISVSFILT, DISHSFILT to 1) in the GMSL deserializer. Next, disable VSYNC/HSYNC inversion in both the serializer and GMSL deserialzer (set INVVSYNC, INVHSYNC to 0). Then, set PRBSEN = 1 (0x04, D5) in the serializer and then the GMSL deserializer to start the PRBS test. Set PRBSEN = 0 (0x04, D5) first in the GMSL deserializer and then the serializer to exit the PRBS self test. Microcontrollers on Both Sides of the GMSL Link (Dual C Control) Usually the microcontroller is either on the serializer side for video-display applications or on the GMSL deserializer side for image-sensing applications. For the former case, both the CDS pins of the serializer/GMSL deserializer are set to low, and for the later case, the CDS pins are set to high. However, if the CDS pin of the serializer is low and the same pin of the GMSL deserializer is high, then the serializer/GMSL deserializer connect to both FCs simultaneously. In such a case, the FCs on either side can communicate with the serializer and GMSL. Contentions of the control link can happen if the FCs on both sides are using the link at the same time. The serializer/GMSL deserializer do not provide the solution for contention avoidance. The serializer/GMSL deserializer do not send an acknowledge frame when communication fails due to contention. Users can always implement a higher layer protocol to avoid the contention. In addition, if UART communication across the serial link is not required, the FCs can disable the forward and reverse control channel through the FWDCCEN and REVCCEN bits (0x04, D[1:0]) in the serializer/GMSL deserializer. UART communication across the serial link is stopped and contention between FCs no longer occurs. During dual FC operation, if one of the CDS pins on either side changes state, the link resumes the corresponding state described in the Link Startup Procedure section. 38 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface accurately tracks the LOCK status of the video link. LOCK asserts for video link only and not for the configuration link. Jitter-Filtering PLL Both the serializer and GMSL deserializer have softwareprogrammable device addresses. This allows multiple GMSL devices, along with I2C peripherals to coexist on the same control channel. The serializer device address is stored in registers 0x00 of each device, while the deserializer device address is stored in register 0x01 of each device. To change the device address, first write to the device whose address changes (register 0x00 of the serializer for serializer device address change, or register 0x01 of the GMSL deserializer for deserializer device address change). Then write the same address into the corresponding register on the other device (register 0x00 of the GMSL deserializer for serializer device address change, or register 0x01 of the serializer for deserializer device address change). In some applications, the LVDS input clock to the serializer (RXCLKIN_) includes noise, which reduces link reliability. The serializer has a narrowband jitter-filtering PLL to attenuate frequency components outside the PLL's bandwidth (< 100kHz, typ). Enable the jitter-filtering PLL by setting DISFPLL = 0 (0x05, D6). Changing the Clock Frequency Both the video clock rate (fRXCLKIN_) and the controlchannel clock rate (fUART) can be changed on-the-fly to support applications with multiple clock speeds. It is recommended to enable the serial link after the video clock stabilizes. To recalibrate any automatic settings if a clean frequency change cannot be guaranteed, stop the video clock for 5Fs and restart the serial link or toggle SEREN after each change in the video clock frequency. The reverse control channel remains unavailable for 350Fs after serial link start or stop. Limit on-thefly changes in fUART to factors of less than 3.5 at a time to ensure that the device recognizes the UART sync pattern. For example, when lowering the UART frequency from 1Mbps to 100kbps, first send data at 333kbps and then at 100kbps to have reduction ratios of 3 and 3.333, respectively. Do not interrupt RXCLKIN or change its frequency while encryption is enabled. Otherwise HDCP synchronization is lost and authentication must be repeated. To change the RXCLKIN_ frequency, stop the high-value content A/V data. Then disable encryption in the serializer/GMSL deserializer within the same VSYNC cycle--encryption stops at the next VSYNC falling edge. RXCLKIN can now be changed/stopped. Reenable encryption before sending any high-value content A/V data. Fast Detection of Loss-of-Synchronization A measure of link quality is the recovery time from loss of HDCP synchronization. With the GMSL, loss of GMSL lock usually accompanies a loss of HDCP sync. The host can be quickly notified of loss-of-lock by connecting the GMSL deserializer LOCK output to the INT input. If other sources use the interrupt input, such as a touch-screen controller, the FC can implement a routine to distinguish between interrupts from loss-of-sync and normal interrupts. Reverse control-channel communication does not require an active forward link to operate and Software Programming of the Device Addresses 3-Level Inputs for Default Device Address ADD0 and ADD1 are 3-level inputs that control the serializer's default device slave addresses (Table 2). Connect ADD0/ADD1 through a pullup resistor to IOVDD, a pulldown resistor to GND, or a high-impedance connection. For digital control, use three-state logic to drive the 3-level logic inputs. ADD0/ADD1 set the device addresses in the serializer only and not the GMSL deserializer. Set the GMSL deserializer's ADD0/ADD1 inputs to the same settings as the serializer. Alternatively, write to register 0x00 and 0x01 of the GMSL deserializer to reflect any changes made due to the 3-level inputs. Configuration Blocking The serializer can block changes to its non-HDCP registers. Set CFGBLOCK to make all non-HDCP registers as read only. Once set, the registers remain blocked until the supplies are removed or until PWDN is low. Backward Compatibility The serializer is backward compatible with the nonHDCP MAX9249 serializer, with the following exceptions: * Address pins: The ADD0 and ADD1 pins on the serializer are the reserved pins on the MAX9249 serializer. Connect ADD0 and ADD1 to GND to set the serializer's default device addresses to the same values as the MAX9249 serializer. ______________________________________________________________________________________ 39 MAX9265 As an example of dual FC use in an image-sensing application, the serializer can be in sleep mode and waiting for wake-up by the GMSL deserializer. After wake-up, the serializer-side FC sets the serializer's CDS pin low and assumes master control of the serializer's registers. MAX9265 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface * First UART packet delay: The FC must wait 2.7ms after power-up before sending the first UART packet to the serializer. This delay is < 200Fs for the MAX9249 serializer. The pinouts and packages are otherwise the same for both devices. See Table 3 and the Pin Description for backward-compatible pin mapping. Key Memory Each device has a unique HDCP key set that is stored in secure on-chip nonvolatile memory (NVM). The HDCP key set consists of forty 56-bit private keys and one 40-bit public key. The NVM is qualified for automotive applications. Line-Fault Detection The line-fault detector in the serializer monitors for line failures such as short to ground, short to battery, and open link for system fault diagnosis. Figure 3 shows the required external resistor connections. LFLT = low when a line fault is detected and LFLT goes high when the line returns to normal. The line-fault type is stored in 0x08 D[3:0] of the serializer. Filter LFLT with the FC to reduce the detector's susceptibility to short ground shifts. The fault detector threshold voltages are referenced to the serializer ground. Additional passive components set the DC level of the cable (Figure 3). If the serializer and GMSL deserializer grounds are different, the link DC voltage during normal operation can vary and cross one of the faultdetection thresholds. For the fault-detection circuit, select the resistor's power rating to handle a short to the battery. To detect the short-together case, refer to Application Note 4709: GMSL Line-Fault Detection. Table 15 lists the mapping for line-fault types. Internal Input Pulldowns The control and configuration inputs on the serializer/ GMSL deserializer include a pulldown resistor to GND. Pulldowns are disabled when the device is shut down PWDN = low) or put into sleep mode. Keep all inputs driven or use external pullup/pulldown resistors to prevent additional current consumption and undesired configuration due to undefined inputs. Choosing I2C/UART Pullup Resistors I2C/UART Both open-drain lines require pullup resistors to provide a logic-high level. There are tradeoffs between power dissipation and speed, and a compromise made in choosing pullup resistor values. Every device connected to the bus introduces some capacitance even when the device is not in operation. I2C specifies 300ns rise times to go from low to high (30% to 70%) for fast mode, which is defined for data rates up to 400kbps (see the I2C specifications in the Electrical Characteristics table for details). To meet the fast-mode rise-time requirement, choose the pullup resistors so that rise time tR = 0.85 x RPULLUP x CBUS < 300ns. The waveforms are not recognized if the transition time becomes too slow. The serializer/GMSL deserializer supports I2C/UART rates up to 1Mbps. AC-Coupling AC-coupling isolates the receiver from DC voltages up to the voltage rating of the capacitor. Four capacitors (two at the serializer output and two at the deserializer input) are needed for proper link operation and to provide protection if either end of the cable is shorted to a high voltage. AC-coupling blocks low-frequency ground shifts and low-frequency common-mode noise. Table 15. Line-Fault Mapping REGISTER ADDRESS BITS D[3:2] NAME LFNEG 0x08 D[1:0] LFPOS VALUE LINE FAULT TYPE 00 Negative cable wire shorted to supply voltage. 01 Negative cable wire shorted to ground. 10 Normal operation. 11 Negative cable wire disconnected. 00 Positive cable wire shorted to supply voltage. 01 Positive cable wire shorted to ground. 10 Normal operation. 11 Positive cable wire disconnected. *For the short-together case, refer to Application Note 4709: GMSL Line-Fault Detection. 40 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface Power-Supply Circuits and Bypassing The serializer uses an AVDD and DVDD of 1.7V to 1.9V, and an LVDSVDD of 3.0V to 3.6V. All single-ended inputs and outputs derive power from an IOVDD of 1.7V to 3.6V, which scale with IOVDD. Proper voltage-supply bypassing is essential for high-frequency circuit stability. Cables and Connectors Interconnect for CML typically has a differential impedance of 100I. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Twisted-pair and shielded twisted-pair cables tend to generate less EMI due to magnetic-field canceling effects. Balanced cables pick up noise as common mode rejected by the CML receiver. Table 16 lists the suggested cables and connectors used in the GMSL link. Board Layout Separate the digital signals and CML/LVDS high-speed signals to prevent crosstalk. Use a four-layer PCB with separate layers for power, ground, CML/LVDS, and digital signals. Lay out PCB traces close to each other for a 100I differential characteristic impedance. The trace dimensions depend on the type of trace used (microstrip or stripline). Note that two 50I PCB traces do not have 100I differential impedance when brought close together--the impedance goes down when the traces are brought closer. Route the PCB traces for a CML/LVDS channel (there are two conductors per CML/LVDS channel) in parallel to maintain the differential characteristic impedance. Avoid vias. Keep PCB traces that make up a differential pair equal length to avoid skew within the differential pair. ESD Protection The serializer's ESD tolerance is rated for Human Body Model, IEC 61000-4-2, and ISO 10605. The ISO 10605 and IEC 61000-4-2 standards specify ESD tolerance for electronic systems. CML/LVDS I/O are tested for ISO 10605 ESD protection and IEC 61000-4-2 ESD protection. All pins are tested for the Human Body Model. The Human Body Model discharge components are CS = 100pF and RD = 1.5kI (Figure 26). The IEC 61000-4-2 discharge components are CS = 150pF and RD = 330I (Figure 27). The ISO 10605 discharge components are CS = 330pF and RD = 2kI (Figure 28). Table 16. Suggested Connectors and Cables for GMSL VENDOR CONNECTOR CABLE Rosenberger D4S10A-40ML5-Z Dacar 538 Nissei GT11L-2S F-2WME AWG28 JAE MX38-FF A-BW-Lxxxxx 1MI HIGHVOLTAGE DC SOURCE CHARGE-CURRENTLIMIT RESISTOR CS 100pF RD 1.5kI DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 26. Human Body Model ESD Test Circuit ______________________________________________________________________________________ 41 MAX9265 Selection of AC-Coupling Capacitors Voltage droop and the digital sum variation (DSV) of transmitted symbols cause signal transitions to start from different voltage levels. Because the transition time is finite, starting the signal transition from different voltage levels causes timing jitter. Choose the time constant for an AC-coupled link to reduce droop and jitter to an acceptable level. The RC network for an AC-coupled link consists of the CML receiver termination resistor (RTR), the CML driver termination resistor (RTD), and the series AC-coupling capacitors (C). The RC time constant for four equal-value series capacitors is (C x (RTD + RTR))/4. RTD and RTR are required to match the transmission line impedance (usually 100I). This leaves the capacitor selection to change the system time constant. Use at least 0.2FF high-frequency surface-mount ceramic capacitors, with sufficient voltage rating to withstand a short to battery, to pass the lower speed reverse controlchannel signal. Use capacitors with a case size less than 3.2mm x 1.6mm to have lower parasitic effects to the high-speed signal. MAX9265 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface RD 330I HIGHVOLTAGE DC SOURCE CHARGE-CURRENTLIMIT RESISTOR CS 150pF RD 2kI DISCHARGE RESISTANCE STORAGE CAPACITOR HIGHVOLTAGE DC SOURCE DEVICE UNDER TEST Figure 27. IEC 61000-4-2 Contact Discharge ESD Test Circuit CHARGE-CURRENTLIMIT RESISTOR CS 330pF DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 28. ISO 10605 Contact Discharge ESD Test Circuit Table 17. Serializer GMSL Core Register Table (see Table 1) REGISTER ADDRESS BITS NAME VALUE D[7:1] SERID XXXXXXX D0 CFGBLOCK D[7:1] DESID XXXXXXX D0 -- 0 0x00 0x01 D[7:5] SS Normal operation. 1 Registers 0x00 to 0x1F are read only. 001 0.5% spread spectrum. Power-up default when SSEN = high. 010 1.5% spread spectrum. 011 111 D[3:2] D[1:0] PRNG SRNG Reserved. 000 110 AUDIOEN Deserializer device address. Power-up default address determined by ADD0 and ADD1 (see Table 2). No spread spectrum. Power-up default when SSEN = low. 101 D4 Serializer device address. Power-up default address determined by ADD0 and ADD1 (see Table 2). 0 100 0x02 FUNCTION 0 1 2% spread spectrum. DEFAULT VALUE XX00XX0 0 XX01XX0 0 000, 001 No spread spectrum. 1% spread spectrum. 3% spread spectrum. 4% spread spectrum. Disable I2S channel. Enable I2S channel. 00 12.5MHz to 25MHz pixel clock. 01 25MHz to 50MHz pixel clock. 10 50MHz to 104MHz pixel clock. 11 Automatically detect the pixel clock range. 00 0.5Gbps to 1Gbps serial-bit rate. 01 1Gbps to 2Gps serial-bit rate. 10 2Gbps to 3.125Gbps serial-bit rate. 11 Automatically detect serial-bit rate. 42 1 11 11 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface REGISTER ADDRESS BITS D[7:6] NAME D7 0x04 SDIV CLINKEN D5 PRBSEN D4 D[3:2] Calibrate spread-modulation rate only once after locking. 01 Calibrate spread-modulation rate every 2ms after locking. 10 Calibrate spread-modulation rate every 16ms after locking. 11 Calibrate spread-modulation rate every 256ms after locking. 000000 Autocalibrate sawtooth divider. XXXXXX Manual SDIV setting. See the Manual Programming of the Spread-Spectrum Divider section. 0 Disable serial link. Power-up default when AUTOS = high. Reverse control-channel communication remains unavailable for 350Fs after the serializer starts/stops the serial link. 1 Enable serial link. Power-up default when AUTOS = low. Reverse control-channel communication remains unavailable for 350Fs after the serializer starts/stops the serial link. 0 Disable configuration link. 1 Enable configuration link. 0 Disable PRBS test. 1 Enable PRBS test. 0 Normal mode. Default value depends on the CDS and AUTOS pin values at power-up). 1 Activate sleep mode. Default value depends on the CDS and AUTOS pin values at power-up. 00 Base mode uses I2C peripheral interface. 01 Base mode uses UART peripheral interface. SEREN D6 SLEEP INTTYPE 10, 11 D1 D0 FUNCTION 00 AUTOFM 0x03 D[5:0] VALUE Disable reverse control channel from deserializer (receiving). 1 Enable reverse control channel from deserializer (receiving). 0 Disable forward control channel to deserializer (sending). 1 Enable forward control channel to deserializer (sending). FWDCCEN 00 000000 0, 1 0 0 0, 1 00 Base mode peripheral interface disabled. 0 REVCCEN DEFAULT VALUE 1 1 ______________________________________________________________________________________ 43 MAX9265 Table 17. Serializer GMSL Core Register Table (see Table 1) (continued) MAX9265 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface Table 17. Serializer GMSL Core Register Table (see Table 1) (continued) REGISTER ADDRESS BITS NAME D7 I2CMETHOD D6 DISFPLL D[5:4] CMLLVL 0x05 D[3:0] PREEMP VALUE FUNCTION 0 I2C conversion sends the register address. 1 Disable sending of I2C register address (commandbyte-only mode). 0 Filter PLL active. 1 Filter PLL disabled. 00 Do not use. 01 200mV CML signal level. 10 300mV CML signal level. 11 400mV CML signal level. 0000 Preemphasis off. 0001 -1.2dB preemphasis. 0010 -2.5dB preemphasis. 0011 -4.1dB preemphasis. 0100 -6.0dB preemphasis. 0101 Do not use. 0110 Do not use. 0111 Do not use. 1000 1.1dB preemphasis. 1001 2.2dB preemphasis. 1010 3.3dB preemphasis. 1011 4.4dB preemphasis. 1100 6.0dB preemphasis. 1101 8.0dB preemphasis. 1110 10.5dB preemphasis. 1111 14.0dB preemphasis. DEFAULT VALUE 0 1 11 0000 0x06 D[7:0] -- 01000000 Reserved. 01000000 0x07 D[7:0] -- 00100010 Reserved. 00100010 D[7:4] -- 0000 Reserved. 0000 (read only) D[3:2] LFNEG 0x08 0x0C D[1:0] LFPOS D[7:0] -- 00 Negative cable wire shorted to supply voltage. 01 Negative cable wire shorted to ground. 10 Normal operation. 11 Negative cable wire disconnected. 00 Positive cable wire shorted to supply voltage. 01 Positive cable wire shorted to ground. 10 Normal operation. 11 Positive cable wire disconnected. 01110000 Reserved. 44 10 (read only) 10 (read only) 01110000 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface REGISTER ADDRESS BITS NAME D7 SETINT D6 INVVSYNC D5 INVHSYNC D[4:0] -- D4 DISRES 0x0D D[3:0] 0x1E 0x1F SKEWADJ VALUE FUNCTION 0 Set INT low when SETINT transitions from 1 to 0. 1 Set INT high when SETINT transitions from 0 to 1. 0 Serializer does not invert VSYNC. 1 Serializer inverts VSYNC. 0 Serializer does not invert HSYNC. 1 Serializer inverts HSYNC. 00000 Reserved. 0 RES (LVDS interface) mapped to DIN27. 1 CNTL1 mapped to DIN27. 0000 Adjust x7PLL clock skew +50ps. 0001 Adjust x7PLL clock skew +100ps. 0010 Adjust x7PLL clock skew +200ps. 0011 Adjust x7PLL clock skew +250ps. 0100 Adjust x7PLL clock skew +300ps. 0101 Adjust x7PLL clock skew +350ps. 0110 Adjust x7PLL clock skew +400ps. 0111 Do not use. 1000 Adjust x7PLL clock skew +50ps. 1001 Adjust x7PLL clock skew +100ps. 1010 Adjust x7PLL clock skew +200ps. 1011 Adjust x7PLL clock skew +250ps. 1100 Adjust x7PLL clock skew +300ps. 1101 Adjust x7PLL clock skew +350ps. 1110 Adjust x7PLL clock skew +400ps. 1111 No x7PLL clock skew adjustment. D[7:0] ID 00000111 D[7:5] -- 000 D4 CAPS D[3:0] REVISION DEFAULT VALUE 0 0 0 00000 0 1111 Device identifier (MAX9265 = 0x07). 00000111 (read only) Reserved. 000 (read only) 0 Not HDCP capable. 1 HDCP capable. 1 (read only) XXXX Device revision. (read only) ______________________________________________________________________________________ 45 MAX9265 Table 17. Serializer GMSL Core Register Table (see Table 1) (continued) MAX9265 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface Table 18. Serializer HDCP Register Table (see Table 1) REGISTER ADDRESS SIZE (BYTES) NAME READ/ WRITE 0x80 to 0x84 5 BKSV Read/write HDCP receiver KSV Read/write RI (read only) of the transmitter when EN_INT_COMP = 0 RI' (read/write) of the receiver when EN_INT_COMP = 1 0x0000 PJ/PJ' Read/write PJ (read only) of the transmitter when EN_INT_COMP = 0 PJ' (read/write) of the receiver when EN_INT_COMP = 1 0x00 0x85 to 0x86 2 RI/RI' FUNCTION DEFAULT VALUE (hex) 0x0000000000 0x87 1 0x88 to 0x8F 8 AN Read only Session random number (Read only) 0x90 to 0x94 5 AKSV Read only HDCP transmitter KSV (Read only) D7 = PD_HDCP 1 = Power down HDCP circuits 0 = HDCP circuits normal D6 = EN_INT_COMP 1 = Internal comparison mode 0 = FC comparison mode D5 = FORCE_AUDIO 1 = Force audio data to 0 0 = Normal operation D4 = FORCE_VIDEO 1 = Force video data DFORCE value 0 = Normal operation 0x95 1 ACTRL Read/write D3 = RESET_HDCP 1 = Reset HDCP circuits Automatically set to 0 upon completion 0 = Normal operation D2 = START_AUTHENTICATION 1 = Start authentication Automatically set to 0 once authentication starts 0 = Normal operation D1 = VSYNC_DET 1 = Internal falling edge on VSYNC detected 0 = No falling edge detected D0 = ENCRYPTION_ENABLE 1 = Enable encryption 0 = Disable encryption 46 0x00 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface REGISTER ADDRESS SIZE (BYTES) NAME READ/ WRITE FUNCTION DEFAULT VALUE (hex) D[7:4] = Reserved D3 = V_MATCHED 1 = V matches V' (when EN_INT_COMP = 1) 0 = V does not match V' or EN_INT_COMP = 0 0x96 1 ASTATUS Read only D2 = PJ_MATCHED 1 = PJ matches PJ' (when EN_INT_COMP = 1) 0 = PJ does not match PJ' or EN_INT_COMP = 0 D1 = R0_RI_MATCHED 1 = RI matches RI' (when EN_INT_COMP = 1) 0 = RI does not match RI' or EN_INT_COMP = 0 0x00 (read only) D0 = BKSV_INVALID 1 = BKSV is not valid 0 = BKSV is valid D[7:1] = RESERVED D0 = REPEATER 1 = Set to 1 if device is a repeater 0 = Set to 0 if device is not a repeater 0x97 1 BCAPS Read/write 0x98 to 0x9C 5 ASEED Read/write Internal random number generator optional seed value Read/write Forced video data transmitted when FORCE_VIDEO = 1 R[7:0] = DFORCE[7:0] G[7:0] = DFORCE[15:8] B[7:0] = DFORCE[23:16] 0x000000 Read/write H0 part of SHA-1 hash value V (read only) of the transmitter when EN_INT_COMP = 0 V' (read/write) of the receiver when EN_INT_COMP = 1 0x00000000 Read/write H1 part of SHA-1 hash value V (read only) of the transmitter when EN_INT_COMP = 0 V' (read/write) of the receiver when EN_INT_COMP = 1 0x00000000 Read/write H2 part of SHA-1 hash value V (read only) of the transmitter when EN_INT_COMP = 0 V' (read/write) of the receiver when EN_INT_COMP = 1 0x00000000 0x9D to 0x9F 0xA0 to 0xA3 0xA4 to 0xA7 0xA8 to 0xAB 3 4 4 4 DFORCE V.H0, V'.H0 V.H1, V'.H1 V.H2, V'.H2 0x00 0x0000000000 ______________________________________________________________________________________ 47 MAX9265 Table 18. Serializer HDCP Register Table (see Table 1) (continued) MAX9265 HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface Table 18. Serializer HDCP Register Table (see Table 1) (continued) REGISTER ADDRESS 0xAC to 0xAF 0xB0 to 0xB3 SIZE (BYTES) 4 4 NAME V.H3, V'.H3 V.H4, V'.H4 READ/ WRITE FUNCTION DEFAULT VALUE (hex) Read/write H3 part of SHA-1 hash value V (read only) of the transmitter when EN_INT_COMP = 0 V' (read/write) of the receiver when EN_INT_COMP = 1 0x00000000 Read/write H4 part of SHA-1 hash value V (read only) of the transmitter when EN_INT_COMP = 0 V' (read/write) of the receiver when EN_INT_COMP = 1 0x00000000 D[15:12] = Reserved D11 = MAX_CASCADE_EXCEEDED 1 = Set to one if more than 7 cascaded devices attached 0 = Set to zero if 7 or fewer cascaded devices attached 0xB4 to 0xB5 2 BINFO Read/write D[10:8] = DEPTH Depth of cascaded devices 0x0000 D7 = MAX_DEVS_EXCEEDED 1 = Set to one if more than 14 devices attached 0 = Set to zero if 14 or fewer devices attached D[6:0] = DEVICE_COUNT Number of devices attached 0xB6 1 GPMEM Read/write General-purpose memory byte 0xB7 to 0xB9 3 -- Read only Reserved 0xBA to 0xFF 70 KSV_LIST Read/write List of KSV's downstream repeaters and receivers (maximum of 14 devices) 48 0x00 0x000000 All zero HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface RXCLKIN+/RXIN0+/- TO RXIN2+/- TXCLK+/TX0+/- TO TX2+/GPU CDS PCLK RGB HSYNC VSYNC DE PCLKOUT DOUT[17:0] DOUT18/HS DOUT19/VS DOUT20 45kI 45kI 5kI 5kI CDS DISPLAY AUTOS LMN1 LMN0 ECU MAX9265 UART TX RX/SDA TX/SCL RX LFLT INT MS LFLT INT MS MAX9264 OUT+ IN+ OUT- IN50kI TO PERIPHERALS INT RX/SDA TX/SCL 50kI ADD0 SCL SDA WS LOCK ADD1 WS SCK AUDIO SD WS SCK SD/CNTL0 WS SCK SD MAX9850 SCK SD PLL MCLK NOTE: NOT ALL PULLUP/PULLDOWN RESISTORS ARE SHOWN. SEE PIN DESCRIPTION FOR DETAILS. VIDEO-DISPLAY APPLICATION Chip Information PROCESS: BiCMOS X1 OUT Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 48 TQFP-EP C48E+8 21-0065 90-0138 ______________________________________________________________________________________ 49 MAX9265 Typical Application Circuit HDCP Gigabit Multimedia Serial Link Serializer with LVDS System Interface MAX9265 Revision History REVISION NUMBER REVISION DATE 0 12/10 DESCRIPTION Initial release PAGES CHANGED -- Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 50 (c) Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.