ISL78310ARAJZ-TR5303 - Intersil Corporation

High Performance 1A LDO

ISL78310

The ISL78310 is a low dropout voltage, high-current, single

output LDO specified for 1A output current. This part operates

from input voltages down to 2.2V and up to 6V. The part offers

fixed and external resistor adjustable output voltages from 0.8V

to 5V. Custom voltage options are available upon request.

For applications that desire to set the in-rush current to less than

the current limit of the part, or for applications that require

turn-on time control, an external capacitor can be placed on the

soft-start pin for maximum control. A supply-independent

ENABLE signal allows the part to be placed into a low quiescent

current shutdown mode. Sub-micron CMOS process is used for

this product family to deliver best-in-class analog performance

and overall value.

This CMOS LDO consumes significant lower quiescent (ground

pin) current as a function of load over bipolar LDOs, which

translates into higher efficiency and packages with smaller

footprints. Quiescent current is optimized to achieve a very fast

load transient response.

The ISL78310 is both AEC-Q100 rated and fully TS16949

compliant. The ISL78310 is rated for the automotive

temperature range (-40°C to +125°C).

Applications

•Core & I/O Power

• Camera Modules

• Post Regulation of Switched Supplies

• Radio Systems

• Infotainment Systems

Features

• 2.2V to 6V Input Supply

• 130mV Dropout Voltage Typical (at 1A)

• Fast Load Transient Response

• ±0.2% Initial VOUT Accuracy

• Adjustable In-Rush Current Limiting

• 58dB Typical PSRR

• 63µVRMS Output Noise at VOUT = 1.8V

• Power-Good Feature

• 500mV Feedback Voltage

• Supply-Independent 1V Enable Input Threshold

• Short-Circuit Current Protection

• 1A Peak Reverse Current

•Over-Temperature Shutdown

• Any Cap Stable with Minimum 10µF Ceramic

• ±1.8% Guaranteed VOUT Accuracy for Junction Temperature

Range from -40°C to +125°C

• Available in a 10 Lead DFN Package

• Pb-Free (RoHS Compliant)

• AEC-Q100 Tested

• TS16949 Compliant

Pin Configuration

ISL78310

(10 LD 3x3 DFN)

TOP VIEW

VOUT

SENSE/ADJ

GND

VIN

ENABLE

PAD

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

February 17, 2011

FN7810.0

ISL78310

2FN7810.0

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Pin Descriptions

NUMBER PIN NAME DESCRIPTION

1, 2 VOUT Regulated output voltage. A minimum 10µF X5R/X7R output capacitor is required for stability. See “External

Capacitor Requirements” on page 9 for more details.

3 SENSE/ADJ For internally fixed VOUT option, this pin provides output voltage feedback. By connecting this pin to the output rail

at the load, small voltage drops caused by PCB trace resistance can be eliminated.

For the adjustable output voltage option, this pin is connected to the feedback resistor divider and provides voltage

feedback signals for the LDO to set the outpt voltage.

4 PG This is an open drain logic output used to indicate the status of the output voltage. Logic low indicates VOUT is not

in regulation. Must be grounded if not used.

5GNDGround.

6 SS External capacitor on this pin adjusts startup ramp and controls in-rush current.

7ENABLE V

IN independent chip enable. TTL and CMOS compatible.

8 NC Do not connect this pin to ground or supply. Leave floating.

9, 10 VIN Input supply pin. A minimum 10µF X5R/X7R input capacitor is required for stability. See “External Capacitor

Requirements” on page 9 for more details.

EPAD EPAD at ground potential. Soldering it directly to GND plane is required for thermal considerations. See “Heatsinking

the DFN Package” on page 11 for more details.

Ordering Information

PART NUMBER

(Notes 1, 3, 4) PART MARKING

VOUT VOLTAGE

(Note 2) TEMP RANGE (°C)

PACKAGE

(Pb-Free) PKG DWG. #

ISL78310ARAJZ DZAE ADJ -40 to +125 10 Ld 3x3 DFN L10.3x3

ISL78310ARAJZ-TR5303 DZAE ADJ -40 to +125 10 Ld 3x3 DFN L10.3x3

NOTES:

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. For other output voltages, contact Intersil Marketing.

3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

4. For Moisture Sensitivity Level (MSL), please see device information page for ISL78310. For more information on MSL please see techbrief TB363.

ISL78310

3FN7810.0

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Typical Application Diagrams

FIGURE 1. FIXED TYPICAL APPLICATION DIAGRAM

FIGURE 2. ADJUSTABLE TYPICAL APPLICATION DIAGRAM

NOTE:

5. Used when large bulk capacitance required on VOUT for application.

VIN

ENABLE

GND

SENSE/ADJ

VIN

VOUT 1

10k 100k

10µF

2.5V ± 10% 1.8V ± 1.8%

VOUT

ISL78310

(NOTE 5)

10µF

VIN

ENABLE

GND

VIN

VOUT

10k 100k

10µF 10µF

2.5V ± 10% 1.8V ± 1.8%

SENSE/ADJ

2.6k

VOUT

ISL78310

(NOTE 5)

ISL78310

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ISL78310 Schematic Block Diagram



VIN

VOUT

ISL78310

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Absolute Maximum Ratings Thermal Information

VIN relative to GND (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V

VOUT relative to GND (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V

PG, ENABLE, SENSE/ADJ, SS

Relative to GND (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V

Recommended Operating Conditions (Notes 9, 10)

Junction Temperature Range (TJ) (Note 9) . . . . . . . . . . . .-40°C to +125°C

VIN relative to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2V to 6V

VOUT range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mV to 5V

PG, ENABLE, SENSE/ADJ, SS relative to GND . . . . . . . . . . . . . . . 0V to +6V

PG Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <10mA

Thermal Resistance . . . . . . . . . . . . . . . . . . . . θJA (°C/W) θJC (°C/W)

10 Ld DFN Package (Notes 7, 8) . . . . . . . . 48 7

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

ESD Rating

Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 2500V

Machine Model (Tested per JESD-A115-A) . . . . . . . . . . . . . . . . . . . . . 250V

Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . . 1000V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

6. Absolute maximum voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.

7. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

Brief TB379.

8. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

9. Extended operation at these conditions may compromise reliability. Exceeding these limits will result in damage. Recommended operating conditions

define limits where specifications are guaranteed.

10. Electromigration specification defined as lifetime average junction temperature of +110°C where max rated DC current = lifetime average current.

Electrical Specifications Unless otherwise noted, VIN = VOUT + 0.4V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, ILOAD = 0A.

Applications must follow thermal guidelines of the package to determine worst case junction temperature. Please refer to “ISL78310 Schematic

Block Diagram” on page 4 and Tech Brief TB379. Boldface limits apply over the operating temperature range, -40°C to +125°C.

PARAMETER SYMBOL TEST CONDITIONS

MIN

(Note 11) TYP

MAX

(Note 11) UNITS

DC CHARACTERISTICS

DC Output Voltage Accuracy VOUT VOUT Options: 0.8V, 1.2V, 1.5V and 1.8V

2.2V ≤ VIN < 3.6V; 0A < ILOAD ≤ 1A -1.8 0.2 1.8 %

VOUT Options: 2.5V, 3.3V and 5.0V

VOUT + 0.4V ≤ VIN ≤ 6V; 0A < ILOAD < 1A -1.8 0.2 1.8 %

Feedback Pin (ADJ Option Only) VADJ 2.2V ≤VIN ≤ 6V, 0A < ILOAD < 1A 491 500 509 mV

DC Input Line Regulation ΔVOUT/

ΔVIN

VOUT + 0.5V < VIN < 5V 1%

DC Output Load Regulation ΔVOUT/

ΔIOUT

0A < ILOAD < 1A, All voltage options -1 %

Feedback Input Current VADJ = 0.5V 0.01 1µA

Ground Pin Current IQILOAD = 0A, 2.2V < VIN < 6V 3 5mA

ILOAD = 1A, 2.2V < VIN < 6V 5 7mA

Ground Pin Current in Shutdown ISHDN ENABLE Pin = 0V, VIN = 6V 0.2 12 µA

Dropout Voltage (Note 12) VDO ILOAD = 1A, VOUT = 2.5V 130 212 mV

Output Short Circuit Current OCP VOUT = 0V, 2.2V < VIN < 6V 1.75 A

Thermal Shutdown Temperature TSD 2.2V < VIN < 6V 160 °C

Thermal Shutdown Hysteresis

(Rising Threshold)

TSDn 2.2V < VIN < 6V 30 °C

AC CHARACTERISTICS

Input Supply Ripple Rejection PSRR f = 1kHz, ILOAD = 1A; VIN = 2.2V 58 dB

f = 120Hz, ILOAD = 1A; VIN = 2.2V 72 dB

Output Noise Voltage ILOAD = 1A, BW = 10Hz < f < 100kHz 63 µVRMS

ISL78310

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ENABLE PIN CHARACTERISTICS

Turn-on Threshold 2.2V < VIN < 6V 0.3 0.8 1V

Hysteresis (Rising Threshold) 2.2V < VOUT + 0.4V < 6V 10 80 200 mV

Enable Pin Turn-on Delay COUT = 10µF, ILOAD = 1A 100 µs

Enable Pin Leakage Current VIN = 6V, EN = 3V 1µA

ADJUSTABLE INRUSH CURRENT LIMIT CHARACTERISTICS

Current limit adjust IPD VIN = 3.5V, EN = 0V, SS = 1V 0.5 11.3 mA

ICHG -3.3 -2 -0.8 µA

PG PIN CHARACTERISTICS

VOUT PG Flag Threshold 75 85 92 %VOUT

VOUT PG Flag Hysteresis 4%

PG Flag Low Voltage VIN = 2.5V, ISINK = 500µA 100 mV

PG Flag Leakage Current VIN = 6V, PG = 6V 1µA

NOTES:

11. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

12. Dropout is defined by the difference in supply VIN and VOUT when the supply produces a 2% drop in VOUT from its nominal value.

Electrical Specifications Unless otherwise noted, VIN = VOUT + 0.4V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, ILOAD = 0A.

Applications must follow thermal guidelines of the package to determine worst case junction temperature. Please refer to “ISL78310 Schematic

Block Diagram” on page 4 and Tech Brief TB379. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)

PARAMETER SYMBOL TEST CONDITIONS

MIN

(Note 11) TYP

MAX

(Note 11) UNITS

ISL78310

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Typical Operating Performance

Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A.

FIGURE 3. VOUT vs TEMPERATURE FIGURE 4. VOUT vs SUPPLY VOLTAGE

FIGURE 5. VOUT vs LOAD CURRENT FIGURE 6. GROUND CURRENT vs SUPPLY VOLTAGE

FIGURE 7. GROUND CURRENT vs LOAD CURRENT FIGURE 8. DROPOUT VOLTAGE vs TEMPERATURE

-1.8

-1.2

-0.6

0.6

1.2

1.8

-50-250 255075100125150

JUNCTION TEMPERATURE (°C)

ΔVOUT (%)

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0246

SUPPLY VOLTAGE (V)

VOUT (V)

135

+125°C

+25°C -40°C

-1.8

-1.2

-0.6

0.6

1.2

1.8

00.25 0.50 0.75 1.00

LOAD CURRENT (A)

ΔVOUT (%)

+125°C

+25°C

-40°C

INPUT VOLTAGE (V)

GROUND CURRENT (mA)

356

1.50

1.75

2.00

2.25

2.50

2.75

3.00

3.25

3.50

0 0.25 0.50 0.75 1.00

LOAD CURRENT (A)

GROUND CURRENT (mA)

-40°C

+125°C

+25°C

100

120

140

160

180

200

-40 -25 -10 5 20 35 50 65 80 95 110 125

TEMPERATURE (°C)

DROPOUT VOLTAGE (mV)

VOUT = 2.5V

ILOAD = 1A

ILOAD = 500mA

ILOAD = 100mA

ISL78310

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FIGURE 9. LOAD TRANSIENT RESPONSE

FIGURE 10. ENABLE START-UP

FIGURE 11. PSRR vs FREQUENCY

FIGURE 12. SPECTRAL NOISE DENSITY vs FREQUENCY

Typical Operating Performance

Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A. (Continued)

20µs/DIV

1mA di/dt = 4A/µs

VOLTAGE RAILS AT 50mV/DIV

VIN = 3.7V, VOUT = 3.3V, COUT = 10µF, CPB = 100pF

VIN = 2.9V, VOUT = 2.5V, COUT = 10µF, CPB = 82pF

VIN = 2.5V, VOUT = 1.8V, COUT = 10µF, CPB = 82pF

VIN = 2.5V, VOUT = 1.5V, COUT = 22µF, CPB = 150pF

VIN = 2.5V, VOUT = 1.2V, COUT = 47µF, CPB = 270pF

VIN = 2.5V, VOUT = 1.0V, COUT = 47µF, CPB = 220pF



ENABLE

VOUT (1V/DIV)

SS (1V/DIV)

PG (1V/DIV)

(2V/DIV)

(500µs/DIV)

0mA

100mA

500mA

100 1k 10k 100k 1M

FREQUENCY (Hz)

PSRR (dB)

VIN = 2.5V, VOUT = 1.8V, COUT = 10µF, CPB =82pF

0.001

0.01

0.1

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

ILOAD = 1A

SPECTRAL NOISE DENSITY (µV/√Hz)

ISL78310

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Applications Information

Input Voltage Requirements

ISL78310 is capable of delivering output voltages from 0.8V to

5.0V. Due to the nature of an LDO, VIN must be some margin

higher than the output voltage plus dropout at the maximum

rated current of the application if active filtering (PSRR) is

expected from VIN to VOUT. The generous dropout specification of

this family of LDOs allows applications to design for a level of

efficiency that can accommodate profiles smaller than the

TO220/263.

External Capacitor Requirements

GENERAL GUIDELINE

External capacitors are required for proper operation. Careful

attention must be paid to layout guidelines and selection of

capacitor type and value to ensure optimal performance.

OUTPUT CAPACITOR

The ISL78310 applies state-of-the-art internal compensation to

keep the selection of the output capacitor simple for the

customer. Stable operation over full temperation, VIN range, VOUT

range and load extremes are guaranteed for all capacitor types

and values assuming a minimum of 10µF X5R/X7R is used for

local bypass on VOUT. This output capacitor must be connected to

the VOUT and GND pins of the LDO with PCB traces no longer than

0.5cm. Additional capacitors of any value in ceramic, POSCAP,

alum/tantalum electrolytic types may be placed in parallel to

improve PSRR at higher frequencies and/or load transient AC

output voltage tolerances.

INPUT CAPACITOR

For proper operation, a minimum capacitance of 10µF X5R/X7R

is required at the input. This ceramic input capacitor must be

connected to VIN and GND pins of the LDO with PCB traces no

longer than 0.5cm.

Phase Boost Capacitor (CPB)

A small phase boost capacitor, CPB, can be placed across the top

resistor in the feedback resistor divider network (Figure 13

below) in order to place a zero at:

This zero increases the crossover frequency of the LDO and

provides additional phase resulting in faster load transient

response.

It is also important to note that the LDO stability and load transient

are affected by the type of output capacitor used. For optimal

result, empirical tuning of CPB is suggested for each specific

application. It is recommended to not use CPB when high ESR

capacitors such as Aluminum Electrolytic or Tantalum are used.

Table 1 shows the recommended CPB, RTOP, RBOTTOM and CPB

values for different output voltage rails.

Thermal Fault Protection

In the event the die temperature exceeds typically +160°C, then

the output of the LDO shuts down until the die temperature cools

down to typically +130°C. The level of power, combined with the

thermal resistance of the package (+48°C/W for DFN),

determines whether the junction temperature exceeds the

thermal shutdown temperature specified in the “Electrical

Specifications” table on page 5 (see thermal packaging

guidelines).

(EQ. 1)

FZ12piR

TOP CPB

•••()⁄=

TABLE 1.

VOUT

(V)

RTOP

(kΩ)

RBOTTOM

(Ω)

CPB

(pF)

COUT

(µF)

5.0 2.61 287 100 10

3.3 2.61 464 100 10

2.5 2.61 649 82 10

1.8 2.61 1.0k 82 10

1.5* 2.61 1.3k 68 10

1.5 2.61 1.3k 150 22

1.2* 2.61 1.87k 120 22

1.2* 2.61 1.87k 270 47

1.0 2.61 2.61k 220 47

0.8 2.61 4.32k 220 47

*Either option could be used, depending on cost/performance

requirements.

ISL78310

CIN

RTOP

RBOTTOM

CPB

VIN VOUT

COUT

ADJ

FIGURE 13.

ISL78310

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Current Limit Protection

The ISL78310 LDO incorporates protection against overcurrent

due to any short or overload condition applied to the output pin.

The current limit circuit performs as a constant current source

when the output current exceeds the current limit threshold

noted in the “Electrical Specifications” table on page 5. If the

short or overload condition is removed from VOUT, then the

output returns to normal voltage mode regulation. In the event of

an overload condition on the DFN package, the LDO will begin to

cycle on and off due to the die temperature exceeding thermal

fault condition.

Functional Description

Enable Operation

The Enable turn-on threshold is typically 0.8V with a hysteresis of

80mV. The Enable pin does not have an internal pull-up or

pull-down resistor. As a result, this pin must not be left floating.

This pin must be tied to VIN if it is not used. A pull-up resistor

(typically 1kΩ to 10kΩ) will be required for applications that use

open collector or open drain outputs to control the Enable pin.

The Enable pin may be connected directly to VIN for applications

that are always on.

Soft-Start Operation

The soft-start circuit controls the rate at which the output voltage

rises up to regulation at power-up or LDO enable. This start-up

ramp time can be set by adding an external capacitor from the

SS pin to GND. An internal 2µA current source charges up this

CSS and the feedback reference voltage is clamped to the

voltage across it. The startup time of the regulator output voltage

for a given CSS value can be calculated using Equation 2.

The soft-start function also effectively limits the amount of in-

rush current to less than the programmed current limit during

start-up or an enable sequence, to avoid an over current fault

condition. This can be an issue for applications that require large,

external bulk capacitances on VOUT where high levels of charging

current can be seen for a significant period of time. High in-rush

currents can cause VIN to drop below minimum, which could

cause VOUT to shutdown.

tRAMP

CSSx0.5V

2μA

-------------------------

=(EQ. 2)

FIGURE 14. IN-RUSH CURRENT WITH NO CSS,

COUT = 1000µF, IN-RUSH CURRENT = 1.8A

FIGURE 15. IN-RUSH CURRENT WITH CSS = 15nF, COUT = 1000µF,

IN-RUSH CURRENT = 0.5A

FIGURE 16. IN-RUSH CURRENT WITH CSS = 33nF, COUT = 1000µF, IN-RUSH CURRENT = 0.2A

ISL78310

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Equation 3 can be used to calculate CSS for a desired in-rush

current, where VOUT is the output voltage, COUT is the total

capacitance on the output, and IINRUSH is the desired in-rush

current.

The scopes in Figure 14 to 33 capture the response for the soft-

start function. The output voltage is set to 1.8V.

The external capacitor is always discharged to ground at the

beginning of start-up or enabling.

Power-Good Operation

The PGOOD is a logic output that indicates the status of VOUT.

The PGOOD flag is an open-drain NMOS that can sink 10mA

during a fault condition. The PGOOD pin requires an external pull-

up resistor, which is typically connected to the VOUT pin. The

PGOOD pin should not be pulled up to a voltage source greater

than VIN. PGOOD goes low when the output voltage drops below

84% of the nominal output voltage or if the part is disabled. The

PGOOD comparator fuctions during current limit and thermal

shutdown. For applications not using this feature, connect this

pin to ground.

Output Voltage Selection

An external resistor divider is used to scale the output voltage

relative to the internal reference voltage. This voltage is then fed

back to the error amplifier. The output voltage can be

programmed to any level between 0.8V and 5V. An external

resistor divider, R1 and R2, is used to set the output voltage as

shown in Equation 4. The recommended value for R2 is 500Ω to

1kΩ. R1 is then chosen according to Equation 5.

Power Dissipation

The junction temperature must not exceed the range specified in

the “Recommended Operating Conditions” on page 5. The power

dissipation can be calculated by using Equation 6:

The maximum allowed junction temperature, TJ(MAX), and the

maximum expected ambient temperature, TA(MAX), will

determine the maximum allowable power dissipation, as shown

in Equation 7:

θJA is the junction-to-ambient thermal resistance.

For safe operation, ensure that the power disspiation PD,

calculated from Equation 6, is less than the maximum allowable

power dissipation PD(MAX).

Heatsinking the DFN Package

The DFN package uses the copper area on the PCB as a heat-sink.

The EPAD of this package must be soldered to the copper plane

(GND plane) for heat sinking. Figure 17 shows a curve for the θJA of

the DFN package for different copper area sizes.

General PowerPAD Design

Considerations

Figure 18 shows the recommended use of vias on the thermal

pad to remove heat from the IC. This typical array populates the

thermal pad footprint with vias spaced three times the radius

distance from the center of each via. Small via size is advisable,

but not to the extent that solder reflow becomes difficult.

All vias should be connected to the pad potential, with low

thermal resistance for efficient heat transfer. Complete

connection of the plated-through hole to each plane is important.

It is not recommended to use “thermal relief” patterns to connect

the vias.

CSS

VOUTxCOUTx2μA()

IINRUSHx0.5V

--------------------------------------------------

=(EQ. 3)

VOUT 0.5V

-------1+

⎝⎠

⎜⎟

⎛⎞

×=(EQ. 4)

R1R2

VOUT

0.5V

-------------1–

⎝⎠

⎛⎞

×=(EQ. 5)

PDVIN VOUT

–()IOUT VIN IGND

×+×=(EQ. 6)

PDMAX()TJMAX()

–()θ

⁄=(EQ. 7)

FIGURE 17. 3mmx3mm 10 LD DFN ON 4-LAYER PCB WITH

THERMAL VIAS θJA vs EPAD-MOUNT COPPER LAND

AREA ON PCB

(°C/W)

2 4 6 8 10 12 14 16 18 20 22 24

EPAD-MOUNT COPPER LAND AREA ON PCB, mm2



FIGURE 18. PCB VIA PATTERN

ISL78310

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7810.0

February 17, 2011

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Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make

sure you have the latest Rev.

DATE REVISION CHANGE

2/17/11 FN7810.0 Initial Release.

ISL78310

13 FN7810.0

February 17, 2011

Package Outline Drawing

L10.3x3

10 LEAD DUAL FLAT PACKAGE (DFN)

Rev 6, 09/09

located within the zone indicated. The pin #1 indentifier may be

Unless otherwise specified, tolerance : Decimal ± 0.05

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

between 0.18mm and 0.30mm from the terminal tip.

Lead width applies to the metallized terminal and is measured

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

either a mold or mark feature.

Dimensions are in millimeters.1.

NOTES:

BOTTOM VIEW

DETAIL "X"

SIDE VIEW

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

(4X) 0.10

INDEX AREA

PIN 1

PIN #1 INDEX AREA

SEATING PLANE

BASE PLANE

0.08

SEE DETAIL "X"

0.10 C

PACKAGE

1.00

0.20

8x 0.50

2.00

3.00

(10x 0.23)

(8x 0.50)

2.00

1.60

(10 x 0.55)

3.00

0.05

0.20 REF

10 x 0.23

10x 0.35

1.60

OUTLINE

MAX

(4X) 0.10 AB

0.415

0.23

0.35

0.200