TOSHIBA
Toshiba TC86R4400
MIPS RISC High Performance
Microprocessor
Product Brief
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC
.
1
Toshiba is the leading silicon vendor licensed to develop, manu-
facture and sell MIPS
â
Reduced Instruction Set Computing
(RISC)-based products. ToshibaÕs R4400-based systems will run
a choice of advanced operating systems, such as UNIX
â
and
Windows NT
ä
from Microsoft Corporation.
Toshiba is the key supplier of MIPS Reduced Instruction Set
Computing (RISC) technology for the computer system and
embedded control markets. From the introduction of the
R2000
ä
, Toshiba has been a foundry for MIPS RISC-based
products. Since then, the R3000, R4000 and R4400 processors
have been gaining wide acceptance and have been designed into a
variety of products by industry-leading companies.
In 1991, Toshiba delivered one of the Þrst R4000 compo-
nents, displaying its strength in advanced process technology
applied to high-end microprocessors. With a leading combination
of highest overall performance, 64-bit architecture and design
ßexibility, ToshibaÕs R4400 establishes the standard for RISC
microprocessors through the end of this decade.
R4400 Performance
The single-chip R4400 delivers the high performance necessary
for a wide range of applications while maintaining full software
compatibility with previous generations of MIPS microproces-
sors. Its scalable performance makes it possible to design the
R4400 into applications ranging from embedded controllers, such
as those in satellites and telephone switches, to computers rang-
ing from laptops to mainframe-class servers. In designing the
R4400, the basic components of the central CPU subsystem,
including integer processor, ßoating point co-processor, memory
management unit and primary cache, were integrated onto a sin-
gle chip. In addition, the R4400 includes full multiprocessing
capabilities, superpipelining, and control and management facili-
ties for external secondary cache.
The R4400 is offered in two variants tailored for multiple
price/performance points:
¥ The R4400SC supports high-performance uniprocessor
designs with secondary cache
¥ The R4400MC is the full multiprocessing version of the prod-
uct and supports both secondary cache and cache coherence
mechanisms necessary for synchronizing multiple processors
The R4400 family provides a balanced mix in integer and
ßoating point performance. Through superpipelining, RISC opti-
mization techniques and on-chip integration, high integer perfor-
mance is achieved for applications such as databases, graphics,
spreadsheets and word processing. Superpipelining increases
throughput by putting more instructions into the pipeline at the
same time. RISC optimization techniques streamline processing
operations by minimizing interruptions to the steady progress of
the pipeline. In addition, on-chip integration takes more function-
ality off the board and puts it directly onto the processor to
shorten paths and reduce lengthy accesses to main memory.
In the R4400 design, superpipelining requires less circuitry
than other multiple-instruction issue techniques, so it leaves more
room on the chip for other functions. Further, superpipelining
provides greater integer processing than most other techniques
whose beneÞts are conÞned mainly to ßoating-point operations.
This results in higher overall performance from integer and ßoat-
ing-point units, a desirable characteristic in a microprocessor that
is to have broad-based acceptance and applications.
The R4400 takes advantage of optimization techniques built
into the MIPS compiler software to run applications faster than
other RISC processors at similar or higher clock speeds. With
RISC, the microprocessor design is streamlined by eliminating
less frequently used instructions and circuitry, shifting the bal-
ance of computing from hardware to compiler software. Compil-
ers offered by MIPS have been simultaneously developed and
integrated with the R4400 from the start to deliver maximum per-
formance.
Table 1. TC86R4400SC/MC Options
Internal Frequency External Frequency Voltage Temperature Internal Cache Package (PGA)
150 MHz 75 MHz 3.3V 70
°
C 16KI + 16KD 447-pin
175 MHz 87 MHz 3.3V 70
°
C 16KI + 16 KD 447-pin
200 MHz 100 MHz 3.3V 70
°
C 16KI + 16 KD 447-pin
200 MHz 100 MHz 3.3V 85
°
C 16KI + 16 KD 447-pin
200 MHz 100 MHz 3.45V 70
°
C 16KI + 16 KD 447-pin
250 MHz 125 MHz 3.45V 70
°
C 16KI + 16 KD 447-pin
TC86R4400 MIPS RISC Microprocessor
2
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC
.
R4400SC Microprocessor
ToshibaÕs R4400SC 64-bit microprocessor and an advanced
operating system, like Windows NT
ä,
gives the designer the
ability to address new expectations in the mainstream system
and high-end server/workstation market at unbeatable price/
performance points. R4400SC-based systems can run a choice
of advanced operating systems, such as Windows NT and UNIX
â
which protect end user software investments while also providing
an open software environment, are two important achievements
for Toshiba in meeting the mainstream and high-end PC market
needs. The R4400SC operates from 150MHz (input clock 75
MHz) to 250MHz (input clock 125MHz), and can sustain
performance in excess of 175SPECint92.
R4400SC Overview
ToshibaÕs R4400SC is a highly integrated, single-chip RISC
microprocessor designed for high-performance uniprocessor sys-
tems with secondary cache support. The R4400SC provides com-
plete application software compatibility with the MIPS R2000,
R3000, R4000, and R8000 processors. High integer performance,
as well as ßoating-point performance, has been achieved through
a number of techniques such as superpipelining, on-chip data and
instruction caches, a pipelined ßoating point unit, support for two
level cache memory and a high-performance on-chip TLB. The
R4400SC provides a compatible, timely and necessary path from
32-bit to true 64-bit computing for users and software developers.
R4400SC Features
¥ True 64-bit microprocessor with 64-bit integer and floating-
point operations, registers and virtual addresses
¥ Fully compatible with earlier 32-bit MIPS microprocessor.
¥ Dual instruction issue with no restrictions on the type of
instruction issued
¥On-chip Memory Management Unit (MMU) containing a fully
associative TLB whose entries have a variable page size rang-
ing from 4Kbyte to 16Mbyte
¥ On-chip ANSI/IEEE-754 standard floating-point unit with
precise exceptions
¥ 32 doubleword (64-bit) general-purpose registers and 32
doubleword floating-point registers
¥ 36-bit physical address accessing 64GB of physical
memory
¥ Built in primary direct mapped caches with parity protection:
Ð 16KB instruction cache
Ð 16KB data cache
Ð Buffered write back with ConÞgurable 4 or 8 word
line size
¥ R4400SC also has built-in direct mapped secondary cache
support:
Ð The secondary cache can range from 128Kbytes to
4Mbytes
Ð 128-bit interface to minimize cache miss latency
Ð Timing ßexibility for 128-bit secondary cache interface
Ð ECC protection
¥ 64-bit system interface to allow speed matching of logic and
memory components
¥ Dynamically configurable big-endian or little-endian byte
ordering
In order to achieve the high performance required in a third
generation RISC design, the TC86R4400SC exploits instruction-
level parallelism using a superpipelined micro-instruction. The
TC86R4400SC implements an 8-stage superpipeline which
places no restrictions on instruction issue. Any two instructions
can be issued each cycle under normal circumstances. Since the
superpipeline places no restrictions on the order of instruction
issue, the full beneÞt of the TC86R4400SC can be realized by
existing application programs without any need for recompila-
tion. The internal pipeline of the TC86R4400SC operates at fre-
quency from 150MHz to 200MHz, which is twice the external
clock frequency.
R4400MC Microprocessor
TC86R4400MC-based multiprocessor computer systems
can run a choice of advanced operating systems, such as
Windows NT, UNIX and Univel. Protecting the end user soft-
ware investments and also providing an open software environ-
ment are two important achievements in meeting the high-end
market needs. The TC86R4400MC operates at frequencies from
150MHz internal (external clock 75MHz) to 250MHz internal
(125MHz external), and can sustain performance in excess of
175SPECint92.
R4400MC Overview
Toshiba R4400MC is a highly integrated, single-chip RISC
microprocessor designed for high-performance multiprocessing
systems. The R4400MC provides complete application-software
compatibility with the MIPS R2000, R3000, R4400 and R8000
processors. High integer performance, as well as ßoating-point
performance, has been achieved through a number of techniques
such as superpipelining, on-chip data and instruction caches, a
pipelined ßoating point unit, support for two level cache memory
and a high-performance on-chip TLB. The R4400MC provides a
compatible, timely and necessary path from 32-bit to true 64-bit
computing for users and software developers.
R4400SC/MC Multiprocessor
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC
.
3
R4400MC Features
¥ True 64-bit microprocessor with 64-bit integer and floating-
point operations, registers and virtual addresses
¥ Fully compatible with earlier 32-bit MIPS microprocessors
¥ Dual instruction issue with no restrictions on the type of
instruction issued
¥ Built-in support for multiprocessing
¥On-chip Memory Management Unit (MMU) containing a fully
associative TLB whose entries have a variable page size rang-
ing from 4KB to 16MB
¥ On-chip ANSI/IEEE-754 standard floating-point unit with
precise exceptions
¥ 32 doubleword (64-bit) general-purpose registers and 32
doubleword floating-point registers
¥ 36-bit physical address accessing 64GB of physical
memory
¥ Built-in primary direct mapped caches with parity protection:
Ð 16KB instruction cache
Ð 16KB data cache
Ð Buffered write back with conÞgurable 4 or 8 word line
size
¥ Built-in direct mapped secondary cache support:
Ð The secondary cache can range from 128KB to 4MB
Ð 128-bit interface to minimize cache miss latency
Ð Timing ßexibility for 128-bit secondary cache interface
Ð 64-bit system interface to allow speed matching of logic
and memory components with multiprocessing support
Ð ECC protection
¥ Dynamically configurable big-endian or little-endian byte
ordering
Figure 1. R4400 Block Diagram
Figure 2. R4400MC System Block Diagram
External
Secondary
Cache
RAMs
128 Data
64 Data
Secondary Cache Bus Data, Tag, Addr, Control
64-bit DBus 64-bit IBus
System Bus
Integer
Unit
Memory Management Unit
System Coprocessor 0
(CP0)
Floating Point Unit
Item Coprocessor 1
(CP1)
16K Primary
Data
Cache
16K Primary
Instruction
Cache
Decode Tag Decode Tag
FP Register File
FP Pipeline/Bypass
FP Status Register
FP Multiply
FP Divide
FP Add, Convert,
Square Root
Primary
Cache
Control
System
Secondary
Cache
Control
Pipeline
Control
ALU
Exception/Control Registers
Translation Lookside Buffer
(96 entries, software managed)
Memory Management Unit Registers
Address Unit
PC Incrementer
Register File
Integer Multiply/Divide
Load Aligner
Store Driver
TC86R4400 MIPS RISC Microprocessor
TOSHIBA
ã
1995 Toshiba America Electronic Components, Inc.
Toshiba products described in this document are not authorized for use as critical components in life support systems without the written consent of the appropriate
ofÞcer of Toshiba America, Inc. Life support systems are either systems intended for surgical implant in the body or systems which sustain life. A critical component is
any component of a life support system whose failure to perform may cause a malfunction or failure of the life support system, or may affect its safety or effectiveness.
SpeciÞcations and information herein are subject to change without notice.
This technical data may be controlled under U.S. Export Administration Regulations and may be subject to the approval of the U.S. Department of Commerce prior to
export. Any export or re-export, directly or indirectly, in contravention of the U.S. Export Administration Regulations is strictly prohibited.
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Figure 3. R4400SC System Block Diagram
Multiprocessor Bus
Interface
Component Interface
Component
Interface
Component
System
Memory
I/O
Controller I/O
Controller
R4400MC R4400MC
L2 Cache L2 Cache
64
64 64
128 128
64 64
128 64 64
I/O Bus I/O Bus
R4400SC
SRAM DRAM DRAM
Memory
& I/O
Controller
Data Data
Control
Address
128-bit
Data Tag,
Addrs
Control
(64 + 8)
Address/Data
Command Bus (9-bits)
SCSI ENET
System I/O Bus
Buffer Buffer
RSC-1156/8-95