Integrated
Circuit
Systems, Inc.
ICS93V857-XXX
0693K—03/13/03
1
Block Diagram
2.5V Wide Range Frequency Clock Driver (33MHz - 233MHz)
Pin Configuration
48-Pin TSSOP & TVSOP
Recommended Application:
• DDR Memory Modules / Zero Delay Board Fan Out
• Provides complete DDR DIMM logic solution with
ICSSSTV16857, ICSSSTV16859 or ICSSSTV32852
Product Description/Features:
• Low sk ew, low jitter PLL cloc k driv er
• 1 to 10 differential clock distribution (SSTL_2)
• Feedback pins for input to output synchronization
• PD# for power management
• Spread Spectrum tolerant inputs
• Auto PD when input signal removed
• Choice of static phase offset available,
for easy board tuning;
-XXX = device pattern number for options listed
below.
- ICS93V857-025 ...... 0ps
- ICS93V857-125 +125ps
- ICS93V857-130 .. +40ps
Switching Characteristics:
• Period jitter (>66MHz): <40ps
• CYCLE - CYCLE jitter (66MHz): <120ps
• CYCLE - CYCLE jitter (>100MHz): <65ps
• OUTPUT - OUTPUT skew: <60ps
• Output Rise and F all Time: 650ps - 950ps
• DUTY CYCLE: 49.5% - 50.5%
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
GND
CLKC2
CLKT2
VDD
VDD
CLK_INT
CLK_INC
VDD
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
GND
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
GND
CLKC7
CLKT7
VDD
PD#
FB_INT
FB_INC
VDD
FB_OUTC
FB_OUTT
GND
CLKC8
CLKT8
VDD
CLKT9
CLKC9
GND
ICS93V857-025/125/130
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
STUPNISTUPTUO etatSLLP
DDVA#DPTNI_KLCCNI_KLCTKLCCKLCTTUO_BFCTUO_BF
DNGH L H LH L H ffo/dessapyB
DNGH H L HL H L ffo/dessapyB
V5.2 )mon( LL HZZZ Z ffo
V5.2 )mon( LH LZZZ Z ffo
V5.2 )mon( HL HLHL H no
V5.2 )mon( HH LHLH L no
V5.2 )mon( X)zHM02<
)1(
ZZ Z Z ffo
Functionality
PLL
FB_INT
FB_INC
CLK_INC
CLK_INT
PD# Control
Logic
FB_OUTT
FB_OUTC
CLKT0
CLKT1
CLKT2
CLKT3
CLKT4
CLKT5
CLKT6
CLKT7
CLKT8
CLKT9
CLKC0
CLKC1
CLKC2
CLKC3
CLKC4
CLKC5
CLKC6
CLKC7
CLKC8
CLKC9
6.10 mm. Body, 0.50 mm. pitch = TSSOP
4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP)
2
ICS93V857-XXX
0693K—03/13/03
Pin Descriptions
REBMUNNIPEMANNIPEPYTNOITPIRCSED
,12,51,21,11,4 ,54,83,43,82 DDVRWPV5.2ylppusrewoP
,52,42,81,8,7,1 84,24,14,13 DNGRWPdnuorG
61DDVARWPV5.2,ylppusrewopgolanA
71DNGARWP.dnuorggolanA
,64,44,93,92,72 3,5,01,02,22 )0:9(TKLCTUO.stuptuoriaplaitnereffidfokcolC"eurT"
,74,34,04,03,62 2,6,9,91,32 )0:9(CKLCTUO.stuptuoriaplaitnereffidfoskcolc"yratnemelpmoC"
41CNI_KLCNItupnikcolcecnerefer"yratnemelpmoC"
31TNI_KLCNItupnikcolcecnerefer"eurT"
33CTUO_BFTUO tI.kcabdeeflanretxerofdetacided,tuptuokcabdeeF"yratnemelpmoC" deriwebtsumtuptuosihT.KLCehtsaycneuqerfemasehttasehctiws .CNI_BFot
23TTUO_BFTUO sehctiwstI.kcabdeeflanretxerofdetacided,tuptuokcabdeeF""eurT" otderiwebtsumtuptuosihT.KLCehtsaycneuqerfemasehtta .TNI_BF
63TNI_BFNIrofLLPlanretniehtotlangiskcabdeefsedivorp,tupnikcabdeeF"eurT" .rorreesahpetanimileotTNI_KLChtiwnoitazinorhcnys
53CNI_BFNILLPlanretniehtotlangissedivorp,tupnikcabdeeF"yratnemelpmoC" .rorreesahpetanimileotCNI_KLChtiwnoitazinorhcnysrof
73#DPNItupniSOMCVL.nwoDrewoP
This PLL Clock Buffer is designed for a VDD of 2.5V, AVDD of 2.5V and differential data input and output lev els .
ICS93V857-XXX is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten
differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT,
FB_OUTC). The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT,
FB_INC), the 2.5-V L VCMOS input (PD#) and the Analog P ower input (A VDD). When input (PD#) is low while power is
applied, the receivers are disabled, the PLL is turned off and the differential clock outputs are T ri-Stated. When A VDD
is grounded, the PLL is turned off and bypassed for test purposes.
When the input frequency is less than the operating frequency of the PLL, appproximately 20MHz, the device will enter
a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers,
will detect the low frequency condition and perform the same low power features as when the (PD#) input is low. When
the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and
outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input
clock pair (CLK_INC, CLK_INT).
The PLL in ICS93V857-XXX clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT [0:9], CLKC [0:9]).
ICS93V857-XXX is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
ICS93V857-XXX is characterized for operation from 0°C to 85°C.
3
ICS93V857-XXX
0693K—03/13/03
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD). . . . . . . . . . . -0.5V to 4.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.5V to VDD + 0.5V
Ambient Operating Temperature . . . . . . . . . . 0°C to +85°C
Storage Temperature. . . . . . . . . . . . . . . . . . . -65°C to +150°C
Stresses abov e those listed under
Absolute Maximum Ratings
ma y cause permanent damage to the device . These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
f or e xtended periods may aff ect product reliability.
Elect r i cal Character i st i cs - I nput/Suppl y/ Comm on O ut put Param et ers
TA = 0 - 85C; Supply V ol t age A V DD, V DD = 2. 5 V +/ - 0. 2V (unless ot herwise s t ated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I nput High Current I IH VI = VDD or GND 5 µA
Input Low Current IIL VI = VDD or GND 5 µA
IDD2.5 CL = 0pf @ 100MHz 250 mA
IDDPD CL = 0pf 65 90 mA
I nput Clamp Volt age V IK VDDQ = 2.3V Iin = -18mA -1.2 V
IOH = -1 mA VDD - 0.1 2.45 V
IOH = -12 mA 1.7 2.10 V
IOL=1 mA 0. 05 0. 1 V
IOL=12 mA 0. 35 0. 6 V
I nput Capac i t ance1CIN VI = GND or V DD 3pF
Out put Capac i tanc e1COUT VOUT = G ND o r VDD 3pF
1Guarant eed b
y
desi
g
n at 233M Hz , not 100% t est ed in product ion.
Operat ing S uppl y
Current
High-level output
voltage VOH
Low-level output v ol tage V OL
4
ICS93V857-XXX
0693K—03/13/03
Recomm ended Operat i n
g
Condi t ion
(
see not e1
)
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2. 5 V +/- 0.2V (unl ess otherwise stat ed)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
S uppl y Voltage V DDQ, AVDD 2.3 2.5 2.7 V
CLK_ I NT, CL K _ INC, F B _ I N C,
FB_INT 0.4 VDD/2 - 0.18 V
PD# -0.3 0.7 V
CLK_ I NT, CL K _ INC, F B _ I N C,
FB_INT VDD/2 + 0. 18 2. 1 V
PD# 1.7 VDD + 0.6 V
DC input signal vol t age
(note 2) VIN -0.3 VDD + 0.3 V
DC - C L K_INT , CL K_INC ,
FB _INC, FB _INT 0.36 VDD + 0.6 V
AC - CLK_INT, CLK_INC,
FB _INC, FB _INT 0.7 VDD + 0.6 V
Out put di f f erent i al c ross -
v ol t age (not e 4) VOX VDD/ 2 - 0. 15 V DD/2 + 0.15 V
Input di fferent i al cross-
v ol t age (not e 4) VIX VDD/2 - 0.2 VDD/2 VDD/2 + 0. 2 V
High l evel output current I OH -12 mA
Low l evel output current I OL 12 mA
High Im pedanc e
Out put Current IOZ VDD=2.7V, VOUT=VDD or GND 0. 1 ± 10 m A
Operat i ng f ree-ai r
temperature TA085°C
Diff erent i al input s i gnal
voltage (note 3) VID
Low l evel i nput vol tage V IL
High l evel i nput vol t age V IH
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required f or s witching, where VTR is the true input lev el and VCP is the
complementary input level.
4. Diff erential cross-point v oltage is expected to track v ariations of V DD and is the
voltage at which the differential signal must be crossing.
5
ICS93V857-XXX
0693K—03/13/03
Notes:
1. Ref ers to transition on noninv erting output in PLL bypass mode .
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the f ormula: duty cycle=twH/tc, were
the cycle (tc) decreases as the frequency goes up.
3 . Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
Ti ming Re quir em e nt s
TA = 0 - 85C; Supply V ol t age A V DD, V DD = 2. 5 V +/ - 0. 2V (unless ot herwise s t ated)
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
M ax cl oc k f requenc y3freqop 2.5V+0.2V 33 233 MHz
A ppli cat i on Frequenc y
Range3freqApp 2.5V+0.2V 60 170 MHz
Input clock duty cycle dtin 40 60 %
CLK s tabiliz ation TSTAB 100 µs
Swi t chi ng Character i st i cs
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS
Low-t o hi gh level
propa
g
ation de l a
y
time tPLH1CLK _IN t o any output 5. 5 ns
High-t o l ow lev el propagati on
delay t i m e tPHL1CLK_IN t o any output 5. 5 ns
Output enabl e tim e t en P D# t o any out put 5 ns
Output disable tim e tdis P D# t o any output 5 ns
Period jitter t
j
it
(p
er
)
66/100/125/133/167MHz -40 40 ps
100 t o < 170M Hz -100 100 ps
≥170MHz to 233MHz -120 50 ps
Input clock slew rate tsl
(
I
)
14v/ns
Output clock slew rate tsl
(
o
)
66/100/133/167MHz 1 2 v/ns
Cycle to Cy cle Jitter1tc
c-tc
c66/100/125/133/167MHz 60 ps
P has e error t
(p
has e error
)
4-50 0 50 ps
Out put to O ut put Sk ew t skew 40 60 ps
Ri s e Time, Fall Time tr, tfLoad = 120Ω/16pF 650 800 950 ps
tjit(hper)
Half-period jit ter
6
ICS93V857-XXX
0693K—03/13/03
GND
ICS93V857
VDD
VDD /2
V(CLKC)
V(CLKC)
SCOPE
C=14pF
-VDD/2
-VDD/2
-VDD/2
VDD/2
Z=60Ω
Z=60Ω
Z=50Ω
Z=50Ω
R=10Ω
R=10Ω
R=50Ω
R=60Ω
R=60Ω
R=50Ω
V(TT)
V(TT)
C=14pF
NOTE: V(TT) =GND
tc(n) tc(n+1)
tjit(cc) =t
c(n)±t
c(n+1)
Figure 1. IBIS Model Output Load
Figure 2. Output Load Test Circuit
Y , FB_OUTC
X
Y , FB_OUTT
X
Parameter Measurement Information
ICS93V857
Figure 3. Cycle-to-Cycle Jitter
7
ICS93V857-XXX
0693K—03/13/03
(N is a large number of samples)
t
( ) n+1
t
()n
t
()
=1
n=N
t
()n
N
CLK_INC
CLK_INT
FB_INC
FB_INT
t(skew)
Y#
X
Y , FB_OUTC
X
Y , FB_OUTT
X
Y , FB_OUTC
X
Y , FB_OUTT
X
Y , FB_OUTC
X
Y , FB_OUTT
X
YX
Parameter Measurement Information
Figure 4. Static Phase Offset
Figure 5. Output Skew
1
fO
t=
t
-
(jit_per) tc(n)
C(n)
1
fO
Figure 6. Period Jitter
8
ICS93V857-XXX
0693K—03/13/03
Clock Inputs
and Outputs
80%
20%
80%
20%
tslr tslf
VID,V
OD
Figure 8. Input and Output Slew Rates
Parameter Measurement Information
tjit(hper_n) tjit(hper_n+1)
1
fo
Y , FB_OUTC
X
Y , FB_OUTT
X
Figure 7. Half-Period Jitter
tjit(hper) tjit(hper_n) 1
2xfO
=-
9
ICS93V857-XXX
0693K—03/13/03
Ordering Information
ICS93V857yG-025T ICS93V857yG-125T ICS93V857yG-130T
Designation for tape and reel packaging
Pattern Number
Packag e Ty pe
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
Example:
ICS XXXX y G - PPP - T
INDEX
AREA
INDEX
AREA
12
1 2
N
D
E1 E
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
-C-
- C -
b
c
L
aaa
C
6.10 mm. Body, 0.50 mm. pitch TSSOP
(240 mil) (0.020 mil)
MIN MAX MIN MAX
A -- 1.20 -- .047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.17 0.27 .007 .011
c 0.09 0.20 .0035 .008
D
E
E1 6.00 6.20 .236 .244
e
L 0.45 0.75 .018 .030
N
α0° 8° 0° 8°
aaa -- 0.10 -- .004
VARIATIONS
MIN MAX MIN MAX
48 12.40 12.60 .488 .496
10-0039
ND m m. D (inch)
Re fe rence Doc. : JEDE C Publica tion 95, MO -153
0.50 BASIC 0.020 BASIC
SEE VARIATIONS SEE VARIATIONS
SEE VARIATIONS SEE VARIATIONS
8.10 BASIC 0.319 BASIC
SYMBOL In Millimeters In Inches
COMMON DIMENSIONS COM MON DIM ENS IONS
Choice of static phase offset available, for easy board tuning;
-XXX = de vice pattern number f or options listed below.
- ICS93V857-025 ...... 0ps
- ICS93V857-125 +125ps
- ICS93V857-130 .. +40ps
10
ICS93V857-XXX
0693K—03/13/03
Designation for tape and reel packaging
Pattern Number
Package Type
L=TSSOP (TVSOP)
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit number s)
Prefix
ICS = Standard Device
Example:
ICS XXXX y L - PPP - T
INDEX
AREA
INDEX
AREA
12
1 2
N
D
E1 E
α
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
-C-
- C -
b
c
L
aaa
C
Ordering Information
ICS93V857yL-025T ICS93V857yL-125T ICS93V857yL-130T
MIN MAX MIN MAX
A -- 1.20 -- .047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.13 0.23 .005 .009
c 0.09 0.20 .0035 .008
D
E
E1 4.30 4.50 .169 .177
e
L 0.45 0.75 .018 .030
N
α0° 8° 0° 8°
aaa -- 0.08 -- .003
VARIATIONS
MIN MAX MIN MAX
48 9.60 9.80 .378 .386
10-0037
SYMBOL In Millimet ers In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
SEE VARIATIO NS SEE VARIATIO NS
6.40 BASIC 0.252 BASIC
0.40 BASIC 0.016 BASIC
SEE VARIATIO NS SEE VARIATIO NS
ND mm. D (inch)
Reference Doc.: JEDEC Publicati on 95, MO-153
4.40 mm. Body, 0.40 mm. pitch TSSOP
(173 mil) (16 mil)
Choice of static phase offset available, for easy board tuning;
-XXX = de vice pattern number f or options listed belo w .
- ICS93V857-025 ...... 0ps
- ICS93V857-125 +125ps
- ICS93V857-130 .. +40ps