IS61LV3216
Integrated Circuit Solution Inc. 1
SR009-0B
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FEATURES
• High-speed access time: 10, 12, 15, and 20 ns
• CMOS low power operation
— 150 mW (typical) operating
— 150 µW (typical) standby
• TTL compatible interface levels
• Single 3.3V ± 10% power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Industrial temperature available
• Available in 44-pin 400mil SOJ package and
44-pin TSOP-2
IS61LV3216
32K x 16 LOW VOLTAGE CMOS STATIC RAM
DESCRIPTION
The ICSI IS61LV3216 is a high-speed, 512K static RAM
organized as 32,768 words by 16 bits. It is fabricated using
ICSI's high-performance CMOS technology. This highly reli-
able process coupled with innovative circuit design techniques,
yields fast access times with low power consumption.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable and
Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS61LV3216 is packaged in the JEDEC standard 44-pin
400mil SOJ and 44-pin 400mil TSOP-2.
FUNCTIONAL BLOCK DIAGRAM
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 1997, Integrated Silicon Solution Inc.
A0-A14
CE
OE
WE
32K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
IS61LV3216
2Integrated Circuit Solution Inc.
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PIN CONFIGURATIONS
44-Pin SOJ
PIN DESCRIPTIONS
A0-A14 Address Inputs
I/O0-I/O15 Data Inputs/Outputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
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44
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39
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27
26
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NC
A14
A13
A12
A11
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A10
A9
A8
A7
NC
A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
NC
TRUTH TABLE
I/O PIN
Mode WEWE
WEWE
WE CECE
CECE
CE OEOE
OEOE
OE LBLB
LBLB
LB UBUB
UBUB
UB I/O0-I/O7 I/O8-I/O15 Vcc Current
Not Selected X H X X X High-Z High-Z ISB1, ISB2
Output Disabled H L H X X High-Z High-Z ICC
X L X H H High-Z High-Z
Read H L L L H DOUT High-Z ICC
H L L H L High-Z DOUT
HLLLL DOUT DOUT
Write L L X L H DIN High-Z ICC
L L X H L High-Z DIN
LLXLL DIN DIN
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NC
A14
A13
A12
A11
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A10
A9
A8
A7
NC
A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
NC
44-Pin TSOP-2
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)
NC No Connection
Vcc Power
GND Ground
IS61LV3216
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OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 3.3V ± 10%
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-10 ns -12 ns -15 ns -20 ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit
ICC Vcc Dynamic Operating VCC = Max., Com. — 220 — 200 — 180 — 160 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — — — 230 — 200 — 180
ISB1TTL Standby Current VCC = Max., Com. — 10 — 10 — 10 — 10 mA
(TTL Inputs) VIN = VIH or VIL Ind. — — — 20 — 20 — 20
CE
≥
VIH , f = 0
ISB2CMOS Standby VCC = Max., Com. — 5 — 5 — 5 — 5 mA
Current (CMOS Inputs) CE
≥
VCC – 0.2V, Ind. — — — 10 — 10 — 10
VIN
≥
VCC – 0.2V, or
VIN
≤
0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.3 V
VIL Input LOW Voltage(1) –0.3 0.8 V
ILI Input Leakage GND ≤ VIN ≤ VCC –2 2 µA
ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled –2 2 µA
Notes:
1. VIL (min.) = –3.0V for pulse width less than 10 ns.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VCC Supply Voltage with Respect to GND –0.5 to +4.6 V
VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.5 V
TSTG Storage Temperature –65 to +150 °C
PTPower Dissipation 1.0 W
IOUT DC Output Current (LOW) 20 mA
Note:
1. Stress greater than those listed under
ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the
device. This is a stress rating only and
functional operation of the device at
these or any other conditions above
those indicated in the operational sec-
tions of this specification is not implied.
Exposure to absolute maximum rat-
ing conditions for extended periods
may affect reliability.
IS61LV3216
4Integrated Circuit Solution Inc.
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READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-10 -12 -15 -20
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 10 — 12 — 15 — 20 — ns
tAA Address Access Time — 10 — 12 — 15 — 20 ns
tOHA Output Hold Time 3 — 3 — 3 — 3 — ns
tACE CE Access Time — 10 — 12 — 15 — 20 ns
tDOE OE Access Time — 5 — 6 — 7 — 8 ns
tHZOE
(2)
OE to High-Z Output 0 5 0 6 0 7 0 8 ns
tLZOE
(2)
OE to Low-Z Output 0 — 0 — 0 — 0 — ns
tHZCE
(2
CE to High-Z Output 0 5 0 6 0 7 0 8 ns
tLZCE
(2)
CE to Low-Z Output 4 — 4 — 4 — 4 — ns
tBA LB, UB Access Time — 5 — 6 — 7 — 8 ns
tHZB LB, UB to High-Z Output 0 5 0 6 0 7 0 8 ns
tLZB LB, UB to Low-Z Output 5 — 5 — 5 — 5 — ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of
0 to 3.0V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1a and 1b
AC TEST LOADS
Figure 1a. Figure 1b.
480 Ω
30 pF
Including
jig and
scope
255 Ω
OUTPUT
5V
480 Ω
5 pF
Including
jig and
scope
255 Ω
OUTPUT
5V
CAPACITANCE(1)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
IS61LV3216
Integrated Circuit Solution Inc. 5
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DATA VALID
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z DATA VALID
t
HZB
ADDRESS
OE
CE
LB, UB
D
OUT
t
HZCE
t
BA
t
LZB
READ CYCLE NO. 2(1,3)
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
IS61LV3216
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WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-10 -12 -15 -20
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 10 — 12 — 15 — 20 — ns
tSCE CE to Write End 9 — 10 — 11 — 12 — ns
tAW Address Setup Time 9 — 10 — 11 — 12 — ns
to Write End
tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — 0 — ns
tPWB LB, UB Valid to End of Write 9 — 10 — 11 — 12 — ns
tPWE WE Pulse Width 7 — 8 — 10 — 11 — ns
tSD Data Setup to Write End 5 — 6 — 7 — — 8 ns
tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns
tHZWE
(2)
WE LOW to High-Z Output — 5 — 6 — 7 — 8 ns
tLZWE
(2)
WE HIGH to Low-Z Output 1 — 1 — 1 — 1 — ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
IS61LV3216
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Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least
one of the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
AC WAVEFORMS
WRITE CYCLE NO. 1 (WEWE
WEWE
WE Controlled)(1,2)
UNDEFINED UNDEFINED
tWC
tSCE
tPWB
tAW
tHA
HIGH-ZHIGH-Z
tPWE
tHD
tSA
tHZWE
ADDRESS
CE
LB, UB
WE
WRITE
(1)
D
OUT
D
IN
tLZWE
tSD
IS61LV3216
8Integrated Circuit Solution Inc.
SR009-0B
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
10 IS61LV3216-10T 400mil TSOP-2
10 IS61LV3216-10K 400mil SOJ
12 IS61LV3216-12T 400mil TSOP-2
12 IS61LV3216-12K 400mil SOJ
15 IS61LV3216-15T 400mil TSOP-2
15 IS61LV3216-15K 400mil SOJ
20 IS61LV3216-20T 400mil TSOP-2
20 IS61LV3216-20K 400mil SOJ
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
12 IS61LV3216-12TI 400mil TSOP-2
12 IS61LV3216-12KI 400mil SOJ
15 IS61LV3216-15TI 400mil TSOP-2
15 IS61LV3216-15KI 400mil SOJ
20 IS61LV3216-20TI 400mil TSOP-2
20 IS61LV3216-20KI 400mil SOJ
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
