M368L2923MT1 184pin Unbuffered DDR SDRAM MODULE 1GB DDR SDRAM MODULE (128Mx64(64Mx64*2 bank) based on 64Mx8 DDR SDRAM) Unbuffered 184pin DIMM 64-bit Non-ECC/Parity Revision 0.0 September. 2001 Rev. 0.0 Sep. 2001 M368L2923MT1 184pin Unbuffered DDR SDRAM MODULE Revision History Revision 0 (Sep 2001) 1. First release for internal usage Rev. 0.0 Sep. 2001 M368L2923MT1 184pin Unbuffered DDR SDRAM MODULE M368L2923MT1 DDR SDRAM 184pin DIMM 128Mx64 DDR SDRAM 184pin DIMM based on 64Mx8 FEATURE GENERAL DESCRIPTION The Samsung M368L2923MT1 is 128M bit x 64 Double Data * Performance range Part No. Rate SDRAM high density memory module based on first gen. of 512Mb DDR SDRAM respectively. The Samsung M368- Max Freq. Interface M368L2923MT1-C(L)A2 133MHz(7.5ns@CL=2) L2923MT1 consists of sixteen CMOS 64M x 8 bit with 4banks M368L2923MT1-C(L)B0 133MHz(7.5ns@CL=2.5) Double Data Rate SDRAMs in 66pin TSOP-II(400mil) pack- M368L2923MT1-C(L)A0 100MHz(10ns@CL=2) SSTL_2 ages mounted on a 184pin glass-epoxy substrate. Four 0.1uF * Power supply : Vdd: 2.5V 0.2V, Vddq: 2.5V 0.2V decoupling capacitors are mounted on the printed circuit board * Double-data-rate architecture; two data transfers per clock cycle in parallel for each DDR SDRAM. The M368L2923MT1 Dual In-line Memory Module and is intended for mounting into 184pin edge connector sockets. Synchronous design allows precise cycle control with the use * Bidirectional data strobe(DQS) * Differential clock inputs(CK and CK ) * DLL aligns DQ and DQS transition with CK transition of system clock. I/O transactions are possible on every clock * Programmable Read latency 2, 2.5 (clock) * Programmable Burst length (2, 4, 8) cycle. Range of operating frequencies, programmable laten- * Programmable Burst type (sequential & interleave) cies and burst lengths allows the same device to be useful for a * Edge aligned data output, center aligned data input * Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) variety of high bandwidth, high performance memory system * Serial presence detect with EEPROM * PCB : Height 1250 (mil), double sided component applications. PIN CONFIGURATIONS (Front side/back side) Pin Front Pin Front Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 /CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 *CB0 *CB1 VDD *DQS8 A0 *CB2 VSS *CB3 BA1 KEY DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Front Pin Back Pin Back VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD */CS2 DQ48 DQ49 VSS /CK2 CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC *A13 VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 CKE1 VDDQ *BA2 DQ20 A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 *CB4 *CB5 VDDQ CK0 /CK0 VSS *DM8 A10 *CB6 VDDQ *CB7 KEY VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 145 146 147 148 149 150 151 152 153 PIN DESCRIPTION Pin Back 154 /RAS 155 DQ45 156 VDDQ 157 /CS0 158 /CS1 159 DM5 160 VSS 161 DQ46 162 DQ47 163 */CS3 164 VDDQ 165 DQ52 166 DQ53 167 NC 168 VDD 169 DM6 170 DQ54 171 DQ55 172 VDDQ 173 NC 174 DQ60 175 DQ61 176 VSS 177 DM7 178 DQ62 179 DQ63 180 VDDQ 181 SA0 182 SA1 183 SA2 184 VDDSPD Pin Name Function A0 ~ A12 Address input (Multiplexed) BA0 ~ BA1 Bank Select Address DQ0 ~ DQ63 Data input/output DQS0 ~ DQS7 Data Strobe input/output CK0, CK0 ~ CK2, CK2 Clock input CKE0,CKE1 Clock enable input CS0, CS1 Chip select input RAS Row address strobe CAS Column address strobe WE Write enable DM0 ~ 7 Data - in mask VDD Power supply (2.5V) VDDQ Power Supply for DQS(2.5V) VSS Ground VREF Power supply for reference VDDSPD Serial EEPROM Power Supply (2.3V to 3.6V) SDA Serial data I/O SCL Serial clock SA0 ~ 2 Address in EEPROM VDDID VDD identification flag NC No connection * These pins are not used in this module. SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Rev. 0.0 Sep. 2001 M368L2923MT1 184pin Unbuffered DDR SDRAM MODULE Functional Block Diagram CS1 CS0 DQS4 DM4 DQS0 DM0 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D0 CS DQS D8 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQS CS D4 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D12 DQS5 DM5 DQS1 DM1 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D1 CS DQS D9 CS DQS D5 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D13 DQS6 DM6 DQS2 DM2 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS DM DQS I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D2 CS DQS D10 CS DQS D6 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D14 DQS7 DM7 DQS3 DM3 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D3 CS DQS D11 CS DQS D7 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D15 *Clock Net Wiring Dram1 Serial PD SCL SDA WP BA0 - BA1 A0 - A13 A0 A1 A2 SA0 SA1 SA2 CK0/CK0 CK1/CK1 CK2/CK2 A0-An: SDRAMs D0 - D15 RAS: SDRAMs D0 - D15 CAS CAS: SDRAMs D0 - D15 V DD /VDDQ SPD D0 - D15 D0 - D15 VREF VS S V DDID 4 SDRAMs 6 SDRAMs 6 SDRAMs Dram2 R=120 Dram3 *(Cap.) Card Edge Dram4 *(Cap.) Dram5 BA0-BAn: SDRAMs D0 - D15 RAS V D D S PD Clock Wiring Clock SDRAMs Input D0 - D15 D0 - D15 Strap: see Note 4 CKE1 CKE0 CKE: SDRAMs D8 - D15 CKE: SDRAMs D0 - D7 WE WE: SDRAMs D0 - D15 *If four DRAMs are loaded, Cap will replace DRAM3,4 Dram6 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM resistors: 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD VDDQ. Rev. 0.0 Sep. 2001 M368L2923MT1 184pin Unbuffered DDR SDRAM MODULE ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Symbol Value Unit V IN, VOUT -0.5 ~ 3.6 V Voltage on V DD supply relative to Vss V DD -1.0 ~ 3.6 V Voltage on V DDQ supply relative to Vss V DDQ -0.5 ~ 3.6 V Storage temperature TSTG -55 ~ +150 C Power dissipation PD 16 W Short circuit current IOS 50 mA Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out) Recommended operating conditions(Voltage referenced to V SS =0V, T A=0 to 70C) Parameter Symbol Min Max Supply voltage(for device with a nominal V DD of 2.5V) V DD 2.3 2.7 I/O Supply voltage V DDQ 2.3 2.7 V I/O Reference voltage V REF VDDQ/2-50mV VDDQ/2+50mV V 1 V TT V REF-0.04 V REF+0.04 V 2 Input logic high voltage V I H(DC) V REF+0.15 V DDQ +0.3 V 4 Input logic low voltage V IL (DC) -0.3 V REF-0.15 V 4 Input Voltage Level, CK and CK inputs V I N(DC) -0.3 V DDQ +0.3 V Input Differential Voltage, CK and CK inputs V I D(DC) 0.3 V DDQ +0.6 V 3 Input crossing point voltage, CK and CK inputs V IX (DC) 1.15 1.35 V 5 II -2 2 uA Output leakage current IO Z -5 5 uA Output High Current(Normal strengh driver) ;V OUT = VT T + 0.84V IOH -16.8 mA Output High Current(Normal strengh driver) ;V OUT = VT T - 0.84V IOL 16.8 mA Output High Current(Half strengh driver) ;V OUT = V T T + 0.45V IOH -9 mA Output High Current(Half strengh driver) ;V OUT = VT T - 0.45V IOL 9 mA I/O Termination voltage(system) Input leakage current Unit Note Notes 1. Includes 25mV margin for DC offset on V REF, and a combined total of 50mV margin for all AC noise and DC offset on V REF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V REF and internal DRAM noise coupled TO V REF, both of which may result in V REF noise. V REF should be de-coupled with an inductance of 3nH. 2.V TT is not applied directly to the device. V T T is a system supply for signal termination resistors, is expected to be set equal to V REF, and must track variations in the DC level of V REF 3. V I D is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the dc level of the same. 6. These charactericteristics obey the SSTL-2 class II standards. Rev. 0.0 Sep. 2001 M368L2923MT1 184pin Unbuffered DDR SDRAM MODULE DDR SDRAM SPEC Items and Test Conditions Recommended operating conditions Unless Otherwise Noted, T A=0 to 70 C ) Conditions Symbol Typical Worst Operating current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle IDD0 - - Operating current - One bank operation ; One bank open, BL=4, Reads - Refer to the following page for detailed test condition IDD1 - - Percharge power-down standby current; All banks idle; power - down mode; CKE = <VIL(max); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD2P - - Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs changing once per clock cycle; Vin = Vref for DQ,DQS and DM IDD2F - - Precharge Quiet standby current; CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs stable with keeping >= VIH(min) or =<VIL(max); Vin = Vref for DQ ,DQS and DM IDD2Q - - Active power - down standby current ; one bank active; power-down mode; CKE=< VIL (max); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD3P - - Active standby current; CS# >= VIH(min); CKE>=VIH(min); one bank active; active - precharge; tRC=tRASmax; tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle IDD3N - - Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control inputs changing once per clock cycle; CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A, CL=2.5 at tCK = 133Mhz for DDR266B ; 50% of data changing at every burst; lout = 0 m A IDD4R - - Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active address and control inputs changing once per clock cycle; CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A, CL=2.5 at tCK = 133Mhz for DDR266B ; DQ, DM and DQS inputs changing twice per clock cycle, 50% of input data changing at every burst IDD4W - - Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh IDD5 - - Self refresh current; CKE =< 0.2V; External clock should be on; tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B IDD6 - - Orerating current - Four bank operation ; Four bank interleaving with BL=4 -Refer to the following page for detailed test condition IDD7A - - Typical case: VDD = 2.5V, T = 25'C Worst case : VDD = 2.7V, T = 10'C Rev. 0.0 Sep. 2001 M368L2923MT1 184pin Unbuffered DDR SDRAM MODULE DDR SDRAM IDD spec table Symbol IDD6 B0(DDR266@CL=2.5) A0(DDR200@CL=2) Unit worst typical worst typical worst IDD0 1560 2080 1560 2080 1416 1840 mA IDD1 1720 2280 1720 2280 1624 2040 mA IDD2P 544 808 544 808 456 688 mA IDD2F 760 1160 760 1160 640 960 mA IDD2Q 640 960 640 960 528 800 mA IDD3P 760 1160 760 1160 656 960 mA IDD3N 1040 1520 1040 1520 880 1280 mA IDD4R 1880 2520 1880 2520 1520 2160 mA IDD4W 2120 2760 2120 2760 1720 2400 mA IDD5 2520 3240 2520 3240 2280 2960 mA Normal 48 112 48 112 48 112 mA Low power 32 48 32 48 32 48 mA 3560 4600 3560 4600 3160 4000 mA IDD7A * Module A2(DDR266@CL=2) typical IDD was calculated on the basis of component IDD and Notes Optional can be differently measured according to DQ loading cap. < Detailed test conditions for DDR SDRAM IDD1 & IDD7A > IDD1 : Operating current: One bank operation 1. Typical Case : Vdd = 2.5V, T=25' C 2. Worst Case : Vdd = 2.7V, T= 10' C 3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = 0mA 4. Timing patterns - DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP Rev. 0.0 Sep. 2001 M368L2923MT1 184pin Unbuffered DDR SDRAM MODULE IDD7A : Operating current: Four bank operation 1. Typical Case : Vdd = 2.5V, T=25' C 2. Worst Case : Vdd = 2.7V, T= 10' C 3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not changing. lout = 0mA 4. Timing patterns - DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing *100% of data changing at every burst - DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing *100% of data changing at every burst - DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing *100% of data changing at every burst Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP AC Operating Conditions Parameter/Condition Symbol Min Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC) Input Differential Voltage, CK and CK inputs VID(AC) 0.7 Input Crossing Point Voltage, CK and CK inputs VIX(AC) 0.5*VDDQ-0.2 Max VREF + 0.31 Unit Note V 3 VREF - 0.31 V 3 VDDQ+0.6 V 1 0.5*VDDQ+0.2 V 2 Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz. Rev. 0.0 Sep. 2001 M368L2923MT1 184pin Unbuffered DDR SDRAM MODULE AC OPERATING TEST CONDITIONS (V DD =2.5V, V DDQ =2.5V, T A= 0 to 70 C ) Parameter Value Unit 0.5 * V DDQ V 1.5 V V REF +0.3 1/V REF -0.3 1 V V REF V V tt V Input reference voltage for Clock Input signal maximum peak swing Input Levels(V IH /V IL) Input timing measurement reference level Output timing measurement reference level Output load condition Note See Load Circuit V tt =0.5*V DDQ RT=50 Output Z0=50 V REF CLOAD =30pF =0.5*VDDQ Output Load Circuit (SSTL_2) Input/Output CAPACITANCE (V DD =2.5V, V DDQ =2.5V, T A = 25C, f=1MHz) Symbol Min Max Unit Input capacitance(A 0 ~ A 1 2, BA 0 ~ BA 1 ,RAS ,CAS , WE ) Parameter CIN1 65 81 pF Input capacitance(CKE 0,CKE 1 ) CIN2 42 50 pF Input capacitance( CS 0, CS1 ) CIN3 42 50 pF Input capacitance( CLK 0 , CLK 1,CLK 2) CIN4 27 34 pF Data & DQS input/output capacitance(DQ 0~DQ 63 ) C OUT 10 13 pF Input capacitance(DM 0~DM 8) CIN5 10 13 pF Rev. 0.0 Sep. 2001 M368L2923MT1 184pin Unbuffered DDR SDRAM MODULE AC Timming Parameters & Specifications Parameter Symbol Row cycle time (These AC charicteristics were tested on the Component) -TCA2(DDR266A) -TCB0(DDR266B) Min Max Min Max Min Max 65 Refresh row cycle time tRFC 75 Row active time tRAS 45 RAS to CAS delay tRCD 20 20 20 ns Row active to Row active delay Write recovery time 70 Unit tRC Row precharge time 65 -TCA0 (DDR200) 75 120K 45 ns 80 120K ns 48 120K ns tRP 20 20 20 ns tRRD 15 15 15 ns tWR 2 2 2 tCK Last data in to Read command tCDLR 1 1 1 tCK Col. address to Col. address delay tCCD 1 1 1 tCK Clock cycle time CL=2.0 CL=2.5 Clock high level width Clock low level width tCK tCH 7.5 12 10 12 7.5 12 7.5 12 0.45 0.55 0.45 0.55 10 12 ns 5 12 ns 5 0.45 0.55 tCK tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK tDQSCK -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns Output data access time from CK/CK tAC -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns Data strobe edge to ouput data edge tDQSQ - +0.5 - +0.5 - +0.6 ns Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK DQS-out access time from CK/CK Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS-in setup time tWPRES 0 0 0 ns DQS-in hold time tWPREH 0.25 0.25 0.25 tCK tDSS 0.2 0.2 0.2 tCK DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time tDSH 0.2 0.2 0.2 tCK DQS-in high level width tDQSH 0.35 0.35 0.35 tCK DQS-in low level width tDQSL 0.35 DQS-in cycle time tDSC 0.9 tIS 0.9 Address and Control Input setup time 0.35 1.1 0.9 0.35 1.1 0.9 1.1 2 1.1 tCK ns 6 ns 6 Address and Control Input hold time tIH 0.9 Data-out high impedence time from CK/CK tHZ tACmin 400ps tACmax - 400ps tACmin - 400ps tACmax - 400ps tACmin - 400ps tACmax - 400ps ps Data-out low impedence time from CK/CK tLZ tACmin 400ps tACmax - 400ps tACmin - 400ps tACmax - 400ps tACmin - 400ps tACmax - 400ps ps Input Slew Rate(for input only pins) 5 tCK 0.9 1.1 0.9 Note tSL(I) 0.5 0.5 0.5 V/ns 6 Input Slew Rate(for I/O pins) tSL(IO) 0.5 0.5 0.5 V/ns 7 Output Slew Rate(x4,x8) tSL(O) 1.0 4.5 1.0 4.5 1.0 4.5 V/ns 10 Output Slew Rate(x16) tSL(O) 0.7 5 0.7 5 0.7 5 V/ns 10 Output Slew Rate Matching Ratio(rise to fall) tSLMR 0.67 1.5 0.67 1.5 0.67 1.5 Rev. 0.0 Sep. 2001 M368L2923MT1 Parameter 184pin Unbuffered DDR SDRAM MODULE Symbol -TCA2(DDR266A) Min Max -TCB0(DDR266B) Min Max -TCA0 (DDR200) Min Max Unit Note Mode register set cycle time tMRD 15 15 16 ns DQ & DM setup time to DQS tDS 0.5 0.5 0.6 ns 7,8,9 DQ & DM hold time to DQS tDH 0.5 0.5 0.6 ns 7,8,9 DQ & DM input pulse width tDIPW 1.75 1.75 2 ns Power down exit time tPDEX 10 10 10 ns Exit self refresh to write command tXSW 95 116 ns Exit self refresh to bank active command tXSA 75 75 80 ns Exit self refresh to read command tXSR 200 200 200 Cycle tREF 15.6 15.6 15.6 us 1 7.8 7.8 7.8 us 1 Output DQS valid window tQH tHPmin -tQHS - tHPmin -tQHS - tHPmin -tQHS - ns 5 Clock half period tHP tCLmin or tCHmin - tCLmin or tCHmin - tCLmin or tCHmin - ns Refresh interval time 64Mb, 128Mb 256Mb Data hold skew factor tQHS DQS write postamble time tWPST 0.75 0.25 0.75 0.25 0.8 0.25 4 ns tCK 3 Note : 1. Maximum burst refresh of 8 2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. A write command can be applied with t RCD satisfied after this command. 5. For registered DINNs, t CL and t CH are 45% of the period including both the half period jitter (t JIT(HP) ) of the PLL and the half period jitter due to crosstalk (t JIT(crosstalk)) on the DIMM. Rev. 0.0 Sep. 2001 M368L2923MT1 184pin Unbuffered DDR SDRAM MODULE 6. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate tIS tIH (V/ns) (ps) (ps) 0.5 0 0 0.4 +50 +50 0.3 +100 +100 This derating table is used to increase t IS /tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating I/O Setup/Hold Slew Rate tDS tDH (V/ns) (ps) (ps) 0.5 0 0 0.4 +75 +75 0.3 +150 +150 This derating table is used to increase t DS /tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 8. I/O Setup/Hold Plateau Derating I/O Input Level tDS tDH (mV) (ps) (ps) 280 +50 +50 This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF 310mV for a duration of up to 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate tDS tDH (ns/V) (ps) (ps) 0 0 0 0.25 +50 +50 0.5 +100 +100 This derating table is used to increase t DS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate. 10. This parameter is fir system simulation purpose. It is guranteed by design. Rev. 0.0 Sep. 2001 M368L2923MT1 184pin Unbuffered DDR SDRAM MODULE Command Truth Table (V=Valid, X=Dont Care, H=Logic High, L=Logic Low) COMMAND CKEn-1 CKEn CS RAS CAS WE BA 0,1 A 11, A 12 A9 ~ A0 A 10/AP Note Register Extended MRS H X L L L L OP CODE 1, 2 Register Mode Register Set H X L L L L OP CODE 1, 2 L L L H X L H H H Auto Refresh H Entry Refresh Self Refresh Exit H L 3 L H H X X X Bank Active & Row Addr. H X L L H H V Read & Column Address Auto Precharge Disable H X L H L H V Write & Column Address Auto Precharge Disable H X L H L L V H X L H H L H X L L H L Entry H L H X X X Exit L H Entry H L Auto Precharge Enable 3 All Banks Row Address L H L H Bank Selection Precharge Active Power Down L V V V X X X X H X X X L H H H H X X X V V V Precharge Power Down Mode 3 X Auto Precharge Enable Burst Stop 3 Column Address (A 0~A 9, A11 ) 4 Column Address (A 0~A 9, A11 ) 4 X V L X H 4 4, 6 7 X 5 X X Exit L H L DM H No operation (NOP) : Not defined H X X X H X X X L H H H 8 9 X 9 Note : 1. OP Code : Operand Code. A 0 ~ A 12 & BA 0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank B is selected. If both BA0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A 10 /AP is "High" at row precharge, BA 0 and BA 1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at t RP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. Rev. 0.0 Sep. 2001 M368L2923MT1 184pin Unbuffered DDR SDRAM MODULE PACKAGE DIMENSIONS Units : Inches (Millimeters) 5.25 0.006 (133.350 0.15 ) 0.118 (3.00) 5.077 (128.950) 0.7 (17.80 ) 0.39 3 0.10 0 Min B ( 2.30 Min) A (10 .0 0) (4 .0 0) ( 2X) 0 .1 57 1.25 0.006 (31.75 0.15) 2.500 0.10 M C B A 2.55 1.95 0.145 Max (64.77) (49.53) (3.67 Max) 0.050 0.0039 0.157 (4.00) (2.50 ) 0.26 (6.62) 0.250 (6.350) 0 .1 00 (1.270 0.10) 0.118 (3.00) 0.039 0.002 (1.000 0.050) 0.0787 R (2.00) 0.1496 (3.80) 0.0078 0.006 (0.20 0.15) 2.175 0.071 (1.80 ) Detail A 0.050 (1.270 ) Detail B 0.1575 (4.00) 0.10 M C AM B Tolerances : 0.005(.13) unless otherwise specified. The used device is 64Mx8 SDRAM, TSOP. SDRAM Part NO : K4H510838M-TC Rev. 0.0 Sep. 2001