M368L2923MT1-CA2 - Samsung Semiconductor Division

184pin Unbuffered DDR SDRAM MODULEM368L2923MT1

Rev. 0.0 Sep. 2001

1GB DDR SDRAM MODULE

Unbuffered 184pin DIMM

(128Mx64(64Mx64*2 bank) based on 64Mx8 DDR SDRAM)

64-bit Non-ECC/Parity

Revision 0.0

September. 2001

184pin Unbuffered DDR SDRAM MODULEM368L2923MT1

Rev. 0.0 Sep. 2001

Revision History

Revision 0 (Sep 2001)

1. First release for internal usage

184pin Unbuffered DDR SDRAM MODULEM368L2923MT1

Rev. 0.0 Sep. 2001

The Samsung M368L2923MT1 is 128M bit x 64 Double Data

Rate SDRAM high density memory module based on first gen.

of 512Mb DDR SDRAM respectively. The Samsung M368-

L2923MT1 consists of sixteen CMOS 64M x 8 bit with 4banks

Double Data Rate SDRAMs in 66pin TSOP-II(400mil) pack-

ages mounted on a 184pin glass-epoxy substrate. Four 0.1uF

decoupling capacitors are mounted on the printed circuit board

in parallel for each DDR SDRAM. The M368L2923MT1 Dual

In-line Memory Module and is intended for mounting into

184pin edge connector sockets.

Synchronous design allows precise cycle control with the use

of system clock. I/O transactions are possible on every clock

cycle. Range of operating frequencies, programmable laten-

cies and burst lengths allows the same device to be useful for a

variety of high bandwidth, high performance memory system

applications.

GENERAL DESCRIPTION

PIN DESCRIPTION

* These pins are not used in this module.

Pin Name Function

A0 ~ A12 Address input (Multiplexed)

BA0 ~ BA1 Bank Select Address

DQ0 ~ DQ63 Data input/output

DQS0 ~ DQS7 Data Strobe input/output

CK0,CK0 ~ CK2, CK2 Clock input

CKE0,CKE1 Clock enable input

CS0, CS1 Chip select input

RAS Row address strobe

CAS Column address strobe

WE Write enable

DM0 ~ 7 Data - in mask

VDD Power supply (2.5V)

VDDQ Power Supply for DQS(2.5V)

VSS Ground

VREF Power supply for reference

VDDSPD Serial EEPROM Power

Supply (2.3V to 3.6V)

SDA Serial data I/O

SCL Serial clock

SA0 ~ 2 Address in EEPROM

VDDID VDD identification flag

NC No connection

PIN CONFIGURATIONS (Front side/back side)

Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back

VREF

DQ0

VSS

DQ1

DQS0

DQ2

VDD

DQ3

VSS

DQ8

DQ9

DQS1

VDDQ

CK1

/CK1

VSS

DQ10

DQ11

CKE0

VDDQ

DQ16

DQ17

DQS2

VSS

DQ18

VDDQ

DQ19

DQ24

VSS

DQ25

DQS3

VDD

DQ26

DQ27

VSS

*CB0

*CB1

VDD

*DQS8

*CB2

VSS

*CB3

BA1

DQ32

VDDQ

DQ33

DQS4

DQ34

VSS

BA0

DQ35

DQ40

VDDQ

/WE

DQ41

/CAS

VSS

DQS5

DQ42

DQ43

VDD

*/CS2

DQ48

DQ49

VSS

/CK2

CK2

VDDQ

DQS6

DQ50

DQ51

VSS

VDDID

DQ56

DQ57

VDD

DQS7

DQ58

DQ59

VSS

SDA

SCL

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

VSS

DQ4

DQ5

VDDQ

DM0

DQ6

DQ7

VSS

*A13

VDDQ

DQ12

DQ13

DM1

VDD

DQ14

DQ15

CKE1

VDDQ

*BA2

DQ20

A12

VSS

DQ21

A11

DM2

VDD

DQ22

DQ23

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

VSS

DQ28

DQ29

VDDQ

DM3

DQ30

VSS

DQ31

*CB4

*CB5

VDDQ

CK0

/CK0

VSS

*DM8

A10

*CB6

VDDQ

*CB7

VSS

DQ36

DQ37

VDD

DM4

DQ38

DQ39

VSS

DQ44

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

/RAS

DQ45

VDDQ

/CS0

/CS1

DM5

VSS

DQ46

DQ47

*/CS3

VDDQ

DQ52

DQ53

VDD

DM6

DQ54

DQ55

VDDQ

DQ60

DQ61

VSS

DM7

DQ62

DQ63

VDDQ

SA0

SA1

SA2

VDDSPD

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

KEY

M368L2923MT1 DDR SDRAM 184pin DIMM

128Mx64 DDR SDRAM 184pin DIMM based on 64Mx8

FEATURE

• Performance range

• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• Programmable Read latency 2, 2.5 (clock)

• Programmable Burst length (2, 4, 8)

• Programmable Burst type (sequential & interleave)

• Edge aligned data output, center aligned data input

• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)

• Serial presence detect with EEPROM

• PCB : Height 1250 (mil), double sided component

Part No. Max Freq. Interface

M368L2923MT1-C(L)A2 133MHz(7.5ns@CL=2)

SSTL_2M368L2923MT1-C(L)B0 133MHz(7.5ns@CL=2.5)

M368L2923MT1-C(L)A0 100MHz(10ns@CL=2)

KEY

184pin Unbuffered DDR SDRAM MODULEM368L2923MT1

Rev. 0.0 Sep. 2001

Functional Block Diagram

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

I/O 7

I/O 6

I/O 1

I/O 0

DM0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ12

DQ13

DQ14

DQ8

DQ9

DQ10

DQ11

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

DM1

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

I/O 7

I/O 6

I/O 1

I/O 0

D10

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DM2

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

I/O 7

I/O 6

I/O 1

I/O 0

D11

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DM3

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

I/O 7

I/O 6

I/O 1

I/O 0

DM4

D12

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

I/O 7

I/O 6

I/O 1

I/O 0

D13

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DM5

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

I/O 7

I/O 6

I/O 1

I/O 0

D14

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ60

DQ61

DQ62

DQ63

DQ56

DQ57

DQ58

DQ59

I/O 7

I/O 6

I/O 1

I/O 0

D15

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DM7

A0 - A13 A0-An: SDRAMs D0 - D15

RAS RAS: SDRAMs D0 - D15

CAS CAS: SDRAMs D0 - D15 CKE0 CKE: SDRAMs D0 - D7

WE WE: SDRAMs D0 - D15

CS0 CS1

CS CS CS CS

CS CS

Clock Wiring

CK0/CK0

Clock

Input SDRAMs

CK1/CK1 4 SDRAMs

6 SDRAMs

CKE1 CKE: SDRAMs D8 - D15

BA0 - BA1 BA0-BAn: SDRAMs D0 - D15

DQS0

DQS

DQS4

DQS1 DQS5

DQS DQS

DQS2

DQS DQS

DQS3

DQS DQS

DM6

DQS6

DQS7

DQ15 I/O 2 I/O 5

DQS

DQSDQS

DQS

DQS DQS DQS

CK2/CK2

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must

be maintained as shown.

3. DQ, DQS, DM resistors: 22 Ohms.

4. VDDID strap connections

(for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

STRAP IN (VSS): VDD ≠VDDQ.

*Clock Net Wiring

Card

Edge

Dram1

Dram2

Dram4

Dram5

Dram6

R=120ΩDram3

*(Cap.)

Cap will replace DRAM3,4

*If four DRAMs are loaded,

Serial PD

A1 A2

SA0 SA1 SA2

SCL SDA

VSS

D0 - D15

VDD /VDDQ D0 - D15

D0 - D15

VREF

VDDID Strap: see Note 4

VDDSPD SPD

184pin Unbuffered DDR SDRAM MODULEM368L2923MT1

Rev. 0.0 Sep. 2001

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit

Voltage on any pin relative to Vss VIN, VOUT -0.5 ~ 3.6 V

Voltage on VDD supply relative to Vss VDD -1.0 ~ 3.6 V

Voltage on VDDQ supply relative to Vss VDDQ -0.5 ~ 3.6 V

Storage temperature TSTG -55 ~ +150 °C

Power dissipation PD16 W

Short circuit current IOS 50 mA

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :

POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)

Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF,

bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled

TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH.

2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to

VREF, and must track variations in the DC level of VREF

3. VID is the magnitude of the difference between the input level on CK and the input level on CK.

4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in

simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.

5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.

6. These charactericteristics obey the SSTL-2 class II standards.

Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)

Parameter Symbol Min Max Unit Note

Supply voltage(for device with a nominal VDD of 2.5V) VDD 2.3 2.7

I/O Supply voltage VDDQ 2.3 2.7 V

I/O Reference voltage VREF VDDQ/2-50mV VDDQ/2+50mV V1

I/O Termination voltage(system) VTT VREF-0.04 VREF+0.04 V2

Input logic high voltage VIH(DC) VREF+0.15 VDDQ+0.3 V4

Input logic low voltage VIL(DC) -0.3 VREF-0.15 V4

Input Voltage Level, CK and CK inputs VIN(DC) -0.3 VDDQ+0.3 V

Input Differential Voltage, CK and CK inputs VID(DC) 0.3 VDDQ+0.6 V3

Input crossing point voltage, CK and CK inputs VIX(DC) 1.15 1.35 V5

Input leakage current II-2 2uA

Output leakage current IOZ -5 5uA

Output High Current(Normal strengh driver)

;VOUT = VTT + 0.84V IOH -16.8 mA

Output High Current(Normal strengh driver)

;VOUT = VTT - 0.84V IOL 16.8 mA

Output High Current(Half strengh driver)

;VOUT = VTT + 0.45V IOH -9 mA

Output High Current(Half strengh driver)

;VOUT = VTT - 0.45V IOL 9mA

184pin Unbuffered DDR SDRAM MODULEM368L2923MT1

Rev. 0.0 Sep. 2001

Recommended operating conditions Unless Otherwise Noted, TA=0 to 70°C)

Typical case: VDD = 2.5V, T = 25’C

Worst case : VDD = 2.7V, T = 10’C

Conditions Symbol Typical Worst

Operating current - One bank Active-Precharge;

tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;

DQ,DM and DQS inputs changing twice per clock cycle;

address and control inputs changing once per clock cycle

IDD0 - -

Operating current - One bank operation ; One bank open, BL=4, Reads

- Refer to the following page for detailed test condition IDD1 - -

Percharge power-down standby current; All banks idle; power - down mode;

CKE = <VIL(max); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;

Vin = Vref for DQ,DQS and DM

IDD2P - -

Precharge Floating standby current; CS# > =VIH(min);All banks idle;

CKE > = VIH(min); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;

Address and other control inputs changing once per clock cycle;

Vin = Vref for DQ,DQS and DM

IDD2F - -

Precharge Quiet standby current; CS# > = VIH(min); All banks idle;

CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;

Address and other control inputs stable with keeping >= VIH(min) or =<VIL(max);

Vin = Vref for DQ ,DQS and DM

IDD2Q - -

Active power - down standby current ; one bank active; power-down mode;

CKE=< VIL (max); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;

Vin = Vref for DQ,DQS and DM

IDD3P - -

Active standby current; CS# >= VIH(min); CKE>=VIH(min);

one bank active; active - precharge; tRC=tRASmax; tCK = 100Mhz for DDR200,

133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs changing twice

per clock cycle; address and other control inputs changing once

per clock cycle

IDD3N - -

Operating current - burst read; Burst length = 2; reads; continguous burst;

One bank active; address and control inputs changing once per clock cycle;

CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A, CL=2.5 at tCK =

133Mhz for DDR266B ; 50% of data changing at every burst; lout = 0 m A

IDD4R - -

Operating current - burst write; Burst length = 2; writes; continuous burst;

One bank active address and control inputs changing once per clock cycle;

CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A,

CL=2.5 at tCK = 133Mhz for DDR266B ; DQ, DM and DQS inputs changing twice

per clock cycle, 50% of input data changing at every burst

IDD4W - -

Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz,

10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh IDD5 - -

Self refresh current; CKE =< 0.2V; External clock should be on;

tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B IDD6 - -

Orerating current - Four bank operation ; Four bank interleaving with BL=4

-Refer to the following page for detailed test condition IDD7A - -

DDR SDRAM SPEC Items and Test Conditions

184pin Unbuffered DDR SDRAM MODULEM368L2923MT1

Rev. 0.0 Sep. 2001

DDR SDRAM IDD spec table

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Symbol A2(DDR266@CL=2) B0(DDR266@CL=2.5) A0(DDR200@CL=2) Unit Notes

typical worst typical worst typical worst

IDD0 1560 2080 1560 2080 1416 1840 mA

IDD1 1720 2280 1720 2280 1624 2040 mA

IDD2P 544 808 544 808 456 688 mA

IDD2F 760 1160 760 1160 640 960 mA

IDD2Q 640 960 640 960 528 800 mA

IDD3P 760 1160 760 1160 656 960 mA

IDD3N 1040 1520 1040 1520 880 1280 mA

IDD4R 1880 2520 1880 2520 1520 2160 mA

IDD4W 2120 2760 2120 2760 1720 2400 mA

IDD5 2520 3240 2520 3240 2280 2960 mA

IDD6 Normal 48 112 48 112 48 112 mA

Low power 32 48 32 48 32 48 mA Optional

IDD7A 3560 4600 3560 4600 3160 4000 mA

< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >

IDD1 : Operating current: One bank operation

1. Typical Case : Vdd = 2.5V, T=25’ C

2. Worst Case : Vdd = 2.7V, T= 10’ C

3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once

per clock cycle. lout = 0mA

4. Timing patterns

- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK

Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing

*50% of data changing at every burst

- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK

Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing

*50% of data changing at every burst

- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK

Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing

*50% of data changing at every burst

Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP

184pin Unbuffered DDR SDRAM MODULEM368L2923MT1

Rev. 0.0 Sep. 2001

IDD7A : Operating current: Four bank operation

1. Typical Case : Vdd = 2.5V, T=25’ C

2. Worst Case : Vdd = 2.7V, T= 10’ C

3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not

changing. lout = 0mA

4. Timing patterns

- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing

*100% of data changing at every burst

- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK

Read with autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing

*100% of data changing at every burst

- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing

*100% of data changing at every burst

Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP

AC Operating Conditions

Parameter/Condition Symbol Min Max Unit Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 V3

Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC) VREF - 0.31 V3

Input Differential Voltage, CK and CK inputs VID(AC) 0.7 VDDQ+0.6 V1

Input Crossing Point Voltage, CK and CK inputs VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V2

Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.

2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.

3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-

tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.

184pin Unbuffered DDR SDRAM MODULEM368L2923MT1

Rev. 0.0 Sep. 2001

Input/Output CAPACITANCE (VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz)

Parameter Symbol Min Max Unit

Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS, WE ) CIN1 65 81 pF

Input capacitance(CKE0,CKE1)CIN2 42 50 pF

Input capacitance( CS0, CS1)CIN3 42 50 pF

Input capacitance( CLK0, CLK1,CLK2)CIN4 27 34 pF

Data & DQS input/output capacitance(DQ0~DQ63)COUT 10 13 pF

Input capacitance(DM0~DM8)CIN5 10 13 pF

Output Load Circuit (SSTL_2)

Output Z0=50Ω

CLOAD=30pF

VREF

=0.5*VDDQ

RT=50Ω

Vtt=0.5*VDDQ

AC OPERATING TEST CONDITIONS (VDD=2.5V, VDDQ=2.5V, TA= 0 to 70°C)

Parameter Value Unit Note

Input reference voltage for Clock 0.5 * VDDQ V

Input signal maximum peak swing 1.5 V

Input Levels(VIH/VIL)VREF+0.31/VREF-0.31V

Input timing measurement reference level VREF V

Output timing measurement reference level Vtt V

Output load condition See Load Circuit

184pin Unbuffered DDR SDRAM MODULEM368L2923MT1

Rev. 0.0 Sep. 2001

AC Timming Parameters & Specifications (These AC charicteristics were tested on the Component)

Parameter Symbol -TCA2(DDR266A) -TCB0(DDR266B) -TCA0 (DDR200) Unit Note

Min Max Min Max Min Max

Row cycle time tRC 65 65 70 ns

Refresh row cycle time tRFC 75 75 80 ns

Row active time tRAS 45 120K 45 120K 48 120K ns

RAS to CAS delay tRCD 20 20 20 ns

Row precharge time tRP 20 20 20 ns

Row active to Row active delay tRRD 15 15 15 ns

Write recovery time tWR 2 2 2 tCK

Last data in to Read command tCDLR 1 1 1 tCK

Col. address to Col. address delay tCCD 1 1 1 tCK

Clock cycle time CL=2.0 tCK 7.5 12 10 12 10 12 ns 5

CL=2.5 7.5 12 7.5 12 12 ns 5

Clock high level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK

Clock low level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK

DQS-out access time from CK/CK tDQSCK -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns

Output data access time from CK/CK tAC -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns

Data strobe edge to ouput data edge tDQSQ -+0.5 -+0.5 -+0.6 ns 5

Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK

Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK

CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK

DQS-in setup time tWPRES 0 0 0 ns 2

DQS-in hold time tWPREH 0.25 0.25 0.25 tCK

DQS falling edge to CK rising-setup time tDSS 0.2 0.2 0.2 tCK

DQS falling edge from CK rising-hold time tDSH 0.2 0.2 0.2 tCK

DQS-in high level width tDQSH 0.35 0.35 0.35 tCK

DQS-in low level width tDQSL 0.35 0.35 0.35 tCK

DQS-in cycle time tDSC 0.9 1.1 0.9 1.1 0.9 1.1 tCK

Address and Control Input setup time tIS 0.9 0.9 1.1 ns 6

Address and Control Input hold time tIH 0.9 0.9 1.1 ns 6

Data-out high impedence time from CK/CK tHZ tACmin -

400ps tACmax

- 400ps tACmin

- 400ps tACmax

- 400ps tACmin

- 400ps tACmax

- 400ps ps

Data-out low impedence time from CK/CK tLZ tACmin -

400ps tACmax

- 400ps tACmin

- 400ps tACmax

- 400ps tACmin

- 400ps tACmax

- 400ps ps

Input Slew Rate(for input only pins) tSL(I) 0.5 0.5 0.5 V/ns 6

Input Slew Rate(for I/O pins) tSL(IO) 0.5 0.5 0.5 V/ns 7

Output Slew Rate(x4,x8) tSL(O) 1.0 4.5 1.0 4.5 1.0 4.5 V/ns 10

Output Slew Rate(x16) tSL(O) 0.7 50.7 50.7 5V/ns 10

Output Slew Rate Matching Ratio(rise to fall) tSLMR 0.67 1.5 0.67 1.5 0.67 1.5

184pin Unbuffered DDR SDRAM MODULEM368L2923MT1

Rev. 0.0 Sep. 2001

Note : 1. Maximum burst refresh of 8

2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from

High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,

DQS could be High at this time, depending on tDQSS.

3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,

but system performance (bus turnaround) will degrade accordingly.

4. A write command can be applied with tRCD satisfied after this command.

5. For registered DINNs, tCL and tCH are ≥ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half

period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.

Parameter Symbol -TCA2(DDR266A) -TCB0(DDR266B) -TCA0 (DDR200) Unit Note

Min Max Min Max Min Max

Mode register set cycle time tMRD 15 15 16 ns

DQ & DM setup time to DQS tDS 0.5 0.5 0.6 ns 7,8,9

DQ & DM hold time to DQS tDH 0.5 0.5 0.6 ns 7,8,9

DQ & DM input pulse width tDIPW 1.75 1.75 2ns

Power down exit time tPDEX 10 10 10 ns

Exit self refresh to write command tXSW 95 116 ns

Exit self refresh to bank active command tXSA 75 75 80 ns 4

Exit self refresh to read command tXSR 200 200 200 Cycle

Refresh interval time 64Mb, 128Mb tREF 15.6 15.6 15.6 us 1

256Mb 7.8 7.8 7.8 us 1

Output DQS valid window tQH tHPmin

-tQHS -tHPmin

-tQHS -ns 5

Clock half period tHP tCLmin

or tCHmin -tCLmin

or tCHmin -ns

Data hold skew factor tQHS 0.75 0.75 0.8 ns

DQS write postamble time tWPST 0.25 0.25 0.25 tCK 3

184pin Unbuffered DDR SDRAM MODULEM368L2923MT1

Rev. 0.0 Sep. 2001

6. Input Setup/Hold Slew Rate Derating

This derating table is used to increase tIS/tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate

based on the lesser of AC-AC slew rate and DC-DC slew rate.

7. I/O Setup/Hold Slew Rate Derating

This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate

based on the lesser of AC-AC slew rate and DC-DC slew rate.

8. I/O Setup/Hold Plateau Derating

This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of

up to 2ns.

9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating

This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate

is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall

Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.

10. This parameter is fir system simulation purpose. It is guranteed by design.

Input Setup/Hold Slew Rate ∆tIS ∆tIH

(V/ns) (ps) (ps)

0.5 0 0

0.4 +50 +50

0.3 +100 +100

I/O Setup/Hold Slew Rate ∆tDS ∆tDH

(V/ns) (ps) (ps)

0.5 0 0

0.4 +75 +75

0.3 +150 +150

I/O Input Level ∆tDS ∆tDH

(mV) (ps) (ps)

± 280 +50 +50

Delta Rise/Fall Rate ∆tDS ∆tDH

(ns/V) (ps) (ps)

0 0 0

±0.25 +50 +50

±0.5 +100 +100

184pin Unbuffered DDR SDRAM MODULEM368L2923MT1

Rev. 0.0 Sep. 2001

Command Truth Table

(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)

COMMAND CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP A11, A12

A9 ~ A0Note

Refresh

Auto Refresh HHL L L HX3

Self

Refresh

Entry L 3

Exit LHLH H H X3

HX X X 3

Bank Active & Row Addr. HXL L H H VRow Address

Read &

Column Address Auto Precharge Disable HXLHLHVLColumn

Address

(A0~A9,A11)

Auto Precharge Enable H4

Write &

Column Address Auto Precharge Disable HXLHL L VLColumn

Address

(A0~A9,A11)

Auto Precharge Enable H4, 6

Burst Stop HXLHHLX7

Precharge Bank Selection HXL L HLVLX

All Banks XH5

Active Power Down Entry HLHX X X

XLV V V

Exit LHX X X X

Precharge Power Down Mode

Entry HLHX X X

LH H H

Exit LHHX X X

LV V V

DM HX X 8

No operation (NOP) : Not defined HXHX X X X9

LH H H 9

Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)

2. EMRS/ MRS can be issued only at all banks precharge state.

A new command can be issued 2 clock cycles after EMRS or MRS.

3. Auto refresh functions are same as the CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.

If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.

6. During burst write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

7. Burst stop command is valid at every burst length.

8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).

9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.

184pin Unbuffered DDR SDRAM MODULEM368L2923MT1

Rev. 0.0 Sep. 2001

Tolerances : ± 0.005(.13) unless otherwise specified.

The used device is 64Mx8 SDRAM, TSOP.

SDRAM Part NO : K4H510838M-TC

PACKAGE DIMENSIONS

5.25 ± 0.006

5.077

Units : Inches (Millimeters)

0.050

0.0078 ±0.006

(0.20 ±0.15)

0.145 Max

0.050 ± 0.0039

(1.270 ± 0.10)

0.100 Min

(2.30 Min)

0.393

(10.00)

(1.270)

0.100

(2.50 )

Detail B

A B

(128.950)

(133.350 ± 0.15)

0.250

(6.350)

Detail A

0.157

(4.00)

0.071

(1.80)

(3.67 Max)

0.039 ± 0.002

(1.000 ± 0.050)

(3.80)

2.175

(6.62)

(64.77) (49.53)

(17.80)

2.55 1.95

0.26

2.500

0.7

0.10 MCB A

0.10 MCBA M

0.1496

(3.00)

0.118

R (2.00)

0.0787

(4.00)

0.1575

1.25 ± 0.006

(31.75 ±0.15)

(4.00)

(2X) 0.157

(3.00)

0.118