09/21/04
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IRF7842PbF
HEXFET® Power MOSFET
Notes through are on page 9
Top View
8
1
2
3
45
6
7
D
D
D
DG
S
A
S
S
A
SO-8
PD - 95269
Benefits
lVery Low RDS(on) at 4.5V VGS
lLow Gate Charge
lFully Characterized Avalanche Voltage
and Current
Applications
lSynchronous MOSFET for Notebook
Processor Power
lSecondary Synchronous Rectification
for Isolated DC-DC Converters
lSynchronous Fet for Non-Isolated
DC-DC Converters
lLead-Free
VDSS RDS(on) max Qg (typ
.)
40V 5.0m
:
@VGS = 10V 33nC
Absolute Maximum Ratings
Parameter Units
V
DS Dr ain-to-Sourc e Voltage V
VGS Gat e- to-Source Voltage
ID @ TA = 25 °C
Co nti n uous D r ai n C ur rent, V
GS
@ 10V
ID @ TA = 70 °C Co nti n uous D r ai n C ur rent, VGS @ 10V A
IDM
Pulsed Drai n Curre nt
c
PD @TA = 25°C
f
W
PD @TA = 70°C
f
Linear Derating Fact or W/°C
TJ Operating Junction and °C
TSTG Stor ag e Tem per atur e Ra ng e
Therma l R esistan ce
Parameter Typ. Max. Units
RθJL
Junc ti on-to-Drain Lead
g
––– 20 °C/W
RθJA
Junction-to-Ambient
fg
––– 50
-55 to + 15 0
2.5
0.02
1.6
Max.
18
14
140
± 20
40
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Static @ TJ = 25°C (unles s otherwise specified)
Parameter Min. Typ. Max. Units
BV
DSS Drai n- to-Sou r c e Breakdow n Volta ge 40 ––– ––– V
∆Β
V
DSS
/
∆
T
J B r ea kdow n Voltag e Te m p. Coeff ici e nt ––– 0. 037 ––– V / °C
R
DS(on) Static Drain-to-Source O n- Resistance ––– 4.0 5.0 mΩ
––– 4.7 5.9
V
GS(th) Gate Th r eshold Volt age 1.35 ––– 2.2 5 V
∆
V
GS(th) Gate Th r eshold Volt age Coeff icient ––– - 5. 6 –– – mV/°C
I
DSS Drain-to-S ource Le akage Cur r ent ––– ––– 1.0 µA
––– ––– 150
I
GSS Gate-to-Source Forward Leakage ––– ––– 100 nA
Gate- to-Sou r ce Reverse Leakage ––– –– – -100
gf s F or war d Tr a nsco nductance 81 ––– – –– S
Q
gTotal Gate Charge ––– 33 50
Q
gs1 Pre-Vth Gate-to-Source Charge ––– 9.6 –––
Q
gs2 Post-Vth Gate-to-Source Charge ––– 2.8 ––– nC
Q
gd Ga t e- t o - D r ain C har ge ––– 10 – ––
Q
godr Gate Cha r ge Ove r dr ive ––– 10.6 –––
Q
sw
Switch Charge (Q
gs2
+ Q
gd
)
–––12.8–––
Q
oss Output Charge ––– 18 ––– nC
R
GGate R esi sta nce ––– 1.3 TBD Ω
t
d(on) Turn - O n Delay Time ––– 14 – ––
t
rRise Time –––12–––
t
d(off) Turn-Off Delay Time – –– 2 1 ––– ns
t
fFall Time ––– 5.0 –––
C
iss Input Capaci ta nce ––– 4500 –––
C
oss Output Capacitance ––– 680 ––– pF
C
rss R everse Transfer Capacitance ––– 310 –––
Avalanche Characteristics
Parameter Units
E
AS
Sing le Pulse Avalanche Energy
d
mJ
I
AR
Avalanche Current
c
A
Diode Characteristics
Par a me ter Min. Typ. M a x . Un its
I
SCo ntin uous S our c e Cu r r ent ––– ––– 3. 1
(Body Diode) A
I
SM Pulsed Source Current ––– ––– 140
(Body Diode)
c
V
SD Diode Forward Voltage ––– ––– 1.0 V
t
rr Reverse Reco very Ti me ––– 99 150 ns
Q
rr Reverse Reco very C harge ––– 11 17 nC
Conditions
Max.
50
14
ƒ = 1. 0M H z
Conditions
VGS = 0V, ID = 25 0µA
R efe ren c e to 2 5 °C, ID = 1mA
VGS = 10V, ID = 17A
e
MOSFET symbol
VDS = 16V, VGS = 0V
VDD = 20V, V GS = 4. 5V
e
ID = 14A
VDS = 20V
VGS = 20V
VGS = -20V
VDS = 32V, VGS = 0V
TJ = 25°C, IF = 14A, VDD = 20V
di / d t = 100A/ µs
e
TJ = 25°C, IS = 14A, VGS = 0V
e
showing t he
integral revers e
p- n junction di ode.
VGS = 4.5V , ID = 14A
e
VGS = 4.5V
Typ.
–––
VDS = VGS, ID = 250µA
Clam ped I n duct ive Load
VDS = 20V, ID = 14A
VDS = 32V, VGS = 0V, TJ = 12 5°C
–––
ID = 14A
VGS = 0V
VDS = 20V
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Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
0.1 110 100
VDS, Dr ain-to- Source Voltage (V )
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
≤ 60µs PU LSE WIDTH
Tj = 25° C
2.5V
VGS
TOP 10V
5.0V
4.5V
3.5V
3.3V
3.0V
2.8V
BOTTOM 2.5V
0.1 110 100
VDS, Dr ain-to- Source Voltage (V )
1
10
100
1000
ID, Drain-to-Source Current (A)
≤ 60µs PU LSE WIDTH
Tj = 150° C
2.5V
VGS
TOP 10V
5.0V
4.5V
3.5V
3.3V
3.0V
2.8V
BOTTOM 2.5V
1.5 2.0 2.5 3.0 3.5 4.0
VGS, Gate-to-S ource Voltage (V)
0.1
1.0
10.0
100.0
1000.0
ID, Drain-to-Source Current (Α)
VDS = 25V
≤ 60µs PULSE WIDT H
TJ = 25°C
TJ = 150°C
-60 -40 -20 020 40 60 80 100 120 140 160
TJ , Junction Temperature (° C)
0.5
1.0
1.5
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 18A
VGS = 10V
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
110 100
VDS, Dr ain-to- Source Voltage (V )
100
1000
10000
100000
C, Capacitance (pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0 20406080
QG Total Gate Charge (nC)
0
2
4
6
8
10
12
VGS, Gate-to-Source Voltage (V)
VDS= 30V
VDS= 20V
ID= 14A
0.2 0.4 0.6 0.8 1.0 1.2
VSD, Source-to-D rain Voltage (V )
0.1
1.0
10.0
100.0
1000.0
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 150°C
VGS = 0V
0 1 10 100 1000
VDS , Dr ain-toSource Vol tage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 150° C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
IRF7842PbF
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
Fig 9. Maximum Drain Current Vs.
Case Temperature Fig 10. Threshold Voltage Vs. Temperature
25 50 75 100 125 150
TJ , Junction Temperature (° C)
0
2
4
6
8
10
12
14
16
18
ID , Drain Current (A)
-75 -50 -25 025 50 75 100 125 150
TJ , Temperature ( ° C )
0.4
0.8
1.2
1.6
2.0
2.4
VGS(th) Gate threshold Voltage (V)
ID = 250µA
1E-006 1E-005 0.0001 0.001 0.01 0.1 110 100
t1 , Rectangul ar Pulse D uration ( s ec)
0.0001
0.001
0.01
0.1
1
10
100
Thermal Response ( Z thJA )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
Ri (°C/W) τi (sec)
10.48 0.138167
26.83 1.8582
12.69 44.8
τJ
τJ
τ1
τ1τ2
τ2τ3
τ3
R1
R1R2
R2R3
R3
τ
τ
C
Ci= i/Ri
Ci= τi/Ri
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Fig 13c. Maximum Avalanche Energy
Vs. Drain Current
Fig 14a. Switching Time Test Circuit
Fig 14b. Switching Time Waveforms
VGS
VDS
9
0%
10%
td(on) td(off)
trtf
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
VDD
VDS
LD
D.U.T
+
-
Fig 13b. Unclamped Inductive Waveforms
Fig 13a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
Fig 12. On-Resistance Vs. Gate Voltage
2.0 4.0 6.0 8.0 10.0
VGS, Gate-to-S ource Voltage (V)
0
4
8
12
16
RDS(on), Drain-to -Source On Resistance (mΩ)
TJ = 25°C
TJ = 125°C
ID = 18A
25 50 75 100 125 150
Starti ng TJ, Junction T emperature ( °C)
0
40
80
120
160
200
EAS, Single Pulse Avalanche Energy (mJ)
ID
TOP 6.7A
7.5A
BOTTOM 14A
IRF7842PbF
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D.U.T. VD
S
ID
IG
3mA
VGS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 16. Gate Charge Test Circuit
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
R
e-Applied
V
oltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Fig 17. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
IRF7842PbF
8www.irf.com
SO-8 Package Outline
Dimensions are shown in millimeters (inches)
SO-8 Part Marking
e1
D
E
y
b
A
A1
H
K
L
.189
.1497
0°
.013
.050 BASIC
.0532
.0040
.2284
.0099
.016
.1968
.1574
8°
.020
.0688
.0098
.2440
.0196
.050
4.80
3.80
0.33
1.35
0.10
5.80
0.25
0.40
0°
1.27 BASIC
5.00
4.00
0.51
1.75
0.25
6.20
0.50
1.27
MIN MAX MILLIMETERSINCHES MIN MAX
DIM
8°
e
c .0075 .0098 0.19 0.25
.025 BASIC 0.635 BASIC
87
5
65
D B
E
A
e
6X
H
0.25 [.010] A
6
7
K x 45°
8X L 8X c
y
0.25 [.010] CAB
e1 A
A1
8X b
C
0.10 [.004]
4312
FOOTPRINT
8X 0.72 [.028]
6.46 [.255]
3X 1.27 [.050]
4. OUT LINE CONF ORMS T O JEDEC OUT LINE MS -012AA.
NOTES:
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994.
2. C ONTROLLING DIMENSION: MILLIMETER
3. DIME NSIONS ARE SHOWN IN MILLIMETERS [INCHES].
5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].
7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO
A SUBSTRATE.
MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].
8X 1.78 [.070
]
DATE CODE (YWW)
XXXX
INTERNATIONAL
RECTIFIER
LOGO
F7101
Y = LAST DIGIT OF THE YEAR
PART N UMBER
LOT CODE
WW = WEEK
EXAMPLE: THIS IS AN IRF7101 (MOSFET)
P = DES IGNAT ES LEAD-FREE
PRODUCT (OP TIONAL)
A = ASSEMBLY SITE CODE
IRF7842PbF
www.irf.com 9
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. O UTLINE CO NFORMS TO EIA-48 1 & EIA-54 1.
FEED DIRECTION
TE RM I NAL NUMBE R 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
N
OTES:
1
. CONTROLLING DIMENSION : MILLIMETER.
2
. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3
. OUTLI NE CONFOR M S T O EIA-481 & EIA-541.
SO-8 Tape and Reel
Dimensions are shown in millimeters (inches)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 0.5mH
RG = 25 Ω, IAS = 14A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
When mounted on 1 inch square copper board
Rθ is measured at TJ approximately 90°C
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualifications Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.09/04