Am27C080 8 Megabit (1,048,576 x 8-Bit) CMOS EPROM al Advanced Micro Devices DISTINCTIVE CHARACTERISTICS m@ Fast access time 100ns @ Low power consumption 100 yA maximum CMOS standby current @ JEDEC-approved pinout Plug in upgrade of 1-, 2-, 4-Mbit EPROMs Easy upgrade from 28-pin JEDEC EPROMs @ Single +5 V power supply GENERAL DESCRIPTION The Am27C080 is an 8 Mbit ultraviolet erasable pro- grammabie read-only memory. It is organized as 1,048K words by 8 bits per word, operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. Products are available in windowed ceramic DIP and LCC packages as well as plastic one time programmable (OTP) PDIP and PLCC packages. Typically, any byte can be accessed in less than 100 ns, allowing operation with high-performance microproces- sors without any WAIT states. The Am27C080 offers separate Output Enable (OE) and Chip Enable (CE) BLOCK DIAGRAM o_> Vcc o> Vss _ Output Enable OE/Vpp Chip Enable CE/PGM and P ic Y Decoder A0-A19 Address Inputs x Decoder m +10% power supply tolerance available M 100% Flashrite programming Typical programming time of less than 2 minutes @ Latch-up protected to 100 mA from 1 V to Veco+1V MH High noise immunity m Compact 32-pin DIP, PDIP, and PLCC packages controls, thus eliminating bus contention in a multiple bus microprocessor system. AMD's CMOS process technology provides high speed, low power, and high noise immunity. Typical power con- sumption is only 100 mW in active mode, and 100 pW in standby mode. All signals are TTL levels, including programming sig- nals. Bit locations may be programmed singly, in blocks, or at random. The Am27C080 supports AMDs Flashrite programming algorithm (100 ys pulses) resulting in typi- cal programming times of less than 2 minutes. Data Outputs DQ0-DQ7 (abana Output Buffers 8,388,608 Bit Cell Matrix 15453B-1 Publication# 15453 Rev.B Amendment/0 Issue Date: July 1993 This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. 2-145cl AMD PRODUCT SELECTOR GUIDE PRELIMINARY Family Part No. Am27C080 Ordering Part No: Vcc + 5% 105 -255 Vec + 10% -100 -120 -150 -200 -250 Max Access Time (ns) 100 120 150 200 250 CE (E) Access Time (ns) 100 120 150 200 250 OE (G) Access Time (ns) 50 50 65 75 100 CONNECTION DIAGRAMS Top View DIP PLCC ao Y1 2211 vec seee oeh at [] 2 31] A1s soe Ss Ais []3 30 [] A17 s 432 1 32 31 30 wet} fa a shoe A7 [ 5 28 "| A13 AS[] 7 27 [JA8 as [Is 27 1] As A4[]} 8 26 [JA9 a5 7 26 [] A9 A3[] 9 25 [At A4[]8 25 [] A11 AZT 10 o4 [JOE Gypp A3 [J 9 24 [] OE (GVpp aif] 11 23 [Jato A2 [} 10 23 [] A1o Ao[] 12 22 [CE (E)/PGM (P) Ai (11 22 [] CE (E)/PGM (P) Daof] 13 21 1]DQ7 Ao []} 12 21 {] Da7 14:15 16171819 20 J Dee is _20f] Das S8 88888 pat 14 19 f] Das qaar>aqgnada Da2 [J 1s 18 [] Das Vss [16 17 |] Das 15453B-3 Note: 15453B-2 1. JEDEC nomenciature is in parentheses. PIN DESIGNATIONS LOGIC SYMBOL A0-A19 = Address Inputs CE (E)/PGM (P) = Chip Enable 20 DQ0-DQ7 = Data Inputs/Outputs ri AO-A19 OE (G)/Vpp = Output Enable Input/ Program Supply Voltage 8 Vec = Vcc Supply Voltage DQ0-DQ7 </> Vss = Ground > CE (E)/PGM (P) >] OE (G)/Vep 15453B-4 2-146 Am27C080PRELIMINARY AMD &\ ORDERING INFORMATION EPROM Products AMD Standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27C080 -100 D Cc Le OPTIONAL PROCESSING Blank Standard Processing B Burn-in TEMPERATURE RANGE C = Commercial (0C to +70C) 1 Industrial (-40C to +85C) E = Extended Commercial (-55C to +125C) W PACKAGE TYPE D = 32-Pin Ceramic DIP (CDV032) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER Am27C080 8 Megabit (1,048,576 x 8-Bit) CMOS EPROM Valid Combinations Valid Combinations AM27C080-100 Valid Combinations list configurations planned to be AM27C080-105 DC, DI supported in volume for this device. Consult the lo- cal AMD sales office to confirm availability of specific AM27C080-120 DC, DCB, DI, DIB valid combinations and to check on newly released AM27C080-150 combinations. DC, DCB, DI, DIB, AM27C080-255 Am27C080 2-147al AMD PRELIMINARY ORDERING INFORMATION OTP Products AMD Standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27C080 -120 P Cc L_ OPTIONAL PROCESSING Blank = Standard Processing TEMPERATURE RANGE C = Commercial (0C to +70C) | = Industrial (40C to +85C) PACKAGE TYPE P = 32-Pin Plastic DIP (PD 032) J 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER Am27C080 8 Megabit (1,048,576 x 8-Bit) CMOS OTP EPROM Valid Combinations Valid Combinations AM27C080-120 AM27C080-125 AM27C080-200 AM27C080-255 Valid Combinations list configurations planned to be supported in volume for this device. Consult the lo- cal AMD sales office to confirm availability of specific AM27C080-150 PC, JC, Pl, Jl valid combinations and to check on newly released combinations. 2-148 Am27C080PRELIMINARY AMD & ORDERING INFORMATION Military APL Products AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APL (Approved Products List) products are fully compliant with MIL-STD-883 requirements. The order number (Valid Combination) is formed by a combination of: AM27C080 -150 /B X A [__ LEAD FINISH A = Hot Solder Dip PACKAGE TYPE X = 32-Pin Ceramic DIP (CDV032) DEVICE CLASS /B = Class B SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER Am27C080 8 Megabit (1,048,576 x 8-Bit) CMOS EPROM Valid Combinations Valid Combinations - Valid Combinations list configurations planned to be AM27C080-150 ~ IBXA supported in volume for this device. Consult the fo- AM27C080-200 cal AMD sales office to confirm availability of AM27C080-250 specific valid combinations and to check on newly released combinations. Group A Tests Group A tests consist of Subgroups 1, 2,3, 7, 8, 9, 10, 11. Am27C080 2-149cl AMD FUNCTIONAL DESCRIPTION Erasing the Am27C080 In order to clear all locations of their programmed con- tents, it is necessary to expose the Am27C080 to an ultraviolet light source. A dosage of 15 W seconds/cm?is required to completely erase an Am27C080. This dos- age can be obtained by exposure to an ultraviolet lampwavelength of 2537 Awith intensity of 12,000 LW/crr? for 15 to 20 minutes. The Am27C080 should be directly under and about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the Am27C080 and similar devices will erase with light sources having wavelengths shorter than 4000 A. Although erasure times will be much longer than with UV sources at 25374, exposure to fluorescent light and sunlight will eventually erase the Am27C080 and exposure to them should be prevented to realize maximum system reliability. If used in such an environment, the package window should be covered by an opaque label or substance. Programming the Am27C080 Upon delivery or after each erasure the Am27C080 has all 8,388,608 bits in the ONE or HIGH state. ZEROs are loaded into the Am27C080 through the procedure of programming. The programming mode is entered when 12.75 V + 0.25 V is applied to the OE/Vpp and CE/PGM is at Vit. For programming, the data to be programmed is applied 8 bits in parallel to the data output pins. The Flashrite algorithm reduces programming time by using 100 ys programming pulses and by giving each address only as many pulses as is necessary in order to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data does not verify, additional pulses are given until it verifies or the maximum is reached. This process is re- peated while sequencing through each address of the Am27C080. This part of the algorithm is done at Vcc = 6.25 V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. After the final ad- dress is completed, the entire EPROM memory is veri- tied at Vcc = Vpp = 5.25 V. Please refer to Section 6.0 for programming flow charts and characteristics. Program Inhibit Programming of multiple Am27C080 in parallel with dif- ferent data is also easily accomplished. Except for CE/PGM, all like inputs of the parallel Am27C080 may be common. A TTL low-level program pulse applied to an Am27C080 CE/PGM input and OE/Vep = 12.75 V + PRELIMINARY 0.25 V, will program that Am27C080. A high-level CE/PGM input inhibits the other Am27C080 devices from being programmed. Program Verify Averify should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with CE/PGM at Vit and OE/Vpr at ViL. Auto Select Mode The auto select mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25C + 5C ambient temperature range that is required when programming the Am27C080. To activate this mode, the programming equipment must force 12.0 V + 0.5 V open address the AQ of the Am27C080. Two identifier bytes may then be se- quenced from the device outputs by toggling address line AO from Vit to Vin. All other address lines must be held at Vi. during auto select mode. Byte 0 (Ao = Vi_) represents the manufacturer code, and byte 1 (AO = Vin), the device code. For the Am27C080, these two identifier bytes are given in the Mode Select Table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. Read Mode The Am27C080 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE/PGM) is the power control and should be used for device selection. Output Enable (OE/Vep) is the output control and should be used to gate data to the output pins, independent of device se- lection. Assuming that addresses are stable, address access time (tacc ) is equal to the delay from CE/PGM to output (tce). Data is available at the outputs toe after the falling edge of OE/Vpp, assuming that CE/PGM has been LOW and addresses have been stable for at least tacc -toe. Standby Mode The Am27C080 has a CMOS standby mode which re- duces the maximum Vcc current to 100 1A. It is placed in CMOS-standby when CE/PGM is at Vcc + 0.3 V. The Am27C080 also has a TTL-standby mode which re- duces the maximum Vcc current to 1.0 mA. It is placed in TTL-standby when CE/PGNM is at Vin. When in standby mode, the outputs are in a high-impedance state, inde- pendent of the OE/Vpr input. 2-150 Am27C080PRELIMINARY Output OR-Tieing To accommodate multiple memory connections, a two- line control function is provided to allow for: m@ Low memory power dissipation Assurance that output bus connection will not occur It is recommended that CE/PGM be decoded and used as the primary device-selecting function, while OE/Vpp be made a common connection to all devices in the ar- ray and connected to the READ line from the system control bus. This assures that all deselected memory devices are in low-power standby mode and that the output pins are only active when data is desired froma particular memory device. AMD cl System Applications During the switch between active and standby condi- tions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the out- put capacitance loading of the device. At a minimum, a 0.1-~F ceramic capacitor (high frequency, low inherent inductance) should be used on each device between Vcc and Vss to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive ef- fects of the printed circuit board traces on EPROM ar- rays, a 4.7-1F bulk electrolytic capacitor should be used between Vcc and Vss for each eight devices. The loca- tion of the capacitor should be close to where the power supply is connected to the array. MODE SELECT TABLE Mode Pins| CE/PGM OE/Vpp AO AS Outputs Read Vit ViL AO AQ DouT Output Disable X VIH X X Hi-Z Standby (TTL) VIH X xX X Hi-Z Standby (CMOS) Vcc +0.3 V X Xx X Hi-Z Program VIL Vepp AQ AQ DIN Program Verify ViL ViL X X Dout Program Inhibit VIH Vpp X X Hi-Z Manufacturer Auto Select Code Vit Vit VIL VH 01H (Note 3) Device Code VIL VIL Vin VH 1CH Notes: 1. Vn =12.0405V 2. X = Either Vin or Viz 3. A1l-A8 = A10-A19 = Vie 4 . See DC Programming Characteristics for Vep voltage during programming. Am27C080 2-151cl AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature OTP Products ............... 65C to +125C All Other Products ............ -65C to +150C Ambient Temperature with Power Applied ............. ~55C to +125C Voltage with Respect To Vss All pins except AQ, Vep,Veco .. ee. eee eee 0.6 V to Vcc + 0.6 V AQ and Vpp .......-.....005. 0.6Vt0+13.5V Voo oc ee eee eee -0.6Vto+7.0V Notes: 1, Minimum DC voltage on input or VO pins is -0.5 V. During transitions, the inputs may overshoot Vss to 2.0 V for pe- riods of up to 20 ns. Maximum DC voltage on input and /O pins is Vcc + 0.5 V which may overshoot to Vcc + 2.0 V for periods up to 20ns. 2. For A9 and Vep the minimum DC input is -0.5 V. During transitions, AQ and Veep may overshoot Vss to -2.0 V for periods of up to 20 ns. A9 and Vpp must not exceed 13.5 V for any period of time. Stresses above those listed under Absolute Maximum Rat- ings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicatd in the opera- tional sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for ex- tended periods may affect device reliability. PRELIMINARY OPERATING RANGES Commercial (C) Devices Case Temperature (Tc).......... 0C to +70C Industrial (1) Devices Case Temperature (Tc)........ 40C to +85C Extended Commercial (E) Devices Case Temperature (Tc)....... 55C to +125C Military (M) Devices Case Temperature (Tc)....... 55C to +125C Supply Read Voltages Vec for AmM27C080-XX5 ..... +4.75 V to +5.25 V Voc for AM27C080-XX0 ..... +4.50 V to +5.50 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. 2-152 Am27C080PRELIMINARY DC CHARACTERISTICS over operating range unless otherwise specified. AMD al (Notes 1, 2 and 4) (for APL Products, Group A, Subgroups 1, 2, 3, 6 and 7 are tested un- less otherwise noted) Parameter Symbol | Parameter Description Test Conditions Min Max Unit VoH Output HIGH Voltage loH = 400 LA 2.4 V VoL Output LOW Voltage lo. = 2.1 mA 0.45 V ViH Input HIGH Voltage 2.0 Veco +05} V Vit Input LOW Voltage -0.5 +0.8 V It Input Load Current Vin = 0 V to +Vcc 1.0 pA ILo Output Leakage Current VouT = 0 V to +Vcc 5.0 LA Ice Vcc Active Current CE = Vit, f= 5 MHz, Cil Devices 40 yA (Note 3) louT = 0 mA E/M Devices 50 Icc2 Vcc TTL Standby Current |CE = Vin 1.0 mA lees Vcc CMOS Standby Current|CE = Vcc + 0.3 V 100 yA Ipp1 Vep Current During Read |CE = OE = VIL, Vpp = Vcc 100 pA Notes: 1. Vcc must be applied simultaneously or before Vpp, and removed simultaneously or after Vpp. . Caution: The Am27C080 must not be removed from (or inserted into) a socket when Vcc or Vpp is applied. 2. 3. Icc1 is tested with OE/Vpp = Viti to simulate open outputs. 4 . Minimum DC Input Voltage is -0.5 V. During transitions, the inputs may overshoot to -2.0 V for periods less than 20 ns. Maximum DC Voltage on output pins is Vcc + 0.5 V, which may overshoot to Vcc + 2.0 V for periods less than 20 ns. 40 40 35 HA 35 as a 25 S25 =) rv a rh] n L n MN 20 7 | 20 15 15 1 2 3 4 5 6 7 8 9 10 -7 -50-25 0 25 50 75 100 125 150 Frequency in MHz Temperature in C Figure 1. Typical Supply Current Figure 2. Typical Supply Current vs. Frequency vs. Temperature Vcc = 5.5 V, T = 25C Vec = 5.5 V,f=5 MHz 15453B-5 15453B-6 Am27C080 2-1531 amp PRELIMINARY CAPACITANCE Parameter CDV032 PL 032 PD 032 Symbol Parameter Description | Test Conditions Typ | Max | Typ | Max | Typ | Max | Unit CIN Input Capacitance Vin =0 7 12 7 12 7 12 pF Cout Output Capacitance VouT = 0 12 16 12 16 12 16 pF Notes: 1. This parameter is only sampled and not 100% tested. 2. Ta = 425C, f = 1 MHz SWITCHING CHARACTERISTICS over operating range unless otherwise specified (Notes 1, 3 and 4) (for APL Products, Group A, Subgroups 9,10 and 11 are tested unless otherwise noted) Parameter Am27C080 Symbols Parameter Test -105 -255 JEDEC | Standard | Description Conditions -100 | -120 | -150 | -200 | -250 | Unit tavav tacc Address to CE = OE = Min - = = = = Output Delay VIL Max | 100 | 120 | 150 | 200 | 250 ns tELav tCE Chip Enable to OE = Vit Min - - - - - Output Delay Max | 100 | 120 | 150 200 | 250 ns teLav toe Output Enable to CE = Vit Min - = - - - Output Delay . Max 50 50 55 60 60 ns teHaz toF Chip Enable HIGH or Min = = = = = tGHQZ (Note 2) | Output Enable HIGH, Max 40 40 40 40 60 ns whichever comes first, to Output Float tAxax tOH Output Hold from Min 0 0 0 0 0 Addresses, CE, Max - - ~ - - ns or OE, whichever occurred first Notes: 1. Vec must be applied simultaneously or before Vpp, and removed simultaneously or after Vpp. This parameter is only sampled and not 100% tested. 2 3. Caution: The Am27C080 must not be removed from (or inserted into) a socket or board when Vpp or Vcc is applied. 4 . Output Load: 1 TTL gate and C, = 100 pF Input Rise and Fall Times: 20 ns Input Pulse Levels: 0.45 V to 2.4 V Timing Measurement Reference Level: 0.8 V and 2 V inputs and outputs 2-154 Am27C080PRELIMINARY AMD ol SWITCHING TEST CIRCUIT 2.7 kQ Device Under Test +5.0 V Diodes = IN3064 or Equivalent Ci = 100 pF including jig capacitance 15453B-7 SWITCHING TEST WAVEFORM 2.4V 2.0V 2.0V Test Points 0.8V 0.8 V 0.45 V Input Output AC Testing: Inputs are driven at 2.4 V for a logic 1 and 0.45 V for a logic 0. Input pulse rise and fall times are < 20 ns. 15453B-8 Am27C080 2-155cl AMD PRELIMINARY KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must Be Will Be Steady Steady May Will Be Change Changing from H to L from H to L May Will Be Change Changing from L to H from L to H Dont Care Changing Any Change State Permitted Unknown Does Not Center Apply Line is High Impedence Off State KS000010 SWITCHING WAVEFORMS 2.4 | Addresses X Addresses Valid k 0.45 +_0. 0. ___ CE/PGM \ tte re OE/Vpp \ | _ {DF t toe ~ ns | (Note 2) ACC tOH . Note 1) . High Z 4 High Z Output {(( { Valid Output by) jp Notes: 15453B-9 1. OE/Vpp may be delayed up to tacc toe after the falling edge of the addresses without impact on tacc. 2. toe is specified from OF or CE, whichever occurs first. 2-156 Am27C080