IRF9520 Data Sheet January 2002 6A, 100V, 0.600 Ohm, P-Channel Power MOSFET Features * 6A, 100V This advanced power MOSFET is designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. These are P-Channel enhancement mode silicon gate power field effect transistors designed for applications such as switching regulators, switching converters, motor drivers, relay drivers and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. * rDS(ON) = 0.600 Formerly developmental type TA17501. Symbol * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance D Ordering Information PART NUMBER IRF9520 PACKAGE TO-220AB BRAND G IRF9520 NOTE: When ordering, use the entire part number. S Packaging JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) (c)2002 Fairchild Semiconductor Corporation IRF9520 Rev. B IRF9520 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC =100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor (Figure 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRF9520 -100 -100 -6 -4 -24 20 40 0.32 370 -55 to 150 UNITS V V A A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to TJ = 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER BVDSS ID = -250A, VGS = 0V (Figure 10) -100 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = -250A -2 - -4 V VDS = Rated BVDSS, VGS = 0V - - -25 A VDS = 0.8 x Rated BVDSS, VGS = 0V TC = 125oC - - -250 A VDS > ID(ON) x rDS(ON) MAX, VGS = -10V -6 - - A VGS = 20V - - 100 nA Zero Gate Voltage Drain Current SYMBOL IDSS On-State Drain Current (Note 2) ID(ON) Gate to Source Leakage Current IGSS Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge rDS(ON) gfs td(ON) tr td(OFF) 0.500 0.600 2 - S VDD = 0.5 x Rated BVDSS, ID -6.0A, RG = 50 , RL = 7.7 for VDSS = 50 MOSFET Switching Times are Essentially Independent of Operating Temperature - 25 50 ns - 50 100 ns - 50 100 ns - 50 100 ns VGS = -10V, ID = -6A, VDS = 0.8 x Rated BVDSS (Figure 14) Gate Charge is Essentially Independent of Operating Temperature - 16 22 nC - 9 - nC tf Qg(TOT) Qgs Gate to Drain "Miller" Charge Qgd Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Internal Drain Inductance 0.9 ID = -3.5A, VGS = -10V (Figures 8, 9) VDS > ID(ON) x rDS(ON)MAX, ID = -3.5A ( Figure 12) LD VDS = -25V, VGS = 0V, f = 1MHz (Figure 11) Measured From the Modified MOSFET Contact Screw on Tab To Symbol Showing the Center of Die Internal Devices Measured From the Drain Inductances D Lead, 6mm (0.25in) from Package to Center of Die Internal Source Inductance LS Measured From the Source Lead, 6mm (0.25in) From Header to Source Bonding Pad - 7 - nC - 300 - pF - 200 - pF - 50 - pF - 3.5 - nH - 4.5 - nH - 7.5 - nH - - 3.12 oC/W - - 62.5 oC/W LD G LS S Thermal Resistance Junction-to-Case RJC Thermal Resistance Junction-to-Ambient RJA (c)2002 Fairchild Semiconductor Corporation Typical Socket Mount IRF9520 Rev. B IRF9520 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current MIN TYP MAX - - -6.0 A - - -24 A TC = 25oC, ISD = -6.0A, VGS = 0V (Figure 13) - - -1.5 V trr TJ = 150oC, ISD = -6.0A, dISD/dt = 100A/s - 230 - ns QRR TJ = 150oC, ISD = -6.0A, dISD/dt = 100A/s - 1.3 - C ISD Pulse Source to Drain Current (Note 3) ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode UNITS D G S Source to Drain Diode Voltage (Note 2) VSD Reverse Recovery Time Reverse Recovery Charge NOTES: 2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 25V, starting TJ = 25oC, L = 15.4mH, RG = 25, peak IAS = 6.0A. Typical Performance Curves Unless Otherwise Specified 6.0 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 0.2 4.8 3.6 2.4 1.2 0 0.0 0 25 50 75 100 TA , CASE TEMPERATURE (oC) 125 25 150 125 100 150 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE ZJC, NORMALIZED TRANSIENT THERMAL IMPEDANCE 75 50 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1 0.5 PDM 0.2 0.1 0.1 t1 t2 0.05 0.02 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 1 10 t 1, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED TRANSIENT THERMAL IMPEDANCE (c)2002 Fairchild Semiconductor Corporation IRF9520 Rev. B IRF9520 Typical Performance Curves Unless Otherwise Specified (Continued) -10 VGS = -9V VGS = -10V 10s 100s 1ms OPERATION IN THIS AREA IS LIMITED BY rDS(ON) 1 10ms 100ms DC ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) -8 10 -6 1 VGS = -7V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. -4 VGS = -6V -2 TC = 25oC TJ = MAX RATED 0.1 VGS = -8V VGS = -5V VGS = -4V 0 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 0 FIGURE 4. FORWARD BIAS SAFE OPERATING AREA -10 VGS = -7V VGS = -8V -4 ID(ON), ON-STATE DRAIN CURRENT (A) ID, DRAIN CURRENT (A) -50 FIGURE 5. OUTPUT CHARACTERISTICS -5 VGS = -9V VGS = -10V -3 VGS = -6V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. -2 VGS = -5V -1 VGS = -4V 0 VDS I D(ON) x rDS(ON) MAX PULSE DURATION = 80s -8 DUTY CYCLE = 0.5% MAX. TJ = 125oC TJ = 25oC -6 TJ = -55oC -4 -2 0 0 -2 -3 -4 -1 VDS, DRAIN TO SOURCE VOLTAGE (V) -5 0 FIGURE 6. SATURATION CHARACTERISTICS -10 2.2 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. 1.6 1.2 VGS = -10V 0.8 0.4 0 -2 -4 -6 -8 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 7. TRANSFER CHARACTERISTICS 2.0 rDS(ON), DRAIN TO SOURCE ON RESISTANCE () -10 -20 -30 -40 VDS, DRAIN TO SOURCE VOLTAGE (V) VGS = -20V VGS = -10V, ID = -4A PULSE DURATION = 80s 1.8 DUTY CYCLE = 0.5% MAX. 1.4 1.0 0.6 0.2 0 -5 -10 -15 ID, DRAIN CURRENT (A) -20 -25 FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT (c)2002 Fairchild Semiconductor Corporation -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE IRF9520 Rev. B IRF9520 Typical Performance Curves Unless Otherwise Specified (Continued) 500 1.25 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD 400 1.15 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A 1.05 0.95 CISS 300 0.85 0.75 -40 0 40 80 120 200 COSS 100 CRSS 0 160 -10 0 TJ , JUNCTION TEMPERATURE (oC) ISD, DRAIN CURRENT (A) gfs, TRANSCONDUCTANCE (S) -50 -100 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. 2 TJ = -55oC TJ = 25oC TJ = 125oC 1 -2 -40 FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 3 0 -30 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 0 -20 -4 -6 ID , DRAIN CURRENT (A) -8 -10 TJ = 25oC -1.0 -0.1 -0.4 -10 TJ = 150oC -0.8 -0.6 -1.0 -1.2 -1.4 -1.6 -1.8 VSD, SOURCE TO DRAIN VOLTAGE (V) FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 0 VGS, GATE TO SOURCE (V) ID = -6A -5 VDS = -80V -10 VDS = -50V VDS = -20V 0 4 8 12 16 20 Qg(TOT) , TOTAL GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE (c)2002 Fairchild Semiconductor Corporation IRF9520 Rev. B IRF9520 Test Circuits and Waveforms VDS tAV L 0 VARY tP TO OBTAIN - RG REQUIRED PEAK IAS + VDD DUT 0V VDD tP VGS IAS IAS VDS tP 0.01 BVDSS FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(OFF) td(ON) tr 0 RL - DUT VGS + 10% 10% VDS VDD RG tf VGS 0 90% 90% 10% 50% 50% PULSE WIDTH 90% FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS -VDS (ISOLATED SUPPLY) CURRENT REGULATOR 0 VDS DUT 12V BATTERY 0.2F 50k 0.3F Qgs Qg(TOT) DUT G VGS Qgd D VDD 0 S IG(REF) IG CURRENT SAMPLING RESISTOR +VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT (c)2002 Fairchild Semiconductor Corporation 0 IG(REF) FIGURE 20. GATE CHARGE WAVEFORMS IRF9520 Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM FAST FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET VCXTM STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4