PIC16(L)F1777/8/9 28/40/44-Pin, 8-Bit Flash Microcontroller Description PIC16(L)F1777/8/9 microcontrollers feature a high level of integration of intelligent analog and digital peripherals for a wide range of applications, such as lighting, power supplies, battery charging, motor control and other general purpose applications. These devices deliver multiple op amps, 5-/10-bit DACs, high-speed comparators, 10-bit ADC, 10-/16-bit PWMs, programmable ramp generator (PRG) and other peripherals that can be connected internally to create closedloop systems without using pins or the printed circuit board (PCB) area. The 10-/16-bit PWMs, digital signal modulators and tri-state output op amp can be used together to create a LED dimming engine for lighting applications. The peripheral pin select (PPS) functionality provides flexibility, eases PCB layout and peripheral utilization by allowing digital peripheral pin mapping to an I/O. Core Features eXtreme Low-Power (XLP) Features * C Compiler Optimized RISC Architecture * Only 49 Instructions * Operating Speed: - DC - 32 MHz clock input - 125 ns minimum instruction cycle * Interrupt Capability * 16-Level Deep Hardware Stack * Five 8-Bit Timers * Three 16-Bit Timers * Low-Current Power-on Reset (POR) * Configurable Power-up Timer (PWRT) * Brown-out Reset (BOR) with Selectable Trip Point * Extended Watchdog Timer (EWDT): - Low-power 31 kHz WDT - Software selectable prescaler - Software selectable enable * * * * Memory * * * * Up to 28 Kbytes Program Flash Memory (PFM) Up to 2 Kbytes Data RAM Direct, Indirect and Relative Addressing modes High-Endurance Flash (HEF): - 128B of nonvolatile data storage - 100K Erase/Write cycles Operating Characteristics * Operating Voltage Range: - 1.8V to 3.6V (PIC16LF1777/8/9) - 2.3V to 5.5V (PIC16F1777/8/9) * Temperature Range: - Industrial: -40C to 85C - Extended: -40C to 125C 2015-2016 Microchip Technology Inc. Sleep mode: 50 nA @ 1.8V, typical Watchdog Timer: 500 nA @ 1.8V, typical Secondary Oscillator: 500 nA @ 32 kHz Operating Current: - 8 uA @ 31 kHz, 1.8V, typical - 32 uA/MHz @ 1.8V, typical Intelligent Analog Peripherals * 10-Bit Analog-to-Digital Converter (ADC): - Up to 28 external channels - Conversion available during Sleep * Four Operational Amplifiers (OPA): - Selectable internal and external channels - Tri-state output - Part of LED dimming engine - Selectable internal and external channels * Eight High-Speed Comparators (HS Comp): - Up to nine external inverting inputs - Up to 12 external non-inverting inputs - Fixed Voltage Reference at inverting and non-inverting input(s) - Comparator outputs externally accessible * Digital-to-Analog Converters (DAC): - Four 10-bit resolution DACs - 10-bit resolution, rail-to-rail - Conversion during Sleep - Internal connections to ADCs and HS Comparators * Voltage Reference: - Fixed Voltage Reference (FVR) - 1.024V, 2.048V and 4.096V output levels * Zero-Cross Detector (ZCD): - Detect high-voltage AC signal * Four Programmable Ramp Generators (PRG): - Slope compensation - Ramp generation * High-Current Drive I/Os: - Up to 100 mA sink or source @ 5V DS40001819B-page 1 PIC16(L)F1777/8/9 - I/O remapping of digital peripherals * Serial Communications: - Enhanced USART (EUSART) - SPI, I2C, RS-232, RS-485, LIN compatible - Auto-Baud Detect, auto-wake-up on start * Up to 25 I/O Pins: - Individually programmable pull-ups - Slew rate control - Interrupt-on-change with edge-select Digital Peripherals * Four Configurable Logic Cells (CLC): - Integrated combinational and state logic * Four Complementary Output Generators (COG): - Push-pull, Full-Bridge and Steering modes * Four Capture/Compare/PWM (CCP) Modules * Pulse-Width Modulator (PWM): - Four 16-bit PWMs - Independent timers - Multiple output modes (Edge-, CenterAligned, set and toggle on register match) - User settings for phase, duty cycle, period, offset and polarity - 16-bit timer capability - Three 10-bit PWMs * Digital Signal Modulator (DSM): - Modulates a carrier signal with a digital data to create custom carrier synchronized output waveforms - Part of LED dimming engine * Peripheral Pin Select (PPS): * Precision Internal Oscillator: - 1% at calibration - Selectable frequency range 32 MHz to 31 kHz * 31 kHz Low-Power Internal Oscillator * 4x Phase-Locked Loop (PLL) for up to 32 MHz Internal Operation * External Oscillator Block with Three External Clock modes up to 32 MHz Device Program Flash Memory (bytes) Program Flash Memory (word) High Endurance Flash (B) Data SRAM (Bytes) I/O Pins(1) 8-Bit/16-Bit Timers High-Speed Comparator 10-bit ADC (ch) 5/10-bit DAC CCP 10-bit/16-bit PWM COG CLC Op Amp Zero Cross Detect Programmable Ramp Gen High-Current I/Os Peripheral Pin Select EUSART I2C/SPI Debug(2) PIC16(L)F1773/6/7/8/9 FAMILY TYPES Data Sheet Index TABLE 1: Clocking Structure PIC16(L)F1773 (A) 7K 4K 128 512 25 5/3 6 17 3/3 3 3/3 3 4 3 1 3 2 Y 1 1 I PIC16(L)F1776 (A) 14K 8K 128 1K 25 5/3 6 17 3/3 3 3/3 3 4 3 1 3 2 Y 1 1 I PIC16(L)F1777 (B) 14K 8K 128 1K 36 5/3 8 28 4/4 4 4/4 4 4 4 1 4 2 Y 1 1 I PIC16(L)F1778 (B) 28K 16K 128 2K 25 5/3 6 17 3/3 3 3/3 3 4 3 1 3 2 Y 1 1 I PIC16(L)F1779 (B) 28K 16K 128 2K 36 5/3 8 28 4/4 4 4/4 4 4 4 1 4 2 Y 1 1 I Note 1: 2: One pin is input-only. I - Debugging integrated on chip. Data Sheet Index: A: B: Note: DS40001810 DS40001819 PIC16(L)F1773/6 Data Sheet, 28-Pin, 8-bit Flash Microcontrollers PIC16(L)F1777/8/9 Data Sheet, 28/40/44-Pin, 8-bit Flash Microcontrollers For other small form-factor package availability and marking information, please visit http://www.microchip.com/packaging or contact your local sales office. DS40001819B-page 2 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 2: PACKAGES Packages PIC16(L)F1778 SPDIP PIC16(L)F1777/9 Note: PDIP SOIC SSOP UQFN QFN TQFP Pin details are subject to change. 2015-2016 Microchip Technology Inc. DS40001819B-page 3 PIC16(L)F1777/8/9 PIN DIAGRAMS 28-PIN SPDIP, SOIC, SSOP 1 28 RB7/ICSPDAT RA0 2 27 RB6/ICSPCLK RA1 3 26 RB5 RA2 4 25 RB4 RA3 5 6 24 23 RB3 RA4 22 21 RB1 RB0 20 VDD 19 VSS 18 RC7 RC6 VPP/MCLR/RE3 RA5 VSS 7 RA7 9 RA6 10 RC0 11 8 RC1 12 RC2 13 16 RC5 14 15 RC4 See Table 3 for location of all peripheral functions. 28-PIN UQFN (6x6x0.5 mm) RA1 RA0 RE3/MCLR/VPP RB7/ICSPDAT RB6/ICSPCLK RB5 RB4 FIGURE 2: RB2 17 RC3 Note: PIC16(L)F1778 FIGURE 1: 28 27 26 25 24 23 22 RA2 RA3 RA4 RA5 VSS RA7 RA6 1 2 3 4 5 6 7 PIC16(L)F1778 21 20 19 18 17 16 15 RB3 RB2 RB1 RB0 VDD VSS RC7 Note: RC1 RC2 RC3 RC4 RC5 RC6 RC0 8 9 10 11 12 13 14 See Table 3 for location of all peripheral functions. DS40001819B-page 4 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 40-PIN PDIP VPP/MCLR/RE3 1 40 RB7/ICSPDAT RA0 2 39 RB6/ICSPCLK RA1 3 38 RB5 RA2 4 37 RB4 RA3 5 36 RB3 RA4 6 35 RB2 RA5 RE0 7 34 8 33 RB1 RB0 RE1 9 RE2 10 VDD 11 VSS 12 RA7 13 RA6 VDD 31 VSS 30 RD7 29 RD6 28 RD5 14 27 RD4 15 26 RC7 RC1 16 25 RC6 RC2 17 24 RC5 RC3 18 23 RC4 19 22 RD3 21 RD2 RD1 20 See Table 4 for location of all peripheral functions. 40-PIN UQFN (5x5x0.5 mm) RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 FIGURE 4: 32 RC0 RD0 Note: PIC16(L)F1777/9 FIGURE 3: RC7 1 RD4 2 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 40 39 38 37 36 35 34 33 32 31 30 3 4 5 6 RC0 29 RA6 28 RA7 27 VSS PIC16(L)F1777/9 7 26 VDD 25 RE2 24 RE1 23 RE0 8 9 22 RA5 21 RA4 10 Note: VPP/MCLR/RE3 RA0 RA1 RA2 RA3 RB3 RB4 RB5 ICSPCLK/RB6 ICSPDAT/RB7 11 12 13 14 15 16 17 18 19 20 See Table 4 for location of all peripheral functions. 2015-2016 Microchip Technology Inc. DS40001819B-page 5 PIC16(L)F1777/8/9 44-PIN TQFP (10x10 mm) RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 NC FIGURE 5: RC7 RD4 1 2 3 4 5 6 7 8 9 10 11 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 RB3 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 PIC16(L)F1777/9 27 26 25 24 23 NC RC0 RA6 RA7 VSS VDD RE2 RE1 RE0 RA5 RA4 Note: RD2 RD1 RD0 RC3 RC2 RC1 RC0 40 39 38 37 36 35 34 RC4 RD3 41 43 42 RC6 RC5 44 44-PIN QFN (8X8 mm) RC7 1 33 RA6 RD4 2 32 RA7 RD5 3 31 N/C RD6 4 30 AVSS RD7 5 29 N/C VSS 6 28 VDD PIC16F1777/9 21 22 RA2 RA3 RA4 RA1 23 20 11 19 RB2 18 RA5 RA0 24 VPP/MCLR/RE3 10 17 RE0 RB1 16 25 ICSPDAT/RB7 9 ICSPCLK/RB6 RE1 RB0 15 RE2 26 RB5 27 8 13 14 7 12 VDD AVDD N/C RB4 FIGURE 6: See Table 4 for location of all peripheral functions. RB3 Note: NC RB4 RB5 ICSPCLK/RB6 ICSPDAT/RB7 VPP/MCLR/RE3 AN0/RA0 AN1/RA1 RA2 RA3 NC 12 13 14 15 16 17 18 19 20 21 22 See Table 4 for location of all peripheral functions. DS40001819B-page 6 2015-2016 Microchip Technology Inc. VREF DAC Op Amp ZCD PRG Timers PWM CCP COG CLC Modulator EUSART MSSP Interrupt Pull-ups High Current Basic 2 27 AN0 -- -- -- C1IN0C2IN0C3IN0C4IN0C5IN0C6IN0- -- -- -- -- -- -- CLCIN0(1) -- -- -- IOC Y -- -- RA1 3 28 AN1 -- -- OPA1OUT OPA2IN1+ OPA2IN1- C1IN1C2IN1C3IN1C4IN1- -- PRG1IN0 PRG2IN1 -- -- -- -- CLCIN1(1) -- -- -- IOC Y -- -- RA2 4 1 AN2 VREF- DAC1REF0DAC2REF0DAC3REF0DAC4REF0DAC5REF0DAC7REF0- DAC1OUT1 -- C1IN0+ C2IN0+ C3IN0+ C4IN0+ C5IN0+ C6IN0+ -- -- -- -- -- -- -- -- -- -- IOC Y -- -- RA3 5 2 AN3 VREF+ DAC1REF0+ DAC2REF0+ DAC3REF0+ DAC4REF0+ DAC5REF0+ DAC7REF0+ -- -- C1IN1+ -- -- -- -- -- -- -- MD1CL(1) -- -- IOC Y -- -- RA4 6 3 -- -- DAC4OUT1 OPA1IN0+ -- -- PRG1R(1) T0CKI -- -- -- -- MD1CH(1) -- -- IOC Y -- -- (1) -- -- -- -- -- MD1MOD(1) -- SS IOC Y -- -- Comparator ADC RA0 RA5 7 4 AN4 -- DAC2OUT1 OPA1IN0- -- -- PRG1F RA6 10 7 -- -- -- -- C6IN1+ -- -- -- -- -- -- -- -- -- -- IOC Y -- OSC2 CLKOUT RA7 9 6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IOC Y -- OSC1 CLKIN RB0 21 18 AN12 -- -- -- C2IN1+ ZCD -- -- -- -- COG1IN(1) -- -- -- -- IOC INT Y HIB0 -- -- -- -- -- IOC Y HIB1 -- DS40001819B-page 7 RB1 22 19 AN10 -- -- OPA2OUT OPA1IN1+ OPA1IN1- C1IN3C2IN3C3IN3C4IN3- -- PRG2IN0 PRG1IN1 -- -- -- COG2IN(1) RB2 23 20 AN8 -- DAC3OUT1 OPA2IN0- -- -- -- -- -- -- COG3IN(1) -- -- -- -- IOC Y -- -- RB3 24 21 AN9 -- -- OPA2IN0+ C1IN2C2IN2C3IN2- -- -- -- -- -- -- -- MD3CL(1) -- -- IOC Y -- -- Note 1: 2: 3: Default peripheral input. Input can be moved to any other pin with the PPS input selection register. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. PIC16(L)F1777/8/9 28-Pin UQFN 28-PIN ALLOCATION TABLE (PIC16(L)F1778) 28-Pin SPDIP/SOIC/SSOP TABLE 3: I/O 2015-2016 Microchip Technology Inc. PIN ALLOCATION TABLES Modulator EUSART MSSP Interrupt T5G -- -- -- -- MD3CH(1) -- -- IOC Y -- -- -- T1G -- CCP7(1) -- -- MD3MOD(1) -- -- IOC Y -- -- RB6 27 24 -- DAC5REF1+ DAC7REF1+ -- -- C4IN1+ -- -- -- -- -- -- CLCIN2(1) -- -- -- IOC Y -- ICSPCLK RB7 28 25 -- -- DAC1OUT2 DAC2OUT2 DAC3OUT2 DAC4OUT2 DAC5OUT2 DAC7OUT2 -- C5IN1+ -- -- T6IN(1) -- -- -- CLCIN3(1) -- -- -- IOC Y -- ICSPDAT RC0 11 8 -- -- DAC5OUT1 -- -- -- -- T1CKI(1) T3CKI(1) T3G(1) SOSCO -- -- -- -- -- -- -- IOC Y -- -- RC1 12 9 -- -- DAC7OUT1 -- -- -- PRG2R(1) SOSCI -- CCP2(1) -- -- -- -- -- IOC Y -- -- T5CKI -- CCP1(1) -- -- -- -- -- IOC Y -- -- Basic CLC -- -- High Current COG -- C4IN2- Pull-ups CCP C3IN1+ -- PWM -- -- Timers -- DAC5REF1DAC7REF1- PRG Comparator -- AN13 ZCD Op Amp AN11 23 DAC 22 26 VREF 25 ADC 28-Pin UQFN RB4 RB5 I/O 28-Pin SPDIP/SOIC/SSOP 28-PIN ALLOCATION TABLE (PIC16(L)F1778) (CONTINUED) 2015-2016 Microchip Technology Inc. RC2 13 10 AN14 -- -- -- C5IN2C6IN2- -- PRG2F(1) RC3 14 11 AN15 -- -- -- C1IN4C2IN4C3IN4C4IN4C5IN4C6IN4- -- -- T2IN(1) -- -- -- -- MD2CL(1) -- SCL IOC Y -- -- RC4 15 12 AN16 -- -- -- C5IN3C6IN3- -- PRG3R(1) T8IN(1) -- -- -- -- MD2CH(1) -- SDA IOC Y -- -- RC5 16 13 AN17 -- -- OPA3IN0+ -- -- PRG3F(1) T4IN(1) -- -- -- -- MD2MOD(1) -- -- IOC Y -- -- RC6 17 14 AN18 -- -- OPA3OUT C5IN1C6IN1- -- PRG3IN0 -- -- -- -- -- -- -- -- IOC Y -- -- RC7 18 15 AN19 -- -- OPA3IN0- -- -- -- -- -- -- -- -- -- -- -- IOC Y -- -- RE3 1 26 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IOC -- -- MCLR VPP VDD 20 17 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDD VSS 8 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VSS VSS 19 16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VSS Note 1: 2: 3: Default peripheral input. Input can be moved to any other pin with the PPS input selection register. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. PIC16(L)F1777/8/9 DS40001819B-page 8 TABLE 3: Note 1: 2: 3: CLC1OUT CLC2OUT CLC3OUT CLC4OUT MD1OUT MD2OUT MD3OUT DT(3) TX CK SDO SDA(3) SCK SCL(3) Basic COG1A COG1B COG1C COG1D COG2A COG2B COG2C COG2D COG3A COG3B COG3C COG3D High Current CCP1 CCP2 CCP7 Pull-ups PWM3 PWM4 PWM5 PWM6 PWM9 PWM11 Interrupt -- MSSP -- EUSART -- Modulator C1OUT C2OUT C3OUT C4OUT C5OUT C6OUT CLC -- COG -- CCP Op Amp -- PWM DAC -- Timers VREF -- PRG ADC -- ZCD 28-Pin UQFN OUT(2) Comparator 28-Pin SPDIP/SOIC/SSOP 28-PIN ALLOCATION TABLE (PIC16(L)F1778) (CONTINUED) I/O 2015-2016 Microchip Technology Inc. TABLE 3: -- -- -- -- Default peripheral input. Input can be moved to any other pin with the PPS input selection register. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. PIC16(L)F1777/8/9 DS40001819B-page 9 44-Pin TQFP 44-Pin QFN ADC VREF DAC Op Amp ZCD PRG Timers PWM CCP COG CLC Modulator EUSART MSSP Interrupt Pull-ups High Current Basic 2 17 19 19 AN0 -- -- -- C1IN0C2IN0C3IN0C4IN0C5IN0C6IN0C7IN0C8IN0- -- -- -- -- -- -- CLCIN0(1) -- -- -- IOC Y -- -- RA1 3 18 20 20 AN1 -- -- OPA1OUT OPA2IN1+ OPA2IN1- C1IN1C2IN1C3IN1C4IN1- -- PRG1IN0 PRG2IN1 -- -- -- -- CLCIN1(1) -- -- -- IOC Y -- -- RA2 4 19 21 21 AN2 DAC1REF0DAC2REF0DAC3REF0DAC4REF0DAC5REF0DAC6REF0DAC7REF0DAC8REF0- DAC1OUT1 -- C1IN0+ C2IN0+ C3IN0+ C4IN0+ C5IN0+ C6IN0+ C7IN0+ C8IN0+ -- -- -- -- -- -- -- -- -- -- IOC Y -- -- RA3 5 20 22 22 AN3 DAC1REF0+ DAC2REF0+ DAC3REF0+ DAC4REF0+ DAC5REF0+ DAC6REF0+ DAC7REF0+ DAC8REF0+ -- -- C1IN1+ -- -- -- -- -- -- -- MD1CL(1) -- -- IOC Y -- -- RA4 6 21 23 23 -- -- -- OPA1IN0+ -- -- PRG1R(1) -- -- -- -- -- MD1CH(1) -- -- IOC Y -- -- -- -- -- -- -- MD1MOD(1) -- SS IOC Y -- -- Comparator 40-Pin (U)QFN RA0 I/O 40-Pin PDIP 40/44-PIN ALLOCATION TABLE (PIC16(L)F1777/9) 2015-2016 Microchip Technology Inc. RA5 7 22 24 24 AN4 -- DAC2OUT1 OPA1IN0- -- -- PRG1F(1) RA6 14 29 31 33 -- -- -- -- C6IN1+ -- -- -- -- -- -- -- -- -- -- IOC Y -- OSC2 CLKOUT RA7 13 28 30 32 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IOC Y -- OSC1 CLKIN RB0 33 8 8 9 AN12 -- -- -- C2IN1+ ZCD -- -- -- CCP8(1) COG1IN(1) -- MD4CL(1) -- -- IOC INT Y HIB0 -- RB1 34 9 9 10 AN10 -- -- OPA2OUT OPA1IN1+ OPA1IN1- C1IN3C2IN3C3IN3C4IN3- -- PRG2IN0 PRG1IN1 PRG4R(1) -- -- -- COG2IN(1) -- MD4CH(1) -- -- IOC Y HIB1 -- RB2 35 10 10 11 AN8 -- DAC3OUT1 OPA2IN0- -- -- PRG4F(1) -- -- -- COG3IN(1) -- MD4MOD(1) -- -- IOC Y -- -- RB3 36 11 11 12 AN9 -- -- OPA2IN0+ C1IN2C2IN2C3IN2- -- -- -- -- -- -- -- MD3CL(1) -- -- IOC Y -- -- RB4 37 12 14 14 AN11 -- -- -- C3IN1+ -- -- -- -- -- -- -- MD3CH(1) -- -- IOC Y -- -- Note 1: 2: 3: Default peripheral input. Input can be moved to any other pin with the PPS input selection register. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. PIC16(L)F1777/8/9 DS40001819B-page 10 TABLE 4: 40-Pin PDIP 40-Pin (U)QFN 44-Pin TQFP 44-Pin QFN ADC VREF DAC Op Amp Comparator ZCD PRG Timers PWM CCP COG CLC Modulator EUSART MSSP Interrupt Pull-ups High Current Basic 40/44-PIN ALLOCATION TABLE (PIC16(L)F1777/9) (CONTINUED) RB5 38 13 15 15 AN13 DAC5REF1DAC7REF1- -- -- C4IN2- -- -- -- -- CCP7(1) -- -- MD3MOD(1) -- -- IOC Y -- -- RB6 39 14 16 16 -- DAC5REF1+ DAC7REF1+ -- -- C4IN1+ -- -- -- -- -- -- CLCIN2(1) -- -- -- IOC Y -- ICSPCLK RB7 40 15 17 17 -- -- DAC1OUT2 DAC2OUT2 DAC3OUT2 DAC4OUT2 DAC5OUT2 DAC6OUT2 DAC7OUT2 DAC8OUT2 -- C5IN1+ -- -- T6IN(1) -- -- -- CLCIN3(1) -- -- -- IOC Y -- ICSPDAT RC0 15 30 32 34 -- -- DAC5OUT1 -- -- -- -- T1CKI(1) T3CKI(1) T3G(1) SOSCO -- -- -- -- -- -- -- IOC Y -- -- I/O 2015-2016 Microchip Technology Inc. TABLE 4: 16 31 35 35 -- -- DAC7OUT1 -- -- -- PRG2R(1) SOSCI -- CCP2(1) -- -- -- -- -- IOC Y -- -- RC2 17 32 36 36 AN14 -- -- -- C5IN2C6IN2- -- PRG2F(1) -- -- CCP1(1) -- -- -- -- -- IOC Y -- -- RC3 18 33 37 37 AN15 -- -- -- -- -- -- T2IN(1) -- -- -- -- MD2CL(1) -- SCL IOC Y -- -- RC4 23 38 42 42 AN16 -- -- -- C5IN3C6IN3- -- PRG3R(1) T8IN(1) -- -- -- -- MD2CH(1) -- SDA IOC Y -- -- RC5 24 39 43 43 AN17 -- -- OPA3IN0+ -- -- PRG3F(1) T4IN(1) -- -- -- -- MD2MOD(1) -- -- IOC Y -- -- RC6 25 40 44 44 AN18 -- -- OPA3OUT OPA4IN1+ OPA4IN1- C5IN1C6IN1C7IN1C8IN1- -- PRG3IN0 PRG4IN1 -- -- -- -- -- -- -- -- IOC Y -- -- RC7 26 1 1 1 AN19 -- -- OPA3IN0- -- -- -- -- -- -- -- -- -- -- -- IOC Y -- -- RD0 19 34 38 38 AN20 -- -- OPA4IN0+ -- -- -- -- -- -- -- -- -- -- -- -- Y -- -- RD1 20 35 39 39 AN21 -- -- OPA4OUT OPA3IN1+ OPA3IN1- C1IN4C2IN4C3IN4C4IN4C5IN4C6IN4C7IN4C8IN4- -- PRG3IN1 PRG4IN0 -- -- -- -- -- -- -- -- -- Y -- -- DS40001819B-page 11 RD2 21 36 40 40 AN22 -- DAC4OUT1 OPA4IN0- -- -- -- -- -- -- -- -- -- -- -- -- Y -- -- RD3 22 37 41 41 AN23 -- -- -- C8IN2- -- -- -- -- -- -- -- -- -- -- -- Y -- -- RD4 27 2 2 2 AN24 -- -- -- C7IN2- -- -- -- -- -- -- -- -- -- -- -- Y -- -- RD5 28 3 3 3 AN25 -- -- -- C7IN3C8IN3- -- -- -- -- -- -- -- -- -- -- -- Y -- -- RD6 29 4 4 4 AN26 -- -- -- C7IN1+ -- -- -- -- -- -- -- -- -- -- -- Y -- -- RD7 30 5 5 5 AN27 -- -- -- C8IN1+ -- -- -- -- -- -- -- -- -- -- -- Y -- -- Note 1: 2: 3: Default peripheral input. Input can be moved to any other pin with the PPS input selection register. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. PIC16(L)F1777/8/9 RC1 40-Pin (U)QFN 44-Pin TQFP 44-Pin QFN ADC VREF DAC Op Amp Comparator ZCD PRG Timers PWM CCP COG CLC Modulator EUSART MSSP Interrupt Pull-ups High Current Basic RE0 8 23 25 25 AN5 DAC6REF1+ DAC8REF1+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- Y -- -- RE1 9 24 26 26 AN6 DAC6REF1DAC8REF1- DAC6OUT1 -- -- -- -- -- -- -- -- -- -- -- -- -- Y -- -- RE2 10 25 27 27 AN7 -- DAC8OUT1 -- -- -- -- -- -- -- -- -- -- -- -- -- Y -- -- RE3 1 16 18 18 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IOC Y -- MCLR VPP I/O 40-Pin PDIP 40/44-PIN ALLOCATION TABLE (PIC16(L)F1777/9) (CONTINUED) VDD 11 7 7 7,8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDD VDD 32 26 28 28 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDD VSS 12 6 6 6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VSS VSS 31 27 29 30 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VSS OUT(2) -- -- -- -- -- -- -- C1OUT C2OUT C3OUT C4OUT C5OUT C6OUT C7OUT C8OUT -- -- -- PWM3 PWM4 PWM5 PWM6 PWM9 PWM10 PWM11 PWM12 CCP1 CCP2 CCP7 CCP8 COG1A COG1B COG1C COG1D COG2A COG2B COG2C COG2D COG3A COG3B COG3C COG3D COG4A COG4B COG4C COG4D CLC1OUT CLC2OUT CLC3OUT CLC4OUT MD1OUT MD2OUT MD3OUT MD4OUT DT(3) TX CK SDO SDA(3) SCK SCL(3) -- -- -- -- Note 1: 2: 3: Default peripheral input. Input can be moved to any other pin with the PPS input selection register. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. PIC16(L)F1777/8/9 DS40001819B-page 12 TABLE 4: 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 15 2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 34 3.0 Memory Organization ................................................................................................................................................................. 36 4.0 Device Configuration .................................................................................................................................................................. 94 5.0 Oscillator Module (with Fail-Safe Clock Monitor) ..................................................................................................................... 101 6.0 Resets ...................................................................................................................................................................................... 119 7.0 Interrupts .................................................................................................................................................................................. 127 8.0 Power-Down Mode (Sleep) ...................................................................................................................................................... 146 9.0 Watchdog Timer (WDT) ........................................................................................................................................................... 151 10.0 Flash Program Memory Control ............................................................................................................................................... 156 11.0 I/O Ports ................................................................................................................................................................................... 173 12.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 203 13.0 Interrupt-On-Change ................................................................................................................................................................ 213 14.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 221 15.0 Temperature Indicator Module ................................................................................................................................................. 224 16.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 226 17.0 5-Bit Digital-to-Analog Converter (DAC) Module...................................................................................................................... 241 18.0 10-bit Digital-to-Analog Converter (DAC) Module .................................................................................................................... 246 19.0 Comparator Module.................................................................................................................................................................. 252 20.0 Zero-Cross Detection (ZCD) Module........................................................................................................................................ 265 21.0 Timer0 Module ......................................................................................................................................................................... 272 22.0 Timer1/3/5 Module with Gate Control....................................................................................................................................... 275 23.0 Timer2/4/6/8 Module ................................................................................................................................................................ 286 24.0 Capture/Compare/PWM Modules ............................................................................................................................................ 311 25.0 10-Bit Pulse-Width Modulation (PWM) Module ........................................................................................................................ 325 26.0 16-bit Pulse-Width Modulation (PWM) Module ........................................................................................................................ 332 27.0 Complementary Output Generator (COG) Modules................................................................................................................. 359 28.0 Configurable Logic Cell (CLC).................................................................................................................................................. 391 29.0 Operational Amplifier (OPA) Modules ...................................................................................................................................... 406 30.0 Programmable Ramp Generator (PRG) Module ...................................................................................................................... 413 31.0 Data Signal Modulator (DSM) .................................................................................................................................................. 427 32.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 440 33.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 493 34.0 In-Circuit Serial ProgrammingTM (ICSPTM) ............................................................................................................................... 524 35.0 Instruction Set Summary .......................................................................................................................................................... 526 36.0 Electrical Specifications............................................................................................................................................................ 540 37.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 575 38.0 Development Support............................................................................................................................................................... 599 39.0 Packaging Information.............................................................................................................................................................. 603 Appendix A: Data Sheet Revision History ......................................................................................................................................... 625 2015-2016 Microchip Technology Inc. DS40001819B-page 13 PIC16(L)F1777/8/9 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Website; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our website at www.microchip.com to receive the most current information on all of our products. DS40001819B-page 14 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 1-1: The PIC16(L)F1777/8/9 are described within this data sheet. See Table 2 for available package configurations. Figure 1-1 shows a block diagram of the PIC16(L)F1777/8/9 devices. Table 1-2 shows the pinout descriptions. Refer to Table 1-1 for peripherals available per device. PIC16(L)F1777/9 Peripheral Analog-to-Digital Converter (ADC) Fixed Voltage Reference (FVR) Zero-Cross Detection (ZCD) Temperature Indicator Complementary Output Generator (COG) COG1 COG2 COG3 COG4 PRG2 PRG3 PRG4 DAC2 DAC5 DAC6 DAC4 DAC7 DAC8 CCP2 CCP7 CCP8 Comparators 2015-2016 Microchip Technology Inc. C1 C2 C3 C4 C5 C6 C7 C8 DSM1 DSM2 DSM3 EUSART MSSP OPA1 OPA2 OPA3 10-bit Pulse-Width Modulator (PWM) PWM3 PWM4 PWM9 PWM10 16-bit Pulse-Width Modulator (PWM) PWM5 PWM6 PWM11 PWM12 8-bit Timers Capture/Compare/PWM (CCP/ECCP) Modules OPA4 CCP1 Op Amps 5-bit Digital-to-Analog Converter (DAC) CLC4 Master Synchronous Serial Ports DAC3 DSM4 10-bit Digital-to-Analog Converter (DAC) CLC3 Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter (EUSART) DAC1 Data Signal Modulator (DSM) Programmable Ramp Generator (PRG) CLC2 Configurable Logic Cell (CLC) PRG1 CLC1 Peripheral DEVICE PERIPHERAL SUMMARY PIC16(L)F1778 TABLE 1-1: DEVICE PERIPHERAL SUMMARY PIC16(L)F1777/9 DEVICE OVERVIEW PIC16(L)F1778 1.0 Timer0 Timer2 Timer4 Timer6 Timer8 Timer1 Timer3 Timer5 16-bit Timers DS40001819B-page 15 PIC16(L)F1777/8/9 1.1 1.1.1 Register and Bit naming conventions REGISTER NAMES When there are multiple instances of the same peripheral in a device, the peripheral control registers will be depicted as the concatenation of a peripheral identifier, peripheral instance, and control identifier. The control registers section will show just one instance of all the register names with an `x' in the place of the peripheral instance number. This naming convention may also be applied to peripherals when there is only one instance of that peripheral in the device to maintain compatibility with other devices in the family that contain more than one. 1.1.2 BIT NAMES There are two variants for bit names: * Short name: Bit function abbreviation * Long name: Peripheral abbreviation + short name 1.1.2.1 Short Bit Names 1.1.2.3 Bit Fields Bit fields are two or more adjacent bits in the same register. Bit fields adhere only to the short bit naming convention. For example, the three Least Significant bits of the COG1CON0 register contain the mode control bits. The short name for this field is MD. There is no long bit name variant. Bit field access is only possible in C programs. The following example demonstrates a C program instruction for setting the COG1 to the Push-Pull mode: COG1CON0bits.MD = 0x5; Individual bits in a bit field can also be accessed with long and short bit names. Each bit is the field name appended with the number of the bit position within the field. For example, the Most Significant mode bit has the short bit name MD2 and the long bit name is G1MD2. The following two examples demonstrate assembly program sequences for setting the COG1 to the Push-Pull mode: EXAMPLE 1-1: MOVLW ANDWF MOVLW IORWF Short bit names are an abbreviation for the bit function. For example, some peripherals are enabled with the EN bit. The bit names shown in the registers are the short name variant. ~(1<<G1MD1) COG1CON0,F 1<<G1MD2 | 1<<G1MD0 COG1CON0,F Short bit names are useful when accessing bits in C programs. The general format for accessing bits by the short name is RegisterNamebits.ShortName. For example, the enable bit, EN, in the COG1CON0 register can be set in C programs with the instruction COG1CON0bits.EN = 1. EXAMPLE 1-2: Short names are generally not useful in assembly programs because the same name may be used by different peripherals in different bit positions. When this occurs, during the include file generation, all instances of that short bit name are appended with an underscore plus the name of the register in which the bit resides to avoid naming contentions. 1.1.3 1.1.2.2 Long Bit Names Long bit names are constructed by adding a peripheral abbreviation prefix to the short name. The prefix is unique to the peripheral, thereby making every long bit name unique. The long bit name for the COG1 enable bit is the COG1 prefix, G1, appended with the enable bit short name, EN, resulting in the unique bit name G1EN. Long bit names are useful in both C and assembly programs. For example, in C the COG1CON0 enable bit can be set with the G1EN = 1 instruction. In assembly, this bit can be set with the BSF COG1CON0,G1EN instruction. BSF BCF BSF 1.1.3.1 COG1CON0,G1MD2 COG1CON0,G1MD1 COG1CON0,G1MD0 REGISTER AND BIT NAMING EXCEPTIONS Status, Interrupt, and Mirror Bits Status, interrupt enables, interrupt flags, and mirror bits are contained in registers that span more than one peripheral. In these cases, the bit name shown is unique so there is no prefix or short name variant. 1.1.3.2 Legacy Peripherals There are some peripherals that do not strictly adhere to these naming conventions. Peripherals that have existed for many years and are present in almost every device are the exceptions. These exceptions were necessary to limit the adverse impact of the new conventions on legacy code. Peripherals that do adhere to the new convention will include a table in the registers section indicating the long name prefix for each peripheral instance. Peripherals that fall into the exception category will not have this table. These peripherals include, but are not limited to, the following: * EUSART * MSSP DS40001819B-page 16 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 1-1: PIC16(L)F1777/8/9 BLOCK DIAGRAM Program Flash Memory RAM PORTA PORTB CLKOUT Timing Generation HFINTOSC/ LFINTOSC Oscillator CLKIN PORTC CPU PORTD Figure 1-1 MCLR PORTE DSMs PRGs ZCD Op Amps Temp. Indicator Note Timers 8-bit PWMs 1: ADC 10-Bit Timers 16-bit FVR DACs 5-bit DACs 10-bit MSSP Comparators COG CCPs EUSART CLCs See applicable chapters for more information on peripherals. 2015-2016 Microchip Technology Inc. DS40001819B-page 17 PIC16(L)F1777/8/9 TABLE 1-2: PIC16(L)F1778 PINOUT DESCRIPTION Name RA0/AN0/C1IN0-/C2IN0-/ C3IN0-/C4IN0-/C5IN0-/ C6IN0-/CLCIN0(1) RA1/AN1/C1IN1-/C2IN1-/ C3IN1-/C4IN1-/PRG1IN0/ PRG2IN1/OPA1OUT/OPA2IN1+/ OPA2IN1-/CLCIN1(1) Function RA0 Output Type Description TTL/ST CMOS General purpose I/O. AN0 AN -- ADC Channel 0 input. C1IN0- AN -- Comparator 1 negative input. C2IN0- AN -- Comparator 2 negative input. C3IN0- AN -- Comparator 3 negative input. C4IN0- AN -- Comparator 4 negative input. C5IN0- AN -- Comparator 5 negative input. C6IN0- AN -- Comparator 6 negative input. CLCIN0(1) TTL/ST -- CLC input 0. RA1 TTL/ST CMOS General purpose I/O. AN1 AN -- Channel 1 input. C1IN1- AN -- Comparator 1 negative input. C2IN1- AN -- Comparator 2 negative input. C3IN1- AN -- Comparator 3 negative input. C4IN1- AN -- Comparator 4 negative input. PRG1IN0 AN -- Ramp generator 1 reference voltage input. PRG2IN1 AN -- Ramp generator 2 reference voltage input. OPA1OUT -- AN Operational amplifier 1 output. OPA2IN1+ AN -- Operational amplifier 2 non-inverting input. OPA2IN1- AN -- Operational amplifier 2 inverting input. TTL/ST -- CLC input 1. CLCIN1(1) RA2/AN2/VREF-/DAC1REF0-/ DAC2REF0-/DAC3REF0-/ DAC4REF0-/DAC5REF0-/ DAC7REF0-/C1IN0+/C2IN0+/ C3IN0+/C4IN0+/C5IN0+/ C6IN0+/DAC1OUT1 Input Type RA2 TTL/ST CMOS General purpose I/O. AN2 AN -- VREF- AN -- ADC Channel 2 input. ADC negative reference. DAC1REF0- AN -- DAC1 negative reference. DAC2REF0- AN -- DAC2 negative reference. DAC3REF0- AN -- DAC3 negative reference. DAC4REF0- AN -- DAC4 negative reference. DAC5REF0- AN -- DAC5 negative reference. DAC7REF0- AN -- DAC7 negative reference. C1IN0+ AN -- Comparator 1 positive input. C2IN0+ AN -- Comparator 2 positive input. C3IN0+ AN -- Comparator 3 positive input. C4IN0+ AN -- Comparator 4 positive input. C5IN0+ AN -- Comparator 5 positive input. C6IN0+ AN -- Comparator 6 positive input. DAC1OUT1 -- AN DAC1 voltage output. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HP = High Power XTAL = Crystal levels Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers. 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. DS40001819B-page 18 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 1-2: PIC16(L)F1778 PINOUT DESCRIPTION (CONTINUED) Name RA3/AN3/VREF+/DAC1REF0+/ DAC2REF0+/DAC3REF0+/ DAC4REF0+/DAC5REF0+/ DAC7REF0+/C1IN1+/MD1CL RA4/OPA1IN0+/PRG1R/ MD1CH/DAC4OUT1/T0CKI Function RA3 Description TTL/ST CMOS General purpose I/O. AN3 AN -- AN -- ADC positive reference. DAC1REF0+ AN -- DAC1 positive reference. DAC2REF0+ AN -- DAC2 positive reference. DAC3REF0+ AN -- DAC3 positive reference. DAC4REF0+ AN -- DAC4 positive reference. DAC5REF0+ AN -- DAC5 positive reference. DAC7REF0+ AN -- DAC7 positive reference. ADC Channel 3 input. C1IN1+ AN -- Comparator 1 positive input. MD1CL(1) TTL/ST -- Data signal modulator 1 low carrier input. RA4 TTL/ST CMOS General purpose I/O. OPA1IN0+ AN -- Operational Amplifier 1 non-inverting input. (1) TTL/ST -- Ramp generator set_rising input. MD1CH(1) TTL/ST -- Data signal modulator 1 high carrier input. DAC4OUT1 -- AN DAC4 voltage output. T0CKI(1) TTL/ST -- Timer0 clock input. RA5 TTL/ST CMOS General purpose I/O. AN4 AN -- ADC Channel 4 input. OPA1IN0- AN -- Operational amplifier 1 inverting input. DAC2OUT1 -- AN DAC2 voltage output. PRG1F(1) TTL/ST -- Ramp generator set_falling input. MD1MOD(1) TTL/ST -- Data signal modulator modulation input. SS ST -- Slave Select input. RA6/CLKOUT/C6IN1+/OSC2 RA6 TTL/ST CMOS General purpose I/O. CLKOUT -- C6IN1+ AN -- Comparator 6 positive input. OSC2 XTAL -- Crystal/Resonator (LP, XT, HS modes). RA7/CLKIN/OSC1 RB0/AN12/ZCD/HIB0/C2IN1+/ COG1IN Output Type VREF+ PRG1R RA5/AN4/OPA1IN0-/ DAC2OUT1/PRG1F/ MD1MOD/SS Input Type RA7 CMOS FOSC/4 output. TTL/ST CMOS General purpose I/O. CLKIN TTL/ST -- CLC input. OSC1 XTAL -- Crystal/Resonator (LP, XT, HS modes). RB0 AN12 TTL/ST CMOS General purpose I/O. AN -- ADC Channel 12 input. ZCD AN -- Zero-cross detection input. HIB0 HP HP High-Power output. C2IN1+ AN -- Comparator 2 positive input. COG1IN(1) TTL/ST -- Complementary output generator 1 input. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HP = High Power XTAL = Crystal levels Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers. 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. 2015-2016 Microchip Technology Inc. DS40001819B-page 19 PIC16(L)F1777/8/9 TABLE 1-2: PIC16(L)F1778 PINOUT DESCRIPTION (CONTINUED) Name Function RB1/AN10/PRG1IN1/PRG2IN0/ HIB1/C1IN3-/C2IN3-/C3IN3-/ C4IN3-/OPA2OUT/OPA1IN1+/ OPA1IN1-/COG2IN RB1 RB2/AN8/OPA2IN0-/ DAC3OUT1/COG3IN RB4/AN11/C3IN1+/T5G/MD3CH Description AN10 AN -- ADC Channel 10 input. PRG1IN1 AN -- Ramp generator 1 reference voltage input. PRG2IN0 AN -- Ramp generator 2 reference voltage input. HIB1 HP HP High-Power output. C1IN3- AN -- Comparator 1 negative input. C2IN3- AN -- Comparator 2 negative input. C3IN3- AN -- Comparator 3 negative input. C4IN3- AN -- Comparator 4 negative input. OPA2OUT -- AN Operational amplifier 2 output. OPA1IN1+ AN -- Operational amplifier 1 non-inverting input. OPA1IN1- AN -- Operational amplifier 1 inverting input. COG2IN(1) TTL/ST -- Complementary output generator 2 input. RB2 TTL/ST CMOS General purpose I/O. AN8 AN -- ADC Channel 8 input. OPA2IN0- AN -- Operational amplifier 2 inverting input. DAC3OUT1 -- AN DAC3 voltage output. TTL/ST -- Complementary output generator 3 input. (1) RB3 TTL/ST CMOS General purpose I/O. AN9 AN -- ADC Channel 9 input. C1IN2- AN -- Comparator 1 negative input. C2IN2- AN -- Comparator 2 negative input. C3IN2- AN -- Comparator 3 negative input. OPA2IN0+ AN MD3CL(1) TTL/ST -- Data signal modulator 3 low carrier input. RB4 Operational amplifier 2 non-inverting input. TTL/ST CMOS General purpose I/O. AN11 AN -- ADC Channel 11 input. C3IN1+ AN -- Comparator 3 positive input. T5G(1) TTL/ST -- Timer5 gate input. TTL/ST -- Data signal modulator 3 high carrier input. MD3CH RB5/AN13/DAC5REF1-/ DAC7REF1-/C4IN2-/T1G/CCP7/ MD3MOD Output Type TTL/ST CMOS General purpose I/O. COG3IN RB3/AN9/C1IN2-/C2IN2-/ C3IN2-/OPA2IN0+/MD3CL Input Type (1) RB5 TTL/ST CMOS General purpose I/O. AN13 AN -- ADC Channel 11 input. DAC5REF1- AN -- DAC5 negative reference. DAC7REF1- AN -- DAC7 negative reference. C4IN2- AN -- Comparator 4 negative input. T1G(1) TTL/ST -- Timer1 gate input. CCP7(1) TTL/ST -- CCP7 capture input. TTL/ST -- Data signal modulator modulation input. MD3MOD (1) Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HP = High Power XTAL = Crystal levels Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers. 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. DS40001819B-page 20 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 1-2: PIC16(L)F1778 PINOUT DESCRIPTION (CONTINUED) Name Function RB6/DAC5REF1+/DAC7REF1+/ C4IN1+/CLCIN2/ICSPCLK RB6 RC0/DAC5OUT1/T1CKI/T3CKI/ T3G/SOSCO RC1/DAC7OUT1/PRG2R/CCP2/ SOSCI Description DAC5REF1+ AN -- DAC5 positive reference. DAC7REF1+ AN -- DAC7 positive reference. C4IN1+ AN -- Comparator 2 positive input. CLCIN2(1) TTL/ST -- CLC input 2. ST -- Serial Programming Clock. RB7 TTL/ST CMOS General purpose I/O. C5IN1+ AN -- Comparator 5 positive input. DAC1OUT2 -- AN DAC1 voltage output. DAC2OUT2 -- AN DAC2 voltage output. DAC3OUT2 -- AN DAC3 voltage output. DAC4OUT2 -- AN DAC4 voltage output. DAC5OUT2 -- AN DAC5 voltage output. DAC7OUT2 -- AN DAC7 voltage output. T6IN(1) TTL/ST -- Timer6 gate input. CLCIN3(1) TTL/ST -- CLC input 3. ICSPDAT ST RC0 CMOS ICSPTM Data I/O. TTL/ST CMOS General purpose I/O. DAC5OUT1 -- AN T1CKI(1) AN -- Comparator 4 negative input. T3CKI(1) TTL/ST -- Timer3 clock input. T3G(1) TTL/ST -- Timer3 gate input. SOSCO -- XTAL RC1 DAC5 voltage output. Secondary oscillator output. TTL/ST CMOS General purpose I/O. DAC7OUT1 (1) -- AN DAC7 voltage output. TTL/ST -- Ramp generator set_rising input. CCP2(1) TTL/ST -- CCP2 capture input. SOSCI XTAL -- Secondary oscillator input. PRG2R RC2/AN14/C5IN2-/C6IN2-/ PRG2F/CCP1/T5CKI Output Type TTL/ST CMOS General purpose I/O. ICSPCLK RB7/C5IN1+/DAC1OUT2/ DAC2OUT2/DAC3OUT2/ DAC4OUT2/DAC5OUT2/ DAC7OUT2/T6IN/CLCIN3/ ICSPDAT Input Type RC2 TTL/ST CMOS General purpose I/O. AN14 AN -- ADC Channel 14 input. C5IN2- AN -- Comparator 5 negative input. C6IN2- AN -- Comparator 6 negative input. PRG2F(1) TTL/ST -- Ramp generator set_falling input. CCP1(1) TTL/ST -- CCP1 capture input. T5CKI(1) TTL/ST -- Timer5 clock input. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HP = High Power XTAL = Crystal levels Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers. 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. 2015-2016 Microchip Technology Inc. DS40001819B-page 21 PIC16(L)F1777/8/9 TABLE 1-2: PIC16(L)F1778 PINOUT DESCRIPTION (CONTINUED) Name RC3/AN15/C1IN4-/C2IN4-/ C3IN4-/C4IN4-/C5IN4-/C6IN4-/ T2IN//MD2CL/SCL RC4/AN16/C5IN3-/C6IN3-/T8IN/ PRG3R/MD2CH/SDA RC5/AN17/OPA3IN0+/T4IN/ PRG3F/MD2MOD RC6/AN18/PRG3IN0/C5IN1-/ C6IN1-/OPA3OUT RC7/AN19/OPA3IN0- Function RC3 Output Type Description TTL/ST CMOS General purpose I/O. AN15 AN -- ADC Channel 15 input. C1IN4- AN -- Comparator 1 negative input. C2IN4- AN -- Comparator 2 negative input. C3IN4- AN -- Comparator 3 negative input. C4IN4- AN -- Comparator 4 negative input. C5IN4- AN -- Comparator 5 negative input. C6IN4- AN -- Comparator 6 negative input. T2IN(1) TTL/ST -- Timer2 gate input. MD2CL(1) TTL/ST -- Data signal modulator 2 low carrier input. SCL I2C OD I2C clock. RC4 TTL/ST CMOS General purpose I/O. AN16 AN -- ADC Channel 16 input. C5IN3- AN -- Comparator 5 negative input. C6IN3- AN -- Comparator 6 negative input. T8IN(1) TTL/ST -- Timer8 gate input. PRG3R(1) TTL/ST -- Ramp generator set_rising input. MD2CH(1) TTL/ST -- Data signal modulator 2 high carrier input. SDA I2C OD I2C data input/output. RC5 AN17 TTL/ST CMOS General purpose I/O. AN -- ADC Channel 17 input. OPA3IN0+ AN -- Operational amplifier 3 inverting input. T4IN(1) TTL/ST -- Timer4 gate input. PRG3F(1) TTL/ST -- Ramp generator set_falling input. MD2MOD(1) TTL/ST -- Data signal modulator modulation input. RC6 TTL/ST CMOS General purpose I/O. AN18 AN -- ADC Channel 18 input. PRG3IN0 AN -- Ramp generator 3 reference voltage input. C5IN1- AN -- Comparator 5 negative input. C6IN1- AN -- Comparator 6 negative input. OPA3OUT -- AN Operational amplifier 3 output. RC7 AN19 OPA3IN0- RE3/MCLR Input Type RE3 TTL/ST CMOS General purpose I/O. AN -- ADC Channel 19 input. AN -- Operational amplifier 3 non-inverting input. TTL/ST CMOS General purpose input. MCLR ST -- Master clear input. VDD VDD Power -- Positive supply. VSS VSS Power -- Ground reference. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HP = High Power XTAL = Crystal levels Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers. 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. DS40001819B-page 22 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 1-2: PIC16(L)F1778 PINOUT DESCRIPTION (CONTINUED) Name OUT(2) Function Input Type Output Type Description C1OUT CMOS Comparator 1 output. C2OUT CMOS Comparator 2 output. C3OUT CMOS Comparator 3 output. C4OUT CMOS Comparator 4 output. C5OUT CMOS Comparator 5 output. C6OUT CMOS Comparator 6 output. CCP1 CMOS Compare/PWM1 output. CCP2 CMOS Compare/PWM2 output. CCP7 CMOS Compare/PWM7 output. MD1OUT CMOS Data signal modulator 1 output. MD2OUT CMOS Data signal modulator 2 output. MD3OUT CMOS Data signal modulator 3 output. PWM3OUT CMOS PWM3 output. PWM4OUT CMOS PWM4 output. PWM5OUT CMOS PWM5 output. PWM6OUT CMOS PWM6 output. PWM9OUT CMOS PWM9 output. PWM11OUT COG1A CMOS PWM11 output. CMOS Complementary output generator 1 output A. COG1B CMOS Complementary output generator 1 output B. COG1C CMOS Complementary output generator 1 output C. COG1D CMOS Complementary output generator 1 output D. COG2A CMOS Complementary output generator 2 output A. COG2B CMOS Complementary output generator 2 output B. COG2C CMOS Complementary output generator 2 output C. COG2D CMOS Complementary output generator 2 output D. COG3A CMOS Complementary output generator 3 output A. COG3B CMOS Complementary output generator 3 output B. COG3C CMOS Complementary output generator 3 output C. COG3D CMOS Complementary output generator 3 output D. SDA(3) SCK SCL(3) SDO OD I2C data output. CMOS SPI clock output. OD I2C clock output. CMOS SPI data output. TX CMOS EUSART asynchronous TX data out. CK CMOS EUSART synchronous clock out. DT(3) CMOS EUSART synchronous data output. CLC1OUT CMOS Configurable logic cell 1 output. CLC2OUT CMOS Configurable logic cell 2 output. CLC3OUT CMOS Configurable logic cell 3 output. CLC4OUT CMOS Configurable logic cell 4 output. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HP = High Power XTAL = Crystal levels Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers. 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. 2015-2016 Microchip Technology Inc. DS40001819B-page 23 PIC16(L)F1777/8/9 TABLE 1-3: PIC16(L)F1777/9 PINOUT DESCRIPTION Name RA0/AN0/C1IN0-/C2IN0-/ C3IN0-/C4IN0-/C5IN0-/ C6IN0-/C7IN0-/C8IN0-/CLCIN0 Function RA0 Output Type Description TTL/ST CMOS General purpose I/O. AN0 AN -- ADC Channel 0 input. C1IN0- AN -- Comparator 1 negative input. C2IN0- AN -- Comparator 2 negative input. C3IN0- AN -- Comparator 3 negative input. C4IN0- AN -- Comparator 4 negative input. C5IN0- AN -- Comparator 5 negative input. C6IN0- AN -- Comparator 6 negative input. C7IN0- AN -- Comparator 7 negative input. C8IN0- AN -- Comparator 8 negative input. TTL/ST -- CLC input 0. CLCIN0(1) RA1/AN1/C1IN1-/C2IN1-/ C3IN1-/C4IN1-/PRG1IN0/ PRG2IN1/OPA1OUT/OPA2IN1+/ OPA2IN1-/CLCIN1 Input Type RA1 TTL/ST CMOS General purpose I/O. AN1 AN -- Channel 1 input. C1IN1- AN -- Comparator 1 negative input. C2IN1- AN -- Comparator 2 negative input. C3IN1- AN -- Comparator 3 negative input. C4IN1- AN -- Comparator 4 negative input. PRG1IN0 AN -- Ramp generator 1 reference voltage input. Ramp generator 2 reference voltage input. PRG2IN1 AN -- OPA1OUT -- AN Operational amplifier 1 output. OPA2IN1+ AN -- Operational amplifier 2 non-inverting input. OPA2IN1- AN -- Operational amplifier 2 inverting input. CLCIN1(1) TTL/ST -- CLC input 0. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HP = High Power XTAL = Crystal levels Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers. 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. DS40001819B-page 24 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 1-3: PIC16(L)F1777/9 PINOUT DESCRIPTION (CONTINUED) Name RA2/AN2/DAC1REF0-/ DAC2REF0-/DAC3REF0-/ DAC4REF0-/DAC5REF0-/ DAC6REF0-/DAC7REF0-/ DAC8REF0-/C1IN0+/C2IN0+/ C3IN0+/C4IN0+/C5IN0+/ C6IN0+/C7IN0+/C8IN0+/ DAC1OUT1 RA3/AN3/DAC1REF0+/ DAC2REF0+/DAC3REF0+/ DAC4REF0+/DAC5REF0+/ DAC6REF0+/DAC7REF0+/ DAC8REF0+/C1IN1+/MD1CL Function RA2 Input Type Output Type Description TTL/ST CMOS General purpose I/O. AN2 AN -- ADC Channel 2 input. DAC1REF0- AN -- DAC1 negative reference. DAC2REF0- AN -- DAC2 negative reference. DAC3REF0- AN -- DAC3 negative reference. DAC4REF0- AN -- DAC4 negative reference. DAC5REF0- AN -- DAC5 negative reference. DAC6REF0- AN -- DAC6 negative reference. DAC7REF0- AN -- DAC7 negative reference. DAC8REF0- AN -- DAC8 negative reference. C1IN0+ AN -- Comparator 1 positive input. C2IN0+ AN -- Comparator 2 positive input. C3IN0+ AN -- Comparator 3 positive input. C4IN0+ AN -- Comparator 4 positive input. C5IN0+ AN -- Comparator 5 positive input. C6IN0+ AN -- Comparator 6 positive input. C7IN0+ AN -- Comparator 7 positive input. C8IN0+ AN -- Comparator 8 positive input. DAC1OUT1 -- AN DAC1 voltage output. RA3 AN3 TTL/ST CMOS General purpose I/O. AN -- ADC Channel 3 input. VREF+ AN -- ADC positive reference. DAC1REF0+ AN -- DAC1 positive reference. DAC2REF0+ AN -- DAC2 positive reference. DAC3REF0+ AN -- DAC3 positive reference. DAC4REF0+ AN -- DAC4 positive reference. DAC5REF0+ AN -- DAC5 positive reference. DAC6REF0+ AN -- DAC6 positive reference. DAC7REF0+ AN -- DAC7 positive reference. DAC8REF0+ AN -- DAC8 positive reference. C1IN1+ AN -- Comparator 1 positive input. MD1CL(1) TTL/ST -- Data signal modulator 1 low carrier input. RA4/OPA1IN0+/PRG1R/MD1CH RA4 TTL/ST CMOS General purpose I/O. OPA1IN0+ AN -- Operational Amplifier 1 non-inverting input. PRG1R(1) TTL/ST -- Ramp generator set_rising input. MD1CH(1) TTL/ST -- Data signal modulator 1 high carrier input. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HP = High Power XTAL = Crystal levels Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers. 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. 2015-2016 Microchip Technology Inc. DS40001819B-page 25 PIC16(L)F1777/8/9 TABLE 1-3: PIC16(L)F1777/9 PINOUT DESCRIPTION (CONTINUED) Name RA5/AN4/OPA1IN0-/ DAC2OUT1/PRG1F/ MD1MOD/SS RA6/CLKOUT/C6IN1+/OSC2 Function RA5 AN4 AN -- ADC Channel 4 input. AN -- Operational amplifier 1 inverting input. DAC2OUT1 -- AN DAC2 voltage output. PRG1F(1) TTL/ST -- Ramp generator set_falling input. MD1MOD(1) TTL/ST -- Data signal modulator modulation input. SS ST -- Slave Select input. RA6 TTL/ST CMOS General purpose I/O. -- CMOS FOSC/4 output. C6IN1+ AN -- Comparator 6 positive input. OSC2 XTAL -- Crystal/Resonator (LP, XT, HS modes). RA7 TTL/ST CMOS General purpose I/O. OSC1 RB1/AN10/PRG1IN1/PRG2IN0/ PRG4R/HIB1/C1IN3-/C2IN3-/ C3IN3-/C4IN3-/OPA2OUT/ OPA1IN1+/OPA1IN1-/COG2IN/ MD4CH Description OPA1IN0- CLKIN RB0/AN12/ZCD/HIB0/C2IN1+/ CCP8/COG1IN/MD4CL/ INT Output Type TTL/ST CMOS General purpose I/O. CLKOUT RA7/CLKIN/OSC1 Input Type RB0 TTL/ST -- CLC input. XTAL -- Crystal/Resonator (LP, XT, HS modes). TTL/ST CMOS General purpose I/O. AN12 AN -- ADC Channel 12 input. ZCD AN -- Zero-cross detection input. High-Power output. HIB0 HP HP C2IN1+ AN -- Comparator 2 positive input. CCP8(1) TTL/ST -- CCP8 capture input. COG1IN(1) TTL/ST -- Complementary output generator 1 input. MD4CL(1) TTL/ST -- Data signal modulator 4 low carrier input. INT TTL/ST -- External interrupt. RB1 TTL/ST CMOS General purpose I/O. AN10 AN -- ADC Channel 10 input. PRG1IN1 AN -- Ramp generator 1 reference voltage input. PRG2IN0 AN -- Ramp generator 2 reference voltage input. PRG4R(1) TTL/ST -- Ramp generator set_rising input. HIB1 HP HP High-Power output. C1IN3- AN -- Comparator 1 negative input. C2IN3- AN -- Comparator 2 negative input. C3IN3- AN -- Comparator 3 negative input. C4IN3- AN -- Comparator 4 negative input. OPA2OUT -- AN Operational amplifier 2 output. OPA1IN1+ AN -- Operational amplifier 1 non-inverting input. OPA1IN1- AN -- Operational amplifier 1 inverting input. COG2IN(1) TTL/ST -- Complementary output generator 2 input. (1) TTL/ST -- Data signal modulator 4 high carrier input. MD4CH Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HP = High Power XTAL = Crystal levels Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers. 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. DS40001819B-page 26 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 1-3: PIC16(L)F1777/9 PINOUT DESCRIPTION (CONTINUED) Name RB2/AN8/OPA2IN0-/ DAC3OUT1/PRG4F/COG3IN/ MD4MOD Function RB2 Description TTL/ST CMOS General purpose I/O. AN8 AN -- ADC Channel 8 input. AN -- Operational amplifier 2 inverting input. DAC3OUT1 -- AN DAC3 voltage output. PRG4F(1) TTL/ST -- Ramp generator set_falling input. COG3IN(1) TTL/ST -- Complementary output generator 3 input. MD4MOD(1) TTL/ST -- Data signal modulator modulation input. RB3 TTL/ST CMOS General purpose I/O. AN9 AN -- ADC Channel 9 input. C1IN2- AN -- Comparator 1 negative input. C2IN2- AN -- Comparator 2 negative input. C3IN2- AN -- Comparator 3 negative input. OPA2IN0+ AN MD3CL RB4/AN11/C3IN1+/MD3CH RB6/DAC5REF1+/DAC7REF1+/ C4IN1+/CLCIN2/ICSPCLK Output Type OPA2IN0- RB3/AN9/C1IN2-/C2IN2-/ C3IN2-/OPA2IN0+/MD3CL RB5/AN13/DAC5REF1-/ DAC7REF1-/C4IN2-/CCP7/ MD3MOD Input Type (1) RB4 TTL/ST Operational amplifier 2 non-inverting input. -- Data signal modulator 3 low carrier input. TTL/ST CMOS General purpose I/O. AN11 AN -- ADC Channel 11 input. C3IN1+ AN -- Comparator 3 positive input. MD3CH(1) TTL/ST -- Data signal modulator 3 high carrier input. RB5 TTL/ST CMOS General purpose I/O. AN13 AN -- ADC Channel 11 input. DAC5REF1- AN -- DAC5 negative reference. DAC7REF1- AN -- DAC7 negative reference. C4IN2- AN -- Comparator 4 negative input. CCP7(1) TTL/ST -- CCP7 capture input. MD3MOD(1) TTL/ST -- Data signal modulator modulation input. RB6 TTL/ST CMOS General purpose I/O. DAC5REF1+ AN -- DAC5 positive reference. DAC7REF1+ AN -- DAC7 positive reference. C4IN1+ AN -- Comparator 2 positive input. CLCIN2 (1) ICSPCLK TTL/ST -- CLC input 2. ST -- Serial Programming Clock. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HP = High Power XTAL = Crystal levels Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers. 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. 2015-2016 Microchip Technology Inc. DS40001819B-page 27 PIC16(L)F1777/8/9 TABLE 1-3: PIC16(L)F1777/9 PINOUT DESCRIPTION (CONTINUED) Name RB7/C5IN1+/DAC1OUT2/ DAC2OUT2/DAC3OUT2/ DAC4OUT2/DAC5OUT2/ DAC6OUT2/DAC7OUT2/ DAC8OUT2/T6IN/CLCIN3/ ICSPDAT RC0/DAC5OUT1/T1CKI/T3CKI/ T3G/SOSCO RC1/DAC7OUT1/PRG2R/CCP2/ SOSCI RC2/AN14/C5IN2-/C6IN2-/ PRG2F/CCP1 Function RB7 Output Type Description TTL/ST CMOS General purpose I/O. C5IN1+ AN -- Comparator 5 positive input. DAC1OUT2 -- AN DAC1 voltage output. DAC2OUT2 -- AN DAC2 voltage output. DAC3OUT2 -- AN DAC3 voltage output. DAC4OUT2 -- AN DAC4 voltage output. DAC5OUT2 -- AN DAC5 voltage output. DAC6OUT2 -- AN DAC6 voltage output. DAC7OUT2 -- AN DAC7 voltage output. DAC8OUT2 -- AN DAC8 voltage output. T6IN(1) TTL/ST -- Timer6 gate input. CLCIN3(1) TTL/ST -- CLC input 3. ICSPDAT ST RC0 CMOS ICSPTM Data I/O. TTL/ST CMOS General purpose I/O. DAC5OUT1 -- AN T1CKI(1) AN -- Comparator 4 negative input. T3CKI(1) TTL/ST -- Timer3 clock input. T3G(1) TTL/ST -- Timer3 gate input. SOSCO -- XTAL RC1 DAC5 voltage output. Secondary oscillator output. TTL/ST CMOS General purpose I/O. DAC7OUT1 -- AN DAC7 voltage output. PRG2R(1) TTL/ST -- Ramp generator set_rising input. CCP2(1) TTL/ST -- CCP2 capture input. SOSCI XTAL -- Secondary oscillator input. RC2 TTL/ST CMOS General purpose I/O. AN14 AN -- ADC Channel 14 input. C5IN2- AN -- Comparator 5 negative input. AN -- Comparator 6 negative input. C6IN2RC3/AN15/C1IN4-/C2IN4-/ C3IN4-/C4IN4-/C5IN4-/C6IN4-/ C7IN4-/C8IN4-/T2IN/MD2CL/ SCL Input Type RC3 TTL/ST CMOS General purpose I/O. AN15 AN -- ADC Channel 15 input. C1IN4- AN -- Comparator 1 negative input. C2IN4- AN -- Comparator 2 negative input. C3IN4- AN -- Comparator 3 negative input. C4IN4- AN -- Comparator 4 negative input. C5IN4- AN -- Comparator 5 negative input. C6IN4- AN -- Comparator 6 negative input. C7IN4- AN -- Comparator 7 negative input. C8IN4- AN -- Comparator 8 negative input. T2IN(1) TTL/ST -- Timer2 gate input. MD2CL(1) TTL/ST -- Data signal modulator 2 low carrier input. SCL I2C OD I2C clock. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HP = High Power XTAL = Crystal levels Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers. 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. DS40001819B-page 28 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 1-3: PIC16(L)F1777/9 PINOUT DESCRIPTION (CONTINUED) Name RC4/AN16/C5IN3-/C6IN3-/ PRG3R/T8IN/MD2CH/SDA Function RC4 Description TTL/ST CMOS General purpose I/O. AN16 AN -- ADC Channel 16 input. AN -- Comparator 5 negative input. C6IN3- AN -- Comparator 6 negative input. PRG3R(1) TTL/ST -- Ramp generator set_rising input. Timer8 gate input. TTL/ST -- MD2CH(1) TTL/ST -- Data signal modulator 2 high carrier input. SDA I2C OD I2C data input/output. T8IN RC5 TTL/ST CMOS General purpose I/O. AN17 AN -- ADC Channel 17 input. OPA3IN0 AN -- Operational amplifier 3 inverting input. PRG3F(1) TTL/ST -- Ramp generator set_falling input. T4IN(1) TTL/ST -- Timer4 gate input. TTL/ST -- Data signal modulator modulation input. MD2MOD(1) RC6/AN18/PRG3IN0/PRG4IN1/ C5IN1-/C6IN1-/C7IN1-/C8IN1-/ OPA3OUT/OPA4IN1+/OPA4IN1- Output Type C5IN3- (1) RC5/AN17/OPA3IN0+/PRG3F/ T4IN/MD2MOD Input Type RC6 TTL/ST CMOS General purpose I/O. AN18 AN -- ADC Channel 18 input. PRG3IN0 AN -- Ramp generator 3 reference voltage input. PRG4IN1 AN -- Ramp generator 4 reference voltage input. C5IN1- AN -- Comparator 5 negative input. C6IN1- AN -- Comparator 6 negative input. C7IN1- AN -- Comparator 7 negative input. Comparator 8 negative input. C8IN1- AN -- OPA3OUT -- AN Operational amplifier 3 output. OPA4IN1+ AN -- Operational amplifier 4 non-inverting input. OPA4IN1- AN -- Operational amplifier 4 inverting input. RC7/AN19/OPA3IN0- RC7 TTL/ST CMOS General purpose I/O. AN19 AN -- ADC Channel 19 input. OPA3IN0- AN -- Operational amplifier 3 non-inverting input. RD0/AN20/OPA4IN0+ RD0 TTL/ST CMOS General purpose I/O. AN20 AN -- ADC Channel 20 input. OPA4IN0+ AN -- Operational amplifier 4 non-inverting input. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HP = High Power XTAL = Crystal levels Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers. 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. 2015-2016 Microchip Technology Inc. DS40001819B-page 29 PIC16(L)F1777/8/9 TABLE 1-3: PIC16(L)F1777/9 PINOUT DESCRIPTION (CONTINUED) Name Function RD1/AN21/PRG3IN1/PRG4IN0/ C1IN4-/C2IN4-/C3IN4-/C4IN4-/ C5IN4-/C6IN4-/C7IN4-/C8IN4-/ OPA4OUT/OPA3IN1+/OPA3IN1- RD1 RD2/AN22/DAC4OUT1/ OPA4IN0- RD3/AN23/C8IN2- RD6/AN26/C7IN1+ RD7/AN27/C8IN1+ RE0/AN5/DAC6REF1+/ DAC8REF1+ Description TTL/ST CMOS General purpose I/O. AN21 AN -- ADC Channel 21 input. AN -- Ramp generator 3 reference voltage input. PRG4IN0 AN -- Ramp generator 4 reference voltage input. C1IN4- AN -- Comparator 1 negative input. C2IN4- AN -- Comparator 2 negative input. C3IN4- AN -- Comparator 3 negative input. C4IN4- AN -- Comparator 4 negative input. C5IN4- AN -- Comparator 5 negative input. C6IN4- AN -- Comparator 6 negative input. C7IN4- AN -- Comparator 7 negative input. C8IN4- AN -- Comparator 8 negative input. OPA4OUT -- AN Operational amplifier 4 output. OPA3IN1+ AN -- Operational amplifier 3 non-inverting input. OPA3IN1- AN -- Operational amplifier 3 inverting input. RD2 AN22 TTL/ST CMOS General purpose I/O. AN -- ADC Channel 22 input. DAC4OUT1 -- AN DAC4 voltage output. OPA4IN0- AN -- Operational amplifier 4 inverting input. RD3 C8IN2- RD5/AN25/C7IN3-/C8IN3- Output Type PRG3IN1 AN23 RD4/AN24/C7IN2- Input Type RD4 TTL/ST CMOS General purpose I/O. AN -- ADC Channel 23 input. AN -- Comparator 8 negative input. TTL/ST CMOS General purpose I/O. AN24 AN -- ADC Channel 24 input. C7IN2- AN -- Comparator 8 negative input. RD5 TTL/ST CMOS General purpose I/O. AN25 AN -- ADC Channel 25 input. C7IN3- AN -- Comparator 7 negative input. C8IN3- AN -- Comparator 8 negative input. RD6 TTL/ST CMOS General purpose I/O. AN26 AN -- ADC Channel 26 input. C7IN1+ AN -- Comparator 7 positive input. RD7 TTL/ST CMOS General purpose I/O. AN27 AN -- ADC Channel 27 input. C8IN1+ AN -- Comparator 8 positive input. RE0 TTL/ST CMOS General purpose I/O. AN5 AN -- ADC Channel 5 input. DAC6REF1+ AN -- DAC6 positive reference. DAC8REF1+ AN -- DAC8 positive reference. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HP = High Power XTAL = Crystal levels Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers. 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. DS40001819B-page 30 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 1-3: PIC16(L)F1777/9 PINOUT DESCRIPTION (CONTINUED) Name Function RE1/AN6/DAC6OUT1/ DAC6REF1-/DAC8REF1- RE1 Description TTL/ST CMOS General purpose I/O. AN6 AN -- -- AN DAC6 voltage output. DAC6REF1- AN -- DAC6 negative reference. DAC8REF1- AN -- DAC8 negative reference. RE2 ADC Channel 6 input. TTL/ST CMOS General purpose I/O. AN7 AN -- ADC Channel 7 input. DAC8OUT1 -- AN DAC8 voltage output. RE3 RE3/MCLR/VPP TTL/ST CMOS General purpose input. MCLR ST -- Master clear input. VDD Power -- Positive supply. VSS Power -- Ground reference. VDD VSS OUT Output Type DAC6OUT1 RE2/AN7/DAC8OUT1 (2) Input Type C1OUT CMOS Comparator 1 output. C2OUT CMOS Comparator 2 output. C3OUT CMOS Comparator 3 output. C4OUT CMOS Comparator 4 output. C5OUT CMOS Comparator 5 output. C6OUT CMOS Comparator 6 output. C7OUT CMOS Comparator 7 output. C8OUT CMOS Comparator 8 output. CCP1 CMOS Compare/PWM1 output. CCP2 CMOS Compare/PWM2 output. CCP7 CMOS Compare/PWM7 output. CCP8 CMOS Compare/PWM8 output. MD1OUT CMOS Data signal modulator 1 output. MD2OUT CMOS Data signal modulator 2 output. MD3OUT CMOS Data signal modulator 3 output. MD4OUT CMOS Data signal modulator 4 output. PWM3OUT CMOS PWM3 output. PWM4OUT CMOS PWM4 output. PWM5OUT CMOS PWM5 output. PWM6OUT CMOS PWM6 output. PWM9OUT CMOS PWM9 output. PWM10OUT CMOS PWM10 output. PWM11OUT CMOS PWM11 output. PWM12OUT CMOS PWM12 output. COG1A CMOS Complementary output generator 1 output A. COG1B CMOS Complementary output generator 1 output B. COG1C CMOS Complementary output generator 1 output C. COG1D CMOS Complementary output generator 1 output D. COG2A CMOS Complementary output generator 2 output A. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HP = High Power XTAL = Crystal levels Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers. 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. 2015-2016 Microchip Technology Inc. DS40001819B-page 31 PIC16(L)F1777/8/9 TABLE 1-3: PIC16(L)F1777/9 PINOUT DESCRIPTION (CONTINUED) Name OUT(2) (Cont.) Function Input Type Output Type Description COG2B CMOS Complementary output generator 2 output B. COG2C CMOS Complementary output generator 2 output C. COG2D CMOS Complementary output generator 2 output D. COG3A CMOS Complementary output generator 3 output A. COG3B CMOS Complementary output generator 3 output B. COG3C CMOS Complementary output generator 3 output C. COG3D CMOS Complementary output generator 3 output D. COG4A CMOS Complementary output generator 4 output A. COG4B CMOS Complementary output generator 4 output B. COG4C CMOS Complementary output generator 4 output C. COG4D CMOS Complementary output generator 4 output D. SDA(3) SCK SCL OD CMOS SPI clock output. (3) SDO I2C data output. OD I2C clock output. CMOS SPI data output. TX CMOS EUSART asynchronous TX data out. CK CMOS EUSART synchronous clock out. DT (3) CMOS EUSART synchronous data output. CLC1OUT CMOS Configurable logic cell 1 output. CLC2OUT CMOS Configurable logic cell 2 output. CLC3OUT CMOS Configurable logic cell 3 output. CLC4OUT CMOS Configurable logic cell 4 output. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HP = High Power XTAL = Crystal levels Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers. 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. 1.2 Peripheral Connection Matrix Input selection multiplexers on many of the peripherals enable selecting the output of another peripheral such that the signal path is contained entirely within the device. Although the peripheral output can also be routed to a pin, with the PPS selection feature, it is not necessary to do so. Table 1-4 shows all the possible inter-peripheral signal connections. Please refer to corresponding peripheral section to obtain the multiplexer selection codes for the desired connection. DS40001819B-page 32 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 1-4: PERIPHERAL CONNECTION MATRIX PRG 5-bit DAC CCP Comparator (async) CLC Timer0 Clock Timer1/3/5 Gate Timer2/4/6/8 Reset Timer2/4/6/8 Clock CCP Clock CCP Capture 10-bit DAC Comparator (sync) 16-bit PWM 10-bit PWM Op Amp - Op Amp Override Op Amp + DSM CL DSM Mod DSM CH ZCD CLC Comparator - Comparator + PRG Rising/Falling 5-bit DAC PRG Analog Input FVR 10-bit DAC COG Shutdown COG Rising/Falling COG Clock Peripheral Output ADC Trigger Peripheral Input DSM COG EUSART TX/CK EUSART DT MSSP SCK/SCL MSSP SDO/SDA Op Amp 10-bit PWM 16-bit PWM Timer0 overflow Timer2 = T2PR Timer4 = T4PR Timer6 = T6PR Timer8 = T8PR Timer2 Postscale Timer4 Postscale Timer6 Postscale Timer8 Postscale Timer1 overflow Timer3 overflow Timer5 overflow SOSC FOSC/4 FOSC HFINTOSC LFINTOSC MFINTOSC IOCIF PPS Input pin 2015-2016 Microchip Technology Inc. DS40001819B-page 33 PIC16(L)F1777/8/9 2.0 Relative Addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and FIGURE 2-1: * * * * Automatic Interrupt Context Saving 16-level Stack with Overflow and Underflow File Select Registers Instruction Set CORE BLOCK DIAGRAM 15 Configuration 15 MUX Flash Program Memory Program Bus 16-Level 8 Level Stack Stack (13-bit) (15-bit) 14 Instruction Instruction Reg reg 8 Data Bus Program Counter RAM Program Memory Read (PMR) 12 RAM Addr Addr MUX Indirect Addr 12 12 Direct Addr 7 5 BSR FSR Reg reg 15 FSR0reg Reg FSR FSR1 Reg FSR reg 15 STATUS Reg reg STATUS 8 3 Power-up Timer OSC1/CLKIN OSC2/CLKOUT Instruction Decodeand & Decode Control Timing Generation Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset MUX ALU 8 W reg Internal Oscillator Block VDD DS40001819B-page 34 VSS 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 7.5 "Automatic Context Saving" for more information. 2.2 16-Level Stack with Overflow and Underflow These devices have a hardware stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled, will cause a software Reset. See Section 3.6 "Stack" for more details. 2.3 File Select Registers There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See Section 3.7 "Indirect Addressing" for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 35.0 "Instruction Set Summary" for more details. 2015-2016 Microchip Technology Inc. DS40001819B-page 35 PIC16(L)F1777/8/9 3.0 MEMORY ORGANIZATION These devices contain the following types of memory: * Program Memory - Configuration Words - Device ID - User ID - Flash Program Memory * Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM 3.1 The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented for the PIC16(L)F1777/8/9 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures 3-1 and 3-2). 3.2 Note 1: The method to access Flash memory through the PMCON registers is described in Section 10.0 "Flash Program Memory Control". The following features are associated with access and control of program memory and data memory: Program Memory Organization High-Endurance Flash This device has a 128-byte section of high-endurance program Flash memory (PFM) in lieu of data EEPROM. This area is especially well suited for nonvolatile data storage that is expected to be updated frequently over the life of the end product. See Section 10.2 "Flash Program Memory Overview" for more information on writing data to PFM. See Section 3.2.1.2 "Indirect Read with FSR" for more information about using the FSR registers to read byte data stored in PFM. * PCL and PCLATH * Stack * Indirect Addressing TABLE 3-1: DEVICE SIZES AND ADDRESSES Program Memory Space (Words) Last Program Memory Address High-Endurance Flash Memory Address Range(1) PIC16(L)F1777 8,192 1FFFh 1F80h-1FFFh PIC16(L)F1778/9 16,384 3FFFh 3F80h-3FFFh Device Note 1: High-endurance Flash applies to the low byte of each address in the range. DS40001819B-page 36 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1777 FIGURE 3-2: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1778/9 Rev. 10-000040B 7/30/2013 Rev. 10-000040E 7/30/2013 PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE 15 15 Stack Level 0 Stack Level 0 Stack Level 1 Stack Level 1 Stack Level 15 Stack Level 15 Reset Vector 0000h Reset Vector 0000h Interrupt Vector 0004h 0005h Interrupt Vector 0004h 0005h Page 0 Page 0 07FFh 0800h On-chip Program Memory 07FFh 0800h Page 1 Page 1 0FFFh 1000h Page 2 17FFh 1800h Page 3 Rollover to Page 0 On-chip Program Memory 0FFFh 1000h Page 2 17FFh 1800h Page 3 1FFFh 2000h 1FFFh 2000h Page 4 Page 7 Rollover to Page 3 2015-2016 Microchip Technology Inc. 7FFFh Rollover to Page 0 3FFFh 4000h Rollover to Page 7 7FFFh DS40001819B-page 37 PIC16(L)F1777/8/9 3.2.1 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.2.1.1 RETLW Instruction The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1. EXAMPLE 3-1: constants BRW RETLW RETLW RETLW RETLW DATA0 DATA1 DATA2 DATA3 RETLW INSTRUCTION ;Add Index in W to ;program counter to ;select data ;Index0 data ;Index1 data EXAMPLE 3-2: ACCESSING PROGRAM MEMORY VIA FSR constants DW DATA0 ;First constant DW DATA1 ;Second constant DW DATA2 DW DATA3 my_function ;... LOTS OF CODE... MOVLW DATA_INDEX ADDLW LOW constants MOVWF FSR1L MOVLW HIGH constants;MSb sets automatically MOVWF FSR1H BTFSC STATUS, C ;carry from ADDLW? INCF FSR1H, f ;yes MOVIW 0[FSR1] ;THE PROGRAM MEMORY IS IN W my_function ;... LOTS OF CODE... MOVLW DATA_INDEX call constants ;... THE CONSTANT IS IN W The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. 3.2.1.2 Indirect Read with FSR The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower eight bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR. The high directive will set bit<7> if a label points to a location in program memory. DS40001819B-page 38 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 3.3 Data Memory Organization 3.3.1.1 STATUS Register The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-3): The STATUS register, shown in Register 3-1, contains: * * * * The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. 12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as `0'. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section 3.7 "Indirect Addressing" for more information. Data memory uses a 12-bit address. The upper five bits of the address define the Bank address and the lower seven bits select the registers/RAM in that bank. 3.3.1 CORE REGISTERS The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0Bh/x8Bh). These registers are listed below in Table 3-2. For detailed information, see Table 3-17. TABLE 3-2: * the arithmetic status of the ALU * the Reset status For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as `000u u1uu' (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 35.0 "Instruction Set Summary"). Note: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. CORE REGISTERS Addresses BANKx x00h or x80h x01h or x81h x02h or x82h x03h or x83h x04h or x84h x05h or x85h x06h or x86h x07h or x87h x08h or x88h x09h or x89h x0Ah or x8Ah x0Bh or x8Bh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON 2015-2016 Microchip Technology Inc. DS40001819B-page 39 PIC16(L)F1777/8/9 3.4 Register Definitions: Status REGISTER 3-1: U-0 STATUS: STATUS REGISTER U-0 -- -- U-0 R-1/q -- TO R-1/q PD R/W-0/u R/W-0/u (1) Z DC R/W-0/u C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as `0' bit 4 TO: Time-Out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT Time-out occurred bit 3 PD: Power-Down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. DS40001819B-page 40 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 3.4.1 SPECIAL FUNCTION REGISTER The Special Function Registers (SFR) are registers used by the application to control the desired operation of peripheral functions in the device. The SFR occupies the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of each peripheral are described in the corresponding peripheral chapters of this data sheet. 3.4.2 FIGURE 3-3: 7-bit Bank Offset 0Bh 0Ch GENERAL PURPOSE RAM Core Registers (12 bytes) Special Function Registers (20 bytes maximum) 1Fh 20h Linear Access to GPR The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section 3.7.2 "Linear Data Memory" for more information. 3.4.3 Memory Region 00h There are up to 80 bytes of General Purpose Registers (GPR) in each data memory bank. The GPR occupies the space immediately after the SFR of selected data memory banks. The number of banks selected depends on the total amount of GPR space available in the device. 3.4.2.1 BANKED MEMORY PARTITIONING General Purpose RAM (80 bytes maximum) COMMON RAM There are 16 bytes of common RAM accessible from all banks. 6Fh 70h Common RAM (16 bytes) 7Fh 3.4.4 DEVICE MEMORY MAPS The memory maps for the device family are as shown in Tables 3-3 through 3-16. 2015-2016 Microchip Technology Inc. DS40001819B-page 41 2015-2016 Microchip Technology Inc. TABLE 3-3: PIC16(L)F1778 MEMORY MAP (BANKS 0-7) BANK 0 000h BANK 1 080h Core Registers (Table 3-2) 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h Core Registers (Table 3-2) Core Registers (Table 3-2) BANK 6 300h Core Registers (Table 3-2) BANK 7 380h Core Registers (Table 3-2) Core Registers (Table 3-2) LATA LATB LATC -- -- CMOUT CM1CON0 CM1CON1 CM1NSEL CM1PSEL CM2CON0 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h ANSELA ANSELB ANSELC -- -- PMADRL PMADRH PMDATL PMDATH PMCON1 PMCON2 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h WPUA WPUB WPUC -- WPUE SSP1BUF SSP1ADD SSP1MSK SSP1STAT SSP1CON1 SSP1CON2 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h ODCONA ODCONB ODCONC -- -- CCPR1L CCPR1H CCP1CON CCP1CAP CCPR2L CCPR2H 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h SLRCONA SLRCONB SLRCONC -- -- -- -- -- -- MD1CON0 MD1CON1 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h INLVLA INLVLB INLVLC -- INLVLE IOCAP IOCAN IOCAF IOCBP IOCBN IOCBF TMR0 TMR1L TMR1H T1CON T1GCON TMR3L TMR3H T3CON 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh OPTION_REG PCON WDTCON OSCTUNE OSCCON OSCSTAT BORCON FVRCON 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh CM2CON1 CM2NSEL CM2PSEL CM3CON0 CM3CON1 CM3NSEL CM3PSEL -- 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh VREGCON(1) -- RC1REG TX1REG SP1BRGL SP1BRGH RC1STA TX1STA 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh SSP1CON3 -- -- -- MD3CON0 MD3CON1 MD3SRC MD3CARL 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh CCP2CON CCP2CAP CCPR7L CCPR7H CCP7CON CCP7CAP -- CCPTMRS1 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh MD1SRC MD1CARL MD1CARH -- MD2CON0 MD2CON1 MD2SRC MD2CARL 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh IOCCP IOCCN IOCCF -- -- -- IOCEP IOCEN T3GCON 09Fh 0A0h ZCD1CON 11Fh 120h -- 19Fh 1A0h BAUD1CON 21Fh 220h MD3CARH 29Fh 2A0h CCPTMRS2 31Fh 320h 32Fh 330h MD2CARH 39Fh 3A0h IOCEF General Purpose Register 80 Bytes General Purpose Register 80 Bytes 16Fh 170h Accesses 70h - 7Fh 0FFh 1EFh 1F0h Accesses 70h - 7Fh 17Fh = Unimplemented data memory locations, read as `0'. DS40001819B-page 42 Unimplemented on PIC16LF1778. General Purpose Register 80 Bytes General Purpose Register 80 Bytes 26Fh 270h Accesses 70h - 7Fh 1FFh General Purpose Register 80 Bytes 27Fh 36Fh 370h 2EFh 2F0h Accesses 70h - 7Fh Accesses 70h - 7Fh 2FFh General Purpose Register 80 Bytes General Purpose Register 80 Bytes 3EFh 3F0h Accesses 70h - 7Fh 37Fh Accesses 70h - 7Fh 3FFh PIC16(L)F1777/8/9 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h Common RAM 70h - 7Fh 1: Core Registers (Table 3-2) BANK 5 280h TRISA TRISB TRISC -- TRISE PIE1 PIE2 PIE3 PIE4 PIE5 PIE6 0EFh 0F0h Legend: Core Registers (Table 3-2) BANK 4 200h 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 06Fh 070h Note BANK 3 180h PORTA PORTB PORTC -- PORTE PIR1 PIR2 PIR3 PIR4 PIR5 PIR6 General Purpose Register 80 Bytes 07Fh BANK 2 100h PIC16(L)F1777/9 MEMORY MAP (BANKS 0-7) BANK 0 000h BANK 1 080h Core Registers (Table 3-2) 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h Core Registers (Table 3-2) Core Registers (Table 3-2) BANK 6 300h Core Registers (Table 3-2) BANK 7 380h Core Registers (Table 3-2) Core Registers (Table 3-2) 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h LATA LATB LATC LATD LATE CMOUT CM1CON0 CM1CON1 CM1NSEL CM1PSEL CM2CON0 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h ANSELA ANSELB ANSELC ANSELD ANSELE PMADRL PMADRH PMDATL PMDATH PMCON1 PMCON2 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h WPUA WPUB WPUC WPUD WPUE SSP1BUF SSP1ADD SSP1MSK SSP1STAT SSP1CON1 SSP1CON2 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h ODCONA ODCONB ODCONC ODCOND ODCONE CCPR1L CCPR1H CCP1CON CCP1CAP CCPR2L CCPR2H 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h SLRCONA SLRCONB SLRCONC SLRCOND SLRCONE CCPR8L CCPR8H CCP8CON CCP8CAP MD1CON0 MD1CON1 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h INLVLA INLVLB INLVLC INLVLD INLVLE IOCAP IOCAN IOCAF IOCBP IOCBN IOCBF TMR0 TMR1L TMR1H T1CON T1GCON TMR3L TMR3H T3CON 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh OPTION_REG PCON WDTCON OSCTUNE OSCCON OSCSTAT BORCON FVRCON 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh CM2CON1 CM2NSEL CM2PSEL CM3CON0 CM3CON1 CM3NSEL CM3PSEL -- 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh VREGCON(1) -- RC1REG TX1REG SP1BRGL SP1BRGH RC1STA TX1STA 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh SSP1CON3 -- -- -- MD3CON0 MD3CON1 MD3SRC MD3CARL 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh CCP2CON CCP2CAP CCPR7L CCPR7H CCP7CON CCP7CAP -- CCPTMRS1 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh MD1SRC MD1CARL MD1CARH -- MD2CON0 MD2CON1 MD2SRC MD2CARL 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh IOCCP IOCCN IOCCF -- -- -- IOCEP IOCEN T3GCON 09Fh 0A0h ZCD1CON 11Fh 120h -- 19Fh 1A0h BAUD1CON 21Fh 220h MD3CARH 29Fh 2A0h CCPTMRS2 31Fh 320h MD2CARH 39Fh 3A0h IOCEF General Purpose Register 80 Bytes General Purpose Register 80 Bytes 2015-2016 Microchip Technology Inc. 0EFh 0F0h 16Fh 170h Accesses 70h - 7Fh 0FFh 1: Core Registers (Table 3-2) BANK 5 280h TRISA TRISB TRISC TRISD TRISE PIE1 PIE2 PIE3 PIE4 PIE5 PIE6 Common RAM 70h - 7Fh Note Core Registers (Table 3-2) BANK 4 200h 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 06Fh 070h 07Fh BANK 3 180h PORTA PORTB PORTC PORTD PORTE PIR1 PIR2 PIR3 PIR4 PIR5 PIR6 General Purpose Register 80 Bytes Legend: BANK 2 100h 1EFh 1F0h Accesses 70h - 7Fh 17Fh = Unimplemented data memory locations, read as `0'. Unimplemented on PIC16LF1777/9. General Purpose Register 80 Bytes General Purpose Register 80 Bytes 26Fh 270h Accesses 70h - 7Fh 1FFh General Purpose Register 80 Bytes 27Fh 36Fh 370h 2EFh 2F0h Accesses 70h - 7Fh General Purpose Register 80 Bytes Accesses 70h - 7Fh 2FFh General Purpose Register 80 Bytes 3EFh 3F0h Accesses 70h - 7Fh 37Fh Accesses 70h - 7Fh 3FFh PIC16(L)F1777/8/9 DS40001819B-page 43 TABLE 3-4: 2015-2016 Microchip Technology Inc. TABLE 3-5: PIC16(L)F1778 MEMORY MAP, BANK 8-15 BANK 8 400h BANK 9 480h Core Registers (Table 3-2) 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h -- HIDRVB -- TMR5L TMR5H T5CON T5GCON T4TMR T4PR T4CON T4HLT T4CLKCON T4RST -- T6TMR T6PR T6CON T6HLT T6CLKCON T6RST Core Registers (Table 3-2) 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h General Purpose Register 80 Bytes Legend: Core Registers (Table 3-2) 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h General Purpose Register 80 Bytes 4EFh 4F0h Accesses 70h - 7Fh 47Fh -- -- ADRESL ADRESH ADCON0 ADCON1 ADCON2 T2TMR T2PR T2CON T2HLT T2CLKCON T2RST -- T8TMR T8PR T8CON T8HLT T8CLKCON T8RST -- -- -- OPA1NCHS OPA1PCHS OPA1CON OPA1ORS OPA2NCHS OPA2PCHS OPA2CON OPA2ORS OPA3NCHS OPA3PCHS OPA3CON OPA3ORS -- -- -- -- -- 56Fh 570h 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h -- DACLD DAC1CON0 DAC1REFL DAC1REFH DAC2CON0 DAC2REFL DAC2REFH DAC3CON0 DAC3REF DAC4CON0 DAC4REF DAC5CON0 DAC5REFL DAC5REFH -- -- -- DAC7CON0 DA73REF Accesses 70h - 7Fh = Unimplemented data memory locations, read as `0'. 60Bh 60Ch 60Dh 60Eh 60Fh 610h 611h 612h 613h 614h 615h 616h 617h 618h 619h 61Ah 61Bh 61Ch 61Dh 61Eh 61Fh 620h -- -- -- -- -- -- -- -- PWM3DCL PWM3DCH PWM3CON PWM4DCL PWM4DCH PWM4CON PWM9DCL PWM9DCH PWM9CON -- -- -- 66Fh 670h 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h -- COG1PHR COG1PHF COG1BLKR COG1BLKF COG1DBR COG1DBF COG1CON0 COG1CON1 COG1RIS0 COG1RIS1 COG1RSIM0 COG1RSIM1 COG1FIS0 COG1FIS1 COG1FSIM0 COG1FSIM1 COG1ASD0 COG1ASD1 COG1STR 6EFh 6F0h 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h -- COG2PHR COG2PHF COG2BLKR COG2BLKF COG2DBR COG2DBF COG2CON0 COG2CON1 COG2RIS0 COG2RIS1 COG2RSIM0 COG2RSIM1 COG2FIS0 COG2FIS1 COG2FSIM0 COG2FSIM1 COG2ASD0 COG2ASD1 COG2STR Core Registers (Table 3-2) 78Bh 78Ch 78Dh 78Eh 78Fh 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h General Purpose Register 80 Bytes 76Fh 770h Accesses 70h - 7Fh 6FFh BANK 15 780h Core Registers (Table 3-2) General Purpose Register 80 Bytes Accesses 70h - 7Fh 67Fh BANK 14 700h Core Registers (Table 3-2) General Purpose Register 80 Bytes Accesses 70h - 7Fh 5FFh BANK 13 680h Core Registers (Table 3-2) General Purpose Register 80 Bytes 5EFh 5F0h 57Fh BANK 12 600h Core Registers (Table 3-2) General Purpose Register 80 Bytes Accesses 70h - 7Fh 4FFh BANK 11 580h General Purpose Register 80 Bytes 7EFh 7F0h Accesses 70h - 7Fh 77Fh -- -- PRG1RTSS PRG1FTSS PRG1INS PRG1CON0 PRG1CON1 PRG1CON2 PRG2RTSS PRG2FTSS PRG2INS PRG2CON0 PRG2CON1 PRG2CON2 PRG3RTSS PRG3FTSS PRG3INS PRG3CON0 PRG3CON1 PRG3CON2 Accesses 70h - 7Fh 7FFh DS40001819B-page 44 PIC16(L)F1777/8/9 46Fh 470h BANK 10 500h PIC16(L)F1777 MEMORY MAP, BANK 8-15 BANK 8 400h BANK 9 480h Core Registers (Table 3-2) 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h -- HIDRVB -- TMR5L TMR5H T5CON T5GCON T4TMR T4PR T4CON T4HLT T4CLKCON T4RST -- T6TMR T6PR T6CON T6HLT T6CLKCON T6RST Core Registers (Table 3-2) 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h General Purpose Register 80 Bytes 46Fh 470h 2015-2016 Microchip Technology Inc. Legend: -- -- ADRESL ADRESH ADCON0 ADCON1 ADCON2 T2TMR T2PR T2CON T2HLT T2CLKCON T2RST -- T8TMR T8PR T8CON T8HLT T8CLKCON T8RST 4EFh 4F0h 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h -- -- -- OPA1NCHS OPA1PCHS OPA1CON OPA1ORS OPA2NCHS OPA2PCHS OPA2CON OPA2ORS OPA3NCHS OPA3PCHS OPA3CON OPA3ORS OPA4NCHS OPA4PCHS OPA4CON OPA4ORS -- 56Fh 570h 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h Accesses 70h - 7Fh 60Bh 60Ch 60Dh 60Eh 60Fh 610h 611h 612h 613h 614h 615h 616h 617h 618h 619h 61Ah 61Bh 61Ch 61Dh 61Eh 61Fh 620h General Purpose Register 80 Bytes 64Fh 650h = Unimplemented data memory locations, read as `0'. 66Fh 670h Accesses 70h - 7Fh 5FFh BANK 13 680h Core Registers (Table 3-2) -- DACLD DAC1CON0 DAC1REFL DAC1REFH DAC2CON0 DAC2REFL DAC2REFH DAC3CON0 DAC3REF DAC4CON0 DAC4REF DAC5CON0 DAC5REFL DAC5REFH DAC6CON0 DAC6REFL DAC6REFH DAC7CON0 DA73REF 5EFh 5F0h 57Fh BANK 12 600h Core Registers (Table 3-2) General Purpose Register 80 Bytes Accesses 70h - 7Fh 4FFh BANK 11 580h Core Registers (Table 3-2) General Purpose Register 80 Bytes Accesses 70h - 7Fh 47Fh BANK 10 500h DAC8CON0 DAC8REFL PRG4RTSS PRG4FTSS PRG4INS PRG4CON0 PRG4CON1 PRG4CON2 PWM3DCL PWM3DCH PWM3CON PWM4DCL PWM4DCH PWM4CON PWM9DCL PWM9DCH PWM9CON PWM10DCL PWM10DCH PWM10CON General Purpose Register 48 Bytes Unimplemented Read as `0' Core Registers (Table 3-2) 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h -- COG1PHR COG1PHF COG1BLKR COG1BLKF COG1DBR COG1DBF COG1CON0 COG1CON1 COG1RIS0 COG1RIS1 COG1RSIM0 COG1RSIM1 COG1FIS0 COG1FIS1 COG1FSIM0 COG1FSIM1 COG1ASD0 COG1ASD1 COG1STR 6EFh 6F0h 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h -- COG2PHR COG2PHF COG2BLKR COG2BLKF COG2DBR COG2DBF COG2CON0 COG2CON1 COG2RIS0 COG2RIS1 COG2RSIM0 COG2RSIM1 COG2FIS0 COG2FIS1 COG2FSIM0 COG2FSIM1 COG2ASD0 COG2ASD1 COG2STR Core Registers (Table 3-2) 78Bh 78Ch 78Dh 78Eh 78Fh 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h Unimplemented Read as `0' 76Fh 770h Accesses 70h - 7Fh 6FFh BANK 15 780h Core Registers (Table 3-2) Unimplemented Read as `0' Accesses 70h - 7Fh 67Fh BANK 14 700h Unimplemented Read as `0' 7EFh 7F0h Accesses 70h - 7Fh 77Fh -- -- PRG1RTSS PRG1FTSS PRG1INS PRG1CON0 PRG1CON1 PRG1CON2 PRG2RTSS PRG2FTSS PRG2INS PRG2CON0 PRG2CON1 PRG2CON2 PRG3RTSS PRG3FTSS PRG3INS PRG3CON0 PRG3CON1 PRG3CON2 Accesses 70h - 7Fh 7FFh PIC16(L)F1777/8/9 DS40001819B-page 45 TABLE 3-6: 2015-2016 Microchip Technology Inc. TABLE 3-7: PIC16(L)F1779 MEMORY MAP, BANK 8-15 BANK 8 400h BANK 9 480h Core Registers (Table 3-2) 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h -- HIDRVB -- TMR5L TMR5H T5CON T5GCON T4TMR T4PR T4CON T4HLT T4CLKCON T4RST -- T6TMR T6PR T6CON T6HLT T6CLKCON T6RST Core Registers (Table 3-2) 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h General Purpose Register 80 Bytes Legend: Core Registers (Table 3-2) 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h General Purpose Register 80 Bytes 4EFh 4F0h Accesses 70h - 7Fh 47Fh -- -- ADRESL ADRESH ADCON0 ADCON1 ADCON2 T2TMR T2PR T2CON T2HLT T2CLKCON T2RST -- T8TMR T8PR T8CON T8HLT T8CLKCON T8RST -- -- -- OPA1NCHS OPA1PCHS OPA1CON OPA1ORS OPA2NCHS OPA2PCHS OPA2CON OPA2ORS OPA3NCHS OPA3PCHS OPA3CON OPA3ORS OPA4NCHS OPA4PCHS OPA4CON OPA4ORS -- 56Fh 570h 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h -- DACLD DAC1CON0 DAC1REFL DAC1REFH DAC2CON0 DAC2REFL DAC2REFH DAC3CON0 DAC3REF DAC4CON0 DAC4REF DAC5CON0 DAC5REFL DAC5REFH DAC6CON0 DAC6REFL DAC6REFH DAC7CON0 DA73REF Accesses 70h - 7Fh = Unimplemented data memory locations, read as `0'. 60Bh 60Ch 60Dh 60Eh 60Fh 610h 611h 612h 613h 614h 615h 616h 617h 618h 619h 61Ah 61Bh 61Ch 61Dh 61Eh 61Fh 620h DAC8CON0 DAC8REFL PRG4RTSS PRG4FTSS PRG4INS PRG4CON0 PRG4CON1 PRG4CON2 PWM3DCL PWM3DCH PWM3CON PWM4DCL PWM4DCH PWM4CON PWM9DCL PWM9DCH PWM9CON PWM10DCL PWM10DCH PWM10CON 66Fh 670h 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h -- COG1PHR COG1PHF COG1BLKR COG1BLKF COG1DBR COG1DBF COG1CON0 COG1CON1 COG1RIS0 COG1RIS1 COG1RSIM0 COG1RSIM1 COG1FIS0 COG1FIS1 COG1FSIM0 COG1FSIM1 COG1ASD0 COG1ASD1 COG1STR 6EFh 6F0h 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h -- COG2PHR COG2PHF COG2BLKR COG2BLKF COG2DBR COG2DBF COG2CON0 COG2CON1 COG2RIS0 COG2RIS1 COG2RSIM0 COG2RSIM1 COG2FIS0 COG2FIS1 COG2FSIM0 COG2FSIM1 COG2ASD0 COG2ASD1 COG2STR Core Registers (Table 3-2) 78Bh 78Ch 78Dh 78Eh 78Fh 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h General Purpose Register 80 Bytes 76Fh 770h Accesses 70h - 7Fh 6FFh BANK 15 780h Core Registers (Table 3-2) General Purpose Register 80 Bytes Accesses 70h - 7Fh 67Fh BANK 14 700h Core Registers (Table 3-2) General Purpose Register 80 Bytes Accesses 70h - 7Fh 5FFh BANK 13 680h Core Registers (Table 3-2) General Purpose Register 80 Bytes 5EFh 5F0h 57Fh BANK 12 600h Core Registers (Table 3-2) General Purpose Register 80 Bytes Accesses 70h - 7Fh 4FFh BANK 11 580h General Purpose Register 80 Bytes 7EFh 7F0h Accesses 70h - 7Fh 77Fh -- -- PRG1RTSS PRG1FTSS PRG1INS PRG1CON0 PRG1CON1 PRG1CON2 PRG2RTSS PRG2FTSS PRG2INS PRG2CON0 PRG2CON1 PRG2CON2 PRG3RTSS PRG3FTSS PRG3INS PRG3CON0 PRG3CON1 PRG3CON2 Accesses 70h - 7Fh 7FFh DS40001819B-page 46 PIC16(L)F1777/8/9 46Fh 470h BANK 10 500h 2015-2016 Microchip Technology Inc. TABLE 3-8: PIC16(L)F1778 MEMORY MAP, BANK 16-23 BANK 16 800h BANK 17 880h Core Registers (Table 3-2) 80Bh 80Ch 80Dh 80Eh 80Fh 810h 811h 812h 813h 814h 815h 816h 817h 818h 819h 81Ah 81Bh 81Ch 81Dh 81Eh 81Fh 820h -- COG3PHR COG3PHF COG3BLKR COG3BLKF COG3DBR COG3DBF COG3CON0 COG3CON1 COG3RIS0 COG3RIS1 COG3RSIM0 COG3RSIM1 COG3FIS0 COG3FIS1 COG3FSIM0 COG3FSIM1 COG3ASD0 COG3ASD1 COG3STR Core Registers (Table 3-2) 88Bh 88Ch Unimplemented Read as `0' 90Bh 90Ch 90Dh 90Eh 90Fh 910h 911h 912h 913h 914h 915h 916h 917h 918h CM4CON0 CM4CON1 CM4NSEL CM4PSEL CM5CON0 CM5CON1 CM5NSEL CM5PSEL CM6CON0 CM6CON1 CM6NSEL CM6PSEL Core Registers (Table 3-2) 98Bh 98Ch BANK 21 A80h Core Registers (Table 3-2) A0Bh A0Ch Unimplemented Read as `0' BANK 22 B00h Core Registers (Table 3-2) A8Bh A8Ch Unimplemented Read as `0' BANK 23 B80h Core Registers (Table 3-2) B0Bh B0Ch Unimplemented Read as `0' Core Registers (Table 3-2) B8Bh B8Ch Unimplemented Read as `0' Unimplemented Read as `0' 89Fh 8A0h 91Fh 920h General Purpose Register 48 Bytes 8EFh 8F0h General Purpose Register 48 Bytes A1Fh A20h General Purpose Register 48 Bytes 9EFh 9F0h 96Fh 970h Accesses 70h - 7Fh 8FFh 99Fh 9A0h Accesses 70h - 7Fh 97Fh = Unimplemented data memory locations, read as `0'. General Purpose Register 48 Bytes General Purpose Register 48 Bytes Accesses 70h - 7Fh A7Fh B1Fh B20h AEFh AF0h A6Fh A70h Accesses 70h - 7Fh 9FFh A9Fh AA0h General Purpose Register 48 Bytes General Purpose Register 48 Bytes BEFh BF0h B6Fh B70h Accesses 70h - 7Fh AFFh B9Fh BA0h Accesses 70h - 7Fh B7Fh Accesses 70h - 7Fh BFFh DS40001819B-page 47 PIC16(L)F1777/8/9 87Fh Core Registers (Table 3-2) BANK 20 A00h Read as `0' Accesses 70h - 7Fh Legend: BANK 19 980h Unimplemented General Purpose Register 48 Bytes 86Fh 870h BANK 18 900h 2015-2016 Microchip Technology Inc. TABLE 3-9: PIC16(L)F1777 MEMORY MAP, BANK 16-23 BANK 16 800h BANK 17 880h Core Registers (Table 3-2) 80Bh 80Ch 80Dh 80Eh 80Fh 810h 811h 812h 813h 814h 815h 816h 817h 818h 819h 81Ah 81Bh 81Ch 81Dh 81Eh 81Fh 820h -- COG3PHR COG3PHF COG3BLKR COG3BLKF COG3DBR COG3DBF COG3CON0 COG3CON1 COG3RIS0 COG3RIS1 COG3RSIM0 COG3RSIM1 COG3FIS0 COG3FIS1 COG3FSIM0 COG3FSIM1 COG3ASD0 COG3ASD1 COG3STR Core Registers (Table 3-2) 88Bh 88Ch 89Fh 8A0h 87Fh COG4PHR COG4PHF COG4BLKR COG4BLKF COG4DBR COG4DBF COG4CON0 COG4CON1 COG4RIS0 COG4RIS1 COG4RSIM0 COG4RSIM1 COG4FIS0 COG4FIS1 COG4FSIM0 COG4FSIM1 COG4ASD0 COG4ASD1 COG4STR Core Registers (Table 3-2) 90Bh 90Ch 90Dh 90Eh 90Fh 910h 911h 912h 913h 914h 915h 916h 917h 918h 91Fh 920h Unimplemented Read as `0' 8EFh 8F0h Accesses 70h - 7Fh Legend: -- CM4CON0 CM4CON1 CM4NSEL CM4PSEL CM5CON0 CM5CON1 CM5NSEL CM5PSEL CM6CON0 CM6CON1 CM6NSEL CM6PSEL CM7CON0 CM7CON1 CM7NSEL CM7PSEL CM8CON0 CM8CON1 CM8NSEL CM8PSEL BANK 20 A00h Core Registers (Table 3-2) 98Bh 98Ch BANK 21 A80h Core Registers (Table 3-2) A0Bh A0Ch Unimplemented Read as `0' BANK 22 B00h Core Registers (Table 3-2) A8Bh A8Ch Unimplemented Read as `0' BANK 23 B80h Core Registers (Table 3-2) B0Bh B0Ch Unimplemented Read as `0' Core Registers (Table 3-2) B8Bh B8Ch Unimplemented Read as `0' Unimplemented Read as `0' Unimplemented Read as `0' 9EFh 9F0h 96Fh 970h Accesses 70h - 7Fh 8FFh BANK 19 980h Accesses 70h - 7Fh 97Fh = Unimplemented data memory locations, read as `0'. Accesses 70h - 7Fh 9FFh AEFh AF0h A6Fh A70h Accesses 70h - 7Fh A7Fh Accesses 70h - 7Fh AFFh BEFh BF0h B6Fh B70h Accesses 70h - 7Fh B7Fh Accesses 70h - 7Fh BFFh DS40001819B-page 48 PIC16(L)F1777/8/9 Unimplemented Read as `0' 86Fh 870h BANK 18 900h PIC16(L)F1779 MEMORY MAP, BANK 16-23 BANK 16 800h BANK 17 880h Core Registers (Table 3-2) 80Bh 80Ch 80Dh 80Eh 80Fh 810h 811h 812h 813h 814h 815h 816h 817h 818h 819h 81Ah 81Bh 81Ch 81Dh 81Eh 81Fh 820h -- COG3PHR COG3PHF COG3BLKR COG3BLKF COG3DBR COG3DBF COG3CON0 COG3CON1 COG3RIS0 COG3RIS1 COG3RSIM0 COG3RSIM1 COG3FIS0 COG3FIS1 COG3FSIM0 COG3FSIM1 COG3ASD0 COG3ASD1 COG3STR Core Registers (Table 3-2) 88Bh 88Ch 89Fh 8A0h General Purpose Register 48 Bytes 86Fh 870h 2015-2016 Microchip Technology Inc. 87Fh -- COG4PHR COG4PHF COG4BLKR COG4BLKF COG4DBR COG4DBF COG4CON0 COG4CON1 COG4RIS0 COG4RIS1 COG4RSIM0 COG4RSIM1 COG4FIS0 COG4FIS1 COG4FSIM0 COG4FSIM1 COG4ASD0 COG4ASD1 COG4STR 8EFh 8F0h 90Bh 90Ch 90Dh 90Eh 90Fh 910h 911h 912h 913h 914h 915h 916h 917h 918h 91Fh 920h CM4CON0 CM4CON1 CM4NSEL CM4PSEL CM5CON0 CM5CON1 CM5NSEL CM5PSEL CM6CON0 CM6CON1 CM6NSEL CM6PSEL CM7CON0 CM7CON1 CM7NSEL CM7PSEL CM8CON0 CM8CON1 CM8NSEL CM8PSEL 98Bh 98Ch 97Fh Unimplemented Read as `0' General Purpose Register 48 Bytes Accesses 70h - 7Fh Unimplemented Read as `0' B9Fh BA0h General Purpose Register 48 Bytes General Purpose Register 48 Bytes BEFh BF0h B6Fh B70h Accesses 70h - 7Fh AFFh Core Registers (Table 3-2) B8Bh B8Ch B1Fh B20h AEFh AF0h A6Fh A70h A7Fh B0Bh B0Ch A9Fh AA0h BANK 23 B80h Core Registers (Table 3-2) Unimplemented Read as `0' General Purpose Register 48 Bytes Accesses 70h - 7Fh 9FFh A8Bh A8Ch A1Fh A20H BANK 22 B00h Core Registers (Table 3-2) Unimplemented Read as `0' General Purpose Register 48 Bytes Accesses 70h - 7Fh = Unimplemented data memory locations, read as `0'. Core Registers (Table 3-2) Unimplemented Read as `0' 99Fh 9A0h BANK 21 A80h A0Bh A0Ch 9EFh 9F0h 96Fh 970h BANK 20 A00h Core Registers (Table 3-2) General Purpose Register 48 Bytes Accesses 70h - 7Fh 8FFh BANK 19 980h Core Registers (Table 3-2) General Purpose Register 48 Bytes Accesses 70h - 7Fh Legend: BANK 18 900h Accesses 70h - 7Fh B7Fh Accesses 70h - 7Fh BFFh PIC16(L)F1777/8/9 DS40001819B-page 49 TABLE 3-10: 2015-2016 Microchip Technology Inc. TABLE 3-11: PIC16(L)F1778 MEMORY MAP, BANK 24-31 BANK 24 C00h BANK 25 C80h Core Registers (Table 3-2) C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- C6Fh C70h Core Registers (Table 3-2) C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h CBFh CC0h CEFh CF0h Accesses 70h - 7Fh CFFh Legend: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- General Purpose Register 32 Bytes Unimplemented Read as `0' Core Registers (Table 3-2) D0Bh D0Ch D0Dh D0Eh D0Fh D10h D11h D12h D13h D14h D15h D16h D17h D18h D19h D1Ah D1Bh D1Ch D1Dh D1Eh D1Fh D20h BANK 28 E00h Core Registers (Table 3-2) D8Bh -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BANK 29 E80h Core Registers (Table 3-2) E0Bh See Table 3-14 for register mapping details BANK 30 F00h Core Registers (Table 3-2) E8Bh See Table 3-14 for register mapping details BANK 31 F80h Core Registers (Table 3-2) F0Bh See Table 3-14 for register mapping details Core Registers (Table 3-2) F8Bh See Table 3-14 for register mapping details See Table 3-16 for register mapping details Unimplemented Read as `0' D6Fh D70h Accesses 70h - 7Fh CFFh BANK 27 D80h DEFh DF0h Accesses 70h - 7Fh D7Fh = Unimplemented data memory locations, read as `0'. E6Fh E70h Accesses 70h - 7Fh DFFh EEFh EF0h Accesses 70h - 7Fh E7Fh F6Fh F70h Accesses 70h - 7Fh EFFh FEFh FF0h Accesses 70h - 7Fh F7Fh Accesses 70h - 7Fh FFFh DS40001819B-page 50 PIC16(L)F1777/8/9 General Purpose Register 80 Bytes BANK 26 D00h 2015-2016 Microchip Technology Inc. TABLE 3-12: PIC16(L)F1777 MEMORY MAP, BANK 24-31 BANK 24 C00h BANK 25 C80h Core Registers (Table 3-2) C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- C6Fh C70h Core Registers (Table 3-2) C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h CFFh Core Registers (Table 3-2) D0Bh D0Ch D0Dh D0Eh D0Fh D10h D11h D12h D13h D14h D15h D16h D17h D18h D19h D1Ah D1Bh D1Ch D1Dh D1Eh D1Fh D20h CBFh Unimplemented Read as `0' CC0h CEFh CF0h Accesses 70h - 7Fh Legend: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BANK 28 E00h Core Registers (Table 3-2) D8Bh -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MD4CON0 MD4CON1 MD4SRC MD4CARL MD4CARH BANK 29 E80h Core Registers (Table 3-2) E0Bh See Table 3-15 for register mapping details BANK 30 F00h Core Registers (Table 3-2) E8Bh See Table 3-15 for register mapping details BANK 31 F80h Core Registers (Table 3-2) F0Bh See Table 3-15 for register mapping details Core Registers (Table 3-2) F8Bh See Table 3-15 for register mapping details See Table 3-16 for register mapping details Unimplemented Read as `0' D6Fh D70h Accesses 70h - 7Fh CFFh BANK 27 D80h DEFh DF0h Accesses 70h - 7Fh D7Fh = Unimplemented data memory locations, read as `0'. E6Fh E70h Accesses 70h - 7Fh DFFh EEFh EF0h Accesses 70h - 7Fh E7Fh F6Fh F70h Accesses 70h - 7Fh EFFh FEFh FF0h Accesses 70h - 7Fh F7Fh Accesses 70h - 7Fh FFFh DS40001819B-page 51 PIC16(L)F1777/8/9 Unimplemented Read as `0' BANK 26 D00h PIC16(L)F1779 MEMORY MAP, BANK 24-31 BANK 24 C00h BANK 25 C80h Core Registers (Table 3-2) C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h Core Registers (Table 3-2) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h General Purpose Register 80 Bytes CBFh CC0h C6Fh C70h CEFh CF0h 2015-2016 Microchip Technology Inc. Accesses 70h - 7Fh CFFh Legend: BANK 26 D00h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- General Purpose Register 32 Bytes Unimplemented Read as `0' Core Registers (Table 3-2) D0Bh D0Ch D0Dh D0Eh D0Fh D10h D11h D12h D13h D14h D15h D16h D17h D18h D19h D1Ah D1Bh D1Ch D1Dh D1Eh D1Fh D20h BANK 28 E00h Core Registers (Table 3-2) D8Bh -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MD4CON0 MD4CON1 MD4SRC MD4CARL MD4CARH BANK 29 E80h Core Registers (Table 3-2) E0Bh See Table 3-15 for register mapping details BANK 30 F00h Core Registers (Table 3-2) E8Bh See Table 3-15 for register mapping details BANK 31 F80h Core Registers (Table 3-2) F0Bh See Table 3-15 for register mapping details Core Registers (Table 3-2) F8Bh See Table 3-15 for register mapping details See Table 3-16 for register mapping details Unimplemented Read as `0' D6Fh D70h Accesses 70h - 7Fh CFFh BANK 27 D80h DEFh DF0h Accesses 70h - 7Fh D7Fh = Unimplemented data memory locations, read as `0'. E6Fh E70h Accesses 70h - 7Fh DFFh EEFh EF0h Accesses 70h - 7Fh E7Fh F6Fh F70h Accesses 70h - 7Fh EFFh FEFh FF0h Accesses 70h - 7Fh F7Fh Accesses 70h - 7Fh FFFh PIC16(L)F1777/8/9 DS40001819B-page 52 TABLE 3-13: PIC16(L)F1777/8/9 TABLE 3-14: PIC16(L)F1778 MEMORY MAP, BANK 27-30 Bank 27 D8Ch D8Dh D8Eh D8Fh D90h D91h D92h D93h D94h D95h D96h D97h D98h D99h D9Ah D9Bh D9Ch D9Dh D9Eh D9Fh DA0h DA1h DA2h DA3h DA4h DA5h DA6h DA7h DA8h DA9h DAAh DABh DACh DADh DAEh DAFh DB0h DB1h DB2h DB3h DB4h DB5h DB6h DB7h DB8h DB9h DBAh DBBh DBCh DBDh DBEh DBFh DC0h -- -- PWMEN PWMLD PWMOUT PWM5PHL PWM5PHH PWM5DCL PWM5DCH PWM5PRL PWM5PRH PWM5OFL PWM5OFH PWM5TMRL PWM5TMRH PWM5CON PWM5INTE PWM5INTF PWM5CLKCON PWM5LDCON PWM5OFCON PWM6PHL PWM6PHH PWM6DCL PWM6DCH PWM6PRL PWM6PRH PWM6OFL PWM6OFH PWM6TMRL PWM6TMRH PWM6CON PWM6INTE PWM6INTF PWM6CLKCON PWM6LDCON PWM6OFCON PWM11PHL PWM11PHH PWM11DCL PWM11DCH PWM11PRL PWM11PRH PWM11OFL PWM11OFH PWM11TMRL PWM11TMRH PWM11CON PWM11INTE PWM11INTF PWM11CLKCON PWM11LDCON PWM11OFCON Bank 28 E0Ch E0Dh E0Eh E0Fh E10h E11h E12h E13h E14h E15h E16h E17h E18h E19h E1Ah E1Bh E1Ch E1Dh E1Eh E1Fh E20h E21h E22h E23h E24h E25h E26h E27h E28h E29h E2Ah E2Bh E2Ch E2Dh E2Eh E2Fh E30h E31h E32h E33h E34h E35h E36h E37h E38h E39h E3Ah E3Bh E3Ch E3Dh E3Eh E3Fh E40h DC1h DEFh CLCIN0PPS CLCIN1PPS CLCIN2PPS CLCIN3PPS ADCACTPPS SSPCLKPPS SSPDATPPS SSPSSPPS RXPPS CKPPS -- Bank 29 E8Ch E8Dh E8Eh E8Fh E90h E91h E92h E93h E94h E95h E96h E97h E98h E99h E9Ah E9Bh E9Ch E9Dh E9Eh E9Fh EA0h EA1h EA2h EA3h EA4h EA5h EA6h EA7h EA8h EA9h EAAh EABh EACh EADh EAEh EAFh EB0h EB1h EB2h EB3h EB4h EB5h EB6h EB7h EB8h EB9h EBAh EBBh EBCh EBDh EBEh EBFh EC0h -- -- Legend: PPSLOCK INTPPS T0CKIPPS T1CKIPPS T1GPPS T3CKIPPS T3GPPS T5CKIPPS T5GPPS T2INPPS T4INPPS T6INPPS T8INPPS CCP1PPS CCP2PPS CCP7PPS -- COG1INPPS COG2INPPS COG3INPPS -- MD1CLPPS MD1CHPPS MD1MODPPS MD2CLPPS MD2CHPPS MD2MODPPS MD3CLPPS MD3CHPPS MD3MODPPS -- -- -- PRG1RPPS PRG1FPPS PRG2RPPS PRG2FPPS PRG3FPPS PRG3RPPS E6Fh -- -- -- -- RA0PPS RA1PPS RA2PPS RA3PPS RA4PPS RA5PPS RA6PPS RA7PPS RB0PPS RB1PPS RB2PPS RB3PPS RB4PPS RB5PPS RB6PPS RB7PPS RC0PPS RC1PPS RC2PPS RC3PPS RC4PPS RC5PPS RC6PPS RC7PPS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bank 30 F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h F18h F19h F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h F21h F22h F23h F24h F25h F26h F27h F28h F29h F2Ah F2Bh F2Ch F2Dh F2Eh F2Fh F30h F31h F32h F33h F34h F35h F36h F37h F38h F39h F3Ah F3Bh F3Ch F3Dh F3Eh F3Fh F40h -- -- EEFh -- -- -- CLCDATA CLC1CON CLC1POL CLC1SEL0 CLC1SEL1 CLC1SEL2 CLC1SEL3 CLC1GLS0 CLC1GLS1 CLC1GLS2 CLC1GLS3 CLC2CON CLC2POL CLC2SEL0 CLC2SEL1 CLC2SEL2 CLC2SEL3 CLC2GLS0 CLC2GLS1 CLC2GLS2 CLC2GLS3 CLC3CON CLC3POL CLC3SEL0 CLC3SEL1 CLC3SEL2 CLC3SEL3 CLC3GLS0 CLC3GLS1 CLC3GLS2 CLC3GLS3 CLC4CON CLC4POL CLC4SEL0 CLC4SEL1 CLC4SEL2 CLC4SEL3 CLC4GLS0 CLC4GLS1 CLC4GLS2 CLC4GLS3 -- -- -- -- -- -- -- -- F6Fh = Unimplemented data memory locations, read as `0', 2015-2016 Microchip Technology Inc. DS40001819B-page 53 PIC16(L)F1777/8/9 TABLE 3-15: D8Ch D8Dh D8Eh D8Fh D90h D91h D92h D93h D94h D95h D96h D97h D98h D99h D9Ah D9Bh D9Ch D9Dh D9Eh D9Fh DA0h DA1h DA2h DA3h DA4h DA5h DA6h DA7h DA8h DA9h DAAh DABh DACh DADh DAEh DAFh DB0h DB1h DB2h DB3h DB4h DB5h DB6h DB7h DB8h DB9h DBAh DBBh DBCh DBDh DBEh DBFh DC0h DC1h DC2h DC3h DC4h DC5h DC6h DC7h DC8h DC9h DCAh DCBh DCCh DCDh DCEh DCFh DCFh DD0h DD1h DEFh Legend: PIC16(L)F1777/9 MEMORY MAP, BANK 27-30 Bank 27 -- -- PWMEN PWMLD PWMOUT PWM5PHL PWM5PHH PWM5DCL PWM5DCH PWM5PRL PWM5PRH PWM5OFL PWM5OFH PWM5TMRL PWM5TMRH PWM5CON PWM5INTE PWM5INTF PWM5CLKCON PWM5LDCON PWM5OFCON PWM6PHL PWM6PHH PWM6DCL PWM6DCH PWM6PRL PWM6PRH PWM6OFL PWM6OFH PWM6TMRL PWM6TMRH PWM6CON PWM6INTE PWM6INTF PWM6CLKCON PWM6LDCON PWM6OFCON PWM11PHL PWM11PHH PWM11DCL PWM11DCH PWM11PRL PWM11PRH PWM11OFL PWM11OFH PWM11TMRL PWM11TMRH PWM11CON PWM11INTE PWM11INTF PWM11CLKCON PWM11LDCON PWM11OFCON PWM12PHL PWM12PHH PWM12DCL PWM12DCH PWM12PRL PWM12PRH PWM12OFL PWM12OFH PWM12TMRL PWM12TMRH PWM12CON PWM12INTE PWM12INTF PWM12CLKCON PWM12LDCON PWM12LDCON PWM12OFCON -- E0Ch E0Dh E0Eh E0Fh E10h E11h E12h E13h E14h E15h E16h E17h E18h E19h E1Ah E1Bh E1Ch E1Dh E1Eh E1Fh E20h E21h E22h E23h E24h E25h E26h E27h E28h E29h E2Ah E2Bh E2Ch E2Dh E2Eh E2Fh E30h E31h E32h E33h E34h E35h E36h E37h E38h E39h E3Ah E3Bh E3Ch E3Dh E3Eh E3Fh E40h E31h E32h E33h E34h E35h E36h E37h E38h E39h E3Ah E3Bh E3Ch E3Dh E3Eh E3Fh E3Fh E6Fh E6Fh E6Fh Bank 28 PPSLOCK INTPPS T0CKIPPS T1CKIPPS T1GPPS T3CKIPPS T3GPPS T5CKIPPS T5GPPS T2INPPS T4INPPS T6INPPS T8INPPS CCP1PPS CCP2PPS CCP7PPS CCP8PPS COG1INPPS COG2INPPS COG3INPPS COG4INPPS MD1CLPPS MD1CHPPS MD1MODPPS MD2CLPPS MD2CHPPS MD2MODPPS MD3CLPPS MD3CHPPS MD3MODPPS MD4CLPPS MD4CHPPS MD4MODPPS PRG1RPPS PRG1FPPS PRG2RPPS PRG2FPPS PRG3FPPS PRG3RPPS PRG4FPPS PRG4RPPS CLCIN0PPS CLCIN1PPS CLCIN2PPS CLCIN3PPS ADCACTPPS SSPCLKPPS SSPDATPPS SSPSSPPS RXPPS CKPPS -- E8Ch E8Dh E8Eh E8Fh E90h E91h E92h E93h E94h E95h E96h E97h E98h E99h E9Ah E9Bh E9Ch E9Dh E9Eh E9Fh EA0h EA1h EA2h EA3h EA4h EA5h EA6h EA7h EA8h EA9h EAAh EABh EACh EADh EAEh EAFh EB0h EB1h EB2h EB3h EB4h EB5h EB6h EB7h EB8h EB9h EBAh EBBh EBCh EBDh EBEh EBFh EC0h EB1h EB2h EB3h EB4h EB5h EB6h EB7h EB8h EB9h EBAh EBBh EBCh EBDh EBEh EBFh EBFh EEFh EEFh EEFh Bank 29 -- -- -- -- RA0PPS RA1PPS RA2PPS RA3PPS RA4PPS RA5PPS RA6PPS RA7PPS RB0PPS RB1PPS RB2PPS RB3PPS RB4PPS RB5PPS RB6PPS RB7PPS RC0PPS RC1PPS RC2PPS RC3PPS RC4PPS RC5PPS RC6PPS RC7PPS RD0PPS RD1PPS RD2PPS RD3PPS RD4PPS RD5PPS RD6PPS RD7PPS RE0PPS RE1PPS RE2PPS -- F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h F18h F19h F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h F21h F22h F23h F24h F25h F26h F27h F28h F29h F2Ah F2Bh F2Ch F2Dh F2Eh F2Fh F30h F31h F32h F33h F34h F35h F36h F37h F38h F39h F3Ah F3Bh F3Ch F3Dh F3Eh F3Fh F40h F31h F32h F33h F34h F35h F36h F37h F38h F39h F3Ah F3Bh F3Ch F3Dh F3Eh F3Fh F3Fh F6Fh F6Fh F6Fh Bank 30 -- -- -- CLCDATA CLC1CON CLC1POL CLC1SEL0 CLC1SEL1 CLC1SEL2 CLC1SEL3 CLC1GLS0 CLC1GLS1 CLC1GLS2 CLC1GLS3 CLC2CON CLC2POL CLC2SEL0 CLC2SEL1 CLC2SEL2 CLC2SEL3 CLC2GLS0 CLC2GLS1 CLC2GLS2 CLC2GLS3 CLC3CON CLC3POL CLC3SEL0 CLC3SEL1 CLC3SEL2 CLC3SEL3 CLC3GLS0 CLC3GLS1 CLC3GLS2 CLC3GLS3 CLC4CON CLC4POL CLC4SEL0 CLC4SEL1 CLC4SEL2 CLC4SEL3 CLC4GLS0 CLC4GLS1 CLC4GLS2 CLC4GLS3 -- = Unimplemented data memory locations, read as `0', DS40001819B-page 54 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 3-16: PIC16(L)F1777/8/9 MEMORY MAP, BANK 31 Bank 31 F8Ch FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh Legend: Unimplemented Read as `0' STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H_SHAD FSR1L_SHAD FSR1H_SHAD -- STKPTR TOSL TOSH = Unimplemented data memory locations, read as `0', 2015-2016 Microchip Technology Inc. DS40001819B-page 55 PIC16(L)F1777/8/9 3.4.5 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table 3-17 can be addressed from any Bank. TABLE 3-17: Addr CORE FUNCTION REGISTERS SUMMARY(1) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0-31 x00h or INDF0 x80h Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx uuuu uuuu x01h or INDF1 x81h Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx uuuu uuuu x02h or PCL x82h Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 x03h or STATUS x83h -- -- -- TO PD Z DC C ---1 1000 ---q quuu x04h or FSR0L x84h Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu x05h or FSR0H x85h Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 x06h or FSR1L x86h Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu x07h or FSR1H x87h Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 x08h or BSR x88h x09h or WREG x89h -- -- x0Bh or INTCON x8Bh GIE Note 1: -- BSR4 BSR3 BSR2 BSR1 BSR0 Working Register x0Ah or PCLATH x8Ah Legend: -- 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE ---0 0000 ---0 0000 TMR0IE INTE IOCIE TMR0IF -000 0000 -000 0000 INTF IOCIF 0000 0000 0000 0000 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. These registers can be addressed from any bank. DS40001819B-page 56 2015-2016 Microchip Technology Inc. 2015-2016 Microchip Technology Inc. TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets 00Ch PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx uuuu uuuu 00Dh PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 00Eh PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 00Fh PORTD(3) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu -- -- -- -- RE3 RE2(3) RE1(3) RE0(3) ---- xxxx ---- uuuu 0000 0000 Addr Name Bank 0 010h PORTE 011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 012h PIR2 OSFIF C2IF C1IF COG1IF BCL1IF C4IF C3IF CCP2IF 0000 0000 0000 0000 013h PIR3 -- -- COG2IF ZCDIF CLC4IF CLC3IF CLC2IF CLC1IF --00 0000 --00 0000 014h PIR4 -- TMR8IF TMR5GIF TMR5IF TMR3GIF TMR3IF TMR6IF TRM4IF -000 0000 -000 0000 015h PIR5 CCP8IF(3) CCP7IF COG4IF(3) COG3IF C8IF(3) C7IF(3) C6IF C5IF 0000 --00 0000 --00 016h PIR6 -- -- -- -- PWM12IF(3) PWM11IF PWM6IF PWM5IF ---- 0000 ---- 0000 017h TMR0 Timer0 Module Register 0000 0000 0000 0000 018h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 019h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0000 00-0 uuuu uu-u 01Ah T1CON 01Bh T1GCON CS<1:0> GE CKPS<1:0> GPOL GTM GSPM OSCEN SYNC GGO/DONE GVAL -- ON GSS<1:0> uuuu uxuu Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu 01Dh TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu 0000 00-0 uuuu uu-u 0000 0x00 uuuu uxuu 01Eh T3CON 01Fh T3GCON Legend: Note 1: 2: 3: CS<1:0> GE CKPS<1:0> GPOL GTM GSPM OSCEN SYNC GGO/DONE GVAL x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. -- ON GSS<1:0> DS40001819B-page 57 PIC16(L)F1777/8/9 0000 0x00 01Ch TMR3L SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets 08Ch TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 08Dh TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111 08Eh TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 08Fh TRISD(3) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111 -- -- -- -- --(1) TRISE2(3) TRISE1(3) TRISE0(3) ---- 1111 ---- 1111 0000 0000 Addr Name Bank 1 090h TRISE 091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 092h PIE2 OSFIE C2IE C1IE COG1IE BCL1IE C4IE C3IE CCP2IE 0000 0000 0000 0000 093h PIE3 -- -- COG2IE ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE --00 0000 --00 0000 094h PIE4 -- TMR8IE TMR5GIE TMR5IE TMR3GIE TMR3IE TMR6IE TRM4IE -000 0000 -000 0000 095h PIE5 CCP8IE(3) CCP7IE COG4IE(3) COG3IE C8IE(3) C7IE(3) C6IE C5IE 0000 0000 0000 0000 096h PIE6 -- -- -- -- PWM12IE(3) PWM11IE PWM6IE PWM5IE ---- 0000 ---- 0000 1111 1111 1111 1111 BOR 00-1 11qq qq-q qquu SWDTEN --01 0110 --01 0110 --00 0000 --00 0000 0011 1-00 0011 1-00 097h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA 098h PCON STKOVF STKUNF -- RWDT RMCLR 099h WDTCON PS<2:0> RI POR -- -- 09Ah OSCTUNE -- -- 09Bh OSCCON SPLLEN 09Ch OSCSTAT SOSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 0qq0 0q0q qqqq qq0q 09Dh BORCON SBOREN BORFS -- -- -- -- -- BORRDY 10-- ---q uu-- ---u 09Eh FVRCON FVREN FVRRDY TSEN TSRNG 0q00 0000 0q00 0000 EN -- OUT POL -- INTP 0-x0 --00 0-x0 --00 09Fh ZCD1CON Legend: Note 2015-2016 Microchip Technology Inc. 1: 2: 3: WDTPS<4:0> TUN<5:0> IRCF<3:0> -- CDAFVR<1:0> -- x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. SCS<1:0> ADFVR<1:0> INTN PIC16(L)F1777/8/9 DS40001819B-page 58 TABLE 3-18: 2015-2016 Microchip Technology Inc. TABLE 3-18: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 10Ch LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx xxxx uuuu uuuu 10Dh LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx uuuu uuuu 10Eh LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu 10Fh LATD(3) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx uuuu uuuu 110h LATE(3) -- -- -- -- -- LATE2 LATE1 LATE0 ---- -111 ---- -111 111h CMOUT MC8OUT(3) MC7OUT(3) MC6OUT MC5OUT MC4OUT MC3OUT MC2OUT MC1OUT 0000 0000 0000 0000 112h CM1CON0 ON OUT -- POL ZLF Reserved HYS SYNC 00-0 0100 00-0 0100 113h CM1CON1 -- -- -- -- -- -- INTP INTN ---- --00 ---- --00 114h CM1NSEL -- -- -- -- NCH<3:0> ---- 0000 ---- 0000 115h CM1PSEL -- -- -- -- PCH<3:0> ---- 0000 ---- 0000 116h CM2CON0 ON OUT -- POL ZLF Reserved HYS SYNC 00-0 0100 00-0 0100 117h CM2CON1 -- -- -- -- -- -- INTP INTN ---- --00 ---- --00 118h CM2NSEL -- -- -- -- NCH<3:0> ---- 0000 ---- 0000 119h CM2PSEL -- -- -- -- PCH<3:0> ---- 0000 ---- 0000 11Ah CM3CON0 ON OUT -- POL ZLF Reserved HYS SYNC 00-0 0100 00-0 0100 11Bh CM3CON1 -- -- -- -- -- -- INTP INTN ---- --00 ---- --00 11Ch CM3NSEL -- -- -- -- NCH<3:0> ---- 0000 ---- 0000 11Dh CM3PSEL -- -- -- -- PCH<3:0> ---- 0000 ---- 0000 -- Unimplemented -- -- 11Fh -- Unimplemented -- -- Legend: Note 1: 2: 3: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. DS40001819B-page 59 PIC16(L)F1777/8/9 11Eh Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 --11 1111 --11 1111 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111 ANSC5 ANSC4 ANSC3 ANSC2 -- -- 1111 11-- 1111 11-- ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 1111 1111 1111 1111 -- -- -- -- ANSE2 ANSE1 ANSE0 ---- -111 ---- -111 0000 0000 0000 0000 1000 0000 1000 0000 Bit 7 Bit 6 18Ch ANSELA -- -- 18Dh ANSELB -- -- 18Eh ANSELC ANSC7 ANSC6 18Fh ANSELD(3) ANSD7 -- Bit 5 Bank 3 190h ANSELE(3) 191h PMADRL 192h PMADRH Program Memory Address Register Low Byte 193h PMDATL 194h PMDATH -- -- 195h PMCON1 --(1) CFGS 196h PMCON2 197h VREGCON 198h -- 198h 199h --(1) Program Memory Address Register High Byte Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu --xx xxxx --uu uuuu 1000 x000 1000 q000 0000 0000 0000 0000 ---- --01 ---- --01 Unimplemented -- -- -- Unimplemented -- -- RC1REG EUSART Receive Data Register 0000 0000 0000 0000 19Ah TX1REG EUSART Transmit Data Register 0000 0000 0000 0000 Program Memory Read Data Register High Byte LWLO FREE WRERR WREN WR RD Program Memory Control Register 2 -- -- -- -- -- -- VREGPM(2) Reserved 19Bh SP1BRGL SP1BRG<7:0> 0000 0000 0000 0000 19Ch SP1BRGH SP1BRG<15:8> 0000 0000 0000 0000 19Dh RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 0000 0000 0000 19Eh TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 01-0 0-00 01-0 0-00 -- -- 19Fh BAUD1CON 199h -- -- 19Fh 2015-2016 Microchip Technology Inc. Legend: Note 1: 2: 3: Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. PIC16(L)F1777/8/9 DS40001819B-page 60 TABLE 3-18: 2015-2016 Microchip Technology Inc. TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets 20Ch WPUA WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 1111 1111 1111 1111 20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111 20Eh WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 1111 1111 1111 1111 20Fh WPUD(3) WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 1111 1111 1111 1111 -- -- -- -- WPUE3 WPUE2(3) WPUE1(3) WPUE0(3) ---- 1111 ---- 1111 xxxx xxxx uuuu uuuu Addr Name Bank 4 210h WPUE 211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 212h SSP1ADD ADD<7:0> 0000 0000 0000 0000 213h SSP1MSK MSK<7:0> 1111 1111 1111 1111 214h SSP1STAT SMP CKE D/A P 215h SSP1CON1 WCOL SSPOV SSPEN CKP 216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN 217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN 218h -- -- 21Ah S R/W UA BF 0000 0000 0000 0000 0000 0000 0000 0000 SEN 0000 0000 0000 0000 DHEN 0000 0000 0000 0000 -- -- 0-00 ---0 SSPM<3:0> Unimplemented 21Bh MD3CON0 EN -- OUT OPOL -- -- -- BIT 0-00 ---0 21Ch MD3CON1 -- -- CHPOL CHSYNC -- -- CLPOL CLSYNC --00 --00 --00 --00 21Dh MD3SRC -- -- -- MS<4:0> ---0 0000 ---0 0000 21Eh MD3CARL -- -- -- CL<4:0> ---0 0000 ---0 0000 21Fh MD3CARH -- -- -- CH<4:0> ---0 0000 ---0 0000 Note 1: 2: 3: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. DS40001819B-page 61 PIC16(L)F1777/8/9 Legend: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets 28Ch ODCONA ODA7 ODA6 ODA5 ODA4 ODA3 ODA2 ODA1 ODA0 0000 0000 0000 0000 28Dh ODCONB ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 0000 0000 0000 0000 28Eh ODCONC ODC7 ODC6 ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 0000 0000 0000 0000 28Fh ODCOND(3) ODD7 ODD6 ODD5 ODD4 ODD3 ODD2 ODD1 ODD0 0000 0000 0000 0000 -- -- -- -- -- ODE2 ODE1 ODE0 ---- -000 --- -000 xxxx xxxx uuuu uuuu Addr Name Bank 5 290h ODCONE(3) 291h CCPR1L Capture/Compare/PWM Register 1 (LSB) 292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu 293h CCP1CON EN -- OUT FMT MODE<3:0> 0-00 0000 0-00 0000 294h CCP1CAP -- -- -- -- CTS<3:0> ---- 0000 ---- 0000 295h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu 296h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu 297h CCP2CON 298h CCP2CAP 299h CCPR7L Capture/Compare/PWM Register 7 (LSB) 29Ah CCPR7H Capture/Compare/PWM Register 7 (MSB) xxxx xxxx uuuu uuuu 29Bh CCP7CON 29Ch CCP7CAP 29Dh -- EN -- OUT FMT MODE<3:0> 0-00 0000 0-00 0000 -- -- -- -- CTS<3:0> ---- 0000 ---- 0000 xxxx xxxx uuuu uuuu EN -- OUT FMT MODE<3:0> 0-00 0000 0-00 0000 -- -- -- -- CTS<3:0> ---- 0000 ---- 0000 Unimplemented -- -- 29Eh CCPTMRS1 C8TSEL<1:0>(3) C7TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> --00 0000 --00 0000 29Fh CCPTMRS2 P10TSEL<1:0>(3) P9TSEL<1:0> P4TSEL<1:0> P3TSEL<1:0> --00 0000 --00 0000 Legend: Note 2015-2016 Microchip Technology Inc. 1: 2: 3: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. PIC16(L)F1777/8/9 DS40001819B-page 62 TABLE 3-18: 2015-2016 Microchip Technology Inc. TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets 30Ch SLRCONA SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 1111 1111 1111 1111 30Dh SLRCONB SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 1111 1111 1111 1111 30Eh SLRCONC SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 1111 1111 1111 1111 30Fh SLRCOND(3) SLRD7 SLRD6 SLRD5 SLRD4 SLRD3 SLRD2 SLRD1 SLRD0 1111 1111 1111 1111 -- -- -- -- -- SLRE2 SLRE1 SLRE0 Addr Name Bank 6 310h SLRCONE(3) ---- -111 ---- -111 311h CCPR8L Capture/Compare/PWM Register 8 (LSB) xxxx xxxx uuuu uuuu 312h CCPR8H Capture/Compare/PWM Register 8 (MSB) xxxx xxxx uuuu uuuu 313h CCP8CON EN -- OUT FMT MODE<3:0> 0-00 0000 0-00 0000 314h CCP8CAP -- -- -- -- CTS<3:0> ---- 0000 ---- 0000 315h MD1CON0 EN -- OUT OPOL -- -- -- BIT 0-00 ---0 0-00 ---0 316h MD1CON1 -- -- CHPOL CHSYNC -- -- CLPOL CLSYNC --00 --00 --00 --00 317h MD1SRC -- -- -- MS<4:0> ---0 0000 ---0 0000 318h MD1CARL -- -- -- CL<4:0> ---0 0000 ---0 0000 319h MD1CARH -- -- -- CH<4:0> ---0 0000 ---0 0000 31Ah -- Unimplemented EN -- OUT OPOL -- 31Ch MD2CON1 -- -- CHPOL CHSYNC -- 31Dh MD2SRC -- -- -- 31Eh MD2CARL -- -- 31Fh MD2CARH -- -- Legend: Note 1: 2: 3: -- -- BIT -- CLPOL CLSYNC -- 0-00 ---0 0-00 ---0 --00 --00 --00 --00 MS<4:0> ---0 0000 ---0 0000 -- CL<4:0> ---0 0000 ---0 0000 -- CH<4:0> ---0 0000 ---0 0000 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. DS40001819B-page 63 PIC16(L)F1777/8/9 31Bh MD2CON0 -- SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets 38Ch INLVLA INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 1111 1111 1111 1111 38Dh INLVLB INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0 1111 1111 1111 1111 38Eh INLVLC INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 1111 1111 1111 1111 38Fh INLVLD(3) INLVLD7 INLVLD6 INLVLD5 INLVLD4 INLVLD3 INLVLD2 INLVLD1 INLVLD0 1111 1111 1111 1111 Addr Name Bank 7 390h INLVLE(3) -- -- -- -- INLVLE3 INLVLE2 INLVLE1 INLVLE0 ---- 1111 ---- 1111 391h IOCAP IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 0000 0000 0000 0000 392h IOCAN IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 0000 0000 0000 0000 393h IOCAF IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 0000 0000 0000 0000 394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 0000 0000 0000 0000 395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 0000 0000 0000 0000 396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0000 0000 0000 0000 397h IOCCP IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 0000 0000 0000 0000 398h IOCCN IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 0000 0000 0000 0000 399h IOCCF IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 0000 0000 0000 0000 39Ah -- Unimplemented -- -- 39Bh -- Unimplemented -- -- 39Ch -- Unimplemented -- -- 39Dh IOCEP -- -- -- -- IOCEP3 -- -- -- ---- 0--- ---- 0--- 39Eh IOCEN -- -- -- -- IOCEN3 -- -- -- ---- 0--- ---- 0--- 39Fh IOCEF -- -- -- -- IOCEF3 -- -- -- ---- 0--- ---- 0--- Legend: Note 2015-2016 Microchip Technology Inc. 1: 2: 3: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. PIC16(L)F1777/8/9 DS40001819B-page 64 TABLE 3-18: 2015-2016 Microchip Technology Inc. TABLE 3-18: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- -- ---- --00 ---- --00 Bank 8 40Ch -- -- 40Ch Unimplemented 40Dh HIDRVB -- -- -- -- 40Eh -- Unimplemented 40Fh TMR5L Holding Register for the Least Significant Byte of the 16-bit TMR5 Register 410h TMR5H Holding Register for the Most Significant Byte of the 16-bit TMR5 Register 411h T5CON 412h T5GCON CS<1:0> GE CKPS<1:0> GPOL GTM GSPM -- -- HIDB1 OSCEN SYNC GGO/ DONE GVAL HIDB0 -- ON GSS<1:0> -- -- xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 0000 00-0 uuuu uu-u 0000 0x00 uuuu uxuu 413h T4TMR Holding Register for the 8-bit TMR4 Register 0000 0000 0000 0000 414h T4PR TMR4 Period Register 1111 1111 1111 1111 415h T4CON ON 0000 0000 0000 0000 416h T4HLT PSYNC CKPOL CKSYNC 417h T4CLKCON -- -- -- 418h T4RST -- -- -- 419h -- CKPS<2:0> Holding Register for the 8-bit TMR6 Register 41Bh T6PR TMR6 Period Register ON 41Dh T6HLT PSYNC CKPOL CKSYNC 41Eh T6CLKCON -- -- -- 41Fh T6RST -- -- -- 1: 2: 3: -- CS<3:0> RSEL<4:0> CKPS<2:0> OUTPS<3:0> MODE<4:0> -- x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. CS<3:0> RSEL<4:0> ---0 0000 ---0 0000 ---- 0000 ---- 0000 ---0 0000 ---0 0000 -- -- 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 ---0 0000 ---0 0000 ---- 0000 ---- 0000 ---0 0000 ---0 0000 DS40001819B-page 65 PIC16(L)F1777/8/9 41Ch T6CON Note MODE<4:0> Unimplemented 41Ah T6TMR Legend: OUTPS<3:0> Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- -- uuuu uuuu Bank 9 48Ch to -- 48Dh Unimplemented 48Eh ADRESL ADC Result Register Low xxxx xxxx 48Fh ADRESH ADC Result Register High xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0000 -000 0000 -000 --00 0000 --00 0000 490h ADCON0 CHS<5:0> GO/DONE ADCS<2:0> ADON 491h ADCON1 ADFM 492h ADCON2 -- 493h T2TMR Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000 494h T2PR TMR2 Period Register 1111 1111 1111 1111 495h T2CON ON 0000 0000 0000 0000 496h T2HLT PSYNC CKPOL CKSYNC 0000 0000 0000 0000 497h T2CLKCON -- -- -- ---- 0000 ---- 0000 498h T2RST -- -- -- ---0 0000 ---0 0000 499h -- CKPS<2:0> 49Bh T8PR TMR8 Period Register 49Ch T8CON ON 49Dh T8HLT PSYNC CKPOL CKSYNC 49Eh T8CLKCON -- -- -- 49Fh T8RST -- -- -- 2015-2016 Microchip Technology Inc. 1: 2: 3: OUTPS<3:0> MODE<4:0> -- CS<3:0> RSEL<4:0> Unimplemented Holding Register for the 8-bit TMR8 Register Note ADNREF TRIGSEL<5:0> 49Ah T8TMR Legend: -- -- CKPS<2:0> OUTPS<3:0> MODE<4:0> -- x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. CS<3:0> RSEL<4:0> ADPREF<1:0> -- -- 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 ---- 0000 ---- 0000 ---0 0000 ---0 0000 PIC16(L)F1777/8/9 DS40001819B-page 66 TABLE 3-18: 2015-2016 Microchip Technology Inc. TABLE 3-18: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- -- ---- 0000 Bank 10 50Ch -- -- 50Eh Unimplemented 50Fh OPA1NCHS -- -- -- -- NCH<3:0> ---- 0000 510h OPA1PCHS -- -- -- -- PCH<3:0> ---- 0000 ---- 0000 511h OPA1CON EN -- -- UG 0--0 -000 0--0 -000 512h OPA1ORS -- -- -- 513h OPA2NCHS -- -- -- 514h OPA2PCHS -- -- -- -- 515h OPA2CON EN -- -- UG 516h OPA2ORS -- -- -- 517h OPA3NCHS -- -- -- 518h OPA3PCHS -- -- -- -- 519h OPA3CON EN SP -- UG 51Ah OPA3ORS -- -- -- 51Bh OPA4NCHS(3) -- -- -- ORM<1:0> PCH<3:0> -- ORPOL ORM<1:0> ORS<4:0> -- -- -- SP -- UG -- -- -- NCH<3:0> PCH<3:0> -- Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. ORPOL ORS<4:0> ORM<1:0> ---0 0000 ---0 0000 ---- 0000 ---- 0000 ---- 0000 ---- 0000 0--0 -000 0--0 -000 ---0 0000 ---0 0000 ---- 0000 ---- 0000 ---- 0000 ---- 0000 00-0 -000 00-0 -000 ---0 0000 ---0 0000 ---- 0000 ---- 0000 ---- 0000 ---- 0000 00-0 -000 00-0 -000 ---0 0000 ---0 0000 -- -- DS40001819B-page 67 PIC16(L)F1777/8/9 1: 2: 3: ORPOL NCH<3:0> -- -- Note PCH<3:0> -- ORS<4:0> EN Legend: ORM<1:0> NCH<3:0> -- 51Dh OPA4CON(3) 51Fh -- ORPOL ORS<4:0> -- 51Ch OPA4PCHS(3) 51Eh OPA4ORS(3) -- Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- -- -- -- DAC2LD DAC1LD --00 --00 --00 --00 Bank 11 58Ch -- Unimplemented 58Dh DACLD -- -- DAC6LD(3) DAC5LD 58Eh DAC1CON0 EN FM OE1 OE2 58Fh DAC1REFL 590h DAC1REFH 591h DAC2CON0 592h DAC2REFL FM OE1 OE2 DAC2REFH DAC3CON0 EN -- OE1 595h DAC3REF -- -- -- 596h DAC4CON0 EN -- OE1 597h DAC4REF -- -- -- 598h DAC5CON0 EN FM OE1 599h DAC5REFL PSS<1:0> NSS<1:0> REF<4:0> OE2 PSS<1:0> OE2 PSS<1:0> NSS<1:0> REF<4:0> NSS<1:0> REF<7:0> REF<15:8> EN FM OE1 OE2 59Ch DAC6REFL(3) PSS<1:0> NSS<1:0> REF<7:0> 59Dh DAC6REFH(3) REF<15:8> 59Eh DAC7CON0 EN -- OE1 59Fh DAC7REF -- -- -- 2015-2016 Microchip Technology Inc. 1: 2: 3: NSS<1:0> REF<15:8> OE2 59Ah DAC5REFH Note PSS<1:0> REF<7:0> 593h Legend: NSS<1:0> REF<15:8> EN 594h 59Bh DAC6CON0(3) PSS<1:0> REF<7:0> OE2 PSS<1:0> x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. REF<4:0> NSS<1:0> 0000 0000 0000 0000 00000 0000 0000 0000 00000 0000 0000 0000 0000 0000 0000 0000 00000 0000 0000 0000 00000 0000 0000 0000 0-00 0000 0-00 0000 ---0 0000 ---0 0000 0-00 0000 0-00 0000 ---0 0000 0000 0000 0000 0000 0000 0000 00000 0000 0000 0000 00000 0000 0000 0000 0000 0000 0000 0000 00000 0000 0000 0000 00000 0000 0000 0000 0-00 0000 0-00 0000 ---0 0000 0000 0000 PIC16(L)F1777/8/9 DS40001819B-page 68 TABLE 3-18: 2015-2016 Microchip Technology Inc. TABLE 3-18: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- -- 0-00 0000 0-00 0000 Bank 12 60Ch to -- 613h Unimplemented 60Ch DAC8CON0(3) EN -- OE1 60Dh DAC8REF(3) -- -- -- 60Eh PRG4RTSS(3) -- -- -- -- 60Fh PRG4FTSS(3) OE2 PSS<1:0> NSS1 NSS0 REF<4:0> ---0 0000 0000 0000 RTSS<3:0> ---- 0000 ---- 0000 ---- 0000 -- -- -- -- FTSS<3:0> ---- 0000 610h PRG4INS(3) -- -- -- -- INS<3:0> ---- 0000 ---- 0000 611h PRG4CON0(3) EN -- FEDG REDG -- 612h PRG4CON1(3) -- -- -- 613h PRG4CON2(3) -- -- -- 614h PWM3DCL 615h PWM3DCH 616h PWM3CON 617h PWM4DCL 618h PWM4DCH 619h PWM4CON DC<1:0> -- DC<1:0> -- -- FPOL RPOL ---- -000 ---- -000 OUT -- EN -- DC<1:0> -- DC<1:0> -- uu-- ---- -- -- xxxx xxxx uuuu uuuu POL -- -- -- -- 0-00 ---- 0-00 ---- -- -- -- -- -- xx-- ---- uu-- ---- xxxx xxxx uuuu uuuu OUT POL -- -- -- -- 0-00 ---- 0-00 ---- -- -- -- -- -- -- xx-- ---- uu-- ---- xxxx xxxx uuuu uuuu OUT POL -- -- -- -- 0-00 ---- 0-00 ---- -- -- -- -- -- -- xx-- ---- uu-- ---- DC<9:2> EN ---0 0000 xx-- ---- -- DC<9:2> EN ---0 0000 OUT POL -- x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. -- -- -- xxxx xxxx uuuu uuuu 0-00 ---- 0-00 ---- DS40001819B-page 69 PIC16(L)F1777/8/9 1: 2: 3: 0-00 0000 -- 61Eh PWM10DCH(3) Note 0-000 0000 DC<9:2> 61Dh PWM10DCL(3) Legend: RDY GO ISET<4:0> 61Bh PWM9DCH 61Fh PWM10CON(3) -- OS DC<9:2> EN 61Ah PWM9DCL 61Ch PWM9CON MODE<1:0> Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 13 68Ch -- -- -- 68Dh COG1PHR Unimplemented -- -- COG Rising Edge Phase Delay Count Register --00 0000 --00 0000 68Eh COG1PHF -- -- COG Falling Edge Phase Delay Count Register --00 0000 --00 0000 68Fh COG1BLKR -- -- COG Rising Edge Blanking Count Register --00 0000 --00 0000 690h COG1BLKF -- -- COG Falling Edge Blanking Count Register --00 0000 --00 0000 691h COG1DBR -- -- COG Rising Edge Dead-band Count Register --00 0000 --00 0000 692h COG1DBF -- -- COG Falling Edge Dead-band Count Register --00 0000 --00 0000 693h COG1CON0 EN LD -- 694h COG1CON1 RDBS FDBS -- 695h COG1RIS0 RIS7 RIS6 RIS5 RIS4 RIS3 RIS2 696h COG1RIS1 RIS15 RIS14 RIS13 RIS12 RIS11 RIS10 697h COG1RSIM0 RSIM7 RSIM6 RSIM5 RSIM4 RSIM3 RSIM2 698h COG1RSIM1 RSIM15 RSIM14 RSIM13 RSIM12 RSIM11 699h COG1FIS0 FIS7 FIS6 FIS5 FIS4 FIS3 69Ah COG1FIS1 FIS15 FIS14 FIS13 FIS12 69Bh COG1FSIM0 FSIM7 FSIM6 FSIM5 69Ch COG1FSIM1 FSIM15 FSIM14 FSIM13 69Dh COG1ASD0 ASE ARSEN CS<1:0> MD<2:0> 00-0 0000 00-0 0000 POLA 00-- 0000 00-- 0000 RIS1 RIS0 0000 0000 0000 0000 RIS9 RIS8 0000 0000 0000 0000 RSIM1 RSIM0 0000 0000 0000 0000 RSIM10 RSIM9 RSIM8 0000 0000 0000 0000 FIS2 FIS1 FIS0 0000 0000 0000 0000 FIS11 FIS10 FIS9 FIS8 0000 0000 0000 0000 FSIM4 FSIM3 FSIM2 FSIM1 FSIM0 0000 0000 0000 0000 FSIM12 FSIM11 FSIM10 FSIM9 FSIM8 0000 0000 0000 0000 -- -- 0001 01-- 0001 01-- -- ASDBD<1:0> POLD POLC ASDAC<1:0> POLB 69Eh COG1ASD1 AS7E AS6E AS5E AS4E AS3E AS2E AS1E AS0E 0000 0000 0000 0000 69Fh COG1STR SDATD SDATC SDATB SDATA STRD STRC STRB STRA 0000 0000 0000 0000 Legend: Note 2015-2016 Microchip Technology Inc. 1: 2: 3: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. PIC16(L)F1777/8/9 DS40001819B-page 70 TABLE 3-18: 2015-2016 Microchip Technology Inc. TABLE 3-18: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 14 70Ch -- -- -- 70Dh COG2PHR Unimplemented -- -- COG Rising Edge Phase Delay Count Register --00 0000 --00 0000 70Eh COG2PHF -- -- COG Falling Edge Phase Delay Count Register --00 0000 --00 0000 70Fh COG2BLKR -- -- COG Rising Edge Blanking Count Register --00 0000 --00 0000 710h COG2BLKF -- -- COG Falling Edge Blanking Count Register --00 0000 --00 0000 711h COG2DBR -- -- COG Rising Edge Dead-band Count Register --00 0000 --00 0000 712h COG2DBF -- -- COG Falling Edge Dead-band Count Register --00 0000 --00 0000 713h COG2CON0 EN LD -- 714h COG2CON1 RDBS FDBS -- 715h COG2RIS0 RIS7 RIS6 RIS5 RIS4 RIS3 RIS2 716h COG2RIS1 RIS15 RIS14 RIS13 RIS12 RIS11 RIS10 717h COG2RSIM0 RSIM7 RSIM6 RSIM5 RSIM4 RSIM3 RSIM2 718h COG2RSIM1 RSIM15 RSIM14 RSIM13 RSIM12 RSIM11 719h COG2FIS0 FIS7 FIS6 FIS5 FIS4 71Ah COG2FIS1 FIS15 FIS14 FIS13 71Bh COG2FSIM0 FSIM7 FSIM6 71Ch COG2FSIM1 FSIM15 FSIM14 71Dh COG2ASD0 ASE ARSEN CS<1:0> MD<2:0> 00-0 0000 00-0 0000 POLA 00-- 0000 00-- 0000 RIS1 RIS0 0000 0000 0000 0000 RIS9 RIS8 0000 0000 0000 0000 RSIM1 RSIM0 0000 0000 0000 0000 RSIM10 RSIM9 RSIM8 0000 0000 0000 0000 FIS3 FIS2 FIS1 FIS0 0000 0000 0000 0000 FIS12 FIS11 FIS10 FIS9 FIS8 0000 0000 0000 0000 FSIM5 FSIM4 FSIM3 FSIM2 FSIM1 FSIM0 0000 0000 0000 0000 FSIM13 FSIM12 FSIM11 FSIM10 FSIM9 FSIM8 0000 0000 0000 0000 -- -- 0001 01-- 0001 01-- -- ASDBD<1:0> POLD POLC ASDAC<1:0> POLB AS7E AS6E AS5E AS4E AS3E AS2E AS1E AS0E 0000 0000 0000 0000 71Fh COG2STR SDATD SDATC SDATB SDATA STRD STRC STRB STRA 0000 0000 0000 0000 Legend: Note 1: 2: 3: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. DS40001819B-page 71 PIC16(L)F1777/8/9 71Eh COG2ASD1 Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- -- Bank 15 78Ch -- -- 78Dh Unimplemented 78Eh PRG1RTSS -- -- -- -- RTSS<3:0> ---- 0000 ---- 0000 78Fh PRG1FTSS -- -- -- -- FTSS<3:0> ---- 0000 ---- 0000 790h PRG1INS -- -- -- -- INS<3:0> ---- 0000 ---- 0000 791h PRG1CON0 EN -- FEDG REDG -- 792h PRG1CON1 -- -- -- 793h PRG1CON2 -- -- -- 794h PRG2RTSS -- -- -- -- 795h PRG2FTSS -- -- -- 796h PRG2INS -- -- -- 797h PRG2CON0 EN -- FEDG REDG -- MODE<1:0> -- RDY OS GO 0-000 0000 0-00 0000 FPOL RPOL ---- -000 ---- -000 ISET<4:0> ---0 0000 ---0 0000 RTSS<3:0> ---- 0000 ---- 0000 -- FTSS<3:0> ---- 0000 ---- 0000 -- INS<3:0> ---- 0000 ---- 0000 798h PRG2CON1 -- -- -- 799h PRG2CON2 -- -- -- 79Ah PRG3RTSS -- -- -- -- MODE<1:0> -- RDY OS GO 0-000 0000 0-00 0000 FPOL RPOL ---- -000 ---- -000 ISET<4:0> ---0 0000 ---0 0000 RTSS<3:0> ---- 0000 ---- 0000 ---- 0000 79Bh PRG3FTSS -- -- -- -- FTSS<3:0> ---- 0000 79Ch PRG3INS -- -- -- -- INS<3:0> ---- 0000 ---- 0000 79Dh PRG3CON0 EN -- FEDG REDG 79Eh PRG3CON1 -- -- -- -- 79Fh PRG3CON2 -- -- -- Legend: Note 2015-2016 Microchip Technology Inc. 1: 2: 3: MODE<1:0> -- x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. RDY ISET<4:0> OS GO 0-000 0000 0-00 0000 FPOL RPOL ---- -000 ---- -000 ---0 0000 ---0 0000 PIC16(L)F1777/8/9 DS40001819B-page 72 TABLE 3-18: 2015-2016 Microchip Technology Inc. TABLE 3-18: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 16 80Ch -- -- -- 80Dh COG3PHR Unimplemented -- -- COG Rising Edge Phase Delay Count Register --00 0000 --00 0000 80Eh COG3PHF -- -- COG Falling Edge Phase Delay Count Register --00 0000 --00 0000 80Fh COG3BLKR -- -- COG Rising Edge Blanking Count Register --00 0000 --00 0000 810h COG3BLKF -- -- COG Falling Edge Blanking Count Register --00 0000 --00 0000 811h COG3DBR -- -- COG Rising Edge Dead-band Count Register --00 0000 --00 0000 812h COG3DBF -- -- COG Falling Edge Dead-band Count Register --00 0000 --00 0000 813h COG3CON0 EN LD -- 814h COG3CON1 RDBS FDBS -- -- POLD POLC POLB 815h COG3RIS0 RIS7 RIS6 RIS5 RIS4 RIS3 RIS2 RIS15 RIS14 RIS13 RIS12 RIS11 RIS10 CS<1:0> MD<2:0> 00-0 0000 00-0 0000 POLA 00-- 0000 00-- 0000 RIS1 RIS0 0000 0000 0000 0000 RIS9 RIS8 0000 0000 0000 0000 0000 0000 0000 0000 816h COG3RIS1 817h COG3RSIM0 RSIM7 RSIM6 RSIM5 RSIM4 RSIM3 RSIM2 RSIM1 RSIM0 818h COG3RSIM1 RSIM15 RSIM14 RSIM13 RSIM12 RSIM11 RSIM10 RSIM9 RSIM8 0000 0000 0000 0000 819h 0000 0000 0000 0000 FIS7 FIS6 FIS5 FIS4 FIS3 FIS2 FIS1 FIS0 FIS15 FIS14 FIS13 FIS12 FIS11 FIS10 FIS9 FIS8 0000 0000 0000 0000 81Bh COG3FSIM0 FSIM7 FSIM6 FSIM5 FSIM4 FSIM3 FSIM2 FSIM1 FSIM0 0000 0000 0000 0000 81Ch COG3FSIM1 FSIM15 FSIM14 FSIM13 FSIM12 FSIM11 FSIM10 FSIM9 FSIM8 0000 0000 0000 0000 81Dh COG3ASD0 ASE ARSEN -- -- 0001 01-- 0001 01-- 81Eh COG3ASD1 AS7E AS6E AS5E AS4E AS3E AS2E AS1E AS0E 0000 0000 0000 0000 81Fh COG3STR SDATD SDATC SDATB SDATA STRD STRC STRB STRA 0000 0000 0000 0000 Legend: Note 1: 2: 3: ASDBD<1:0> ASDAC<1:0> x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. DS40001819B-page 73 PIC16(L)F1777/8/9 COG3FIS0 81Ah COG3FIS1 Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 17 88Ch -- -- -- 88Dh COG4PHR(3) Unimplemented -- -- COG Rising Edge Phase Delay Count Register --00 0000 --00 0000 88Eh COG4PHF(3) -- -- COG Falling Edge Phase Delay Count Register --00 0000 --00 0000 88Fh COG4BLKR(3) -- -- COG Rising Edge Blanking Count Register --00 0000 --00 0000 890h COG4BLKF(3) -- -- COG Falling Edge Blanking Count Register --00 0000 --00 0000 891h COG4DBR(3) -- -- COG Rising Edge Dead-band Count Register --00 0000 --00 0000 892h COG4DBF(3) -- -- COG Falling Edge Dead-band Count Register --00 0000 --00 0000 893h COG4CON0(3) EN LD -- 894h COG4CON1(3) RDBS FDBS -- -- POLD POLC POLB POLA 895h COG4RIS0(3) RIS7 RIS6 RIS5 RIS4 RIS3 RIS2 RIS1 RIS0 0000 0000 0000 0000 896h (3) COG4RIS1 RIS15 RIS14 RIS13 RIS12 RIS11 RIS10 RIS9 RIS8 0000 0000 0000 0000 897h COG4RSIM0(3) RSIM7 RSIM6 RSIM5 RSIM4 RSIM3 RSIM2 RSIM1 RSIM0 0000 0000 0000 0000 898h COG4RSIM1(3) RSIM15 RSIM14 RSIM13 RSIM12 RSIM11 RSIM10 RSIM9 RSIM8 0000 0000 0000 0000 899h COG4FIS0(3) FIS7 FIS6 FIS5 FIS4 FIS3 FIS2 FIS1 FIS0 0000 0000 0000 0000 0000 0000 CS<1:0> MD<2:0> 00-0 0000 00-0 0000 00-- 0000 00-- 0000 89Ah COG4FIS1(3) FIS15 FIS14 FIS13 FIS12 FIS11 FIS10 FIS9 FIS8 0000 0000 89Bh COG4FSIM0(3) FSIM7 FSIM6 FSIM5 FSIM4 FSIM3 FSIM2 FSIM1 FSIM0 0000 0000 0000 0000 FSIM8 0000 0000 0000 0000 0001 01-- 89Ch COG4FSIM1(3) FSIM15 FSIM14 COG4ASD0(3) ASE ARSEN -- -- 0001 01-- 89Eh COG4ASD1(3) AS7E AS6E AS5E AS4E AS3E AS2E AS1E AS0E 0000 0000 0000 0000 SDATD SDATC SDATB SDATA STRD STRC STRB STRA 0000 0000 0000 0000 89Dh 89Fh COG4STR(3) Legend: 2015-2016 Microchip Technology Inc. Note 1: 2: 3: FSIM13 FSIM12 ASDBD<1:0> FSIM11 FSIM10 ASDAC<1:0> x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. FSIM9 PIC16(L)F1777/8/9 DS40001819B-page 74 TABLE 3-18: 2015-2016 Microchip Technology Inc. TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets 90Ch CM4CON0 ON OUT -- POL ZLF Reserved HYS SYNC 00-0 0100 00-0 0100 90Dh CM4CON1 -- -- -- -- -- -- INTP INTN ---- --00 ---- --00 90Eh CM4NSEL -- -- -- -- NCH<3:0> ---- 0000 ---- 0000 90Fh CM4PSEL -- -- -- -- PCH<3:0> ---- 0000 ---- 0000 910h CM5CON0 ON OUT -- POL ZLF Reserved HYS SYNC 00-0 0100 00-0 0100 911h CM5CON1 -- -- -- -- -- -- INTP INTN ---- --00 ---- --00 912h CM5NSEL -- -- -- -- NCH<3:0> ---- 0000 ---- 0000 913h CM5PSEL -- -- -- -- PCH<3:0> ---- 0000 ---- 0000 914h CM6CON0 ON OUT -- POL ZLF Reserved HYS SYNC 00-0 0100 00-0 0100 915h CM6CON1 -- -- -- -- -- -- INTP INTN ---- --00 ---- --00 916h CM6NSEL -- -- -- -- NCH<3:0> ---- 0000 ---- 0000 917h CM6PSEL -- -- -- -- PCH<3:0> ---- 0000 ---- 0000 918h CM7CON0(3) ON OUT -- POL ZLF Reserved HYS SYNC 00-0 0100 00-0 0100 919h CM7CON1(3) -- -- -- -- -- -- INTP INTN ---- --00 ---- --00 91Ah CM7NSEL(3) -- -- -- -- NCH<3:0> ---- 0000 ---- 0000 91Bh CM7PSEL(3) -- -- -- -- PCH<3:0> ---- 0000 ---- 0000 91Ch CM8CON0(3) ON OUT -- POL ZLF Reserved HYS SYNC 00-0 0100 00-0 0100 91Dh CM8CON1(3) -- -- -- -- -- -- INTP INTN ---- --00 ---- --00 91Eh CM8NSEL(3) -- -- -- -- NCH<3:0> ---- 0000 ---- 0000 91Fh CM8PSEL(3) -- -- -- -- PCH<3:0> ---- 0000 ---- 0000 -- -- Addr Name Bank 18 x0Ch/ -- x8Ch -- x1Fh/ x9Fh Legend: Note DS40001819B-page 75 1: 2: 3: Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. PIC16(L)F1777/8/9 Bank 19-25 Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- -- 0-00 ---0 Bank 26 D0Ch -- -- D1Ah Unimplemented D1Bh MD4CON0(3) EN -- OUT OPOL -- -- -- BIT 0-00 ---0 D1Ch MD4CON1(3) -- -- CHPOL CHSYNC -- -- CLPOL CLSYNC --00 --00 --00 --00 D1Dh MD4SRC(3) -- -- -- MS<4:0> ---0 0000 ---0 0000 D1Eh MD4CARL(3) -- -- -- CL<4:0> ---0 0000 ---0 0000 D1Fh MD4CARH(3) -- -- -- CH<4:0> ---0 0000 ---0 0000 Legend: Note 1: 2: 3: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. PIC16(L)F1777/8/9 DS40001819B-page 76 TABLE 3-18: 2015-2016 Microchip Technology Inc. Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- Bank 27 D8Ch -- Unimplemented -- D8Dh -- Unimplemented -- -- MPWM5EN ---- 0000 ---- 0000 ---- 0000 D8Eh PWMEN -- -- -- -- MPWM12EN(3) D8Fh PWMLD -- -- -- -- MPWM12LD(3) MPWM11LD MPWM6LD MPWM5LD ---- 0000 D90h PWMOUT -- -- -- -- MPWM12OUT(3) MPWM11OUT MPWM6OUT MPWM5OUT ---- 0000 ---- 0000 MPWM11EN MPWM6EN D91h PWM5PHL PH<7:0> xxxx xxxx uuuu uuuu D92h PWM5PHH PH<15:8> xxxx xxxx uuuu uuuu D93h PWM5DCL DC<7:0> xxxx xxxx uuuu uuuu D94h PWM5DCH DC<15:8> xxxx xxxx uuuu uuuu D95h PWM5PRL PR<7:0> xxxx xxxx uuuu uuuu D96h PWM5PRH PR<15:8> xxxx xxxx uuuu uuuu D97h PWM5OFL OF<7:0> xxxx xxxx uuuu uuuu D98h PWM5OFH OF<15:8> xxxx xxxx uuuu uuuu D99h PWM5TMRL TMR<7:0> 0000 0000 0000 0000 D9Ah PWM5TMRH TMR<15:8> 0000 0000 0000 0000 D9Bh PWM5CON EN -- OUT POL -- -- 0-00 00-- 0-00 00-- D9Ch PWM5INTE -- -- -- -- OFIE PHIE DCIE PRIE ---- 0000 ---- 0000 D9Dh PWM5INTF -- -- -- -- OFIF PHIF DCIF PRIF ---- 0000 ---- 0000 D9Eh PWM5CLKCON -- -- -- CS<1:0> -000 --00 -000 --00 -- -- -- LDS<1:0> 00-- --00 00-- --00 OFO -- -- OFS<1:0> -000 --00 -000 --00 D9Fh PWM5LDCON LDA DA0h PWM5OFCON -- MODE<1:0> PS<2:0> LDT -- OFM<1:0> 2015-2016 Microchip Technology Inc. DA1h PWM6PHL PH<7:0> xxxx xxxx uuuu uuuu DA2h PWM6PHH PH<15:8> xxxx xxxx uuuu uuuu DA3h PWM6DCL DC<7:0> xxxx xxxx uuuu uuuu DA4h PWM6DCH DC<15:8> xxxx xxxx uuuu uuuu DA5h PWM6PRL PR<7:0> xxxx xxxx uuuu uuuu DA6h PWM6PRH PR<15:8> xxxx xxxx uuuu uuuu DA7h PWM6OFL OF<7:0> xxxx xxxx uuuu uuuu DA8h PWM6OFH OF<15:8> xxxx xxxx uuuu uuuu DA9h PWM6TMRL TMR<7:0> 0000 0000 0000 0000 DAAh PWM6TMRH TMR<15:8> 0000 0000 0000 0000 Legend: Note 1: 2: 3: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. PIC16(L)F1777/8/9 DS40001819B-page 77 TABLE 3-18: 2015-2016 Microchip Technology Inc. TABLE 3-18: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 DABh PWM6CON EN -- OUT POL DACh PWM6INTE -- -- -- -- DADh PWM6INTF -- -- -- -- DAEh PWM6CLKCON -- Bit 3 Bit 0 Value on POR, BOR Value on all other Resets -- -- 0-00 00-- 0-00 00-- DCIE PRIE ---- 0000 ---- 0000 PRIF ---- 0000 ---- 0000 CS<1:0> -000 --00 -000 --00 -- LDS<1:0> 00-- --00 00-- --00 -- OFS<1:0> -000 --00 -000 --00 Bit 2 Bit 1 OFIE PHIE OFIF PHIF DCIF -- -- -- -- OFO -- Bank 27 (Continued) DAFh PWM6LDCON LDA DB0h PWM6OFCON -- MODE<1:0> PS<2:0> LDT -- OFM<1:0> DB1h PWM11PHL PH<7:0> xxxx xxxx uuuu uuuu DB2h PWM11PHH PH<15:8> xxxx xxxx uuuu uuuu DB3h PWM11DCL DC<7:0> xxxx xxxx uuuu uuuu DB4h PWM11DCH DC<15:8> xxxx xxxx uuuu uuuu DB5h PWM11PRL PR<7:0> xxxx xxxx uuuu uuuu DB6h PWM11PRH PR<15:8> xxxx xxxx uuuu uuuu DB7h PWM11OFL OF<7:0> xxxx xxxx uuuu uuuu DB8h PWM11OFH OF<15:8> xxxx xxxx uuuu uuuu DB9h PWM11TMRL TMR<7:0> 0000 0000 0000 0000 DBAh PWM11TMRH TMR<15:8> 0000 0000 0000 0000 EN -- OUT POL DBCh PWM11INTE -- -- -- -- OFIE DBDh PWM11INTF -- -- -- -- DBEh PWM11CLKCON -- DBFh PWM11LDCON LDA DC0h PWM11OFCON -- Legend: Note 1: 2: 3: -- -- 0-00 00-- 0-00 00-- PHIE DCIE PRIE ---- 0000 ---- 0000 OFIF PHIF DCIF PRIF ---- 0000 ---- 0000 -- -- CS<1:0> -000 --00 -000 --00 -- -- -- LDS<1:0> 00-- --00 00-- --00 OFO -- -- OFS<1:0> -000 --00 -000 --00 PS<2:0> LDT -- OFM<1:0> MODE<1:0> x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. DS40001819B-page 78 PIC16(L)F1777/8/9 DBBh PWM11CON Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets xxxx xxxx uuuu uuuu Bank 27 (Continued) DC1h PWM12PHL(3) PH<7:0> DC2h PWM12PHH PH<15:8> xxxx xxxx uuuu uuuu DC3h PWM12DCL(3) DC<7:0> xxxx xxxx uuuu uuuu DC4h PWM12DCH(3) DC<15:8> xxxx xxxx uuuu uuuu DC5h PWM12PRL(3) PR<7:0> xxxx xxxx uuuu uuuu DC6h PWM12PRH(3) PR<15:8> xxxx xxxx uuuu uuuu DC7h PWM12OFL OF<7:0> xxxx xxxx uuuu uuuu DC8h PWM12OFH(3) OF<15:8> xxxx xxxx uuuu uuuu (3) (3) DC9h PWM12TMRL TMR<7:0> 0000 0000 0000 0000 DCAh PWM12TMRH(3) TMR<15:8> 0000 0000 0000 0000 (3) DCBh PWM12CON(3) EN -- OUT POL -- -- 0-00 00-- 0-00 00-- DCCh PWM12INTE(3) -- -- -- -- OFIE PHIE DCIE PRIE ---- 0000 ---- 0000 DCDh PWM12INTF -- -- -- -- OFIF PHIF DCIF PRIF -- -- -- -- OFO -- (3) DCEh PWM12CLKCON(3) DCFh PWM12LDCON (3) DD0h PWM12OFCON(3) DD1h to -- DEFh Legend: Note 2015-2016 Microchip Technology Inc. 1: 2: 3: -- LDA -- PS<2:0> LDT -- OFM<1:0> MODE<1:0> Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. ---- 0000 ---- 0000 CS<1:0> -000 --00 -000 --00 -- LDS<1:0> 00-- --00 00-- --00 -- OFS<1:0> -000 --00 -000 --00 -- -- PIC16(L)F1777/8/9 DS40001819B-page 79 TABLE 3-18: 2015-2016 Microchip Technology Inc. TABLE 3-18: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- -- Bank 28 E0Ch -- E0Bh -- Unimplemented -- -- ---- ---0 ---- ---0 E0Dh INTPPS -- -- INTPPS<5:0> --00 1000 --uu uuuu E0Eh T0CKIPPS -- -- T0CKIPPS<5:0> --00 0100 --uu uuuu E0Fh T1CKIPPS -- -- T1CKIPPS<5:0> --01 0000 --uu uuuu E10h T1GPPS -- -- T1GPPS<5:0> --00 1101 --uu uuuu E11h T3CKIPPS -- -- T3CKIPPS<5:0> --01 0000 --uu uuuu E12h T3GPPS -- -- T3GPPS<5:0> --01 0000 --uu uuuu E13h T5CKIPPS -- -- T5CKIPPS<5:0> --01 0000 --uu uuuu E14h T5GPPS -- -- T5GPPS<5:0> --00 1100 --uu uuuu E15h T2INPPS -- -- T2INPPS<5:0> --01 0011 --uu uuuu E16h T4INPPS -- -- T4INPPS<5:0> --01 0101 --uu uuuu E17h T6INPPS -- -- T6INPPS<5:0> --01 0100 --uu uuuu E18h T8INPPS -- -- T8INPPS<5:0> --01 0010 --uu uuuu E19h CCP1PPS -- -- CCP1PPS<5:0> --01 0010 --uu uuuu E1Ah CCP2PPS -- -- CCP2PPS<5:0> --01 0001 --uu uuuu E1Bh CCP7PPS -- -- CCP7PPS<5:0> --00 1101 --uu uuuu E1Ch CCP8PPS(3) -- -- CCP8PPS<5:0> --00 1101 --uu uuuu E1Dh COGIN1PPS -- -- COG1PPS<5:0> --00 1000 --uu uuuu E1Eh COG2INPPS -- -- COG2PPS<5:0> --00 1001 --uu uuuu E1Fh COG3INPPS -- -- COG3PPS<5:0> --00 1010 --uu uuuu E20h COG4INPPS(3) -- -- COG4PPS<5:0> --00 1010 --uu uuuu E21h MD1CLPPS -- -- MD1CLPPS<5:0> --00 0100 --uu uuuu E22h MD1CHPPS -- -- MD1CHPPS<5:0> --00 0011 --uu uuuu E23h MD1MODPPS -- -- MD1MODPPS<5:0> --00 0101 --uu uuuu E24h MD2CLPPS -- -- MD2CLPPS<5:0> --00 0100 --uu uuuu E25h MD2CHPPS -- -- MD2CHPPS<5:0> --00 0011 --uu uuuu E26h MD2MODPPS -- -- MD2MODPPS<5:0> --00 0101 --uu uuuu Legend: Note 1: 2: 3: -- -- -- -- x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. -- PPSLOCKED PIC16(L)F1777/8/9 DS40001819B-page 80 E0Ch PPSLOCK SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) 2015-2016 Microchip Technology Inc. Value on POR, BOR Value on all other Resets MD3CLPPS<5:0> --00 1100 --uu uuuu MD3CHPPS<5:0> --00 1011 --uu uuuu MD3MODPPS<5:0> --00 0101 --uu uuuu -- MD4CLPPS<5:0> --00 1100 --uu uuuu -- -- MD4CHPPS<5:0> --00 1011 --uu uuuu E2Ch MD4MODPPS(3) -- -- MD4MODPPS<5:0> --00 0101 --uu uuuu E2Dh PRG1RPPS -- -- PRG1RPPS<5:0> --00 0100 --uu uuuu E2Eh PRG1FPPS -- -- PRG1FPPS<5:0> --00 0101 --uu uuuu E2Fh PRG2RPPS -- -- PRG2RPPS<5:0> --01 0001 --uu uuuu E30h PRG2FPPS -- -- PRG2FPPS<5:0> --01 0010 --uu uuuu E31h PRG3RPPS -- -- PRG3RPPS<5:0> --01 0100 --uu uuuu E32h PRG3FPPS -- -- PRG3FPPS<5:0> --01 0101 --uu uuuu E33h PRG4RPPS(3) -- -- PRG4RPPS<5:0> --01 0100 --uu uuuu E34h PRG4FPPS(3) -- -- PRG4FPPS<5:0> --01 0101 --uu uuuu E35h CLC1IN0PPS -- -- CLCIN0PPS<5:0> --00 0000 --uu uuuu E36h CLC1IN1PPS -- -- CLCIN1PPS<5:0> --00 0001 --uu uuuu E37h CLC1IN2PPS -- -- CLCIN2PPS<5:0> --00 1110 --uu uuuu E38h CLC1IN3PPS -- -- CLCIN3PPS<5:0> --00 1111 --uu uuuu E39h ADCACTPPS -- -- ADCACTPPS<5:0> --00 1100 --uu uuuu E3Ah SSPCLKPPS -- -- SSPCLKPPS<5:0> --01 0011 --uu uuuu E3Bh SSPDATPPS -- -- SSPDATPPS<5:0> --01 0100 --uu uuuu E3Ch SSPSSPPS -- -- SSPSSPPS<5:0> --00 0101 --uu uuuu E3Dh RXPPS -- -- RXPPS<5:0> --01 0111 --uu uuuu E3Eh CKPPS -- -- CKPPS<5:0> --01 0110 --uu uuuu -- -- Addr Name Bit 7 Bit 6 E27h MD3CLPPS -- -- E28h MD3CHPPS -- -- E29h MD3MODPPS -- -- E2Ah MD4CLPPS(3) -- E2Bh MD4CHPPS(3) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank 28 (Continued) E3Fh -- -- E6Fh Legend: Note 1: 2: 3: Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. PIC16(L)F1777/8/9 DS40001819B-page 81 TABLE 3-18: 2015-2016 Microchip Technology Inc. TABLE 3-18: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- -- Bank 29 E8Ch -- -- E8Fh Unimplemented -- -- RA0PPS<4:0> --00 0000 --uu uuuu -- -- RA1PPS<4:0> --00 0000 --uu uuuu E92h RA2PPS -- -- RA2PPS<4:0> --00 0000 --uu uuuu E93h RA3PPS -- -- RA3PPS<4:0> --00 0000 --uu uuuu E94h RA4PPS -- -- RA4PPS<4:0> --00 0000 --uu uuuu E95h RA5PPS -- -- RA5PPS<4:0> --00 0000 --uu uuuu E96h RA6PPS -- -- RA6PPS<4:0> --00 0000 --uu uuuu E97h RA7PPS -- -- RA7PPS<4:0> --00 0000 --uu uuuu E98h RB0PPS -- -- RB0PPS<5:0> --00 0000 --uu uuuu E99h RB1PPS -- -- RB1PPS<5:0> --00 0000 --uu uuuu E9Ah RB2PPS -- -- RB2PPS<5:0> --00 0000 --uu uuuu E9Bh RB3PPS -- -- RB3PPS<5:0> --00 0000 --uu uuuu E9Ch RB4PPS -- -- RB4PPS<5:0> --00 0000 --uu uuuu E9Dh RB5PPS -- -- RB5PPS<5:0> --00 0000 --uu uuuu E9Eh RB6PPS -- -- RB6PPS<5:0> --00 0000 --uu uuuu E9Fh RB7PPS -- -- RB7PPS<5:0> --00 0000 --uu uuuu EA0h RC0PPS -- -- RC0PPS<5:0> --00 0000 --uu uuuu EA1h RC1PPS -- -- RC1PPS<5:0> --00 0000 --uu uuuu EA2h RC2PPS -- -- RC2PPS<5:0> --00 0000 --uu uuuu EA3h RC3PPS -- -- RC3PPS<5:0> --00 0000 --uu uuuu EA4h RC4PPS -- -- RC4PPS<5:0> --00 0000 --uu uuuu EA5h RC5PPS -- -- RC5PPS<5:0> --00 0000 --uu uuuu EA6h RC6PPS -- -- RC6PPS<5:0> --00 0000 --uu uuuu EA7h RC7PPS -- -- RC7PPS<5:0> --00 0000 --uu uuuu Legend: DS40001819B-page 82 Note 1: 2: 3: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. PIC16(L)F1777/8/9 E90h RA0PPS E91h RA1PPS SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on POR, BOR Value on all other Resets RD0PPS<5:0> --00 0000 --uu uuuu -- RD1PPS<5:0> --00 0000 --uu uuuu -- RD2PPS<5:0> --00 0000 --uu uuuu -- -- RD3PPS<5:0> --00 0000 --uu uuuu -- -- RD4PPS<5:0> --00 0000 --uu uuuu (3) EADh RD5PPS -- -- RD5PPS<5:0> --00 0000 --uu uuuu EAEh RD6PPS(3) -- -- RD6PPS<5:0> --00 0000 --uu uuuu RD7PPS(3) -- -- RD7PPS<5:0> --00 0000 --uu uuuu EB0h RE0PPS(3) -- -- RE0PPS<5:0> --00 0000 --uu uuuu EB1h RE1PPS(3) -- -- RE1PPS<5:0> --00 0000 --uu uuuu EB2h RE2PPS(3) -- -- RE2PPS<5:0> --00 0000 --uu uuuu -- -- Addr Name Bit 7 Bit 6 EA8h RD0PPS(3) -- -- (3) EA9h RD1PPS -- EAAh RD2PPS(3) -- (3) EABh RD3PPS EACh RD4PPS(3) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank 29 (Cont.) EAFh EB3h to -- EEFh Legend: Note 1: 2: 3: Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. PIC16(L)F1777/8/9 DS40001819B-page 83 TABLE 3-18: 2015-2016 Microchip Technology Inc. 2015-2016 Microchip Technology Inc. TABLE 3-18: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- -- Bank 30 F0Ch -- -- F0Eh Unimplemented F0Fh CLCDATA -- -- -- -- MLC4OUT F10h CLC1CON EN -- OUT INTP INTN F11h -- -- G4POL CLC1POL MLC3OUT MLC2OUT MLC1OUT MODE<2:0> ---- x000 ---- u000 0-00 0000 0-00 0000 POL -- 0--- xxxx 0--- uuuu F12h CLC1SEL0 -- -- D1S<5:0> --xx xxxx --uu uuuu F13h CLC1SEL1 -- -- D2S<5:0> --xx xxxx --uu uuuu F14h CLC1SEL2 -- -- D3S<5:0> --xx xxxx --uu uuuu F15h CLC1SEL3 -- -- D4S<5:0> --xx xxxx --uu uuuu F16h CLC1GLS0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N xxxx xxxx uuuu uuuu F17h CLC1GLS1 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N xxxx xxxx uuuu uuuu F18h CLC1GLS2 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N xxxx xxxx uuuu uuuu F19h CLC1GLS3 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N xxxx xxxx uuuu uuuu F1Ah CLC2CON EN -- OUT INTP INTN 0-00 0000 0-00 0000 F1Bh CLC2POL POL -- -- -- G4POL F1Ch CLC2SEL0 -- -- F1Dh CLC2SEL1 -- F1Eh CLC2SEL2 -- F1Fh CLC2SEL3 G3POL G2POL G1POL MODE<2:0> G3POL G2POL G1POL 0--- uuuu D1S<5:0> --xx xxxx --uu uuuu -- D2S<5:0> --xx xxxx --uu uuuu -- D3S<5:0> --xx xxxx --uu uuuu -- -- D4S<5:0> --xx xxxx --uu uuuu F20h CLC2GLS0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N xxxx xxxx uuuu uuuu F21h CLC2GLS1 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N xxxx xxxx uuuu uuuu F22h CLC2GLS2 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N xxxx xxxx uuuu uuuu F23h CLC2GLS3 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N xxxx xxxx uuuu uuuu F24h CLC3CON EN -- OUT INTP INTN 0-00 0000 0-00 0000 F25h CLC3POL POL -- -- -- G4POL F26h CLC3SEL0 -- -- F27h CLC3SEL1 -- F28h CLC3SEL2 -- F29h CLC3SEL3 F2Ah CLC3GLS0 Legend: Note 1: 2: 3: MODE<2:0> G3POL G2POL G1POL 0--- xxxx 0--- uuuu D1S<5:0> --xx xxxx --uu uuuu -- D2S<5:0> --xx xxxx --uu uuuu -- D3S<5:0> --xx xxxx --uu uuuu -- -- D4S<5:0> --xx xxxx --uu uuuu G1D4T G1D4N xxxx xxxx uuuu uuuu G1D3T G1D3N G1D2T x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. G1D2N G1D1T G1D1N PIC16(L)F1777/8/9 DS40001819B-page 84 0--- xxxx Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 30 (Continued) F2Bh CLC3GLS1 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N xxxx xxxx uuuu uuuu F2Ch CLC3GLS2 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N xxxx xxxx uuuu uuuu F2Dh CLC3GLS3 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N xxxx xxxx uuuu uuuu F2Eh CLC4CON EN OE OUT INTP INTN F2Fh CLC4POL POL -- -- -- G4POL MODE<2:0> G3POL G2POL G1POL 0000 0000 0000 0000 0--- xxxx 0--- uuuu F30h CLC4SEL0 D1S<7:0> xxxx xxxx uuuu uuuu F31h CLC4SEL1 D2S<7:0> xxxx xxxx uuuu uuuu F32h CLC4SEL2 D3S<7:0> xxxx xxxx uuuu uuuu F33h CLC4SEL3 D4S<7:0> xxxx xxxx uuuu uuuu F34h CLC4GLS0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N xxxx xxxx uuuu uuuu F35h CLC4GLS1 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N xxxx xxxx uuuu uuuu F36h CLC4GLS2 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N xxxx xxxx uuuu uuuu F37h CLC4GLS3 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N xxxx xxxx uuuu uuuu -- -- F2Eh -- -- F6Fh Legend: Note 1: 2: 3: Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. PIC16(L)F1777/8/9 DS40001819B-page 85 TABLE 3-18: 2015-2016 Microchip Technology Inc. 2015-2016 Microchip Technology Inc. TABLE 3-18: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- -- ---- -xxx ---- -uuu xxxx xxxx uuuu uuuu Bank 31 F8Ch to -- FE3h Unimplemented FE4h STATUS_SHAD FE5h WREG_SHAD -- -- -- -- -- Working Register Shadow FE6h BSR_SHAD -- FE7h PCLATH_SHAD -- -- -- Bank Select Register Shadow Program Counter Latch High Register Shadow Z DC C ---x xxxx ---u uuuu -xxx xxxx uuuu uuuu FE8h FSR0L_SHAD Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu FE9h FSR0H_SHAD Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu FEAh FSR1L_SHAD Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu FEBh FSR1H_SHAD Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu FECh -- Unimplemented FEDh STKPTR FEEh TOSL FEFh TOSH Legend: Note 1: 2: 3: -- -- -- Current Stack Pointer Top of Stack Low byte -- Top of Stack High byte -- -- ---1 1111 ---1 1111 xxxx xxxx uuuu uuuu -xxx xxxx -uuu uuuu x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. Unimplemented, read as `1'. Unimplemented on PIC16LF1777/8/9. Unimplemented on PIC16(L)F1778. PIC16(L)F1777/8/9 DS40001819B-page 86 PIC16(L)F1777/8/9 3.5 3.5.3 PCL and PCLATH COMPUTED FUNCTION CALLS The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-4 shows the five situations for the loading of the PC. A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function CALL, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). FIGURE 3-4: If using the CALL instruction, the PCH<2:0> and PCL registers are loaded with the operand of the CALL instruction. PCH<6:3> is loaded with PCLATH<6:3>. PC LOADING OF PC IN DIFFERENT SITUATIONS 14 PCH 6 7 14 PCH PCL 0 PCLATH PC 8 ALU Result PCL 0 4 0 11 OPCODE <10:0> PC 14 PCH PCL 0 CALLW 6 PCLATH PC Instruction with PCL as Destination GOTO, CALL 6 PCLATH 0 14 7 0 PCH 8 W PCL 0 BRW PC + W 14 PCH 3.5.4 BRANCHING The branching instructions add an offset to the PC. This allows relocatable code and code that crosses page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed. If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded with the address PC + 1 + W. If using BRA, the entire PC will be loaded with PC + 1 +, the signed value of the operand of the BRA instruction. 15 PC The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address. A computed CALLW is accomplished by loading the W register with the desired address and executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH. PCL 0 BRA 15 PC + OPCODE <8:0> 3.5.1 MODIFYING PCL Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper seven bits to the PCLATH register. When the lower eight bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register. 3.5.2 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to Application Note AN556, "Implementing a Table Read" (DS00556). 2015-2016 Microchip Technology Inc. DS40001819B-page 87 PIC16(L)F1777/8/9 3.6 3.6.1 Stack All devices have a 16-level x 15-bit wide hardware stack (refer to Figures 3-1 and 3-2). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer if the STVREN bit is programmed to `0` (Configuration Words). This means that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is enabled. Note: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, CALLW, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-5: ACCESSING THE STACK The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. The TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is five bits to allow detection of overflow and underflow. Note: Care should be taken when modifying the STKPTR while interrupts are enabled. During normal program operation, CALL, CALLW and Interrupts will increment STKPTR while RETLW, RETURN, and RETFIE will decrement STKPTR. At any time, STKPTR can be inspected to see how much stack is left. The STKPTR always points at the currently used place on the stack. Therefore, a CALL or CALLW will increment the STKPTR and then write the PC, and a return will unload the PC and then decrement the STKPTR. Reference Figure 3-5 through Figure 3-8 for examples of accessing the stack. ACCESSING THE STACK EXAMPLE 1 Rev. 10-000043A 7/30/2013 TOSH:TOSL 0x0F STKPTR = 0x1F Stack Reset Disabled (STVREN = 0) 0x0E 0x0D 0x0C 0x0B Initial Stack Configuration: 0x0A After Reset, the stack is empty. The empty stack is initialized so the Stack Pointer is pointing at 0x1F. If the Stack Overflow/Underflow Reset is enabled, the TOSH/TOSL register will return `0'. If the Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL register will return the contents of stack address 0x0F. 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 TOSH:TOSL DS40001819B-page 88 0x1F 0x0000 STKPTR = 0x1F Stack Reset Enabled (STVREN = 1) 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 Rev. 10-000043B 7/30/2013 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F). 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL FIGURE 3-7: 0x00 Return Address STKPTR = 0x00 ACCESSING THE STACK EXAMPLE 3 Rev. 10-000043C 7/30/2013 0x0F 0x0E 0x0D 0x0C After seven CALLs or six CALLs and an interrupt, the stack looks like the figure on the left. A series of RETURN instructions will repeatedly place the return addresses into the Program Counter and pop the stack. 0x0B 0x0A 0x09 0x08 0x07 TOSH:TOSL 2015-2016 Microchip Technology Inc. 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address STKPTR = 0x06 DS40001819B-page 89 PIC16(L)F1777/8/9 FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4 Rev. 10-000043D 7/30/2013 TOSH:TOSL 3.6.2 0x0F Return Address 0x0E Return Address 0x0D Return Address 0x0C Return Address 0x0B Return Address 0x0A Return Address 0x09 Return Address 0x08 Return Address 0x07 Return Address 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address When the stack is full, the next CALL or an interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. If the Stack Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will not be overwritten. STKPTR = 0x10 OVERFLOW/UNDERFLOW RESET If the STVREN bit in Configuration Words is programmed to `1', the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register. 3.7 Indirect Addressing The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return `0' and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: * Traditional Data Memory * Linear Data Memory * Program Flash Memory DS40001819B-page 90 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 3-9: INDIRECT ADDRESSING Rev. 10-000044A 7/30/2013 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x1000 0x0FFF Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved FSR Address Range 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. 2015-2016 Microchip Technology Inc. DS40001819B-page 91 PIC16(L)F1777/8/9 3.7.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 3-10: TRADITIONAL DATA MEMORY MAP Rev. 10-000056A 7/31/2013 Direct Addressing 4 BSR 0 Indirect Addressing From Opcode 6 0 Bank Select 7 FSRxH 0 0 0 0 Location Select 0x00 00000 Bank Select 00001 00010 11111 Bank 0 Bank 1 Bank 2 Bank 31 0 7 FSRxL 0 Location Select 0x7F DS40001819B-page 92 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 3.7.2 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank. The 16 bytes of common memory are not included in the linear data memory region. FIGURE 3-11: LINEAR DATA MEMORY MAP 3.7.3 PROGRAM FLASH MEMORY To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the lower eight bits of each memory location is accessible via INDF. Writing to the program Flash memory cannot be accomplished via the FSR/INDF interface. All instructions that access program Flash memory via the FSR/INDF interface will require one additional instruction cycle to complete. FIGURE 3-12: PROGRAM FLASH MEMORY MAP Rev. 10-000057A 7/31/2013 7 FSRnH 0 0 1 0 7 FSRnL Rev. 10-000058A 7/31/2013 7 1 0 FSRnH 0 Location Select Location Select 0x2000 7 FSRnL 0 0x8000 0x0A0 Bank 1 0x0EF Program Flash Memory (low 8 bits) 0x120 Bank 2 0x16F 0x29AF 2015-2016 Microchip Technology Inc. 0x0000 0x020 Bank 0 0x06F 0xF20 Bank 30 0xF6F 0xFFFF 0x7FFF DS40001819B-page 93 PIC16(L)F1777/8/9 4.0 DEVICE CONFIGURATION Device configuration consists of Configuration Words, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a `1'. DS40001819B-page 94 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 4.2 Register Definitions: Configuration Words REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 R/P-1 R/P-1 R/P-1 FCMEN IESO CLKOUTEN R/P-1 R/P-1 U-1 BOREN<1:0> -- bit 13 R/P-1 (1) CP R/P-1 R/P-1 MCLRE PWRTE bit 8 R/P-1 R/P-1 WDTE<1:0> R/P-1 R/P-1 R/P-1 FOSC<2:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `1' `0' = Bit is cleared `1' = Bit is set -n = Value when blank or after Bulk Erase bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = ON Fail-Safe Clock Monitor and internal/external switchover are both enabled 0 = OFF Fail-Safe Clock Monitor is disabled bit 12 IESO: Internal External Switchover bit 1 = ON Internal/External Switchover mode is enabled 0 = OFF Internal/External Switchover mode is disabled bit 11 CLKOUTEN: Clock Out Enable bit If FOSC Configuration bits are set to LP, XT, HS modes: This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin. All other FOSC modes: 1 = ON CLKOUT function is disabled. I/O function on the CLKOUT pin. 0 = OFF CLKOUT function is enabled on the CLKOUT pin. bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits 11 = ON BOR enabled 10 = NSLEEP BOR enabled during operation and disabled in Sleep 01 = SBODEN BOR controlled by SBOREN bit of the BORCON register 00 = OFF BOR disabled bit 8 Unimplemented: Read as `1' bit 7 CP: Code Protection bit(1) 1 = OFF Program memory code protection is disabled 0 = ON Program memory code protection is enabled bit 6 MCLRE: MCLR/VPP Pin Function Select bit If LVP bit = 1: This bit is ignored. If LVP bit = 0: 1 = ON MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 = OFF MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUA3 bit. bit 5 PWRTE: Power-up Timer Enable bit 1 = OFF PWRT disabled 0 = ON PWRT enabled bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit 11 = ON WDT enabled 10 = NSLEEP WDT enabled while running and disabled in Sleep 01 = SWDTEN WDT controlled by the SWDTEN bit in the WDTCON register 00 = OFF WDT disabled 2015-2016 Microchip Technology Inc. DS40001819B-page 95 PIC16(L)F1777/8/9 REGISTER 4-1: bit 2-0 Note 1: CONFIG1: CONFIGURATION WORD 1 (CONTINUED) FOSC<2:0>: Oscillator Selection bits 111 = ECH External Clock, High-Power mode: CLKIN supplied to OSC1/CLKIN pin 110 = ECM External Clock, Medium Power mode: CLKIN supplied to OSC1/CLKIN pin 101 = ECL External Clock, Low-Power mode: CLKIN supplied to OSC1/CLKIN pin 100 = INTOSC Internal HFINTOSC. I/O function on CLKIN pin 011 = EXTRC External RC circuit connected to CLKIN pin 010 = HS High-speed crystal/resonator connected between OSC1 and OSC2 pins 001 = XT Crystal/resonator connected between OSC1 and OSC2 pins 000 = LP Low-power crystal connected between OSC1 and OSC2 pins The entire Flash program memory will be erased when the code protection is turned off during an erase. When a Bulk Erase Program Memory command is executed, the entire program Flash memory and configuration memory will be erased. DS40001819B-page 96 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2 R/P-1 LVP (1) R/P-1 DEBUG R/P-1 (2) LPBOR R/P-1 (3) BORV R/P-1 R/P-1 STVREN PLLEN bit 13 bit 8 R/P-1 U-1 U-1 U-1 U-1 R/P-1 ZCD -- -- -- -- PPS1WAY R/P-1 R/P-1 WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `1' `0' = Bit is cleared `1' = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = ON Low-voltage programming enabled 0 = OFF High-voltage on MCLR must be used for programming bit 12 DEBUG: In-Circuit Debugger Mode bit(2) 1 = OFF In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins 0 = ON In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger bit 11 LPBOR: Low-Power BOR Enable bit 1 = OFF Low-Power Brown-out Reset is disabled 0 = ON Low-Power Brown-out Reset is enabled bit 10 BORV: Brown-out Reset Voltage Selection bit(3) 1 = LO Brown-out Reset voltage (VBOR), low trip point selected 0 = HI Brown-out Reset voltage (VBOR), high trip point selected bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = ON Stack Overflow or Underflow will cause a Reset 0 = OFF Stack Overflow or Underflow will not cause a Reset bit 8 PLLEN: PLL Enable bit 1 = ON 4xPLL enabled 0 = OFF 4xPLL disabled bit 7 ZCD: ZCD Enable bit 1 = OFF ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON 0 = ON ZCD always enabled bit 6-3 Unimplemented: Read as `1' bit 2 PPS1WAY: PPSLOCK Bit One-Way Set Enable bit The PPSLOCK bit can only be set once after an unlocking sequence is executed; once PPSLOCK is set, all future changes to PPS registers are prevented 0 = OFF The PPSLOCK bit can be set and cleared as needed (provided an unlocking sequence is executed) 1 = ON bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits 4 kW Flash memory (PIC16(L)F1764/8) 11 = OFF Write protection off 10 = BOOT 0000h to 01FFh write protected, 0200h to 0FFFh may be modified by PMCON control 01 = HALF 0000h to 07FFh write protected, 0800h to 0FFFh may be modified by PMCON control 00 = ALL 0000h to 0FFFh write protected, no addresses may be modified by PMCON control 8 kW Flash memory (PIC16(L)F1765/9) 11 = OFF Write protection off 10 = BOOT 0000h to 01FFh write protected, 0200h to 1FFFh may be modified by PMCON control 01 = HALF 0000h to 0FFFh write protected, 1000h to 1FFFh may be modified by PMCON control 00 = ALL 0000h to 1FFFh write protected, no addresses may be modified by PMCON control Note 1: 2: 3: The LVP bit cannot be programmed to `0' when Programming mode is entered via LVP. The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a `1'. See VBOR parameter for specific trip point voltages. 2015-2016 Microchip Technology Inc. DS40001819B-page 97 PIC16(L)F1777/8/9 4.3 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection is controlled independently. Internal access to the program memory is unaffected by any code protection setting. 4.3.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words. When CP = 0, external reads and writes of program memory are inhibited and a read will return all `0's. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See Section 4.4 "Write Protection" for more information. 4.4 Write Protection Write protection allows the device to be protected from unintended self-writes. Applications, such as boot loader software, can be protected while allowing other regions of the program memory to be modified. The WRT<1:0> bits in Configuration Words define the size of the program memory block that is protected. 4.5 User ID Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See Section 10.4 "User ID, Device ID and Configuration Word Access" for more information on accessing these memory locations. For more information on checksum calculation, see the "PIC16(L)F170X Memory Programming Specification" (DS41683). DS40001819B-page 98 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 4.6 Device ID and Revision ID The 14-bit device ID word is located at 8006h and the 14-bit revision ID is located at 8005h. These locations are read-only and cannot be erased or modified. See Section 10.4 "User ID, Device ID and Configuration Word Access" for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. 4.7 Register Definitions: Device and Revision REGISTER 4-3: DEVID: DEVICE ID REGISTER R R R R R R DEV<13:8> bit 13 R R bit 8 R R R R R R DEV<7:0> bit 7 bit 0 Legend: R = Readable bit `1' = Bit is set bit 13-0 `0' = Bit is cleared DEV<13:0>: Device ID bits Device DEVID<13:0> Values PIC16F1777 11 0000 1000 1110 (308E) PIC16F1778 11 0000 1000 1111 (308F) PIC16F1779 11 0000 1001 0000 (3090) PIC16LF1777 11 0000 1001 0001 (3091) PIC16LF1778 11 0000 1001 0010 (3092) PIC16LF1779 11 0000 1001 0011 (3093) 2015-2016 Microchip Technology Inc. DS40001819B-page 99 PIC16(L)F1777/8/9 REGISTER 4-4: REVID: REVISION ID REGISTER R R R R R R REV<13:8> bit 13 R R bit 8 R R R R R R REV<7:0> bit 7 bit 0 Legend: R = Readable bit `1' = Bit is set bit 13-0 `0' = Bit is cleared REV<13:0>: Revision ID bits DS40001819B-page 100 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 5.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 5.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be supplied from one of two internal oscillators and PLL circuits, with a choice of speeds selectable via software. Additional clock features include: * Selectable system clock source between external or internal sources via software. * Two-Speed Start-up mode, which minimizes latency between external oscillator start-up and code execution. * Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, ECH, ECM, ECL or EXTRC modes) and switch automatically to the internal oscillator. * Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources. 2015-2016 Microchip Technology Inc. The oscillator module can be configured in one of the following clock modes. 1. 2. 3. 4. 5. 6. 7. 8. ECL - External Clock Low-Power mode (0 MHz to 0.5 MHz) ECM - External Clock Medium Power mode (0.5 MHz to 4 MHz) ECH - External Clock High-Power mode (4 MHz to 32 MHz) LP - 32 kHz Low-Power Crystal mode. XT - Medium Gain Crystal or Ceramic Resonator Oscillator mode (up to 4 MHz) HS - High Gain Crystal or Ceramic Resonator mode (4 MHz to 20 MHz) EXTRC - External Resistor-Capacitor INTOSC - Internal oscillator (31 kHz to 32 MHz) Clock Source modes are selected by the FOSC<2:0> bits in the Configuration Words. The FOSC bits determine the type of oscillator that will be used when the device is first powered. The ECH, ECM, and ECL clock modes rely on an external logic level signal as the device clock source. The LP, XT, and HS clock modes require an external crystal or resonator to be connected to the device. Each mode is optimized for a different frequency range. The EXTRC clock mode requires an external resistor and capacitor to set the oscillator frequency. The INTOSC internal oscillator block produces low, medium, and high-frequency clock sources, designated LFINTOSC, MFINTOSC and HFINTOSC. (see Internal Oscillator Block, Figure 5-1). A wide selection of device clock frequencies may be derived from these three clock sources. DS40001819B-page 101 PIC16(L)F1777/8/9 SIMPLIFIED PIC(R) MCU CLOCK SOURCE BLOCK DIAGRAM FIGURE 5-1: Secondary Oscillator Timer1 Timer1 Clock Source Option for other modules SOSCO T1OSCEN Enable Oscillator SOSCI T1OSC 01 External Oscillator LP, XT, HS, RC, EC OSC2 0 Sleep 00 PRIMUX OSC1 4 x PLL 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.25 kHz PLLMUX 500 kHz Source 16 MHz (HFINTOSC) 500 kHz (MFINTOSC) 31 kHz Source INTOSC SCS<1:0> 31 kHz 0000 31 kHz (LFINTOSC) WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules Inputs FOSC<2:0> PLLEN or SPLLEN 0 =100 1 =00 100 00 X DS40001819B-page 102 0 1X 1111 MUX HFPLL Postscaler Internal Oscillator Block FOSC To CPU and Peripherals 1 IRCF<3:0> SCS Sleep 0 1 Outputs IRCF PRIMUX PLLMUX x 1 0 =1110 1 1 1110 1 0 x 0 0 1 x 0 1 X X X X 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 5.2 Clock Source Types Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (ECH, ECM, ECL mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (EXTRC) mode circuits. Internal clock sources are contained within the oscillator module. The internal oscillator block has two internal oscillators and a dedicated Phase Lock Loop (HFPLL) that are used to generate three internal system clock sources: the 16 MHz High-Frequency Internal Oscillator (HFINTOSC), 500 kHz (MFINTOSC) and the 31 kHz Low-Frequency Internal Oscillator (LFINTOSC). The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bits in the OSCCON register. See Section 5.3 "Clock Switching" for additional information. 5.2.1 EXTERNAL CLOCK SOURCES An external clock source can be used as the device system clock by performing one of the following actions: * Program the FOSC<2:0> bits in the Configuration Words to select an external clock source that will be used as the default system clock upon a device Reset. * Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to: - Secondary oscillator during run-time, or - An external clock source determined by the value of the FOSC bits. See Section 5.3 "Clock Switching" for more information. 5.2.1.1 EC Mode The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure 5-2 shows the pin connections for EC mode. EC mode has three power modes to select from through Configuration Words: The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC(R) MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed. FIGURE 5-2: EXTERNAL CLOCK (EC) MODE OPERATION Rev. 10-000045A 7/30/2013 Clock from Ext. system OSC1/CLKIN PIC(R) MCU (1) FOSC/4 or I/O Note 1: 5.2.1.2 OSC2/CLKOUT Output depends upon the CLKOUTEN bit of the Configuration Words. LP, XT, HS Modes The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 5-3). The three modes select a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals). XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification. HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting. Figure 5-3 and Figure 5-4 show typical circuits for quartz crystal and ceramic resonators, respectively. * ECH - High power, 4-32 MHz * ECM - Medium power, 0.5-4 MHz * ECL - Low power, 0-0.5 MHz 2015-2016 Microchip Technology Inc. DS40001819B-page 103 PIC16(L)F1777/8/9 FIGURE 5-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) FIGURE 5-4: CERAMIC RESONATOR OPERATION (XT OR HS MODE) Rev. 10-000059A 7/30/2013 Rev. 10-000060A 7/30/2013 PIC(R) MCU PIC(R) MCU Ceramic Resonator OSC1/CLKIN OSC1/CLKIN C1 C2 Note 1: 2: C1 To Internal Logic Quartz Crystal RF(2) RS(1) OSC2/CLKOUT RP(3) Sleep A series resistor (Rs) may be required for quartz crystals with low drive level. C2 Note 1: The value of RF varies with the Oscillator mode selected (typically between 2 M and 10 M). Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Application Notes: * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPIC(R) and PIC(R) Devices" (DS00826) * AN849, "Basic PIC(R) Oscillator Design" (DS00849) * AN943, "Practical PIC(R) Oscillator Analysis and Design" (DS00943) * AN949, "Making Your Oscillator Work" (DS00949) DS40001819B-page 104 To Internal Logic 5.2.1.3 RS(1) RF(2) Sleep OSC2/CLKOUT A series resistor (Rs) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M and 10 M). 3. An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation. Oscillator Start-up Timer (OST) If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended, unless either FSCM or Two-Speed Start-Up are enabled. In this case, code will continue to execute at the selected INTOSC frequency while the OST is counting. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 5.4 "Two-Speed Clock Start-up Mode"). 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 5.2.1.4 4x PLL The oscillator module contains a 4x PLL that can be used with both external and internal clock sources to provide a system clock source. The input frequency for the 4x PLL must fall within specifications. See the PLL Clock Timing Specifications in Table 36-9. The 4x PLL may be enabled for use by one of two methods: 1. 2. Program the PLLEN bit in Configuration Words to a `1'. Write the SPLLEN bit in the OSCCON register to a `1'. If the PLLEN bit in Configuration Words is programmed to a `1', then the value of SPLLEN is ignored. 5.2.1.5 Secondary Oscillator The secondary oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the SOSCO and SOSCI device pins. The secondary oscillator can be used as an alternate system clock source and can be selected during run-time using clock switching. Refer to Section 5.3 "Clock Switching" for more information. FIGURE 5-5: Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Application Notes: * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPIC(R) and PIC(R) Devices" (DS00826) * AN849, "Basic PIC(R) Oscillator Design" (DS00849) * AN943, "Practical PIC(R) Oscillator Analysis and Design" (DS00943) * AN949, "Making Your Oscillator Work" (DS00949) * TB097, "Interfacing a Micro Crystal MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS" (DS91097) * AN1288, "Design Practices for Low-Power External Oscillators" (DS01288) QUARTZ CRYSTAL OPERATION (SECONDARY OSCILLATOR) Rev. 10-000061A 7/30/2013 PIC(R) MCU SOSCI C1 To Internal Logic 32.768 kHz Quartz Crystal C2 SOSCO 2015-2016 Microchip Technology Inc. DS40001819B-page 105 PIC16(L)F1777/8/9 5.2.1.6 External RC Mode 5.2.2 The external Resistor-Capacitor (EXTRC) mode supports the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. The RC circuit connects to OSC1. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN bit in Configuration Words. Figure 5-6 shows the external RC mode connections. FIGURE 5-6: EXTERNAL RC MODES Rev. 10-000062A 7/31/2013 (R) PIC MCU REXT CEXT The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: * Program the FOSC<2:0> bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. * Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 5.3 "Clock Switching" for more information. In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN bit in Configuration Words. VDD OSC1/CLKIN Internal Clock The internal oscillator block has two independent oscillators and a dedicated Phase Lock Loop, HFPLL, that can produce one of three internal system clock sources. 1. VSS FOSC/4 or I/O(1) OSC2/CLKOUT Recommended values:10 k REXT 100 k, <3V 3 k REXT 100 k, 3-5V CEXT > 20 pF, 2-5V Note 1: INTERNAL CLOCK SOURCES Output depends upon the CLKOUTEN bit of the Configuration Words. 2. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are: * threshold voltage variation * component tolerances * packaging variations in capacitance 3. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 16 MHz. The HFINTOSC source is generated from the 500 kHz MFINTOSC source and the dedicated Phase Lock Loop, HFPLL. The frequency of the HFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 5-3). The MFINTOSC (Medium-Frequency Internal Oscillator) is factory calibrated and operates at 500 kHz. The frequency of the MFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 5-3). The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at 31 kHz. The user also needs to take into account variation due to tolerance of external RC components used. DS40001819B-page 106 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 5.2.2.1 HFINTOSC The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 5-3). The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). One of multiple frequencies derived from the HFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 5.2.2.7 "Internal Oscillator Clock Switch Timing" for more information. The HFINTOSC is enabled by: * Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and * FOSC<2:0> = 100, or * Set the System Clock Source (SCS) bits of the OSCCON register to `1x'. A fast start-up oscillator allows internal circuits to power up and stabilize before switching to HFINTOSC. The High-Frequency Internal Oscillator Ready bit (HFIOFR) of the OSCSTAT register indicates when the HFINTOSC is running. The High-Frequency Internal Oscillator Status Locked bit (HFIOFL) of the OSCSTAT register indicates when the HFINTOSC is running within 2% of its final value. The High-Frequency Internal Oscillator Stable bit (HFIOFS) of the OSCSTAT register indicates when the HFINTOSC is running within 0.5% of its final value. 5.2.2.2 MFINTOSC The Medium-Frequency Internal Oscillator (MFINTOSC) is a factory calibrated 500 kHz internal clock source. The frequency of the MFINTOSC can be altered via software using the OSCTUNE register (Register 5-3). The output of the MFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). One of nine frequencies derived from the MFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 5.2.2.7 "Internal Oscillator Clock Switch Timing" for more information. The MFINTOSC is enabled by: * Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and * FOSC<2:0> = 100, or * Set the System Clock Source (SCS) bits of the OSCCON register to `1x'. The Medium-Frequency Internal Oscillator Ready bit (MFIOFR) of the OSCSTAT register indicates when the MFINTOSC is running. 2015-2016 Microchip Technology Inc. 5.2.2.3 Internal Oscillator Frequency Adjustment The 500 kHz internal oscillator is factory calibrated. This internal oscillator can be adjusted in software by writing to the OSCTUNE register (Register 5-3). Since the HFINTOSC and MFINTOSC clock sources are derived from the 500 kHz internal oscillator, a change in the OSCTUNE register value will apply to both. The default value of the OSCTUNE register is `0'. The value is a 6-bit two's complement number. A value of 1Fh will provide an adjustment to the maximum frequency. A value of 20h will provide an adjustment to the minimum frequency. When the OSCTUNE register is modified, the oscillator frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. 5.2.2.4 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a multiplexer (see Figure 5-1). Select 31 kHz, via software, using the IRCF<3:0> bits of the OSCCON register. See Section 5.2.2.7 "Internal Oscillator Clock Switch Timing" for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled by selecting 31 kHz (IRCF<3:0> bits of the OSCCON register = 000) as the system clock source (SCS bits of the OSCCON register = 1x), or when any of the following are enabled: * Configure the IRCF<3:0> bits of the OSCCON register for the desired LF frequency, and * FOSC<2:0> = 100, or * Set the System Clock Source (SCS) bits of the OSCCON register to `1x'. Peripherals that use the LFINTOSC are: * Power-up Timer (PWRT) * Watchdog Timer (WDT) * Fail-Safe Clock Monitor (FSCM) The Low-Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running. DS40001819B-page 107 PIC16(L)F1777/8/9 5.2.2.5 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register. The postscaled output of the 16 MHz HFINTOSC, 500 kHz MFINTOSC, and 31 kHz LFINTOSC connect to a multiplexer (see Figure 5-1). The Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register select the frequency output of the internal oscillators. One of the following frequencies can be selected via software: - 32 MHz (requires 4x PLL) 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz (default after Reset) 250 kHz 125 kHz 62.5 kHz 31.25 kHz 31 kHz (LFINTOSC) Note: Following any Reset, the IRCF<3:0> bits of the OSCCON register are set to `0111' and the frequency selection is set to 500 kHz. The user can modify the IRCF bits to select a different frequency. 5.2.2.6 32 MHz Internal Oscillator Frequency Selection The Internal Oscillator Block can be used with the 4x PLL associated with the External Oscillator Block to produce a 32 MHz internal system clock source. The following settings are required to use the 32 MHz internal clock source: * The FOSC bits in Configuration Words must be set to use the INTOSC source as the device system clock (FOSC<2:0> = 100). * The SCS bits in the OSCCON register must be cleared to use the clock determined by FOSC<2:0> in Configuration Words (SCS<1:0> = 00). * The IRCF bits in the OSCCON register must be set to the 8 MHz HFINTOSC set to use (IRCF<3:0> = 1110). * The SPLLEN bit in the OSCCON register must be set to enable the 4x PLL, or the PLLEN bit of the Configuration Words must be programmed to a `1'. Note: When using the PLLEN bit of the Configuration Words, the 4x PLL cannot be disabled by software and the SPLLEN option will not be available. The 4x PLL is not available for use with the internal oscillator when the SCS bits of the OSCCON register are set to `1x'. The SCS bits must be set to `00' to use the 4x PLL with the internal oscillator. The IRCF<3:0> bits of the OSCCON register allow duplicate selections for some frequencies. These duplicate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes that use the same oscillator source. DS40001819B-page 108 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 5.2.2.7 Internal Oscillator Clock Switch Timing When switching between the HFINTOSC, MFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure 5-7). If this is the case, there is a delay after the IRCF<3:0> bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC, MFINTOSC and LFINTOSC oscillators. The sequence of a frequency selection is as follows: 1. 2. 3. 4. 5. 6. 7. IRCF<3:0> bits of the OSCCON register are modified. If the new clock is shut down, a clock start-up delay is started. Clock switch circuitry waits for a falling edge of the current clock. The current clock is held low and the clock switch circuitry waits for a rising edge in the new clock. The new clock is now active. The OSCSTAT register is updated as required. Clock switch is complete. See Figure 5-7 for more details. If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 5-1. Start-up delay specifications are located in the oscillator tables of Section 36.0 "Electrical Specifications". 2015-2016 Microchip Technology Inc. DS40001819B-page 109 PIC16(L)F1777/8/9 FIGURE 5-7: HFINTOSC/ MFINTOSC INTERNAL OSCILLATOR SWITCH TIMING LFINTOSC (FSCM and WDT disabled) HFINTOSC/ MFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC 0 IRCF <3:0> 0 System Clock HFINTOSC/ MFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC/ MFINTOSC 2-cycle Sync Running LFINTOSC 0 IRCF <3:0> 0 System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC/ MFINTOSC IRCF <3:0> =0 0 System Clock DS40001819B-page 110 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 5.3 Clock Switching 5.3.3 SECONDARY OSCILLATOR The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: The secondary oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the SOSCO and SOSCI device pins. * Default system oscillator determined by FOSC bits in Configuration Words * Timer1 32 kHz crystal oscillator * Internal Oscillator Block (INTOSC) The secondary oscillator is enabled using the OSCEN control bit in the T1CON register. See Section 22.0 "Timer1/3/5 Module with Gate Control" for more information about the Timer1 peripheral. 5.3.1 SYSTEM CLOCK SELECT (SCS) BITS The System Clock Select (SCS) bits of the OSCCON register select the system clock source that is used for the CPU and peripherals. * When the SCS bits of the OSCCON register = 00, the system clock source is determined by the value of the FOSC<2:0> bits in the Configuration Words. * When the SCS bits of the OSCCON register = 01, the system clock source is the secondary oscillator. * When the SCS bits of the OSCCON register = 1x, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the SCS bits of the OSCCON register are always cleared. Note: Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 5-1. 5.3.2 5.3.4 SECONDARY OSCILLATOR READY (SOSCR) BIT The user must ensure that the secondary oscillator is ready to be used before it is selected as a system clock source. The Secondary Oscillator Ready (SOSCR) bit of the OSCSTAT register indicates whether the secondary oscillator is ready to be used. After the SOSCR bit is set, the SCS bits can be configured to select the secondary oscillator. 5.3.5 CLOCK SWITCH BEFORE SLEEP When a clock switch from an old clock to a new clock is requested just prior to entering Sleep mode, it is necessary to confirm that the switch is complete before the sleep instruction is executed. Failure to do so may result in an incomplete switch and consequential loss of the system clock altogether. Clock switching is confirmed by monitoring the clock status bits in the OSCSTAT register. Switch confirmation can be accomplished by sensing that the ready bit for the new clock is set or the ready bit for the old clock is cleared. For example, when switching between the internal oscillator with the PLL and the internal oscillator without the PLL, monitor the PLLR bit. When PLLR is set, the switch to 32 MHz operation is complete. Conversely, when PLLR is cleared the switch from 32 MHz operation to the selected internal clock is complete. OSCILLATOR START-UP TIMER STATUS (OSTS) BIT The Oscillator Start-up Timer Status (OSTS) bit of the OSCSTAT register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Words, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. The OST does not reflect the status of the secondary oscillator. 2015-2016 Microchip Technology Inc. DS40001819B-page 111 PIC16(L)F1777/8/9 5.4 5.4.1 Two-Speed Clock Start-up Mode Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC internal oscillator block as the clock source and go back to Sleep without waiting for the external oscillator to become stable. Two-Speed Start-up provides benefits when the oscillator module is configured for LP, XT or HS modes. The Oscillator Start-up Timer (OST) is enabled for these modes and must count 1024 oscillations before the oscillator can be used as the system clock source. TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: * IESO (of the Configuration Words) = 1; Internal/External Switchover bit (Two-Speed Start-up mode enabled). * SCS (of the OSCCON register) = 00. * FOSC<2:0> bits in the Configuration Words configured for LP, XT or HS mode. Two-Speed Start-up mode is entered after: * Power-on Reset (POR) and, if enabled, after Power-up Timer (PWRT) has expired, or * Wake-up from Sleep. If the oscillator module is configured for any mode other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep. If the OST count reaches 1024 before the device enters Sleep mode, the OSTS bit of the OSCSTAT register is set and program execution switches to the external oscillator. However, the system may never operate from the external oscillator if the time spent awake is very short. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear. TABLE 5-1: OSCILLATOR SWITCHING DELAYS Switch From Switch To Frequency Oscillator Delay LFINTOSC(1) Sleep MFINTOSC(1) HFINTOSC(1) 31 kHz 31.25 kHz-500 kHz 31.25 kHz-16 MHz Oscillator Warm-up Delay (TWARM)(2) Sleep/POR EC, RC(1) DC - 32 MHz 2 cycles LFINTOSC EC, RC(1) DC - 32 MHz 1 cycle of each Sleep/POR Secondary Oscillator 32 kHz-20 MHz LP, XT, HS(1) 1024 Clock Cycles (OST) Any clock source MFINTOSC(1) HFINTOSC(1) 31.25 kHz-500 kHz 31.25 kHz-16 MHz 2 s (approx.) Any clock source LFINTOSC(1) 31 kHz Any clock source Secondary Oscillator 32 kHz 1024 Clock Cycles (OST) PLL inactive PLL active 2 ms (approx.) Note 1: 2: 16-32 MHz 1 cycle of each PLL inactive. See Section 36.0 "Electrical Specifications". DS40001819B-page 112 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 5.4.2 1. 2. 3. 4. 5. 6. 7. TWO-SPEED START-UP SEQUENCE 5.4.3 Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source. FIGURE 5-8: CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Words, or the internal oscillator. TWO-SPEED START-UP INTOSC TOST OSC1 0 1 1022 1023 OSC2 Program Counter PC - N PC PC + 1 System Clock 2015-2016 Microchip Technology Inc. DS40001819B-page 113 PIC16(L)F1777/8/9 5.5 5.5.3 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Words. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, Secondary Oscillator and RC). FIGURE 5-9: FSCM BLOCK DIAGRAM Clock Monitor Latch External Clock LFINTOSC Oscillator / 64 31 kHz (~32 s) 488 Hz (~2 ms) S Q R Q Sample Clock 5.5.1 FAIL-SAFE DETECTION The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 5-9. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low. 5.5.2 The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register. When the SCS bits are changed, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared after successfully switching to the external clock source. The OSFIF bit should be cleared prior to switching to the external clock source. If the Fail-Safe condition still exists, the OSFIF flag will again become set by hardware. 5.5.4 Clock Failure Detected FAIL-SAFE CONDITION CLEARING RESET OR WAKE-UP FROM SLEEP The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. When the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing code while the OST is operating. Note: Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the Status bits in the OSCSTAT register to verify the oscillator start-up and that the system clock switchover has successfully completed. FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. DS40001819B-page 114 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 5-10: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 2015-2016 Microchip Technology Inc. DS40001819B-page 115 PIC16(L)F1777/8/9 5.6 Register Definitions: Oscillator Control REGISTER 5-1: R/W-0/0 OSCCON: OSCILLATOR CONTROL REGISTER R/W-0/0 SPLLEN R/W-1/1 R/W-1/1 R/W-1/1 IRCF<3:0> U-0 R/W-0/0 -- R/W-0/0 SCS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 SPLLEN: Software PLL Enable bit If PLLEN in Configuration Words = 1: SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements) If PLLEN in Configuration Words = 0: 1 = 4x PLL Is enabled 0 = 4x PLL is disabled bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits 1111 = 16 MHz HF 1110 = 8 MHz or 32 MHz HF(2) 1101 = 4 MHz HF 1100 = 2 MHz HF 1011 = 1 MHz HF 1010 = 500 kHz HF(1) 1001 = 250 kHz HF(1) 1000 = 125 kHz HF(1) 0111 = 500 kHz MF (default upon Reset) 0110 = 250 kHz MF 0101 = 125 kHz MF 0100 = 62.5 kHz MF 0011 = 31.25 kHz HF(1) 0010 = 31.25 kHz MF 000x = 31 kHz LF bit 2 Unimplemented: Read as `0' bit 1-0 SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Secondary oscillator 00 = Clock determined by FOSC<2:0> in Configuration Words Note 1: 2: Duplicate frequency derived from HFINTOSC. 32 MHz when SPLLEN bit is set. Refer to Section 5.2.2.6 "32 MHz Internal Oscillator Frequency Selection". DS40001819B-page 116 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q SOSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Conditional bit 7 SOSCR: Secondary Oscillator Ready bit If T1OSCEN = 1: 1 = Secondary oscillator is ready 0 = Secondary oscillator is not ready If T1OSCEN = 0: 1 = Secondary clock source is always ready bit 6 PLLR 4x PLL Ready bit 1 = 4x PLL is ready 0 = 4x PLL is not ready bit 5 OSTS: Oscillator Start-up Timer Status bit 1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Words 0 = Running from an internal oscillator (FOSC<2:0> = 100) bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit 1 = HFINTOSC is ready 0 = HFINTOSC is not ready bit 3 HFIOFL: High-Frequency Internal Oscillator Locked bit 1 = HFINTOSC is at least 2% accurate 0 = HFINTOSC is not 2% accurate bit 2 MFIOFR: Medium-Frequency Internal Oscillator Ready bit 1 = MFINTOSC is ready 0 = MFINTOSC is not ready bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit 1 = LFINTOSC is ready 0 = LFINTOSC is not ready bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit 1 = HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate 2015-2016 Microchip Technology Inc. DS40001819B-page 117 PIC16(L)F1777/8/9 REGISTER 5-3: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 TUN<5:0>: Frequency Tuning bits 100000 = Minimum frequency * * * 111111 = 000000 = Oscillator module is running at the factory-calibrated frequency 000001 = * * * 011110 = 011111 = Maximum frequency TABLE 5-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 OSCCON SPLLEN OSCSTAT SOSCR PLLR OSCTUNE -- -- PIR2 OSFIF C2IF C1IF COG1IF PIE2 OSFIE C2IE C1IE COG1IE Legend: CONFIG1 Legend: OSTS Bit 1 -- HFIOFR HFIOFL Bit 0 SCS<1:0> MFIOFR 116 LFIOFR HFIOFS 117 C4IF C3IF CCP2IF 140 BCL1IE C4IE C3IE CCP2IE 134 OSCEN SYNC -- ON 283 TUN<5:0> CKPS<1:0> Register on Page BCL1IF 118 -- = unimplemented location, read as `0'. Shaded cells are not used by clock sources. TABLE 5-3: Name IRCF<3:0> CS<1:0> T1CON Bit 2 SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 13:8 -- -- FCMEN IESO CLKOUTEN 7:0 CP MCLRE PWRTE WDTE<1:0> Bit 10/2 Bit 9/1 BOREN<1:0> FOSC<2:0> Bit 8/0 -- Register on Page 95 -- = unimplemented location, read as `0'. Shaded cells are not used by clock sources. DS40001819B-page 118 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 6.0 A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 6-1. RESETS There are multiple ways to reset this device: * * * * * * * * * Power-on Reset (POR) Brown-out Reset (BOR) Low-Power Brown-out Reset (LPBOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BOR or POR event. FIGURE 6-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Rev. 10-000006A 8/14/2013 ICSPTM Programming Mode Exit RESET Instruction Stack Underflow Stack Overlfow MCLRE VPP/MCLR Sleep WDT Time-out Device Reset Power-on Reset VDD BOR Active(1) Brown-out Reset LPBOR Reset Note 1: R LFINTOSC Power-up Timer PWRTE See Table 6.2.1 for BOR active conditions. 2015-2016 Microchip Technology Inc. DS40001819B-page 119 PIC16(L)F1777/8/9 6.1 Refer to Table 6.2.1 for more information. Power-On Reset (POR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. 6.1.1 POWER-UP TIMER (PWRT) The Power-up Timer provides a nominal 64 ms time-out on POR or Brown-out Reset. The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the VDD to rise to an acceptable level. The Power-up Timer is enabled by clearing the PWRTE bit in Configuration Words. The Power-up Timer starts after the release of the POR and BOR. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting" (DS00607). 6.2 Brown-Out Reset (BOR) The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented. The Brown-out Reset module has four operating modes controlled by the BOREN<1:0> bits in Configuration Words. The four operating modes are: * * * * BOR is always on BOR is off when in Sleep BOR is controlled by software BOR is always off TABLE 6-1: The Brown-out Reset voltage level is selectable by configuring the BORV bit in Configuration Words. A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a duration greater than parameter TBORDC, the device will reset. See Figure 6-2 for more information. 6.2.1 BOR IS ALWAYS ON When the BOREN bits of Configuration Words are programmed to `11', the BOR is always on. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep. 6.2.2 BOR IS OFF IN SLEEP When the BOREN bits of Configuration Words are programmed to `10', the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready. 6.2.3 BOR CONTROLLED BY SOFTWARE When the BOREN bits of Configuration Words are programmed to `01', the BOR is controlled by the SBOREN bit of the BORCON register. The device start-up is not delayed by the BOR ready condition or the VDD level. BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY bit of the BORCON register. BOR protection is unchanged by Sleep. BOR OPERATING MODES BOREN<1:0> SBOREN Device Mode BOR Mode 11 X X Active Awake Active 10 X Sleep Disabled 1 X Active 0 X Disabled X X Disabled 01 00 Instruction Execution upon: Release of POR or Wake-up from Sleep Waits for BOR ready(1) (BORRDY = 1) Waits for BOR ready (BORRDY = 1) Waits for BOR ready(1) (BORRDY = 1) Begins immediately (BORRDY = x) Note 1: In these specific cases, "Release of POR" and "Wake-up from Sleep", there is no delay in start-up. The BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN<1:0> bits. DS40001819B-page 120 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 6-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal Reset < TPWRT TPWRT(1) VDD VBOR Internal Reset Note 1: 6.3 TPWRT(1) TPWRT delay only if PWRTE bit is programmed to `0'. Register Definitions: BOR Control REGISTER 6-1: BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u SBOREN BORFS(1) -- -- -- -- -- BORRDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 SBOREN: Software Brown-out Reset Enable bit If BOREN <1:0> in Configuration Words 01: SBOREN is read/write, but has no effect on the BOR. If BOREN <1:0> in Configuration Words = 01: 1 = BOR Enabled 0 = BOR Disabled bit 6 BORFS: Brown-out Reset Fast Start bit(1) If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off) BORFS is Read/Write, but has no effect. If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control): 1 = Band gap is forced on always (covers sleep/wake-up/operating cases) 0 = Band gap operates normally, and may turn off bit 5-1 Unimplemented: Read as `0' bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive Note 1: BOREN<1:0> bits are located in Configuration Words. 2015-2016 Microchip Technology Inc. DS40001819B-page 121 PIC16(L)F1777/8/9 6.4 Low-Power Brown-Out Reset (LPBOR) The Low-Power Brown-out Reset (LPBOR) is an essential part of the Reset subsystem. Refer to Figure 6-1 to see how the BOR interacts with other modules. The LPBOR is used to monitor the external VDD pin. When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The same bit is set for both the BOR and the LPBOR. Refer to Register 6-2. 6.4.1 ENABLING LPBOR The LPBOR is controlled by the LPBOR bit of Configuration Words. When the device is erased, the LPBOR module defaults to disabled. 6.4.1.1 LPBOR Module Output The output of the LPBOR module is a signal indicating whether or not a Reset is to be asserted. This signal is OR'd together with the Reset signal of the BOR module to provide the generic BOR signal, which goes to the PCON register and to the power control block. 6.5 MCLR 6.6 Watchdog Timer (WDT) Reset The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The TO and PD bits in the STATUS register are changed to indicate the WDT Reset. See Section 9.0 "Watchdog Timer (WDT)" for more information. 6.7 RESET Instruction A RESET instruction will cause a device Reset. The RI bit in the PCON register will be set to `0'. See Table 6-4 for default conditions after a RESET instruction has occurred. 6.8 Stack Overflow/Underflow Reset The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Words. See Section 3.6.2 "Overflow/Underflow Reset" for more information. 6.9 Programming Mode Exit Upon exit of Programming mode, the device will behave as if a POR had just occurred. The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit of Configuration Words and the LVP bit of Configuration Words (Table 6-2). 6.10 TABLE 6-2: The Power-up Timer is controlled by the PWRTE bit of Configuration Words. MCLR CONFIGURATION MCLRE LVP MCLR x 1 Enabled 1 0 Enabled 0 0 Disabled 6.5.1 MCLR ENABLED When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up. The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. Note: 6.5.2 A Reset does not drive the MCLR pin low. MCLR DISABLED When MCLR is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. See Section 11.1 "PORTA Registers" for more information. DS40001819B-page 122 Power-Up Timer The Power-up Timer optionally delays device execution after a BOR or POR event. This timer is typically used to allow VDD to stabilize before allowing the device to start running. 6.11 Start-up Sequence Upon the release of a POR or BOR, the following must occur before the device will begin executing: 1. 2. 3. Power-up Timer runs to completion (if enabled). Oscillator start-up timer runs to completion (if required for oscillator source). MCLR must be released (if enabled). The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See Section 5.0 "Oscillator Module (with Fail-Safe Clock Monitor)" for more information. The Power-up Timer and oscillator start-up timer run independently of MCLR Reset. If MCLR is kept low long enough, the Power-up Timer and oscillator start-up timer will expire. Upon bringing MCLR high, the device will begin execution after 10 FOSC cycles (see Figure 6-3). This is useful for testing purposes or to synchronize more than one device operating in parallel. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 6-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC 2015-2016 Microchip Technology Inc. DS40001819B-page 123 PIC16(L)F1777/8/9 6.12 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON registers are updated to indicate the cause of the Reset. Table 6-3 and Table 6-4 show the Reset conditions of these registers. TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition 0 0 1 1 1 0 x 1 1 Power-on Reset 0 0 1 1 1 0 x 0 x Illegal, TO is set on POR 0 0 1 1 1 0 x x 0 Illegal, PD is set on POR 0 0 u 1 1 u 0 1 1 Brown-out Reset u u 0 u u u u 0 u WDT Reset u u u u u u u 0 0 WDT Wake-up from Sleep u u u u u u u 1 0 Interrupt Wake-up from Sleep u u u 0 u u u u u MCLR Reset during normal operation u u u 0 u u u 1 0 MCLR Reset during Sleep u u u u 0 u u u u RESET Instruction Executed 1 u u u u u u u u Stack Overflow Reset (STVREN = 1) u 1 u u u u u u u Stack Underflow Reset (STVREN = 1) TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON Register Power-on Reset 0000h ---1 1000 00-- 110x MCLR Reset during normal operation 0000h ---u uuuu uu-- 0uuu MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu WDT Reset 0000h ---0 uuuu uu-- uuuu WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu Brown-out Reset 0000h ---1 1uuu 00-- 11u0 ---1 0uuu uu-- uuuu ---u uuuu uu-- u0uu Condition Interrupt Wake-up from Sleep RESET Instruction Executed PC + 1 (1) 0000h Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. DS40001819B-page 124 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 6.13 Power Control (PCON) Register The PCON register bits are shown in Register 6-2. The Power Control (PCON) register contains flag bits to differentiate between a: * * * * * * * Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) MCLR Reset (RMCLR) Watchdog Timer Reset (RWDT) Stack Underflow Reset (STKUNF) Stack Overflow Reset (STKOVF) 6.14 Register Definitions: Power Control REGISTER 6-2: PCON: POWER CONTROL REGISTER R/W/HS-0/q R/W/HS-0/q U-0 STKOVF STKUNF -- R/W/HC-1/q R/W/HC-1/q RWDT R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u RI POR BOR RMCLR bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 STKOVF: Stack Overflow Flag bit 1 = A Stack Overflow occurred 0 = A Stack Overflow has not occurred or cleared by firmware bit 6 STKUNF: Stack Underflow Flag bit 1 = A Stack Underflow occurred 0 = A Stack Underflow has not occurred or cleared by firmware bit 5 Unimplemented: Read as `0' bit 4 RWDT: Watchdog Timer Reset Flag bit 1 = A Watchdog Timer Reset has not occurred or set to `1' by firmware 0 = A Watchdog Timer Reset has occurred (cleared by hardware) bit 3 RMCLR: MCLR Reset Flag bit 1 = A MCLR Reset has not occurred or set to `1' by firmware 0 = A MCLR Reset has occurred (cleared by hardware) bit 2 RI: RESET Instruction Flag bit 1 = A RESET instruction has not been executed or set to `1' by firmware 0 = A RESET instruction has been executed (cleared by hardware) bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2015-2016 Microchip Technology Inc. DS40001819B-page 125 PIC16(L)F1777/8/9 TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN BORFS -- -- -- -- -- BORRDY 121 PCON STKOVF STKUNF -- RWDT RMCLR RI POR BOR 125 STATUS -- -- -- TO PD Z DC C 40 WDTCON -- -- SWDTEN 154 WDTPS<4:0> Legend: -- = unimplemented location, read as `0'. Shaded cells are not used by Resets. DS40001819B-page 126 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 7.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: * * * * * Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving Many peripherals produce interrupts. Refer to the corresponding chapters for details. A block diagram of the interrupt logic is shown in Figure 7-1. FIGURE 7-1: INTERRUPT LOGIC Rev. 10-000010A 1/13/2014 TMR0IF TMR0IE Peripheral Interrupts (TMR1IF) PIR1<0> (TMR1IE) PIE1<0> Wake-up (If in Sleep mode) INTF INTE IOCIF IOCIE Interrupt to CPU PEIE PIRn<7> PIEn<7> 2015-2016 Microchip Technology Inc. GIE DS40001819B-page 127 PIC16(L)F1777/8/9 7.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: * GIE bit of the INTCON register * Interrupt Enable bit(s) for the specific interrupt event(s) * PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIE1 or PIE2 registers) 7.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is three or four instruction cycles. For asynchronous interrupts, the latency is three to five instruction cycles, depending on when the interrupt occurs. See Figure 7-2 and Figure 7-3 for more details. The INTCON, PIR1 and PIR2 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits. The following events happen when an interrupt event occurs while the GIE bit is set: * Current prefetched instruction is flushed * GIE bit is cleared * Current Program Counter (PC) is pushed onto the stack * Critical registers are automatically saved to the shadow registers (See "Section 7.5 "Automatic Context Saving") * PC is loaded with the interrupt vector 0004h The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit. For additional information on a specific interrupt's operation, refer to its peripheral chapter. Note 1: Individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. DS40001819B-page 128 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 7-2: INTERRUPT LATENCY OSC1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKR Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1 Cycle Instruction at PC PC+1 0004h 0005h NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP NOP Inst(0004h) Inst(PC) Interrupt GIE PC Execute PC-1 PC 2 Cycle Instruction at PC Interrupt GIE PC Execute PC-1 PC 3 Cycle Instruction at PC Interrupt GIE PC Execute PC-1 PC 3 Cycle Instruction at PC 2015-2016 Microchip Technology Inc. PC+2 NOP NOP DS40001819B-page 129 PIC16(L)F1777/8/9 FIGURE 7-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) (4) INT pin (1) (1) INTF Interrupt Latency (2) (5) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC - 1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 -- Forced NOP 0004h Inst (0004h) Forced NOP 0005h Inst (0005h) Inst (0004h) INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT not available in all oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section 36.0 "Electrical Specifications"". 5: INTF is enabled to be set any time during the Q4-Q1 cycles. DS40001819B-page 130 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 7.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to Section 8.0 "Power-Down Mode (Sleep)" for more details. 7.4 INT Pin The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The INTEDG bit of the OPTION_REG register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector. 7.5 Automatic Context Saving Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the shadow registers: * * * * * W register STATUS register (except for TO and PD) BSR register FSR registers PCLATH register Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding shadow register should be modified and the value will be restored when exiting the ISR. The shadow registers are available in Bank 31 and are readable and writable. Depending on the user's application, other registers may also need to be saved. 2015-2016 Microchip Technology Inc. DS40001819B-page 131 PIC16(L)F1777/8/9 7.6 Register Definitions: Interrupt Control REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 GIE: Global Interrupt Enable bit 1 = Enables all active interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt bit 3 IOCIE: Interrupt-on-Change Enable bit 1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed 0 = TMR0 register did not overflow bit 1 INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit(1) 1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state Note 1: Note: The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCxF registers have been cleared by software. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS40001819B-page 132 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 gate acquisition interrupt 0 = Disables the Timer1 gate acquisition interrupt bit 6 ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 RCIE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt bit 4 TXIE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt bit 3 SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to T2PR Match Interrupt Enable bit 1 = Enables the Timer2 to T2PR match interrupt 0 = Disables the Timer2 to T2PR match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. 2015-2016 Microchip Technology Inc. DS40001819B-page 133 PIC16(L)F1777/8/9 REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 OSFIE C2IE C1IE COG1IE BCL1IE C4IE C3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator Fail interrupt 0 = Disables the Oscillator Fail interrupt bit 6 C2IE: Comparator C2 Interrupt Enable bit 1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt bit 5 C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt bit 4 COG1IE: COG1 Auto-Shutdown Interrupt Enable bit 1 = COG1 interrupt enabled 0 = COG1 interrupt disabled bit 3 BCL1IE: MSSP Bus Collision Interrupt Enable bit 1 = Enables the MSSP Bus Collision interrupt 0 = Disables the MSSP Bus Collision interrupt bit 2 C4IE: TMR6 to T6PR Match Interrupt Enable bit 1 = Enables the Comparator C4 interrupt 0 = Disables the Comparator C4 interrupt bit 1 C3IE: TMR4 to T4PR Match Interrupt Enable bit 1 = Enables the Comparator C3 interrupt 0 = Disables the Comparator C3 interrupt bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. DS40001819B-page 134 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 7-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- COG2IE ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5 COG2IE: COG2 Auto-Shutdown Interrupt Enable bit 1 = COG2 interrupt enabled 0 = COG2 interrupt disabled bit 4 ZCDIE: Zero-Cross Detection Interrupt Enable bit 1 = ZCD interrupt enabled 0 = ZCD interrupt disabled bit 3 CLC4IE: CLC4 Interrupt Enable bit 1 = CLC4 interrupt enabled 0 = CLC4 interrupt disabled bit 2 CLC3IE: CLC3 Interrupt Enable bit 1 = CLC3 interrupt enabled 0 = CLC3 interrupt disabled bit 1 CLC2IE: CLC2 Interrupt Enable bit 1 = CLC2 interrupt enabled 0 = CLC2 interrupt disabled bit 0 CLC1IE: CLC1 Interrupt Enable bit 1 = CLC1 interrupt enabled 0 = CLC1 interrupt disabled Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. 2015-2016 Microchip Technology Inc. DS40001819B-page 135 PIC16(L)F1777/8/9 REGISTER 7-5: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- TMR8IE TMR5GIE TMR5IE TMR3GIE TMR3IE TMR6IE TRM4IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6 TMR8IE: TMR8 to T8PR Match Interrupt Enable bit 1 = Enables the Timer8 to T8PR match interrupt 0 = Disables the Timer8 to T8PR match interrupt bit 5 TMR5GIE: Timer5 Gate Interrupt Enable bit 1 = Enables the Timer5 gate acquisition interrupt 0 = Disables the Timer5 gate acquisition interrupt bit 4 TMR5IE: TMR5 to Overflow Interrupt Enable bit 1 = Enables the Timer5 to T5PR match interrupt 0 = Disables the Timer5 to T5PR match interrupt bit 3 TMR3GIE: Timer3 Gate Interrupt Enable bit 1 = Enables the Timer3 gate acquisition interrupt 0 = Disables the Timer3 gate acquisition interrupt bit 2 TMR3IE: TMR3 to Overflow Interrupt Enable bit 1 = Enables the Timer3 to T3PR match interrupt 0 = Disables the Timer3 to T3PR match interrupt bit 1 TMR6IE: TMR6 to T6PR Match Interrupt Enable bit 1 = Enables the Timer6 to T6PR match interrupt 0 = Disables the Timer6 to T6PR match interrupt bit 0 TMR4IE: TMR4 to T4PR Match Interrupt Enable bit 1 = Enables the Timer4 to T4PR match interrupt 0 = Disables the Timer4 to T4PR match interrupt DS40001819B-page 136 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 7-6: R/W-0/0 CCP8IE PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5 R/W-0/0 (1) CCP7IE R/W-0/0 COG4IE R/W-0/0 R/W-0/0 R/W-0/0 COG3IE (1) (1) C8IE C7IE R/W-0/0 R/W-0/0 C6IE C5IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 CCP8IE: CCP8 Interrupt Enable bit(1) 1 = Enables the CCP8 interrupt 0 = Disables the CCP8 interrupt bit 6 CCP7IE: CCP7 Interrupt Enable bit 1 = Enables the CCP7 interrupt 0 = Disables the CCP7 interrupt bit 5 COG4IE: COG4 Auto-Shutdown Interrupt Enable bit 1 = COG4 interrupt enabled 0 = COG4 interrupt disabled bit 4 COG3IE: COG3 Auto-Shutdown Interrupt Enable bit 1 = COG3 interrupt enabled 0 = COG3 interrupt disabled bit 3 C8IE: Comparator C8 Interrupt Enable bit(1) 1 = Enables the Comparator C8 interrupt 0 = Disables the Comparator C8 interrupt bit 2 C7IE: Comparator C7 Interrupt Enable bit(1) 1 = Enables the Comparator C7 interrupt 0 = Disables the Comparator C7 interrupt bit 1 C6IE: Comparator C6 Interrupt Enable bit 1 = Enables the Comparator C6 interrupt 0 = Disables the Comparator C6 interrupt bit 0 C5IE: Comparator C5 Interrupt Enable bit 1 = Enables the Comparator C5 interrupt 0 = Disables the Comparator C5 interrupt Note 1: PIC16(L)F1777/9 only. 2015-2016 Microchip Technology Inc. DS40001819B-page 137 PIC16(L)F1777/8/9 REGISTER 7-7: R/W-0/0 PIE6: PERIPHERAL INTERRUPT ENABLE REGISTER 6 R/W-0/0 -- R/W-0/0 -- R/W-0/0 -- -- R/W-0/0 (1) PWM12IE R/W-0/0 R/W-0/0 R/W-0/0 PWM11IE PWM6IE PWM5IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3 PWM12IE: PWM12 Interrupt Enable bit(1) 1 = PWM12 interrupt enabled 0 = PWM12 interrupt disabled bit 2 PWM11IE: PWM11 Interrupt Enable bit 1 = PWM11 interrupt enabled 0 = PWM11 interrupt disabled bit 1 PWM6IE: PWM6 Interrupt Enable bit 1 = PWM6 interrupt enabled 0 = PWM6 interrupt disabled bit 0 PWM5IE: PWM5 Interrupt Enable bit 1 = PWM5 interrupt enabled 0 = PWM5 interrupt disabled Note 1: PIC16(L)F1777/9 only. DS40001819B-page 138 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 7-8: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 ADIF: Analog-to-Digital Converter (ADC) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 RCIF: EUSART Receive Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 TXIF: EUSART Transmit Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 CCP1IF: CCP1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 TMR2IF: Timer2 to T2PR Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. 2015-2016 Microchip Technology Inc. DS40001819B-page 139 PIC16(L)F1777/8/9 REGISTER 7-9: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 OSFIF C2IF C1IF COG1IF BCL1IF C4IF C3IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 C2IF: Comparator C2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 C1IF: Comparator C1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 COG1IF: COG1 Auto-Shutdown Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 BCL1IF: MSSP Bus Collision Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 C4IF: Comparator C4 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 C3IF: Comparator C3 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 CCP2IF: CCP2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS40001819B-page 140 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 7-10: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- COG2IF ZCDIF CLC4IF CLC3IF CLC2IF CLC1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5 COG2IF: COG2 Auto-Shutdown Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 ZCDIF: Zero-Cross Detection Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 CLC4IF: CLC4 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 CLC3IF: CLC3 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 CLC2IF: CLC2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 CLC1IF: CLC1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. 2015-2016 Microchip Technology Inc. DS40001819B-page 141 PIC16(L)F1777/8/9 REGISTER 7-11: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- TMR8IF TMR5GIF TMR5IF TMR3GIF TMR3IF TMR6IF TRM4IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6 TMR8IF: TMR8 to T8PR Match Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 TMR5GIF: Timer5 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 TMR5IF: TMR5 to Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 TMR3GIF: Timer3 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 TMR3IF: TMR3 to Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 TMR6IF: TMR6 to T6PR Match Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 TMR4IF: TMR4 to T4PR Match Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending DS40001819B-page 142 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 7-12: R/W-0/0 CCP8IF PIR5: PERIPHERAL INTERRUPT REQUEST REGISTER 5 R/W-0/0 (1) CCP7IF R/W-0/0 COG4IF R/W-0/0 COG3IF R/W-0/0 C8IF (1) R/W-0/0 C7IF (1) R/W-0/0 R/W-0/0 C6IF C5IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 CCP8IF: CCP8 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 CCP7IF: CCP7 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 COG4IF: COG4 Auto-Shutdown Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 COG3IF: COG3 Auto-Shutdown Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 C8IF: Comparator C8 Interrupt Flag bit(1) 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 C7IF: Comparator C7 Interrupt Flag bit(1) 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 C6IF: Comparator C6 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 C5IF: Comparator C5 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note 1: PIC16(L)F1777/9 only. 2015-2016 Microchip Technology Inc. DS40001819B-page 143 PIC16(L)F1777/8/9 REGISTER 7-13: R/W-0/0 PIR6: PERIPHERAL INTERRUPT REQUEST REGISTER 6 R/W-0/0 -- R/W-0/0 -- R/W-0/0 -- -- R/W-0/0 PWM12IF (1) R/W-0/0 R/W-0/0 R/W-0/0 PWM11IF PWM6IF PWM5IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3 PWM12IF: PWM12 Interrupt Flag bit(1) 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 PWM11IF: PWM11 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 PWM6IF: PWM6 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 PWM5IF: PWM5 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note 1: PIC16(L)F1777/9 only. DS40001819B-page 144 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 7-1: Name INTCON OPTION_REG SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132 WPUEN INTEDG TMR0CS TMR0SE PSA PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE PS<2:0> TMR1IE 274 PIE2 OSFIE C2IE C1IE COG1IE BCL1IE C4IE C3IE CCP2IE 134 PIE3 -- -- COG2IE ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE 135 133 PIE4 -- TMR8IE TMR5GIE TMR5IE TMR3GIE TMR3IE TMR6IE TRM4IE 136 PIE5 CCP8IE(1) CCP7IE COG4IE(1) COG3IE C8IE(1) C7IE(1) C6IE C5IE 137 PIE6 -- -- -- -- PWM6IE PWM5IE 138 PIR1 TMR1GIF ADIF RCIF TXIF TMR2IF TMR1IF 139 PIR2 OSFIF C2IF C1IF COG1IF BCL1IF C4IF C3IF CCP2IF 140 PIR3 -- -- COG2IF ZCDIF CLC4IF CLC3IF CLC2IF CLC1IF 141 PIR4 -- TMR8IF TMR5GIF TMR5IF TMR3GIF TMR3IF TMR6IF TRM4IF 142 PIR5 CCP8IF(1) CCP7IF COG4IF(1) COG3IF C8IF(1) C7IF(1) C6IF C5IF 143 PWM11IF PWM6IF PWM5IF 144 PIR6 Legend: Note 1: -- -- -- -- PWM12IE(1) PWM11IE SSP1IF (1) PWM12IF CCP1IF -- = unimplemented location, read as `0'. Shaded cells are not used by interrupts. PIC16(L)F1777/9 only. 2015-2016 Microchip Technology Inc. DS40001819B-page 145 PIC16(L)F1777/8/9 8.0 POWER-DOWN MODE (SLEEP) 8.1 Wake-up from Sleep The Power-Down mode is entered by executing a SLEEP instruction. The device can wake-up from Sleep through one of the following events: Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 1. 2. 3. 4. 5. 6. 7. 8. 9. WDT will be cleared but keeps running, if enabled for operation during Sleep. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. CPU clock is disabled. 31 kHz LFINTOSC is unaffected and peripherals that operate from it may continue operation in Sleep. Timer1 and peripherals that operate from Timer1 continue operation in Sleep when the Timer1 clock source selected is: * LFINTOSC * T1CKI * Secondary oscillator ADC is unaffected, if the dedicated FRC oscillator is selected. I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance). Resets other than WDT are not affected by Sleep mode. Refer to individual chapters for more details on peripheral operation during Sleep. To minimize current consumption, the following conditions should be considered: * * * * * * External Reset input on MCLR pin, if enabled BOR Reset, if enabled POR Reset Watchdog Timer, if enabled Any external interrupt Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information) The first three events will cause a device Reset. The last three events are considered a continuation of program execution. To determine whether a device Reset or wake-up event occurred, refer to Section 6.12 "Determining the Cause of a Reset". When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEP instruction, the device will then call the Interrupt Service Routine. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up. I/O pins should not be floating External circuitry sinking current from I/O pins Internal circuitry sourcing current from I/O pins Current draw from pins with internal weak pull-ups Modules using 31 kHz LFINTOSC Modules using secondary oscillator I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs. Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR modules. See Section 17.0 "5-Bit Digital-to-Analog Converter (DAC) Module" and Section 14.0 "Fixed Voltage Reference (FVR)" for more information on these modules. DS40001819B-page 146 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 8.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP - WDT and WDT prescaler will not be cleared - TO bit of the STATUS register will not be set - PD bit of the STATUS register will not be cleared FIGURE 8-1: * If the interrupt occurs during or after the execution of a SLEEP instruction - SLEEP instruction will be completely executed - Device will immediately wake-up from Sleep - WDT and WDT prescaler will be cleared - TO bit of the STATUS register will be set - PD bit of the STATUS register will be cleared Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKIN(1) TOST(3) CLKOUT(2) Interrupt flag Interrupt Latency (4) GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: Processor in Sleep PC Inst(PC) = Sleep Inst(PC - 1) PC + 1 PC + 2 PC + 2 Inst(PC + 1) Inst(PC + 2) Sleep Inst(PC + 1) PC + 2 Forced NOP 0004h 0005h Inst(0004h) Inst(0005h) Forced NOP Inst(0004h) External clock. High, Medium, Low mode assumed. CLKOUT is shown here for timing reference. TOST = 1024 TOSC. This delay does not apply to EC, RC and INTOSC Oscillator modes or Two-Speed Start-up (see Section 5.4 "Two-Speed Clock Start-up Mode". GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line. 2015-2016 Microchip Technology Inc. DS40001819B-page 147 PIC16(L)F1777/8/9 8.2 Low-Power Sleep Mode The PIC16F1773/6 devices contain an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a lower voltage. The LDO and its associated reference circuitry must remain active when the device is in Sleep mode. The PIC16F1773/6 allow the user to optimize the operating current in Sleep, depending on the application requirements. A Low-Power Sleep mode can be selected by setting the VREGPM bit of the VREGCON register. With this bit set, the LDO and reference circuitry are placed in a low-power state when the device is in Sleep. 8.2.1 SLEEP CURRENT VS. WAKE-UP TIME In the Default Operating mode, the LDO and reference circuitry remain in the normal configuration while in Sleep. The device is able to exit Sleep mode quickly since all circuits remain active. In Low-Power Sleep mode, when waking up from Sleep, an extra delay time is required for these circuits to return to the normal configuration and stabilize. 8.2.2 PERIPHERAL USAGE IN SLEEP Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected. The Low-Power Sleep mode is intended for use with the following peripherals only: * * * * Brown-out Reset (BOR) Watchdog Timer (WDT) External interrupt pin/interrupt-on-change pins Timer1 (with external clock source < 100 kHz) Note: The PIC16LF1777/8/9 do not have a configurable Low-Power Sleep mode. PIC16LF1777/8/9 are unregulated devices and are always in the lowest power state when in Sleep, with no wake-up time penalty. These devices have a lower maximum VDD and I/O voltage than the PIC16F1777/8/9. See Section 36.0 "Electrical Specifications" for more information. The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time. The Normal mode is beneficial for applications that need to wake from Sleep quickly and frequently. DS40001819B-page 148 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 8.3 Register Definitions: Voltage Regulator Control REGISTER 8-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1 -- -- -- -- -- -- VREGPM Reserved bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-2 Unimplemented: Read as `0' bit 1 VREGPM: Voltage Regulator Power Mode Selection bit 1 = Low-Power Sleep mode enabled in Sleep(2) Draws lowest current in Sleep, slower wake-up 0 = Normal Power mode enabled in Sleep(2) Draws higher current in Sleep, faster wake-up bit 0 Reserved: Read as `1'. Maintain this bit set. Note 1: 2: PIC16F1777/8/9 only. See Section 36.0 "Electrical Specifications". 2015-2016 Microchip Technology Inc. DS40001819B-page 149 PIC16(L)F1777/8/9 TABLE 8-1: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132 IOCAP IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 215 IOCAN IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 215 IOCAF IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 215 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 216 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 216 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 216 IOCCP IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 216 IOCCN IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 216 IOCCF IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 216 IOCEP -- -- -- -- IOCEP3 -- -- -- 219 IOCEN -- -- -- -- IOCEN3 -- -- -- 219 IOCEF -- -- -- -- IOCEF3 -- -- -- 220 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133 PIE2 OSFIE C2IE C1IE COG1IE BCL1IE C4IE C3IE CCP2IE 134 PIE3 -- -- COG2IE ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE 135 PIE4 -- TMR8IE TMR5GIE TMR5IE TMR3GIE TMR3IE TMR6IE TRM4IE 136 PIE5 CCP8IE(1) CCP7IE COG4IE(1) COG3IE C8IE(1) C7IE(1) C6IE C5IE 137 PWM11IE PWM6IE PWM5IE 138 (1) PIE6 -- -- -- -- PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139 PIR2 OSFIF C2IF C1IF COG1IF BCL1IF C4IF C3IF CCP2IF 140 PIR3 -- -- COG2IF ZCDIF CLC4IF CLC3IF CLC2IF CLC1IF 141 PIR4 -- TMR8IF TMR5GIF TMR5IF TMR3GIF TMR3IF TMR6IF TRM4IF 142 PIR5 CCP8IF(1) CCP7IF COG4IF(1) COG3IF C8IF(1) C7IF(1) C6IF C5IF 143 PIR6 -- -- -- -- PWM6IF PWM5IF 144 STATUS -- -- -- TO PD Z DC C 40 VREGCON(1) -- -- -- -- -- -- VREGPM(2) Reserved 149 WDTCON -- -- SWDTEN 154 Legend: Note 1: 2: PWM12IE PWM12IF(1) PWM11IF WDTPS<4:0> -- = unimplemented location, read as `0'. Shaded cells are not used in Power-Down mode. PIC16(L)F1777/9 only. Unimplemented on PIC16LF1777/8/9. DS40001819B-page 150 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 9.0 WATCHDOG TIMER (WDT) The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events. The WDT has the following features: * Independent clock source * Multiple operating modes - WDT is always on - WDT is off when in Sleep - WDT is controlled by software - WDT is always off * Configurable time-out period is from 1 ms to 256 seconds (nominal) * Multiple Reset conditions * Operation during Sleep FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM Rev. 10-000141A 7/30/2013 WDTE<1:0> = 01 SWDTEN WDTE<1:0> = 11 LFINTOSC 23-%it Programmable Prescaler WDT WDT Time-out WDTE<1:0> = 10 Sleep 2015-2016 Microchip Technology Inc. WDTPS<4:0> DS40001819B-page 151 PIC16(L)F1777/8/9 9.1 Independent Clock Source 9.4 The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See Table 36-8: Oscillator Parameters for the LFINTOSC specification. 9.2 WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Words. See Table 9-1. 9.2.1 WDT protection is active during Sleep. WDT IS OFF IN SLEEP When the WDTE bits of Configuration Words are set to `10', the WDT is on, except in Sleep. WDT protection is not active during Sleep. 9.2.3 WDT CONTROLLED BY SOFTWARE When the WDTE bits of Configuration Words are set to `01', the WDT is controlled by the SWDTEN bit of the WDTCON register. WDT protection is unchanged by Sleep. See Table 9-1 for more details. TABLE 9-1: The WDT is cleared when any of the following conditions occur: * * * * * * * Any Reset CLRWDT instruction is executed Device enters Sleep Device wakes up from Sleep Oscillator fail WDT is disabled Oscillator Start-up Timer (OST) is running See Table 9-2 for more information. WDT IS ALWAYS ON When the WDTE bits of Configuration Words are set to `11', the WDT is always on. 9.2.2 Clearing the WDT 9.5 Operation During Sleep When the device enters Sleep, the WDT is cleared. If the WDT is enabled during Sleep, the WDT resumes counting. When the device exits Sleep, the WDT is cleared again. The WDT remains clear until the OST, if enabled, completes. See Section 5.0 "Oscillator Module (with Fail-Safe Clock Monitor)" for more information on the OST. When a WDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO and PD bits in the STATUS register are changed to indicate the event. See STATUS Register (Register 3-1) for more information. WDT OPERATING MODES WDTE<1:0> SWDTEN Device Mode 11 X X 10 X WDT Mode Active Awake Active 1 01 Sleep X 0 00 9.3 X X Disabled Active Disabled Disabled Time-Out Period The WDTPS bits of the WDTCON register set the time-out period from 1 ms to 256 seconds (nominal). After a Reset, the default time-out period is two seconds. DS40001819B-page 152 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 9-2: WDT CLEARING CONDITIONS Conditions WDT WDTE<1:0> = 00 WDTE<1:0> = 01 and SWDTEN = 0 WDTE<1:0> = 10 and enter Sleep CLRWDT Command Cleared Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Change INTOSC divider (IRCF bits) 2015-2016 Microchip Technology Inc. Cleared until the end of OST Unaffected DS40001819B-page 153 PIC16(L)F1777/8/9 9.6 Register Definitions: Watchdog Control REGISTER 9-1: U-0 WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 -- R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 (1) -- WDTPS<4:0> R/W-0/0 SWDTEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits(1) Bit Value = Prescale Rate 11111 = Reserved. Results in minimum interval (1:32) * * * 10011 = Reserved. Results in minimum interval (1:32) 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 bit 0 Note 1: = = = = = = = = = = = = = = = = = = = 1:8388608 (223) (Interval 256s nominal) 1:4194304 (222) (Interval 128s nominal) 1:2097152 (221) (Interval 64s nominal) 1:1048576 (220) (Interval 32s nominal) 1:524288 (219) (Interval 16s nominal) 1:262144 (218) (Interval 8s nominal) 1:131072 (217) (Interval 4s nominal) 1:65536 (Interval 2s nominal) (Reset value) 1:32768 (Interval 1s nominal) 1:16384 (Interval 512 ms nominal) 1:8192 (Interval 256 ms nominal) 1:4096 (Interval 128 ms nominal) 1:2048 (Interval 64 ms nominal) 1:1024 (Interval 32 ms nominal) 1:512 (Interval 16 ms nominal) 1:256 (Interval 8 ms nominal) 1:128 (Interval 4 ms nominal) 1:64 (Interval 2 ms nominal) 1:32 (Interval 1 ms nominal) SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 1x: This bit is ignored. If WDTE<1:0> = 01: 1 = WDT is turned on 0 = WDT is turned off If WDTE<1:0> = 00: This bit is ignored. Times are approximate. WDT time is based on 31 kHz LFINTOSC. DS40001819B-page 154 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 9-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Bit 7 Bit 6 OSCCON SPLLEN STATUS -- -- WDTCON -- -- Bit 5 Bit 4 Bit 3 IRCF<3:0> -- Bit 2 -- TO PD Z Bit 1 Bit 0 SCS<1:0> DC WDTPS<4:0> Register on Page 116 C 40 SWDTEN 154 Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by Watchdog Timer. TABLE 9-4: Name CONFIG1 Bits SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 IESO CLKOUTEN 13:8 -- -- FCMEN 7:0 CP MCLRE PWRTE WDTE<1:0> Bit 10/2 Bit 9/1 Bit 8/0 BOREN<1:0> -- FOSC<2:0> Register on Page 95 Legend: -- = unimplemented location, read as `0'. Shaded cells are not used by Watchdog Timer. 2015-2016 Microchip Technology Inc. DS40001819B-page 155 PIC16(L)F1777/8/9 10.0 FLASH PROGRAM MEMORY CONTROL The Flash program memory is readable and writable during normal operation over the full VDD range. Program memory is indirectly addressed using Special Function Registers (SFRs). The SFRs used to access program memory are: * * * * * * PMCON1 PMCON2 PMDATL PMDATH PMADRL PMADRH When accessing the program memory, the PMDATH:PMDATL register pair forms a 2-byte word that holds the 14-bit data for read/write, and the PMADRH:PMADRL register pair forms a 2-byte word that holds the 15-bit address of the program memory location being read. The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the operating voltage range of the device. The Flash program memory can be protected in two ways; by code protection (CP bit in Configuration Words) and write protection (WRT<1:0> bits in Configuration Words). Code protection (CP = 0)(1), disables access, reading and writing, to the Flash program memory via external device programmers. Code protection does not affect the self-write and erase functionality. Code protection can only be reset by a device programmer performing a Bulk Erase to the device, clearing all Flash program memory, Configuration bits and User IDs. Write protection prohibits self-write and erase to a portion or all of the Flash program memory as defined by the bits, WRT<1:0>. Write protection does not affect a device programmers ability to read, write or erase the device. Note 1: Code protection of the entire Flash program memory array is enabled by clearing the CP bit of Configuration Words. 10.1 PMADRL and PMADRH Registers The PMADRH:PMADRL register pair can address up to a maximum of 32K words of program memory. When selecting a program address value, the MSB of the address is written to the PMADRH register and the LSB is written to the PMADRL register. DS40001819B-page 156 10.1.1 PMCON1 AND PMCON2 REGISTERS PMCON1 is the control register for Flash program memory accesses. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared by hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation to occur. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit and execute the appropriate error handling routine. The PMCON2 register is a write-only register. Attempting to read the PMCON2 register will return all `0's. To enable writes to the program memory, a specific pattern (the unlock sequence), must be written to the PMCON2 register. The required unlock sequence prevents inadvertent writes to the program memory write latches and Flash program memory. 10.2 Flash Program Memory Overview It is important to understand the Flash program memory structure for erase and programming operations. Flash program memory is arranged in rows. A row consists of a fixed number of 14-bit program memory words. A row is the minimum size that can be erased by user software. After a row has been erased, the user can reprogram all or a portion of this row. Data to be written into the program memory row is written to 14-bit wide data write latches. These write latches are not directly accessible to the user, but may be loaded via sequential writes to the PMDATH:PMDATL register pair. Note: If the user wants to modify only a portion of a previously programmed row, then the contents of the entire row must be read and saved in RAM prior to the erase. Then, new data and retained data can be written into the write latches to reprogram the row of Flash program memory. However, any unprogrammed locations can be written without first erasing the row. In this case, it is not necessary to save and rewrite the other previously programmed locations. See Table 10-1 for Erase Row size and the number of write latches for Flash program memory. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 10-1: FLASH MEMORY ORGANIZATION BY DEVICE Device PIC16(L)F1778 PIC16(L)F1777/9 10.2.1 Row Erase (words) 32 2. 3. 32 READING THE FLASH PROGRAM MEMORY Write the desired address to the PMADRH:PMADRL register pair. Clear the CFGS bit of the PMCON1 register. Then, set control bit RD of the PMCON1 register. Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the "BSF PMCON1,RD" instruction to be ignored. The data is available in the very next cycle, in the PMDATH:PMDATL register pair; therefore, it can be read as two bytes in the following instructions. The PMDATH:PMDATL register pair will hold this value until another read or until it is written to by the user. Note: FLASH PROGRAM MEMORY READ FLOWCHART Write Latches (words) To read a program memory location, the user must: 1. FIGURE 10-1: The two instructions following a program memory read are required to be NOPs. This prevents the user from executing a 2-cycle instruction on the next instruction after the RD bit is set. Rev. 10-000046A 7/30/2013 Start Read Operation Select Program or Configuration Memory (CFGS) Select Word Address (PMADRH:PMADRL) Initiate Read operation (RD = 1) Instruction fetched ignored NOP execution forced Instruction fetched ignored NOP execution forced Data read now in PMDATH:PMDATL End Read Operation 2015-2016 Microchip Technology Inc. DS40001819B-page 157 PIC16(L)F1777/8/9 FIGURE 10-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Flash ADDR Flash Data PC + 1 INSTR (PC) INSTR(PC - 1) executed here PMADRH,PMADRL INSTR (PC + 1) BSF PMCON1,RD executed here PC +3 PC+3 PMDATH,PMDATL INSTR(PC + 1) instruction ignored Forced NOP executed here PC + 5 PC + 4 INSTR (PC + 3) INSTR(PC + 2) instruction ignored Forced NOP executed here INSTR (PC + 4) INSTR(PC + 3) executed here INSTR(PC + 4) executed here RD bit PMDATH PMDATL Register EXAMPLE 10-1: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF MOVLW MOVWF PMADRL PROG_ADDR_LO PMADRL PROG_ADDR_HI PMADRH ; Select Bank for PMCON registers ; ; Store LSB of address ; ; Store MSB of address BCF BSF NOP NOP PMCON1,CFGS PMCON1,RD ; ; ; ; Do not select Configuration Space Initiate read Ignored (Figure 10-1) Ignored (Figure 10-1) MOVF MOVWF MOVF MOVWF PMDATL,W PROG_DATA_LO PMDATH,W PROG_DATA_HI ; ; ; ; Get LSB of word Store in user location Get MSB of word Store in user location DS40001819B-page 158 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 10.2.2 FLASH MEMORY UNLOCK SEQUENCE The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write programming or erasing. The sequence must be executed and completed without interruption to successfully complete any of the following operations: * Row Erase * Load program memory write latches * Write of program memory write latches to program memory * Write of program memory write latches to User IDs FIGURE 10-3: FLASH PROGRAM MEMORY UNLOCK SEQUENCE FLOWCHART Rev. 10-000047A 7/30/2013 Start Unlock Sequence Write 0x55 to PMCON2 The unlock sequence consists of the following steps: 1. Write 55h to PMCON2 2. Write AAh to PMCON2 Write 0xAA to PMCON2 3. Set the WR bit in PMCON1 4. NOP instruction 5. NOP instruction Once the WR bit is set, the processor will always force two NOP instructions. When an Erase Row or Program Row operation is being performed, the processor will stall internal operations (typical 2 ms), until the operation is complete and then resume with the next instruction. When the operation is loading the program memory write latches, the processor will always force the two NOP instructions and continue uninterrupted with the next instruction. Since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed. 2015-2016 Microchip Technology Inc. Initiate Write or Erase operation (WR = 1) Instruction fetched ignored NOP execution forced Instruction fetched ignored NOP execution forced End Unlock Sequence DS40001819B-page 159 PIC16(L)F1777/8/9 10.2.3 ERASING FLASH PROGRAM MEMORY While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. Load the PMADRH:PMADRL register pair with any address within the row to be erased. Clear the CFGS bit of the PMCON1 register. Set the FREE and WREN bits of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming unlock sequence). Set control bit WR of the PMCON1 register to begin the erase operation. See Example 10-2. After the "BSF PMCON1,WR" instruction, the processor requires two cycles to set up the erase operation. The user must place two NOP instructions immediately following the WR bit set instruction. The processor will halt internal operations for the typical 2 ms erase time. This is not Sleep mode as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the PMCON1 write instruction. FIGURE 10-4: FLASH PROGRAM MEMORY ERASE FLOWCHART Rev. 10-000048A 7/30/2013 Start Erase Operation Disable Interrupts (GIE = 0) Select Program or Configuration Memory (CFGS) Select Row Address (PMADRH:PMADRL) Select Erase Operation (FREE = 1) Enable Write/Erase Operation (WREN = 1) Unlock Sequence (See Note 1) CPU stalls while Erase operation completes (2 ms typical) Disable Write/Erase Operation (WREN = 0) Re-enable Interrupts (GIE = 1) End Erase Operation Note 1: See Figure 10-3. DS40001819B-page 160 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 EXAMPLE 10-2: ERASING ONE ROW OF PROGRAM MEMORY Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase row is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF BANKSEL MOVF MOVWF MOVF MOVWF BCF BSF BSF INTCON,GIE PMADRL ADDRL,W PMADRL ADDRH,W PMADRH PMCON1,CFGS PMCON1,FREE PMCON1,WREN MOVLW MOVWF MOVLW MOVWF BSF NOP NOP 55h PMCON2 0AAh PMCON2 PMCON1,WR BCF BSF PMCON1,WREN INTCON,GIE 2015-2016 Microchip Technology Inc. ; Disable ints so required sequences will execute properly ; Load lower 8 bits of erase address boundary ; Load upper 6 bits of erase address boundary ; Not configuration space ; Specify an erase operation ; Enable writes ; ; ; ; ; ; ; ; ; ; Start of required sequence to initiate erase Write 55h Write AAh Set WR bit to begin erase NOP instructions are forced as processor starts row erase of program memory. The processor stalls until the erase process is complete after erase processor continues with 3rd instruction ; Disable writes ; Enable interrupts DS40001819B-page 161 PIC16(L)F1777/8/9 10.2.4 WRITING TO FLASH PROGRAM MEMORY Program memory is programmed using the following steps: 1. 2. 3. 4. Load the address in PMADRH:PMADRL of the row to be programmed. Load each write latch with data. Initiate a programming operation. Repeat steps 1 through 3 until all data is written. The following steps should be completed to load the write latches and program a row of program memory. These steps are divided into two parts. First, each write latch is loaded with data from the PMDATH:PMDATL using the unlock sequence with LWLO = 1. When the last word to be loaded into the write latch is ready, the LWLO bit is cleared and the unlock sequence executed. This initiates the programming operation, writing all the latches into Flash program memory. Note: Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Program memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write. Program memory can be written one or more words at a time. The maximum number of words written at one time is equal to the number of write latches. See Figure 10-5 (row writes to program memory with 32 write latches) for more details. The write latches are aligned to the Flash row address boundary defined by the upper ten bits of PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:5>) with the lower five bits of PMADRL, (PMADRL<4:0>) determining the write latch being loaded. Write operations do not cross these boundaries. At the completion of a program memory write operation, the data in the write latches is reset to contain 0x3FFF. The special unlock sequence is required to load a write latch with data or initiate a Flash programming operation. If the unlock sequence is interrupted, writing to the latches or program memory will not be initiated. 1. 2. 3. Set the WREN bit of the PMCON1 register. Clear the CFGS bit of the PMCON1 register. Set the LWLO bit of the PMCON1 register. When the LWLO bit of the PMCON1 register is `1', the write sequence will only load the write latches and will not initiate the write to Flash program memory. 4. Load the PMADRH:PMADRL register pair with the address of the location to be written. 5. Load the PMDATH:PMDATL register pair with the program memory data to be written. 6. Execute the unlock sequence (Section 10.2.2 "Flash Memory Unlock Sequence"). The write latch is now loaded. 7. Increment the PMADRH:PMADRL register pair to point to the next location. 8. Repeat steps 5 through 7 until all but the last write latch has been loaded. 9. Clear the LWLO bit of the PMCON1 register. When the LWLO bit of the PMCON1 register is `0', the write sequence will initiate the write to Flash program memory. 10. Load the PMDATH:PMDATL register pair with the program memory data to be written. 11. Execute the unlock sequence (Section 10.2.2 "Flash Memory Unlock Sequence"). The entire program memory latch content is now written to Flash program memory. Note: The program memory write latches are reset to the blank state (0x3FFF) at the completion of every write or erase operation. As a result, it is not necessary to load all the program memory write latches. Unloaded latches will remain in the blank state. An example of the complete write sequence is shown in Example 10-3. The initial address is loaded into the PMADRH:PMADRL register pair; the data is loaded using indirect addressing. DS40001819B-page 162 2015-2016 Microchip Technology Inc. 7 BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES 6 0 7 5 4 PMADRH - r9 r8 r7 r6 r5 0 7 PMADRL r4 r3 r2 r1 r0 c4 c3 c2 c1 - 5 - 0 7 PMDATH PMDATL 6 c0 Rev. 10-000004A 7/30/2013 0 8 14 Program Memory Write Latches 5 10 14 PMADRL<4:0> Write Latch #0 00h 14 CFGS = 0 2015-2016 Microchip Technology Inc. PMADRH<6:0>: PMADRL<7:5> Row Address Decode 14 14 14 Write Latch #30 1Eh Write Latch #1 01h 14 Write Latch #31 1Fh 14 14 Row Addr Addr Addr Addr 000h 0000h 0001h 001Eh 001Fh 001h 0020h 0021h 003Eh 003Fh 002h 0040h 0041h 005Eh 005Fh 3FEh 7FC0h 7FC1h 7FDEh 7FDFh 3FFh 7FE0h 7FE1h 7FFEh 7FFFh Flash Program Memory 400h CFGS = 1 8000h - 8003h 8004h - 8005h 8006h 8007h - 8008h 8009h - 801Fh USER ID 0 - 3 reserved DEVICE ID Dev / Rev Configuration Words reserved Configuration Memory PIC16(L)F1777/8/9 DS40001819B-page 163 FIGURE 10-5: PIC16(L)F1777/8/9 FIGURE 10-6: FLASH PROGRAM MEMORY WRITE FLOWCHART Start Write Operation Determine number of words to be written into Program or Configuration Memory. The number of words cannot exceed the number of words per row. (word_cnt) Disable Interrupts (GIE = 0) Select Program or Config. Memory (CFGS) Select Row Address (PMADRH:PMADRL) Enable Write/Erase Operation (WREN = 1) Load the value to write (PMDATH:PMDATL) Update the word counter (word_cnt--) Last word to write ? Yes No Unlock Sequence (Figure10-3 x-x) Figure Select Write Operation (FREE = 0) No delay when writing to Program Memory Latches Load Write Latches Only (LWLO = 1) Increment Address (PMADRH:PMADRL++) Write Latches to Flash (LWLO = 0) Unlock Sequence (Figure10-3 x-x) Figure CPU stalls while Write operation completes (2ms typical) Disable Write/Erase Operation (WREN = 0) Re-enable Interrupts (GIE = 1) End Write Operation DS40001819B-page 164 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 EXAMPLE 10-3: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF BANKSEL MOVF MOVWF MOVF MOVWF MOVLW MOVWF MOVLW MOVWF BCF BSF BSF INTCON,GIE PMADRH ADDRH,W PMADRH ADDRL,W PMADRL LOW DATA_ADDR FSR0L HIGH DATA_ADDR FSR0H PMCON1,CFGS PMCON1,WREN PMCON1,LWLO ; ; ; ; ; ; ; ; ; ; ; ; ; Disable ints so required sequences will execute properly Bank 3 Load initial address MOVIW MOVWF MOVIW MOVWF FSR0++ PMDATL FSR0++ PMDATH ; Load first data byte into lower ; ; Load second data byte into upper ; MOVF XORLW ANDLW BTFSC GOTO PMADRL,W 0x1F 0x1F STATUS,Z START_WRITE ; Check if lower bits of address are '00000' ; Check if we're on the last of 32 addresses ; ; Exit if last of 32 words, ; MOVLW MOVWF MOVLW MOVWF BSF NOP 55h PMCON2 0AAh PMCON2 PMCON1,WR ; ; ; ; ; ; ; ; PMADRL,F LOOP ; Still loading latches Increment address ; Write next latches PMCON1,LWLO ; No more loading latches - Actually start Flash program ; memory write 55h PMCON2 0AAh PMCON2 PMCON1,WR ; ; ; ; ; ; ; ; ; ; ; ; ; Load initial data address Load initial data address Not configuration space Enable writes Only Load Write Latches Required Sequence LOOP NOP INCF GOTO Required Sequence START_WRITE BCF MOVLW MOVWF MOVLW MOVWF BSF NOP NOP BCF BSF PMCON1,WREN INTCON,GIE 2015-2016 Microchip Technology Inc. Start of required write sequence: Write 55h Write AAh Set WR bit to begin write NOP instructions are forced as processor loads program memory write latches Start of required write sequence: Write 55h Write AAh Set WR bit to begin write NOP instructions are forced as processor writes all the program memory write latches simultaneously to program memory. After NOPs, the processor stalls until the self-write process in complete after write processor continues with 3rd instruction Disable writes Enable interrupts DS40001819B-page 165 PIC16(L)F1777/8/9 10.3 Modifying Flash Program Memory When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory. Load the starting address of the row to be rewritten. Erase the program memory row. Load the write latches with data from the RAM image. Initiate a programming operation. FIGURE 10-7: FLASH PROGRAM MEMORY MODIFY FLOWCHART Rev. 10-000050A 7/30/2013 Start Modify Operation Read Operation (See Note 1) An image of the entire row read must be stored in RAM Modify Image The words to be modified are changed in the RAM image Erase Operation (See Note 2) Write Operation Use RAM image (See Note 3) End Modify Operation Note 1: See Figure 10-1. 2: See Figure 10-4. 3: See Figure 10-6. DS40001819B-page 166 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 10.4 User ID, Device ID and Configuration Word Access Instead of accessing program memory, the User ID's, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the PMCON1 register. This is the region that would be pointed to by PC<15> = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 10-2. When read access is initiated on an address outside the parameters listed in Table 10-2, the PMDATH:PMDATL register pair is cleared, reading back `0's. TABLE 10-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1) Address Function Read Access Write Access 8000h-8003h 8005h-8006h 8007h-8008h User IDs Device ID/Revision ID Configuration Words 1 and 2 Yes Yes Yes Yes No No EXAMPLE 10-4: CONFIGURATION WORD AND DEVICE ID ACCESS * This code block will read 1 word of program memory at the memory address: * PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF CLRF PMADRL PROG_ADDR_LO PMADRL PMADRH ; Select correct Bank ; ; Store LSB of address ; Clear MSB of address BSF BCF BSF NOP NOP BSF PMCON1,CFGS INTCON,GIE PMCON1,RD INTCON,GIE ; ; ; ; ; ; Select Configuration Space Disable interrupts Initiate read Executed (See Figure 10-2) Ignored (See Figure 10-2) Restore interrupts MOVF MOVWF MOVF MOVWF PMDATL,W PROG_DATA_LO PMDATH,W PROG_DATA_HI ; ; ; ; Get LSB of word Store in user location Get MSB of word Store in user location 2015-2016 Microchip Technology Inc. DS40001819B-page 167 PIC16(L)F1777/8/9 10.5 Write/Verify It is considered good programming practice to verify that program memory writes agree with the intended value. Since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete. FIGURE 10-8: FLASH PROGRAM MEMORY VERIFY FLOWCHART Rev. 10-000051A 7/30/2013 Start Verify Operation This routine assumes that the last row of data written was from an image saved on RAM. This image will be used to verify the data currently stored in Flash Program Memory Read Operation (See Note 1) PMDAT = RAM image ? No Yes Fail Verify Operation No Last word ? Yes End Verify Operation Note 1: See Figure 10-1. DS40001819B-page 168 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 10.6 Register Definitions: Flash Program Memory Control REGISTER 10-1: R/W-x/u PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PMDAT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 PMDAT<7:0>: Read/write value for Least Significant bits of program memory REGISTER 10-2: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER U-0 U-0 -- -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PMDAT<13:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 PMDAT<13:8>: Read/write value for Most Significant bits of program memory REGISTER 10-3: R/W-0/0 PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PMADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 PMADR<7:0>: Specifies the Least Significant bits for program memory address 2015-2016 Microchip Technology Inc. DS40001819B-page 169 PIC16(L)F1777/8/9 REGISTER 10-4: U-1 PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 --(1) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PMADR<14:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `1' bit 6-0 PMADR<14:8>: Specifies the Most Significant bits for program memory address Note 1: Unimplemented, read as `1'. DS40001819B-page 170 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 10-5: U-1 PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER R/W-0/0 (1) -- CFGS R/W-0/0 LWLO R/W/HC-0/0 R/W/HC-x/q(2) R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 FREE WRERR WREN WR RD (3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Bit is cleared by hardware bit 7 Unimplemented: Read as `1' bit 6 CFGS: Configuration Select bit 1 = Access Configuration, User ID and Device ID Registers 0 = Access Flash program memory bit 5 LWLO: Load Write Latches Only bit(3) 1 = Only the addressed program memory write latch is loaded/updated on the next WR command 0 = The addressed program memory write latch is loaded/updated and a write of all program memory write latches will be initiated on the next WR command bit 4 FREE: Program Flash Erase Enable bit 1 = Performs an erase operation on the next WR command (hardware cleared upon completion) 0 = Performs a write operation on the next WR command bit 3 WRERR: Program/Erase Error Flag bit 1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically on any set attempt (write `1') of the WR bit). 0 = The program or erase operation completed normally bit 2 WREN: Program/Erase Enable bit 1 = Allows program/erase cycles 0 = Inhibits programming/erasing of program Flash bit 1 WR: Write Control bit 1 = Initiates a program Flash program/erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software. 0 = Program/erase operation to the Flash is complete and inactive bit 0 RD: Read Control bit 1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a program Flash read Note 1: 2: 3: Unimplemented bit, read as `1'. The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1). The LWLO bit is ignored during a program memory erase operation (FREE = 1). 2015-2016 Microchip Technology Inc. DS40001819B-page 171 PIC16(L)F1777/8/9 REGISTER 10-6: W-0/0 PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 Program Memory Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the PMCON1 register. The value written to this register is used to unlock the writes. There are specific timing requirements on these writes. TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY Register on Page Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132 PMCON1 --(1) CFGS LWLO FREE WRERR WREN WR RD 171 PMCON2 Program Memory Control Register 2 172 PMADRL<7:0> 169 PMADRL PMADRH --(1) PMADRH<6:0> PMDATL 170 PMDATL<7:0> -- PMDATH -- 169 PMDATH<5:0> 169 Legend: -- = unimplemented location, read as `0'. Shaded cells are not used by Flash program memory. Note 1: Unimplemented, read as `1'. TABLE 10-4: Name CONFIG1 CONFIG2 Legend: SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 13:8 -- -- FCMEN IESO CLKOUTEN 7:0 CP MCLRE PWRTE 13:8 -- -- LVP DEBUG LPBOR BORV 7:0 ZCD -- -- -- -- PPS1WAY Bit 9/1 BOREN<1:0> WDTE<1:0> Bit 8/0 -- FOSC<2:0> STVREN PLLEN WRT<1:0> Register on Page 95 97 -- = unimplemented location, read as `0'. Shaded cells are not used by Flash program memory. DS40001819B-page 172 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 11.0 I/O PORTS FIGURE 11-1: GENERIC I/O PORT OPERATION Each port has six standard registers for its operation. These registers are: * TRISx registers (data direction) * PORTx registers (reads the levels on the pins of the device) * LATx registers (output latch) * INLVLx (input level control) * ODCONx registers (open-drain) * SLRCONx registers (slew rate Rev. 10-000052A 7/30/2013 Read LATx TRISx D Write LATx Write PORTx VDD CK Some ports may have one or more of the following additional registers. These registers are: Data Register Data bus * ANSELx (analog select) * WPUx (weak pull-up) I/O pin Read PORTx In general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output. However, the pin can still be read. PORTC PIC16(L)F1777/9 ANSELx To analog peripherals PORTE PORTB PIC16(L)F1778 PORTD Device To digital peripherals VSS PORT AVAILABILITY PER DEVICE PORTA TABLE 11-1: Q The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins are driving. A write operation to the LATx register has the same effect as a write to the corresponding PORTx register. A read of the LATx register reads of the values held in the I/O PORT latches, while a read of the PORTx register reads the actual I/O pin value. Ports that support analog inputs have an associated ANSELx register. When an ANSEL bit is set, the digital input buffer associated with that bit is disabled. Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 11-1. 2015-2016 Microchip Technology Inc. DS40001819B-page 173 PIC16(L)F1777/8/9 11.1 11.1.1 PORTA Registers DATA REGISTER PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 11-2). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). The exception is RA3, which is input-only and its TRIS bit will always read as `1'. Example 11-1 shows how to initialize PORTA. 11.1.5 The INLVLA register (Register 11-8) controls the input voltage threshold for each of the available PORTA input pins. A selection between the Schmitt Trigger CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTA register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See Table 36-4: I/O Ports for more information on threshold levels. Note: Reading the PORTA register (Register 11-1) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATA). 11.1.2 DIRECTION CONTROL The TRISA register (Register 11-2) controls the PORTA pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read `0'. 11.1.3 OPEN-DRAIN CONTROL The ODCONA register (Register 11-6) controls the open-drain feature of the port. Open-drain operation is independently selected for each pin. When an ODCONA bit is set, the corresponding port output becomes an open-drain driver capable of sinking current only. When an ODCONA bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. 11.1.4 SLEW RATE CONTROL The SLRCONA register (Register 11-7) controls the slew rate option for each port pin. Slew rate control is independently selectable for each port pin. When an SLRCONA bit is set, the corresponding port pin drive is slew rate limited. When an SLRCONA bit is cleared, The corresponding port pin drive slews at the maximum rate possible. DS40001819B-page 174 INPUT THRESHOLD CONTROL 11.1.6 Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. ANALOG CONTROL The ANSELA register (Register 11-4) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELA bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The ANSELA bits default to the Analog mode after reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to `0' by user software. EXAMPLE 11-1: ; ; ; ; INITIALIZING PORTA This code example illustrates initializing the PORTA register. The other ports are initialized in the same manner. BANKSEL CLRF BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF PORTA PORTA LATA LATA ANSELA ANSELA TRISA B'00111000' TRISA ; ;Init PORTA ;Data Latch ; ; ;digital I/O ; ;Set RA<5:3> as inputs ;and set RA<2:0> as ;outputs 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 11.1.7 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. Each pin defaults to the PORT latch data after reset. Other functions are selected with the peripheral pin select logic. See Section 12.0 "Peripheral Pin Select (PPS) Module" for more information. Analog input functions, such as ADC and comparator inputs are not shown in the peripheral pin select lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELA register. Digital output functions may continue to control the pin when it is in Analog mode. 2015-2016 Microchip Technology Inc. DS40001819B-page 175 PIC16(L)F1777/8/9 11.2 Register Definitions: PORTA REGISTER 11-1: PORTA: PORTA REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x R-x/x R/W-x/x R/W-x/x R/W-x/x RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared RA<7:0>: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 11-2: TRISA: PORTA TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 TRISA<7:0>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output REGISTER 11-3: LATA: PORTA DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: LATA<7:0>: RA<7:0> Output Latch Value bits(1) Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. DS40001819B-page 176 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 11-4: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 -- -- ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 ANSA<5:0>: Analog Select between Analog or Digital Function on pins RA<5:0> 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. 0 = Digital I/O. Pin is assigned to port or digital special function. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. REGISTER 11-5: WPUA: WEAK PULL-UP PORTA REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: 2: WPUA<7:0>: Weak Pull-up Register bits(1),(2) 1 = Pull-up enabled 0 = Pull-up disabled Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is configured as an output. 2015-2016 Microchip Technology Inc. DS40001819B-page 177 PIC16(L)F1777/8/9 REGISTER 11-6: ODCONA: PORTA OPEN-DRAIN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ODA7 ODA6 ODA5 ODA4 ODA3 ODA2 ODA1 ODA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ODA<7:0>: PORTA Open-Drain Enable bits For RA<7:0> pins 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) REGISTER 11-7: SLRCONA: PORTA SLEW RATE CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 SLRA<7:0>: PORTA Slew Rate Enable bits For RA<7:0> pins 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate REGISTER 11-8: INLVLA: PORTA INPUT LEVEL CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 INLVLA<7:0>: PORTA Input Level Select bits For RA<7:0> pins 1 = Port pin digital input operates with ST thresholds 0 = Port pin digital input operates with TTL thresholds DS40001819B-page 178 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 11-2: Name ANSELA INLVLA SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- -- ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 178 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 176 ODA6 ODA5 ODA4 ODA3 ODA2 ODA1 ODA0 INLVLA7 INLVLA6 LATA LATA7 ODCONA ODA7 OPTION_REG WPUEN PORTA SLRCONA INTEDG TMR0CS TMR0SE PSA PS<2:0> 178 274 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 176 SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 178 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176 WPUA WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 177 Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTA. TABLE 11-3: Name CONFIG1 SUMMARY OF CONFIGURATION WORD WITH PORTA Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 13:8 -- -- FCMEN IESO CLKOUTEN 7:0 CP MCLRE PWRTE WDTE<1:0> Bit 10/2 Bit 9/1 Bit 8/0 BOREN<1:0> -- FOSC<2:0> Register on Page 95 Legend: -- = unimplemented location, read as `0'. Shaded cells are not used by PORTA. 2015-2016 Microchip Technology Inc. DS40001819B-page 179 PIC16(L)F1777/8/9 11.3 11.3.1 PORTB Registers DATA REGISTER PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 11-10). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 11-1 shows how to initialize an I/O port. 11.3.5 The INLVLB register (Register 11-16) controls the input voltage threshold for each of the available PORTB input pins. A selection between the Schmitt Trigger CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTB register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See Table 36-4: I/O Ports for more information on threshold levels. Note: Reading the PORTB register (Register 11-9) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATB). 11.3.2 DIRECTION CONTROL The TRISB register (Register 11-10) controls the PORTB pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISB register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read `0'. 11.3.3 OPEN-DRAIN CONTROL The ODCONB register (Register 11-14) controls the open-drain feature of the port. Open-drain operation is independently selected for each pin. When an ODCONB bit is set, the corresponding port output becomes an open-drain driver capable of sinking current only. When an ODCONB bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. 11.3.4 SLEW RATE CONTROL The SLRCONB register (Register 11-15) controls the slew rate option for each port pin. Slew rate control is independently selectable for each port pin. When an SLRCONB bit is set, the corresponding port pin drive is slew rate limited. When an SLRCONB bit is cleared, The corresponding port pin drive slews at the maximum rate possible. INPUT THRESHOLD CONTROL 11.3.6 Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. ANALOG CONTROL The ANSELB register (Register 11-12) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELB bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELB bits has no effect on digital output functions. A pin with TRIS clear and ANSELB set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: 11.3.7 The ANSELB bits default to the Analog mode after reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to `0' by user software. PORTB FUNCTIONS AND OUTPUT PRIORITIES Each pin defaults to the PORT latch data after reset. Other functions are selected with the peripheral pin select logic. See Section 12.0 "Peripheral Pin Select (PPS) Module" for more information. Analog input functions, such as ADC and op amp inputs, are not shown in the peripheral pin select lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELB register. Digital output functions may continue to control the pin when it is in Analog mode. 11.3.8 HIGH CURRENT DRIVE CONTROL The output drivers on RB1 and RB0 are capable of sourcing and sinking up to 100 mA. This extra drive capacity can be enabled and disabled with the control bits in the HIDRVB register (Register 11-17). DS40001819B-page 180 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 11.4 Register Definitions: PORTB REGISTER 11-9: PORTB: PORTB REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared RB<7:0>: PORTB General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values. REGISTER 11-10: TRISB: PORTB TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 TRISB<7:0>: PORTB Tri-State Control bits 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output REGISTER 11-11: LATB: PORTB DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: LATB<7:0>: PORTB Output Latch Value bits(1) Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values. 2015-2016 Microchip Technology Inc. DS40001819B-page 181 PIC16(L)F1777/8/9 REGISTER 11-12: ANSELB: PORTB ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 -- -- ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 ANSB<5:0>: Analog Select between Analog or Digital Function on pins RB<5:0> 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. 0 = Digital I/O. Pin is assigned to port or digital special function. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. REGISTER 11-13: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Note 1: 2: WPUB<7:0>: Weak Pull-up Register bits(1,2) 1 = Pull-up enabled 0 = Pull-up disabled Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is configured as an output. DS40001819B-page 182 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 11-14: ODCONB: PORTB OPEN-DRAIN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ODB<7:0>: PORTB Open-Drain Enable bits For RB<7:0> pins 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) REGISTER 11-15: SLRCONB: PORTB SLEW RATE CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 SLRB<7:0>: PORTB Slew Rate Enable bits For RB<7:0> pins 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate REGISTER 11-16: INLVLB: PORTB INPUT LEVEL CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 INLVLB<7:0>: PORTB Input Level Select bits For RB<7:0> pins 1 = Port pin digital input operates with ST thresholds 0 = Port pin digital input operates with TTL thresholds 2015-2016 Microchip Technology Inc. DS40001819B-page 183 PIC16(L)F1777/8/9 REGISTER 11-17: HIDRVB: PORTB HIGH DRIVE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 -- -- -- -- -- -- HIDB1 HIDB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-2 Unimplemented: Read as `0' bit 1-0 HIDB<1:0>: PORTB High Drive Enable bits For RB<1:0> pins 1 = High current source and sink enabled 0 = Standard current source and sink TABLE 11-4: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Register on Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ANSELB -- -- ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182 HIDRVB -- -- -- -- -- -- HIDB1 HIDB0 184 INLVLB INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0 183 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 181 ODCONB ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 183 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 181 SLRCONB SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 183 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 183 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 182 PORTB WPUB Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTB. DS40001819B-page 184 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 11.5 11.5.1 PORTC Registers DATA REGISTER PORTC is an 8-bit wide bidirectional port in the PIC16(L)F1777/8/9 devices. The corresponding data direction register is TRISC (Register 11-19). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 11-1 shows how to initialize an I/O port. Reading the PORTC register (Register 11-18) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATC). 11.5.2 DIRECTION CONTROL The TRISC register (Register 11-19) controls the PORTC pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISC register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read `0'. 11.5.3 INPUT THRESHOLD CONTROL The INLVLC register (Register 11-25) controls the input voltage threshold for each of the available PORTC input pins. A selection between the Schmitt Trigger CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTC register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See Table 36-4: I/O Ports for more information on threshold levels. Note: Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. 2015-2016 Microchip Technology Inc. 11.5.4 OPEN-DRAIN CONTROL The ODCONC register (Register 11-23) controls the open-drain feature of the port. Open-drain operation is independently selected for each pin. When an ODCONC bit is set, the corresponding port output becomes an open-drain driver capable of sinking current only. When an ODCONC bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. 11.5.5 SLEW RATE CONTROL The SLRCONC register (Register 11-24) controls the slew rate option for each port pin. Slew rate control is independently selectable for each port pin. When an SLRCONC bit is set, the corresponding port pin drive is slew rate limited. When an SLRCONC bit is cleared, The corresponding port pin drive slews at the maximum rate possible. 11.5.6 ANALOG CONTROL The ANSELC register (Register 11-21) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELC bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELC bits has no effect on digital output functions. A pin with TRIS clear and ANSELC set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: 11.5.7 The ANSELC bits default to the Analog mode after reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to `0' by user software. PORTC FUNCTIONS AND OUTPUT PRIORITIES Each pin defaults to the PORT latch data after reset. Other functions are selected with the peripheral pin select logic. See Section 12.0 "Peripheral Pin Select (PPS) Module" for more information. Analog input functions, such as ADC and comparator inputs, are not shown in the peripheral pin select lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELC register. Digital output functions may continue to control the pin when it is in Analog mode. DS40001819B-page 185 PIC16(L)F1777/8/9 11.6 Register Definitions: PORTC REGISTER 11-18: PORTC: PORTC REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared RC<7:0>: PORTC General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values. REGISTER 11-19: TRISC: PORTC TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output DS40001819B-page 186 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 11-20: LATC: PORTC DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 LATC<7:0>: PORTC Output Latch Value bits REGISTER 11-21: ANSELC: PORTC ANALOG SELECT REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-2 ANSC<7:2>: Analog Select between Analog or Digital Function on pins RC<7:2>(1) 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. 0 = Digital I/O. Pin is assigned to port or digital special function. bit 1-0 Unimplemented: Read as `0' Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. 2015-2016 Microchip Technology Inc. DS40001819B-page 187 PIC16(L)F1777/8/9 REGISTER 11-22: WPUC: WEAK PULL-UP PORTC REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared WPUC<7:0>: Weak Pull-up Register bits(1, 2) 1 = Pull-up enabled 0 = Pull-up disabled bit 7-0 Note 1: 2: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is configured as an output. REGISTER 11-23: ODCONC: PORTC OPEN-DRAIN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ODC7 ODC6 ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ODC<7:0>: PORTC Open-Drain Enable bits For RC<7:0> pins 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) DS40001819B-page 188 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 11-24: SLRCONC: PORTC SLEW RATE CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 SLRC<7:0>: PORTC Slew Rate Enable bits For RC<7:0> pins 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate REGISTER 11-25: INLVLC: PORTC INPUT LEVEL CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 INLVLC<7:0>: PORTC Input Level Select bits For RC<7:0> pins 1 = Port pin digital input operates with ST thresholds 0 = Port pin digital input operates with TTL thresholds 2015-2016 Microchip Technology Inc. DS40001819B-page 189 PIC16(L)F1777/8/9 TABLE 11-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 -- -- 187 INLVLC INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 187 ODCONC ODC7 ODC6 ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 188 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 186 SLRCONC SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 189 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186 WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 188 Name PORTC WPUC Legend: INLVLC1 INLVLC0 189 x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTC. DS40001819B-page 190 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 11.7 11.7.1 PORTD Registers (PIC16(L)F1777/9 only) DATA REGISTER PORTD is an 8-bit wide bidirectional port in the PIC16(L)F1777/8/9 devices. The corresponding data direction register is TRISD (Register 11-27). Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 11-1 shows how to initialize an I/O port. Reading the PORTD register (Register 11-26) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATD). 11.7.2 DIRECTION CONTROL The TRISD register (Register 11-27) controls the PORTD pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISD register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read `0'. 11.7.3 INPUT THRESHOLD CONTROL The INLVLD register (Register 11-33) controls the input voltage threshold for each of the available PORTD input pins. A selection between the Schmitt Trigger CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTD register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See Table 36-4: I/O Ports for more information on threshold levels. Note: Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. 2015-2016 Microchip Technology Inc. 11.7.4 OPEN-DRAIN CONTROL The ODCOND register (Register 11-31) controls the open-drain feature of the port. Open-drain operation is independently selected for each pin. When an ODCOND bit is set, the corresponding port output becomes an open-drain driver capable of sinking current only. When an ODCOND bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. 11.7.5 SLEW RATE CONTROL The SLRCOND register (Register 11-32) controls the slew rate option for each port pin. Slew rate control is independently selectable for each port pin. When an SLRCOND bit is set, the corresponding port pin drive is slew rate limited. When an SLRCOND bit is cleared, The corresponding port pin drive slews at the maximum rate possible. 11.7.6 ANALOG CONTROL The ANSELD register (Register 11-29) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELD bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELD bits has no effect on digital output functions. A pin with TRIS clear and ANSELD set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: 11.7.7 The ANSELD bits default to the Analog mode after reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to `0' by user software. PORTD FUNCTIONS AND OUTPUT PRIORITIES Each pin defaults to the PORT latch data after reset. Other functions are selected with the peripheral pin select logic. See Section 12.0 "Peripheral Pin Select (PPS) Module" for more information. Analog input functions, such as ADC and comparator inputs, are not shown in the peripheral pin select lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELD register. Digital output functions may continue to control the pin when it is in Analog mode. DS40001819B-page 191 PIC16(L)F1777/8/9 11.8 Register Definitions: PORTD REGISTER 11-26: PORTD: PORTD REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared RD<7:0>: PORTD General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is return of actual I/O pin values. REGISTER 11-27: TRISD: PORTD TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 TRISD<7:0>: PORTD Tri-State Control bits 1 = PORTD pin configured as an input (tri-stated) 0 = PORTD pin configured as an output DS40001819B-page 192 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 11-28: LATD: PORTD DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 LATD<7:0>: PORTD Output Latch Value bits REGISTER 11-29: ANSELD: PORTD ANALOG SELECT REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: ANSD<7:0>: Analog Select between Analog or Digital Function on pins RD<7:0>(1) 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. 0 = Digital I/O. Pin is assigned to port or digital special function. When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. 2015-2016 Microchip Technology Inc. DS40001819B-page 193 PIC16(L)F1777/8/9 REGISTER 11-30: WPUD: WEAK PULL-UP PORTD REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared WPUD<7:0>: Weak Pull-up Register bits(1, 2) 1 = Pull-up enabled 0 = Pull-up disabled bit 7-0 Note 1: 2: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is configured as an output. REGISTER 11-31: ODCOND: PORTD OPEN-DRAIN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ODD7 ODD6 ODD5 ODD4 ODD3 ODD2 ODD1 ODD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ODD<7:0>: PORTD Open-Drain Enable bits For RD<7:0> pins 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) DS40001819B-page 194 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 11-32: SLRCOND: PORTD SLEW RATE CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 SLRD7 SLRD6 SLRD5 SLRD4 SLRD3 SLRD2 SLRD1 SLRD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 SLRD<7:0>: PORTD Slew Rate Enable bits For RD<7:0> pins 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate REGISTER 11-33: INLVLD: PORTD INPUT LEVEL CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 INLVLD7 INLVLD6 INLVLD5 INLVLD4 INLVLD3 INLVLD2 INLVLD1 INLVLD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 INLVLD<7:0>: PORTD Input Level Select bits For RD<7:0> pins 1 = Port pin digital input operates with ST thresholds 0 = Port pin digital input operates with TTL thresholds 2015-2016 Microchip Technology Inc. DS40001819B-page 195 PIC16(L)F1777/8/9 TABLE 11-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 193 INLVLD INLVLD7 INLVLD6 INLVLD5 INLVLD4 INLVLD3 INLVLD2 INLVLD1 INLVLD0 195 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 193 ODCOND ODD7 ODD6 ODD5 ODD4 ODD3 ODD2 ODD1 ODD0 194 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 195 SLRCOND SLRD7 SLRD6 SLRD5 SLRD4 SLRD3 SLRD2 SLRD1 SLRD0 195 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 192 WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 194 Name PORTD WPUD Legend: Note 1: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTD. PIC16(L)F1777/9 only. DS40001819B-page 196 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 11.9 11.9.1 PORTE Registers DATA REGISTER PORTE is a 4-bit wide, bidirectional port. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). The exception is RE3, which is input only and its TRIS bit will always read as `1'. Example 11-1 shows how to initialize an I/O port. Reading the PORTE register (Register 11-34) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATE). RE3 reads `0' when MCLRE = 1. Note: 11.9.2 The RE<2:0>, TRISE<2:0>, INLVL<2:0> and WPUE<2:0> pins are available on PIC16(L)F1777/9 only. DIRECTION CONTROL The TRISE register (Register 11-35) controls the PORTE pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISE register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read `0'. 11.9.3 INPUT THRESHOLD CONTROL The INLVLE register (Register 11-41) controls the input voltage threshold for each of the available PORTE input pins. A selection between the Schmitt Trigger CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTE register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See Table 36-4: I/O Ports for more information on threshold levels. Note: Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. 2015-2016 Microchip Technology Inc. 11.9.4 OPEN-DRAIN CONTROL(1) The ODCONE register (Register 11-39) controls the open-drain feature of the port. Open-drain operation is independently selected for each pin. When an ODCONE bit is set, the corresponding port output becomes an open-drain driver capable of sinking current only. When an ODCONE bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. Note 1: Implemented on PIC16(L)F1777/9 only. 11.9.5 SLEW RATE CONTROL(1) The SLRCONE register (Register 11-40) controls the slew rate option for each port pin. Slew rate control is independently selectable for each port pin. When an SLRCONE bit is set, the corresponding port pin drive is slew rate limited. When an SLRCONE bit is cleared, The corresponding port pin drive slews at the maximum rate possible. Note 1: Implemented on PIC16(L)F1777/9 only. 11.9.6 ANALOG CONTROL(1) The ANSELE register (Register 11-37) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELE bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELE bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. The TRISE register (Register 11-35) controls the PORTE pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISE register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. Note 1: Implemented on PIC16(L)F1777/9 only. 2: The ANSELE bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to `0' by user software. DS40001819B-page 197 PIC16(L)F1777/8/9 11.9.7 PORTE FUNCTIONS AND OUTPUT PRIORITIES Each pin defaults to the PORT latch data after Reset. Other functions are selected with the peripheral pin select logic. See Section 12.0 "Peripheral Pin Select (PPS) Module" for more information. Analog input functions, such as ADC and comparator inputs, are not shown in the peripheral pin select lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELE register. Digital output functions may continue to control the pin when it is in Analog mode. DS40001819B-page 198 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 11.10 Register Definitions: PORTE REGISTER 11-34: PORTE: PORTE REGISTER U-0 U-0 -- U-0 -- -- U-0 -- R-x/u R/W-x/u RE3 RE2(1) R/W-x/u RE1 (1) bit 7 R/W-x/u RE0(1) bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3-0 RE<3:0>: PORTE I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: RE<2:0> are not implemented on the PIC16(L)F1778. Read as `0'. Writes to RE<2:0> are actually written to corresponding LATE register. Reads from PORTE register is the return of actual I/O pin values. REGISTER 11-35: TRISE: PORTE TRI-STATE REGISTER U-0 U-0 -- U-0 -- -- U-0 -- U-1(2) R/W-1 R/W-1 R/W-1 -- TRISE2(1) TRISE1(1) TRISE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3 Unimplemented: Read as `1' bit 2-0 TRISE<2:0>: RE<2:0> Tri-State Control bits(1) 1 = PORTE pin configured as an input (tri-stated) 0 = PORTE pin configured as an output Note 1: 2: TRISE<2:0> are not implemented on the PIC16(L)F1778. Unimplemented, read as `1'. 2015-2016 Microchip Technology Inc. DS40001819B-page 199 PIC16(L)F1777/8/9 REGISTER 11-36: LATE: PORTE DATA LATCH REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u -- -- -- -- -- LATE2 LATE1 LATE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-3 Unimplemented: Read as `0' bit 2-0 LATE<2:0>: PORTE Output Latch Value bits Note 1: The LATE register is not implemented on the PIC16(L)F1778. Writes to RE<2:0> are actually written to corresponding LATE register. Reads from PORTE register is the return of actual I/O pin values. REGISTER 11-37: ANSELE: PORTE ANALOG SELECT REGISTER(2) U-0 U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 -- -- -- -- -- ANSE2 ANSE1 ANSE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-3 Unimplemented: Read as `0' bit 2-0 ANSE<2:0>: Analog Select between Analog or Digital Function on pins RE<2:0>(1) 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. 0 = Digital I/O. Pin is assigned to port or digital special function. Note 1: 2: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. The ANSELE register is not implemented on the PIC16(L)F1778. DS40001819B-page 200 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 11-38: WPUE: WEAK PULL-UP PORTE REGISTER U-0 U-0 -- U-0 -- -- U-0 -- R/W-1/1 WPUE3 R/W-1/1 WPUE2 (3) R/W-1/1 WPUE1 (3) bit 7 R/W-1/1 WPUE0(3) bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3-0 WPUE<3:0>: Weak Pull-up Register bit(3) 1 = Pull-up enabled 0 = Pull-up disabled Note 1: 2: 3: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in configured as an output. WPUE<2:0> is not implemented on the PIC16(L)F1778. REGISTER 11-39: ODCONE: PORTE OPEN-DRAIN CONTROL REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- -- -- -- ODE2 ODE1 ODE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-3 Unimplemented: Read as `0' bit 2-0 ODE<2:0>: PORTE Open-Drain Enable bits For RE<2:0> pins 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) Note 1: The ODCONE register is not implemented on the PIC16(L)F1778. 2015-2016 Microchip Technology Inc. DS40001819B-page 201 PIC16(L)F1777/8/9 REGISTER 11-40: SLRCONE: PORTE SLEW RATE CONTROL REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 -- -- -- -- -- SLRE2 SLRE1 SLRE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-3 Unimplemented: Read as `0' bit 2-0 SLRE<2:0>: PORTE Slew Rate Enable bits For RE<2:0> pins 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate Note 1: The SLRCONE register is not implemented on the PIC16(L)F1778. REGISTER 11-41: INLVLE: PORTE INPUT LEVEL CONTROL REGISTER U-0 U-0 -- U-0 -- U-0 -- -- R/W-1/1 R/W-1/1 INLVLE3 INLVLE2 R/W-1/1 (1) INLVLE1 R/W-1/1 (1) INLVLE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3-0 INLVLE<3:0>: PORTE Input Level Select bit 1 = ST input used for PORT reads and interrupt-on-change 0 = TTL input used for PORT reads and interrupt-on-change Note 1: INLVLE<2:0> are not implemented on the PIC16(L)F1778. TABLE 11-7: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Bit 3 Bit 2 Bit 1 Bit 0 Register on Page Bit 7 Bit 6 Bit 5 Bit 4 ANSELE(2) -- -- -- -- -- ANSELE2 ANSELE1 ANSELE0 200 INLVLE -- -- -- -- INLVLE3 INLVLE2(2) INLVLE1(2) INLVLE0(2) 202 LATE(2) -- -- -- -- -- LATE2 LATE1 LATE0 200 ODCONE(2) -- -- -- -- -- ODE2 ODE1 ODE0 201 (2) (2) (2) PORTE -- -- -- -- RE3 RE2 RE1 RE0 199 SLRCONE(2) -- -- -- -- -- SLRE2 SLRE1 SLRE0 202 TRISE2(2) TRISE1(2) TRISE0(2) 199 WPUE2(2) WPUE1(2) WPUE0(2) 201 TRISE -- -- -- -- --(1) WPUE -- -- -- -- WPUE3 Legend: Note 1: 2: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTE. Unimplemented, read as `1'. PIC16(L)F1777/9 only. DS40001819B-page 202 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 12.0 PERIPHERAL PIN SELECT (PPS) MODULE The Peripheral Pin Select (PPS) module connects peripheral inputs and outputs to the device I/O pins. Only digital signals are included in the selections. All analog inputs and outputs remain fixed to their assigned pins. Input and output selections are independent as shown in the simplified block diagram Figure 12-1. 12.1 PPS Inputs Each peripheral has a PPS register with which the inputs to the peripheral are selected. Inputs include the device pins. 12.2 PPS Outputs Each I/O pin has a PPS register with which the pin output source is selected. With few exceptions, the port TRIS control associated with that pin retains control over the pin output driver. Peripherals that control the pin output driver as part of the peripheral operation will override the TRIS control as needed. These peripherals include: * EUSART (synchronous operation) * MSSP (I2C) * COG (auto-shutdown) Although every pin has its own PPS peripheral selection register, the selections are identical for every pin as shown in Register 12-2. Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has associated analog functions, the ANSEL bit for that pin must be cleared to enable the digital input buffer. Note: The notation "Rxy" is a place holder for the pin identifier. For example, RA0PPS. Although every peripheral has its own PPS input selection register, the selections are identical for every peripheral as shown in Register 12-1. Note: The notation "xxx" in the register name is a place holder for the peripheral identifier. For example, CLC1PPS. FIGURE 12-1: SIMPLIFIED PPS BLOCK DIAGRAM PPS Outputs RA0PPS PPS Inputs abcPPS RA0 RA0 Peripheral abc RxyPPS Rxy Peripheral xyz RC7 xyzPPS 2015-2016 Microchip Technology Inc. RC7PPS RC7 DS40001819B-page 203 PIC16(L)F1777/8/9 12.3 Bidirectional Pins PPS selections for peripherals with bidirectional signals on a single pin must be made so that the PPS input and PPS output select the same pin. Peripherals that have bidirectional signals include: * EUSART (synchronous operation) * MSSP (I2C) Note: 12.4 The I2C default input pins are I2C and SMBus compatible and are the only pins on the device with this compatibility. PPS Permanent Lock The PPS can be permanently locked by setting the PPS1WAY Configuration bit. When this bit is set, the PPSLOCKED bit can only be cleared and set one time after a device Reset. This allows for clearing the PPSLOCKED bit so that the input and output selections can be made during initialization. When the PPSLOCKED bit is set after all selections have been made, it will remain set and cannot be cleared until after the next device Reset event. 12.6 Operation During Sleep PPS input and output selections are unaffected by Sleep. PPS Lock The PPS includes a mode in which all input and output selections can be locked to prevent inadvertent changes. PPS selections are locked by setting the PPSLOCKED bit of the PPSLOCK register. Setting and clearing this bit requires a special sequence as an extra precaution against inadvertent changes. Examples of setting and clearing the PPSLOCKED bit are shown in Example 12-1. EXAMPLE 12-1: 12.5 12.7 Effects of a Reset A device Power-on Reset (POR) clears all PPS input and output selections to their default values. All other Resets leave the selections unchanged. Default input selections are shown in Table 12-1. PPS LOCK/UNLOCK SEQUENCE ; suspend interrupts bcf INTCON,GIE ; BANKSEL PPSLOCK ; set bank ; required sequence, next 5 instructions movlw 0x55 movwf PPSLOCK movlw 0xAA movwf PPSLOCK ; Set PPSLOCKED bit to disable writes or ; Clear PPSLOCKED bit to enable writes bsf PPSLOCK,PPSLOCKED ; restore interrupts bsf INTCON,GIE DS40001819B-page 204 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 12.8 Register Definitions: PPS Input Selection REGISTER 12-1: xxxPPS: PERIPHERAL xxx INPUT SELECTION U-0 U-0 -- -- R/W-q/u R/W-q/u R/W-q/u R/W-q/u R/W-q/u R/W-q/u xxxPPS<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = value depends on peripheral bit 7-6 Unimplemented: Read as `0' bit 5-3 xxxPPS<5:3>: Peripheral xxx Input PORT Selection bits 100 = Peripheral input is PORTE 011 = Peripheral input is PORTD(1) 010 = Peripheral input is PORTC 001 = Peripheral input is PORTB 000 = Peripheral input is PORTA bit 2-0 xxxPPS<2:0>: Peripheral xxx Input Bit Selection bits(1) 111 = Peripheral input is from PORTx Bit 7 (Rx7) 110 = Peripheral input is from PORTx Bit 6 (Rx6) 101 = Peripheral input is from PORTx Bit 5 (Rx5) 100 = Peripheral input is from PORTx Bit 4 (Rx4) 011 = Peripheral input is from PORTx Bit 3 (Rx3) 010 = Peripheral input is from PORTx Bit 2 (Rx2) 001 = Peripheral input is from PORTx Bit 1 (Rx1) 000 = Peripheral input is from PORTx Bit 0 (Rx0) Note 1: 2: See Table 12-1 for xxxPPS register list and Reset values. PIC16(L)F1777/9 only. REGISTER 12-2: RxyPPS: PIN Rxy OUTPUT SOURCE SELECTION REGISTER U-0 U-0 -- -- R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u RxyPPS<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 RxyPPS<5:0>: Pin Rxy Output Source Selection bits Selection code determines the output signal on the port pin. See Table 12-2 for the selection codes 2015-2016 Microchip Technology Inc. DS40001819B-page 205 PIC16(L)F1777/8/9 REGISTER 12-3: PPSLOCK: PPS LOCK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 -- -- -- -- -- -- -- PPSLOCKED bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-1 Unimplemented: Read as `0' bit 0 PPSLOCKED: PPS Locked bit 1 = PPS is locked. PPS selections can not be changed. 0 = PPS is not locked. PPS selections can be changed. DS40001819B-page 206 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 12-1: PPS INPUT REGISTER RESET VALUES xxxPPS Register Peripheral Default Pin Selection Reset Value (xxxPPS<5:0>) PIC16(L)F1777/8/9 PIC16(L)F1777/8/9 Port Selection PIC16(L)F1777/9 A B Interrupt-on-change INTPPS RB0 001000 Timer0clock T0CKIPPS RA4 000100 Timer1clock T1CKIPPS RC0 010000 Timer1 gate T1GPPS RB5 001101 Timer3 clock T3CKIPPS RC0 010000 Timer3 gate T3GPPS RC0 010000 Timer5 clock T5CKIPPS RC2 010010 Timer5 gate T5GPPS RB4 001100 Timer2 input T2INPPS RC3 010011 Timer4 input T4INPPS RC5 010101 Timer6 input T6INPPS RB7 001111 Timer8 input T8INPPS RC4 010100 CCP1 CCP1PPS RC2 010010 CCP2 CCP2PPS RC1 010001 CCP7 CCP7PPS RB5 001101 CCP8(1) CCP8PPS RB0 001000 COG1 COG1INPPS RB0 001000 COG2 COG2INPPS RB1 001001 COG3 COG3INPPS RB2 COG4(1) COG4INPPS DSM1 low carrier C D Port Selection PIC16(L)F1778 A B 001010 RB3 001011 MD1CLPPS RA3 000011 DSM1 high carrier MD1CHPPS RA4 000100 DSM1 modulation MD1MODPPS RA5 000101 DSM2 low carrier MD2CLPPS RC3 010011 DSM2 high carrier MD2CHPPS RC4 010100 DSM2 modulation MD2MODPPS RC5 010101 DSM3 low carrier MD3CLPPS RB3 001011 DSM3 high carrier MD3CHPPS RB4 001100 DSM3 modulation MD3MODPPS RB5 001101 DSM4 low carrier(1) MD4CLPPS RB0 001000 DSM4 high carrier(1) MD4CHPPS RB1 001001 MD4MODPPS RB2 001010 PRG1 set rising PRG1RPPS RA4 000100 PRG1 set falling PRG1FPPS RA5 000101 PRG2 set rising PRG2RPPS RC1 010001 PRG2 set falling PRG2FPPS RC2 010010 PRG3 set rising PRG3RPPS RC4 010100 PRG3 set falling PRG3FPPS RC5 010101 PRG4 set rising(1) PRG4RPPS RB1 010100 PRG4set falling(1) PRG4FPPS RB2 010101 ADC trigger ADCACTPPS RB4 001100 DSM4 modulation (1) C E Example: CCP1PPS = 0x13 selects RC3 as the CCP1 input. Note 1: PIC16(L)F1777/9 only 2015-2016 Microchip Technology Inc. DS40001819B-page 207 PIC16(L)F1777/8/9 TABLE 12-1: PPS INPUT REGISTER RESET VALUES (CONTINUED) xxxPPS Register Peripheral 2 Default Pin Selection Reset Value (xxxPPS<5:0>) PIC16(L)F1777/8/9 PIC16(L)F1777/8/9 Port Selection PIC16(L)F1777/9 A B C D Port Selection PIC16(L)F1778 E A B C SPI and I C clock SSPCLKPPS RC3 010011 SPI and I2C data SSPDATPPS RC4 010100 SPI slave select SSPSSPPS RA5 000101 EUSART RX RXPPS RC7 010111 EUSART CK CKPPS RC6 010110 All CLCs CLCIN0PPS RA0 000000 All CLCs CLCIN1PPS RA1 000001 All CLCs CLCIN2PPS RB6 001110 All CLCs CLCIN3PPS RB7 001111 Example: CCP1PPS = 0x13 selects RC3 as the CCP1 input. Note 1: PIC16(L)F1777/9 only DS40001819B-page 208 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 12-2: AVAILABLE PORTS FOR OUTPUT BY PERIPHERAL(2) RxyPPS<5:0> Output Signal PIC16(L)F1778 A PIC16(L)F1777/9 B C (3) A B C D -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 110001 MD4_out 110000 MD3_out 101111 MD2_out 101110 MD1_out 101101 sync_C8OUT(3) -- 101100 (3) sync_C7OUT -- 101011 sync_C6OUT 101010 sync_C5OUT 101001 sync_C4OUT 101000 sync_C3OUT 100111 sync_C2OUT 100110 sync_C1OUT 100101 DT 100100 TX/CK 100011 SDO 100010 SDA 100001 SCK/SCL(1) 100000 PWM12_out(3) 011111 PWM11_out 011110 PWM6_out 011101 PWM5_out 011100 PWM10_out(3) 011011 PWM9_out 011010 PWM4_out 011001 PWM3_out 011000 CCP8_out(3) 010111 CCP7_out 010110 CCP2_out 010101 CCP1_out 010100 COG4D(1,3) 010011 (1,3) COG4C 010010 COG4B(1,3) 010001 COG4A(1,3) 010000 COG3D(1) 001111 COG3C(1) 001110 COG3B(1) 001101 COG3A (1) 001100 COG2D(1) 001011 COG2C(1) 001010 COG2B(1) Note 1: 2: 3: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- E -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRIS control is overridden by the peripheral as required. Unsupported peripherals will output a `0'. PIC16(L)F1777/9 only. 2015-2016 Microchip Technology Inc. DS40001819B-page 209 PIC16(L)F1777/8/9 TABLE 12-2: AVAILABLE PORTS FOR OUTPUT BY PERIPHERAL(2) (CONTINUED) RxyPPS<5:0> Output Signal A (1) 001001 COG2A 001000 COG1D(1) 000111 (1) COG1C 000110 COG1B(1) 000101 COG1A(1) 000100 LC4_out 000011 LC3_out 000010 LC2_out 000001 LC1_out 000000 LATxy Note 1: 2: 3: PIC16(L)F1778 PIC16(L)F1777/9 B C A B C D E TRIS control is overridden by the peripheral as required. Unsupported peripherals will output a `0'. PIC16(L)F1777/9 only. DS40001819B-page 210 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 12-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE Register on page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PPSLOCK -- -- -- -- -- -- -- PPSLOCKED INTPPS -- -- INTPPS<5:0> 205 T0CKIPPS -- -- T0CKIPPS<5:0> 205 T1CKIPPS -- -- T1CKIPPS<5:0> 205 T1GPPS -- -- T1GPPS<5:0> 205 T3CKIPPS -- -- T3CKIPPS<5:0> 205 T3GPPS -- -- T3GPPS<5:0> 205 T5CKIPPS -- -- T5CKIPPS<5:0> 205 T5GPPS -- -- T5GPPS<5:0> 205 T2INPPS -- -- T2INPPS<5:0> 205 T4INPPS -- -- T4INPPS<5:0> 205 T6INPPS -- -- T6INPPS<5:0> 205 T8INPPS -- -- T8INPPS<5:0> 205 CCP1PPS -- -- CCP1PPS<5:0> 205 CCP2PPS -- -- CCP2PPS<5:0> 205 CCP7PPS -- -- CCP7PPS<5:0> 205 CCP8PPS(1) -- -- CCP8PPS<5:0> 205 COGIN1PPS -- -- COG1PPS<5:0> 205 COG2INPPS -- -- COG2PPS<5:0> 205 COG3INPPS -- -- COG3PPS<5:0> 205 -- -- COG4PPS<5:0> 205 MD1CLPPS -- -- MD1CLPPS<5:0> 205 MD1CHPPS -- -- MD1CHPPS<5:0> 205 MD1MODPPS -- -- MD1MODPPS<5:0> 205 MD2CLPPS -- -- MD2CLPPS<5:0> 205 COG4INPPS (1) 206 MD2CHPPS -- -- MD2CHPPS<5:0> 205 MD2MODPPS -- -- MD2MODPPS<5:0> 205 MD3CLPPS -- -- MD3CLPPS<5:0> 205 MD3CHPPS -- -- MD3CHPPS<5:0> 205 MD3MODPPS -- -- MD3MODPPS<5:0> 205 (1) -- -- MD4CLPPS<5:0> 205 MD4CHPPS(1) -- -- MD4CHPPS<5:0> 205 MD4MODPPS(1) -- -- MD4MODPPS<5:0> 205 PRG1RPPS -- -- PRG1RPPS<5:0> 205 PRG1FPPS -- -- PRG1FPPS<5:0> 205 PRG2RPPS -- -- PRG2RPPS<5:0> 205 PRG2FPPS -- -- PRG2FPPS<5:0> 205 PRG3RPPS -- -- PRG3RPPS<5:0> 205 PRG3FPPS -- -- PRG3FPPS<5:0> 205 PRG4RPPS -- -- PRG4RPPS<5:0> 205 PRG4FPPS -- -- PRG4FPPS<5:0> 205 CLC1IN0PPS -- -- CLCIN0PPS<5:0> 205 MD4CLPPS 2015-2016 Microchip Technology Inc. DS40001819B-page 211 PIC16(L)F1777/8/9 TABLE 12-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE (CONTINUED) Bit 6 CLC1IN1PPS -- -- CLCIN1PPS<5:0> 205 CLC1IN2PPS -- -- CLCIN2PPS<5:0> 205 CLC1IN3PPS -- -- CLCIN3PPS<5:0> 205 ADCACTPPS -- -- ADCACTPPS<5:0> 205 SSPCLKPPS -- -- SSPCLKPPS<5:0> 205 SSPDATPPS -- -- SSPDATPPS<5:0> 205 SSPSSPPS -- -- SSPSSPPS<5:0> 205 RXPPS -- -- RXPPS<5:0> 205 CKPPS -- -- Legend: Note 1: Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 CKPPS<5:0> -- = unimplemented, read as `0'. Shaded cells are unused by the PPS module. PIC16(L)F1777/9 only. DS40001819B-page 212 Bit 0 Register on page Bit 7 205 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 13.0 INTERRUPT-ON-CHANGE All pins on all ports can be configured to operate as Interrupt-on-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual pin, or combination of pins, can be configured to generate an interrupt. The interrupt-on-change module has the following features: * * * * Interrupt-on-Change enable (Master Switch) Individual pin configuration Rising and falling edge detection Individual pin interrupt flags Figure 13-1 is a block diagram of the IOC module. 13.1 Enabling the Module 13.3 Interrupt Flags The bits located in the IOCxF registers are status flags that correspond to the Interrupt-on-Change pins of each port. If an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set. The IOCIF bit of the INTCON register reflects the status of all IOCxF bits. 13.4 Clearing Interrupt Flags The individual status flags, (IOCxF register bits), can be cleared by resetting them to zero. If another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. To allow individual pins to generate an interrupt, the IOCIE bit of the INTCON register must be set. If the IOCIE bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. In order to ensure that no detected edge is lost while clearing flags, only AND operations masking out known changed bits should be performed. The following sequence is an example of what should be performed. 13.2 Individual Pin Configuration EXAMPLE 13-1: For each pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising edge, the associated bit of the IOCxP register is set. To enable a pin to detect a falling edge, the associated bit of the IOCxN register is set. MOVLW XORWF ANDWF A pin can be configured to detect rising and falling edges simultaneously by setting the associated bits in both of the IOCxP and IOCxN registers. 13.5 CLEARING INTERRUPT FLAGS (PORTA EXAMPLE) 0xff IOCAF, W IOCAF, F Operation in Sleep The Interrupt-on-Change interrupt sequence will wake the device from Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the affected IOCxF register will be updated prior to the first instruction executed out of Sleep. 2015-2016 Microchip Technology Inc. DS40001819B-page 213 PIC16(L)F1777/8/9 FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE) Rev. 10-000 037A 6/2/201 4 IOCANx D Q R Q4Q1 edge detect RAx IOCAPx D data bus = 0 or 1 Q D S to data bus IOCAFx Q write IOCAFx R IOCIE Q2 IOC interrupt to CPU core from all other IOCnFx individual pin detectors FOSC Q1 Q1 Q2 Q2 Q2 Q3 Q3 Q4 Q4Q1 Q1 Q3 Q4 Q4Q1 DS40001819B-page 214 Q4 Q4Q1 Q4Q1 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 13.6 Register Definitions: Interrupt-on-Change Control REGISTER 13-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 IOCAP<7:0>: Interrupt-on-Change PORTA Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCAFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 13-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 IOCAN<7:0>: Interrupt-on-Change PORTA Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCAFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. 2015-2016 Microchip Technology Inc. DS40001819B-page 215 PIC16(L)F1777/8/9 REGISTER 13-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER R/W/HS-0/0 R/W/HS-0/0 IOCAF7 IOCAF6 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCAF5 IOCAF4 IOCAF3 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCAF2 IOCAF1 IOCAF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HS - Bit is set in hardware bit 7-0 IOCAF<7:0>: Interrupt-on-Change PORTA Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling edge was detected on RAx. 0 = No change was detected, or the user cleared the detected change. REGISTER 13-4: IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 IOCBP<7:0>: Interrupt-on-Change PORTB Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCBFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 13-5: IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 IOCBN<7:0>: Interrupt-on-Change PORTB Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCBFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. DS40001819B-page 216 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 13-6: IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER R/W/HS-0/0 R/W/HS-0/0 IOCBF7 IOCBF6 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCBF5 IOCBF4 IOCBF3 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCBF2 IOCBF1 IOCBF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HS - Bit is set in hardware bit 7-0 IOCBF<7:0>: Interrupt-on-Change PORTB Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling edge was detected on RBx. 0 = No change was detected, or the user cleared the detected change. 2015-2016 Microchip Technology Inc. DS40001819B-page 217 PIC16(L)F1777/8/9 REGISTER 13-7: IOCCP: INTERRUPT-ON-CHANGE PORTC POSITIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 IOCCP<7:0>: Interrupt-on-Change PORTC Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCCFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 13-8: IOCCN: INTERRUPT-ON-CHANGE PORTC NEGATIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 IOCCN<7:0>: Interrupt-on-Change PORTC Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCCFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 13-9: IOCCF: INTERRUPT-ON-CHANGE PORTC FLAG REGISTER R/W/HS-0/0 R/W/HS-0/0 IOCCF7 IOCCF6 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCCF5 IOCCF4 IOCCF3 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCCF2 IOCCF1 IOCCF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HS - Bit is set in hardware bit 7-0 IOCCF<7:0>: Interrupt-on-Change PORTC Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCCPx = 1 and a rising edge was detected on RCx, or when IOCCNx = 1 and a falling edge was detected on RCx. 0 = No change was detected, or the user cleared the detected change. DS40001819B-page 218 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 13-10: IOCEP: INTERRUPT-ON-CHANGE PORTE POSITIVE EDGE REGISTER U-0 U-0 U-0 U-0 R/W-0/0 U-0 U-0 U-0 -- -- -- -- IOCEP3 -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3 IOCEP3: Interrupt-on-Change PORTE Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCEFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. bit 2-0 Unimplemented: Read as `0' REGISTER 13-11: IOCEN: INTERRUPT-ON-CHANGE PORTE NEGATIVE EDGE REGISTER U-0 U-0 U-0 U-0 R/W-0/0 U-0 U-0 U-0 -- -- -- -- IOCEN3 -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3 IOCEN3: Interrupt-on-Change PORTE Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCEFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. bit 2-0 Unimplemented: Read as `0' 2015-2016 Microchip Technology Inc. DS40001819B-page 219 PIC16(L)F1777/8/9 REGISTER 13-12: IOCEF: INTERRUPT-ON-CHANGE PORTE FLAG REGISTER U-0 U-0 U-0 U-0 R/W/HS-0/0 U-0 U-0 U-0 -- -- -- -- IOCEF3 -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HS - Bit is set in hardware bit 7-4 Unimplemented: Read as `0' bit 3 IOCEF3: Interrupt-on-Change PORTE Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCEPx = 1 and a rising edge was detected on REx, or when IOCENx = 1 and a falling edge was detected on REx. 0 = No change was detected, or the user cleared the detected change. bit 2-0 Unimplemented: Read as `0' TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA -- -- ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177 ANSELB -- -- ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182 -- 187 Name ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 -- INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132 IOCAF IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 216 IOCAN IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 215 IOCAP IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 215 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 217 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 216 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 216 IOCCF IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 218 IOCCN IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 218 IOCCP IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 218 IOCEP -- -- -- -- IOCEP3 -- -- -- 219 IOCEN -- -- -- -- IOCEN3 -- -- -- 219 IOCEF -- -- -- -- IOCEF3 -- -- -- 220 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186 TRISE -- -- -- -- --(1) TRISE2(2) TRISE1(2) TRISE0(2) 199 Legend: Note 1: 2: -- = unimplemented location, read as `0'. Shaded cells are not used by interrupt-on-change. Unimplemented, read as `1'. Unimplemented on PIC16(L)F1778. DS40001819B-page 220 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 14.0 FIXED VOLTAGE REFERENCE (FVR) The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following: * * * * ADC input channel ADC positive reference Comparator positive input Digital-to-Analog Converter (DAC) The FVR can be enabled by setting the FVREN bit of the FVRCON register. 14.1 14.2 FVR Stabilization Period When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. See Figure 37-77: FVR Stabilization Period, PIC16LF1777/8/9 Only.. 14.3 FVR Buffer Stabilization Period When either FVR Buffer1 or Buffer2 is enabled then the buffer amplifier circuits require 30 s to stabilize.This stabilization time is required even when the FVR is already operating and stable. Independent Gain Amplifiers The output of the FVR supplied to the ADC, Comparators, and DAC is routed through two independent programmable gain amplifiers. Each amplifier can be programmed for a gain of 1x, 2x or 4x, to produce the three possible voltage levels. The ADFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Reference Section 16.0 "Analog-to-Digital Converter (ADC) Module" for additional information. The CDAFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the DAC and comparator module. Reference Section 17.0 "5-Bit Digital-to-Analog Converter (DAC) Module" and Section 19.0 "Comparator Module" for additional information. 2015-2016 Microchip Technology Inc. DS40001819B-page 221 PIC16(L)F1777/8/9 FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> CDA1FVR<1:0> CDA2FVR<1:0> 2 X1 X2 X4 ADFVR (To ADC Module) X1 X2 X4 CDA1FVR (To Comparators, DAC) X1 X2 X4 CDA2FVR (To Comparators, DAC) 2 2 HFINTOSC Enable HFINTOSC To BOR, LDO FVREN + _ FVRRDY Any peripheral requiring the Fixed Reference (See Table 14-1) TABLE 14-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR) Peripheral HFINTOSC Conditions Description FOSC<2:0> = 100 and IRCF<3:0> 000x INTOSC is active and device is not in Sleep BOREN<1:0> = 11 BOR always enabled BOR BOREN<1:0> = 10 and BORFS = 1 BOR disabled in Sleep mode, BOR Fast Start enabled BOREN<1:0> = 01 and BORFS = 1 BOR under software control, BOR Fast Start enabled LDO All PIC16F1773/6 devices, when VREGPM = 1 and not in Sleep The device runs off of the ULP regulator when in Sleep mode DS40001819B-page 222 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 14.4 Register Definitions: FVR Control REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q FVREN FVRRDY(1) R/W-0/0 TSEN (3) R/W-0/0 TSRNG R/W-0/0 (3) R/W-0/0 R/W-0/0 CDAFVR<1:0> R/W-0/0 ADFVR<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 FVREN: Fixed Voltage Reference Enable bit 1 = Fixed Voltage Reference is enabled 0 = Fixed Voltage Reference is disabled bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1) 1 = Fixed Voltage Reference output is ready for use 0 = Fixed Voltage Reference output is not ready or not enabled bit 5 TSEN: Temperature Indicator Enable bit(3) 1 = Temperature Indicator is enabled 0 = Temperature Indicator is disabled bit 4 TSRNG: Temperature Indicator Range Selection bit(3) 1 = VOUT = VDD - 4VT (High Range) 0 = VOUT = VDD - 2VT (Low Range) bit 3-2 CDAFVR<1:0>: Comparator/DAC FVR Buffer Gain Selection bits 11 = Comparator/DAC FVR Buffer Gain is 4x, with output VCDAFVR = 4x VFVR(2) 10 = Comparator/DAC FVR Buffer Gain is 2x, with output VCDAFVR = 2x VFVR(2) 01 = Comparator/DAC FVR Buffer Gain is 1x, with output VCDAFVR = 1x VFVR 00 = Comparator/DAC FVR Buffer is off bit 1-0 ADFVR<1:0>: ADC FVR Buffer Gain Selection bits 11 = ADC FVR Buffer Gain is 4x, with output VADFVR = 4x VFVR(2) 10 = ADC FVR Buffer Gain is 2x, with output VADFVR = 2x VFVR(2) 01 = ADC FVR Buffer Gain is 1x, with output VADFVR = 1x VFVR 00 = ADC FVR Buffer is off Note 1: 2: 3: FVRRDY is always `1' on PIC16F1773/6 only. Fixed Voltage Reference output cannot exceed VDD. See Section 15.0 "Temperature Indicator Module" for additional information. TABLE 14-2: Name FVRCON Legend: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE Bit 7 Bit 6 Bit 5 Bit 4 FVREN FVRRDY TSEN TSRNG Bit 3 Bit 2 CDAFVR<1:0> Bit 1 Bit 0 ADFVR<1:0> Register on page 223 Shaded cells are not used with the Fixed Voltage Reference. 2015-2016 Microchip Technology Inc. DS40001819B-page 223 PIC16(L)F1777/8/9 15.0 TEMPERATURE INDICATOR MODULE FIGURE 15-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit's range of operating temperature falls between -40C and +85C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC. Rev. 10-000069A 7/31/2013 VDD TSEN The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A onepoint calibration allows the circuit to indicate a temperature closely surrounding that point. A two-point calibration allows the circuit to sense the entire range of temperature more accurately. Reference Application Note AN1333, "Use and Calibration of the Internal Temperature Indicator" (DS01333) for more details regarding the calibration process. 15.1 TEMPERATURE CIRCUIT DIAGRAM TSRNG VOUT Temp. Indicator To ADC Circuit Operation Figure 15-1 shows a simplified block diagram of the temperature circuit. The proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions. Equation 15-1 describes the output characteristics of the temperature indicator. EQUATION 15-1: VOUT RANGES High Range: VOUT = VDD - 4VT 15.2 Minimum Operating VDD When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications. When the temperature circuit is operated in high range, the device operating voltage, VDD, must be high enough to ensure that the temperature circuit is correctly biased. Table 15-1 shows the recommended minimum VDD vs. range setting. Low Range: VOUT = VDD - 2VT TABLE 15-1: The temperature sense circuit is integrated with the Fixed Voltage Reference (FVR) module. See Section 14.0 "Fixed Voltage Reference (FVR)" for more information. The circuit is enabled by setting the TSEN bit of the FVRCON register. When disabled, the circuit draws no current. The circuit operates in either high or low range. The high range, selected by setting the TSRNG bit of the FVRCON register, provides a wider output voltage. This provides more resolution over the temperature range, but may be less consistent from part to part. This range requires a higher bias voltage to operate and thus, a higher VDD is needed. RECOMMENDED VDD VS. RANGE Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0 3.6V 1.8V 15.3 Temperature Output The output of the circuit is measured using the internal Analog-to-Digital Converter. A channel is reserved for the temperature circuit output. Refer to Section 16.0 "Analog-to-Digital Converter (ADC) Module" for detailed information. The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. DS40001819B-page 224 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 15.4 ADC Acquisition Time To ensure accurate temperature measurements, the user must wait at least 200 s after the ADC input multiplexer is connected to the temperature indicator output before the conversion is performed. In addition, the user must wait 200 s between sequential conversions of the temperature indicator output. TABLE 15-2: Name FVRCON SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Bit 7 Bit 6 Bit 5 Bit 4 FVREN FVRRDY TSEN TSRNG Bit 3 Bit 2 CDFVR<1:0> Bit 1 Bit 0 ADFVR<1:0> Register on page 223 Legend: Shaded cells are unused by the temperature indicator module. 2015-2016 Microchip Technology Inc. DS40001819B-page 225 PIC16(L)F1777/8/9 16.0 The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESH:ADRESL register pair). Figure 16-1 shows the block diagram of the ADC. The ADC voltage reference is software selectable to be either internally generated or externally supplied. FIGURE 16-1: ADC BLOCK DIAGRAM VDD ADPREF<1:0> Positive Reference Select VDD RESERVED VREF+ pin ADNREF FVR BUFFER VREF- pin ADCS<2:0> VRNEG VRPOS ANa ANb ADC_clk sampled input ANz Internal Channel Inputs Negative Reference Select VSS AN0 External Channel Inputs Rev. 10-000033E 6/11/2015 ADC Clock Select FOSC/n Fosc Divider FRC FOSC FRC Temp Indicator DACx_output ADC CLOCK SOURCE FVR_buffer1 ADC Sample Circuit CHS<4:0> ADFM set bit ADIF Write to bit GO/DONE 10 complete 10-bit Result GO/DONE Q1 Q4 ADRESH Q2 TRIGSEL<5:0> 16 start ADRESL Enable Trigger Select ADON . . . VSS Trigger Sources AUTO CONVERSION TRIGGER DS40001819B-page 226 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 16.1 ADC Configuration When configuring and using the ADC the following functions must be considered: * * * * * * Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 16.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 11.0 "I/O Ports" for more information. Note: 16.1.2 Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. CHANNEL SELECTION There are up to 27 channel selections available: * * * * * * AN<4:0> pins (PIC16(L)F1778 only) AN<11:8> pins (PIC16(L)F1778 only) AN<27:0> pins (PIC16(L)F1777/9 only) Temperature Indicator DAC1_output and DAC3_output DAC2_output and DAC4_output (PIC16(L)F1777/9 only) * FVR_buffer1 16.1.4 ADC NEGATIVE VOLTAGE REFERENCE The ADNREF bit of the ADCON1 register provides control of the negative voltage reference. The negative voltage reference can be: * VREF- pin * VSS 16.1.5 CONVERSION CLOCK The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: * * * * * * * FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (internal RC oscillator) The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11.5 TAD periods as shown in Figure 16-2. For correct conversion, the appropriate TAD specification must be met. Refer to Table 36-16: ADC Conversion Requirements for more information. Table 16-1 gives examples of appropriate ADC clock selections. Note: Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result. The CHS bits of the ADCON0 register (Register 16-1) determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section 16.2 "ADC Operation" for more information. 16.1.3 ADC POSITIVE VOLTAGE REFERENCE The ADPREF bits of the ADCON1 register provide control of the positive voltage reference. The positive voltage reference can be: * * * * * VREF+ pin VDD FVR 2.048V FVR 4.096V (Not available on LF devices) VSS See Section 16.0 "Analog-to-Digital Converter (ADC) Module" for more details on the Fixed Voltage Reference. 2015-2016 Microchip Technology Inc. DS40001819B-page 227 PIC16(L)F1777/8/9 TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz FOSC/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s FOSC/4 100 125 ns (2) (2) (2) (2) FOSC/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) FOSC/16 101 800 ns 800 ns 010 1.0 s FOSC/64 110 FRC x11 FOSC/32 Legend: Note 1: 2: 3: 4: 1.0 s 4.0 s 1.0 s 2.0 s 8.0 s(3) 1.0 s 2.0 s 4.0 s 16.0 s(3) 1.6 s 2.0 s 4.0 s 2.0 s 3.2 s 4.0 s 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 200 ns 250 ns 500 ns 8.0 s 32.0 s(2) (3) 8.0 s 16.0 s (3) 64.0 s(2) (2) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) Shaded cells are outside of recommended range. See TAD parameter for FRC source typical TAD value. These values violate the required TAD time. Outside the recommended TAD time. The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the FRC oscillator source must be used when conversions are to be performed with the device in Sleep mode. FIGURE 16-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES Rev. 10-000035A 7/30/2013 TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 THCD Conversion Starts TACQ Holding capacitor disconnected from analog input (THCD). Set GO bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is reconnected to analog input. Enable ADC (ADON bit) and Select channel (ACS bits) DS40001819B-page 228 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 16.1.6 INTERRUPTS 16.1.7 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit ADC conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format. Figure 16-3 shows the two output formats. Note 1: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. 2: The ADC operates during Sleep only when the FRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the ADIE bit of the PIE1 register and the PEIE bit of the INTCON register must both be set and the GIE bit of the INTCON register must be cleared. If all three of these bits are set, the execution will switch to the Interrupt Service Routine. FIGURE 16-3: 10-BIT ADC CONVERSION RESULT FORMAT Rev. 10-000054A 7/30/2013 ADRESH ADRESL (ADFM = 0) MSB LSB bit 7 bit 0 bit 7 10-bit ADC Result (ADFM = 1) bit 0 Unimplemented: Read as `0' MSB bit 7 Unimplemented: Read as `0' 2015-2016 Microchip Technology Inc. LSB bit 0 bit 7 bit 0 10-bit ADC Result DS40001819B-page 229 PIC16(L)F1777/8/9 16.2 16.2.1 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a `1'. Setting the GO/DONE bit of the ADCON0 register to a `1' will start the Analog-to-Digital conversion. Note: 16.2.2 16.2.5 AUTO-CONVERSION TRIGGER The Auto-conversion Trigger allows periodic ADC measurements without software intervention. When a rising edge of the selected source occurs, the GO/DONE bit is set by hardware. The Auto-conversion Trigger source is selected with the TRIGSEL<5:0> bits of the ADCON2 register. The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 16.2.6 "ADC Conversion Procedure". Using the Auto-conversion Trigger does not assure proper ADC timing. It is the user's responsibility to ensure that the ADC timing requirements are met. COMPLETION OF A CONVERSION TABLE 16-2: See Table 16-2 for auto-conversion sources. When the conversion is complete, the ADC module will: * Clear the GO/DONE bit * Set the ADIF Interrupt Flag bit * Update the ADRESH and ADRESL registers with new conversion result 16.2.3 TERMINATING A CONVERSION If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The ADRESH and ADRESL registers will be updated with the partially complete Analog-to-Digital conversion sample. Incomplete bits will match the last bit converted. Note: 16.2.4 A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC oscillator source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set. Source Peripheral Signal Name CCP1 CCP1_trigger CCP2 CCP2_trigger CCP7 CCP8 CCP7_trigger (1) CCP8_trigger Timer0 T0_overflow Timer1 T1_overflow Timer3 T3_overflow Timer5 T5_overflow Timer2 T2_postscaled Timer4 T4_postscaled Timer6 T6_postscaled Timer8 T8_postscaled Comparator C1 sync_C1OUT Comparator C2 sync_C2OUT Comparator C3 sync_C3OUT Comparator C4 sync_C4OUT Comparator C5 sync_C5OUT Comparator C6 sync_C6OUT Comparator C7(1) Comparator C8 (1) sync_C7OUT sync_C8OUT CLC1 LC1_out CLC2 LC2_out CLC3 LC3_out CLC4 LC4_out PWM3 PWM3OUT PWM4 PWM4OUT PWM9 PWM9OUT PWM9 PR/PH/OF/DC9_match PWM5 PR/PH/OF/DC5_match PWM6 PR/PH/OF/DC6_match PWM10(1) PR/PH/OF/DC10_match PWM11 PR/PH/OF/DC11_match PWM12(1) PR/PH/OF/DC12_match ADCACT ADCACTPPS Pin Note 1: DS40001819B-page 230 AUTO-CONVERSION SOURCES PIC16(L)F1777/9 only. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 16.2.6 ADC CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8. Configure Port: * Disable pin output driver (refer to the TRIS register) * Configure pin as analog (refer to the ANSEL register) * Disable weak pull-ups either globally (refer to the OPTION_REG register) or individually (refer to the appropriate WPUx register) Configure the ADC module: * Select ADC conversion clock * Configure voltage reference * Select ADC input channel * Turn on ADC module Configure ADC interrupt (optional): * Clear ADC interrupt flag * Enable ADC interrupt * Enable peripheral interrupt * Enable global interrupt(1) Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: * Polling the GO/DONE bit * Waiting for the ADC interrupt (interrupts enabled) Read ADC Result. Clear the ADC interrupt flag (required if interrupt is enabled). EXAMPLE 16-1: ADC CONVERSION ;This code block configures the ADC ;for polling, Vdd and Vss references, FRC ;oscillator and AN0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL ADCON1 ; MOVLW B'11110000' ;Right justify, FRC ;oscillator MOVWF ADCON1 ;Vdd and Vss Vref BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input BANKSEL ANSEL ; BSF ANSEL,0 ;Set RA0 to analog BANKSEL WPUA BCF WPUA,0 ;Disable weak ;pull-up on RA0 BANKSEL ADCON0 ; MOVLW B'00000001' ;Select channel AN0 MOVWF ADCON0 ;Turn ADC On CALL SampleTime ;Acquisiton delay BSF ADCON0,ADGO ;Start conversion BTFSC ADCON0,ADGO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section 16.4 "ADC Acquisition Requirements". 2015-2016 Microchip Technology Inc. DS40001819B-page 231 PIC16(L)F1777/8/9 16.3 Register Definitions: ADC Control REGISTER 16-1: R/W-0/0 ADCON0: ADC CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CHS<5:0> R/W-0/0 R/W-0/0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-2 CHS<5:0>: Analog Channel Select bits 111111 = FVR (Fixed Voltage Reference) Buffer 1 Output(2) 111110 = DAC1_output(1) 111101 = Temperature Indicator(3) 111100 = DAC2_output(1) 111011 = DAC3_output(4) 111010 = DAC4_output(4) 111001 = DAC5_output(4) 111000 = DAC6_output(4,6) 110111 = DAC7_output(4) 110110 = DAC8_output(1,6) 110101 = Reserved. No channel connected. 110010 = Switched AN18(5) 110001 = Reserved. No channel connected. * * * 101011 = Reserved. No channel connected. 101010 = Switched AN10(5) 101001 = Reserved. No channel connected. * * * 100010 = Reserved. No channel connected. 100001 = Switched AN1(5) 011100 = Reserved. No channel connected. 011011 = AN27(6) 011010 = AN26(6) 011001 = AN25(6) 011000 = AN24(6) 010111 = AN23(6) 010110 = AN22(6) 010101 = AN21(6) 010100 = AN20(6) 010011 = AN19 010010 = AN18 010001 = AN17 010000 = AN16 001111 = AN15 001110 = AN14 001101 = AN13 001100 = AN12 001011 = AN11 001010 = AN10 001001 = AN9 001000 = AN8 000111 = AN7(6) 000110 = AN6(6) 000101 = AN5(6) 000100 = AN4 000011 = AN3 000010 = AN2 000001 = AN1 000000 = AN0 DS40001819B-page 232 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 16-1: ADCON0: ADC CONTROL REGISTER 0 (CONTINUED) bit 1 GO/DONE: ADC Conversion Status bit 1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. This bit is automatically cleared by hardware when the ADC conversion has completed. 0 = ADC conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: 2: 3: 4: 5: 6: See Section 17.0 "5-Bit Digital-to-Analog Converter (DAC) Module" for more information. See Section 14.0 "Fixed Voltage Reference (FVR)" for more information. See Section 15.0 "Temperature Indicator Module" for more information. See Section 18.0 "10-bit Digital-to-Analog Converter (DAC) Module" for more information. Input source is switched off when op amp override is forcing tri-state. See Section 29.3 "Override Control" PIC16(L)F1777/9 only. 2015-2016 Microchip Technology Inc. DS40001819B-page 233 PIC16(L)F1777/8/9 REGISTER 16-2: R/W-0/0 ADCON1: ADC CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS<2:0> U-0 R/W-0/0 -- ADNREF R/W-0/0 bit 7 R/W-0/0 ADPREF<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 ADFM: ADC Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are set to `0' when the conversion result is loaded. 0 = Left justified. Six Least Significant bits of ADRESL are set to `0' when the conversion result is loaded. bit 6-4 ADCS<2:0>: ADC Conversion Clock Select bits 111 = FRC (clock supplied from an internal RC oscillator) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock supplied from an internal RC oscillator) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 bit 3 Unimplemented: Read as `0' bit 2 ADNREF: ADC Negative Voltage Reference Configuration bit 1 = VREF- is connected to external VREF- pin 0 = VREF- is connected to VSS bit 1-0 ADPREF<1:0>: ADC Positive Voltage Reference Configuration bits 11 = VREF+ is connected to internal Fixed Voltage Reference (FVR) module(1) 10 = VREF+ is connected to external VREF+ pin(1) 01 = Reserved 00 = VREF+ is connected to VDD Note 1: When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage specification exists. See Table 36-16: ADC Conversion Requirements for details. DS40001819B-page 234 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 16-3: ADCON2: ADC CONTROL REGISTER 2 U-0 U-0 -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TRIGSEL<5:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 TRIGSEL<5:0>: Auto-Conversion Trigger Selection bits(1) 101101 = PWM12 - OF12_match(2) 101100 = PWM12 - PH12_match(2) 101011 = PWM12 - PR12_match(2) 101010 = PWM12 - DC12_match(2) 101001 = PWM11 - OF11_match 101000 = PWM11 - PH11_match 100111 = PWM11 - PR11_match 100110 = PWM11 - DC11_match 100101 = PWM6 - OF6_match 100100 = PWM6 - PH6_match 100011 = PWM6 - PR6_match 100010 = PWM6 - DC6_match 100001 = PWM5 - PH5_match 100000 = PWM5 - PH5_match 011111 = PWM5 - PH5_match 011110 = PWM5 - PH5_match 011101 = PWM10 - PWM10OUT(2) 011100 = PWM9 - PWM9OUT 011011 = PWM4 - PWM4OUT 011010 = PWM3 - PWM3OUT 011001 = CCP8 - CCP8_trigger(2) 011000 = CCP7 - CCP7_trigger 010111 = CCP2 - CCP2_trigger 010110 = CCP1 - CCP1_trigger 010101 = CLC4 - LC4_out 010100 = CLC3 - LC3_out 010011 = CLC2 - LC2_out 010010 = CLC1 - LC1_out 010001 = Comparator C8 - sync_C8OUT(2) 010000 = Comparator C7 - sync_C7OUT(2) 001111 = Comparator C6 - sync_C6OUT 001110 = Comparator C5 - sync_C5OUT 001101 = Comparator C4 - sync_C4OUT 001100 = Comparator C3 - sync_C3OUT 001011 = Comparator C2 - sync_C2OUT 001010 = Comparator C1 - sync_C1OUT 001001 = Timer8 - T8_postscaled 001000 = Timer6 - T6_postscaled 000111 = Timer5 - T5_overflow 000110 = Timer4 - T4_postscaled 000101 = Timer3 - T3_overflow 000100 = Timer2 - T2_postscaled 000011 = Timer1 - T1_overflow 000010 = Timer0 - T0_overflow 000001 = ADCACT - ADCACTPPS Pin 000000 = No Auto-conversion Trigger selected Note 1: 2: This is a rising edge sensitive input for all sources. PIC16(L)F1777/9 only. 2015-2016 Microchip Technology Inc. DS40001819B-page 235 PIC16(L)F1777/8/9 REGISTER 16-4: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 16-5: R/W-x/u ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x/u ADRES<1:0> R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u -- -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved: Do not use. DS40001819B-page 236 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 16-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u -- -- -- -- -- -- R/W-x/u R/W-x/u ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Result Register bits Upper two bits of 10-bit conversion result REGISTER 16-7: R/W-x/u ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADRES<7:0>: ADC Result Register bits Lower eight bits of 10-bit conversion result 2015-2016 Microchip Technology Inc. DS40001819B-page 237 PIC16(L)F1777/8/9 16.4 ADC Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 16-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 16-4. The maximum recommended impedance for analog sources is 10 k. As the ACQUISITION TIME EXAMPLE(1,2,3) EQUATION 16-1: Assumptions: source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an ADC acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 16-1 may be used. This equation assumes that 1/2 LSb error is used (1,024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. Temperature = 50C and external impedance of 10k 5.0V V DD T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = T AMP + T C + T COFF = 2s + T C + Temperature - 25C 0.05s/C The value for TC can be approximated with the following equations: 1 = V CHOLD V AP P LI ED 1 - -------------------------n+1 2 -1 ;[1] VCHOLD charged to within 1/2 lsb -TC ---------- RC V AP P LI ED 1 - e = V CHOLD ;[2] VCHOLD charge response to VAPPLIED - Tc --------- 1 RC ;combining [1] and [2] V AP P LI ED 1 - e = V A PP LIE D 1 - -------------------------n+1 2 -1 Note: Where n = number of bits of the ADC. Solving for TC: T C = - C HOLD R IC + R SS + R S ln(1/2047) = - 10pF 1k + 7k + 10k ln(0.0004885) = 1.37 s Therefore: T A CQ = 2s + 892ns + 50C- 25C 0.05 s/C = 4.62s Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. DS40001819B-page 238 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 16-4: ANALOG INPUT MODEL VDD Analog Input pin Rs VT 0.6V CPIN 5 pF VA RIC 1k Sampling Switch SS Rss I LEAKAGE(1) VT 0.6V CHOLD = 10 pF Ref- 6V 5V VDD 4V 3V 2V = Sample/Hold Capacitance = Input Capacitance Legend: CHOLD CPIN RSS I LEAKAGE = Leakage current at the pin due to various junctions = Interconnect Resistance RIC RSS = Resistance of Sampling Switch SS = Sampling Switch VT = Threshold Voltage Note 1: FIGURE 16-5: 5 6 7 8 9 10 11 Sampling Switch (k) Refer to Table 36-4: I/O Ports (parameter D060). ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh ADC Output Code 3FDh 3FCh 3FBh 03h 02h 01h 00h Analog Input Voltage 0.5 LSB Ref- 2015-2016 Microchip Technology Inc. Zero-Scale Transition 1.5 LSB Full-Scale Transition Ref+ DS40001819B-page 239 PIC16(L)F1777/8/9 TABLE 16-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 -- ADNREF CHS<5:0> ADCON0 ADCON1 ADFM -- ADCON2 ADCS<2:0> -- Bit 1 Bit 0 Register on Page GO/DONE ADON 232 ADPREF<1:0> TRIGSEL<5:0> 234 235 ADRESH ADC Result Register High 236, 237 ADRESL ADC Result Register Low 236, 237 ANSELA -- -- ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177 ANSELB -- -- ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 -- -- FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 223 DAC1CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 244 DAC2CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 244 NSS<1:0> 244 DAC5CON0 EN FM OE1 OE2 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB6 TRISB6 TRISB1 TRISB0 181 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186 Legend: PSS<1:0> 187 132 x = unknown, u = unchanged, -- = unimplemented read as `0', q = value depends on condition. Shaded cells are not used for the ADC module. DS40001819B-page 240 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 17.0 5-BIT DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels. The input of the DAC can be connected to: * External VREF pins * VDD supply voltage * FVR (Fixed Voltage Reference) The output of the DAC can be configured to supply a reference voltage to the following: * Comparator positive input * Operational amplifier inverting and non-inverting inputs * ADC input channel * DACXOUTX pin TABLE 17-1: 17.3 DAC Voltage Reference Output The DAC voltage can be output to the DACxOUTx pin by setting the OEx bit of the DACxCON0 register. Selecting the DAC voltage for output on the DACXOUTX pin automatically overrides the digital output buffer and digital input threshold detector functions of that pin. Reading the DACXOUTX pin when it has been configured for DAC voltage output will always return a `0'. Due to the limited current drive capability, a buffer must be used on the DAC voltage output for external connections to the DACXOUTX pin. Figure 17-2 shows an example buffering technique. AVAILABLE 5-BIT DACS Device DAC3 DAC4 DAC7 PIC16(L)F1778 PIC16(L)F1777/9 DAC8 The Digital-to-Analog Converter (DAC) is enabled by setting the EN bit of the DACxCON0 register. 17.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the REF<4:0> bits of the DACxREF register. The DAC output voltage is determined by Equation 17-1: EQUATION 17-1: DAC OUTPUT VOLTAGE IF DACxEN = 1 DACxR 4:0 VOUT = VSOURCE+ - VSOURCE- --------------------------------- + VSOURCE5 2 VSOURCE+ = VDD, VREF, or FVR BUFFER 2 VSOURCE- = VSS 17.2 Ratiometric Output Level The DAC output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. If the voltage of either input source fluctuates, a similar fluctuation will result in the DAC output value. The value of the individual resistors within the ladder can be found in Table 36-20: 10-bit Digital-to-Analog Converter (DAC) Specifications. 2015-2016 Microchip Technology Inc. DS40001819B-page 241 PIC16(L)F1777/8/9 FIGURE 17-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DAC) FVR_buffer2 VSOURCE+ VDD 5 VREF+ R<4:0> R R PSS<1:0> 2 R EN R 32 Steps R 32-to-1 MUX R DACX_Output R (To Comparator and ADC Modules) DACXOUT1 R OE1 NSS<1:0> DACXOUT2 Reserved VSOURCE- OE2 VREF1VREF0VSS FIGURE 17-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC(R) MCU DAC Module R Voltage Reference Output Impedance DS40001819B-page 242 DACXOUTX + - Buffered DAC Output 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 17.4 Operation During Sleep The DAC continues to function during Sleep. When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DACxCON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 17.5 Effects of a Reset A device Reset affects the following: * DAC is disabled. * DAC output voltage is removed from the DACXOUTX pin. * The REF<4:0> voltage reference control bits are cleared. 2015-2016 Microchip Technology Inc. DS40001819B-page 243 PIC16(L)F1777/8/9 17.6 Register Definitions: DAC Control Long bit name prefixes for the 5-bit DAC peripherals are shown in Table 17-2. Refer to Section 1.1 "Register and Bit naming conventions" for more information TABLE 17-2: Peripheral Bit Name Prefix DAC3 DAC3 DAC4 DAC4 DAC7 DAC7 DAC8(1) DAC8 Note 1: PIC16(L)F1777/9 only. REGISTER 17-1: DACxCON0: DACx CONTROL REGISTER 0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 EN -- OE1 OE2 R/W-0/0 R/W-0/0 PSS<1:0> U-0 R/W-0/0 NSS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 EN: DAC Enable bit 1 = DAC is enabled 0 = DAC is disabled bit 6 Unimplemented: Read as `0' bit 5 OE1: DAC Voltage Output Enable bit 1 = DAC voltage level is also an output on the DACxOUT1 pin 0 = DAC voltage level is disconnected from the DACxOUT1 pin bit 4 OE2: DAC Voltage Output Enable bit 1 = DAC voltage level is also an output on the DACxOUT2 pin 0 = DAC voltage level is disconnected from the DACxOUT2 pin bit 3-2 PSS<1:0>: DAC Positive Source Select bits 11 = Reserved, do not use 10 = FVR Buffer2 output 01 = VREF+ pin 00 = VDD bit 1-0 NSS<1:0>: DAC Negative Source Select bits 11 = Reserved, do not use 10 = DACxREF1- (DAC7/8) or Reserved (DAC3/4) 01 = DACxREF000 = AGND (AVSS) DS40001819B-page 244 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 17-2: DACxREF: DACx REFERENCE VOLTAGE OUTPUT SELECT REGISTER U-0 U-0 U-0 -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 REF<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-5 Unimplemented: Read as `0' bit 4-0 REF<4:0>: DACx Reference Voltage Output Select bits (See Equation 17-1) TABLE 17-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE DACx MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page DAC3CON0 EN -- OE1 OE2 PSS<1:0> NSS<1:0> 244 DAC4CON0 EN --- OE1 OE2 PSS<1:0> NSS<1:0> 244 DAC7CON0 EN --- OE1 OE2 PSS<1:0> NSS<1:0> 244 DAC8CON0(1) EN --- OE1 OE2 PSS<1:0> NSS<1:0> DAC3REF --- --- --- REF<4:0> 245 DAC4REF --- --- --- REF<4:0> 245 DAC7REF --- --- --- REF<4:0> 245 --- --- --- REF<4:0> 245 (1) DAC8REF Legend: Note 1: 244 -- = Unimplemented location, read as `0'. Shaded cells are not used with the DACx module. PIC16LF1777/9 only. 2015-2016 Microchip Technology Inc. DS40001819B-page 245 PIC16(L)F1777/8/9 18.0 10-BIT DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE The 10-bit Digital-to-Analog Converter (DAC) supplies a variable voltage reference, ratiometric with the input source, with 1024 selectable output levels. The input of the DAC can be connected to: * External VREF pins * VDD supply voltage * FVR (Fixed Voltage Reference) The output of the DAC can be configured to supply a reference voltage to the following: * * * * Comparator positive input ADC input channel DACXOUT1 pin Op Amp AVAILABLE 10-BIT DACS Device DAC1 DAC2 DAC5 PIC16(L)F1778 PIC16(L)F1777/9 18.1 DAC6 Output Voltage Level Selection The DAC has 1024 voltage levels that are set by the 10-bit reference selection word contained in the DACxREFH and DACxREFL registers. This 10-bit word can be left or right justified. See Section 18.4 "DAC Reference Selection Justification" for more detail. DAC Output The DAC voltage is always available to the internal peripherals that use it. The DAC voltage can be output to the DACxOUTx pin by setting the OEx bit of the DACxCON0 register. Selecting the DAC voltage for output on the DACxOUTx pin automatically overrides the digital output buffer and digital input threshold detector functions of that pin. Reading the DACXOUTX pin when it has been configured for DAC voltage output will always return a `0'. Due to the limited current drive capability, a buffer must be used on the DAC voltage output for external connections to either DACXOUTX pin. Figure 18-3 shows a buffering technique example. 18.4 The Digital-to-Analog Converter is enabled by setting the EN bit of the DACxCON0 register. TABLE 18-1: 18.3 DAC Reference Selection Justification The DAC reference selection can be configured to be left or right justified. When the FM bit of the DACxCON0 register is set, the 10-bit word is left justified such that the eight Most Significant bits fill the DACxREFH register and the two Least Significant bits are left justified in the DACxREFL register. When the FM bit is cleared, the 10-bit word is right justified such that the eight Least Significant bits fill the DACxREFL register and the two Most Significant bits are right justified in the DACxREFH register. Refer to Figure 18-1. The DACxREFL and DACxREFH registers are double buffered. Writing to either register does not take effect immediately. Writing a `1' to the DACxLD bit of the DACLD register transfers the contents of the DACxREFH and DACxREFL registers to the buffers, thereby changing all 10-bits of the DAC reference selection simultaneously. The DAC output voltage can be determined with Equation 18-1. 18.2 Ratiometric Output Voltage The DAC output voltage is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage source. If the voltage of either input source fluctuates, a similar fluctuation will result in the DAC output value. The value of the individual resistors within the ladder can be found in Table 36-20. EQUATION 18-1: DAC OUTPUT VOLTAGE IF EN = 1 DACxR 9:0 DACx_output = VSOURCE + - VSOURCE - ------------------------------- + VSOURCE 10 2 VSOURCE+ = VDD, VREF+, or FVR_buffer2 VSOURCE- = VSS OR VREF- DS40001819B-page 246 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 18-1: DAC JUSTIFICATION FM = 1 R9 R8 R7 R6 R5 R4 R3 R2 7 0 R1 R0 0 7 DACxREFH 0 7 0 0 0 0 0 R9 R8 0 0 0 0 0 0 Rev. 10-000 225A 4/29/201 4 DACxREFL R7 R6 R5 R4 R3 R2 R1 R0 7 0 DACxREFH 0 FM = 0 DACxREFL R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 DACxREF FIGURE Notes: 18-2: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Rev. 10-000219B 6/17/2015 DACxREFH DACxREFL 10-bit Latch (not visible to user) Reserved FVR_buffer2 VSOURCE+ write 1 to DACxLD bit VDD VREF+ 10 R PSS<1:0> R 2 EN R 1024 Steps R R Reserved 1024-to-1 MUX R DACx_output To Peripherals DACxOUT1 OE1 DACxOUT2 VREF1-(1) R OE2 VREF0- VSOURCEVSS NSS<1:0> 2 Note 1: DAC5 only, DAC1/2 is Reserved. 2015-2016 Microchip Technology Inc. DS40001819B-page 247 PIC16(L)F1777/8/9 FIGURE 18-3: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC(R) MCU DAC Module R Voltage Reference Output Impedance 18.5 DACXOUTX + - Buffered DAC Output Operation During Sleep When the device wakes up from Sleep as the result of an interrupt or a Watchdog Timer time-out, the contents of the DACxCON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 18.6 Effects of a Reset A device Reset affects the following: * DAC is disabled * DAC output voltage is removed from the DACXOUTX pin * The REF<9:0> reference selection bits are cleared DS40001819B-page 248 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 18.7 Register Definitions: DAC Control Long bit name prefixes for the 10-bit DAC peripherals are shown in Table 18-2. Refer to Section 1.1 "Register and Bit naming conventions" for more information TABLE 18-2: Peripheral Bit Name Prefix DAC1 DAC1 DAC2 DAC2 DAC5 DAC5 DAC6(1) DAC6 Note 1: PIC16(L)F1777/9 only. REGISTER 18-1: DACxCON0: DAC CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 EN FM OE1 OE2 R/W-0/0 R/W-0/0 R/W-0/0 PSS<1:0> bit 7 R/W-0/0 NSS<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 EN: DAC Enable bit 1 = DACx is enabled 0 = DACx is disabled bit 6 FM: DAC Reference Format bit 1 = DACx reference selection is left justified 0 = DACx reference selection is right justified bit 5 OE1: DAC Voltage Output Enable bit 1 = DACx voltage level is also an output on the DACxOUT1 pin 0 = DACx voltage level is disconnected from the DACxOUT1 pin bit 4 OE2: DAC Voltage Output Enable bit 1 = DACx voltage level is also an output on the DACxOUT2 pin 0 = DACx voltage level is disconnected from the DACxOUT2 pin bit 3-2 PSS<1:0>: DAC Positive Source Select bits 11 = DACxREF1+ (DAC5/6) or Reserved (DAC1/2) 10 = FVR_buffer2 01 = DACXREF0+ 00 = VDD bit 1-0 NSS<1:0>: DAC Negative Source Select bit 11 = Reserved. Do not use. 10 = DACxREF1- (DAC5/6) or Reserved (DAC1/2) 01 = DACxREF000 = AGND (AVSS) 2015-2016 Microchip Technology Inc. DS40001819B-page 249 PIC16(L)F1777/8/9 REGISTER 18-2: R/W-0/0 DACxREFH: DAC REFERENCE VOLTAGE SELECT HIGH REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 REF<9:x> (x Depends on FM bit) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared When FM = 1 (left justified) bit 7-0 REF<9:2>: DAC Reference Voltage Output Select bits DACxOUT1 = f(REF<9:0>) (See Equation 18-1) When FM = 0 (right justified) bit 7-2 Unimplemented: Read as `0' bit 1-0 REF<9:8>: DAC Reference Voltage Output Select bits DACxOUT1 = f(REF<9:0>) (See Equation 18-1) REGISTER 18-3: R/W-0/0 DACxREFL: DAC REFERENCE VOLTAGE SELECT LOW REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 REF<x-1:0> (x Depends on FM bit) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared When FM = 1 (left justified) bit 7-6 REF<1:0>: DAC Reference Voltage Output Select bits DACxOUT1 = f(REF<9:0>) (See Equation 18-1) bit 5-0 Unimplemented: Read as `0' When FM = 0 (right justified) bit 7-0 REF<7:0>: DAC Reference Voltage Output Select bits DACxOUT1 = f(REF<9:0>) (See Equation 18-1) DS40001819B-page 250 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 18-4: DACLD: DAC BUFFER LOAD REGISTER U-0 U-0 U-0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 -- -- DAC6LD(1) DAC5LD -- -- DAC2LD DAC1LD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = value depends on configuration bits bit 7-6 Unimplemented: Read as `0' bit 5 DAC6LD: DAC6 Double Buffer Load bit(1) 1 = DAC6REFHL:DAC6REFL values are transfered to the double buffer. Bit is cleared automatically by hardware. 0 = DAC6REFHL:DAC6REFL double buffers remain unchanged. bit 4 DAC5LD: DAC5 Double Buffer Load bit 1 = DAC5REFHL:DAC5REFL values are transfered to the double buffer. Bit is cleared automatically by hardware. 0 = DAC5REFHL:DAC5REFL double buffers remain unchanged. bit 3-2 Unimplemented: Read as `0' bit 1 DAC2LD: DAC2 Double Buffer Load bit 1 = DAC2REFHL:DAC2REFL values are transfered to the double buffer. Bit is cleared automatically by hardware. 0 = DAC2REFHL:DAC2REFL double buffers remain unchanged. bit 0 DAC1LD: DAC1 Double Buffer Load bit 1 = DAC1REFHL:DAC1REFL values are transfered to the double buffer. Bit is cleared automatically by hardware. 0 = DAC1REFHL:DAC1REFL double buffers remain unchanged. PIC16LF1777/9 only. Note 1: TABLE 18-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE DACx MODULE Bit 6 Bit 5 Bit 4 DAC1CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 249 DAC2CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 249 DAC5CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 249 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 249 (1) DAC6CON0 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page Bit 7 DAC1REFH REF<9:x> (x Depends on FM bit) 250 DAC2REFH REF<9:x> (x Depends on FM bit) 250 DAC5REFH REF<9:x> (x Depends on FM bit) 250 (1) REF<9:x> (x Depends on FM bit) 250 DAC1REFL REF<x-1:0> (x Depends on FM bit) 250 DAC2REFL REF<x-1:0> (x Depends on FM bit) 250 DAC5REFL REF<x-1:0> (x Depends on FM bit) 250 DAC6REFH DAC6REFL DACLD Legend: Note 1: (1) REF<x-1:0> (x Depends on FM bit) -- -- -- DAC5LD -- -- 250 DAC2LD DAC1LD 251 -- = Unimplemented location, read as `0'. Shaded cells are not used with the DACx module. PIC16LF1777/9 only. 2015-2016 Microchip Technology Inc. DS40001819B-page 251 PIC16(L)F1777/8/9 19.0 COMPARATOR MODULE FIGURE 19-1: Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution. The analog comparator module includes the following features: * * * * * * * * * Independent comparator control Programmable input selection Comparator output is available internally/externally Programmable output polarity Interrupt-on-change Wake-up from Sleep Programmable Speed/Power optimization PWM shutdown Programmable and Fixed Voltage Reference 19.1 Comparator Overview SINGLE COMPARATOR VIN+ + VIN- - Output VINVIN+ Output Note: The black areas of the output of the comparator represents the uncertainty due to input offsets and response time. A single comparator is shown in Figure 19-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. The comparators available for this device are located in Table 19-1. TABLE 19-1: Device AVAILABLE COMPARATORS C1 C2 C3 C4 C5 C6 C7 C8 PIC16(L)F1778 PIC16(L)F1777/9 DS40001819B-page 252 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 19-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM CxINTP Interrupt det (1) CxON CxNCH<2:0> Set CxIF 3 CxINTN Interrupt det CXPOL MUX See Table 19-4 (2) CxVN - 0 D Cx CxVP (2) 1 EN Q1 CxHYS MUX See Table 19-5 ZLF + to CMXCON0 (CXOUT) and CM2CON1 (MCXOUT) Q CxZLF CxON CXPCH<3:0> CXSYNC 4 RXYPPS TRIS bit CXOUT 0 PPS D From Timer1 tmr1_clk Note 1: 2: Q 1 sync_CxOUT When CxON = 0, the comparator will produce a `0' at the output. When CxON = 0, all multiplexer inputs are disconnected. 2015-2016 Microchip Technology Inc. DS40001819B-page 253 PIC16(L)F1777/8/9 19.2 Comparator Control Each comparator has two control registers: CMxCON0 and CMxCON1. The CMxCON0 register (see Register 19-1) contains Control and Status bits for the following: * * * * * * * Enable Output Output polarity Zero latency filter Speed/Power selection Hysteresis enable Output synchronization The CMxCON1 register (see Register 19-2) contains Control bits for the following: * * * * Interrupt enable Interrupt edge polarity Positive input channel selection Negative input channel selection 19.2.1 19.2.3 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the POL bit of the CMxCON0 register. Clearing the POL bit results in a non-inverted output. Table 19-2 shows the output state versus input conditions, including polarity control. TABLE 19-2: COMPARATOR OUTPUT STATE VS. INPUT CONDITIONS Input Condition CxPOL CxOUT CxVN > CxVP 0 0 CxVN < CxVP 0 1 CxVN > CxVP 1 1 CxVN < CxVP 1 0 COMPARATOR ENABLE Setting the ON bit of the CMxCON0 register enables the comparator for operation. Clearing the ON bit disables the comparator resulting in minimum current consumption. 19.2.2 COMPARATOR OUTPUT SELECTION The output of the comparator can be monitored by reading either the OUT bit of the CMxCON0 register or the MCxOUT bit of the CMOUT register. In order to make the output available for an external connection, the following conditions must be true: * Desired pin PPS control * Corresponding TRIS bit must be cleared * ON bit of the CMxCON0 register must be set Note 1: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. DS40001819B-page 254 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 19.3 Comparator Hysteresis A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the HYS bit of the CMxCON0 register. The associated interrupt flag bit, CxIF bit of the PIR2 register, must be cleared in software. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. Note: See Comparator Specifications in Table 36-19: Comparator Specifications for more information. 19.4 Timer1 Gate Operation The output resulting from a comparator operation can be used as a source for gate control of Timer1. See Section 22.6 "Timer1 Gate" for more information. This feature is useful for timing the duration or interval of an analog event. It is recommended that the comparator output be synchronized to Timer1. This ensures that Timer1 does not increment while a change in the comparator is occurring. 19.4.1 COMPARATOR OUTPUT SYNCHRONIZATION The output from a comparator can be synchronized with Timer1 by setting the SYNC bit of the CMxCON0 register. Once enabled, the comparator output is latched on the falling edge of the Timer1 source clock. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Block Diagram (Figure 19-2) and the Timer1 Block Diagram (Figure 22-1) for more information. 19.5 Comparator Interrupt An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a falling edge detector are present. When either edge detector is triggered and its associated enable bit is set (INTP and/or INTN bits of the CMxCON1 register), the Corresponding Interrupt Flag bit (CxIF bit of the PIR2 register) will be set. 19.6 Although a comparator is disabled, an interrupt can be generated by changing the output polarity with the POL bit of the CMxCON0 register, or by switching the comparator on or off with the ON bit of the CMxCON0 register. Comparator Positive Input Selection Configuring the PCH<3:0> bits of the CMxPSEL register directs an internal voltage reference or an analog pin to the non-inverting input of the comparator: * * * * * CxIN+ analog pin Programmable ramp generator output DAC output FVR (Fixed Voltage Reference) VSS (Ground) See Section 14.0 "Fixed Voltage Reference (FVR)" for more information on the Fixed Voltage Reference module. See Section 17.0 "5-Bit Digital-to-Analog Converter (DAC) Module" for more information on the DAC input signal. Any time the comparator is disabled (CxON = 0), all comparator inputs are disabled. 19.7 Comparator Negative Input Selection The NCH<3:0> bits of the CMxNSEL register direct an analog input pin and internal reference voltage or analog ground to the inverting input of the comparator: * CxIN- pin * FVR (Fixed Voltage Reference) * Analog Ground Some inverting input selections share a pin with the operational amplifier output function. Enabling both functions at the same time will direct the operational amplifier output to the comparator inverting input. To enable the interrupt, you must set the following bits: * ON and POL bits of the CMxCON0 register * CxIE bit of the PIE2 register * INTP bit of the CMxCON1 register (for a rising edge detection) * INTN bit of the CMxCON1 register (for a falling edge detection) * PEIE and GIE bits of the INTCON register 2015-2016 Microchip Technology Inc. Note: To use CxINy+ and CxINy- pins as analog input, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers. DS40001819B-page 255 PIC16(L)F1777/8/9 19.8 Comparator Response Time The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference Specifications in Table 36-19: Comparator Specifications for more details. 19.9 Zero Latency Filter In high-speed operation, and under proper circuit conditions, it is possible for the comparator output to oscillate. This oscillation can have adverse effects on the hardware and software relying on this signal. Therefore, a digital filter has been added to the comparator output to suppress the comparator output oscillation. Once the comparator output changes, the output is prevented from reversing the change for a nominal time of 20 ns. This allows the comparator output to stabilize without affecting other dependent devices. Refer to Figure 19-3. FIGURE 19-3: COMPARATOR ZERO LATENCY FILTER OPERATION CxOUT From Comparator CxOUT From ZLF TZLF Output waiting for TZLF to expire before an output change is allowed. TZLF has expired so output change of ZLF is immediate based on comparator output change. DS40001819B-page 256 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 19.10 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 19-4. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. Note 1: When reading a PORT register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. FIGURE 19-4: ANALOG INPUT MODEL Rev. 10-000071A 8/2/2013 VDD RS < 10K Analog Input pin VT 0.6V RIC To Comparator ILEAKAGE(1) CPIN 5pF VA VT 0.6V VSS Legend: CPIN ILEAKAGE RIC RS VA VT = Input Capacitance = Leakage Current at the pin due to various junctions = Interconnect Resistance = Source Impedance = Analog Voltage = Threshold Voltage Note 1: See I/O Ports in Table 36-4: I/O Ports. 2015-2016 Microchip Technology Inc. DS40001819B-page 257 PIC16(L)F1777/8/9 19.11 Register Definitions: Comparator Control Long bit name prefixes for the Comparator peripherals are shown in Table 19-3. Refer to Section 1.1.2.2 "Long Bit Names" for more information TABLE 19-3: Peripheral Bit Name Prefix Comparator 1 C1 Comparator 2 C2 Comparator 3 C3 Comparator 4 C4 Comparator 5 C5 Comparator 6 C6 (1) C7 Comparator 8(1) C8 Comparator 7 Note 1: PIC16(L)F1777/9 only. REGISTER 19-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0 R/W-0/0 R-0/0 U-0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-0/0 ON OUT -- POL ZLF -- HYS SYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 ON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled and consumes no active power bit 6 OUT: Comparator Output bit If POL = 1 (inverted polarity): 1 = CxVP < CxVN 0 = CxVP > CxVN If POL = 0 (non-inverted polarity): 1 = CxVP > CxVN 0 = CxVP < CxVN bit 5 Reserved: Read as `1'. Maintain this bit set. bit 4 POL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 3 ZLF: Comparator Zero Latency Filter Enable bit 1 = Comparator output is filtered 0 = Comparator output is unfiltered bit 2 Reserved: Read as `1'. Maintain this bit set. bit 1 HYS: Comparator Hysteresis Enable bit 1 = Comparator hysteresis enabled 0 = Comparator hysteresis disabled bit 0 SYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source. 0 = Comparator output to Timer1 and I/O pin is asynchronous DS40001819B-page 258 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 19-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 -- -- -- -- -- -- INTP INTN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-2 Unimplemented: Read as `0' bit 1 INTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit 0 = No interrupt flag will be set on a positive going edge of the CxOUT bit bit 0 INTN: Comparator Interrupt on Negative Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit 0 = No interrupt flag will be set on a negative going edge of the CxOUT bit 2015-2016 Microchip Technology Inc. DS40001819B-page 259 PIC16(L)F1777/8/9 REGISTER 19-3: CMxNSEL: COMPARATOR Cx NEGATIVE CHANNEL SELECT REGISTER U-0 U-0 U-0 U-0 -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NCH<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3-0 NCH<3:0>: Comparator Negative Input Channel Select bits CxVN connects to input source indicated by Table 19-4: Negative Input Sources TABLE 19-4: NEGATIVE INPUT SOURCES NCH<3:0> C1, C2, C3, C4 C5, C6, C7(1), C8(1) 1111 Reserved. Do not use Reserved. Do not use 1110 Reserved. Do not use Reserved. Do not use 1101 Reserved. Do not use Reserved. Do not use 1100 Reserved. Do not use Reserved. Do not use 1011 Reserved. Do not use Reserved. Do not use 1010 OPA2IN- pin OPA4IN- pin(1) 1001 OPA1IN- pin OPA3IN- pin 1000 AGND AGND 0111 PRG2_out PRG4_out(1) 0110 PRG1_out PRG3_out 0101 FVR_Buffer2 FVR_Buffer2 0100 CxIN4- pin CxIN4- (OPA4OUT) pin(1) 0011 CxIN3- (OPA2OUT) pin CxIN3- pin 0010 CxIN2- pin CxIN2- pin 0001 CxIN1- (OPA1OUT) pin CxIN1- (OPA3OUT) pin 0000 CxIN0- pin CxIN0- pin Note 1: PIC16(L)F1777/9 only. DS40001819B-page 260 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 19-4: U-0 CMxPSEL: COMPARATOR Cx POSITIVE CHANNEL SELECT REGISTER 1 U-0 -- U-0 -- U-0 -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PCH<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3-0 PCH<3:0>: Comparator Positive Input Channel Select bits CxVP connects to input source indicated by Table 19-5: Positive Input Sources TABLE 19-5: POSITIVE INPUT SOURCES PCH<3:0> C1, C2, C3, C4 C5, C6, C7(1), C8(1) 1111 Reserved. Do not use Reserved. Do not use 1110 Reserved. Do not use Reserved. Do not use 1101 Reserved. Do not use Reserved. Do not use 1100 Reserved. Do not use Reserved. Do not use 1011 Reserved. Do not use Reserved. Do not use 1010 Reserved. Do not use Reserved. Do not use 1001 AGND AGND 1000 DAC4_out DAC8_out(1) 0111 DAC3_out DAC7_out 0110 DAC2_out DAC6_out(1) 0101 DAC1_out DAC5_out 0100 PRG2_out PRG4_out(1) 0011 PRG1_out PRG3_out 0010 FVR_Buffer2 FVR_Buffer2 0001 CxIN1+ pin CxIN1+ pin 0000 CxIN0+ pin CxIN0+ pin Note 1: PIC16(L)F1777/9 only. 2015-2016 Microchip Technology Inc. DS40001819B-page 261 PIC16(L)F1777/8/9 Note: There are no long and short bit name variants for the following mirror register REGISTER 19-5: R-0/0 MC8OUT CMOUT: COMPARATOR OUTPUT REGISTER R-0/0 (1) MC7OUT (1) R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 MC6OUT MC5OUT MC4OUT MC3OUT MC2OUT MC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 MC8OUT: Mirror Copy of C8OUT bit(1) bit 6 MC7OUT: Mirror Copy of C7OUT bit(1) bit 5 MC6OUT: Mirror Copy of C6OUT bit bit 4 MC5OUT: Mirror Copy of C5OUT bit bit 3 MC4OUT: Mirror Copy of C4OUT bit bit 2 MC3OUT: Mirror Copy of C3OUT bit bit 1 MC2OUT: Mirror Copy of C2OUT bit bit 0 MC1OUT: Mirror Copy of C1OUT bit Note 1: PIC16LF1777/9 only. DS40001819B-page 262 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 19-6: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA -- -- ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177 ANSELB -- -- ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 -- -- 187 CM1CON0 ON OUT -- POL ZLF Reserved HYS SYNC 258 CM2CON0 ON OUT -- POL ZLF Reserved HYS SYNC 258 CM3CON0 ON OUT -- POL ZLF Reserved HYS SYNC 258 CM4CON0 ON OUT -- POL ZLF Reserved HYS SYNC 258 CM5CON0 ON OUT -- POL ZLF Reserved HYS SYNC 258 CM6CON0 ON OUT -- POL ZLF Reserved HYS SYNC 258 CM1CON1 -- -- -- -- -- -- INTP INTN 259 CM2CON1 -- -- -- -- -- -- INTP INTN 259 CM3CON1 -- -- -- -- -- -- INTP INTN 259 CM4CON1 -- -- -- -- -- -- INTP INTN 259 CM5CON1 -- -- -- -- -- -- INTP INTN 259 CM6CON1 -- -- -- -- -- -- INTP INTN 259 CM7CON1(1) -- -- -- -- -- -- INTP INTN 259 CM8CON1(1) -- -- -- -- -- -- INTP INTN CM1NSEL -- -- -- -- NCH<3:0> 260 CM2NSEL -- -- -- -- NCH<3:0> 260 CM3NSEL -- -- -- -- NCH<3:0> 260 CM4NSEL -- -- -- -- NCH<3:0> 260 CM5NSEL -- -- -- -- NCH<3:0> 260 CM6NSEL -- -- -- -- NCH<3:0> 260 CM7NSEL(1) -- -- -- -- NCH<3:0> 260 (1) CM8NSEL -- -- -- -- NCH<3:0> 260 CM1PSEL -- -- -- -- PCH<3:0> 261 CM2PSEL -- -- -- -- PCH<3:0> 261 CM3PSEL -- -- -- -- PCH<3:0> 261 CM4PSEL -- -- -- -- PCH<3:0> 261 CM5PSEL -- -- -- -- PCH<3:0> 261 CM6PSEL -- -- -- -- PCH<3:0> 261 CM7PSEL(1) -- -- -- -- PCH<3:0> 261 Name CM8PSEL(1) -- -- -- -- CMOUT MC8OUT(1) MC7OUT(1) MC6OUT MC5OUT FVRCON PCH<3:0> MC4OUT MC3OUT 259 261 MC2OUT MC1OUT 262 FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 223 DAC1CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 249 DAC2CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 249 DAC5CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 249 DAC6CON0(1) EN FM OE1 OE2 PSS<1:0> NSS<1:0> 249 DAC3CON0 EN -- OE1 OE2 PSS<1:0> NSS<1:0> 244 244 DAC4CON0 EN -- OE1 OE2 PSS<1:0> NSS<1:0> DAC7CON0 EN -- OE1 OE2 PSS<1:0> NSS<1:0> 244 DAC8CON0(1) EN -- OE1 OE2 PSS<1:0> NSS<1:0> 244 DAC3REF --- --- --- REF<4:0> 245 DAC4REF --- --- --- REF<4:0> 245 DAC7REF --- --- --- REF<4:0> 245 DAC8REF(1) --- --- --- REF<4:0> 245 DAC1REFH Legend: Note 1: REF<9:x> (x Depends on FM bit) 250 -- = unimplemented location, read as `0'. Shaded cells are unused by the comparator module. PIC16LF1777/9 only. 2015-2016 Microchip Technology Inc. DS40001819B-page 263 PIC16(L)F1777/8/9 TABLE 19-4: Name SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE (CONT.) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page DAC2REFH REF<9:x> (x Depends on FM bit) DAC5REFH REF<9:x> (x Depends on FM bit) 250 DAC6REFH(1) REF<9:x> (x Depends on FM bit) 250 DAC1REFL REF<x-1:0> (x Depends on FM bit) 250 DAC2REFL REF<x-1:0> (x Depends on FM bit) 250 DAC5REFL REF<x-1:0> (x Depends on FM bit) 250 DAC6REFL(1) INTCON PIE2 250 REF<x-1:0> (x Depends on FM bit) GIE OSFIE (1) 250 PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132 C2IE C1IE COG1IE BCL1IE C4IE C3IE CCP2IE 134 (1) PIE5 CCP8IE COG3IE C8IE C6IE C5IE 137 OSFIF C2IF C1IF COG1IF BCL1IF C4IF C3IF CCP2IF 140 PIR5 CCP8IF(1) CCP7IF COG4IF(1) COG3IF C8IF(1) C7IF(1) C6IF C5IF 143 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186 Legend: Note 1: COG4IE (1) PIR2 TRISC CCP7IE (1) C7IE -- = unimplemented location, read as `0'. Shaded cells are unused by the comparator module. PIC16LF1777/9 only. DS40001819B-page 264 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 20.0 ZERO-CROSS DETECTION (ZCD) MODULE 20.1 The ZCD module detects when an A/C signal crosses through the ground potential. The actual zero-crossing threshold is the zero-crossing reference voltage, ZCPINV, which is typically 0.75V above ground. The connection to the signal to be detected is through a series current limiting resistor. The module applies a current source or sink to the ZCD pin to maintain a constant voltage on the pin, thereby preventing the pin voltage from forward biasing the ESD protection diodes. When the applied voltage is greater than the reference voltage, the module sinks current. When the applied voltage is less than the reference voltage, the module sources current. The current source and sink action keeps the pin voltage constant over the full range of the applied voltage. The ZCD module is shown in the simplified block diagram Figure 20-2. The ZCD module requires a current limiting resistor in series with the external voltage source. The impedance and rating of this resistor depends on the external source peak voltage. Select a resistor value that will drop all of the peak voltage when the current through the resistor is nominally 300 A. Refer to Equation 20-1 and Figure 20-1. Make sure that the ZCD I/O pin internal weak pull-up is disabled so it does not interfere with the current source and sink. EQUATION 20-1: R EXTERNAL RESISTOR Vpeak = -----------------series -4 3 10 FIGURE 20-1: The ZCD module is useful when monitoring an AC waveform for, but not limited to, the following purposes: * * * * External Resistor Selection EXTERNAL VOLTAGE maxpeak minpeak Vpeak A/C period measurement Accurate long term time measurement Dimmer phase delayed drive Low EMI cycle switching FIGURE 20-2: ZCPINV SIMPLIFIED ZCD BLOCK DIAGRAM optional VDD Vpullup Rpullup External current limiting resistor ZCPINV + Rseries ZCD pin Rpulldown optional External voltage source ZCDx_output D POL Q1 Q OUT LE Interrupt det INTP Sets ZCDIF flag INTN Interrupt det 2015-2016 Microchip Technology Inc. DS40001819B-page 265 PIC16(L)F1777/8/9 20.2 ZCD Logic Output 20.5 Correcting for ZCPINV Offset The ZCD module includes a Status bit, which can be read to determine whether the current source or sink is active. The OUT bit of the ZCDCON register is set when the current sink is active, and cleared when the current source is active. The OUT bit is affected by the polarity bit. The actual voltage at which the ZCD switches is the reference voltage at the non-inverting input of the ZCD op amp. For external voltage source waveforms other than square waves this voltage offset from zero causes the zero-cross event to occur either too early or too late. 20.3 20.5.1 ZCD Logic Polarity The POL bit of the ZCDxCON register inverts the OUT bit relative to the current source and sink output. When the POL bit is set, a OUT high indicates that the current source is active, and a low output indicates that the current sink is active. The POL bit affects the ZCD interrupts. See Section 20.4 "ZCD Interrupts". 20.4 ZCD Interrupts An interrupt will be generated upon a change in the ZCD logic output when the appropriate interrupt enables are set. A rising edge detector and a falling edge detector are present in the ZCD for this purpose. The ZCDIF bit of the PIR3 register will be set when either edge detector is triggered and its associated enable bit is set. The INTP enables rising edge interrupts and the INTN bit enables falling edge interrupts. Both are located in the ZCDxCON register. CORRECTION BY AC COUPLING When the external voltage source is sinusoidal, the effects of the ZCPINV offset can be eliminated by isolating the external voltage source from the ZCD pin with a capacitor in addition to the voltage reducing resistor. The capacitor will cause a phase shift resulting in the ZCD output switch in advance of the actual zero-crossing event. The phase shift will be the same for both rising and falling zero crossings, which can be compensated for by either delaying the CPU response to the ZCD switch by a timer or other means, or selecting a capacitor value large enough that the phase shift is negligible. To determine the series resistor and capacitor values for this configuration, start by computing the impedance, Z, to obtain a peak current of 300 A. Next, arbitrarily select a suitably large non-polar capacitor and compute its reactance, XC, at the external voltage source frequency. Finally, compute the series resistor, capacitor peak voltage, and phase shift by the formulas shown in Equation 20-2. To fully enable the interrupt, the following bits must be set: * ZCDIE bit of the PIE3 register * INTP bit of the ZCDxCON register (for a rising edge detection) * INTN bit of the ZCDxCON register (for a falling edge detection) * PEIE and GIE bits of the INTCON register Changing the POL bit will cause an interrupt, regardless of the level of the EN bit. The ZCDIF bit of the PIR3 register must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. DS40001819B-page 266 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 EQUATION 20-2: R-C CALCULATIONS Vpeak = external voltage source peak voltage EQUATION 20-3: V peak = V rms 2 = 169.7 f = external voltage source frequency C = series capacitor R = series resistor f = 60 Hz VC = Peak capacitor voltage C = 0.1 f = Capacitor induced zero crossing phase advance in radians T = Time ZC event occurs before actual zero crossing V peak 169.7 Z = ------------------- = ------------------- = 565.7 kOhms -4 -4 3 10 3 10 1 1 XC = ----------------- = -------------------------------------------- = 26.53 kOhms 2fC 2 60 1 10 - 7 VP E A K Z = ----------------4 3x10 R 1 X C = ---------------- 2fC R = R-C CALCULATIONS EXAMPLE 2 Z - XC -4 V C = X C 3x10 -1 X C = Tan ------ R T = ------------ 2f Vrms = 120 2015-2016 Microchip Technology Inc. = 560 kOhms ZR = 2 R + X c 2 = 560.6 kOhm using actual resistor Vpeak -6 I peak = ------------- = 302.7 10 ZR V C = X C I peak = 8.0 V -1 X C = Tan ------ = 0.047 radians R T = ------------- = 125.6 s 2f DS40001819B-page 267 PIC16(L)F1777/8/9 20.5.2 CORRECTION BY OFFSET CURRENT When the waveform is varying relative to Vss then the zero cross is detected too early as the waveform falls and too late as the waveform rises. When the waveform is varying relative to VDD then the zero cross is detected too late as the waveform rises and too early as the waveform falls. The actual offset time can be determined for sinusoidal waveforms with the corresponding equations shown in Equation 20-4. EQUATION 20-4: ZCD EVENT OFFSET The pull-up and pull-down resistor values are significantly affected by small variations of ZCPINV. Measuring ZCPINV can be difficult, especially when the waveform is relative to VDD. However, by combining Equation 20-4 and Equation 20-5 the resistor value can be determined from the time difference between the ZCDOUT high and low periods. Note that the time difference, T, is 4*Toffset. The equation for determining the pull-up and pull-down resistor values from the high and low ZCDOUT periods is shown in Equation 20-6. The ZCDOUT signal can be directly observed on a pin by routing the ZCDOUT signal through one of the CLCs. When External Voltage Source is relative to Vss: EQUATION 20-6: Z cpinv asin ----------------- V peak T offset = ---------------------------------2 Freq When External Voltage Source is relative to VDD: V DD - Z cpinv asin -------------------------------- V peak T = ------------------------------------------------offset 2 Freq This offset time can be compensated for by adding a pull-up or pull-down biasing resistor to the ZCD pin. A pull-up resistor is used when the external voltage source is varying relative to Vss. A pull-down resistor is used when the voltage is varying relative to VDD.The resistor adds a bias to the ZCD pin so that the target external voltage source must go to zero to pull the pin voltage to the ZCPINV switching voltage. The pull-up or pull-down value can be determined with the equations shown in Equation 20-5. EQUATION 20-5: ZCD PULL-UP/DOWN When External Signal is relative to Vss: R V -Z series pullup cpinv Rpullup = --------------------------------------------------------------------Z cpinv When External Signal is relative to VDD: R Z series cpinv Rpulldown = ----------------------------------------- V DD - Z cpinv DS40001819B-page 268 R = R V bias ---------------------------------------------------------------- - 1 series T Vpeak sin Freq ---------- 2 R is pull-up or pull-down resistor Vbias is Vpullup when R is pull-up or VDD when R is pull-down T is the ZCDOUT high and low period difference 20.6 Handling Vpeak variations If the peak amplitude of the external voltage is expected to vary then the series resistor must be selected to keep the ZCD current source and sink below the design maximum range of 600 A for the maximum expected voltage and high enough to be detected accurately at the minimum peak voltage. A general rule of thumb is that the maximum peak voltage can be no more than six times the minimum peak voltage. To ensure that the maximum current does not exceed 600 A and the minimum is at least 100 A, compute the series resistance as shown in Equation 20-7. The compensating pull-up for this series resistance can be determined with Equation 20-5 because the pull-up value is independent from the peak voltage. EQUATION 20-7: R series SERIES R FOR V RANGE V maxpeak + V minpeak = ------------------------------------------------------------4 7 10 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 20.7 Operation During Sleep The ZCD current sources and interrupts are unaffected by Sleep. 20.8 Effects of a Reset The ZCD circuit can be configured to default to the active or inactive state on Power-on-Reset (POR). When the ZCD Configuration bit is cleared, the ZCD circuit will be active at POR. When the ZCD Configuration bit is set, the ZCDEN bit of the ZCDCON register must be set to enable the ZCD module. 2015-2016 Microchip Technology Inc. DS40001819B-page 269 PIC16(L)F1777/8/9 20.9 Register Definitions: ZCD Control Long bit name prefixes for the zero-cross detect peripheral is shown in Table 20-1. Refer to 1.1.2.2 "Long Bit Names" for more information TABLE 20-1: Peripheral Bit Name Prefix ZCD1 ZCD1 REGISTER 20-1: ZCDxCON: ZERO-CROSS DETECTION CONTROL REGISTER R/W-0/0 U-0 R-x/x R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 EN -- OUT POL -- -- INTP INTN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = value depends on configuration bits bit 7 EN: Zero-Cross Detection Enable bit(1) 1 = Zero-cross detect is enabled. ZCD pin is forced to output to source and sink current. 0 = Zero-cross detect is disabled. ZCD pin operates according to PPS and TRIS controls. bit 6 Unimplemented: Read as `0' bit 5 OUT: Zero-Cross Detection Logic Level bit POL bit = 0: 1 = ZCD pin is sinking current 0 = ZCD pin is sourcing current POL bit = 1: 1 = ZCD pin is sourcing current 0 = ZCD pin is sinking current bit 4 POL: Zero-Cross Detection Logic Output Polarity bit 1 = ZCD logic output is inverted 0 = ZCD logic output is not inverted bit 3-2 Unimplemented: Read as `0' bit 1 INTP: Zero-Cross Positive Edge Interrupt Enable bit 1 = ZCDIF bit is set on low-to-high OUT transition 0 = ZCDIF bit is unaffected by low-to-high OUT transition bit 0 INTN: Zero-Cross Negative Edge Interrupt Enable bit 1 = ZCDIF bit is set on high-to-low OUT transition 0 = ZCDIF bit is unaffected by high-to-low OUT transition Note 1: The EN bit has no effect when the ZCD Configuration bit is cleared. DS40001819B-page 270 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 20-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE ZCD MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page PIE3 -- -- COG2IE ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE 135 PIR3 -- -- COG2IF ZCDIF CLC4IF CLC3IF CLC2IF CLC1IF 141 ZCD1CON EN -- OUT POL -- -- INTP INTN 270 Name Legend: -- = unimplemented, read as `0'. Shaded cells are unused by the ZCD module. TABLE 20-3: Name Bits CONFIG2 13:8 7:0 SUMMARY OF CONFIGURATION WORD WITH THE ZCD MODULE Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register on Page -- -- LVP DEBUG LPBOR BORV STVREN PLLEN 97 ZCD -- -- -- -- PPS1WAY WRT<1:0> Legend: -- = unimplemented location, read as `0'. Shaded cells are not used by the ZCD module. 2015-2016 Microchip Technology Inc. DS40001819B-page 271 PIC16(L)F1777/8/9 21.0 21.1.2 TIMER0 MODULE 8-BIT COUNTER MODE The Timer0 module is an 8-bit timer/counter with the following features: In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. * * * * * * 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to `1'. 8-bit timer/counter register (TMR0) 8-bit prescaler (independent of Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt-on-overflow TMR0 can be used to gate Timer1 The rising or falling transition of the incrementing edge for either input source is determined by the TMR0SE bit in the OPTION_REG register. Figure 21-1 is a block diagram of the Timer0 module. 21.1 Timer0 Operation The Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 21.1.1 8-BIT TIMER MODE The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-bit Timer mode is selected by clearing the TMR0CS bit of the OPTION_REG register. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. Note: FIGURE 21-1: BLOCK DIAGRAM OF THE TIMER0 FOSC/4 Data Bus T0CKIPPS 0 8 T0CKI Set TMR0IF 1 PPS Sync 2 TCY 1 TMR0 Timer0 overflow 0 TMR0SE TMR0CS 8-bit Prescaler PSA 8 PS<2:0> DS40001819B-page 272 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 21.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be disabled by setting the PSA bit of the OPTION_REG register. The prescaler is not readable or writable. All instructions writing to the TMR0 register will clear the prescaler. 21.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register. Note: 21.1.5 The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. 8-BIT COUNTER MODE SYNCHRONIZATION When in 8-Bit Counter mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Table 36-12: Timer0 and Timer1 External Clock Requirements. 21.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. 2015-2016 Microchip Technology Inc. DS40001819B-page 273 PIC16(L)F1777/8/9 21.2 Register Definitions: Option Register REGISTER 21-1: OPTION_REG: OPTION REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUEN INTEDG TMR0CS TMR0SE PSA R/W-1/1 R/W-1/1 R/W-1/1 PS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 WPUEN: Weak Pull-Up Enable bit 1 = All weak pull-ups are disabled (except MCLR, if it is enabled) 0 = Weak pull-ups are enabled by individual WPUx latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 TMR0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 TMR0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is not assigned to the Timer0 module 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits TABLE 21-1: Name INTCON TRISA Timer0 Rate 000 001 010 011 100 101 110 111 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Bit 7 GIE OPTION_REG WPUEN TMR0 Bit Value Bit 6 PEIE INTEDG Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE IOCIE TMR0IF TMR0CS TMR0SE PSA Bit 1 Bit 0 INTF IOCIF PS<2:0> TRISA6 TRISA5 132 274 Timer0 Module Register TRISA7 Register on Page 272* TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176 Legend: -- = Unimplemented location, read as `0'. Shaded cells are not used by the Timer0 module. * Page provides register information. DS40001819B-page 274 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 22.0 * * * * * TIMER1/3/5 MODULE WITH GATE CONTROL The Timer1 module is a 16-bit timer/counter with the following features: * * * * * * * * 16-bit timer/counter register pair (TMR1H:TMR1L) Programmable internal or external clock source 2-bit prescaler Dedicated 32 kHz oscillator circuit Optionally synchronized comparator out Multiple Timer1 gate (count enable) sources Interrupt-on-overflow Wake-up on overflow (external clock, Asynchronous mode only) * Time base for the Capture/Compare function * Auto-conversion Trigger (with CCP) FIGURE 22-1: Selectable Gate Source Polarity Gate Toggle mode Gate Single-pulse mode Gate Value Status Gate Event Interrupt Figure 22-1 is a block diagram of the Timer1 module. This device has three instances of Timer1 type modules. They include: * Timer1 * Timer3 * Timer5 All references to Timer1 and Timer1 Gate apply to Timer3 and Timer5. Note: TIMER1 BLOCK DIAGRAM T1GSS<1:0> T1GPPS PPS 00 Timer0 overflow 01 T1G T1GSPM 0 t1g_in T1GVAL 0 sync_C1OUT 10 sync_C2OUT 11 Single-Pulse D Q CK Q R TMR1ON 1 Acq. Control 1 Q1 Data Bus D Q RD T1GCON EN Interrupt T1GGO/DONE Set TMR1GIF det T1GTM T1GPOL TMR1GE Set flag bit TMR1IF on Overflow To ADC Auto-Conversion TMR1ON To Comparator Module TMR1(2) TMR1H EN TMR1L Q D T1CLK Synchronized clock input 0 1 TMR1CS<1:0> SOSCO LFINTOSC SOSC SOSCI Synchronize(3) Prescaler 1, 2, 4, 8 det 10 EN T1OSCEN T1CKIPPS (1) PPS 11 1 0 T1CKI T1SYNC OUT FOSC Internal Clock 01 FOSC/4 Internal Clock 00 2 T1CKPS<1:0> FOSC/2 Internal Clock Sleep input To Clock Switching Modules Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2015-2016 Microchip Technology Inc. DS40001819B-page 275 PIC16(L)F1777/8/9 22.1 Timer1 Operation 22.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. Timer1 is enabled by configuring the ON and GE bits in the T1CON and T1GCON registers, respectively. Table 22-1 displays the Timer1 enable selections. TABLE 22-1: TIMER1 ENABLE SELECTIONS Clock Source Selection The CS<1:0> and OSCEN bits of the T1CON register are used to select the clock source for Timer1. Table 22-2 displays the clock source selections. 22.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected, the TMR1H:TMR1L register pair will increment on multiples of FOSC as determined by the Timer1 prescaler. When the FOSC internal clock source is selected, the Timer1 register value will increment by four counts every instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the Timer1 value. To utilize the full resolution of Timer1, an asynchronous input signal must be used to gate the Timer1 clock input. The following asynchronous sources may be used: Timer1 Operation TMR1ON TMR1GE 0 0 Off 0 1 Off 1 0 Always On 1 1 Count Enabled * Asynchronous event on the T1G pin to Timer1 gate * C1 or C2 comparator input to Timer1 gate 22.2.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. When enabled to count, Timer1 is incremented on the rising edge of the external clock input T1CKI, which can be synchronized to the microcontroller system clock or can run asynchronously. When used as a timer with a clock oscillator, an external 32.768 kHz crystal can be used in conjunction with the dedicated internal oscillator circuit. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: * * * * TABLE 22-2: TMR1CS<1:0> Timer1 enabled after POR Write to TMR1H or TMR1L Timer1 is disabled Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. CLOCK SOURCE SELECTIONS T1OSCEN Clock Source 11 x LFINTOSC 10 0 External Clocking on T1CKI Pin 01 x System Clock (FOSC) 00 x Instruction Clock (FOSC/4) DS40001819B-page 276 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 22.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 22.4 Timer1 (Secondary) Oscillator 22.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. A dedicated low-power 32.768 kHz oscillator circuit is built-in between pins SOSCI (input) and SOSCO (amplifier output). This internal circuit is to be used in conjunction with an external 32.768 kHz crystal. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. The oscillator circuit is enabled by setting the OSCEN bit of the T1CON register. The oscillator will continue to run during Sleep. 22.6 Note: 22.5 The oscillator requires a start-up and stabilization time before use. Thus, OSCEN should be set and a suitable delay observed prior to using Timer1. A suitable delay similar to the OST delay can be implemented in software by clearing the TMR1IF bit then presetting the TMR1H:TMR1L register pair to FC00h. The TMR1IF flag will be set when 1024 clock cycles have elapsed, thereby indicating that the oscillator is running and reasonably stable. Timer1 Operation in Asynchronous Counter Mode If the control bit SYNC of the T1CON register is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If the external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt-on-overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 22.5.1 "Reading and Writing Timer1 in Asynchronous Counter Mode"). Note: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment. 2015-2016 Microchip Technology Inc. Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry. This is also referred to as Timer1 Gate Enable. Timer1 gate can also be driven by multiple selectable sources. 22.6.1 TIMER1 GATE ENABLE The Timer1 Gate Enable mode is enabled by setting the GE bit of the T1GCON register. The polarity of the Timer1 Gate Enable mode is configured using the GPOL bit of the T1GCON register. When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock source. When Timer1 Gate Enable mode is disabled, no incrementing will occur and Timer1 will hold the current count. See Figure 22-3 for timing details. TABLE 22-3: TIMER1 GATE ENABLE SELECTIONS T1CLK T1GPOL T1G Timer1 Operation 1 1 Counts 1 0 Holds Count 0 1 Holds Count 0 0 Counts DS40001819B-page 277 PIC16(L)F1777/8/9 22.6.2 TIMER1 GATE SOURCE SELECTION Timer1 gate source selections are shown in Table 22-4. Source selection is controlled by the T1GSS bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register. TABLE 22-4: T1GSS TIMER1 GATE SOURCES Timer1 Gate Source 11 Comparator 2 Output sync_C2OUT (optionally Timer1 synchronized output) 10 Comparator 1 Output sync_C1OUT (optionally Timer1 synchronized output) 01 Overflow of Timer0 (TMR0 increments from FFh to 00h) 00 Timer1 Gate Pin 22.6.2.1 T1G Pin Gate Operation The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry. 22.6.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. 22.6.2.3 Comparator C1 Gate Operation The output resulting from a Comparator 1 operation can be selected as a source for Timer1 gate control. The Comparator 1 output (sync_C1OUT) can be synchronized to the Timer1 clock or left asynchronous. For more information see Section 19.4.1 "Comparator Output Synchronization". 22.6.2.4 Comparator C2 Gate Operation The output resulting from a Comparator 2 operation can be selected as a source for Timer1 gate control. The Comparator 2 output (sync_C2OUT) can be synchronized to the Timer1 clock or left asynchronous. For more information see Section 19.4.1 "Comparator Output Synchronization". 22.6.3 TIMER1 GATE TOGGLE MODE When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse. Timer1 Gate Toggle mode is enabled by setting the T1GTM bit of the T1GCON register. When the T1GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. Note: 22.6.4 Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation. TIMER1 GATE SINGLE-PULSE MODE When Timer1 Gate Single-Pulse mode is enabled, it is possible to capture a single-pulse gate event. Timer1 Gate Single-Pulse mode is first enabled by setting the T1GSPM bit in the T1GCON register. Next, the T1GGO/DONE bit in the T1GCON register must be set. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the T1GGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1 until the T1GGO/DONE bit is once again set in software. See Figure 22-5 for timing details. If the Single-Pulse Gate mode is disabled by clearing the T1GSPM bit in the T1GCON register, the T1GGO/DONE bit should also be cleared. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1 gate source to be measured. See Figure 22-6 for timing details. 22.6.5 TIMER1 GATE VALUE STATUS When Timer1 Gate Value Status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the T1GVAL bit in the T1GCON register. The T1GVAL bit is valid even when the Timer1 gate is not enabled (TMR1GE bit is cleared). 22.6.6 TIMER1 GATE EVENT INTERRUPT When Timer1 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of T1GVAL occurs, the TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 gate is not enabled (TMR1GE bit is cleared). The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 22-4 for timing details. DS40001819B-page 278 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 22.7 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt-on-rollover, you must set these bits: * * * * ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. The TMR1H:TMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts. Note: 22.8 Timer1 Operation During Sleep Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: * * * * * * ON bit of the T1CON register must be set TMR1IE bit of the PIE1 register must be set PEIE bit of the INTCON register must be set SYNC bit of the T1CON register must be set CS bits of the T1CON register must be configured OSCEN bit of the T1CON register must be configured The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine. 22.9 CCP Capture/Compare Time Base The CCP modules use the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event. In Compare mode, an event is triggered when the value in the CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be an Auto-conversion Trigger. For more information, see "Capture/Compare/PWM Modules". Section 24.0 22.10 CCP Auto-Conversion Trigger When any of the CCP's are configured to trigger an auto-conversion, the trigger will clear the TMR1H:TMR1L register pair. This auto-conversion does not cause a Timer1 interrupt. The CCP module may still be configured to generate a CCP interrupt. In this mode of operation, the CCPR1H:CCPR1L register pair becomes the period register for Timer1. Timer1 should be synchronized and FOSC/4 should be selected as the clock source in order to utilize the Auto-conversion Trigger. Asynchronous operation of Timer1 can cause an Auto-conversion Trigger to be missed. In the event that a write to TMR1H or TMR1L coincides with an Auto-conversion Trigger from the CCP, the write will take precedence. For more information, see Section 24.2.1 "Auto-Conversion Trigger". Secondary oscillator will continue to operate in Sleep regardless of the SYNC bit setting. FIGURE 22-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2015-2016 Microchip Technology Inc. DS40001819B-page 279 PIC16(L)F1777/8/9 FIGURE 22-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N FIGURE 22-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 N DS40001819B-page 280 N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 22-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF N Cleared by software 2015-2016 Microchip Technology Inc. N+1 N+2 Set by hardware on falling edge of T1GVAL Cleared by software DS40001819B-page 281 PIC16(L)F1777/8/9 FIGURE 22-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF DS40001819B-page 282 N Cleared by software N+1 N+2 N+3 N+4 Set by hardware on falling edge of T1GVAL Cleared by software 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 22.11 Register Definitions: Timer1 Control Long bit name prefixes for the Timer1 peripherals are shown in Table 22-5. Refer to Section 1.1.2.2 "Long Bit Names" for more information TABLE 22-5: Peripheral Bit Name Prefix Timer1 T1 Timer3 T3 Timer5 T5 REGISTER 22-1: R/W-0/u T1CON: TIMER1 CONTROL REGISTER R/W-0/u R/W-0/u CS<1:0> R/W-0/u CKPS<1:0> R/W-0/u (1) OSCEN R/W-0/u U-0 R/W-0/u SYNC -- ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 CS<1:0>: Timer1 Clock Source Select bits 11 = LFINTOSC 10 = Timer1 clock source is pin or oscillator:(1) If T1OSCEN = 0: External clock from T1CKI pin (on the rising edge) If T1OSCEN = 1: Crystal oscillator on SOSCI/SOSCO pins 01 = Timer1 clock source is system clock (FOSC) 00 = Timer1 clock source is instruction clock (FOSC/4) bit 5-4 CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 OSCEN: LP Oscillator Enable Control bit(1) 1 = Dedicated secondary oscillator circuit enabled 0 = Dedicated secondary oscillator circuit disabled bit 2 SYNC: Timer1 Synchronization Control bit 1 = Do not synchronize asynchronous clock input 0 = Synchronize asynchronous clock input with system clock (FOSC) bit 1 Unimplemented: Read as `0' bit 0 ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 and clears Timer1 gate flip-flop Note 1: Timer1 only. Reserved, do not use for Timer3 and Timer5. 2015-2016 Microchip Technology Inc. DS40001819B-page 283 PIC16(L)F1777/8/9 REGISTER 22-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x GE GPOL GTM GSPM GGO/ DONE GVAL R/W-0/u R/W-0/u GSS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Bit is cleared by hardware bit 7 GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function bit 6 GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 5 GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1 gate flip-flop toggles on every rising edge. bit 4 GSPM: Timer1 Gate Single-Pulse Mode bit 1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 Gate Single-Pulse mode is disabled bit 3 GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started bit 2 GVAL: Timer1 Gate Value Status bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L Unaffected by Timer1 Gate Enable (TMR1GE) bit 1-0 GSS<1:0>: Timer1 Gate Source Select bits 11 = Comparator 2 optionally synchronized output (sync_C2OUT) 10 = Comparator 1 optionally synchronized output (sync_C1OUT) 01 = Timer0 overflow output 00 = Timer1 gate pin DS40001819B-page 284 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 22-6: Name ANSELA SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- -- ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177 CCPxCON EN -- OUT FMT INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF PIE1 PIR1 MODE<3:0> TMRxH Holding Register for the Most Significant Byte of the 16-bit TMR1/3/5 Register TMRxL Holding Register for the Least Significant Byte of the 16-bit TMR1/3/5 Register TRISA TRISA7 TxCON TxGCON Legend: * TRISA6 CS<1:0> GE GPOL TRISA5 TRISA4 CKPS<1:0> GTM GSPM 319 139 275* 275* TRISA3 TRISA2 TRISA1 TRISA0 OSCEN SYNC -- ON GGO/ DONE GVAL GSS<1:0> 176 283 284 -- = unimplemented location, read as `0'. Shaded cells are not used by the Timer1 module. Page provides register information. 2015-2016 Microchip Technology Inc. DS40001819B-page 285 PIC16(L)F1777/8/9 23.0 * Three modes of operation: - Free Running Period - One-shot - Monostable TIMER2/4/6/8 MODULE The Timer2/4/6/8 modules are 8-bit timers that can operate as free-running period counters or in conjunction with external signals that control start, run, freeze, and reset operation in One-Shot and Monostable modes of operation. Sophisticated waveform control such as pulse density modulation are possible by combining the operation of these timers with other internal peripherals such as the comparators and CCP modules. Features of the timer include: * * * * * * * * See Figure 23-1 for a block diagram of Timer2. See Figure 23-2 for the clock source block diagram. Note: 8-bit timer register 8-bit period register Selectable external hardware timer Resets Programmable prescaler (1:1 to 1:128) Programmable postscaler (1:1 to 1:16) Selectable synchronous/asynchronous operation Alternate clock sources Interrupt-on-period FIGURE 23-1: TIMER2 BLOCK DIAGRAM RSEL TxINPPS TxIN PPS External Reset Sources (Table 23-4) Three identical Timer2 modules are implemented on this device. The timers are named Timer2, Timer4, Timer6, and Timer8. All references to Timer2 apply as well to Timer4, Timer6 and Timer8. All references to T2PR apply as well to T4PR, T6PR and T8PR. Rev. 10-000 168B 5/29/201 4 MODE<4:0> TMRx_ers Edg e Detecto r Level Dete ctor Mode Control (2 clock Sync) MODE<3> reset CCP_pset MODE<4:3>=01 enable D MODE<4:1>=1011 Q Clear ON CKPOL 0 Pre scaler TMRx_clk TMRx 3 CKPS<2:0> Sync 1 Fosc/4 PSYNC R Set flag bi t TMRxIF Comparator Postscaler TMRx_postscaled 4 ON Sync (2 Clocks) 1 PRx OUTPS<3:0> 0 CKSYNC Note 1: 2: Signal to the CCP to trigger the PWM pulse See Section 22.5 for description of CCP interaction in the different TMR modes DS40001819B-page 286 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 23-2: TIMER2 CLOCK SOURCE BLOCK DIAGRAM TxCLKCON Rev. 10-000 169B 5/29/201 4 TXINPPS TXIN PPS Timer Clock Sources (See Table 23-3) 23.1 23.1.1 FREE RUNNING PERIOD MODE The value of TMR2 is compared to that of the Period register, T2PR, on each clock cycle. When the two values match, the comparator resets the value of TMR2 to 00h on the next cycle and increments the output postscaler counter. When the postscaler count equals the value in the OUTPS<4:0> bits of the TMRxCON1 register then a one clock period wide pulse occurs on the TMR2_postscaled output, and the postscaler count is cleared. TMR2_clk Timer2 Operation 23.1.2 ONE-SHOT MODE The One-Shot mode is identical to the Free Running Period mode except that the ON bit is cleared and the timer is stopped when TMR2 matches T2PR and will not restart until the T2ON bit is cycled off and on. Postscaler OUTPS<4:0> values other than 0 are meaningless in this mode because the timer is stopped at the first period event and the postscaler is reset when the timer is restarted. Timer2 operates in three major modes: 23.1.3 * Free Running Period * One-shot * Monostable Monostable modes are similar to One-Shot modes except that the ON bit is not cleared and the timer can be restarted by an external Reset event. Within each mode there are several options for starting, stopping, and reset. Table 23-1 lists the options. 23.2 In all modes, the TMR2 count register is incremented on the rising edge of the clock signal from the programmable prescaler. When TMR2 equals T2PR, a high level is output to the postscaler counter. TMR2 is cleared on the next clock input. An external signal from hardware can also be configured to gate the timer operation or force a TMR2 count Reset. In Gate modes the counter stops when the gate is disabled and resumes when the gate is enabled. In Reset modes the TMR2 count is reset on either the level or edge from the external source. The TMR2 and T2PR registers are both directly readable and writable. The TMR2 register is cleared and the T2PR register initializes to FFh on any device Reset. Both the prescaler and postscaler counters are cleared on the following events: * * * * a write to the TMR2 register a write to the T2CON register any device Reset External Reset Source event that resets the timer. Note: TMR2 is not cleared when T2CON is written. 2015-2016 Microchip Technology Inc. MONOSTABLE MODE PRx Period Register The PRx period register is double buffered, software reads and writes the PRx register. However, the timer uses a buffered PRx register for operation. Software does not have direct access to the buffered PRx register. The contents of the PRx register is transferred to the buffer by any of the following events: * A write to the TMRx register * A write to the TMRxCON register * When TMRx = PRx buffer and the prescaler rolls over * An external Reset event 23.3 Timer2 Output The Timer2 module's primary output is TMR2_postscaled, which pulses for a single TMR2_clk period when the postscaler counter matches the value in the OUTPS bits of the TMR2xCON register. The T2PR postscaler is incremented each time the TMR2 value matches the T2PR value. This signal can be selected as an input to several other input modules: * The ADC module, as an Auto-conversion Trigger * COG, as an auto-shutdown source DS40001819B-page 287 PIC16(L)F1777/8/9 In addition, the Timer2 is also used by the CCP module for pulse generation in PWM mode. Both the actual TMR2 value as well as other internal signals are sent to the CCP module to properly clock both the period and pulse width of the PWM signal. See Section 24.6 "CCP/PWM Clock Selection" for more details on setting up Timer2 for use with the CCP, as well as the timing diagrams in Section 23.6 "Operation Examples" for examples of how the varying Timer2 modes affect CCP PWM output. 23.4 External Reset Sources In addition to the clock source, the Timer2 also takes in an external Reset source. This external Reset source is selected for Timer2, Timer4, Timer6 and Timer8 with the T2RST, T4RST, T6RST and T8RST registers, respectively. This source can control starting and stopping of the timer, as well as resetting the timer, depending on which mode the timer is in. The mode of the timer is controlled by the MODE<4:0> bits of the TMRxHLT register. Edge-Triggered modes require six Timer clock periods between external triggers. Level-Triggered modes require the triggering level to be at least three Timer clock periods long. External triggers are ignored while in Debug Freeze mode. DS40001819B-page 288 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 23-1: TIMER2 OPERATING MODES MODE<4:0> Mode <4:3> <2:0> Output Operation 000 001 Period Pulse 010 Free Running Period Start Reset Stop Software gate (Figure 23-4) ON = 1 -- ON = 0 Hardware gate, active-high (Figure 23-5) ON = 1 and TMRx_ers = 1 -- ON = 0 or TMRx_ers = 0 Hardware gate, active-low ON = 1 and TMRx_ers = 0 -- ON = 0 or TMRx_ers = 1 011 Rising or falling edge Reset TMRx_ers 100 Rising edge Reset (Figure 23-6) TMRx_ers 00 101 110 Period Pulse with Hardware Reset 111 000 001 010 One-shot Edge triggered start (Note 1) 011 One-shot Timer Control Operation 01 100 101 110 111 Edge triggered start and hardware Reset (Note 1) Falling edge Reset Mono-stable 010 High level Reset (Figure 23-7) 10 Reserved 111 Reserved Note 1: 2: 3: 11 TMRx_ers = 1 ON = 0 or TMRx_ers = 1 ON = 1 -- Rising edge start (Figure 23-9) ON = 1 and TMRx_ers -- Falling edge start ON = 1 and TMRx_ers -- Any edge start ON = 1 and TMRx_ers -- Rising edge start and Rising edge Reset (Figure 23-10) ON = 1 and TMRx_ers TMRx_ers Falling edge start and Falling edge Reset ON = 1 and TMRx_ers TMRx_ers Rising edge start and Low level Reset (Figure 23-11) ON = 1 and TMRx_ers TMRx_ers = 0 Falling edge start and High level Reset ON = 1 and TMRx_ers TMRx_ers = 1 Edge triggered start (Note 1) Rising edge start (Figure 23-12) ON = 1 and TMRx_ers -- Falling edge start ON = 1 and TMRx_ers -- Any edge start ON = 1 and TMRx_ers -- ON = 0 or Next clock after TMRx = PRx (Note 2) ON = 0 or Next clock after TMRx = PRx (Note 3) Reserved Reserved 101 One-shot ON = 0 or TMRx_ers = 0 Software start (Figure 23-8) 100 110 TMRx_ers = 0 Reserved 011 Reserved TMRx_ers ON = 1 Low level Reset 000 001 ON = 0 Level triggered start and hardware Reset xxx High level start and Low level Reset (Figure 23-13) ON = 1 and TMRx_ers = 1 TMRx_ers = 0 Low level start & High level Reset ON = 1 and TMRx_ers = 0 TMRx_ers = 1 ON = 0 or Held in Reset (Note 2) Reserved If ON = 0 then an edge is required to restart the timer after ON = 1. When TMRx = PRx then the next clock clears ON and stops TMRx at 00h. When TMRx = PRx then the next clock stops TMRx at 00h but does not clear ON. 2015-2016 Microchip Technology Inc. DS40001819B-page 289 PIC16(L)F1777/8/9 23.5 Timer2 Interrupt Timer2 can also generate a device interrupt. The interrupt is generated when the postscaler counter matches one of 16 postscale options (from 1:1 through 1:16), which are selected with the postscaler control bits, OUTPS<3:0> of the T2CON register. The interrupt is enabled by setting the TMR2IE interrupt enable bit of the PIE1 register. Interrupt timing is illustrated in Figure 23-3. FIGURE 23-3: TIMER2 PRESCALER, POSTSCALER, AND INTERRUPT TIMING DIAGRAM Rev. 10-000205A 4/7/2016 CKPS 0b010 PRx 1 OUTPS 0b0001 TMRx_clk TMRx 0 0 1 1 0 1 0 TMRx_postscaled TMRxIF (1) (2) (1) Note 1: Setting the interrupt flag is synchronized with the instruction clock. Synchronization may take as many as 2 instruction cycles 2: Cleared by software. DS40001819B-page 290 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 23.6 23.6.1 Operation Examples This mode corresponds to legacy Timer2 operation. The timer increments with each clock input when ON = 1 and does not increment when ON = 0. When the TMRx count equals the PRx period count the timer resets on the next clock and continues counting from 0. Operation with the ON bit software controlled is illustrated in Figure 23-4. With PRx = 5, the counter advances until TMRx = 5, and goes to zero with the next clock. Unless otherwise specified, the following notes apply to the following timing diagrams: - Both the prescaler and postscaler are set to 1:1 (both the CKPS and OUTPS bits in the TxCON register are cleared). - The diagrams illustrate any clock except Fosc/4 and show clock-sync delays of at least two full cycles for both ON and Timer2_ers. When using Fosc/4, the clock-sync delay is at least one instruction period for Timer2_ers; ON applies in the next instruction period. - The PWM Duty Cycle and PWM output are illustrated assuming that the timer is used for the PWM function of the CCP module as described in Section 24.6 "CCP/PWM Clock Selection". The signals are not a part of the Timer2 module. FIGURE 23-4: SOFTWARE GATE MODE SOFTWARE GATE MODE TIMING DIAGRAM (MODE = 00000) Rev. 10-000195B 5/30/2014 0b00000 MODE TMRx_clk Instruction(1) BSF BCF BSF ON PRx TMRx 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. 2015-2016 Microchip Technology Inc. DS40001819B-page 291 PIC16(L)F1777/8/9 23.6.2 HARDWARE GATE MODE When MODE<4:0> = 00001 then the timer is stopped when the external signal is high. When MODE<4:0> = 00010 then the timer is stopped when the external signal is low. The Hardware Gate modes operate the same as the Software Gate mode except the TMRx_ers external signal can also gate the timer. When used with the CCP the gating extends the PWM period. If the timer is stopped when the PWM output is high then the duty cycle is also extended. FIGURE 23-5: Figure 23-5 illustrates the Hardware Gating mode for MODE<4:0> = 00001 in which a high input level starts the counter. HARDWARE GATE MODE TIMING DIAGRAM (MODE = 00001) Rev. 10-000 196B 5/30/201 4 0b00001 MODE TMRx_clk TMRx_ers PRx TMRx 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output DS40001819B-page 292 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 23.6.3 EDGE-TRIGGERED HARDWARE LIMIT MODE In Hardware Limit mode the timer can be reset by the TMRx_ers external signal before the timer reaches the period count. Three types of Resets are possible: * Reset on rising or falling edge (MODE<4:0>= 00011) * Reset on rising edge (MODE<4:0> = 00100) * Reset on falling edge (MODE<4:0> = 00101) When the timer is used in conjunction with the CCP in PWM mode then an early Reset shortens the period and restarts the PWM pulse after a two clock delay. Refer to Figure 23-6. FIGURE 23-6: EDGE-TRIGGERED HARDWARE LIMIT MODE TIMING DIAGRAM (MODE = 00100) Rev. 10-000 197B 5/30/201 4 0b00100 MODE TMRx_clk PRx 5 Instruction(1) BSF BCF BSF ON TMRx_ers TMRx 0 1 2 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. 2015-2016 Microchip Technology Inc. DS40001819B-page 293 PIC16(L)F1777/8/9 23.6.4 LEVEL-TRIGGERED HARDWARE LIMIT MODE The timer starts counting, and the PWM output is set high, on either the clock following the PRx match or two clocks after the external Reset signal relinquishes the Reset. The PWM output will remain high until the timer counts up to match the CCPRx pulse width value. If the external Reset signal goes true while the PWM output is high then the PWM output will remain high until the Reset signal is released allowing the timer to count up to match the CCPRx value. In the Level-Triggered Hardware Limit Timer modes the counter is reset by high or low levels of the external signal TMRx_ers, as shown in Figure 23-7. Selecting MODE<4:0> = 00110 will cause the timer to reset on a low level external signal. Selecting MODE<4:0> = 00111 will cause the timer to reset on a high level external signal. In the example, the counter is reset while TMRx_ers = 1. ON is controlled by BSF and BCF instructions. When ON = 0 the external signal is ignored. When the CCP uses the timer as the PWM time base then the PWM output will be set high when the timer starts counting and then set low only when the timer count matches the CCPRx value. The timer is reset when either the timer count matches the PRx value or two clock periods after the external Reset signal goes true and stays true. FIGURE 23-7: LEVEL-TRIGGERED HARDWARE LIMIT MODE TIMING DIAGRAM (MODE = 00111) Rev. 10-000198B 5/30/2014 0b00111 MODE TMRx_clk 5 PRx Instruction(1) BSF BCF BSF ON TMRx_ers 0 TMRx 1 2 0 1 2 3 4 5 0 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. DS40001819B-page 294 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 23.6.5 SOFTWARE START ONE-SHOT MODE When One-Shot mode is used in conjunction with the CCP PWM operation the PWM pulse drive starts concurrent with setting the ON bit. Clearing the ON bit while the PWM drive is active will extend the PWM drive. The PWM drive will terminate when the timer value matches the CCPRx pulse width value. The PWM drive will remain off until software sets the ON bit to start another cycle. If software clears the ON bit after the CCPRx match but before the PRx match then the PWM drive will be extended by the length of time the ON bit remains cleared. Another timing cycle can only be initiated by setting the ON bit after it has been cleared by a PRx period count match. In One-Shot mode the timer resets and the ON bit is cleared when the timer value matches the PRx period value. The ON bit must be set by software to start another timer cycle. Setting MODE<4:0> = 01000 selects One-Shot mode which is illustrated in Figure 23-8. In the example, ON is controlled by BSF and BCF instructions. In the first case, a BSF instruction sets ON and the counter runs to completion and clears ON. In the second case, a BSF instruction starts the cycle, BCF/BSF instructions turn the counter off and on during the cycle, and then it runs to completion. FIGURE 23-8: SOFTWARE START ONE-SHOT MODE TIMING DIAGRAM (MODE = 01000) Rev. 10-000199B 4/7/2016 0b01000 MODE TMRx_clk 5 PRx Instruction(1) BSF BSF BCF BSF ON TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. 2015-2016 Microchip Technology Inc. DS40001819B-page 295 PIC16(L)F1777/8/9 23.6.6 EDGE-TRIGGERED ONE-SHOT MODE The Edge-Triggered One-Shot modes start the timer on an edge from the external signal input, after the ON bit is set, and clear the ON bit when the timer matches the PRx period value. The following edges will start the timer: * Rising edge (MODE<4:0> = 01001) * Falling edge (MODE<4:0> = 01010) * Rising or Falling edge (MODE<4:0> = 01011) FIGURE 23-9: If the timer is halted by clearing the ON bit then another TMRx_ers edge is required after the ON bit is set to resume counting. Figure 23-9 illustrates operation in the rising edge One-Shot mode. When Edge-Triggered One-Shot mode is used in conjunction with the CCP then the edge-trigger will activate the PWM drive and the PWM drive will deactivate when the timer matches the CCPRx pulse width value and stay deactivated when the timer halts at the PRx period count match. EDGE-TRIGGERED ONE-SHOT MODE TIMING DIAGRAM (MODE = 01001) Rev. 10-000200B 5/19/2016 0b01001 MODE TMRx_clk 5 PRx Instruction(1) BSF BSF BCF ON TMRx_ers TMRx 0 1 2 3 4 5 0 1 2 CCP_pset TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. DS40001819B-page 296 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 23.6.7 EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE In Edge-Triggered Hardware Limit One-Shot modes the timer starts on the first external signal edge after the ON bit is set and resets on all subsequent edges. Only the first edge after the ON bit is set is needed to start the timer. The counter will resume counting automatically two clocks after all subsequent external Reset edges. Edge triggers are as follows: * Rising edge start and Reset (MODE<4:0> = 01100) * Falling edge start and Reset (MODE<4:0> = 01101) The timer resets and clears the ON bit when the timer value matches the PRx period value. External signal edges will have no effect until after software sets the ON bit. Figure 23-10 illustrates the rising edge hardware limit one-shot operation. When this mode is used in conjunction with the CCP then the first starting edge trigger, and all subsequent Reset edges, will activate the PWM drive. The PWM drive will deactivate when the timer matches the CCPRx pulse-width value and stay deactivated until the timer halts at the PRx period match unless an external signal edge resets the timer before the match occurs. 2015-2016 Microchip Technology Inc. DS40001819B-page 297 2015-2016 Microchip Technology Inc. FIGURE 23-10: EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 01100) Rev. 10-000201B 4/7/2016 MODE 0b01100 TMRx_clk 5 PRx Instruction(1) BSF BSF ON TMRx_ers 0 TMRx 1 2 3 4 5 0 1 2 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. DS40001819B-page 298 PIC16(L)F1777/8/9 Note PIC16(L)F1777/8/9 23.6.8 LEVEL RESET, EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODES In Level -Triggered One-Shot mode the timer count is reset on the external signal level and starts counting on the rising/falling edge of the transition from Reset level to the active level while the ON bit is set. Reset levels are selected as follows: * Low Reset level (MODE<4:0> = 01110) * High Reset level (MODE<4:0> = 01111) When the timer count matches the PRx period count, the timer is reset and the ON bit is cleared. When the ON bit is cleared by either a PRx match or by software control a new external signal edge is required after the ON bit is set to start the counter. When Level-Triggered Reset One-Shot mode is used in conjunction with the CCP PWM operation the PWM drive goes active with the external signal edge that starts the timer. The PWM drive goes inactive when the timer count equals the CCPRx pulse width count. The PWM drive does not go active when the timer count clears at the PRx period count match. 2015-2016 Microchip Technology Inc. DS40001819B-page 299 2015-2016 Microchip Technology Inc. FIGURE 23-11: LOW LEVEL RESET, EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 01110) Rev. 10-000202B 4/7/2016 MODE 0b01110 TMRx_clk 5 PRx Instruction(1) BSF BSF ON TMRx_ers 0 TMRx 1 2 3 4 5 0 1 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. DS40001819B-page 300 PIC16(L)F1777/8/9 Note PIC16(L)F1777/8/9 23.6.9 EDGE-TRIGGERED MONOSTABLE MODES The Edge-Triggered Monostable modes start the timer on an edge from the external Reset signal input, after the ON bit is set, and stop incrementing the timer when the timer matches the PRx period value. The following edges will start the timer: * Rising edge (MODE<4:0> = 10001) * Falling edge (MODE<4:0> = 10010) * Rising or Falling edge (MODE<4:0> = 10011) When an Edge-Triggered Monostable mode is used in conjunction with the CCP PWM operation the PWM drive goes active with the external Reset signal edge that starts the timer, but will not go active when the timer matches the PRx value. While the timer is incrementing, additional edges on the external Reset signal will not affect the CCP PWM. 2015-2016 Microchip Technology Inc. DS40001819B-page 301 2015-2016 Microchip Technology Inc. FIGURE 23-12: RISING EDGE-TRIGGERED MONOSTABLE MODE TIMING DIAGRAM (MODE = 10001) Rev. 10-000203A 4/7/2016 0b10001 MODE TMRx_clk PRx Instruction(1) 5 BSF BCF BSF BCF BSF ON TMRx_ers TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. DS40001819B-page 302 PIC16(L)F1777/8/9 Note PIC16(L)F1777/8/9 23.6.10 LEVEL-TRIGGERED HARDWARE LIMIT ONE-SHOT MODES The Level-Triggered Hardware Limit One-Shot modes hold the timer in Reset on an external Reset level and start counting when both the ON bit is set and the external signal is not at the Reset level. If one of either the external signal is not in Reset or the ON bit is set then the other signal being set/made active will start the timer. Reset levels are selected as follows: * Low Reset level (MODE<4:0> = 10110) * High Reset level (MODE<4:0> = 10111) When the timer count matches the PRx period count, the timer is reset and the ON bit is cleared. When the ON bit is cleared by either a PRx match or by software control the timer will stay in Reset until both the ON bit is set and the external signal is not at the Reset level. When Level-Triggered Hardware Limit One-Shot modes are used in conjunction with the CCP PWM operation the PWM drive goes active with either the external signal edge or the setting of the ON bit, whichever of the two starts the timer. 2015-2016 Microchip Technology Inc. DS40001819B-page 303 2015-2016 Microchip Technology Inc. FIGURE 23-13: LEVEL-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 10110) Rev. 10-000204A 4/7/2016 0b10110 MODE TMR2_clk PRx 5 Instruction(1) BSF BSF BCF BSF ON TMR2_ers TMRx 0 1 2 3 4 5 0 1 2 3 0 1 2 3 4 5 0 TMR2_postscaled `D3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. DS40001819B-page 304 PIC16(L)F1777/8/9 PWM Duty Cycle PIC16(L)F1777/8/9 23.7 PR2 Period Register The PR2 period register (T2PR) is double-buffered. Software reads and writes the PR2 register. However, the timer uses a buffered PR2 register for operation. Software does not have direct access to the buffered PR2 register. The contents of the PR2 register are transferred to the buffer by any of the following events: * A write to the TMR2 register * A write to the TMR2CON register * When TMR2 = PR2 buffer and the prescaler rolls over * An external Reset event 23.8 Timer2 Operation During Sleep When PSYNC = 1, Timer2 cannot be operated while the processor is in Sleep mode. The contents of the TMR2 and T2PR registers will remain unchanged while processor is in Sleep mode. When PSYNC = 0, Timer2 will operate in Sleep as long as the clock source selected is also still running. Selecting the LFINTOSC, MFINTOSC, or HFINTOSC oscillator as the timer clock source will keep the selected oscillator running during Sleep. 2015-2016 Microchip Technology Inc. DS40001819B-page 305 PIC16(L)F1777/8/9 23.9 Register Definitions: Timer2/4/6/8 Control Long bit name prefixes for the Timer2/4/6/8 peripherals are shown in Table 23-2. Refer to Section 1.1.2.2 "Long Bit Names" for more information TABLE 23-2: Peripheral Bit Name Prefix Timer2 T2 Timer4 T4 Timer6 T6 Timer8 T8 REGISTER 23-1: TxCLKCON: TIMERx CLOCK SELECTION REGISTER U-0 U-0 U-0 U-0 -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3-0 CS<3:0>: Timerx Clock Selection bits See Table 23-3. TABLE 23-3: TIMERX CLOCK SOURCES CS<3:0> Timer2 Timer4 Timer6 Timer8 1100-1111 Reserved Reserved Reserved Reserved 1011 LC4_out LC4_out LC4_out LC4_out 1010 LC3_out LC3_out LC3_out LC3_out 1001 LC2_out LC2_out LC2_out LC2_out 1000 LC1_out LC1_out LC1_out LC1_out 0111 ZCD_out ZCD_out ZCD_out ZCD_out 0110 SOSC SOSC SOSC SOSC 0101 MFINTOSC MFINTOSC MFINTOSC MFINTOSC 0100 LFINTOSC LFINTOSC LFINTOSC LFINTOSC 0011 HFINTOSC HFINTOSC HFINTOSC HFINTOSC 0010 Fosc Fosc Fosc Fosc 0001 Fosc/4 Fosc/4 Fosc/4 Fosc/4 0000 Pin selected by T2INPPS Pin selected by T4INPPS Pin selected by T6INPPS Pin selected by T8INPPS DS40001819B-page 306 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 23-2: R/W/HC-0/0 TxCON: TIMERx CONTROL REGISTER R/W-0/0 (1) ON R/W-0/0 R/W-0/0 R/W-0/0 CKPS<2:0> R/W-0/0 R/W-0/0 R/W-0/0 OUTPS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Bit is cleared by hardware bit 7 ON: Timerx On bit 1 = Timerx is on 0 = Timerx is off: all counters and state machines are reset bit 6-4 CKPS<2:0>: Timer2-type Clock Prescale Select bits 111 = 1:128 Prescaler 110 = 1:64 Prescaler 101 = 1:32 Prescaler 100 = 1:16 Prescaler 011 = 1:8 Prescaler 010 = 1:4 Prescaler 001 = 1:2 Prescaler 000 = 1:1 Prescaler bit 3-0 OUTPS<3:0>: Timerx Output Postscaler Select bits 1111 = 1:16 Postscaler 1110 = 1:15 Postscaler 1101 = 1:14 Postscaler 1100 = 1:13 Postscaler 1011 = 1:12 Postscaler 1010 = 1:11 Postscaler 1001 = 1:10 Postscaler 1000 = 1:9 Postscaler 0111 = 1:8 Postscaler 0110 = 1:7 Postscaler 0101 = 1:6 Postscaler 0100 = 1:5 Postscaler 0011 = 1:4 Postscaler 0010 = 1:3 Postscaler 0001 = 1:2 Postscaler 0000 = 1:1 Postscaler Note 1: In certain modes, the ON bit will be auto-cleared by hardware. See Section 23.6 "Operation Examples". 2015-2016 Microchip Technology Inc. DS40001819B-page 307 PIC16(L)F1777/8/9 REGISTER 23-3: R/W-0/0 TxHLT: TIMERx HARDWARE LIMIT CONTROL REGISTER R/W-0/0 (1, 2) PSYNC CKPOL (3) R/W-0/0 R/W-0/0 R/W-0/0 (4, 5) CKSYNC R/W-0/0 MODE<4:0> R/W-0/0 R/W-0/0 (6, 7) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 PSYNC: Timerx Prescaler Synchronization Enable bit(1, 2) 1 = TMRx Prescaler Output is synchronized to Fosc/4 0 = TMRx Prescaler Output is not synchronized to Fosc/4 bit 6 CKPOL: Timerx Clock Polarity Selection bit(3) 1 = Falling edge of input clock clocks timer/prescaler 0 = Rising edge of input clock clocks timer/prescaler bit 5 CKSYNC: Timerx Clock Synchronization Enable bit(4, 5) 1 = ON register bit is synchronized to TMR2_clk input 0 = ON register bit is not synchronized to TMR2_clk input bit 4-0 MODE<4:0>: Timerx Control Mode Selection bits(6, 7) See Table 23-1. Note 1: Setting this bit ensures that reading TMRx will return a valid value. 2: When this bit is `1', Timer2 cannot operate in Sleep mode. 3: CKPOL should not be changed while ON = 1. 4: Setting this bit ensures glitch-free operation when the ON is enabled or disabled. 5: When this bit is set then the timer operation will be delayed by two TMRx input clocks after the ON bit is set. 6: Unless otherwise indicated, all modes start upon ON = 1 and stop upon ON = 0 (stops occur without affecting the value of TMRx). 7: When TMRx = PRx, the next clock clears TMRx, regardless of the operating mode. DS40001819B-page 308 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 23-4: TXRST: TIMERX EXTERNAL RESET SIGNAL SELECTION REGISTER U-0 U-0 U-0 -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 RSEL<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-5 Unimplemented: Read as `0' bit 4-0 RSEL<4:0>: TimerX External Reset Signal Source Selection bits See Table 23-4. TABLE 23-4: EXTERNAL RESET SOURCES RSEL<4:0> Timer2 Timer4 Timer6 Timer8 11111 Reserved Reserved Reserved Reserved 11110 Reserved Reserved Reserved Reserved 11101 LC4_out LC4_out LC4_out LC4_out 11100 LC3_out LC3_out LC3_out LC3_out 11011 LC2_out LC2_out LC2_out LC2_out 11010 LC1_out LC1_out LC1_out LC1_out 11001 ZCD_out ZCD_out ZCD_out ZCD_out 11000(1) sync_C8OUT sync_C8OUT sync_C8OUT sync_C8OUT 10111(1) sync_C7OUT sync_C7OUT sync_C7OUT sync_C7OUT 10110 sync_C6OUT sync_C6OUT sync_C6OUT sync_C6OUT 10101 sync_C5OUT sync_C5OUT sync_C5OUT sync_C5OUT 10100 sync_C4OUT sync_C4OUT sync_C4OUT sync_C4OUT 10011 sync_C3OUT sync_C3OUT sync_C3OUT sync_C3OUT 10010 sync_C2OUT sync_C2OUT sync_C2OUT sync_C2OUT 10001 sync_C1OUT sync_C1OUT sync_C1OUT sync_C1OUT 10000(1) PWM12_out PWM12_out PWM12_out PWM12_out 01111 PWM11_out PWM11_out PWM11_out PWM11_out 01110 PWM6_out PWM6_out PWM6_out PWM6_out 01101 PWM5_out PWM5_out PWM5_out PWM5_out 01100(1) PWM10_out PWM10_out PWM10_out PWM10_out 01011 PWM9_out PWM9_out PWM9_out PWM9_out 01010 PWM4_out PWM4_out PWM4_out PWM4_out 01001 PWM3_out PWM3_out PWM3_out PWM3_out 01000(1) CCP8_out CCP8_out CCP8_out CCP8_out 00111 CCP7_out CCP7_out CCP7_out CCP7_out 00110 CCP2_out CCP2_out CCP2_out CCP2_out 00101 CCP1_out CCP1_out CCP1_out CCP1_out 00100 TMR8_postscaled TMR8_postscaled TMR8_postscaled Reserved 00011 TMR6_postscaled TMR6_postscaled Reserved TMR6_postscaled 00010 TMR4_postscaled Reserved TMR4_postscaled TMR4_postscaled 00001 Reserved TMR2_postscaled TMR2_postscaled TMR2_postscaled 00000 Note 1: Pin selected byT2INPPS Pin selected by T4INPPS Pin selected by T6INPPS Pin selected by T6INPPS PIC16LF1777/9 only. 2015-2016 Microchip Technology Inc. DS40001819B-page 309 PIC16(L)F1777/8/9 TABLE 23-5: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Bit 7 Bit 6 CCP1CON EN CCP2CON Bit 4 -- OUT FMT MODE<3:0> 319 EN -- OUT FMT MODE<3:0> 319 CCP7CON EN -- OUT FMT MODE<3:0> 319 CCP8CON(1) EN -- OUT FMT MODE<3:0> 319 INTCON PIE1 PIR1 Bit 3 Bit 2 Bit 1 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF T2PR Timer2 Module Period Register TMR2 Holding Register for the 8-bit TMR2 Register 287* ON T2CLKCON -- -- -- T2RST -- -- -- RSEL<4:0> CKPS<2:0> PSYNC CKPOL CKSYNC MODE<4:0> T4PR Timer4 Module Period Register TMR4 Holding Register for the 8-bit TMR4 Register -- OUTPS<3:0> 307 CS<3:0> 306 308 287* ON T4CLKCON -- -- -- T4RST -- -- -- RSEL<4:0> CKPS<2:0> PSYNC CKPOL CKSYNC MODE<4:0> T6PR Timer6 Module Period Register TMR6 Holding Register for the 8-bit TMR6 Register -- OUTPS<3:0> 307 CS<3:0> 306 309 308 287* 287* T6CON ON T6CLKCON -- -- -- T6RST -- -- -- RSEL<4:0> PSYNC CKPOL CKSYNC MODE<4:0> T6HLT 309 287* T4CON T4HLT 139 287* T2CON T2HLT Bit 0 Register on Page Bit 5 CKPS<2:0> T8PR Timer6 Module Period Register TMR8 Holding Register for the 8-bit TMR6 Register -- OUTPS<3:0> 307 CS<3:0> 306 309 308 287* 287* T8CON ON T8CLKCON -- -- -- T8RST -- -- -- RSEL<4:0> 309 PSYNC CKPOL CKSYNC MODE<4:0> 308 T8HLT Legend: * Note 1: CKPS<2:0> -- OUTPS<3:0> 307 CS<3:0> 306 -- = unimplemented location, read as `0'. Shaded cells are not used for Timer2 module. Page provides register information. PIC16LF1777/9 only. DS40001819B-page 310 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 24.0 CAPTURE/COMPARE/PWM MODULES 24.1 The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle. TABLE 24-1: Device AVAILABLE CCP MODULES CCP1 CCP2 CCP7 CCP8 PIC16(L)F1778 PIC16(L)F1777/9 Note 1: In devices with more than one CCP module, it is very important to pay close attention to the register names used. A number placed after the module acronym is used to distinguish between separate modules. For example, the CCP1CON and CCP2CON control the same operational aspects of two completely different CCP modules. 2: Throughout this section, generic references to a CCP module in any of its operating modes may be interpreted as being equally applicable to a CCPx module. Register names, module signals, I/O pins, and bit names may use the generic designator `x' to indicate the use of a numeral to distinguish a particular module, when required. Capture Mode The Capture mode function described in this section is available and identical for all CCP modules. Capture mode makes use of the 16-bit Timer1 resource. When an event occurs on the CCPx input, the 16-bit CCPRxH:CCPRxL register pair captures and stores the 16-bit value of the TMR1H:TMR1L register pair, respectively. An event is defined as one of the following and is configured by the MODE<3:0> bits of the CCPxCON register: * * * * * Every edge (rising or falling) Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge The CCPx capture input signal is configured by the CTS bits of the CCPxCAP register with the following options: * * * * * CCPx pin Comparator 1 output (C1_OUT_sync) Comparator 2 output (C2_OUT_sync) Comparator 7 output (C7_OUT_sync) Comparator 8 output (C8_OUT_sync) (PIC16(L)F1777/9 only) * LC2_output * LC3_output * Interrupt-on-change interrupt trigger (IOC_interrupt) When a capture is made, the Interrupt Request Flag bit CCPxIF of the PIRx register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPRxH:CCPRxL register pair is read, the old captured value is overwritten by the new captured value. Figure 24-1 shows a simplified diagram of the capture operation. 24.1.1 CCP PIN CONFIGURATION In Capture mode, select the interrupt source using the CTS bits of the CCPxCAP register. If the CCPx pin is chosen, it should be configured as an input by setting the associated TRIS control bit. Note: 2015-2016 Microchip Technology Inc. If the CCPx pin is configured as an output, a write to the port can cause a capture condition. DS40001819B-page 311 PIC16(L)F1777/8/9 FIGURE 24-1: CAPTURE MODE OPERATION BLOCK DIAGRAM Rev. 10-000 158E 9/5/201 4 RxyPPS CTS<2:0> CCPx PPS TRIS Control CCPRxH CCPRxL 16 Prescaler 1,4,16 set CCPxIF and Edge Detect 16 CCPx PPS MODE <3:0> TMR1H TMR1L CCPxPPS Note: 24.1.2 Capture sources. See Register 24-4. TIMER1 MODE RESOURCE 24.1.5 CAPTURE DURING SLEEP Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. See Section 22.0 "Timer1/3/5 Module with Gate Control" for more information on configuring Timer1. When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. 24.1.3 SOFTWARE INTERRUPT MODE When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit of the PIEx register clear to avoid false interrupts. Additionally, the user should clear the CCPxIF interrupt flag bit of the PIRx register following any change in operating mode. Note: 24.1.4 Clocking Timer1 from the system clock (FOSC) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCPx pin, Timer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. CCP PRESCALER There are four prescaler settings specified by the MODE<3:0> bits of the CCPxCON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the EN bit of the CCPxCON register before changing the prescaler. DS40001819B-page 312 Capture mode will operate during Sleep when Timer1 is clocked by an external clock source. 24.1.6 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the PPS controls. See Section 12.0 "Peripheral Pin Select (PPS) Module" for more details. 24.1.7 CAPTURE OUTPUT Whenever a capture occurs, the output of the CCP will go high for a period equal to one system clock period (1/FOSC). This output is available as an input signal to the following peripherals: * * * * * * * * ADC Trigger COG PRG DSM CLC Op Amp override Timer2/4/6/8 Reset Any device pins In addition, the CCP output can be output to any pin with that pin's PPS control. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 24.2 Compare Mode The Compare mode function described in this section is available and identical for all CCP modules. Compare mode makes use of the 16-bit Timer1 resource. The 16-bit value of the CCPRxH:CCPRxL register pair is constantly compared against the 16-bit value of the TMR1H:TMR1L register pair. When a match occurs, one of the following events can occur: * * * * * * Toggle the CCPx output Set the CCPx output Clear the CCPx output Pulse the CCPx output Generate a Software Interrupt Auto-conversion Trigger register pair. The TMR1H:TMR1L register pair is not reset until the next rising edge of the Timer1 clock. The Auto-conversion Trigger output starts an ADC conversion (if the ADC module is enabled). This allows the CCPRxH:CCPRxL register pair to effectively provide a 16-bit programmable period register for Timer1. Refer to Section 16.2.5 "Auto-Conversion Trigger" for more information. Note 1: The Auto-conversion Trigger from the CCP module does not set interrupt flag bit TMR1IF of the PIR1 register. 2: Removing the match condition by changing the contents of the CCPRxH and CCPRxL register pair, between the clock edge that generates the Auto-conversion Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring. The action on the pin is based on the value of the MODE<3:0> control bits of the CCPxCON register. At the same time, the interrupt flag CCPxIF bit is set. All Compare modes can generate an interrupt. 24.2.2 Figure 24-2 shows a simplified diagram of the compare operation. The user must configure the CCPx pin as an output by clearing the associated TRIS bit. 24.2.1 The CCPx pin function can be moved to alternate pins using the PPS controls. See Section 12.0 "Peripheral Pin Select (PPS) Module" for more detail. AUTO-CONVERSION TRIGGER When Auto-Conversion Trigger mode is chosen (CCPxM<3:0> = 1011), the CCPx module does the following: CCPx PIN CONFIGURATION Clearing the CCPxCON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch. Note: * Resets Timer1 * Starts an ADC conversion if ADC is enabled The CCPx module does not assert control of the CCPx pin in this mode. The Auto-conversion Trigger output of the CCP occurs immediately upon a match between the TMR1H, TMR1L register pair and the CCPRxH:CCPRxL FIGURE 24-2: COMPARE MODE OPERATION BLOCK DIAGRAM Rev. 10-000 159B 9/5/201 4 To Peripherals CCPRxH CCPRxL set CCPxIF Comparator Output Logic 4 TMR1H TMR1L 2015-2016 Microchip Technology Inc. S Q PPS CCP x TRIS Control R RxyPPS MODE<3:0> DS40001819B-page 313 PIC16(L)F1777/8/9 24.2.3 TIMER1 MODE RESOURCE In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. See Section 22.0 "Timer1/3/5 Module with Gate Control" for more information on configuring Timer1. Note: 24.2.4 Clocking Timer1 from the system clock (FOSC) should not be used in Compare mode. In order for Compare mode to recognize the trigger event on the CCPx pin, TImer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. SOFTWARE INTERRUPT MODE When Generate Software Interrupt mode is chosen (MODE<3:0> = 1010), the CCPx module does not assert control of the CCPx pin (see the CCPxCON register). 24.2.5 COMPARE DURING SLEEP The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep. 24.2.6 24.2.7 CAPTURE OUTPUT When in Compare mode, the CCP will provide an output upon the 16-bit value of the CCPRxH:CCPRxL register pair, matching the TMR1H:TMR1L register pair. The compare output depends on which Compare mode the CCP is configured as. If the MODE bits of CCPxCON register are equal to `1011' or `1010', the CCP module will output high, while TMR1 is equal to the CCPRxH:CCPRxL register pair. This means that the pulse width is determined by the TMR1 prescaler. If the MODE bits of CCPxCON are equal to `0001' or `0010', the output will toggle upon a match, going from `0' to `1' or vice-versa. If the MODE bits of CCPxCON are equal to `1001', the output is cleared on a match, and if the MODE bits are equal to `1000', the output is set on a match. This output is available to the following peripherals: * * * * * * * * ADC Trigger COG PRG DSM CLC Op Amp override Timer2/4/6/8 Reset Any device pins ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the PPS controls. See Section 12.0 "Peripheral Pin Select (PPS) Module" for more detail. DS40001819B-page 314 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 24.3 PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load. PWM Overview Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. Lowering the number of steps applied, which shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete cycle or the total amount of on and off time combined. FIGURE 24-3: The term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, where 0% is fully off and 100% is fully on. A lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. Figure 24-3 shows a typical waveform of the PWM signal. SIMPLIFIED PWM BLOCK DIAGRAM Rev. 10-000 157C 9/5/201 4 Duty cycle registers CCPRxH CCPRxL CCPx_out set CCPIF 10-bit Latch(2) (Not accessible by user) Comparator R S TMR2 Module R TMR2 To Peripherals Q PPS RxyPPS CCPx TRIS Control (1) ERS logic Comparator CCPx_pset PR2 Notes: 1. 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to create 10-bit time-base. 2. The alignment of the 10 bits from the CCPR register is determined by the FMT bit. 2015-2016 Microchip Technology Inc. DS40001819B-page 315 PIC16(L)F1777/8/9 24.3.1 STANDARD PWM OPERATION 24.3.2 SETUP FOR PWM OPERATION The standard PWM function described in this section is available and identical for all CCP modules. The following steps should be taken when configuring the CCP module for standard PWM operation: The standard PWM mode generates a Pulse-Width Modulation (PWM) signal on the CCPx pin with up to ten bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: 1. * T2PR/T4PR/T6PR/T8PR registers * T2CON/T4CON/T6CON/T8CON registers * CCPRxH:CCPRxL register pair 3. Figure 24-3 shows a simplified block diagram of PWM operation. Note 1: The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin. 2. 4. 5. 6. 2: Clearing the CCPxCON register will relinquish control of the CCPx pin. 7. Disable the CCPx pin output driver by setting the associated TRIS bit. Select the timer associated with the PWM by setting the CCPTMRS register. Load the associated T2PR/T4PR/T6PR/T8PR register with the PWM period value. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. Load the CCPRxH:CCPRxL register pair with the PWM duty cycle value. Configure and start the timer selected in step 2: * Clear the timer interrupt flag bit of the PIRx register. See Note below. * Configure the CKPS bits of the TxCON register with the Timer prescale value. * Enable the Timer by setting the ON bit of the TxCON register. Enable PWM output pin: * Wait until the Timer overflows and the timer interrupt bit of the PIRx register is set. See Note below. * Enable the CCPx pin output driver by clearing the associated TRIS bit. Note: DS40001819B-page 316 In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 24.4 CCP/PWM Clock Selection The PIC16(L)F1777/8/9 allows each individual CCP and PWM module to select the timer source that controls the module. Each module has an independent selection. As there are up to four 8-bit timers with auto-reload (Timer2/4/6/8). The PWM mode on the CCP and PWM modules can use any of these timers. The CCPTMRS register is used to select which timer is used. 24.4.1 USING THE TMR2/4/6/8 WITH THE CCP MODULE This device has a new version of the TMR2 module that has many new modes, which allow for greater customization and control of the PWM signals than older parts. Refer to Section 23.6 "Operation Examples" for examples of PWM signal generation using the different modes of Timer2. The CCP operation requires that the timer used as the PWM time base has the FOSC/4 clock source selected. 24.4.2 PWM PERIOD The PWM period is specified by the T2PR/T4PR/T6PR/T8PR register of Timer2/4/6/8. The PWM period can be calculated using the formula of Equation 24-1. EQUATION 24-1: PWM PERIOD PWM Period = PR2 + 1 4 T OSC (TMR2 Prescale Value) Note 1: TOSC = 1/FOSC When TMR2/4/6/8 is equal to its respective T2PR/T4PR/T6PR/T8PR register, the following three events occur on the next increment cycle: * TMR2/4/6/8 is cleared * The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) * The PWM duty cycle is latched from the CCPRxH:CCPRxL pair into the internal 10-bit latch. Note: 24.4.3 The Timer postscaler (see Figure 24-1) is not used in the determination of the PWM frequency. eight bits to the CCPRxL register. If FMT = 1, the Least Significant two bits of the duty cycle should be written to bits <7:6> of the CCPRxL register and the Most Significant eight bits to the CCPRxH register. This is illustrated in Figure 24-4. These bits can be written at any time. The duty cycle value is not latched into the internal latch until after the period completes (i.e., a match between T2PR/T4PR/T6PR/T8PR and TMR2/4/6/8 registers occurs). Equation 24-2 is used to calculate the PWM pulse width. Equation 24-3 is used to calculate the PWM duty cycle ratio. EQUATION 24-2: PULSE WIDTH Pulse Width = CCPRxH:CCPRxL T OSC (TMR2 Prescale Value) EQUATION 24-3: DUTY CYCLE RATIO CCPRxH:CCPRxL Duty Cycle Ratio = -------------------------------------------------4 PRx + 1 The PWM duty cycle registers are double buffered for glitchless PWM operation. The 8-bit timer TMR2/4/6/8 register is concatenated with either the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2/4/6/8 prescaler is set to 1:1. When the 10-bit time base matches the internal buffer register, then the CCPx pin is cleared (see Figure 24-3). FIGURE 24-4: CCPx DUTY CYCLE ALIGNMENT Rev. 10-000 160A 12/9/201 3 CCPRxH CCPRxL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 FMT = 1 FMT = 0 CCPRxH CCPRxL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 10-bit Duty Cycle 9 8 7 6 5 4 3 2 1 0 PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to two registers: the CCPRxH:CCPRxL register pair. Where the particular bits go is determined by the FMT bit of the CCPxCON register. If FMT = 0, the two Most Significant bits of the duty cycle value should be written to bits <1:0> of the CCPRxH register and the remaining 2015-2016 Microchip Technology Inc. DS40001819B-page 317 PIC16(L)F1777/8/9 24.4.4 PWM RESOLUTION EQUATION 24-4: The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when T2PR/T4PR/T6PR/T8PR is 255. The resolution is a function of the T2PR/T4PR/T6PR/T8PR register value as shown by Equation 24-4. TABLE 24-2: PWM Frequency T2PR Value Note: If the pulse-width value is greater than the period, the assigned PWM pin(s) will remain unchanged. 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6 Maximum Resolution (bits) EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 16 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 Timer Prescale T2PR Value Maximum Resolution (bits) 24.4.5 log 4 PR2 + 1 Resolution = ------------------------------------------ bits log 2 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) Timer Prescale TABLE 24-3: PWM RESOLUTION CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 5.0 "Oscillator Module (with Fail-Safe Clock Monitor)" for additional details. 24.4.6 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. 24.4.7 PWM OUTPUT The output of the CCP in PWM mode is the PWM signal generated by the module and described above. This output is available to the following peripherals: * * * * * * * * ADC Trigger COG PRG DSM CLC Op Amp override Timer2/4/6/8 Reset Any device pins DS40001819B-page 318 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 24.5 Register Definitions: CCP Control REGISTER 24-1: CCPxCON: CCPx CONTROL REGISTER R/W-0/0 U-0 R-x R/W-0/0 EN -- OUT FMT R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 MODE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset `1' = Bit is set `0' = Bit is cleared bit 7 EN: CCPx Module Enable bit 1 = CCPx is enabled 0 = CCPx is disabled bit 6 Unimplemented: Read as `0' bit 5 OUT: CCPx Output Data bit (read-only) bit 4 FMT: CCPW (Pulse-Width) Alignment bit If MODE = PWM Mode 1 = Left-aligned format, CCPRxH <7> is the MSB of the PWM duty cycle 0 = Right-aligned format, CCPRxL<0> is the LSB of the PWM duty cycle bit 3-0 MODE<3:0>: CCPx Mode Selection bits 11xx = PWM mode 1011 = 1010 = 1001 = 1000 = Compare mode: Pulse output, clear TMR1 Compare mode: Pulse output (0 - 1 - 0) Compare mode: clear output on compare match. Output is set upon selection of this mode. Compare mode: set output on compare match. Output is set upon selection of this mode. 0111 = 0110 = 0101 = 0100 = Capture mode: every 16th rising edge Capture mode: every 4th rising edge Capture mode: every rising edge Capture mode: every falling edge 0011 = 0010 = 0001 = 0000 = Capture mode: every rising or falling edge Compare mode: toggle output on match Compare mode: Toggle output and clear TMR1 on match Capture/Compare/PWM off (resets CCPx module) (reserved for backwards compatibility) 2015-2016 Microchip Technology Inc. DS40001819B-page 319 PIC16(L)F1777/8/9 REGISTER 24-2: R/W-0/0 CCPRxL: CCPx LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CCPR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset `1' = Bit is set `0' = Bit is cleared bit 7-0 MODE = Capture Mode CCPRxL<7:0>: LSB of captured TMR1 value MODE = Compare Mode CCPRxL<7:0>: LSB compared to TMR1 value MODE = PWM Mode && FMT = 0 CCPRxL<7:0>: CCPW<7:0> - Pulse width Least Significant eight bits MODE = PWM Mode && FMT = 1 CCPRxL<7:6>: CCPW<1:0> - Pulse width Least Significant two bits CCPRxL<5:0>: Not used REGISTER 24-3: R/W-0/0 CCPRxH: CCPx HIGH BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CCPR<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset `1' = Bit is set `0' = Bit is cleared bit 7-0 MODE = Capture Mode CCPRxH<7:0>: MSB of captured TMR1 value MODE = Compare Mode CCPRxH<7:0>: MSB compared to TMR1 value MODE = PWM Mode && FMT = 0 CCPRxH<7:2>: Not used CCPRxH<1:0>: CCPW<9:8> - Pulse width Most Significant two bits MODE = PWM Mode && FMT = 1 CCPRxH<7:0>: CCPW<9:2> - Pulse width Most Significant eight bits DS40001819B-page 320 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 24-4: CCPxCAP: CCPx CAPTURE INPUT SELECTION REGISTER U-0 U-0 U-0 U-0 -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CTS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3-0 CTS<3:0>: Capture Trigger Input Selection bits 1101 = IOC_event 1100 = LC4_output 1011 = LC3_output 1010 = LC2_output 1001 = LC1_output 1000 = C8_sync_out(1) 0111 = C7_sync_out(1) 0110 = C6_sync_out 0101 = C5_sync_out 0100 = C4_sync_out 0011 = C3_sync_out 0010 = C2_sync_out 0001 = C1_sync_out 0000 = Pin selected with the CCPxPPS register Note 1: PIC16LF1777/9 only. 2015-2016 Microchip Technology Inc. DS40001819B-page 321 PIC16(L)F1777/8/9 24.6 CCP/PWM Clock Selection This device allows each individual CCP and PWM module to select the timer source that controls the module. Each module has an independent selection. As there are four 8-bit timers with auto-reload (Timer2, Timer4, Timer6 and Timer8). The PWM mode on the CCP and 10-bit PWM modules can use any of these timers. The CCPTMRS register is used to select which timer is used. 24.7 Register Definitions: CCP/PWM Timers Control REGISTER 24-5: R/W-0/0 CCPTMRS1: PWM TIMER SELECTION CONTROL REGISTER 1 R/W-0/0 R/W-0/0 C8TSEL<1:0>(1) R/W-0/0 C7TSEL<1:0> R/W-0/0 R/W-0/0 R/W-0/0 C2TSEL<1:0> R/W-0/0 C1TSEL<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 C8TSEL<1:0>: CCP8 (PWM8) Timer Selection bits(1) 11 = CCP8 is based off Timer8 in PWM mode 10 = CCP8 is based off Timer6 in PWM mode 01 = CCP8 is based off Timer4 in PWM mode 00 = CCP8 is based off Timer2 in PWM mode bit 5-4 C7TSEL<1:0>: CCP7 (PWM7) Timer Selection bits 11 = CCP7 is based off Timer8 in PWM mode 10 = CCP7 is based off Timer6 in PWM mode 01 = CCP7 is based off Timer4 in PWM mode 00 = CCP7 is based off Timer2 in PWM mode bit 3-2 C2TSEL<1:0>: CCP2 (PWM2) Timer Selection bits 11 = CCP2 is based off Timer8 in PWM mode 10 = CCP2 is based off Timer6 in PWM mode 01 = CCP2 is based off Timer4 in PWM mode 00 = CCP2 is based off Timer2 in PWM mode bit 1-0 C1TSEL<1:0>: CCP1 (PWM1) Timer Selection bits 11 = CCP1 is based off Timer8 in PWM mode 10 = CCP1 is based off Timer6 in PWM mode 01 = CCP1 is based off Timer4 in PWM mode 00 = CCP1 is based off Timer2 in PWM mode Note 1: PIC16(L)F1777/9 only. DS40001819B-page 322 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 24-6: R/W-0/0 CCPTMRS2: PWM TIMER SELECTION CONTROL REGISTER 2 R/W-0/0 R/W-0/0 (1) P10TSEL<1:0> R/W-0/0 R/W-0/0 P9TSEL<1:0> R/W-0/0 R/W-0/0 P4TSEL<1:0> bit 7 R/W-0/0 P3TSEL<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 P10TSEL<1:0>: PWM10 Timer Selection bits(1) 11 = PWM10 is based off Timer8 in PWM mode 10 = PWM10 is based off Timer6 in PWM mode 01 = PWM10 is based off Timer4 in PWM mode 00 = PWM10 is based off Timer2 in PWM mode bit 5-4 P9TSEL<1:0>: PWM9 Timer Selection bits 11 = PWM9 is based off Timer8 in PWM mode 10 = PWM9 is based off Timer6 in PWM mode 01 = PWM9 is based off Timer4 in PWM mode 00 = PWM9 is based off Timer2 in PWM mode bit 3-2 P4TSEL<1:0>: PWM4 Timer Selection bits 11 = PWM4 is based off Timer8 in PWM mode 10 = PWM4 is based off Timer6 in PWM mode 01 = PWM4 is based off Timer4 in PWM mode 00 = PWM4 is based off Timer2 in PWM mode bit 1-0 P3TSEL<1:0>: PWM3 Timer Selection bits 11 = PWM3 is based off Timer8 in PWM mode 10 = PWM3 is based off Timer6 in PWM mode 01 = PWM3 is based off Timer4 in PWM mode 00 = PWM3 is based off Timer2 in PWM mode Note 1: PIC16(L)F1777/9 only. 2015-2016 Microchip Technology Inc. DS40001819B-page 323 PIC16(L)F1777/8/9 TABLE 24-4: Name SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM Bit 5 Bit 6 CCPxCAP -- -- -- -- CTS<3:0> 321 CCPxCON EN -- OUT FMT MODE<3:0> 319 CCPRxL Capture/Compare/PWM Register x (LSB) CCPRxH Capture/Compare/PWM Register x (MSB) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page Bit 7 320 320 CCPTMRS1 C8TSEL<1:0>(1) CCPTMRS2 P10TSEL<1:0>(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133 PIE2 OSFIE C2IE C1IE COG1IE BCL1IE C4IE C3IE CCP2IE 134 PIE5 CCP8IE(1) CCP7IE COG4IE(1) COG3IE C8IE(1) C7IE(1) C6IE C5IE 137 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139 PIR2 OSFIF C2IF C1IF COG1IF BCL1IF C4IF C3IF CCP2IF 140 PIR5 CCP8IF(1) CCP7IF COG4IF(1) COG3IF C8IF(1) C7IF(1) C6IF C5IF 143 T2PR T2CON C7TSEL<1:0> P9TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> P4TSEL<1:0> P3TSEL<1:0> Timer2 Period Register ON 323 323 132 287* CKPS<2:0> OUTPS<3:0> 307 TMR2 Timer2 Module Register 287 T4PR Timer4 Period Register 287* T4CON ON TMR4 Timer4 Module Register T6PR Timer6 Period Register T6CON ON CKPS<2:0> OUTPS<3:0> 307 287 287* CKPS<2:0> OUTPS<3:0> 307 TMR6 Timer6 Module Register 287 T8PR Timer8 Period Register 287* T8CON TMR8 ON CKPS<2:0> OUTPS<3:0> Timer8 Module Register 307 287 Legend: -- = Unimplemented location, read as `0'. Shaded cells are not used by the PWM. * Page provides register information. Note 1: PIC16(L)F1777/9 only. DS40001819B-page 324 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 25.0 10-BIT PULSE-WIDTH MODULATION (PWM) MODULE TABLE 25-1: The 10-bit PWM module generates a Pulse-Width Modulated signal determined by the duty cycle, period, and resolution that are configured by the following registers: * * * * * AVAILABLE 10-BIT PWM MODULES Device PWM3 PWM4 PWM9 PIC16(L)F1778 PIC16(L)F1777/9 PWM10 T2PR T2CON PWMxDCH PWMxDCL PWMxCON Figure 25-1 shows a simplified block diagram of PWM operation. Figure 25-2 shows a typical waveform of the PWM signal. FIGURE 25-1: SIMPLIFIED PWM BLOCK DIAGRAM Duty Cycle registers PWMxDCL<7:6> PWMxDCH Latched (Not visible to user) PWMxOUT to other peripherals: ADC, COG, CLC PRG, DSM, Op Amp override R Comparator Q PWMx 0 PPS S Q 1 RXYPPS TRIS TMR2 Module TMR2 (1) Output Polarity (PWMxPOL) Comparator T2PR Note 1: Clear Timer, PWMx pin and latch Duty Cycle 8-bit timer is concatenated with the two Least Significant bits of 1/FOSC adjusted by the Timer2 prescaler to create a 10-bit time base. For a step-by-step procedure on how to set up this module for PWM operation, refer to Section 25.1.9 "Setup for PWM Operation using PWMx Output Pins". FIGURE 25-2: Period Pulse Width TMR2 = 0 2015-2016 Microchip Technology Inc. PWM OUTPUT TMR2 = T2PR TMR2 = PWMxDCH<7:0>:PWMxDCL<7:6> DS40001819B-page 325 PIC16(L)F1777/8/9 25.1 PWMx Pin Configuration All PWM outputs are multiplexed with the PORT data latch. The user must configure the pins as outputs by clearing the associated TRIS bits. 25.1.1 FUNDAMENTAL OPERATION The PWM module produces a 10-bit resolution output. Timer2 and T2PR set the period of the PWM. The PWMxDCL and PWMxDCH registers configure the duty cycle. The period is common to all PWM modules, whereas the duty cycle is independently controlled. Note: The Timer2 postscaler is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. All PWM outputs associated with Timer2 are set when TMR2 is cleared. Each PWMx is cleared when TMR2 is equal to the value specified in the corresponding PWMxDCH (8 MSb) and PWMxDCL<7:6> (2 LSb) registers. When the value is greater than or equal to T2PR, the PWM output is never cleared (100% duty cycle). Note: The PWMxDCH and PWMxDCL registers are double buffered. The buffers are updated when Timer2 matches T2PR. Care should be taken to update both registers before the timer match occurs. 25.1.2 PWM OUTPUT POLARITY The output polarity is inverted by setting the PWMxPOL bit of the PWMxCON register. 25.1.3 PWM PERIOD The PWM period is specified by the T2PR register of Timer2. The PWM period can be calculated using the formula of Equation 25-1. EQUATION 25-1: PWM PERIOD PWM Period = T2PR + 1 4 T OSC When TMR2 is equal to T2PR, the following three events occur on the next increment cycle: * TMR2 is cleared * The PWM output is active. (Exception: When the PWM duty cycle = 0%, the PWM output will remain inactive.) * The PWMxDCH and PWMxDCL register values are latched into the buffers. Note: 25.1.4 The Timer2 postscaler has no effect on the PWM operation. PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to the PWMxDCH and PWMxDCL register pair. The PWMxDCH register contains the eight MSbs and the PWMxDCL<7:6>, the two LSbs. The PWMxDCH and PWMxDCL registers can be written to at any time. Equation 25-2 is used to calculate the PWM pulse width. Equation 25-3 is used to calculate the PWM duty cycle ratio. EQUATION 25-2: PULSE WIDTH Pulse Width = PWMxDCH:PWMxDCL<7:6> T OS C (TMR2 Prescale Value) Note: TOSC = 1/FOSC EQUATION 25-3: DUTY CYCLE RATIO PWMxDCH:PWMxDCL<7:6> Duty Cycle Ratio = ----------------------------------------------------------------------------------4 T2PR + 1 The 8-bit timer TMR2 register is concatenated with the two Least Significant bits of 1/FOSC, adjusted by the Timer2 prescaler to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. (TMR2 Prescale Value) Note: TOSC = 1/FOSC DS40001819B-page 326 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 25.1.5 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when T2PR is 255. The resolution is a function of the T2PR register value as shown by Equation 25-4. EQUATION 25-4: PWM RESOLUTION log 4 T2PR + 1 Resolution = ---------------------------------------------- bits log 2 Note: If the pulse-width value is greater than the period the assigned PWM pin(s) will remain unchanged. TABLE 25-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 0.31 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 64 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 Timer Prescale T2PR Value Maximum Resolution (bits) TABLE 25-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 0.31 kHz Timer Prescale T2PR Value 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 64 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 Maximum Resolution (bits) 25.1.6 4.90 kHz OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the PWMx pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 25.1.7 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency (FOSC). Any changes in the system clock frequency will result in changes to the PWM frequency. Refer to Section 5.0 "Oscillator Module (with Fail-Safe Clock Monitor)" for additional details. 25.1.8 EFFECTS OF RESET Any Reset will force all ports to Input mode and the PWM registers to their Reset states. 2015-2016 Microchip Technology Inc. DS40001819B-page 327 PIC16(L)F1777/8/9 25.1.9 SETUP FOR PWM OPERATION USING PWMx OUTPUT PINS 25.1.10 SETUP FOR PWM OPERATION TO OTHER DEVICE PERIPHERALS The following steps should be taken when configuring the module for PWM operation using the PWMx output pins: The following steps should be taken when configuring the module for PWM operation to be used by other device peripherals: 1. 1. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s). 2. Clear the PWMxCON register. 3. Load the T2PR register with the PWM period value. 4. Load the PWMxDCH register and bits <7:6> of the PWMxDCL register with the PWM duty cycle value. 5. Configure and start Timer2: * Clear the TMR2IF interrupt flag bit of the PIR1 register. See Note below. * Configure the CKPS bits of the T2CON register with the Timer2 prescale value. * Enable Timer2 by setting the ON bit of the T2CON register. 6. Enable PWM output pin and wait until Timer2 overflows, TMR2IF bit of the PIR1 register is set. See Note below. 7. Enable the PWMx pin output driver(s) by clearing the associated TRIS bit(s) and setting the desired pin PPS control bits. 8. Configure the PWM module by loading the PWMxCON register with the appropriate values. Note 1: In order to send a complete duty cycle and period on the first PWM output, the above steps must be followed in the order given. If it is not critical to start with a complete PWM signal, then move Step 8 to replace Step 4. 2. 3. 4. 5. * * * 6. * 7. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s). Clear the PWMxCON register. Load the T2PR register with the PWM period value. Load the PWMxDCH register and bits <7:6> of the PWMxDCL register with the PWM duty cycle value. Configure and start Timer2: Clear the TMR2IF interrupt flag bit of the PIR1 register. See Note below. Configure the CKPS bits of the T2CON register with the Timer2 prescale value. Enable Timer2 by setting the ON bit of the T2CON register. Enable PWM output pin: Wait until Timer2 overflows, TMR2IF bit of the PIR1 register is set. See Note below. Configure the PWM module by loading the PWMxCON register with the appropriate values. Note: In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. 2: For operation with other peripherals only, disable PWMx pin outputs. DS40001819B-page 328 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 25.2 Register Definitions: 10-Bit PWM Control Long bit name prefixes for the DSM peripherals are shown in Table 25-4. Refer to Section 1.1.2.2 "Long Bit Names" for more information TABLE 25-4: Peripheral Bit Name Prefix PWM3 PWM3 PWM4 PWM4 PWM9 PWM9 PWM10(1) PWM10 Note 1: PIC16(L)F1777/9 only. REGISTER 25-1: PWMxCON: PWM CONTROL REGISTER R/W-0/0 U-0 R-0/0 R/W-0/0 U-0 U-0 U-0 U-0 EN -- OUT POL -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 EN: PWM Module Enable bit 1 = PWM module is enabled 0 = PWM module is disabled bit 6 Unimplemented: Read as `0' bit 5 OUT: PWM module output level when bit is read. bit 4 POL: PWMx Output Polarity Select bit 1 = PWM output is active-low 0 = PWM output is active-high bit 3-0 Unimplemented: Read as `0' 2015-2016 Microchip Technology Inc. DS40001819B-page 329 PIC16(L)F1777/8/9 REGISTER 25-2: R/W-x/u PWMxDCH: PWM DUTY CYCLE HIGH BITS R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u DC<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 DC<9:2>: PWM Duty Cycle Most Significant bits These bits are the MSbs of the PWM duty cycle. The two LSbs are found in the PWMxDCL Register. REGISTER 25-3: R/W-x/u PWMxDCL: PWM DUTY CYCLE LOW BITS R/W-x/u DC<1:0> U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 DC<1:0>: PWM Duty Cycle Least Significant bits These bits are the LSbs of the PWM duty cycle. The MSbs are found in the PWMxDCH Register. bit 5-0 Unimplemented: Read as `0' DS40001819B-page 330 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 25-5: Name SUMMARY OF REGISTERS ASSOCIATED WITH 10-BIT PWM Bit 7 Bit 6 CCPTMRS2 P10TSEL<1:0>(1) PWM3CON EN -- Bit 5 Bit 4 P9TSEL<1:0> OUT DC<1:0> EN -- -- -- OUT POL PWM4DCH DC<1:0> -- EN -- -- OUT POL PWM9DCH DC<1:0> EN -- P3TSEL<1:0> -- -- -- -- -- -- -- -- DC<1:0> RxyPPS -- TxCON ON -- 330 -- -- -- -- 329 -- -- -- -- 330 -- -- -- -- 329 330 330 -- -- -- -- -- -- 330 POL -- -- -- -- 329 -- -- -- 330 -- -- -- -- RxyPPS<5:0> CKPS<2:0> -- 329 330 DC<9:2> PWM10DCL(1) 323 OUT PWM10DCH(1) TxCLKCON Register on Page DC<9:2> PWM9DCL TxPR Bit 0 DC<9:2> PWM4DCL PWM10CON(1) Bit 1 DC<9:2> PWM3DCL PWM9CON Bit 2 P4TSEL<1:0> POL PWM3DCH PWM4CON Bit 3 -- 205 OUTPS<3:0> -- 330 307 CS<3:0> 306 TMRx Period Register 287 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186 Legend: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the PWM. Note 1: PIC16LF1777/9 only. 2015-2016 Microchip Technology Inc. DS40001819B-page 331 PIC16(L)F1777/8/9 26.0 For a more detailed description of each PWM mode, refer to Section 26.2 "PWM Modes". 16-BIT PULSE-WIDTH MODULATION (PWM) MODULE Each PWM module has four offset modes: The Pulse-Width Modulation (PWM) module generates a pulse-width modulated signal determined by the phase, duty cycle, period, and offset event counts that are contained in the following registers: * PWMxPH register * PWMxDC register * PWMxPR register * PWMxOF register Figure 26-1 shows a simplified block diagram of the PWM operation. Each PWM module has four modes of operation: * Standard * Set On Match * Toggle On Match * Center Aligned TABLE 26-1: * * * * Independent Run Slave Run with Synchronous Start One-Shot Slave with Synchronous Start Continuous Run Slave with Synchronous Start and Timer Reset Using the offset modes, each PWM module can offset its waveform relative to any other PWM module in the same device. For a more detailed description of the offset modes refer to Section 26.3 "Offset Modes". Every PWM module has a configurable reload operation to ensure all event count buffers change at the end of a period, thereby avoiding signal glitches. Figure 26-2 shows a simplified block diagram of the reload operation. For a more detailed description of the reload operation, refer to Section Section 26.4 "Reload Operation". AVAILABLE 16-BIT PWM MODULES Device PWM5 PWM6 PIC16(L)F1778 PIC16(L)F1777/9 FIGURE 26-1: PWM11 PWM12 16-BIT PWM BLOCK DIAGRAM MODE<1:0> EN PHx_match Rev. 10-000 152B 4/22/201 4 PWM Control Unit DCx_match D Q4 PWMxOUT Q CK PWMxPOL OF6_match (1) OF5_match (1) PWMx_output 1 OF_match 0 PRx_match PPS OFM<1:0> OFS E PWM_clock Comparator PRx_match set PRIF 16-bt Latch LDx_trigger PWMxPR Comparator DS40001819B-page 332 R U/D RxyPPS PWMxTMR PHx_match set PHIF 16-bt Latch LDx_trigger PWMxPH Note 1: To Peripherals Offset Control Comparator OFx_match set OFIF 16-bt Latch LDx_trigger PWMxOF PWMx TRIS Control Comparator DCx_match set DCIF 16-bt Latch LDx_trigger PWMxDC A PWM module cannot trigger from its own offset match event. The input corresponding to a PWM module's own offset match is reserved. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 26-2: LOAD TRIGGER BLOCK DIAGRAM Rev. 10-000 153B 7/9/201 5 LDx_trigger(1) LDy_trigger 1 PWMxLDS 0 PRx_match PWMxLDT Note 26.1 D PWMxLDA(2) LDx_trigger PWM_clock 1. The input corresponding to a PWM module's own load trigger is reserved. 2. PWMxLDA is cleared by hardware upon LDx_trigger. Fundamental Operation FIGURE 26-3: The PWM module produces a 16-bit resolution pulse-width modulated output. Each PWM module has an independent timer driven by a selection of clock sources determined by the PWMxCLKCON register (Register 26-4). The timer value is compared to event count registers to generate the various events of a the PWM waveform, such as the period and duty cycle. For a block diagram describing the clock sources refer to Figure 26-3. The current state of the PWM output can be read using the OUT bit of the PWMxCON register. In some modes this bit can be set and cleared by software giving additional software control over the PWM waveform. This bit is synchronized to FOSC/4 and therefore does not change in real time with respect to the PWM_clock. If PWM_clock > FOSC/4, the OUT bit may not accurately represent the output state of the PWM. PWM CLOCK SOURCE BLOCK DIAGRAM Rev. 10-000156A 1/7/2015 PWMxCS<1:0> Each PWM module can be enabled individually using the EN bit of the PWMxCON register, or several PWM modules can be enabled simultaneously using the MPWMxEN bits of the PWMEN register. Note: Q 26.1.1 FOSC 00 HFINTOSC 01 LFINTOSC 10 Reserved 11 PWMxPS<2:0> Prescaler PWMx_clock PWMx PIN CONFIGURATION This device uses the PPS control circuitry to route peripherals to any device I/O pin. Select the desired pin, or pins, for PWM output with the device pin RxyPPS control registers (Register 12-2). All PWM outputs are multiplexed with the PORT data latch, so the pins must also be configured as outputs by clearing the associated PORT TRIS bits. The slew rate feature may be configured to optimize the rate to be used in conjunction with the PWM outputs. High-speed output switching is attained by clearing the associated PORT SLRCON bits. The PWM outputs can be configured to be open-drain outputs by setting the associated PORT ODCON bits. 26.1.2 PWMx Output Polarity The output polarity is inverted by setting the POL bit of the PWMxCON register. The polarity control affects the PWM output even when the module is not enabled. 2015-2016 Microchip Technology Inc. DS40001819B-page 333 PIC16(L)F1777/8/9 26.2 PWM Modes PWM modes are selected with MODE<1:0> bits of the PWMxCON register (Register 26-1). In all PWM modes an offset match event can also be used to synchronize the PWMxTMR in three offset modes. See Section 26.3 "Offset Modes" for more information. 26.2.1 STANDARD MODE The Standard mode (MODE = 00) selects a single phase PWM output. The PWM output in this mode is determined by when the period, duty cycle, and phase counts match the PWMxTMR value. The start of the duty cycle occurs on the phase match and the end of the duty cycle occurs on the duty cycle match. The period match resets the timer. The offset match can also be used to synchronize the PWMxTMR in the offset modes. See Section 26.3 "Offset Modes" for more information. Equation 26-1 is used to calculate the PWM period in Standard mode. Equation 26-2 is used to calculate the PWM duty cycle ratio in Standard mode. EQUATION 26-1: PWM PERIOD IN STANDARD MODE PWMxPR + 1 Prescale Period = ---------------------------------------------------------------------PWM _clock The PWMxOUT bit can be used to set or clear the output of the PWM in this mode. Writes to this bit will take place on the next rising edge of the PWM_clock after the bit is written. A detailed timing diagram for Set On Match is shown in Figure 26-5. 26.2.3 TOGGLE ON MATCH MODE The Toggle On Match mode (MODE = 10) generates a 50% duty cycle PWM with a period twice as long as that computed for the standard PWM mode. Duty cycle count has no effect in this mode. The phase count determines how many PWMxTMR periods after a period event the output will toggle. Writes to the OUT bit of the PWMxCON register will have no effect in this mode. A detailed timing diagram for Toggle On Match is shown in Figure 26-6. 26.2.4 CENTER ALIGNED MODE The Center Aligned mode (MODE = 11) generates a PWM waveform that is centered in the period. In this mode the period is two times the PWMxPR count. The PWMxTMR counts up to the period value then counts back down to 0. The duty cycle count determines both the start and end of the active PWM output. The start of the duty cycle occurs at the match event when PWMxTMR is incrementing and the duty cycle ends at the match event when PWMxTMR is decrementing. The incrementing match value is the period count minus the duty cycle count. The decrementing match value is the incrementing match value plus 1. Equation 26-3 is used to calculate the PWM period in Center Aligned mode. EQUATION 26-2: PWM DUTY CYCLE IN STANDARD MODE PWMxDC - PWMx PH Duty Cycle = ----------------------------------------------------------------- PWMxPR + 1 EQUATION 26-3: PWM PERIOD IN CENTER ALIGNED MODE PWMxPR + 1 2 Prescale Period = -----------------------------------------------------------------------------PWM _clock A detailed timing diagram for Standard mode is shown in Figure 26-4. Equation 26-4 is used to calculate the PWM duty cycle ratio in Center Aligned mode 26.2.2 EQUATION 26-4: SET ON MATCH MODE The Set On Match mode (MODE = 01) generates an active output when the phase count matches the PWMxTMR value. The output stays active until the OUT bit of the PWMxCON register is cleared or the PWM module is disabled. The duty cycle count has no effect in this mode. The period count only determines the maximum PWMxTMR value above which no phase matches can occur. PWM DUTY CYCLE IN CENTER ALIGNED MODE PWMxDC 2 Duty Cycle = ------------------------------------------------ PWMx PR + 1 2 Writes to PWMxOUT will have no effect in this mode. A detailed timing diagram for Center Aligned mode is shown in Figure 26-7. DS40001819B-page 334 2015-2016 Microchip Technology Inc. 2015-2016 Microchip Technology Inc. FIGURE 26-4: STANDARD PWM MODE TIMING DIAGRAM Rev. 10-000142A 9/5/2013 Period Duty Cycle Phase PWMxCLK PWMxPR 10 PWMxPH 4 PWMxDC 9 PWMxTMR 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 PWMxOUT FIGURE 26-5: SET ON MATCH PWM MODE TIMING DIAGRAM Period Phase PWMxCLK PWMxPR 10 PWMxPH 4 DS40001819B-page 335 PWMxTMR PWMxOUT 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 PIC16(L)F1777/8/9 Rev. 10-000143A 9/5/2013 TOGGLE ON MATCH PWM MODE TIMING DIAGRAM Rev. 10-000144A 9/5/2013 Period Phase PWMxCLK PWMxPR 10 PWMxPH 4 PWMxTMR 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 PWMxOUT FIGURE 26-7: CENTER ALIGNED PWM MODE TIMING DIAGRAM Rev. 10-000 145A 4/22/201 4 Period Duty Cycle PWMxCLK 2015-2016 Microchip Technology Inc. PWMxPR 6 PWMxDC 4 PWMxTMR PWMxOUT 0 1 2 3 4 5 6 6 5 4 3 2 1 0 0 1 2 3 PIC16(L)F1777/8/9 DS40001819B-page 336 FIGURE 26-6: PIC16(L)F1777/8/9 26.3 Offset Modes The offset modes provide the means to adjust the waveform of a slave PWM module relative to the waveform of a master PWM module in the same device. 26.3.1 INDEPENDENT RUN MODE In Independent Run mode (OFM = 00), the PWM module is unaffected by the other PWM modules in the device. The PWMxTMR associated with the PWM module in this mode starts counting as soon as the EN bit associated with this PWM module is set and continues counting until the EN bit is cleared. Period events reset the PWMxTMR to zero after which the timer continues to count. A detailed timing diagram of this mode used with Standard PWM mode is shown in Figure 26-8. 26.3.2 SLAVE RUN MODE WITH SYNC START In Slave Run mode with Sync Start (OFM = 01), the slave PWMxTMR waits for the master's OF_match event. When this event occurs, if the EN bit is set, the PWMxTMR begins counting and continues to count until software clears the EN bit. Slave period events reset the PWMxTMR to zero after which the timer continues to count. A detailed timing diagram of this mode used with Standard PWM mode is shown in Figure 26-9. 26.3.3 ONE-SHOT SLAVE MODE WITH SYNC START In One-Shot Slave mode with Synchronous Start (OFM = 10), the slave PWMxTMR waits until the master's OF_match event. The timer then begins counting, starting from the value that is already in the timer, and continues to count until the period match event. When the period event occurs the timer resets to zero and stops counting. The timer then waits until the next master OF_match event after which it begins counting again to repeat the cycle. will reset the slave PWMxTMR to zero after which the timer will continue to count. Slaves operating in this mode must have a PWMxPH register pair value equal to or greater than 1, otherwise the phase match event will not occur precluding the start of the PWM output duty cycle. The offset timing will persist if both the master and slave PWMxPR values are the same and the Slave Offset mode is changed to Independent Run mode while the PWM module is operating. A detailed timing diagram of this mode used in Standard PWM mode is shown in Figure 26-11. Note: 26.3.5 Unexpected results will occur if the slave PWM_clock is a higher frequency than the master PWM_clock. OFFSET MATCH IN CENTER ALIGNED MODE When a master is operating in Center-Aligned mode the offset match event depends on which direction the PWMxTMR is counting. Clearing the OFO bit of the PWMxOFCON register will cause the OF_match event to occur when the timer is counting up. Setting the OFO bit of the PWMxOFCON register will cause the OF_match event to occur when the timer is counting down. The OFO bit is ignored in Non-Center-Aligned modes. The OFO bit is double buffered and requires setting the LDA bit to take effect when the PWM module is operating. Detailed timing diagrams of Center-Aligned mode using offset match control in Independent Slave with Sync Start mode can be seen in Figure 26-12 and Figure 26-13. A detailed timing diagram of this mode used with Standard PWM mode is shown in Figure 26-10. 26.3.4 CONTINUOUS RUN SLAVE MODE WITH SYNC START AND TIMER RESET In Continuous Run Slave mode with Synchronous Start and Timer Reset (OFM = 11) the slave PWMxTMR is inhibited from counting after the slave PWM enable is set. The first master OF_match event starts the slave PWMxTMR. Subsequent master OF_match events reset the slave PWMxTMR timer value back to 1 after which the slave PWMxTMR continues to count. The next master OF_match event resets the slave PWMxTMR back to 1 to repeat the cycle. Slave period events that occur before the master's OF_match event 2015-2016 Microchip Technology Inc. DS40001819B-page 337 INDEPENDENT RUN MODE TIMING DIAGRAM Rev. 10-000 146B 7/8/201 5 Period Duty Cycle Phase Offset PWMxCLK PWMxPR 10 PWMxPH 3 PWMxDC 5 PWMxOF 2 PWMxTMR 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 PWMxOUT OFx_match PHx_match DCx_match PRx_match 2015-2016 Microchip Technology Inc. PWMyTMR PWMyPR 4 PWMyPH 0 PWMyDC 1 PWMyOUT Note: PWMx = Master, PWMy = Slave PIC16(L)F1777/8/9 DS40001819B-page 338 FIGURE 26-8: 2015-2016 Microchip Technology Inc. FIGURE 26-9: SLAVE RUN MODE WITH SYNC START TIMING DIAGRAM Rev. 10-000 147B 7/8/201 5 Period Duty Cycle Phase Offset PWMxCLK PWMxPR 10 PWMxPH 3 PWMxDC 5 PWMxOF 2 PWMxTMR 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 PWMxOUT OFx_match PWMyTMR 0 4 PWMyPH 0 PWMyDC 1 PWMyOUT Note: Master = PWMx, Slave = PWMy DS40001819B-page 339 PIC16(L)F1777/8/9 PWMyPR ONE-SHOT SLAVE RUN MODE WITH SYNC START TIMING DIAGRAM Rev. 10-000 148B 7/8/201 5 Period Duty Cycle Phase Offset PWMxCLK PWMxPR 10 PWMxPH 3 PWMxDC 5 PWMxOF 2 PWMxTMR 0 1 2 3 4 5 6 1 2 3 4 7 8 9 10 0 1 2 3 4 5 6 1 2 3 4 PWMxOUT OFx_match PWMyTMR 0 0 PWMyPR 4 PWMyPH 0 PWMyDC 1 2015-2016 Microchip Technology Inc. PWMyOUT Note: Master = PWMx, Slave = PWMy PIC16(L)F1777/8/9 DS40001819B-page 340 FIGURE 26-10: 2015-2016 Microchip Technology Inc. FIGURE 26-11: CONTINUOUS SLAVE RUN MODE WITH IMMEDIATE RESET AND SYNC START TIMING DIAGRAM Rev. 10-000 149B 7/8/201 5 Period Duty Cycle Phase Offset PWMxCLK PWMxPR 10 PWMxPH 3 PWMxDC 5 PWMxOF 2 PWMxTMR 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 1 2 3 4 0 1 2 3 4 0 1 1 2 3 4 PWMxOUT OFx_match PWMyTMR 0 4 PWMyPH 1 PWMyDC 2 PWMyOUT Note: Master= PWMx, Slave=PWMy DS40001819B-page 341 PIC16(L)F1777/8/9 PWMyPR OFFSET MATCH ON INCREMENTING TIMER TIMING DIAGRAM Rev. 10-000 150B 7/9/201 5 Period Duty Cycle Offset PWMxCLK PWMxPR 6 PWMxDC 2 PWMxOF 2 PWMxTMR 0 1 2 3 4 5 6 6 5 4 3 2 0 1 2 3 4 4 3 2 1 0 1 0 0 1 2 3 0 1 PWMxOUT OFx_match PHx_match DCx_match PRx_match PWMyTMR 0 2015-2016 Microchip Technology Inc. PWMyPR 4 PWMyDC 1 PWMyOUT Note: Master = PWMx, Slave = PWMy 0 PIC16(L)F1777/8/9 DS40001819B-page 342 FIGURE 26-12: 2015-2016 Microchip Technology Inc. FIGURE 26-13: OFFSET MATCH ON DECREMENTING TIMER TIMING DIAGRAM Rev. 10-000 151B 7/9/201 5 Period Duty Cycle Offset PWMxCLK PWMxPR 6 PWMxDC 2 PWMxOF 2 PWMxTMR 0 1 2 3 4 5 6 6 5 4 3 2 1 0 0 1 2 3 0 1 2 3 4 4 3 PWMxOUT OF5_match PH5_match DC5_match PWMyTMR 0 PWMyPR 4 PWMyDC 1 PWMyOUT Note: Master = PWMx, Slave = PWMy DS40001819B-page 343 PIC16(L)F1777/8/9 PR5_match PIC16(L)F1777/8/9 26.4 Reload Operation Four of the PWM module control register pairs and one control bit are double buffered so that all can be updated simultaneously. These include: * * * * * PWMxPHH:PWMxPHL register pair PWMxDCH:PWMxDCL register pair PWMxPRH:PWMxPRL register pair PWMxOFH:PWMxOFL register pair ODO control bit When written to, these registers do not immediately affect the operation of the PWM. By default, writes to these registers will not be loaded into the PWM operating buffer registers until after the arming conditions are met. The arming control has two methods of operation: 26.5 Operation in Sleep Mode Each PWM module will continue to operate in Sleep mode when either the HFINTOSC or LFINTOSC is selected as the clock source by PWMxCLKCON<1:0>. 26.6 Interrupts Each PWM module has four independent interrupts based on the phase, duty cycle, period, and offset match events. The interrupt flag is set on the rising edge of each of these signals. Refer to Figures 26-8 and 26-12 for detailed timing diagrams of the match signals. * Immediate * Triggered The LDT bit of the PWMxLDCON register controls the arming method. Both methods require the LDA bit to be set. All four buffer pairs will load simultaneously at the loading event. 26.4.1 IMMEDIATE RELOAD When the LDT bit is clear then the Immediate mode is selected and the buffers will be loaded at the first period event after the LDA bit is set. Immediate reloading is used when a PWM module is operating stand-alone or when the PWM module is operating as a master to other slave PWM modules. 26.4.2 TRIGGERED RELOAD When the LDT bit is set then the Triggered mode is selected and a trigger event is required for the LDA bit to take effect. The trigger source is the buffer load event of one of the other PWM modules in the device. The triggering source is selected by the LDS<1:0> bits of the PWMxLDCON register. The buffers will be loaded at the first period event following the trigger event. Triggered reloading is used when a PWM module is operating as a slave to another PWM and it is necessary to synchronize the buffer reloads in both modules. Note 1: The buffer load operation clears the LDA bit. 2: If the LDA bit is set at the same time as PWMxTMR = PWMxPR, the LDA bit is ignored until the next period event. Such is the case when triggered reload is selected and the triggering event occurs simultaneously with the target's period event DS40001819B-page 344 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 26.7 Register Definitions: PWM Control Long bit name prefixes for the 16-bit PWM peripherals are shown in Table 26-2. Refer to Section 1.1 "Register and Bit naming conventions" for more information TABLE 26-2: Peripheral Bit Name Prefix PWM5 PWM5 PWM6 PWM6 PWM11 PWM11 PWM12(1) PWM12 Note 1: PIC16(L)F1777/9 only. REGISTER 26-1: PWMxCON: PWM CONTROL REGISTER R/W-0/0 U-0 R/HS/HC-0/0 R/W-0/0 EN -- OUT POL R/W-0/0 R/W-0/0 U-0 U-0 -- -- MODE<1:0> bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 EN: PWM Module Enable bit 1 = Module is enabled 0 = Module is disabled bit 6 Unimplemented: Read as `0' bit 5 OUT: Output State of the PWM module bit 4 POL: PWM Output Polarity Control bit 1 = PWM output active state is low 0 = PWM output active state is high bit 3-2 MODE<1:0>: PWM Mode Control bits 11 = Center Aligned mode 10 = Toggle On Match mode 01 = Set On Match mode 00 = Standard PWM mode bit 1-0 Unimplemented: Read as `0' 2015-2016 Microchip Technology Inc. DS40001819B-page 345 PIC16(L)F1777/8/9 REGISTER 26-2: PWMxINTE: PWM INTERRUPT ENABLE REGISTER U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- -- -- OFIE PHIE DCIE PRIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3 OFIE: Offset Interrupt Enable bit 1 = Interrupt CPU on Offset Match 0 = Do not interrupt CPU on Offset Match bit 2 PHIE: Phase Interrupt Enable bit 1 = Interrupt CPU on Phase Match 0 = Do not Interrupt CPU on Phase Match bit 1 DCIE: Duty Cycle Interrupt Enable bit 1 = Interrupt CPU on Duty Cycle Match 0 = Do not interrupt CPU on Duty Cycle Match bit 0 PRIE: Period Interrupt Enable bit 1 = Interrupt CPU on Period Match 0 = Do not interrupt CPU on Period Match REGISTER 26-3: PWMxINTF: PWM INTERRUPT REQUEST REGISTER U-0 U-0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 -- -- -- -- OFIF PHIF DCIF PRIF bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3 OFIF: Offset Interrupt Flag bit(1) 1 = Offset Match Event occurred 0 = Offset Match Event did not occur bit 2 PHIF: Phase Interrupt Flag bit(1) 1 = Phase Match Event occurred 0 = Phase Match Event did not occur bit 1 DCIF: Duty Cycle Interrupt Flag bit(1) 1 = Duty Cycle Match Event occurred 0 = Duty Cycle Match Event did not occur bit 0 PRIF: Period Interrupt Flag bit(1) 1 = Period Match Event occurred 0 = Period Match Event did not occur Note 1: Bit is forced clear by hardware while module is disabled (EN = 0). DS40001819B-page 346 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 26-4: U-0 PWMxCLKCON: PWM CLOCK CONTROL REGISTER R/W-0/0 -- R/W-0/0 R/W-0/0 PS<2:0> U-0 U-0 -- -- R/W-0/0 R/W-0/0 CS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6-4 PS<2:0>: Clock Source Prescaler Select bits 111 = Divide clock source by 128 110 = Divide clock source by 64 101 = Divide clock source by 32 100 = Divide clock source by 16 011 = Divide clock source by 8 010 = Divide clock source by 4 001 = Divide clock source by 2 000 = No Prescaler bit 3-2 Unimplemented: Read as `0' bit 1-0 CS<1:0>: Clock Source Select bits 11 = Reserved 10 = LFINTOSC (continues to operate during Sleep) 01 = HFINTOSC (continues to operate during Sleep) 00 = FOSC 2015-2016 Microchip Technology Inc. DS40001819B-page 347 PIC16(L)F1777/8/9 REGISTER 26-5: PWMxLDCON: PWM RELOAD TRIGGER SOURCE SELECT REGISTER R/W/HC-0/0 R/W-0/0 U-0 U-0 U-0 U-0 LDA(1) LDT -- -- -- -- R/W-0/0 R/W-0/0 LDS<1:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Cleared by hardware bit 7 LDA: Load Buffer Armed bit(1) If LDT = 1: 1 = Load the ODO bit and OFx, PHx, DCx and PRx buffers at the end of the period in which the selected trigger occurs 0 = Do not load buffers, load has completed If LDT = 0: 1 = Load the ODO bit and OFx, PHx, DCx and PRx buffers at the end of the current period 0 = Do not load buffers, load has completed bit 6 LDT: Load Buffer on Trigger bit 1 = Wait for trigger selected by the LDS<1:0> bits to occur before enabling the LDA bit 0 = Load triggering is disabled. Buffer loads are controlled by the LDA bit alone. bit 5-2 Unimplemented: Read as `0' bit 1-0 LDS<1:0>: Load Trigger Source Select bits(2) 10 = LD11_trigger 01 = LD6_trigger 00 = LD5_trigger Note 1: 2: This bit is cleared by the module after a reload operation. It can be cleared in software to clear an existing arming event. The source corresponding to a PWM module's own LDx_trigger is reserved. DS40001819B-page 348 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 26-6: U-0 PWMxOFCON: PWM OFFSET TRIGGER SOURCE SELECT REGISTER R/W-0/0 -- R/W-0/0 OFM<1:0> R/W-0/0 (1) OFO U-0 U-0 -- -- R/W-0/0 R/W-0/0 OFS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6-5 OFM<1:0>: Offset Mode Select bits 11 = Continuous Run Slave mode with offset triggered timer Reset and synchronized start 10 = One-shot Slave mode with offset triggered synchronized start 01 = Slave Run mode with offset triggered synchronized start 00 = Independent Run mode bit 4 OFO: Offset Match Output Control bit(1) If MODE<1:0> = 11 (PWM center aligned mode): 1 = OFx_match occurs when the PWMxTMR is counting up 0 = OFx_match occurs when the PWMxTMR is counting down If MODE<1:0> = 00, 01, or 10 (all other modes): this bit is ignored bit 3-2 Unimplemented: Read as `0' bit 1-0 OFS<1:0>: Offset Trigger Source Select bit 10 = OF11_match 01 = OF6_match 00 = OF5_match Note 1: The source corresponding to the PWM module's own OFx_match is reserved. 2015-2016 Microchip Technology Inc. DS40001819B-page 349 PIC16(L)F1777/8/9 REGISTER 26-7: R/W-x/u PWMxPHH: PWMx PHASE COUNT HIGH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PH<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 PH<15:8>: PWM Phase High bits Upper eight bits of PWM phase count REGISTER 26-8: R/W-x/u PWMxPHL: PWMx PHASE COUNT LOW REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PH<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 PH<7:0>: PWM Phase Low bits Lower eight bits of PWM phase count DS40001819B-page 350 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 26-9: R/W-x/u PWMxDCH: PWMx DUTY CYCLE COUNT HIGH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u DC<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 DC<15:8>: PWM Duty Cycle High bits Upper eight bits of PWM duty cycle count REGISTER 26-10: PWMxDCL: PWMx DUTY CYCLE COUNT LOW REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u DC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 DC<7:0>: PWM Duty Cycle Low bits Lower eight bits of PWM duty cycle count 2015-2016 Microchip Technology Inc. DS40001819B-page 351 PIC16(L)F1777/8/9 REGISTER 26-11: PWMxPRH: PWMx PERIOD COUNT HIGH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PR<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 PR<15:8>: PWM Period High bits Upper eight bits of PWM period count REGISTER 26-12: PWMxPRL: PWMx PERIOD COUNT LOW REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 PR<7:0>: PWM Period Low bits Lower eight bits of PWM period count DS40001819B-page 352 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 26-13: PWMxOFH: PWMx OFFSET COUNT HIGH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u OF<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 OF<15:8>: PWM Offset High bits Upper eight bits of PWM offset count REGISTER 26-14: PWMxOFL: PWMx OFFSET COUNT LOW REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u OF<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 OF<7:0>: PWM Offset Low bits Lower eight bits of PWM offset count 2015-2016 Microchip Technology Inc. DS40001819B-page 353 PIC16(L)F1777/8/9 REGISTER 26-15: PWMxTMRH: PWMx TIMER HIGH REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 TMR<15:8>: PWM Timer High bits Upper eight bits of PWM timer counter REGISTER 26-16: PWMxTMRL: PWMx TIMER LOW REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 TMR<7:0>: PWM Timer Low bits Lower eight bits of PWM timer counter DS40001819B-page 354 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 Note: There are no long and short bit name variants for the following three mirror registers REGISTER 26-17: PWMEN: PWMEN BIT MIRROR REGISTER U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- -- -- MPWM12EN(1) MPWM11EN MPWM6EN MPWM5EN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-3 Unimplemented: Read as `0' bit 2-0 PWMxEN: PWM11/PWM6/PWM5 Enable bits Mirror copy of each PWM module's PWMxCON<7> bit Note 1: PIC16(L)F1777/9 only. REGISTER 26-18: PWMLD: LDA BIT MIRROR REGISTER U-0 U-0 -- U-0 -- -- U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- MPWM12LD(1) MPWM11LD MPWM6LD MPWM5LD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-3 Unimplemented: Read as `0' bit 2 MPWM11LD: PWM11LD bits Mirror copy of each PWM module's PWMxLDCON<7> bit bit 1 MPWM6LD: PWM6LD bits Mirror copy of each PWM module's PWMxLDCON<7> bit bit 0 MPWM5LD: PWM5LD bits Mirror copy of each PWM module's PWMxLDCON<7> bit Note 1: PIC16(L)F1777/9 only. REGISTER 26-19: PWMOUT: PWMOUT BIT MIRROR REGISTER U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- -- -- MPWM12OUT(1) MPWM11OUT MPWM6OUT MPWM5OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-3 Unimplemented: Read as `0' bit 2 MPWM11OUT: PWM11 OUT bits Mirror copy of each PWM module's PWMxCON<5> bit bit 1 MPWM6OUT: PWM6 OUT bits Mirror copy of each PWM module's PWMxCON<5> bit bit 0 MPWM5OUT: PWM5 OUT bits Mirror copy of each PWM module's PWMxCON<5> bit Note 1: PIC16(L)F1777/9 only. 2015-2016 Microchip Technology Inc. DS40001819B-page 355 PIC16(L)F1777/8/9 TABLE 26-3: SUMMARY OF REGISTERS ASSOCIATED WITH PWM Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 OSCCON SPLLEN PWMEN -- -- -- IRCF<3:0> -- MPWM12EN(1) MPWM11EN PWMLD -- -- -- -- MPWM12LD(1) MPWM11LD PWMOUT -- -- -- -- -- MPWM12OUT(1) MPWM11OUT Bit 0 Register on Page MPWM5EN 355 Bit 1 SCS<1:0> MPWM6EN 116 MPWM6LD MPWM5LD 355 MPWM6OUT MPWM5OUT 355 PWM5PHL PH<7:0> 350 PWM5PHH PH<15:8> 350 PWM5DCL DC<7:0> 351 PWM5DCH DC<15:8> 351 PWM5PRL PR<7:0> 352 PWM5PRH PR<15:8> 352 PWM5OFL OF<7:0> 353 PWM5OFH OF<15:8> 353 PWM5TMRL TMR<7:0> 354 PWM5TMRH TMR<15:8> 354 PWM5CON EN -- OUT POL PWM5INTE -- -- -- -- OFIE PHIE DCIE PRIE 346 PWM5INTF -- -- -- -- OFIF PHIF DCIF PRIF 346 PWM5CLKCON -- PWM5LDCON LDA PWM5OFCON -- PS<2:0> LDT -- OFM<1:0> MODE<1:0> -- -- 345 -- -- CS<1:0> 347 -- -- -- LDS<1:0> 348 OFO -- -- OFS<1:0> 349 PWM6PHL PH<7:0> 350 PWM6PHH PH<15:8> 350 PWM6DCL DC<7:0> 351 PWM6DCH DC<15:8> 351 PWM6PRL PR<7:0> 352 PWM6PRH PR<15:8> 352 PWM6OFL OF<7:0> 353 PWM6OFH OF<15:8> 353 PWM6TMRL TMR<7:0> 354 PWM6TMRH TMR<15:8> PWM6CON EN -- OUT POL PWM6INTE -- -- -- -- OFIE PWM6INTF -- -- -- -- PWM6CLKCON -- PWM6LDCON LDA PWM6OFCON -- -- -- 345 PHIE DCIE PRIE 346 OFIF PHIF DCIF PRIF 346 -- -- CS<1:0> 347 -- -- -- LDS<1:0> 348 OFO -- -- OFS<1:0> 349 PS<2:0> LDT -- OFM<1:0> 354 MODE<1:0> PWM11PHL PH<7:0> 350 PWM11PHH PH<15:8> 350 PWM11DCL DC<7:0> 351 PWM11DCH DC<15:8> 351 PWM11PRL PR<7:0> 352 PWM11PRH PR<15:8> 352 PWM11OFL OF<7:0> 353 PWM11OFH OF<15:8> 353 PWM11TMRL TMR<7:0> 354 PWM11TMRH TMR<15:8> PWM11CON EN -- OUT POL PWM11INTE -- -- -- -- OFIE PWM11INTF -- -- -- -- PWM11CLKCON -- PWM11LDCON Legend: Note 1: LDA PS<2:0> LDT -- -- 354 MODE<1:0> -- -- 345 PHIE DCIE PRIE 346 OFIF PHIF DCIF PRIF 346 -- -- CS<1:0> 347 -- -- LDS<1:0> 348 -- = unimplemented location, read as `0'. Shaded cells are not used by PWM. PIC16(L)F1777/9 only. DS40001819B-page 356 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 26-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH PWM (CONTINUED) Bit 7 PWM11OFCON Bit 6 -- Bit 5 OFM<1:0> Bit 4 Bit 3 Bit 2 -- -- OFO Bit 1 Bit 0 OFS<1:0> Register on Page 349 PWM12PHL(1) PH<7:0> PWM12PHH(1) PH<15:8> 350 PWM12DCL(1) DC<7:0> 351 PWM12DCH(1) DC<15:8> 351 PWM12PRL(1) PR<7:0> 352 PWM12PRH(1) PR<15:8> 352 PWM12OFL(1) OF<7:0> 353 PWM12OFH(1) OF<15:8> 353 PWM12TMRL(1) TMR<7:0> 354 PWM12TMRH(1) TMR<15:8> 350 354 PWM12CON(1) EN -- OUT POL PWM12INTE(1) -- -- -- -- OFIE PWM12INTF(1) -- -- -- -- PWM12CLKCON(1) -- PWM12LDCON(1) LDA PWM12OFCON(1) -- Legend: Note 1: CONFIG1 Legend: -- 345 PHIE DCIE PRIE 346 OFIF PHIF DCIF PRIF 346 -- -- CS<1:0> LDT -- 347 -- -- -- LDS<1:0> OFM<1:0> 348 OFO -- -- OFS<1:0> 349 -- = unimplemented location, read as `0'. Shaded cells are not used by PWM. PIC16(L)F1777/9 only. TABLE 26-4: Name -- PS<2:0> MODE<1:0> Bits SUMMARY OF CONFIGURATION WORDS WITH CLOCK SOURCES Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 IESO CLKOUTEN 13:8 -- -- FCMEN 7:0 CP MCLRE PWRTE Bit 10/2 Bit 9/1 Bit 8/0 BOREN<1:0> WDTE<1:0> -- FOSC<2:0> Register on Page 95 -- = unimplemented location, read as `0'. Shaded cells are not used by clock sources. 2015-2016 Microchip Technology Inc. DS40001819B-page 357 PIC16(L)F1777/8/9 NOTES: DS40001819B-page 358 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 27.0 COMPLEMENTARY OUTPUT GENERATOR (COG) MODULES The primary purpose of the Complementary Output Generator (COG) is to convert a single-output PWM signal into a two-output complementary PWM signal. The COG can also convert two separate input events into a single or complementary PWM output. TABLE 27-1: AVAILABLE COG MODULES Device COG1 COG2 COG3 COG4 PIC16(L)F1778 PIC16(L)F1777/9 The COG PWM frequency and duty cycle are determined by a rising event input and a falling event input. The rising event and falling event may be the same source. Sources may be synchronous or asynchronous to the COG_clock. The rate at which the rising event occurs determines the PWM frequency. The time from the rising event to the falling event determines the duty cycle. A selectable clock input is used to generate the phase delay, blanking, and dead-band times. Dead-band time can also be generated with a programmable delay chain, which is independent from all clock sources. Simplified block diagrams of the various COG modes are shown in Figure 27-2 through Figure 27-6. The COG module has the following features: * Six modes of operation: - Steered PWM mode - Synchronous Steered PWM mode - Forward Full-Bridge mode - Reverse Full-Bridge mode - Half-Bridge mode - Push-Pull mode * Selectable COG_clock clock source * Independently selectable rising event sources * Independently selectable falling event sources * Independently selectable edge or level event sensitivity * Independent output polarity selection * Phase delay with independent rising and falling delay times * Dead-band control with: - independent rising and falling event dead-band times - Synchronous and asynchronous timing * Blanking control with independent rising and falling event blanking times * Auto-shutdown control with: - Independently selectable shutdown sources - Auto-restart enable - Auto-shutdown pin override control (high, low, off, and High-Z) 2015-2016 Microchip Technology Inc. 27.1 Output to Pins (all modes) The COG peripheral has four outputs: COGA, COGB, COGC, and COGD. The operating mode, selected with the MD<2:0> bits of the COGxCON0 register, determine the waveform available at each output. An individual peripheral source control for each device pin selects the pin or pins at which the outputs will appear. Please refer to the RxyPPS register (Register 12-2) for more information. 27.2 Event-Driven PWM (All Modes) Besides generating PWM and complementary outputs from a single PWM input, the COG can also generate PWM waveforms from a periodic rising event and a separate falling event. In this case, the falling event is usually derived from analog feedback within the external PWM driver circuit. In this configuration, high-power switching transients may trigger a false falling event that needs to be blanked out. The COG can be configured to blank falling (and rising) event inputs for a period of time immediately following the rising (and falling) event drive output. This is referred to as input blanking and is covered in Section 27.8 "Blanking Control". It may be necessary to guard against the possibility of external circuit faults. In this case, the active drive must be terminated before the Fault condition causes damage. This is referred to as auto-shutdown and is covered in Section 27.10 "Auto-Shutdown Control". The COG can be configured to operate in phase delayed conjunction with another PWM. The active drive cycle is delayed from the rising event by a phase delay timer. Phase delay is covered in more detail in Section 27.9 "Phase Delay". A typical operating waveform, with phase delay and dead band, generated from a single CCP1 input is shown in Figure 27-10. DS40001819B-page 359 PIC16(L)F1777/8/9 27.3 27.3.1 27.3.2 Modes of Operation STEERED PWM MODES In Steered PWM mode, the PWM signal derived from the input event sources is output as a single phase PWM which can be steered to any combination of the four COG outputs. Output steering takes effect on the instruction cycle following the write to the COGxSTR register. Synchronous Steered PWM mode is identical to the Steered PWM mode except that changes to the output steering take effect on the first rising event after the COGxSTR register write. Static output data is not synchronized. Steering mode configurations are shown in Figure 27-2 and Figure 27-3. Steered PWM and Synchronous Steered PWM modes are selected by setting the MD<2:0> bits of the COGxCON0 register (Register 27-1) to `000' and `001', respectively. FIGURE 27-1: FULL-BRIDGE MODES In both Forward and Reverse Full-Bridge modes, two of the four COG outputs are active and the other two are inactive. Of the two active outputs, one is modulated by the PWM input signal and the other is on at 100% duty cycle. When the direction is changed, the dead-band time is inserted to delay the modulated output. This gives the unmodulated driver time to shut down, thereby, preventing shoot-through current in the series connected power devices. In Forward Full-Bridge mode, the PWM input modulates the COGxD output and drives the COGA output at 100%. In Reverse Full-Bridge mode, the PWM input modulates the COGxB output and drives the COGxC output at 100%. The full-bridge configuration is shown in Figure 27-4. Typical full-bridge waveforms are shown in Figure 27-12 and Figure 27-13. Full-Bridge Forward and Full-Bridge Reverse modes are selected by setting the MD<2:0> bits of the COGxCON0 register to `010' and `011', respectively. EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET Driver QC QA FET Driver COGxA Load COGxB FET Driver COGxC FET Driver QD QB VCOGxD DS40001819B-page 360 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 27.3.3 HALF-BRIDGE MODE In Half-Bridge mode, the COG generates a two output complementary PWM waveform from rising and falling event sources. In the simplest configuration, the rising and falling event sources are the same signal, which is a PWM signal with the desired period and duty cycle. The COG converts this single PWM input into a dual complementary PWM output. The frequency and duty cycle of the dual PWM output match those of the single input PWM signal. The off-to-on transition of each output can be delayed from the on-to-off transition of the other output, thereby, creating a time immediately after the PWM transition where neither output is driven. This is referred to as dead-band time and is covered in Section 27.7 "Dead-Band Control". The half-bridge configuration is shown in Figure 27-5. A typical operating waveform, with dead band, generated from a single CCP1 input is shown in Figure 27-9. The primary output is available on either, or both, COGxA and COGxC. The complementary output is available on either, or both, COGxB and COGxD. Half-Bridge mode is selected by setting the MD<2:0> bits of the COGxCON0 register to `100'. 27.3.4 PUSH-PULL MODE In Push-Pull mode, the COG generates a single PWM output that alternates between the two pairs of the COG outputs at every PWM period. COGxA has the same signal as COGxC. COGxB has the same signal as COGxD. The output drive activates with the rising input event and terminates with the falling event input. Each rising event starts a new period and causes the output to switch to the COG pair not used in the previous period. The Push-Pull configuration is shown in Figure 27-6. A typical Push-Pull waveform generated from a single CCP1 input is shown in Figure 27-11. Push-Pull mode is selected by setting the MD<2:0> bits of the COGxCON0 register to `101'. 2015-2016 Microchip Technology Inc. DS40001819B-page 361 SIMPLIFIED COG BLOCK DIAGRAM (STEERED PWM MODE, MD = 0) ASDAC<1:0> `1' `0' Hi-Z Reserved HFINTOSC 11 10 Fosc Fosc/4 01 00 CS<1:0> COG_clock 1 0 POLA SDATA 0 STRA Rising Input Block src15 ASDBD<1:0> clock `1' `0' Hi-Z Reset Dominates rising_event S Q count_en POLB 1 COGxB SDATB 0 0 STRB Falling Input Block ASDAC<1:0> `1' `0' Hi-Z clock src15 11 10 01 00 1 falling_event COGxC 1 src0 count_en POLC SDATC 0 0 STRC ASDBD<1:0> `1' `0' Hi-Z EN 2015-2016 Microchip Technology Inc. Source 7 AS7E 11 10 01 00 1 COGxD 1 POLD Auto-shutdown source Source 0 AS0E Write ASE High 11 10 01 00 1 R Q src0 Shutdown sources See Register 27-12. COGxA 1 Rising event sources See Register 27-3 and Register 27-4. Falling event sources See Register 27-7 and Register 27-8. 11 10 01 00 SDATD 0 0 STRD ASE S Q ARSEN Write ASE Low R Set Dominates S D Q PIC16(L)F1777/8/9 DS40001819B-page 362 FIGURE 27-2: 2015-2016 Microchip Technology Inc. FIGURE 27-3: SIMPLIFIED COG BLOCK DIAGRAM (SYNCHRONOUS STEERED PWM MODE, MD = 1) ASDAC<1:0> `1' `0' High-Z Reserved HFINTOSC 11 10 Fosc Fosc/4 01 00 CS<1:0> COG_clock 1 0 POLA STRA Rising Input Block src15 0 D Q ASDBD<1:0> `1' `0' High-Z Reset Dominates S Q rising_event POLB STRB Falling Input Block 11 10 01 00 1 COGxB 1 R Q count_en src15 SDATA clock src0 SDATB 0 0 D Q ASDAC<1:0> `1' `0' High-Z clock 11 10 01 00 1 falling_event COGxC 1 src0 POLC STRC SDATC 0 0 D Q ASDBD<1:0> `1' `0' High-Z EN Source 7 AS7E 11 10 01 00 1 COGxD 1 Auto-shutdown source POLD STRD SDATD 0 0 D Q DS40001819B-page 363 Source 0 AS0E ASE S Q Write ASE High ARSEN Write ASE Low R Set Dominates S D Q PIC16(L)F1777/8/9 count_en Shutdown sources See Register 27-12. COGxA 1 Rising event sources See Register 27-3 and Register 27-4. Falling event sources See Register 27-7 and Register 27-8. 11 10 01 00 SIMPLIFIED COG BLOCK DIAGRAM (FULL-BRIDGE MODES, FORWARD: MD = 2, REVERSE: MD = 3) ASDAC<1:0> `1' `0' High-Z Reserved HFINTOSC 11 10 Fosc Fosc/4 01 00 CS<1:0> 11 10 01 00 COG_clock 1 Rising Dead-Band Block Rising Input Block src15 Rising event sources See Register 27-3 and Register 27-4. clock clock Reset Dominates POLA ASDBD<1:0> signal_out signal_in `1' `0' High-Z S Q rising_event 11 10 01 00 COGxB 0 count_en Falling Input Block src15 1 R Q src0 Falling event sources See Register 27-7 and Register 27-8. COGxA 0 Falling Dead-Band Block ASDAC<1:0> POLB `1' `0' High-Z clock clock signal_out signal_in 11 10 01 00 1 falling_event src0 COGxC 0 count_en Forward/Reverse MD0 2015-2016 Microchip Technology Inc. EN ASDBD<1:0> `1' `0' High-Z D Q Q Source 7 AS7E Shutdown sources See Register 27-12. POLC 1 COGxD 0 Auto-shutdown source POLD Source 0 AS0E ASE S Q Write ASE High 11 10 01 00 ARSEN Write ASE Low R Set Dominates S D Q PIC16(L)F1777/8/9 DS40001819B-page 364 FIGURE 27-4: 2015-2016 Microchip Technology Inc. FIGURE 27-5: SIMPLIFIED COG BLOCK DIAGRAM (HALF-BRIDGE MODE, MD = 4) ASDAC<1:0> `1' `0' High-Z reserved HFINTOSC 11 10 Fosc Fosc/4 01 00 CS<1:0> 11 10 01 00 COG_clock 1 COGxA 0 Rising Input Block src15 Rising event sources See Register 27-3 and Register 27-4. Rising Dead-Band Block clock Reset Dominates rising_event S Q POLA ASDBD<1:0> `1' `0' High-Z clock signal_out signal_in 11 10 01 00 Falling Input Block Falling event sources See Register 27-7 and Register 27-8. COGxB 0 count_en src15 1 R Q src0 Falling Dead-Band Block ASDAC<1:0> POLB `1' `0' High-Z clock clock signal_out signal_in 11 10 01 00 1 falling_event src0 COGxC 0 POLC Source 7 AS7E Shutdown sources See Register 27-12. ASDBD<1:0> `1' `0' High-Z EN 1 COGxD 0 Auto-shutdown source DS40001819B-page 365 POLD Source 0 AS0E ASE S Q Write ASE High 11 10 01 00 ARSEN Write ASE Low R Set Dominates S D Q PIC16(L)F1777/8/9 count_en SIMPLIFIED COG BLOCK DIAGRAM (PUSH-PULL MODE, MD = 5) ASDAC<1:0> `1' `0' High-Z reserved HFINTOSC 11 10 Fosc Fosc/4 01 00 CS<1:0> 11 10 01 00 COG_clock 1 Rising Input Block src15 POLA ASDBD<1:0> Push-Pull clock Reset Dominates Rising event sources See Register 27-3 and Register 27-4. rising_event S Q src0 `1' `0' High-Z D Q R Q 11 10 01 00 R Q src15 COGxB ASDAC<1:0> POLB Falling Input Block 1 0 count_en Falling event sources See Register 27-7 and Register 27-8. COGxA 0 `1' `0' High-Z clock 11 10 01 00 1 falling_event src0 COGxC 0 count_en POLC 2015-2016 Microchip Technology Inc. Source 7 AS7E Shutdown sources See Register 27-12. ASDBD<1:0> `1' `0' High-Z EN 1 COGxD 0 Auto-shutdown source POLD Source 0 AS0E ASE S Q Write ASE High 11 10 01 00 ARSEN Write ASE Low R Set Dominates S D Q PIC16(L)F1777/8/9 DS40001819B-page 366 FIGURE 27-6: PIC16(L)F1777/8/9 FIGURE 27-7: COG (RISING/FALLING) INPUT BLOCK clock PH(R/F)<3:0> Blanking = Cnt/Clr count_en Phase Delay BLK(F/R)<3:0> src15 (R/F)IS15 (R/F)SIM15 D Q 1 LE 0 (rising/falling)_event src1 through src14 (R/F)IS1 through (R/F)IS14 (R/F)SIM1 through (R/F)SIM14 src0 (R/F)IS0 (R/F)SIM0 FIGURE 27-8: D Q 1 LE 0 COG (RISING/FALLING) DEAD-BAND BLOCK (R/F)DBTS Synchronous Delay = Cnt/Clr clock 0 0 1 DBR<3:0> 1 Asynchronous Delay Chain signal_in 2015-2016 Microchip Technology Inc. signal_out DS40001819B-page 367 PIC16(L)F1777/8/9 FIGURE 27-9: TYPICAL HALF-BRIDGE MODE COG OPERATION WITH CCP1 COG_clock Source CCP1 COGxA rising event dead band falling event dead band falling event dead band COGxB FIGURE 27-10: HALF-BRIDGE MODE COG OPERATION WITH CCP1 AND PHASE DELAY COG_clock Source CCP1 COGxA falling event dead band Phase Delay rising event dead band falling event dead band COGxB FIGURE 27-11: PUSH-PULL MODE COG OPERATION WITH CCP1 CCP1 COGxA COGxB DS40001819B-page 368 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 27-12: FULL-BRIDGE FORWARD MODE COG OPERATION WITH CCP1 CCP1 COGxA COGxB COGxC COGxD FIGURE 27-13: FULL-BRIDGE MODE COG OPERATION WITH CCP1 AND DIRECTION CHANGE CCP1 COGxA falling event dead band COGxB COGxC COGxD MD0 2015-2016 Microchip Technology Inc. DS40001819B-page 369 PIC16(L)F1777/8/9 27.4 Clock Sources The COG_clock is used as the reference clock to the various timers in the peripheral. Timers that use the COG_clock include: * Rising and falling dead-band time * Rising and falling blanking time * Rising and falling event phase delay Clock sources available for selection include: * 16 MHz HFINTOSC (active during Sleep) * Instruction clock (FOSC/4) * System clock (FOSC) The clock source is selected with the CS<1:0> bits of the COGxCON0 register (Register 27-1). 27.5 Selectable Event Sources The COG uses any combination of independently selectable event sources to generate the complementary waveform. Sources fall into two categories: 2. The second example is similar to the first except that the duty cycle is close to 100%. The feedback comparator high-to-low transition trips the COG drive off, but almost immediately the period source turns the drive back on. If the off cycle is short enough, the comparator input may not reach the low side of the hysteresis band precluding an output change. The comparator output stays low and without a high-to-low transition to trigger the edge sense, the drive of the COG output will be stuck in a constant drive-on condition. See Figure 27-14. FIGURE 27-14: Rising (CCP1) Falling (C1OUT) C1IN- hyst COGOUT * Rising event sources * Falling event sources The rising event sources are selected by setting bits in the COGxRIS0 and COGxRIS1 registers (Register 27-3 and Register 27-4). The falling event sources are selected by setting bits in the COGxFIS0 and COGxF1 registers (Register 27-7 and Register 27-8). All selected sources are OR'd together to generate the corresponding event signal. Refer to Figure 27-7. 27.5.1 EDGE VS. LEVEL SENSING Event input detection may be selected as level or edge sensitive. The detection mode is individually selectable for every source. Rising source detection modes are selected with the COGxRSIM0 and COGxRSIM1 registers (Register 27-5 and Register 27-6). Falling source detection modes are selected with the COGxFSIM0 and COGxFSIM1 registers (Register 27-9 and Register 27-10). A set bit selects edge detection for the corresponding event source. A cleared bit selects level detection. EDGE VS. LEVEL SENSE Edge Sensitive Rising (CCP1) Falling (C1OUT) C1IN- hyst COGOUT Level Sensitive In general, events that are driven from a periodic source should be edge detected and events that are derived from voltage thresholds at the target circuit should be level sensitive. Consider the following two examples: 1. The first example is an application in which the period is determined by a 50% duty cycle clock on the rising event input and the COG output duty cycle is determined by a voltage level fed back through a comparator on the falling event input. If the clock input is level sensitive, duty cycles less than 50% will exhibit erratic operation because the level sensitive clock will suppress the comparator feedback. DS40001819B-page 370 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 27.5.2 RISING EVENT The rising event starts the PWM output active duty cycle period. The rising event is the low-to-high transition of the rising_event output. When the rising event phase delay and dead-band time values are zero, the primary output starts immediately. Otherwise, the primary output is delayed. The rising event source causes all the following actions: * * * * * Start rising event phase delay counter (if enabled). Clear complementary output after phase delay. Start falling event input blanking (if enabled). Start dead-band delay (if enabled). Set primary output after dead-band delay expires. 27.5.3 FALLING EVENT The falling event terminates the PWM output active duty cycle period. The falling event is the high-to-low transition of the falling_event output. When the falling event phase delay and dead-band time values are zero, the complementary output starts immediately. Otherwise, the complementary output is delayed. The falling event source causes all the following actions: * * * * * Start falling event phase delay counter (if enabled). Clear primary output. Start rising event input blanking (if enabled). Start falling event dead-band delay (if enabled). Set complementary output after dead-band delay expires. 27.6 Output Control Upon disabling, or immediately after enabling the COG module, the primary COG outputs are inactive and complementary COG outputs are active. 27.6.1 OUTPUT ENABLES There are no output enable controls in the COG module. Instead, each device pin has an individual output selection control called the PPS register. All four COG outputs are available for selection in the PPS register of every pin. When a COG output is enabled by PPS selection, the output on the pin has several possibilities which depend on the mode, steering control, EN bit, and shutdown state as shown in Table 27-2 and Table 27-3. . TABLE 27-2: EN PIN OUTPUT STATES MD<2:0> = 00x STR bit Shutdown Output Inactive Static steering data 1 Active Shutdown override 1 Inactive Inactive state 1 Inactive Active PWM signal x 0 x 0 1 2015-2016 Microchip Technology Inc. TABLE 27-3: EN PIN OUTPUT STATES MD<2:0> > 001 STR bit Shutdown Inactive Output Inactive state x x x x Active Shutdown override 1 x Inactive Active PWM signal 27.6.2 POLARITY CONTROL The polarity of each COG output can be selected independently. When the output polarity bit is set, the corresponding output is active-low. Clearing the output polarity bit configures the corresponding output as active-high. However, polarity affects the outputs in only one of the four shutdown override modes. See Section 27.10 "Auto-Shutdown Control" for more details. Output polarity is selected with the POLA through POLD bits of the COGxCON1 register (Register 27-2). 27.7 Dead-Band Control The dead-band control provides for non-overlapping PWM output signals to prevent shoot-through current in the external power switches. Dead-band time affects the output only in the Half-Bridge mode and when changing direction in the Full-Bridge mode. The COG contains two dead-band timers. One dead-band timer is used for rising event dead-band control. The other is used for falling event dead-band control. Timer modes are selectable as either: * Asynchronous delay chain * Synchronous counter The Dead-Band Timer mode is selected for the rising event and falling event dead-band times with the respective RDBS and FDBS bits of the COGxCON1 register (Register 27-2). In Half-Bridge mode, the rising event dead-band time delays all selected primary outputs from going active for the selected dead-band time after the rising event. COGxA and COGxC are the primary outputs in Half-Bridge mode. In Half-Bridge mode, the falling event dead-band time delays all selected complementary outputs from going active for the selected dead-band time after the falling event. COGxB and COGxD are the complementary outputs in Half-Bridge mode. In Full-Bridge mode, the dead-band delay occurs only during direction changes. The modulated output is delayed for the falling event dead-band time after a direction change from forward to reverse. The modulated output is delayed for the rising event dead-band time after a direction change from reverse to forward. DS40001819B-page 371 PIC16(L)F1777/8/9 27.7.1 ASYNCHRONOUS DELAY CHAIN DEAD-BAND DELAY Asynchronous dead-band delay is determined by the time it takes the input to propagate through a series of delay elements. Each delay element is a nominal five nanoseconds. For rising event asynchronous dead-band delay set the RDBS bit of the COGxCON0 register and set the COGxDBR register (Register 27-14) value to the desired number of delay elements in the rising event dead-band time. For falling event asynchronous dead-band delay set the FDBS bit of the COGxCON0 register and set the COGxDBF register (Register 27-15) value to the desired number of delay elements in the falling event dead-band time. Setting the value to zero disables dead-band delay. 27.7.2 SYNCHRONOUS COUNTER DEAD-BAND DELAY Synchronous counter dead band is timed by counting COG_clock periods from zero up to the value in the dead-band count register. Use Equation 27-1 to calculate dead-band times. For rising event synchronous dead-band delay clear the RDBS bit of the COGxCON0 register and set the COGxDBR count register value to the number of COG_clock periods in the rising event dead-band time. For falling event synchronous dead-band delay clear the FDBS bit of the COGxCON0 register and set the COGxDBF count register value to the number of COG_clock periods in the falling event dead-band time. See Section 27.7.1 "Asynchronous Delay Chain Dead-Band Delay" and Section 27.7.2 "Synchronous Counter Dead-Band Delay" for more information on setting the rising edge dead-band time. 27.7.5 FALLING EVENT DEAD BAND Falling event dead band delays the turn-on of complementary outputs from when the primary outputs are turned off. The falling event dead-band time starts when the falling_event output goes true. See Section 27.7.1 "Asynchronous Delay Chain Dead-Band Delay" and Section 27.7.2 "Synchronous Counter Dead-Band Delay" for more information on setting the rising edge dead-band time. 27.7.6 DEAD-BAND OVERLAP There are two cases of potential dead-band overlap: * Rising-to-falling * Falling-to-rising 27.7.6.1 Rising-to-Falling Overlap In this case, the falling event occurs while the rising event dead-band counter is still counting. When this happens, the primary drives are suppressed and the dead band extends by the falling event dead-band time. At the termination of the extended dead-band time, the complementary drive goes true. 27.7.6.2 Falling-to-Rising Overlap In this case, the rising event occurs while the falling event dead-band counter is still counting. When this happens, the complementary drive is suppressed and the dead band extends by the rising event dead-band time. At the termination of the extended dead-band time, the primary drive goes true. When the value is zero, dead-band delay is disabled. 27.7.3 SYNCHRONOUS COUNTER DEAD-BAND TIME UNCERTAINTY When the rising and falling events that trigger the dead-band counters come from asynchronous inputs, it creates uncertainty in the synchronous counter dead-band time. The maximum uncertainty is equal to one COG_clock period. Refer to Example 27-1 for more detail. When event input sources are asynchronous with no phase delay, use the Asynchronous Delay Chain Dead-Band mode to avoid the dead-band time uncertainty. 27.7.4 RISING EVENT DEAD BAND Rising event dead band delays the turn-on of the primary outputs from when complementary outputs are turned off. The rising event dead-band time starts when the rising_ event output goes true. DS40001819B-page 372 27.8 Blanking Control Input blanking is a function whereby the event inputs can be masked or blanked for a short period of time. This is to prevent electrical transients caused by the turn-on/off of power components from generating a false input event. The COG contains two blanking counters: one triggered by the rising event and the other triggered by the falling_event. The counters are cross coupled with the events they are blanking. The falling event blanking counter is used to blank rising input events and the rising event blanking counter is used to blank falling input events. Once started, blanking extends for the time specified by the corresponding blanking counter. Blanking is timed by counting COG_clock periods from zero up to the value in the blanking count register. Use Equation 27-1 to calculate blanking times. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 27.8.1 FALLING EVENT BLANKING OF RISING EVENT INPUTS The falling event blanking counter inhibits rising event inputs from triggering a rising event. The falling event blanking time starts when the rising_event output drive goes false. The falling event blanking time is set by the value contained in the COGxBLKF register (Register 27-17). Blanking times are calculated using the formula shown in Equation 27-1. When the COGxBLKF value is zero, falling event blanking is disabled and the blanking counter output is true, thereby, allowing the event signal to pass straight through to the event trigger circuit. 27.8.2 27.9.1 It is not possible to create more than one COG_clock of uncertainty by successive stages. Consider that the phase-delay stage comes after the blanking stage, the dead-band stage comes after either the blanking or phase-delay stages, and the blanking stage comes after the dead-band stage. When the preceding stage is enabled, the output of that stage is necessarily synchronous with the COG_clock, which removes any possibility of uncertainty in the succeeding stage. EQUATION 27-1: RISING EVENT BLANKING OF FALLING EVENT INPUTS When the COGxBLKR value is zero, rising event blanking is disabled and the blanking counter output is true, thereby, allowing the event signal to pass straight through to the event trigger circuit. 27.8.3 BLANKING TIME UNCERTAINTY When the rising and falling sources that trigger the blanking counters are asynchronous to the COG_clock, it creates uncertainty in the blanking time. The maximum uncertainty is equal to one COG_clock period. Refer to Equation 27-1 and Example 27-1 for more detail. 27.9 Phase Delay PHASE, DEAD-BAND, AND BLANKING TIME CALCULATION Count T min = --------------------------------F COG_clock The rising event blanking counter inhibits falling event inputs from triggering a falling event. The rising event blanking time starts when the falling_event output drive goes false. The rising event blanking time is set by the value contained in the COGxBLKR register (Register 27-16). CUMULATIVE UNCERTAINTY T max T Count + 1 = --------------------------------F COG_clock = T uncertainty max -T min Also: T uncertainty 1 = --------------------------------F COG_clock Where: T Count Rising Phase Delay COGxPHR Falling Phase Delay COGxPHF Rising dead band COGxDBR Falling dead band COGxDBF Rising Event Blanking COGxBLKR Falling Event Blanking COGxBLKF It is possible to delay the assertion of either or both the rising event and falling events. This is accomplished by placing a non-zero value in COGxPHR or COGxPHF phase-delay count registers, respectively (Register 27-18 and Register 27-19). Refer to Figure 27-10 for COG operation with CCP1 and phase delay. The delay from the input rising event signal switching to the actual assertion of the events is calculated the same as the dead-band and blanking delays. Refer to Equation 27-1. When the phase-delay count value is zero, phase delay is disabled and the phase-delay counter output is true, thereby, allowing the event signal to pass straight through to the complementary output driver flop. 2015-2016 Microchip Technology Inc. DS40001819B-page 373 PIC16(L)F1777/8/9 EXAMPLE 27-1: TIMER UNCERTAINTY Given: When auto-restart is enabled, the ASE bit will clear automatically and resume operation on the first rising event after the shutdown input clears. See Figure 27-15 and Section 27.10.3.2 "Auto-Restart". Count = Ah = 10d F COG_Clock = 8MHz Therefore: T uncertainty 1 = --------------------------------F COG_clock 1 = --------------8MHz = 125ns Proof: T min Count = --------------------------------F COG_clock = 125ns 10d = 1.25s Count + 1 T = --------------------------------max F COG_clock = 125ns 10d + 1 = 1.375s Therefore: T uncertainty = T max When auto-restart is disabled, the shutdown state will persist until the first rising event after the ASE bit is cleared by software. -T min 27.10.1.2 External Shutdown Source External shutdown inputs provide the fastest way to safely suspend COG operation in the event of a Fault condition. When any of the selected shutdown inputs go true, the output drive latches are reset and the COG outputs immediately go to the selected override levels without software delay. Any combination of the input sources can be selected to cause a shutdown condition. Shutdown occurs when the selected source is low. Shutdown input sources include: * Any input pin selected with the COGxINPPS control * Comparator 1 * Comparator 2 * Comparator 3 * Comparator 4 * CLC2 output/CLC4 output * Timer2 output/Timer6 output * Timer4 output/Timer8 output Shutdown inputs are selected independently with bits of the COGxASD1 register (Register 27-12). Note: = 1.375s - 1.25s = 125ns Shutdown inputs are level sensitive, not edge sensitive. The shutdown state cannot be cleared as long as the shutdown input level persists, except by disabling auto-shutdown, 27.10 Auto-Shutdown Control Auto-shutdown is a method to immediately override the COG output levels with specific overrides that allow for safe shutdown of the circuit. The shutdown state can be either cleared automatically or held until cleared by software. In either case, the shutdown overrides remain in effect until the first rising event after the shutdown is cleared. 27.10.1 SHUTDOWN The shutdown state can be entered by either of the following two mechanisms: * Software generated * External Input 27.10.2 The levels driven to the output pins, while the shutdown is active, are controlled by the ASDAC<1:0> and ASDBC<1:0> bits of the COGxASD0 register (Register 27-11). ASDAC<1:0> controls the COGxA and COGxC override levels and ASDBC<1:0> controls the COGxB and COGxD override levels. There are four override options for each output pair: * * * * Forced low Forced high Tri-state PWM inactive state (same state as that caused by a falling event) Note: 27.10.1.1 Software Generated Shutdown Setting the ASE bit of the COGxASD0 register (Register 27-11) will force the COG into the shutdown state. DS40001819B-page 374 PIN OVERRIDE LEVELS The polarity control does not apply to the forced low and high override levels but does apply to the PWM inactive state. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 27.10.3 AUTO-SHUTDOWN RESTART After an auto-shutdown event has occurred, there are two ways to resume operation: * Software controlled * Auto-restart The restart method is selected with the ARSEN bit of the COGxASD0 register. Waveforms of a software controlled automatic restart are shown in Figure 27-15. 27.10.3.1 Software Controlled Restart When the ARSEN bit of the COGxASD0 register is cleared, software must clear the ASE bit to restart COG operation after an auto-shutdown event. The COG will resume operation on the first rising event after the ASE bit is cleared. Clearing the shutdown state requires all selected shutdown inputs to be false, otherwise, the ASE bit will remain set. 27.10.3.2 Auto-Restart When the ARSEN bit of the COGxASD0 register is set, the COG will restart from the auto-shutdown state automatically. The ASE bit will clear automatically and the COG will resume operation on the first rising event after all selected shutdown inputs go false. 2015-2016 Microchip Technology Inc. DS40001819B-page 375 1 2 3 4 5 CCP1 ARSEN Next rising event Shutdown input Next rising event ASE Cleared in hardware Cleared in software ASDAC 2b00 2b00 2b00 ASDBD COGxA 2015-2016 Microchip Technology Inc. COGxB Operating State NORMAL OUTPUT SHUTDOWN NORMAL OUTPUT SOFTWARE CONTROLLED RESTART SHUTDOWN NORMAL OUTPUT AUTO-RESTART PIC16(L)F1777/8/9 DS40001819B-page 376 FIGURE 27-15: AUTO-SHUTDOWN WAVEFORM - CCP1 AS RISING AND FALLING EVENT INPUT SOURCE PIC16(L)F1777/8/9 27.11 Buffer Updates Changes to the phase, dead-band, and blanking count registers need to occur simultaneously during COG operation to avoid unintended operation that may occur as a result of delays between each register write. This is accomplished with the LD bit of the COGxCON0 register and double buffering of the phase, blanking and dead-band count registers. Before the COG module is enabled, writing the count registers loads the count buffers without need of the LD bit. However, when the COG is enabled, the count buffer updates are suspended after writing the count registers until after the LD bit is set. When the LD bit is set, the phase, dead-band and blanking register values are transferred to the corresponding buffers synchronous with COG operation. The LD bit is cleared by hardware when the transfer is complete. 5. 6. 7. 8. 9. 10. 27.12 Input and Output Pin Selection The COG has one selection for an input from a device pin. That one input can be used as rising and falling event source or a fault source. The COGxINPPS register is used to select the pin. Refer to registers xxxPPS (Register 12-1) and RxyPPS (Register 12-2). The pin PPS control registers are used to enable the COG outputs. Any combination of outputs to pins is possible including multiple pins for the same output. See the RxyPPS control register and Section 12.2 "PPS Outputs" for more details. 27.13 Operation During Sleep The COG continues to operate in Sleep provided that the COG_clock, rising event, and falling event sources remain active. The HFINTSOC remains active during Sleep when the COG is enabled and the HFINTOSC is selected as the COG_clock source. 11. 12. 13. 14. 15. 16. 27.14 Configuring the COG The following steps illustrate how to properly configure the COG to ensure a synchronous start with the rising event input: 1. 2. 3. 4. 17. Set desired dead-band times with the COGxDBR and COGxDBF registers and select the source with the RDBS and FDBS bits of the COGxCON1 register. Set desired blanking times with the COGxBLKR and COGxBLKF registers. Set desired phase delay with the COGxPHR and COGxPHF registers. Select the desired shutdown sources with the COGxASD1 register. Setup the following controls in COGxASD0 auto-shutdown register: * Select both output override controls to the desired levels (this is necessary, even if not using auto-shutdown because start-up will be from a shutdown state). * Set the ASE bit and clear the ARSEN bit. Select the desired rising and falling event sources with the COGxRIS0, COGxRIS1, COGxFIS0, and COGxFIS1 registers. Select the desired rising and falling event modes with the COGxRSIM0, COGxRSIMI1, COGxFSIM0, and COGxFSIM1 registers. Configure the following controls in the COGxCON1 register: * Set the polarity for each output * Select the desired dead-band timing sources Configure the following controls in the COGxCON0 register: * Set the desired operating mode * Select the desired clock source If one of the steering modes is selected then configure the following controls in the COGxSTR register: * Set the steering bits of the outputs to be used. * Set the desired static levels. Set the EN bit. Set the pin PPS controls to direct the COG outputs to the desired pins. If auto-restart is to be used, set the ARSEN bit and the ASE will be cleared automatically. Otherwise, clear the ASE bit to start the COG. If a pin is to be used for the COG fault or event input, use the COGxINPPS register to configure the desired pin. Clear all ANSEL register bits associated with pins that are used for COG functions. Ensure that the TRIS control bits corresponding to the COG outputs to be used are set so that all are configured as inputs. The COG module will enable the output drivers as needed later. Clear the EN bit, if not already cleared. 2015-2016 Microchip Technology Inc. DS40001819B-page 377 PIC16(L)F1777/8/9 27.15 Register Definitions: COG Control Long bit name prefixes for the COG peripherals are shown in Table 27-4. Refer to Section 1.1 "Register and Bit naming conventions" for more information TABLE 27-4: Peripheral Bit Name Prefix COG1 G1 COG2 G2 COG3 G3 COG4(1) G4 Note 1: PIC16(L)F1777/9 only. REGISTER 27-1: R/W-0/0 COGxCON0: COG CONTROL REGISTER 0 R/W-0/0 U-0 LD -- EN R/W-0/0 R/W-0/0 R/W-0/0 CS<1:0> R/W-0/0 R/W-0/0 MD<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 EN: COGx Enable bit 1 = Module is enabled 0 = Module is disabled bit 6 LD: COGx Load Buffers bit 1 = Phase, blanking, and dead-band buffers to be loaded with register values on next input events 0 = Register to buffer transfer is complete bit 5 Unimplemented: Read as `0' bit 4-3 CS<1:0>: COGx Clock Selection bits 11 = Reserved. Do not use. 10 = COG_clock is HFINTOSC (stays active during Sleep) 01 = COG_clock is FOSC 00 = COG_clock is FOSC/4 bit 2-0 MD<2:0>: COGx Mode Selection bits 11x = Reserved. Do not use. 101 = COG outputs operate in Push-Pull mode 100 = COG outputs operate in Half-Bridge mode 011 = COG outputs operate in Reverse Full-Bridge mode 010 = COG outputs operate in Forward Full-Bridge mode 001 = COG outputs operate in synchronous steered PWM mode 000 = COG outputs operate in steered PWM mode DS40001819B-page 378 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 27-2: COGxCON1: COG CONTROL REGISTER 1 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 RDBS FDBS -- -- POLD POLC POLB POLA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 RDBS: COGx Rising Event Dead-band Timing Source Select bit 1 = Delay chain and COGxDBR are used for dead-band timing generation 0 = COGx_clock and COGxDBR are used for dead-band timing generation bit 6 FDBS: COGx Falling Event Dead-band Timing Source select bit 1 = Delay chain and COGxDBF are used for dead-band timing generation 0 = COGx_clock and COGxDBF are used for dead-band timing generation bit 5-4 Unimplemented: Read as `0' bit 3 POLD: COGxD Output Polarity Control bit 1 = Active level of COGxD output is low 0 = Active level of COGxD output is high bit 2 POLC: COGxC Output Polarity Control bit 1 = Active level of COGxC output is low 0 = Active level of COGxC output is high bit 1 POLB: COGxB Output Polarity Control bit 1 = Active level of COGxB output is low 0 = Active level of COGxB output is high bit 0 POLA: COGxA Output Polarity Control bit 1 = Active level of COGxA output is low 0 = Active level of COGxA output is high 2015-2016 Microchip Technology Inc. DS40001819B-page 379 PIC16(L)F1777/8/9 REGISTER 27-3: COGxRIS0: COG RISING EVENT INPUT SELECTION REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 RIS7 RIS6 RIS5 RIS4 RIS3 RIS2 RIS1 RIS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition RIS<7:0>: Source Rising Event Input <n> Source Enable bits(1). See Table 27-5. 1 = Source <n> output is enabled as a rising event input 0 = Source <n> output has no effect on the rising event bit 7-0 Note 1: Any combination of <n> bits can be selected. REGISTER 27-4: COGxRIS1: COG RISING EVENT INPUT SELECTION REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 RIS15 RIS14 RIS13 RIS12 RIS11 RIS10 RIS9 RIS8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition RIS<15:8>: COGx Rising Event Input <n> Source Enable bits(1). See Table 27-5. 1 = Source <n> output is enabled as a rising event input 0 = Source <n> output has no effect on the rising event bit 15-8 Note 1: Any combination of <n> bits can be selected. TABLE 27-5: RISING/FALLING EVENT INPUT SOURCES Bit <n> COG1 COG2 COG3(1) COG3(2) COG4(1) 15 LC4_out LC4_out LC4_out LC4_out LC4_out 14 LC3_out LC3_out LC3_out LC3_out LC3_out 13 LC2_out LC2_out LC2_out LC2_out LC2_out 12 LC1_out LC1_out LC1_out LC1_out LC1_out Note 11 MD1_out MD2_out MD3_out MD3_out MD4_out 10 PWM6_output PWM6_output PWM12_output Reserved PWM12_output 9 PWM5_output PWM5_output PWM11_output PWM11_output PWM11_output 8 PWM4_output PWM4_output PWM10_output Reserved PWM10_output 7 PWM3_output PWM3_output PWM9_output PWM9_output PWM9_output 6 CCP2_out CCP2_out CCP8_out CCP7_out CCP8_out 5 CCP1_out CCP1_out CCP7_out CCP1_out CCP7_out 4 sync_CM4_out sync_CM4_out sync_CM8_out sync_CM6_out sync_CM8_out 3 sync_CM3_out sync_CM3_out sync_CM7_out sync_CM5_out sync_CM7_out 2 sync_CM2_out sync_CM2_out sync_CM6_out sync_CM2_out sync_CM6_out 1 sync_CM1_out sync_CM1_out sync_CM5_out sync_CM1_out sync_CM5_out 0 Pin selected with COG1PPS Pin selected with COG2PPS Pin selected with COG3PPS Pin selected with COG3PPS Pin selected with COG4PPS 1: 2: PIC16(L)F1777/9 only. PIC16(L)F1778 only. DS40001819B-page 380 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 27-5: COGxRSIM0: COG RISING EVENT SOURCE INPUT MODE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 RSIM7 RSIM6 RSIM5 RSIM4 RSIM3 RSIM2 RSIM1 RSIM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition RSIM<7:0>: Rising Event Input Source <n> Mode bits(1). See Table 27-5. RIS<n> = 1: 1 = Source <n> output low-to-high transition will cause a rising event after rising event phase delay 0 = Source <n> output high level will cause an immediate rising event RIS<n> = 0: Source <n> output has no effect on rising event bit 7-0 Note 1: Any combination of <n> bits can be selected. REGISTER 27-6: COGxRSIM1: COG RISING EVENT SOURCE INPUT MODE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 RSIM15 RSIM14 RSIM13 RSIM12 RSIM11 RSIM10 RSIM9 RSIM8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 15-8 Note 1: RSIM<15:8>: Rising Event Input Source <n> Mode bits(1). See Table 27-5. RIS<n> = 1: 1 = Source <n> output low-to-high transition will cause a rising event after rising event phase delay 0 = Source <n> output high level will cause an immediate rising event RIS<n> = 0: Source <n> output has no effect on rising event Any combination of <n> bits can be selected. 2015-2016 Microchip Technology Inc. DS40001819B-page 381 PIC16(L)F1777/8/9 REGISTER 27-7: COGxFIS0: COG FALLING EVENT INPUT SELECTION REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 FIS7 FIS6 FIS5 FIS4 FIS3 FIS2 FIS1 FIS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition FIS<7:0>: Falling Event Input Source <n> Enable bits(1). See Table 27-5. 1 = Source <n> output is enabled as a falling event input 0 = Source <n> output has no effect on the falling event bit 7-0 Note 1: Any combination of <n> bits can be selected. REGISTER 27-8: COGxFIS1: COG FALLING EVENT INPUT SELECTION REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 FIS15 FIS14 FIS13 FIS12 FIS11 FIS10 FIS9 FIS8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 15-8 Note 1: FIS<15:8>: Falling Event Input Source <n> Enable bits(1). See Table 27-5. 1 = Source <n> output is enabled as a falling event input 0 = Source <n> output has no effect on the falling event Any combination of <n> bits can be selected. DS40001819B-page 382 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 27-9: COGxFSIM0: COG FALLING EVENT SOURCE INPUT MODE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 FSIM7 FSIM6 FSIM5 FSIM4 FSIM3 FSIM2 FSIM1 FSIM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition FSIM<7:0>: Falling Event Input Source <n> Mode bits(1). See Table 27-5. FIS<n> = 1: 1 = Source <n> output high-to-low transition will cause a falling event after falling event phase delay 0 = Source <n> output low level will cause an immediate falling event FIS<n> = 0: Source <n> output has no effect on falling event bit 7-0 Note 1: Any combination of <n> bits can be selected. REGISTER 27-10: COGxFSIM1: COG FALLING EVENT SOURCE INPUT MODE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 FSIM15 FSIM14 FSIM13 FSIM12 FSIM11 FSIM10 FSIM9 FSIM8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 15-8 Note 1: FSIM<15:8>: Falling Event Input Source <n> Mode bits(1). See Table 27-5. FIS<n> = 1: 1 = Source <n> output high-to-low transition will cause a falling event after falling event phase delay 0 = Source <n> output low level will cause an immediate falling event FIS<n> = 0: Source <n> output has no effect on falling event Any combination of <n> bits can be selected. 2015-2016 Microchip Technology Inc. DS40001819B-page 383 PIC16(L)F1777/8/9 REGISTER 27-11: COGxASD0: COG AUTO-SHUTDOWN CONTROL REGISTER 0 R/W-0/0 R/W-0/0 ASE ARSEN R/W-0/0 R/W-1/1 ASDBD<1:0> R/W-0/0 R/W-1/1 ASDAC<1:0> bit 7 U-0 U-0 -- -- bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 ASE: Auto-Shutdown Event Status bit 1 = COG is in the shutdown state 0 = COG is either not in the shutdown state or will exit the shutdown state on the next rising event bit 6 ARSEN: Auto-Restart Enable bit 1 = Auto-restart is enabled 0 = Auto-restart is disabled bit 5-4 ASDBD<1:0>: COGxB and COGxD Auto-shutdown Override Level Select bits 11 = A logic `1' is placed on COGxB and COGxD when shutdown is active 10 = A logic `0' is placed on COGxB and COGxD when shutdown is active 01 = COGxB and COGxD are tri-stated when shutdown is active 00 = The inactive state of the pin, including polarity, is placed on COGxB and COGxD when shutdown is active bit 3-2 ASDAC<1:0>: COGxA and COGxC Auto-shutdown Override Level Select bits 11 = A logic `1' is placed on COGxA and COGxC when shutdown is active 10 = A logic `0' is placed on COGxA and COGxC when shutdown is active 01 = COGxA and COGxC are tri-stated when shutdown is active 00 = The inactive state of the pin, including polarity, is placed on COGxA and COGxC when shutdown is active bit 1-0 Unimplemented: Read as `0' DS40001819B-page 384 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 27-12: COGxASD1: COG AUTO-SHUTDOWN CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 AS7E AS6E AS5E AS4E AS3E AS2E AS1E AS0E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition AS<7:0>E: Auto-shutdown Source <n> Enable bits(1). See Table 27-6. 1 = COGx is shutdown when source <n> output is low 0 = Source <n> has no effect on shutdown bit 7-0 Note 1: Any combination of <n> bits can be selected. TABLE 27-6: AUTO-SHUTDOWN SOURCES Bit <n> COG1 COG2 COG3(2) COG3(3) COG4(2) 7 TMR4_postscaled(1) TMR4_postscaled(1) TMR8_postscaled(1) TMR8_postscaled(1) TMR8_postscaled(1) 6 TMR2_postscaled(1) TMR2_postscaled(1) TMR6_postscaled(1) TMR6_postscaled(1) TMR6_postscaled(1) Note 5 LC2_out LC2_out LC4_out LC4_out LC4_out 4 sync_CM4_out sync_CM4_out sync_CM8_out sync_CM6_out sync_CM8_out 3 sync_CM3_out sync_CM3_out sync_CM7_out sync_CM5_out sync_CM7_out 2 sync_CM2_out sync_CM2_out sync_CM6_out sync_CM2_out sync_CM6_out 1 sync_CM1_out sync_CM1_out sync_CM5_out sync_CM1_out sync_CM5_out 0 Pin selected by COG1PPS Pin selected by COG2PPS Pin selected by COG3PPS Pin selected by COG3PPS Pin selected by COG4PPS 1: 2: 3: Shutdown when source is high. PIC16(L)F1777/9 only. PIC16(L)F1778 only. 2015-2016 Microchip Technology Inc. DS40001819B-page 385 PIC16(L)F1777/8/9 REGISTER 27-13: COGxSTR: COG STEERING CONTROL REGISTER 1(1) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SDATD SDATC SDATB SDATA STRD STRC STRB STRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 SDATD: COGxD Static Output Data bit 1 = COGxD static data is high 0 = COGxD static data is low bit 6 SDATC: COGxC Static Output Data bit 1 = COGxC static data is high 0 = COGxC static data is low bit 5 SDATB: COGxB Static Output Data bit 1 = COGxB static data is high 0 = COGxB static data is low bit 4 SDATA: COGxA Static Output Data bit 1 = COGxA static data is high 0 = COGxA static data is low bit 3 STRD: COGxD Steering Control bit 1 = COGxD output has the COGxD waveform with polarity control from POLD bit 0 = COGxD output is the static data level determined by the SDATD bit bit 2 STRC: COGxC Steering Control bit 1 = COGxC output has the COGxC waveform with polarity control from POLC bit 0 = COGxC output is the static data level determined by the SDATC bit bit 1 STRB: COGxB Steering Control bit 1 = COGxB output has the COGxB waveform with polarity control from POLB bit 0 = COGxB output is the static data level determined by the SDATB bit bit 0 STRA: COGxA Steering Control bit 1 = COGxA output has the COGxA waveform with polarity control from POLA bit 0 = COGxA output is the static data level determined by the SDATA bit Note 1: Steering is active only when the MD<1:0> bits of the COGxCON0 register = 00x. (See Register 27-1). DS40001819B-page 386 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 27-14: COGxDBR: COG RISING EVENT DEAD-BAND COUNT REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 DBR<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as `0' bit 5-0 DBR<5:0>: Rising Event Dead-Band Count Value bits RDBS = 1: = Number of delay chain element periods to delay primary output after rising event RDBS = 0: = Number of COGx clock periods to delay primary output after rising event REGISTER 27-15: COGxDBF: COG FALLING EVENT DEAD-BAND COUNT REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 DBF<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as `0' bit 5-0 DBF<5:0>: Falling Event Dead-Band Count Value bits FDBS = 1: = Number of delay chain element periods to delay complementary output after falling event input FDBS = 0: = Number of COGx clock periods to delay complementary output after falling event input 2015-2016 Microchip Technology Inc. DS40001819B-page 387 PIC16(L)F1777/8/9 REGISTER 27-16: COGxBLKR: COG RISING EVENT BLANKING COUNT REGISTER U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u BLKR<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as `0' bit 5-0 BLKR<5:0>: Rising Event Blanking Count Value bits = Number of COGx clock periods to inhibit falling event inputs REGISTER 27-17: COGxBLKF: COG FALLING EVENT BLANKING COUNT REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 BLKF<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as `0' bit 5-0 BLKF<5:0>: Falling Event Blanking Count Value bits = Number of COGx clock periods to inhibit rising event inputs DS40001819B-page 388 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 27-18: COGxPHR: COG RISING EVENT PHASE DELAY COUNT REGISTER U-0 U-0 -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PHR<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as `0' bit 5-0 PHR<5:0>: Rising Event Phase Delay Count Value bits = Number of COGx clock periods to delay rising event REGISTER 27-19: COGxPHF: COG FALLING EVENT PHASE DELAY COUNT REGISTER U-0 U-0 -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PHF<5:0> -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as `0' bit 5-0 PHF<5:0>: Falling Event Phase Delay Count Value bits = Number of COGx clock periods to delay falling event 2015-2016 Microchip Technology Inc. DS40001819B-page 389 PIC16(L)F1777/8/9 TABLE 27-7: Name SUMMARY OF REGISTERS ASSOCIATED WITH COGx(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA -- -- ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177 ANSELB -- -- ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182 ANSELC ANSC5 ANSC4 ANSC3 ANSC2 -- -- 187 -- -- 384 AS1E AS0E 385 ANSC7 ANSC6 COGxASD0 ASE ARSEN COGxASD1 AS7E AS6E COGxBLKR -- -- ASDBD<1:0> AS5E AS4E AS3E AS2E BLKR<5:0> COGxBLKF -- -- COGxCON0 EN LD -- COGxCON1 RDBS FDBS -- -- -- COGxDBR ASDAC<1:0> 388 BLKF<5:0> CS<1:0> -- 388 MD<2:0> POLD POLC POLB 378 POLA DBR<5:0> 379 387 COGxDBF -- -- COGxFIS0 FIS7 FIS6 FIS5 FIS4 FIS3 FIS2 FIS1 FIS0 382 COGxFIS1 FIS15 FIS14 FIS13 FIS12 FIS11 FIS10 FIS9 FIS8 382 COGxFSIM0 FSIM7 FSIM6 FSIM5 FSIM4 FSIM3 FSIM2 FSIM1 FSIM0 383 COGxFSIM1 FSIM13 FSIM12 FSIM11 FSIM10 FSIM9 FSIM8 383 DBF<5:0> 387 FSIM15 FSIM14 COGxPHR -- -- PHR<5:0> COGxPHF -- -- PHF<5:0> 389 COGxPPS -- -- COG1PPS<5:0> 205, 207 389 COGxRIS0 RIS7 RIS6 RIS5 RIS4 RIS3 RIS2 RIS1 RIS0 380 COGxRIS1 RIS15 RIS14 RIS13 RIS12 RIS11 RIS10 RIS9 RIS8 380 COGxRSIM0 RSIM7 RSIM6 RSIM5 RSIM4 RSIM3 RSIM2 RSIM1 RSIM0 381 COGxRSIM1 RSIM15 RSIM14 RSIM13 RSIM12 RSIM11 RSIM10 RSIM9 RSIM8 381 COGxSTR SDATD SDATC SDATB SDATA STRD STRC STRB STRA 386 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132 -- -- INTCON RxyPPS Legend: Note 1: RxyPPS<5:0> 205 x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by COG. COG4 is available on PIC16(L)F1777/9 only. DS40001819B-page 390 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 28.0 Refer to Figure 28-1 for a simplified diagram showing signal flow through the CLCx. CONFIGURABLE LOGIC CELL (CLC) The Configurable Logic Cell (CLCx) provides programmable logic that operates outside the speed limitations of software execution. The logic cell takes up to 32 input signals and, through the use of configurable gates, reduces the 32 inputs to four logic lines that drive one of eight selectable single-output logic functions. Input sources are a combination of the following: * * * * I/O pins Internal clocks Peripherals Register bits The output can be directed internally to peripherals and to an output pin. FIGURE 28-1: Possible configurations include: * Combinatorial Logic - AND - NAND - AND-OR - AND-OR-INVERT - OR-XOR - OR-XNOR * Latches - S-R - Clocked D with Set and Reset - Transparent D with Set and Reset - Clocked J-K with Reset CLCx SIMPLIFIED BLOCK DIAGRAM Rev. 10-000 025D 6/4/201 4 D LCxOUT MLCxOUT Q Q1 . . . See Table 28-1. LCx_in[35] LCx_in[36] LCx_in[37] LCx_out Input Data Selection Gates(1) LCx_in[0] LCx_in[1] LCx_in[2] EN g1 g2 g3 Logic Function to Peripherals CLCxPPS q PPS CLCx (2) g4 POL MODE<2:0> TRIS Interrupt det INTP INTN set bit CLCxIF Interrupt det Note 1: 2: See Figure 28-2: Input Data Selection and Gating. See Figure 28-3: Programmable Logic Functions. 2015-2016 Microchip Technology Inc. DS40001819B-page 391 PIC16(L)F1777/8/9 28.1 TABLE 28-1: CLCx DATA INPUT SELECTION CLCx Setup Programming the CLCx module is performed by configuring the four stages in the logic signal flow. The four stages are: Data Input dy CLCx DxS LCx_in[35] 100011 PWM12_out(1) LCx_in[34] 100010 PWM11_out LCx_in[33] 100001 PWM6_out LCx_in[32] 100000 PWM5_out LCx_in[31] 011111 PWM10_out(1) LCx_in[30] 011110 PWM9_out LCx_in[29] 011101 PWM4_out LCx_in[28] 011100 PWM3_out LCx_in[27] 011011 CCP8_out(1) LCx_in[26] 011010 CCP7_out LCx_in[25] 011001 CCP2_out There are 32 signals available as inputs to the configurable logic. Four 32-input multiplexers are used to select the inputs to pass on to the next stage. LCx_in[24] 011000 CCP1_out LCx_in[23] 010111 COG4B(1) LCx_in[22] 010110 COG4A(1) Data selection is through four multiplexers as indicated on the left side of Figure 28-2. Data inputs in the figure are identified by a generic numbered input name. LCx_in[21] 010101 COG3B LCx_in[20] 010100 COG3A LCx_in[19] 010011 COG2B LCx_in[18] 010010 COG2A LCx_in[17] 010001 COG1B LCx_in[16] 010000 COG1A LCx_in[15] 001111 sync_C8OUT(1) LCx_in[14] 001110 sync_C7OUT(1) LCx_in[13] 001101 sync_C6OUT LCx_in[12] 001100 sync_C5OUT LCx_in[11] 001011 sync_C4OUT LCx_in[10] 001010 sync_C3OUT LCx_in[9] 001001 sync_C2OUT LCx_in[8] 001000 sync_C1OUT LCx_in[7] 000111 LC4_out from the CLC4 LCx_in[6] 000110 LC3_out from the CLC3 LCx_in[5] 000101 LC2_out from the CLC2 LCx_in[4] 000100 LC1_out from the CLC1 LCx_in[3] 000011 CLCIN3 pin input selected in CLCIN3PPS register LCx_in[2] 000010 CLCIN2 pin input selected in CLCIN2PPS register LCx_in[1] 000001 CLCIN1 pin input selected in CLCIN1PPS register LCx_in[0] 000000 CLCIN0 pin input selected in CLCIN0PPS register * * * * Data selection Data gating Logic function selection Output polarity Each stage is setup at run time by writing to the corresponding CLCx Special Function Registers. This has the added advantage of permitting logic reconfiguration on-the-fly during program execution. 28.1.1 DATA SELECTION Table 28-1 correlates the generic input name to the actual signal for each CLC module. The column labeled dy indicates the MUX selection code for the selected data input. DxS is an abbreviation for the MUX select input codes: D1S<4:0> through D4S<4:0>. Data inputs are selected with the CLCxSEL0 through CLCxSEL3 registers (Register 28-3 through Register 28-6). Note: Data selections are undefined at power-up. TABLE 28-1: CLCx DATA INPUT SELECTION Data Input dy CLCx DxS LCx_in[54] 110110 MD1_OUT OR MD2_OUT OR MD3_OUT LCx_in[53] 110101 FOSC LCx_in[52] 110100 HFINTOSC LCx_in[51] 110011 LFINTOSC LCx_in[50] 110010 FRC (ADC RC clock) LCx_in[49] 110001 IOCIF set LCx_in[48] 110000 Timer8_postscaled LCx_in[47] 101111 Timer6_postscaled LCx_in[46] 101110 Timer4_postscaled LCx_in[45] 101101 Timer2_postscaled LCx_in[44] 101100 Timer5 overflow LCx_in[43] 101011 Timer3 overflow LCx_in[42] 101010 Timer1 overflow LCx_in[41] 101001 Timer0 overflow LCx_in[40] 101000 EUSART RX LCx_in[39] 100111 EUSART TX LCx_in[38] 100110 ZCD1_output LCx_in[37] 100101 MSSP1 SDO/SDA LCx_in[36] 100100 MSSP1 SCL/SCK DS40001819B-page 392 Note 1: PIC16(L)F1777/9 only. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 28.1.2 DATA GATING Outputs from the input multiplexers are directed to the desired logic function input through the data gating stage. Each data gate can direct any combination of the four selected inputs. Note: Data gating is undefined at power-up. The gate stage is more than just signal direction. The gate can be configured to direct each input signal as inverted or non-inverted data. Directed signals are ANDed together in each gate. The output of each gate can be inverted before going on to the logic function stage. The gating is in essence a 1-to-4 input AND/NAND/OR/NOR gate. When every input is inverted and the output is inverted, the gate is an OR of all enabled data inputs. When the inputs and output are not inverted, the gate is an AND or all enabled inputs. Table 28-2 summarizes the basic logic that can be obtained in gate 1 by using the gate logic select bits. The table shows the logic of four input variables, but each gate can be configured to use less than four. If no inputs are selected, the output will be zero or one, depending on the gate output polarity bit. TABLE 28-2: DATA GATING LOGIC CLCxGLS0 G1POL Gate Logic 0x55 1 AND 0x55 0 NAND 0xAA 1 NOR 0xAA 0 OR 0x00 0 Logic 0 0x00 1 Logic 1 Data gating is indicated in the right side of Figure 28-2. Only one gate is shown in detail. The remaining three gates are configured identically with the exception that the data enables correspond to the enables for that gate. 28.1.3 LOGIC FUNCTION There are eight available logic functions including: * * * * * * * * AND-OR OR-XOR AND S-R Latch D Flip-Flop with Set and Reset D Flip-Flop with Reset J-K Flip-Flop with Reset Transparent Latch with Set and Reset Logic functions are shown in Figure 28-3. Each logic function has four inputs and one output. The four inputs are the four data gate outputs of the previous stage. The output is fed to the inversion stage and from there to other peripherals, an output pin, and back to the CLCx itself. 28.1.4 OUTPUT POLARITY The last stage in the Configurable Logic Cell is the output polarity. Setting the POL bit of the CLCxCON register inverts the output signal from the logic stage. Changing the polarity while the interrupts are enabled will cause an interrupt for the resulting output transition. It is possible (but not recommended) to select both the true and negated values of an input. When this is done, the gate output is zero, regardless of the other inputs, but may emit logic glitches (transient-induced pulses). If the output of the channel must be zero or one, the recommended method is to set all gate bits to zero and use the gate polarity bit to set the desired level. Data gating is configured with the logic gate select registers as follows: * * * * Gate 1: CLCxGLS0 (Register 28-7) Gate 2: CLCxGLS1 (Register 28-8) Gate 3: CLCxGLS2 (Register 28-9) Gate 4: CLCxGLS3 (Register 28-10) Register number suffixes are different than the gate numbers because other variations of this module have multiple gate selections in the same register. 2015-2016 Microchip Technology Inc. DS40001819B-page 393 PIC16(L)F1777/8/9 28.1.5 CLCx SETUP STEPS The following steps should be followed when setting up the CLCx: * Disable CLCx by clearing the EN bit. * Select desired inputs using CLCxSEL0 through CLCxSEL3 registers (See Table 28-1). * Clear any associated ANSEL bits. * Set all TRIS bits associated with inputs. * Clear all TRIS bits associated with outputs. * Enable the chosen inputs through the four gates using CLCxGLS0, CLCxGLS1, CLCxGLS2, and CLCxGLS3 registers. * Select the gate output polarities with the POLy bits of the CLCxPOL register. * Select the desired logic function with the MODE<2:0> bits of the CLCxCON register. * Select the desired polarity of the logic output with the POL bit of the CLCxPOL register. (This step may be combined with the previous gate output polarity step). * If driving a device pin, set the desired pin PPS control register and also clear the TRIS bit corresponding to that output. * If interrupts are desired, configure the following bits: - Set the INTP bit in the CLCxCON register for rising event. - Set the INTN bit in the CLCxCON register for falling event. - Set the CLCxIE bit of the associated PIE registers. - Set the GIE and PEIE bits of the INTCON register. * Enable the CLCx by setting the EN bit of the CLCxCON register. 28.2 CLCx Interrupts An interrupt will be generated upon a change in the output value of the CLCx when the appropriate interrupt enables are set. A rising edge detector and a falling edge detector are present in each CLC for this purpose. The CLCxIF bit of the associated PIR registers will be set when either edge detector is triggered and its associated enable bit is set. The INTP enables rising edge interrupts and the INTN bit enables falling edge interrupts. Both are located in the CLCxCON register. To fully enable the interrupt, set the following bits: * EN bit of the CLCxCON register * CLCxIE bit of the associated PIE registers * INTP bit of the CLCxCON register (for a rising edge detection) * INTN bit of the CLCxCON register (for a falling edge detection) * PEIE and GIE bits of the INTCON register The CLCxIF bit of the associated PIR registers, must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. 28.3 Output Mirror Copies Mirror copies of all LCxCON output bits are contained in the CLCxDATA register. Reading this register reads the outputs of all CLCs simultaneously. This prevents any reading skew introduced by testing or reading the CLCxOUT bits in the individual CLCxCON registers. 28.4 Effects of a Reset The CLCxCON register is cleared to zero as the result of a Reset. All other selection and gating values remain unchanged. 28.5 Operation During Sleep The CLC module operates independently from the system clock and will continue to run during Sleep, provided that the input sources selected remain active. The HFINTOSC remains active during Sleep when the CLC module is enabled and the HFINTOSC is selected as an input source, regardless of the system clock source selected. In other words, if the HFINTOSC is simultaneously selected as the system clock and as a CLC input source, when the CLC is enabled, the CPU will go idle during Sleep, but the CLC will continue to operate and the HFINTOSC will remain active. This will have a direct effect on the Sleep mode current. DS40001819B-page 394 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 28-2: INPUT DATA SELECTION AND GATING Data Selection LCx_in[0] Data GATE 1 See Table 28-1. d1T D1G1T d1N D1G1N LCx_in[37] D2G1T D1S<4:0> D2G1N g1 LCx_in[0] D3G1T d2T See Table 28-1. G1POL D3G1N d2N D4G1T LCx_in[37] D2S<4:0> D4G1N LCx_in[0] Data GATE 2 g2 d3T See Table 28-1. (Same as Data GATE 1) d3N Data GATE 3 LCx_in[37] g3 D3S<4:0> (Same as Data GATE 1) Data GATE 4 LCx_in[0] g4 d4T See Table 28-1. (Same as Data GATE 1) d4N LCx_in[37] D4S<4:0> Note: All controls are undefined at power-up. 2015-2016 Microchip Technology Inc. DS40001819B-page 395 PIC16(L)F1777/8/9 FIGURE 28-3: PROGRAMMABLE LOGIC FUNCTIONS AND - OR OR - XOR g1 g1 g2 g2 q g3 q g3 g4 g4 MODE<2:0>= 000 MODE<2:0>= 001 4-Input AND S-R Latch g1 g1 g2 g2 q g3 S g3 g4 R g4 MODE<2:0>= 010 q Q MODE<2:0>= 011 1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R g4 g2 D S g4 Q q D g2 g1 g1 Q q R R g3 g3 MODE<2:0>= 100 MODE<2:0>= 101 J-K Flip-Flop with R 1-Input Transparent Latch with S and R g4 g2 J Q g1 g4 K R q g2 D g1 LE g3 S Q q R g3 MODE<2:0>= 110 DS40001819B-page 396 MODE<2:0>= 111 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 28.6 Register Definitions: CLC Control Long bit name prefixes for the CLC peripherals are shown in Table 28-3. Refer to Section 1.1 "Register and Bit naming conventions" for more information TABLE 28-3: Peripheral Bit Name Prefix CLC1 LC1 CLC2 LC2 CLC3 LC3 CLC4 LC4 REGISTER 28-1: CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER R/W-0/0 U-0 R-0/0 R/W-0/0 R/W-0/0 EN -- OUT INTP INTN R/W-0/0 R/W-0/0 R/W-0/0 MODE<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 EN: Configurable Logic Cell Enable bit 1 = Configurable logic cell is enabled and mixing input signals 0 = Configurable logic cell is disabled and has logic zero output bit 6 Unimplemented: Read as `0' bit 5 OUT: Configurable Logic Cell Data Output bit Read-only: logic cell output data, after POL; sampled from lcx_out wire. bit 4 INTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit 1 = CLCxIF will be set when a rising edge occurs on lcx_out 0 = CLCxIF will not be set bit 3 INTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit 1 = CLCxIF will be set when a falling edge occurs on lcx_out 0 = CLCxIF will not be set bit 2-0 MODE<2:0>: Configurable Logic Cell Functional Mode bits 111 = Cell is 1-input transparent latch with S and R 110 = Cell is J-K flip-flop with R 101 = Cell is 2-input D flip-flop with R 100 = Cell is 1-input D flip-flop with S and R 011 = Cell is S-R latch 010 = Cell is 4-input AND 001 = Cell is OR-XOR 000 = Cell is AND-OR 2015-2016 Microchip Technology Inc. DS40001819B-page 397 PIC16(L)F1777/8/9 REGISTER 28-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER R/W-0/0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u POL -- -- -- G4POL G3POL G2POL G1POL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 POL: LCOUT Polarity Control bit 1 = The output of the logic cell is inverted 0 = The output of the logic cell is not inverted bit 6-4 Unimplemented: Read as `0' bit 3 G4POL: Gate 4 Output Polarity Control bit 1 = The output of gate 4 is inverted when applied to the logic cell 0 = The output of gate 4 is not inverted bit 2 G3POL: Gate 3 Output Polarity Control bit 1 = The output of gate 3 is inverted when applied to the logic cell 0 = The output of gate 3 is not inverted bit 1 G2POL: Gate 2 Output Polarity Control bit 1 = The output of gate 2 is inverted when applied to the logic cell 0 = The output of gate 2 is not inverted bit 0 G1POL: Gate 1 Output Polarity Control bit 1 = The output of gate 1 is inverted when applied to the logic cell 0 = The output of gate 1 is not inverted DS40001819B-page 398 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 28-3: CLCxSEL0: GENERIC CLCx DATA 1 SELECT REGISTER U-0 U-0 -- -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u D1S<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 D1S<5:0>: CLCx Data1 Input Selection bits See Table 28-1. REGISTER 28-4: CLCxSEL1: GENERIC CLCx DATA 2 SELECT REGISTER U-0 U-0 -- -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u D2S<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 D2S<5:0>: CLCx Data 2 Input Selection bits See Table 28-1. REGISTER 28-5: CLCxSEL2: GENERIC CLCx DATA 3 SELECT REGISTER U-0 U-0 -- -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u D3S<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 D3S<5:0>: CLCx Data 3 Input Selection bits See Table 28-1. 2015-2016 Microchip Technology Inc. DS40001819B-page 399 PIC16(L)F1777/8/9 REGISTER 28-6: CLCxSEL3: GENERIC CLCx DATA 4 SELECT REGISTER U-0 U-0 -- -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u D4S<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 D4S<5:0>: CLCx Data 4 Input Selection bits See Table 28-1. REGISTER 28-7: CLCxGLS0: GATE 1 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 G1D4T: Gate 1 Data 4 True (non-inverted) bit 1 = d4T is gated into g1 0 = d4T is not gated into g1 bit 6 G1D4N: Gate 1 Data 4 Negated (inverted) bit 1 = d4N is gated into g1 0 = d4N is not gated into g1 bit 5 G1D3T: Gate 1 Data 3 True (non-inverted) bit 1 = d3T is gated into g1 0 = d3T is not gated into g1 bit 4 G1D3N: Gate 1 Data 3 Negated (inverted) bit 1 = d3N is gated into g1 0 = d3N is not gated into g1 bit 3 G1D2T: Gate 1 Data 2 True (non-inverted) bit 1 = d2T is gated into g1 0 = d2T is not gated into g1 bit 2 G1D2N: Gate 1 Data 2 Negated (inverted) bit 1 = d2N is gated into g1 0 = d2N is not gated into g1 bit 1 G1D1T: Gate 1 Data 1 True (non-inverted) bit 1 = d1T is gated into g1 0 = d1T is not gated into g1 bit 0 G1D1N: Gate 1 Data 1 Negated (inverted) bit 1 = d1N is gated into g1 0 = d1N is not gated into g1 DS40001819B-page 400 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 28-8: CLCxGLS1: GATE 2 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 G2D4T: Gate 2 Data 4 True (non-inverted) bit 1 = d4T is gated into g2 0 = d4T is not gated into g2 bit 6 G2D4N: Gate 2 Data 4 Negated (inverted) bit 1 = d4N is gated into g2 0 = d4N is not gated into g2 bit 5 G2D3T: Gate 2 Data 3 True (non-inverted) bit 1 = d3T is gated into g2 0 = d3T is not gated into g2 bit 4 G2D3N: Gate 2 Data 3 Negated (inverted) bit 1 = d3N is gated into g2 0 = d3N is not gated into g2 bit 3 G2D2T: Gate 2 Data 2 True (non-inverted) bit 1 = d2T is gated into g2 0 = d2T is not gated into g2 bit 2 G2D2N: Gate 2 Data 2 Negated (inverted) bit 1 = d2N is gated into g2 0 = d2N is not gated into g2 bit 1 G2D1T: Gate 2 Data 1 True (non-inverted) bit 1 = d1T is gated into g2 0 = d1T is not gated into g2 bit 0 G2D1N: Gate 2 Data 1 Negated (inverted) bit 1 = d1N is gated into g2 0 = d1N is not gated into g2 2015-2016 Microchip Technology Inc. DS40001819B-page 401 PIC16(L)F1777/8/9 REGISTER 28-9: CLCxGLS2: GATE 3 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 G3D4T: Gate 3 Data 4 True (non-inverted) bit 1 = d4T is gated into g3 0 = d4T is not gated into g3 bit 6 G3D4N: Gate 3 Data 4 Negated (inverted) bit 1 = d4N is gated into g3 0 = d4N is not gated into g3 bit 5 G3D3T: Gate 3 Data 3 True (non-inverted) bit 1 = d3T is gated into g3 0 = d3T is not gated into g3 bit 4 G3D3N: Gate 3 Data 3 Negated (inverted) bit 1 = d3N is gated into g3 0 = d3N is not gated into g3 bit 3 G3D2T: Gate 3 Data 2 True (non-inverted) bit 1 = d2T is gated into g3 0 = d2T is not gated into g3 bit 2 G3D2N: Gate 3 Data 2 Negated (inverted) bit 1 = d2N is gated into g3 0 = d2N is not gated into g3 bit 1 G3D1T: Gate 3 Data 1 True (non-inverted) bit 1 = d1T is gated into g3 0 = d1T is not gated into g3 bit 0 G3D1N: Gate 3 Data 1 Negated (inverted) bit 1 = d1N is gated into g3 0 = d1N is not gated into g3 DS40001819B-page 402 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 28-10: CLCxGLS3: GATE 4 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 G4D4T: Gate 4 Data 4 True (non-inverted) bit 1 = d4T is gated into g4 0 = d4T is not gated into g4 bit 6 G4D4N: Gate 4 Data 4 Negated (inverted) bit 1 = d4N is gated into g4 0 = d4N is not gated into g4 bit 5 G4D3T: Gate 4 Data 3 True (non-inverted) bit 1 = d3T is gated into g4 0 = d3T is not gated into g4 bit 4 G4D3N: Gate 4 Data 3 Negated (inverted) bit 1 = d3N is gated into g4 0 = d3N is not gated into g4 bit 3 G4D2T: Gate 4 Data 2 True (non-inverted) bit 1 = d2T is gated into g4 0 = d2T is not gated into g4 bit 2 G4D2N: Gate 4 Data 2 Negated (inverted) bit 1 = d2N is gated into g4 0 = d2N is not gated into g4 bit 1 G4D1T: Gate 4 Data 1 True (non-inverted) bit 1 = d1T is gated into g4 0 = d1T is not gated into g4 bit 0 G4D1N: Gate 4 Data 1 Negated (inverted) bit 1 = d1N is gated into g4 0 = d1N is not gated into g4 2015-2016 Microchip Technology Inc. DS40001819B-page 403 PIC16(L)F1777/8/9 REGISTER 28-11: CLCDATA: CLC DATA OUTPUT U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 -- -- -- -- MLC4OUT MLC3OUT MLC2OUT MLC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3 MLC4OUT: Mirror copy of LC4OUT bit bit 2 MLC3OUT: Mirror copy of LC3OUT bit bit 1 MLC2OUT: Mirror copy of LC2OUT bit bit 0 MLC1OUT: Mirror copy of LC1OUT bit DS40001819B-page 404 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 28-4: Name ANSELA SUMMARY OF REGISTERS ASSOCIATED WITH CLCx Bit7 Bit6 Bit5 Bit4 BIt3 Bit2 Bit1 Bit0 Register on Page -- -- ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177 ANSELB -- -- ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 -- -- 187 CLCxCON EN -- OUT INTP INTN CLCDATA -- -- -- -- MLC4OUT MLC3OUT MLC2OUT MLC1OUT 404 CLCxGLS0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N 400 CLCxGLS1 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N 401 CLCxGLS2 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 402 CLCxGLS3 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N 403 CLCxPOL POL -- -- -- G4POL G3POL G2POL G1POL 398 CLCxSEL0 -- -- D1S<5:0> 399 CLCxSEL1 -- -- D2S<5:0> 399 CLCxSEL2 -- -- D3S<5:0> 399 CLCxSEL3 -- -- D4S<5:0> 400 CLCINxPPS -- -- CLCINxPPS<5:0> 205, 207 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132 -- -- COG2IE ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE 135 PIR3 -- -- COG2IF ZCDIF CLC4IF CLC3IF CLC2IF CLC1IF 141 RxyPPS -- -- TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186 INTCON PIE3 TRISC Legend: MODE<2:0> 397 RxyPPS<5:0> 205 -- = unimplemented read as `0'. Shaded cells are not used for CLC module. 2015-2016 Microchip Technology Inc. DS40001819B-page 405 PIC16(L)F1777/8/9 29.0 OPERATIONAL AMPLIFIER (OPA) MODULES TABLE 29-1: The Operational Amplifier (OPA) is a standard threeterminal device requiring external feedback to operate. The OPA module has the following features: Device * * * * * External connections to I/O ports Low leakage inputs Factory Calibrated Input Offset Voltage Unity gain control Programmable positive and negative source selections * Override controls - Forced tri-state output - Forced unity gain FIGURE 29-1: AVAILABLE OP AMP MODULES OPA1 OP2 OPA3 PIC16(L)F1778 PIC16(L)F1777/9 OPA4 OPAx MODULE BLOCK DIAGRAM OPAxIN0+ EN OPAxIN1+ Internal analog sources See Register 29-4. 0 OPAx_out OPAXOUT OPA 1 PCH<1:0> OPAxIN0OPAxIN1Internal analog sources See Register 29-3. UG NCH<1:0> ORM1 Internal override sources See Register 29-2. ORS<1:0> ORM0 ORPOL DS40001819B-page 406 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 29.1 OPA Module Performance Common AC and DC performance specifications for the OPA module: * * * * * Common-Mode Voltage Range Leakage Current Input Offset Voltage Open-Loop Gain Gain Bandwidth Product Common-mode voltage range is the specified voltage range for the OPA+ and OPA- inputs, for which the OPA module will perform to within its specifications. The OPA module is designed to operate with input voltages between VSS and VDD. Behavior for commonmode voltages greater than VDD, or below VSS, are not guaranteed. Leakage current is a measure of the small source or sink currents on the OPA+ and OPA- inputs. To minimize the effect of leakage currents, the effective impedances connected to the OPA+ and OPA- inputs should be kept as small as possible and equal. Input offset voltage is a measure of the voltage difference between the OPA+ and OPA- inputs in a closed loop circuit with the OPA in its linear region. The offset voltage will appear as a DC offset in the output equal to the input offset voltage, multiplied by the gain of the circuit. The input offset voltage is also affected by the common-mode voltage. The OPA is factory calibrated to minimize the input offset voltage of the module. Open-loop gain is the ratio of the output voltage to the differential input voltage, (OPA+) - (OPA-). The gain is greatest at DC and falls off with frequency. Gain Bandwidth Product or GBWP is the frequency at which the open-loop gain falls off to 0 dB. 29.2 OPA Module Control The OPA module is enabled by setting the OPAxEN bit of the OPAxCON register (Register 29-1). When enabled, the OPA forces the output driver of the OPAxOUT pin into tri-state to prevent contention between the driver and the OPA output. Note: 29.2.1 When the OPA module is enabled, the OPAxOUT pin is driven by the op amp output, not by the PORT digital driver. Refer to Table 36-17: Operational Amplifier (OPA) for the op amp output drive capability. 29.2.2 PROGRAMMABLE SOURCE SELECTIONS The inverting and non-inverting sources are selected with the OPAxNCHS (Register 29-3) and OPAxPCHS (Register 29-4) registers, respectively. Sources include: * * * * Internal DACs Device pins Internal slope compensation ramp generator Other op amps in the device 29.3 29.3.1 Override Control OVERRIDE MODE The op amp operation can be overridden in two ways: * Forced tri-state output * Force unity gain The Override mode is selected with the ORM<1:0> bits of the OPxCON register (Register 29-1). The override is in effect when the mode is selected and the override source is true. 29.3.2 OVERRIDE SOURCES The override source is selected with the OPAxORS register (Register 29-2). Sources are from internal peripherals including: * * * * * * CCP outputs PWM outputs Comparator outputs Zero-cross detect output Configurable Logic Cell outputs COG outputs 29.3.3 OVERRIDE SOURCE POLARITY The override source polarity can be inverted so that the override will occur on either the high or low level of the selected source. Override polarity is controlled by the ORPOL bit of the OPAxCON register (Register 29-1). 29.4 Effects of Reset A device Reset forces all registers to their Reset state. This disables the OPA module. 29.5 Effects of Sleep The operational amplifier continues to operate when the device is put in Sleep mode. UNITY GAIN MODE The OPAxUG bit of the OPAxCON register (Register 29-1) selects the Unity Gain mode. When unity gain is selected, the OPA output is connected to the inverting input and the OPAxIN pin is relinquished, releasing the pin for general purpose input and output. 2015-2016 Microchip Technology Inc. DS40001819B-page 407 PIC16(L)F1777/8/9 29.6 Register Definitions: Op Amp Control Long bit name prefixes for the op amp peripherals are shown in Table 29-2. Refer to Section 1.1 "Register and Bit naming conventions" for more information TABLE 29-2: Peripheral Bit Name Prefix OPA1 OPA1 OPA2 OPA2 Note 1: OPA3 OPA3 OPA4(1) OPA4 PIC16(L)F1777/9 only. REGISTER 29-1: OPAxCON: OPERATIONAL AMPLIFIER (OPAx) CONTROL REGISTER R/W-0/0 U-0 U-0 R/W-0/0 U-0 R/W-0/0 EN -- -- UG -- ORPOL R/W-0/0 R/W-0/0 ORM<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 EN: Op Amp Enable bit 1 = Op amp is enabled 0 = Op amp is disabled and consumes no active power bit 6-5 Unimplemented: Read as `0' bit 4 UG: Op Amp Unity Gain Select bit 1 = OPA output is connected to inverting input. OPAxIN- pin is available for general purpose I/O. 0 = Inverting input is connected to the OPAxIN- pin bit 3 Unimplemented: Read as `0' bit 2 ORPOL: Op Amp Override Source Polarity bit 1 = Override source polarity is inverted. Override occurs when source is high. 0 = Override source polarity is not inverted. Override occurs when source is low. bit 1-0 ORM<1:0>: Op Amp Override Mode Selection bits 11 = Reserved. Do not use. 10 = Op amp is forced to unity gain when override source is true. 01 = Op amp output is tri-stated when override source is true. 00 = Output override function is disabled. DS40001819B-page 408 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 29-2: OPAxORS: OP AMP OVERRIDE SOURCE SELECTION REGISTER U-0 U-0 U-0 -- -- -- R/W-0/0 R/W-0/x R/W-0/x R/W-0/0 R/W-0/x ORS<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as `0' bit 4-0 ORS<4:0>: Op Amp Output Override Source Selection bits See Table 29-3: Override Sources TABLE 29-3: OVERRIDE SOURCES ORS<4:0> OPA1 OPA2 OPA3 OPA4(1) 11111 COG2D COG2D COG4D(1) COG4D 11110 COG2C COG2C COG4C(1) COG4C 11101 COG2B COG2B COG4B(1) COG4B 11100 COG2A COG2A COG4A(1) COG4A 11011 COG1D COG1D COG3D COG3D 11010 COG1C COG1C COG3C COG3C 11001 COG1B COG1B COG3B COG3B 11000 COG1A COG1A COG3A COG3A 10111 LC4_out LC4_out LC4_out LC4_out 10110 LC3_out LC3_out LC3_out LC3_out 10101 LC2_out LC2_out LC2_out LC2_out 10100 LC1_out LC1_out LC1_out (1) sync_C8OUT (1) LC1_out sync_C8OUT (1) sync_C8OUT 10011 sync_C8OUT 10010 sync_C7OUT(1) sync_C7OUT(1) sync_C7OUT(1) sync_C7OUT 10001 sync_C6OUT sync_C6OUT sync_C6OUT sync_C6OUT 10000 sync_C5OUT sync_C5OUT sync_C5OUT sync_C5OUT 01111 sync_C4OUT sync_C4OUT sync_C4OUT sync_C4OUT 01110 sync_C3OUT sync_C3OUT sync_C3OUT sync_C3OUT 01101 sync_C2OUT sync_C2OUT sync_C2OUT sync_C2OUT 01100 sync_C1OUT sync_C1OUT sync_C1OUT sync_C1OUT 01011 PWM12_out(1) PWM12_out(1) PWM12_out(1) PWM12_out 01010 PWM11_out PWM11_out PWM11_out PWM11_out 01001 PWM6_out PWM6_out PWM6_out PWM6_out 01000 PWM5_out PWM5_out PWM5_out PWM5_out (1) (1) 00111 PWM10_out PWM10_out PWM10_out 00110 PWM9_out PWM9_out PWM9_out PWM9_out 00101 PWM4_out PWM4_out PWM4_out PWM4_out 00100 PWM3_out PWM3_out PWM3_out PWM3_out 00011 CCP8_out(1) CCP8_out(1) CCP8_out(1) CCP8_out 00010 CCP7_out CCP7_out CCP7_out CCP7_out 00001 CCP2_out CCP2_out CCP2_out CCP2_out 00000 CCP1_out CCP1_out CCP1_out CCP1_out Note 1: PWM10_out (1) PIC16(L)F1777/9 only. 2015-2016 Microchip Technology Inc. DS40001819B-page 409 PIC16(L)F1777/8/9 REGISTER 29-3: OPAxNCHS: OP AMP NEGATIVE CHANNEL SOURCE SELECT REGISTER U-0 U-0 U-0 U-0 -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NCH<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-4 Unimplemented: Read as `0' bit 3-0 NCH<3:0>: Op Amp Inverting Input Channel Selection bits See Table 29-4: Inverting Input Sources TABLE 29-4: INVERTING INPUT SOURCES NCH<3:0> OPA1 OPA2 OPA3 OPA4(1) 1111 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use 1110 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use 1101 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use 1100 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use 1011 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use 1010 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use 1001 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use PRG4_out 1000 PRG2_out PRG2_out PRG4_out(1) 0111 PRG1_out PRG1_out PRG3_out PRG3_out 0110 FVR_Buffer1 FVR_Buffer1 FVR_Buffer2 FVR_Buffer2 0101 DAC4_out DAC4_out DAC8_out(1) DAC8_out 0100 DAC3_out DAC3_out DAC7_out DAC7_out 0011 DAC2_out DAC2_out DAC6_out(1) DAC6_out 0010 DAC1_out DAC1_out DAC5_out DAC5_out 0001 OPA1IN1- OPA2IN1- OPA3IN1-(1) OPA4IN1- 0000 OPA1IN0- OPA2IN0- OPA3IN0- OPA3IN0- Note 1: PIC16(L)F1777/9 only. DS40001819B-page 410 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 29-4: OPAxPCHS: OP AMP POSITIVE CHANNEL SOURCE SELECT REGISTER U-0 U-0 U-0 U-0 -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PCH<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-4 Unimplemented: Read as `0' bit 3-0 PCH<3:0>: Op Amp Non-Inverting Input Channel Selection bits See Table 29-5: Non-Inverting Input Sources TABLE 29-5: NON-INVERTING INPUT SOURCES NCH<3:0> OPA1 OPA2 OPA3 OPA4(1) 1111 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use 1110 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use 1101 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use 1100 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use 1011 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use 1010 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use 1001 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use 1000 PRG2_out PRG2_out PRG4_out(1) PRG4_out 0111 PRG1_out PRG1_out PRG3_out PRG3_out 0110 FVR_Buffer1 FVR_Buffer1 FVR_Buffer2 FVR_Buffer2 0101 DAC4_out DAC4_out DAC8_out(1) DAC8_out 0100 DAC3_out DAC3_out DAC7_out DAC7_out 0011 DAC2_out DAC2_out DAC6_out(1) DAC6_out 0010 DAC1_out DAC1_out DAC5_out DAC5_out 0001 OPA1IN1+ OPA2IN1+ OPA3IN1+(1) OPA4IN1+ 0000 OPA1IN0+ OPA2IN0+ OPA3IN0+ OPA4IN0+ Note 1: PIC16(L)F1777/9 only. 2015-2016 Microchip Technology Inc. DS40001819B-page 411 PIC16(L)F1777/8/9 TABLE 29-6: SUMMARY OF REGISTERS ASSOCIATED WITH OP AMPS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELB --- --- ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182 ANSELC ANSC3 ANSC2 -- -- 187 Name ANSC7 ANSC6 ANSC5 ANSC4 DAC1CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 249 DAC2CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 249 DAC5CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 249 DAC3CON0 EN -- OE1 OE2 PSS<1:0> NSS<1:0> 244 DAC4CON0 EN -- OE1 OE2 PSS<1:0> NSS<1:0> 244 DAC7CON0 EN -- OE1 OE2 PSS<1:0> NSS<1:0> DAC3REF --- --- --- REF<4:0> 245 DAC4REF --- --- --- REF<4:0> 245 DAC7REF --- --- --- REF<4:0> 245 244 DAC1REFH REF<9:x> (x Depends on FM bit) 250 DAC2REFH REF<9:x> (x Depends on FM bit) 250 DAC5REFH REF<9:x> (x Depends on FM bit) FVRCON FVREN FVRRDY TSEN TSRNG OPAxCON EN -- -- UG OPAxNCHS -- -- -- -- OPAxPCHS -- -- -- -- OPAxORS -- -- -- 250 CDAFVR<1:0> -- ADFVR<1:0> ORPOL ORM<1:0> NCH<3:0> 223 408 410 PCH<3:0> 411 ORS<4:0> 409 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186 Legend: -- = unimplemented location, read as `0'. Shaded cells are not used by op amps. DS40001819B-page 412 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 30.0 PROGRAMMABLE RAMP GENERATOR (PRG) MODULE The Programmable Ramp Generator (PRG) module is designed to provide rising and falling linear ramps. Typical applications include slope compensation for fixed frequency, continuous current, and Current mode switched power supplies. Slope compensation is a necessary feature of these power supplies because it prevents frequency instabilities at duty cycles greater than 50%. The PRG has the following features: * * * * Linear positive and negative voltage ramp outputs Programmable current source/sink Internal and external reference voltage selection Internal and external timing source selection A simplified block diagram of the PRG is shown in Figure 30-1. TABLE 30-1: Device AVAILABLE PRG MODULES PRG1 PRG2 PRG3 PIC16(L)F1778 PIC16(L)F1777/9 30.1 PRG4 Fundamental Operation The PRG can be operated in three voltage ramp generator modes: * Falling Voltage (slope compensation) * Rising Voltage * Alternating Rising and Falling Voltage In the Rising or Falling mode an internal capacitor is discharged when the set_falling timing input is true and charged by an internally generated constant current when the set_rising timing input is true. The resulting linear ramp starts at the selected voltage input level and resets back to that level when the ramp is terminated by the set_falling timing input. The set_falling input dominates when both timing inputs are true. To control the operation with a single-ended source, select the same source for both the set_rising and set_falling inputs and invert the polarity of one of them with the corresponding polarity control bit. In the Alternating mode the capacitor is not discharged but alternates between being charged in one direction then the other. Input selections are identical for all modes. The input voltage is supplied by any of the following: * The PRGxIN0 or PRGxIN1 pins * The buffered output of the internal Fixed Voltage Reference (FVR), * Any of the internal DACs. The timing sources are selected from the following: * The synchronized output of any comparator * Any PWM output * Any I/O pin 2015-2016 Microchip Technology Inc. The ramp output is available as an input to any of the comparators or op amps. 30.1.1 SLOPE COMPENSATION Slope compensation works by quickly discharging an internal capacitor at the beginning of each PWM period. One side of the internal capacitor is connected to the voltage input source and the other side is connected to the internal current sink. The internal current sink charges this capacitor at a programmable rate. As the capacitor charges, the capacitor voltage is subtracted from the voltage source, producing a linear voltage decay at the required rate (see Figure 30-2). The ramp terminates and the capacitor is discharged when the set_falling timing input goes true. The next ramp starts when the set_rising timing input goes true. Enabling the optional one-shot by setting the OS bit of the PRGxCON0 register ensures that the capacitor is fully discharged by overriding the set_rising timing input and holding the shorting switch closed for at least the one-shot period, typically 50 ns. Edge sensitive timing inputs that occur during the one-shot period will be ignored. Level sensitive timing inputs that occur during, and extend beyond, the one-shot period will be suspended until the end of the one-shot time. 30.1.2 RAMP GENERATION Ramp generation is similar to slope compensation except that the slope is either both rising and falling or just rising. 30.1.2.1 Alternating Rising/Falling Ramps The alternating rising/falling ramp generation function works by employing the built-in current source and sink and relying on the synchronous control of the internal analog switches and timing sources to ramp the module's output voltage up and then subsequently down. Once initialized, the output voltage is ramped up linearly by the current source at a programmable rate until the set_falling timing source goes true, at which point the current source is disengaged. At the same time, the current sink is engaged to linearly ramp down the output voltage, also at a programmable rate, until the set_rising timing input goes true, thereby reversing the ramp slope. The process then repeats to create a saw tooth like waveform as shown in Figure 30-3 and Figure 30-4. The set_rising and set_falling timing inputs can be either edge or level sensitive which is selected with the respective REDG and FEDG bits of the PRGxCON0 register. Edge sensitive operation is recommended for periodic signals such as clocks, and level sensitive operation is recommended for analog limit triggers such as comparator outputs. When the one-shot is enabled (OS bit is set) then both the falling and rising ramps will persist for a minimum of the one-shot period. Edge sensitive timing inputs that occur during the one-shot period will be ignored. Level DS40001819B-page 413 PIC16(L)F1777/8/9 sensitive timing inputs that occur during, and extend beyond, the one-shot period will be suspended until the end of the one-shot time. 30.1.2.2 Rising Ramp The Rising Ramp mode is identical to the Slope Compensation mode except that the ramps have a rising slope instead of a falling slope. One side of the internal capacitor is connected to the voltage input source and the other side is connected to the internal current source. The internal current source charges this capacitor at a programmable rate. As the capacitor charges, the capacitor voltage is added to the voltage source, producing a linear voltage rise at the required rate (see Figure 30-5). The ramp terminates and the capacitor is discharged when the set_falling timing input goes true. The next ramp starts when the set_rising timing input goes true. Enabling the optional one-shot by setting the OS bit of the PRGxCON0 register ensures that the capacitor is fully discharged by overriding the set_rising timing input and holding the shorting switch closed for at least the one-shot period, typically 50 ns. Edge sensitive timing inputs that occur during the one-shot period will be ignored. Level sensitive timing inputs that occur during, and extend beyond, the one-shot period will be suspended until the end of the one-shot time. 30.2 Enable, Ready, Go The EN bit of the PRGxCON0 register enables the analog circuitry including the current sources. This permits preparing the PRG module for use and allowing it to become stable before putting it into operation. When the EN bit is set then the timing inputs are enabled so that initial ramp action can be determined before the GO bit is set. The capacitor shorting switch is closed when the EN bit is set and remains closed while the GO bit is zero. The RDY bit of the PRGxCON1 register indicates that the analog circuits and current sources are stable. The GO bit of the PRGxCON0 register enables the switch control circuits, thereby putting the PRG into operation. The GO transition from cleared to set triggers the one-shot, thereby extending the capacitor shorting switch closure for the one-shot period. To ensure predictable operation, set the EN bit first then wait for the RDY bit to go high before setting the GO bit. 30.3 Independent Set_rising and Set_falling Timing Inputs The timing inputs determine when the ramp starts and stops. In the Alternating Rising/Falling mode the ramp rises when the set_rising input goes true and falls when the set_falling input goes true. In the Slope Compensation and Rising Ramp modes the capacitor is discharged when the set_falling timing input goes true and the ramp starts when the set_rising timing input goes true. The set_falling input dominates the set_rising input. DS40001819B-page 414 30.4 Level and Edge Timing Sensitivity The set_rising and set_falling timing inputs can be independently configured as either level or edge sensitive. Level sensitive operation is useful when it is necessary to detect a timing input true state after an overriding condition ceases. For example, level sensitivity is useful for capacitor generated timing inputs that may be suppressed by the overriding action of the one-shot. With level sensitivity a capacitor output that changes during the one-shot period will be detected at the end of the one-shot time. With edge sensitivity the change would be ignored. Edge sensitive operation is useful for periodic timing inputs such as those generated by PWMs and clocks. The duty cycle of a level sensitive periodic signal may interfere with the other timing input. Consider an Alternating Ramp mode with a level sensitive 50% PWM as the set_rising timing source and a level sensitive comparator as the set_falling timing source. If the comparator output reverses the ramp while the PWM signal is still high then the ramp will improperly reverse again when the comparator signal goes low. That same scenario with the set_rising timing input set for edge sensitivity would properly change the ramp output to rising only on the rising edge of the PWM signal. Set_rising and set_falling timing input edge sensitivity is selected with the respective REDG and FEDG bits of the PRGxCON1 register. 30.5 One-Shot Minimum Timing The one-shot timer ensures a minimum capacitor discharge time in the Slope Compensation and Rising Ramp modes, and a minimum rising or falling ramp duration in the Alternating Ramp mode. Setting the OS bit of the PRGxCON0 register enables the one-shot timer. 30.6 DAC Voltage Sources When using any of the DACs as the voltage source expect a voltage offset equal to the current setting times the DAC equivalent resistance. This will be a constant offset in the Slope Compensation and Ramp modes and a positive/negative step offset in the Alternating mode. To avoid this limitation, feed the DAC output to the PRG input through one of the op amps set for unity gain. 30.7 Operation During Sleep The RG module is unaffected by Sleep. 30.8 Effects of a Reset The RG module resets to a disabled condition. 2015-2016 Microchip Technology Inc. 2015-2016 Microchip Technology Inc. FIGURE 30-1: SIMPLIFIED PRG MODULE BLOCK DIAGRAM Rev. 10-000 220A 5/29/201 4 VDD See Table 30-4 ISET<4:0> RTSS<3:0> RPOL SW2 Set_rising Timing Sources (See Table 30-5) RAMPx_out PRGxR PPS to peripherals GO REDG PRGxRPPS EN S Q Switch Control FTSS<3:0> SW1 R FEDG PRGxF OS MODE<1:0> PPS Voltage Sources (See Table 30-3) voltage_ref PRGxIN SW3 FPOL INS<3:0> PRGxFPPS DS40001819B-page 415 See Table 30-4 ISET<4:0> PIC16(L)F1777/8/9 Set_falling Timing Sources (See Table 30-5) SLOPE COMPENSATION (FALLING RAMP) TIMING DIAGRAM (MODE = 00) Rev. 10-000 223A 5/2/201 4 Init EN RDY GO OS set_rising set_falling one_shot sw1_closed sw2_closed sw3_closed voltage_ref 2015-2016 Microchip Technology Inc. RAMPx_out Running Init Running PIC16(L)F1777/8/9 DS40001819B-page 416 FIGURE 30-2: 2015-2016 Microchip Technology Inc. FIGURE 30-3: ALTERNATING RISING/FALLING RAMP GENERATION TIMING DIAGRAM (OS = 0, MODE = 01) Rev. 10-000 222A 4/29/201 4 Init Running Init Running EN RDY GO REDG FEDG set_rising set_falling one_shot sw1_closed sw2_closed voltage_ref RAMPx_out DS40001819B-page 417 PIC16(L)F1777/8/9 sw3_closed ALTERNATING RISING/FALLING RAMP GENERATION TIMING DIAGRAM (OS = 1, MODE = 01) Rev. 10-000 226A 5/2/201 4 Init EN RDY GO REDG FEDG set_rising set_falling one_shot sw1_closed sw2_closed sw3_closed 2015-2016 Microchip Technology Inc. voltage_ref RAMPx_out Running Init Running PIC16(L)F1777/8/9 DS40001819B-page 418 FIGURE 30-4: 2015-2016 Microchip Technology Inc. FIGURE 30-5: RISING RAMP GENERATION TIMING DIAGRAM (MODE = 10) Rev. 10-000 224A 5/2/201 4 Init Running Init Running EN RDY GO OS set_rising set_falling one_shot sw1_closed sw2_closed sw3_closed voltage_ref DS40001819B-page 419 PIC16(L)F1777/8/9 RAMPx_out PIC16(L)F1777/8/9 30.9 For example, when the circuit is using a 1 current sense resistor and the peak current is 1A, then the peak current expressed as a voltage is 1V. Therefore, for this example, the op amp output should be designed to operate at 1V. If the power supply PWM frequency is 1 MHz, then the period is 1 s. Therefore, the desired slope is 0.5 V/s, which is computed as shown in Equation 30-2. Slope Compensation Application An example slope compensation circuit is shown in Figure 30-6. The PRG input voltage is PRGxIN which shares an I/O pin with the op amp output. The op amp output is designed to operate at the expected peak current sense voltage (i.e., VREF). The PRG output voltage starts at VREF and should fall at a rate less than half the target circuit current sense voltage rate of rise. Therefore, the compensator slope expressed as volts per s can be computed by Equation 30-1. EQUATION 30-2: EQUATION 30-1: 1 V REF --------------2 2 -------------------------------------------- = --------- = 0.5V s 1s PWM Period ( s V REF ------------V 2 ------ ------------------------------------------- s PWM Period ( s FIGURE 30-6: Note: The setting for 0.5V/s is ISET<4:0> = 6 EXAMPLE SLOPE COMPENSATION CIRCUIT Rev. 10-000 221A 5/7/201 4 VIN L1 D1 COGxOUTx COG C1 - + R2 CxINxR1 PRG RGxIN DAC OPAxOUT + OPAxIN- R4 R3 - C2 R5 C3 DS40001819B-page 420 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 30.10 Register Definitions: Slope Compensation Control Long bit name prefixes for the PRG peripherals are shown in Table 30-2. Refer to Section 1.1 "Register and Bit naming conventions" for more information TABLE 30-2: Peripheral Bit Name Prefix PRG1 RG1 PRG2 RG2 PRG3 RG3 PRG4(1) RG4 Note 1: PIC16(L)F1777/9 only. REGISTER 30-1: PRGxCON0: PROGRAMMABLE RAMP GENERATOR CONTROL 0 REGISTER R/W-0/0 U-0 R/W-0/0 R/W-0/0 EN -- FEDG REDG R/W-0/0 R/W-0/0 MODE<1:0> R/W-0/0 R/W-0/0 OS GO bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = value depends on configuration bits bit 7 EN: Programmable Ramp Generator Enable bit 1 = PRG module is enabled 0 = PRG module is disabled bit 6 Unimplemented: Read as `0' bit 5 FEDG: Set_falling Input Mode Select bit 1 = Set_falling timing input is edge sensitive 0 = Set_falling timing input is level sensitive bit 4 REDG: Set_rising Input Mode Select bit 1 = Set_rising timing input is edge sensitive 0 = Set_rising timing input is level sensitive bit 3-2 MODE<1:0>: Programmable Ramp Generator Mode Selection bits 11 = Reserved 10 = Rising Ramp Generator 01 = Alternating Rising/Falling Ramp Generator 00 = Slope Compensation bit 1 OS: One-Shot Enable bit 1 = One-shot is enabled. Minimum capacitor discharge is internally timed by one-shot. 0 = One-shot is disabled. Capacitor is discharged when timing input is true. bit 0 GO: Ramp Generation Control Start bit if EN = 1: 1 = Slope or Ramp function is operating 0 = Slope or Ramp function is not operating. All current source current source switches are open and capacitor discharge switch is closed. If EN = 0: This bit is forced to 0 2015-2016 Microchip Technology Inc. DS40001819B-page 421 PIC16(L)F1777/8/9 REGISTER 30-2: PRGxCON1: PROGRAMMABLE RAMP GENERATOR CONTROL 1 REGISTER U-0 U-0 U-0 U-0 U-0 R-0 R/W-0/0 R/W-0/0 -- -- -- -- -- RDY FPOL RPOL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = value depends on configuration bits bit 7-3 Unimplemented: Read as `0' bit 2 RDY: Slope Generator Ready Status bit 1 = PRG is ready 0 = PRG is not ready bit 1 FPOL: Fall Event Polarity Select bit 1 = Set_falling timing input is active-low 0 = Set_falling timing input is active-high bit 0 RPOL: Rise Event Polarity Select bit 1 = Set_rising timing input is active-low 0 = Set_rising timing input is active-high REGISTER 30-3: PRGxINS: VOLTAGE INPUT SELECT REGISTER U-0 U-0 U-0 U-0 -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 INS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = value depends on configuration bits bit 7-4 Unimplemented: Read as `0' bit 3-0 INS<3:0>: Voltage Input Select bits Selects source of voltage level at which the ramp starts. See Table 30-3. TABLE 30-3: INS<2:0> 1010-1111 VOLTAGE INPUT SOURCES PRG4 Voltage Source(2) PRG1 Voltage Source PRG2 Voltage Source PRG3 Voltage Source Reserved Reserved Reserved Reserved Switched PRG3IN1/OPA4OUT(2) Switched PRG4IN1/OPA3OUT 1001(1) Switched PRG1IN1/OPA2OUT Switched PRG1IN1/OPA2OUT 1000(1) Switched PRG1IN0/OPA1OUT Switched PRG1IN0/OPA1OUT Switched PRG3IN0/OPA3OUT Switched PRG4IN0/OPA4OUT 0111 Reserved Reserved Reserved Reserved 0110 DAC4_output DAC4_output DAC8_output(2) DAC8_output 0101 DAC3_output DAC3_output DAC7_output DAC7_output 0100 DAC2_output DAC2_output DAC6_output(2) DAC6_output 0011 DAC1_output DAC1_output DAC5_output DAC5_output 0010 FVR_buffer1 FVR_buffer1 FVR_buffer2 FVR_buffer2 0001 PRG1IN1/OPA2OUT PRG2IN1/OPA1OUT PRG3IN1/OPA4OUT(2) PRG4IN1/OPA3OUT 0000 PRG1IN0/OPA1OUT PRG2IN0/OPA2OUT PRG3IN0/OPA3OUT PRG4IN0/OPA4OUT Note 1: 2: Input source is switched off when op amp override is forcing tri-state. See Section 29.3 "Override Control". PIC16(L)F1777/9 only. DS40001819B-page 422 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 30-4: PRGxCON2: PROGRAMMABLE RAMP GENERATOR CONTROL 2 REGISTER U-0 U-0 U-0 -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ISET<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = value depends on configuration bits bit 7-5 Unimplemented: Read as `0' bit 4-0 ISET<4:0>: PRG Current Source/Sink Set bits Current source/sink setting and slope rate. See Table 30-4. TABLE 30-4: ISET<4:0> PROGRAMMABLE RAMP GENERATOR CURRENT SETTINGS Current Setting (uA) Slope Rate (V/us) ISET<4:0> Current Setting (uA) Slope Rate (V/us) 0h 2 0.2 10h 10 1.0 1h 2.5 0.25 11h 11 1.1 2h 3 0.3 12h 12 1.2 3h 3.5 0.35 13h 13 1.3 4h 4 0.4 14h 14 1.4 5h 4.5 0.45 15h 15 1.5 6h 5 0.5 16h 16 1.6 7h 5.5 0.55 17h 17 1.7 8h 6 0.6 18h 18 1.8 9h 6.5 0.65 19h 19 1.9 Ah 7 0.7 1Ah 20 2.0 Bh 7.5 0.75 1Bh 21 2.1 Ch 8 0.8 1Ch 22 2.2 Dh 8.5 0.85 1Dh 23 2.3 Eh 9 0.9 1Eh 24 2.4 Fh 9.5 0.95 1Fh 25 2.5 2015-2016 Microchip Technology Inc. DS40001819B-page 423 PIC16(L)F1777/8/9 REGISTER 30-5: PRGxRTSS: SET_RISING TIMING SOURCE SELECT REGISTER U-0 U-0 U-0 U-0 -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 RTSS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = value depends on configuration bits bit 7-4 Unimplemented: Read as `0' bit 3-0 RTSS<3:0>: Set_rising Timing Source Select bits See Table 30-5. REGISTER 30-6: PRGxFTSS: SET_FALLING TIMING SOURCE SELECT REGISTER U-0 U-0 U-0 U-0 -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 FTSS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = value depends on configuration bits bit 7-4 Unimplemented: Read as `0' bit 3-0 FTSS<3:0>: Set_falling Timing Source Select bits See Table 30-5. DS40001819B-page 424 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 30-5: PROGRAMMABLE RAMP GENERATOR TIMING SOURCES RTSS<3:0>/ FTSS<3:0> PRG1 Timing Source PRG2 Timing Source PRG3 Timing Source PRG4 Timing Source(2) 1111 Reserved Reserved PWM12_output(2) PWM12_output 1110 Reserved Reserved PWM11_output PWM11_output 1101 LC2_out LC2_out PWM6_output PWM6_output 1100 LC1_out LC1_out PWM5_output PWM5_output 1011 PWM10_output(2) PWM10_output(2) Reserved Reserved 1010 PWM9_output PWM9_output Reserved Reserved 1001 PWM4_output PWM4_output LC4_out(2) LC4_out 1000 PWM3_output PWM3_output LC3_out LC3_out 0111 PRGxR/PRGxF Pin(1) PRGxR/PRGxF Pin(1) PRGxR/PRGxF Pin(1) PRGxR/PRGxF Pin(1) 0110 Reserved Reserved sync_C7OUT(2) sync_C7OUT 0101 Reserved Reserved sync_C6OUT sync_C6OUT 0100 Reserved Reserved sync_C5OUT sync_C5OUT 0011 sync_C4OUT sync_C4OUT Reserved Reserved 0010 sync_C3OUT sync_C3OUT Reserved Reserved 0001 sync_C2OUT sync_C2OUT Reserved Reserved 0000 sync_C1OUT sync_C1OUT Reserved Reserved Note 1: 2: Input pin is selected with the PRGxRPPS or PRGxFPPS register. PIC16(L)F1777/9 only. 2015-2016 Microchip Technology Inc. DS40001819B-page 425 PIC16(L)F1777/8/9 TABLE 30-6: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE PRG MODULE(1) Bit 3 Bit 2 Register on Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 PRGxCON0 EN -- FEDG REDG OS GO PRGxCON1 -- -- -- -- 421 FPOL RPOL 422 PRGxCON2 -- -- -- PRGxINS -- -- -- PRGxRPPS -- -- PRGxRPPS<5:0> 424 PRGxFPPS -- -- PRGxFPPS<5:0> 424 MODE<1:0> -- RDY ISET<4:0> 423 INS<3:0> -- 422 PRGxRTSS -- -- -- -- RTSS<3:0> PRGxFTSS -- -- -- -- FTSS<3:0> PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 186 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 -- -- 187 WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 188 Legend: Note 1: 205, 207 205, 207 -- = unimplemented, read as `0'. Shaded cells are unused by the PRG module. PRG4 available on PIC16(L)F1777/9 only. DS40001819B-page 426 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 31.0 DATA SIGNAL MODULATOR (DSM) The Data Signal Modulator (DSM) is a peripheral that allows the user to mix a data stream, also known as a modulator signal, with a carrier signal to produce a modulated output. Both the carrier and the modulator signals are supplied to the DSM module either internally, from the output of a peripheral, or externally through an input pin. The modulated output signal is generated by performing a logical "AND" operation of both the carrier and modulator signals and then provided to the MDxOUT pin. The carrier signal is comprised of two distinct and separate signals. A carrier high (CARH) signal and a carrier low (CARL) signal. During the time in which the modulator (MOD) signal is in a logic high state, the DSM mixes the carrier high signal with the modulator signal. When the modulator signal is in a logic low state, the DSM mixes the carrier low signal with the modulator signal. Using this method, the DSM can generate the following types of Key Modulation schemes: * Frequency-Shift Keying (FSK) * Phase-Shift Keying (PSK) * On-Off Keying (OOK) Additionally, the following features are provided within the DSM module: * * * * * * * Carrier Synchronization Carrier Source Polarity Select Carrier Source Pin Disable Programmable Modulator Data Modulator Source Pin Disable Modulated Output Polarity Select Slew Rate Control Figure 31-1 shows a Simplified Block Diagram of the Data Signal Modulator peripheral. TABLE 31-1: Device AVAILABLE DSM MODULES DSM1 DSM2 DSM3 PIC16(L)F1778 PIC16(L)F1777/9 2015-2016 Microchip Technology Inc. DSM4 DS40001819B-page 427 PIC16(L)F1777/8/9 FIGURE 31-1: SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR CH<3:0> MDXCHPPS EN PPS Data Signal Modulator Carrier High Sources CARH See Table 31-6 CHPOL D SYNC MS<3:0> MDXMODPPS Q 1 PPS 0 Modulation Sources MDX_OUT MOD CHSYNC See Table 31-6 PPS OPOL CL<3:0> RXYPPS D MDXCLPPS SYNC PPS Q Carrier Low Sources See Table 31-7. MDXOUT 1 0 CARL CLSYNC CLPOL DS40001819B-page 428 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 31.1 DSM Operation The DSM module is enabled by setting the EN bit in the MDxCON register. Clearing the EN bit in the MDxCON register disables the DSM module by automatically switching the carrier high and carrier low signals to the VSS signal source. The modulator signal source is also switched to the BIT bit in the MDxCON0 register. This not only assures that the DSM module is inactive, but that it is also consuming the least amount of current. The values used to select the carrier high, carrier low, and modulator sources held by the Modulation Source, Modulation High Carrier, and Modulation Low Carrier control registers are not affected when the EN bit is cleared and the DSM module is disabled. The values inside these registers remain unchanged while the DSM is inactive. The sources for the carrier high, carrier low and modulator signals will once again be selected when the EN bit is set and the DSM module is enabled and active. The modulated output signal can be output on any device I/O pin by selecting the desired DSM module in the pin's PPS control register (see Register 12-2). If the output is not directed to any I/O pin then the DSM module will remain active and continue to mix signals, but the output value will not be sent to any pin. 31.2 31.3 Carrier Signal Sources The carrier high signal is selected by configuring the CH<4:0> bits of the MDxCARH register. Selections are shown in Table 31-6. The carrier low signal is selected by configuring the CL<4:0> bits of the MDxCARL register. Selections are shown in Table 31-7. 31.4 Carrier Synchronization During the time when the DSM switches between carrier high and carrier low signal sources, the carrier data in the modulated output signal can become truncated. To prevent this, the carrier signal can be synchronized to the modulator signal. When synchronization is enabled, the carrier pulse that is being mixed at the time of the transition is allowed to transition low before the DSM switches over to the next carrier source. Synchronization is enabled separately for the carrier high and carrier low signal sources. Synchronization for the carrier high signal is enabled by setting the CHSYNC bit of the MDxCON1 register. Synchronization for the carrier low signal is enabled by setting the CLSYNC bit of the MDxCON1 register. Figure 31-1 through Figure 31-6 show timing diagrams of using various synchronization methods. Modulator Signal Sources The modulator signal is selected by configuring the MS<4:0> bits of the MDxSRC register. Selections are shown in Table 31-6. 2015-2016 Microchip Technology Inc. DS40001819B-page 429 PIC16(L)F1777/8/9 FIGURE 31-2: ON OFF KEYING (OOK) SYNCHRONIZATION Carrier Low (CARL) Carrier High (CARH) Modulator (MOD) 1 X MDx_out 0 X MDx_out MDCLSYNC MDCHSYNC FIGURE 31-3: NO SYNCHRONIZATION (MDCHSYNC = 0, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDx_out Active Carrier State FIGURE 31-4: CARH CARL CARH CARL CARRIER HIGH SYNCHRONIZATION (MDCHSYNC = 1, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDx_out Active Carrier State DS40001819B-page 430 CARH both CARL CARH both CARL 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 31-5: CARRIER LOW SYNCHRONIZATION (MDCHSYNC = 0, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDx_out Active Carrier State FIGURE 31-6: CARH CARL CARH CARL FULL SYNCHRONIZATION (MDCHSYNC = 1, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) Falling edges used to sync MDx_out Active Carrier State CARH 2015-2016 Microchip Technology Inc. CARL CARH CARL DS40001819B-page 431 PIC16(L)F1777/8/9 31.5 Input and Output Through Pins The modulation and carrier sources may be selected to come from any device pin with the PPS control logic. Selecting a pin requires two settings: The source selection determines that the PPS will be used and the PPS control selects the desired pin. Source and PPS registers are identified in Table 31-2. PPS register pin selections are shown in Register 12-1 and Register 12-2. TABLE 31-2: Source Register PPS Register Modulation MDxSRC MDxMODPPS Carrier High MDxCARH MDxCHPPS Carrier Low MDxCARL MDxCLPPS Source 31.9 Operation in Sleep Mode The DSM module is not affected by Sleep mode. The DSM will operate during Sleep provided that the Carrier and Modulator input sources are also active during Sleep. 31.10 Effects of a Reset Upon any device Reset, the data signal modulator module is disabled. The user's firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values. Any device pin can be selected as the modulation output with the individual pin PPS controls. See Register 12-2 for the pin output selections. 31.6 Carrier Source Polarity Select The signal provided from any selected input source for the carrier high and carrier low signals can be inverted. Inverting the signal for the carrier high source is enabled by setting the CHPOL bit of the MDxCON1 register. Inverting the signal for the carrier low source is enabled by setting the CLPOL bit of the MDxCON1 register. 31.7 Programmable Modulator Data The BIT bit of the MDxCON0 register can be selected as the source for the modulator signal. When the BIT source is selected then software generates the modulation signal by setting and clearing the BIT bit at the respective desired modulation high and low times. 31.8 Modulated Output Polarity The modulated output signal provided on the MDxOUT pin can also be inverted. Inverting the modulated output signal is enabled by setting the OPOL bit of the MDxCON0 register. DS40001819B-page 432 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 31.11 Register Definitions: Data Signal Modulator Long bit name prefixes for the 10-bit DAC peripherals are shown in Table 31-3. Refer to Section 1.1 "Register and Bit naming conventions" for more information TABLE 31-3: Peripheral Bit Name Prefix DSM1 DSM1 DSM2 DSM2 DSM3 DSM3 DSM4(1) DSM4 Note 1: PIC16(L)F1777/9 only. REGISTER 31-1: MDxCON0: MODULATION CONTROL REGISTER 0 R/W-0/0 U-0 R-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 EN -- OUT OPOL -- -- -- BIT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 EN: Modulator Module Enable bit 1 = Modulator module is enabled and mixing input signals 0 = Modulator module is disabled and has no output bit 6 Unimplemented: Read as `0' bit 5 OUT: Modulator Output bit Displays the current output value of the modulator module.(1) bit 4 OPOL: Modulator Output Polarity Select bit 1 = Modulator output signal is inverted. Idle high output. 0 = Modulator output signal is not inverted. Idle low output. bit 3-1 Unimplemented: Read as `0' bit 0 BIT: Allows direct software control of the modulation source input to module(2) 1 = Modulator uses High Carrier source 0 = Modulator uses Low Carrier source Note 1: 2: The modulated output frequency can be greater and asynchronous from the clock that updates this register bit, the bit value may not be valid for higher speed modulator or carrier signals. BIT must be selected as the modulation source in the MDSRC register for this operation. 2015-2016 Microchip Technology Inc. DS40001819B-page 433 PIC16(L)F1777/8/9 REGISTER 31-2: MDxCON1: MODULATION CONTROL REGISTER 1 U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 -- -- CHPOL CHSYNC -- -- CLPOL CLSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5 CHPOL: Modulation High Carrier Polarity Select bit 1 = Selected high carrier source is inverted 0 = Selected high carrier source is not inverted bit 4 CHSYNC: Modulation High Carrier Synchronization Enable bit 1 = Modulator waits for a low edge on the high carrier before allowing a switch to the low carrier 0 = Modulator output is not synchronized to the high carrier(1) bit 3-2 Unimplemented: Read as `0' bit 1 CLPOL: Modulation Low Carrier Polarity Select bit 1 = Selected low carrier source is inverted 0 = Selected low carrier source is not inverted bit 0 CLSYNC: Modulation Low Carrier Synchronization Enable bit 1 = Modulator waits for a low edge on the low carrier before allowing a switch to the high carrier 0 = Modulator output is not synchronized to the low carrier(1) Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. REGISTER 31-3: MDxSRC: MODULATION SOURCE CONTROL REGISTER U-0 U-0 U-0 -- -- -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u MS<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-5 Unimplemented: Read as `0' bit 4-0 MS<4:0> Modulation Source Selection bits See Table 31-4 or Table 31-5. DS40001819B-page 434 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 31-4: MODULATION SOURCE TABLE 31-5: MODULATION SOURCE MS<4:0> Modulation Source PIC16(L)F1777/9 MS<4:0> Modulation Source PIC16(L)F1778 11111 Reserved 11111 Reserved 11110 Reserved 11110 Reserved 11101 Reserved 11101 Reserved 11100 Reserved 11100 Reserved 11011 Reserved 11011 Reserved 11010 sync_C8OUT 11010 sync_C6OUT 11001 sync_C7OUT 11001 sync_C5OUT 11000 sync_C4OUT 11000 sync_C4OUT 10111 sync_C3OUT 10111 sync_C3OUT 10110 sync_C2OUT 10110 sync_C2OUT 10101 sync_C1OUT 10101 sync_C1OUT 10100 LC4_out 10100 LC4_out 10011 LC3_out 10011 LC3_out 10010 LC2_out 10010 LC2_out 10001 LC1_out 10001 LC1_out 10000 PWM12_out 10000 Reserved 01111 PWM11_out 01111 PWM11_out 01110 PWM6_out 01110 PWM6_out 01101 PWM5_out 01101 PWM5_out 01100 PWM10_out 01100 Reserved 01011 PWM9_out 01011 PWM9_out 01010 PWM4_out 01010 PWM4_out 01001 PWM3_out 01001 PWM3_out 01000 PWM8_out 01000 Reserved 00111 CCP7_out 00111 CCP7_out 00110 CCP2_out 00110 CCP2_out 00101 CCP1_out 00101 CCP1_out 00100 SDO_OUT 00100 SDO_OUT 00011 DT 00011 DT 00010 TX_out 00010 TX_out 00001 MDxBIT 00001 MDxBIT 00000 MDxMODPPS pin selection 00000 MDxMODPPS pin selection 2015-2016 Microchip Technology Inc. DS40001819B-page 435 PIC16(L)F1777/8/9 REGISTER 31-4: MDxCARH: MODULATION HIGH CARRIER CONTROL REGISTER U-0 U-0 U-0 -- -- -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u CH<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-5 Unimplemented: Read as `0' bit 4-0 CH<4:0> Modulator Data High Carrier Selection bits(1) See Table 31-6. Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. DS40001819B-page 436 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 31-6: HIGH CARRIER SOURCE CH<4:0> Carrier Source PIC16(L)F1778 Carrier Source PIC16(L)F1777/9 11111 Reserved Reserved 11110 Reserved Reserved 11101 Reserved Reserved 11100 Reserved Reserved 11011 Reserved Reserved 11010 Reserved Reserved 11001 Reserved Reserved 11000 Reserved Reserved 10111 Reserved Reserved 10110 Reserved Reserved 10101 Reserved Reserved 10100 Reserved Reserved 10011 Reserved Reserved 10010 LC4_out LC4_out 10001 LC3_out LC3_out 10000 LC2_out LC2_out 01111 LC1_out LC1_out 01110 Reserved PWM12_out 01101 PWM11_out PWM11_out 01100 PWM6_out PWM6_out 01011 PWM5_out PWM5_out 01010 Reserved PWM10_out 01001 PWM9_out PWM9_out 01000 PWM4_out PWM4_out 00111 PWM3_out PWM3_out 00110 Reserved CCP8_out 00101 CCP7_out CCP7_out 00100 CCP2_out CCP2_out 00011 CCP1_out CCP1_out 00010 HFINTOSC HFINTOSC 00001 FOSC FOSC 00000 MDxMODPPS pin selection MDxMODPPS pin selection 2015-2016 Microchip Technology Inc. DS40001819B-page 437 PIC16(L)F1777/8/9 REGISTER 31-5: MDxCARL: MODULATION LOW CARRIER CONTROL REGISTER U-0 U-0 U-0 -- -- -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u CL<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-5 Unimplemented: Read as `0' bit 4-0 CL<4:0> Modulator Data Low Carrier Selection bits(1) See Table 31-7. Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. DS40001819B-page 438 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 31-7: LOW CARRIER SOURCE CH<4:0> Carrier Source PIC16(L)F1778 Carrier Source PIC16(L)F1777/9 11111 Reserved Reserved 11110 Reserved Reserved 11101 Reserved Reserved 11100 Reserved Reserved 11011 Reserved Reserved 11010 Reserved Reserved 11001 Reserved Reserved 11000 Reserved Reserved 10111 Reserved Reserved 10110 Reserved Reserved 10101 Reserved Reserved 10100 Reserved Reserved 10011 Reserved Reserved 10010 LC4_out LC4_out 10001 LC3_out LC3_out 10000 LC2_out LC2_out 01111 LC1_out LC1_out 01110 Reserved PWM12_out 01101 PWM11_out PWM11_out 01100 PWM6_out PWM6_out 01011 PWM5_out PWM5_out 01010 Reserved PWM10_out 01001 PWM9_out PWM9_out 01000 PWM4_out PWM4_out 00111 PWM3_out PWM3_out 00110 Reserved CCP8_out 00101 CCP7_out CCP7_out 00100 CCP2_out CCP2_out 00011 CCP1_out CCP1_out 00010 HFINTOSC HFINTOSC 00001 FOSC FOSC 00000 MDxMODPPS pin selection MDxMODPPS pin selection TABLE 31-8: Name SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MODE(1) Bit 6 Bit 5 MDxCARH -- -- -- MDxCARL -- -- MDxSRC -- -- MDxCON0 EN -- OUT OPOL -- -- -- BIT 433 MDxCON1 -- -- CHPOL CHSYNC -- -- CLPOL CLSYNC 433 Legend: Note 1: Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page Bit 7 CH<4:0> 436 -- CL<4:0> 438 -- MS<4:0> 434 -- = unimplemented, read as `0'. Shaded cells are not used in the Data Signal Modulator mode. DSM4 available on PIC16LF1777/9 only. 2015-2016 Microchip Technology Inc. DS40001819B-page 439 PIC16(L)F1777/8/9 32.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE 32.1 MSSP Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2C) The SPI interface supports the following modes and features: * * * * * Master mode Slave mode Clock Parity Slave Select Synchronization (Slave mode only) Daisy-chain connection of slave devices Figure 32-1 is a block diagram of the SPI interface module. FIGURE 32-1: MSSP BLOCK DIAGRAM (SPI MODE) Data Bus Read Write SSPxBUF Reg SSPDATPPS SDI PPS SSPSR Reg Shift Clock bit 0 SDO PPS RxyPPS SS SS Control Enable PPS SSPSSPPS Edge Select SSPCLKPPS(2) SCK SSPM<3:0> 4 PPS PPS TRIS bit 2 (CKP, CKE) Clock Select RxyPPS(1) Edge Select ( T2_match 2 ) Prescaler TOSC 4, 16, 64 Baud Rate Generator (SSPxADD) Note 1: Output selection for master mode 2: Input selection for slave mode DS40001819B-page 440 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 The I2C interface supports the following modes and features: * * * * * * * * * * * * * Master mode Slave mode Byte NACKing (Slave mode) Limited multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDA hold times Figure 32-2 is a block diagram of the I2C interface module in Master mode. Figure 32-3 is a diagram of the I2C interface module in Slave mode. MSSP BLOCK DIAGRAM (I2C MASTER MODE) Internal data bus SSPDATPPS(1) SDA in PPS [SSPM<3:0>] Write SSPxBUF Baud Rate Generator (SSPxADD) Shift Clock RxyPPS(1) SSPCLKPPS(2) SCL PPS Receive Enable (RCEN) MSb LSb Start bit, Stop bit, Acknowledge Generate (SSPxCON2) Clock Cntl SSPSR PPS (Hold off clock source) SDA Read Clock arbitrate/BCOL detect FIGURE 32-2: PPS RxyPPS(2) SCL in Bus Collision Start bit detect, Stop bit detect Write collision detect Clock arbitration State counter for end of XMIT/RCV Address Match detect Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV Reset SEN, PEN (SSPxCON2) Set SSP1IF, BCL1IF Note 1: SDA pin selections must be the same for input and output 2: SCL pin selections must be the same for input and output 2015-2016 Microchip Technology Inc. DS40001819B-page 441 PIC16(L)F1777/8/9 MSSP BLOCK DIAGRAM (I2C SLAVE MODE) FIGURE 32-3: Internal Data Bus Read Write SSPCLKPPS(2) SCL PPS PPS SSPxBUF Reg Shift Clock Clock Stretching SSPSR Reg LSb MSb RxyPPS(2) SSPxMSK Reg (1) SSPDATPPS SDA Match Detect Addr Match PPS SSPxADD Reg PPS RxyPPS(1) Start and Stop bit Detect Set, Reset S, P bits (SSPxSTAT Reg) Note 1: SDA pin selections must be the same for input and output 2: SCL pin selections must be the same for input and output DS40001819B-page 442 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 32.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full-Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a Chip Select known as Slave Select. The SPI bus specifies four signal connections: * * * * Serial Clock (SCK) Serial Data Out (SDO) Serial Data In (SDI) Slave Select (SS) Figure 32-1 shows the block diagram of the MSSP module when operating in SPI mode. The SPI bus operates with a single master device and one or more slave devices. When multiple slave devices are used, an independent Slave Select connection is required from the master device to each slave device. Figure 32-4 shows a typical connection between a master device and multiple slave devices. The master selects only one slave at a time. Most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. Transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. With either the master or the slave device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. During each SPI clock cycle, a full-duplex data transmission occurs. This means that while the master device is sending out the MSb from its shift register (on its SDO pin) and the slave device is reading this bit and saving it as the LSb of its shift register, that the slave device is also sending out the MSb from its shift register (on its SDO pin) and the master device is reading this bit and saving it as the LSb of its shift register. After eight bits have been shifted out, the master and slave have exchanged register values. If there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. Whether the data is meaningful or not (dummy data), depends on the application software. This leads to three scenarios for data transmission: * Master sends useful data and slave sends dummy data. * Master sends useful data and slave sends useful data. * Master sends dummy data and slave sends useful data. Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master stops sending the clock signal and it deselects the slave. Every slave device connected to the bus that has not been selected through its slave select line must disregard the clock and transmission signals and must not transmit out any data of its own. Figure 32-5 shows a typical connection between two processors configured as master and slave devices. Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. The master device transmits information out on its SDO output pin which is connected to, and received by, the slave's SDI input pin. The slave device transmits information out on its SDO output pin, which is connected to, and received by, the master's SDI input pin. To begin communication, the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polarity. The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register. 2015-2016 Microchip Technology Inc. DS40001819B-page 443 PIC16(L)F1777/8/9 FIGURE 32-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SPI Master SCK SCK SDO SDI SDI SDO General I/O General I/O SS General I/O SCK SDI SDO SPI Slave #1 SPI Slave #2 SS SCK SDI SDO SPI Slave #3 SS 32.2.1 SPI MODE REGISTERS 32.2.2 The MSSP module has five registers for SPI mode operation. These are: * * * * * * MSSP STATUS register (SSPxSTAT) MSSP Control register 1 (SSPxCON1) MSSP Control register 3 (SSPxCON3) MSSP Data Buffer register (SSPxBUF) MSSP Address register (SSPxADD) MSSP Shift register (SSPSR) (Not directly accessible) SSPxCON1 and SSPxSTAT are the control STATUS registers in SPI mode operation. SSPxCON1 register is readable and writable. lower six bits of the SSPxSTAT are read-only. upper two bits of the SSPxSTAT are read/write. SPI MODE OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). These control bits allow the following to be specified: * * * * and The The The In one SPI Master mode, SSPxADD can be loaded with a value used in the Baud Rate Generator. More information on the Baud Rate Generator is available in Section 32.7 "Baud Rate Generator". SSPSR is the shift register used for shifting data in and out. SSPxBUF provides indirect access to the SSPSR register. SSPxBUF is the buffer register to which data bytes are written, and from which data bytes are read. In receive operations, SSPSR and SSPxBUF together create a buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. During transmission, the SSPxBUF is not buffered. A write to SSPxBUF will write to both SSPxBUF and SSPSR. Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Data Input Sample Phase (middle or end of data output time) * Clock Edge (output data on rising/falling edge of SCK) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only) To enable the serial port, SSP Enable bit, SSPEN of the SSPxCON1 register, must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPxCONx registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: * SDI must have corresponding TRIS bit set * SDO must have corresponding TRIS bit cleared * SCK (Master mode) must have corresponding TRIS bit cleared * SCK (Slave mode) must have corresponding TRIS bit set * SS must have corresponding TRIS bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. DS40001819B-page 444 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 The MSSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPxBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPxBUF holds the data that was written to the SSPSR until the received data is ready. Once the eight bits of data have been received, that byte is moved to the SSPxBUF register. Then, the Buffer Full Detect bit, BF of the SSPxSTAT register, and the interrupt flag bit, SSPxIF, are set. This double-buffering of the received data (SSPxBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPxBUF register during transmission/reception of data will be ignored and the Write Collision Detect bit WCOL of the SSPxCON1 register, will be set. User software must clear the WCOL bit to allow the following write(s) to the SSPxBUF register to complete successfully. FIGURE 32-5: When the application software is expecting to receive valid data, the SSPxBUF should be read before the next byte of data to transfer is written to the SSPxBUF. The Buffer Full bit, BF of the SSPxSTAT register, indicates when SSPxBUF has been loaded with the received data (transmission is complete). When the SSPxBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPxBUF register. Additionally, the SSPxSTAT register indicates the various Status conditions. SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xx = 1010 SPI Slave SSPM<3:0> = 010x SDO SDI Serial Input Buffer (BUF) SDI Shift Register (SSPSR) MSb Serial Input Buffer (SSPxBUF) LSb SCK General I/O Processor 1 2015-2016 Microchip Technology Inc. SDO Serial Clock Slave Select (optional) Shift Register (SSPSR) MSb LSb SCK SS Processor 2 DS40001819B-page 445 PIC16(L)F1777/8/9 32.2.3 SPI MASTER MODE The master can initiate the data transfer at any time because it controls the SCK line. The master determines when the slave (Processor 2, Figure 32-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPxBUF register as if a normal received byte (interrupts and Status bits appropriately set). The clock polarity is selected by appropriately programming the CKP bit of the SSPxCON1 register and the CKE bit of the SSPxSTAT register. This then, would give waveforms for SPI communication as shown in Figure 32-6, Figure 32-8, Figure 32-9 and Figure 32-10, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: * * * * * FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 FOSC/(4 * (SSPxADD + 1)) Figure 32-6 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown. Note: DS40001819B-page 446 In Master mode the clock signal output to the SCK pin is also the clock signal input to the peripheral. The pin selected for output with the RxyPPS register must also be selected as the peripheral input with the SSPCLKPPS register. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 32-6: SPI MODE WAVEFORM (MASTER MODE) Write to SSPxBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDO (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDI (SMP = 1) bit 0 bit 7 Input Sample (SMP = 1) SSPxIF SSPSR to SSPxBUF 32.2.4 SPI SLAVE MODE In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSPxIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit of the SSPxCON1 register. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. The shift register is clocked from the SCK pin input and when a byte is received, the device will generate an interrupt. If enabled, the device will wake-up from Sleep. 2015-2016 Microchip Technology Inc. 32.2.4.1 Daisy-Chain Configuration The SPI bus can sometimes be connected in a daisy-chain configuration. The first slave output is connected to the second slave input, the second slave output is connected to the third slave input, and so on. The final slave output is connected to the master input. Each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. The whole chain acts as one large communication shift register. The daisy-chain feature only requires a single Slave Select line from the master device. Figure 32-7 shows the block diagram of a typical daisy-chain connection when operating in SPI mode. In a daisy-chain configuration, only the most recent byte on the bus is required by the slave. Setting the BOEN bit of the SSPxCON3 register will enable writes to the SSPxBUF register, even if the previous byte has not been read. This allows the software to ignore data that may not apply to it. DS40001819B-page 447 PIC16(L)F1777/8/9 32.2.5 SLAVE SELECT SYNCHRONIZATION When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. The Slave Select can also be used to synchronize communication. The Slave Select line is held high until the master device is ready to communicate. When the Slave Select line is pulled low, the slave knows that a new transmission is starting. If the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the Slave Select line returns to a high state. The slave is then ready to receive a new transmission when the Slave Select line is pulled low again. If the Slave Select line is not used, there is a risk that the slave will eventually become out of sync with the master. If the slave misses a bit, it will always be one bit off in future transmissions. Use of the Slave Select line allows the slave and master to align themselves at the beginning of each transmission. The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPxCON1<3:0> = 0100). FIGURE 32-7: When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPxCON1<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. 2: When the SPI is used in Slave mode with CKE set; the user must enable SS pin control. 3: While operated in SPI Slave mode the SMP bit of the SSPxSTAT register must remain clear. When the SPI module resets, the bit counter is forced to `0'. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. SPI DAISY-CHAIN CONNECTION SPI Master SCK SCK SDO SDI SDI General I/O SDO SPI Slave #1 SS SCK SDI SDO SPI Slave #2 SS SCK SDI SDO SPI Slave #3 SS DS40001819B-page 448 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 32-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPxBUF Shift register SSPSR and bit count are reset SSPxBUF to SSPSR SDO bit 7 bit 6 bit 7 SDI bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPxIF Interrupt Flag SSPSR to SSPxBUF 2015-2016 Microchip Technology Inc. DS40001819B-page 449 PIC16(L)F1777/8/9 FIGURE 32-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPxBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSPxIF Interrupt Flag SSPSR to SSPxBUF Write Collision detection active FIGURE 32-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPxBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 7 bit 0 Input Sample SSPxIF Interrupt Flag SSPSR to SSPxBUF Write Collision detection active DS40001819B-page 450 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 32.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSP clock is much faster than the system clock. In Slave mode, when MSSP interrupts are enabled, after the master completes sending data, an MSSP interrupt will wake the controller from Sleep. If an exit from Sleep mode is not desired, MSSP interrupts should be disabled. TABLE 32-1: Name In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all eight bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA -- -- ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 -- -- 187 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139 RxyPPS -- -- RxyPPS<5:0> 205 SSPCLKPPS -- -- SSPCLKPPS<5:0> 205, 207 SSPDATPPS -- -- SSPDATPPS<5:0> 205, 207 SSPSSPPS -- -- SSPSSPPS<5:0> 205, 207 SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 444* SSP1CON1 WCOL SSPOV SSPEN CKP SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 488 SSP1STAT SMP CKE D/A P S R/W UA BF 488 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186 TRISC Legend: * SSPM<3:0> 489 -- = Unimplemented location, read as `0'. Shaded cells are not used by the MSSP in SPI mode. Page provides register information. 2015-2016 Microchip Technology Inc. DS40001819B-page 451 PIC16(L)F1777/8/9 32.3 I2C MODE OVERVIEW The Inter-Integrated Circuit (I2C) bus is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A slave device is controlled through addressing. VDD SCL The I2C bus specifies two signal connections: * Serial Clock (SCL) * Serial Data (SDA) Figure 32-11 shows the block diagram of the MSSP module when operating in I2C mode. Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. Pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. Figure 32-11 shows a typical connection between two processors configured as master and slave devices. The I2C bus can operate with one or more master devices and one or more slave devices. There are four potential modes of operation for a given device: * Master Transmit mode (master is transmitting data to a slave) * Master Receive mode (master is receiving data from a slave) * Slave Transmit mode (slave is transmitting data to a master) * Slave Receive mode (slave is receiving data from the master) To begin communication, a master device starts out in Master Transmit mode. The master device sends out a Start bit followed by the address byte of the slave it intends to communicate with. This is followed by a single Read/Write bit, which determines whether the master intends to transmit to or receive data from the slave device. If the requested slave exists on the bus, it will respond with an Acknowledge bit, otherwise known as an ACK. The master then continues in either Transmit mode or Receive mode and the slave continues in the complement, either in Receive mode or Transmit mode, respectively. A Start bit is indicated by a high-to-low transition of the SDA line while the SCL line is held high. Address and data bytes are sent out, Most Significant bit (MSb) first. The Read/Write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave. DS40001819B-page 452 I2C MASTER/ SLAVE CONNECTION FIGURE 32-11: SCL VDD Master Slave SDA SDA The Acknowledge bit (ACK) is an active-low signal, which holds the SDA line low to indicate to the transmitter that the slave device has received the transmitted data and is ready to receive more. The transition of a data bit is always performed while the SCL line is held low. Transitions that occur while the SCL line is held high are used to indicate Start and Stop bits. If the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this example, the master device is in Master Transmit mode and the slave is in Slave Receive mode. If the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ACK bit. In this example, the master device is in Master Receive mode and the slave is Slave Transmit mode. On the last byte of data communicated, the master device may end the transmission by sending a Stop bit. If the master device is in Receive mode, it sends the Stop bit in place of the last ACK bit. A Stop bit is indicated by a low-to-high transition of the SDA line while the SCL line is held high. In some cases, the master may want to maintain control of the bus and re-initiate another transmission. If so, the master device may send another Start bit in place of the Stop bit or last ACK bit when it is in receive mode. The I2C bus specifies three message protocols: * Single message where a master writes data to a slave. * Single message where a master reads data from a slave. * Combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCL line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDA line, it is called arbitration. Arbitration ensures that there is only one master device communicating at any single time. 32.3.1 CLOCK STRETCHING When a slave device has not completed processing data, it can delay the transfer of more data through the process of clock stretching. An addressed slave device may hold the SCL clock line low after receiving or sending a bit, indicating that it is not yet ready to continue. The master that is communicating with the slave will attempt to raise the SCL line in order to transfer the next bit, but will detect that the clock line has not yet been released. Because the SCL connection is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. 32.3.2 ARBITRATION Each master device must monitor the bus for Start and Stop bits. If the device detects that the bus is busy, it cannot begin a new message until the bus returns to an Idle state. However, two master devices may try to initiate a transmission on or about the same time. When this occurs, the process of arbitration begins. Each transmitter checks the level of the SDA data line and compares it to the level that it expects to find. The first transmitter to observe that the two levels do not match, loses arbitration, and must stop transmitting on the SDA line. For example, if one transmitter holds the SDA line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the SDA line will be low. The first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. The first transmitter to notice this difference is the one that loses arbitration and must stop driving the SDA line. If this transmitter is also a master device, it also must stop driving the SCL line. It then can monitor the lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDA line continues with its original transmission. It can do so without any complications, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. If two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitration. When two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support. 2015-2016 Microchip Technology Inc. DS40001819B-page 453 PIC16(L)F1777/8/9 32.4 I2C MODE OPERATION All MSSP I2C communication is byte oriented and shifted out MSb first. Six SFR registers and two interrupt flags interface the module with the PIC(R) microcontroller and user software. Two pins, SDA and SCL, are exercised by the module to communicate with other external I2C devices. 32.4.1 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a master to a slave or vice-versa, followed by an Acknowledge bit sent back. After the eighth falling edge of the SCL line, the device outputting data on the SDA changes that pin to an input and reads in an acknowledge value on the next clock pulse. The clock signal, SCL, is provided by the master. Data is valid to change while the SCL signal is low, and sampled on the rising edge of the clock. Changes on the SDA line while the SCL line is high define special conditions on the bus, explained below. 32.4.2 DEFINITION OF I2C TERMINOLOGY There is language and terminology in the description of I2C communication that have definitions specific to I2C. That word usage is defined below and may be used in the rest of this document without explanation. This table was adapted from the Philips I2C specification. 32.4.3 SDA AND SCL PINS Selection of any I2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open-drain. These pins should be set by the user to inputs by setting the appropriate TRIS bits. Note 1: Data is tied to output zero when an I2C mode is enabled. 2: Any device pin can be selected for SDA and SCL functions with the PPS peripheral. These functions are bidirectional. The SDA input is selected with the SSPDATPPS registers. The SCL input is selected with the SSPCLKPPS registers. Outputs are selected with the RxyPPS registers. It is the user's responsibility to make the selections so that both the input and the output for each function is on the same pin. 32.4.4 TABLE 32-2: TERM I2C BUS TERMS Description Transmitter The device which shifts data out onto the bus. Receiver The device which shifts data in from the bus. Master The device that initiates a transfer, generates clock signals and terminates a transfer. Slave The device addressed by the master. Multi-master A bus with more than one device that can initiate data transfers. Arbitration Procedure to ensure that only one master at a time controls the bus. Winning arbitration ensures that the message is not corrupted. Synchronization Procedure to synchronize the clocks of two or more devices on the bus. Idle No master is controlling the bus, and both SDA and SCL lines are high. Active Any time one or more master devices are controlling the bus. Slave device that has received a Addressed Slave matching address and is actively being clocked by a master. Matching Address byte that is clocked into a Address slave that matches the value stored in SSPxADD. Write Request Slave receives a matching address with R/W bit clear, and is ready to clock in data. Read Request Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of the Slave. This data is the next and all following bytes until a Restart or Stop. Clock Stretching When a device on the bus hold SCL low to stall communication. Bus Collision Any time the SDA line is sampled low by the module while it is outputting and expected high state. SDA HOLD TIME The hold time of the SDA pin is selected by the SDAHT bit of the SSPxCON3 register. Hold time is the time SDA is held valid after the falling edge of SCL. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. DS40001819B-page 454 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 32.4.5 START CONDITION 32.4.7 2 The I C specification defines a Start condition as a transition of SDA from a high to a low state while SCL line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 32-12 shows wave forms for Start and Stop conditions. A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart has the same effect on the slave that a Start would, resetting all slave logic and preparing it to clock in an address. The master may want to address the same or another slave. Figure 32-13 shows the wave form for a Restart condition. A bus collision can occur on a Start condition if the module samples the SDA line low before asserting it low. This does not conform to the I2C Specification that states no bus collision can occur on a Start. 32.4.6 RESTART CONDITION In 10-bit Addressing Slave mode a Restart is required for the master to clock data out of the addressed slave. Once a slave has been fully addressed, matching both high and low address bytes, the master can issue a Restart and the high address byte with the R/W bit set. The slave logic will then hold the clock and prepare to clock out data. STOP CONDITION A Stop condition is a transition of the SDA line from low-to-high state while the SCL line is high. Note: At least one SCL low time must appear before a Stop is valid, therefore, if the SDA line goes low then high again while the SCL line stays high, only the Start condition is detected. After a full match with R/W clear in 10-bit mode, a prior match flag is set and maintained until a Stop condition, a high address with R/W clear, or high address match fails. 32.4.8 START/STOP CONDITION INTERRUPT MASKING The SCIE and PCIE bits of the SSPxCON3 register can enable the generation of an interrupt in Slave modes that do not typically support this function. Slave modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect. FIGURE 32-12: I2C START AND STOP CONDITIONS SDA SCL S Start P Change of Change of Data Allowed Data Allowed Condition FIGURE 32-13: Stop Condition I2C RESTART CONDITION Sr Change of Change of Data Allowed Restart Data Allowed Condition 2015-2016 Microchip Technology Inc. DS40001819B-page 455 PIC16(L)F1777/8/9 32.4.9 ACKNOWLEDGE SEQUENCE The ninth SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA line low indicates to the transmitter that the device has received the transmitted data and is ready to receive more. The result of an ACK is placed in the ACKSTAT bit of the SSPxCON2 register. Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to the transmitter. The ACKDT bit of the SSPxCON2 register is set/cleared to determine the response. Slave hardware will generate an ACK response if the AHEN and DHEN bits of the SSPxCON3 register are clear. There are certain conditions where an ACK will not be sent by the slave. If the BF bit of the SSPxSTAT register or the SSPOV bit of the SSPxCON1 register are set when a byte is received. When the module is addressed, after the eighth falling edge of SCL on the bus, the ACKTIM bit of the SSPxCON3 register is set. The ACKTIM bit indicates the acknowledge time of the active bus. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is enabled. 32.5 I2C SLAVE MODE OPERATION The MSSP Slave mode operates in one of four modes selected by the SSPM bits of SSPxCON1 register. The modes can be divided into 7-bit and 10-bit Addressing mode. 10-bit Addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. Modes with Start and Stop bit interrupts operate the same as the other modes with SSPxIF additionally getting set upon detection of a Start, Restart, or Stop condition. 32.5.1 SLAVE MODE ADDRESSES The SSPxADD register (Register 32-6) contains the Slave mode address. The first byte received after a Start or Restart condition is compared against the value stored in this register. If the byte matches, the value is loaded into the SSPxBUF register and an interrupt is generated. If the value does not match, the module goes idle and no indication is given to the software that anything happened. The SSP Mask register (Register 32-5) affects the address matching process. See Section 32.5.8 "SSP Mask Register" for more information. 32.5.1.1 I2C Slave 7-bit Addressing Mode In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an address match. 32.5.1.2 I2C Slave 10-bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of `1 1 1 1 0 A9 A8 0'. A9 and A8 are the two MSb's of the 10-bit address and stored in bits 2 and 1 of the SSPxADD register. After the acknowledge of the high byte the UA bit is set and SCL is held low until the user updates SSPxADD with the low address. The low address byte is clocked in and all eight bits are compared to the low address value in SSPxADD. Even if there is not an address match; SSPxIF and UA are set, and SCL is held low until SSPxADD is updated to receive a high byte again. When SSPxADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match. DS40001819B-page 456 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 32.5.2 SLAVE RECEPTION When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF of the SSPxSTAT register is set, or bit SSPOV of the SSPxCON1 register is set. The BOEN bit of the SSPxCON3 register modifies this operation. For more information see Register 32-4. An MSSP interrupt is generated for each transferred data byte. Flag bit, SSPxIF, must be cleared by software. When the SEN bit of the SSPxCON2 register is set, SCL will be held low (clock stretch) following each received byte. The clock must be released by setting the CKP bit of the SSPxCON1 register, except sometimes in 10-bit mode. See Section 32.5.6.2 "10-bit Addressing Mode" for more detail. 32.5.2.1 7-bit Addressing Reception This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 7-bit Addressing mode. Figure 32-14 and Figure 32-15 is used as a visual reference for this description. This is a step by step process of what typically must be done to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Start bit detected. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. Matching address with R/W bit clear is received. The slave pulls SDA low sending an ACK to the master, and sets SSPxIF bit. Software clears the SSPxIF bit. Software reads received address from SSPxBUF clearing the BF flag. If SEN = 1; Slave software sets CKP bit to release the SCL line. The master clocks out a data byte. Slave drives SDA low sending an ACK to the master, and sets SSPxIF bit. Software clears SSPxIF. Software reads the received byte from SSPxBUF clearing BF. Steps 8-12 are repeated for all received bytes from the master. Master sends Stop condition, setting P bit of SSPxSTAT, and the bus goes idle. 2015-2016 Microchip Technology Inc. 32.5.2.2 7-bit Reception with AHEN and DHEN Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the eighth falling edge of SCL. These additional interrupts allow the slave software to decide whether it wants to ACK the receive address or data byte, rather than the hardware. This functionality adds support for PMBusTM that was not present on previous versions of this module. This list describes the steps that need to be taken by slave software to use these options for I2C communication. Figure 32-16 displays a module using both address and data holding. Figure 32-17 includes the operation with the SEN bit of the SSPxCON2 register set. 1. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 2. Matching address with R/W bit clear is clocked in. SSPxIF is set and CKP cleared after the eighth falling edge of SCL. 3. Slave clears the SSPxIF. 4. Slave can look at the ACKTIM bit of the SSPxCON3 register to determine if the SSPxIF was after or before the ACK. 5. Slave reads the address value from SSPxBUF, clearing the BF flag. 6. Slave sets ACK value clocked out to the master by setting ACKDT. 7. Slave releases the clock by setting CKP. 8. SSPxIF is set after an ACK, not after a NACK. 9. If SEN = 1 the slave hardware will stretch the clock after the ACK. 10. Slave clears SSPxIF. Note: SSPxIF is still set after the ninth falling edge of SCL even if there is no clock stretching and BF has been cleared. Only if NACK is sent to master is SSPxIF not set 11. SSPxIF set and CKP cleared after eighth falling edge of SCL for a received data byte. 12. Slave looks at ACKTIM bit of SSPxCON3 to determine the source of the interrupt. 13. Slave reads the received data from SSPxBUF clearing BF. 14. Steps 7-14 are the same for each received data byte. 15. Communication is ended by either the slave sending an ACK = 1, or the master sending a Stop condition. If a Stop is sent and interrupt on Stop detect is disabled, the slave will only know by polling the P bit of the SSTSTAT register. DS40001819B-page 457 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0) Bus Master sends Stop condition From Slave to Master Receiving Address SDA SCL S Receiving Data A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 ACK 8 9 Receiving Data D7 D6 D5 D4 D3 D2 D1 1 2 3 4 5 6 7 D0 ACK D7 8 9 1 ACK = 1 D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 P SSPxIF Cleared by software Cleared by software BF SSPxBUF is read First byte of data is available in SSPxBUF SSPOV SSPOV set because SSPxBUF is still full. ACK is not sent. SSPxIF set on 9th falling edge of SCL PIC16(L)F1777/8/9 DS40001819B-page 458 FIGURE 32-14: 2015-2016 Microchip Technology Inc. 2015-2016 Microchip Technology Inc. I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 32-15: Bus Master sends Stop condition Receive Address SDA SCL S Receive Data A7 A6 A5 A4 A3 A2 1 2 3 4 5 6 A1 R/W=0 ACK 7 8 9 SEN Receive Data D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 9 SEN ACK D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 P Clock is held low until CKP is set to `1' SSPxIF Cleared by software BF SSPxBUF is read Cleared by software SSPxIF set on 9th falling edge of SCL First byte of data is available in SSPxBUF SSPOV CKP CKP is written to `1' in software, releasing SCL CKP is written to `1' in software, releasing SCL SCL is not held low because ACK= 1 DS40001819B-page 459 PIC16(L)F1777/8/9 SSPOV set because SSPxBUF is still full. ACK is not sent. I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1) Master sends Stop condition Master Releases SDA to slave for ACK sequence Receiving Address SDA Receiving Data ACK D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 Received Data ACK ACK=1 D7 D6 D5 D4 D3 D2 D1 D0 SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P SSPxIF If AHEN = 1: SSPxIF is set BF ACKDT CKP SSPxIF is set on 9th falling edge of SCL, after ACK Address is read from SSBUF Data is read from SSPxBUF Slave software clears ACKDT to ACK the received byte When AHEN=1: CKP is cleared by hardware and SCL is stretched No interrupt after not ACK from Slave Cleared by software Slave software sets ACKDT to not ACK When DHEN=1: CKP is cleared by hardware on 8th falling edge of SCL CKP set by software, SCL is released ACKTIM 2015-2016 Microchip Technology Inc. ACKTIM set by hardware on 8th falling edge of SCL S P ACKTIM cleared by hardware in 9th rising edge of SCL ACKTIM set by hardware on 8th falling edge of SCL PIC16(L)F1777/8/9 DS40001819B-page 460 FIGURE 32-16: 2015-2016 Microchip Technology Inc. I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1) FIGURE 32-17: R/W = 0 Receiving Address A7 A6 A5 A4 A3 A2 A1 SDA SCL S 1 2 3 4 5 6 7 Master sends Stop condition Master releases SDA to slave for ACK sequence ACK 8 9 Receive Data D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 ACK 9 Receive Data D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 ACK 9 P SSPxIF No interrupt after if not ACK from Slave Cleared by software BF Received address is loaded into SSPxBUF Received data is available on SSPxBUF ACKDT Slave software clears ACKDT to ACK the received byte SSPxBUF can be read any time before next byte is loaded Slave sends not ACK When AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared When DHEN = 1; on the 8th falling edge of SCL of a received data byte, CKP is cleared ACKTIM ACKTIM is set by hardware on 8th falling edge of SCL DS40001819B-page 461 S P ACKTIM is cleared by hardware on 9th rising edge of SCL Set by software, release SCL CKP is not cleared if not ACK PIC16(L)F1777/8/9 CKP PIC16(L)F1777/8/9 32.5.3 SLAVE TRANSMISSION 32.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPxSTAT register is set. The received address is loaded into the SSPxBUF register, and an ACK pulse is sent by the slave on the ninth bit. A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission. Figure 32-18 can be used as a reference to this list. Following the ACK, slave hardware clears the CKP bit and the SCL pin is held low (see Section 32.5.6 "Clock Stretching" for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. 1. The transmit data must be loaded into the SSPxBUF register which also loads the SSPSR register. Then the SCL pin should be released by setting the CKP bit of the SSPxCON1 register. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time. The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. This ACK value is copied to the ACKSTAT bit of the SSPxCON2 register. If ACKSTAT is set (not ACK), then the data transfer is complete. In this case, when the not ACK is latched by the slave, the slave goes idle and waits for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, the SCL pin must be released by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared by software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse. 32.5.3.1 Slave Mode Bus Collision A slave receives a Read request and begins shifting data out on the SDA line. If a bus collision is detected and the SBCDE bit of the SSPxCON3 register is set, the BCLIF bit of the PIR register is set. Once a bus collision is detected, the slave goes idle and waits to be addressed again. User software can use the BCLIF bit to handle a slave bus collision. DS40001819B-page 462 Master sends a Start condition on SDA and SCL. 2. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 3. Matching address with R/W bit set is received by the Slave setting SSPxIF bit. 4. Slave hardware generates an ACK and sets SSPxIF. 5. SSPxIF bit is cleared by user. 6. Software reads the received address from SSPxBUF, clearing BF. 7. R/W is set so CKP was automatically cleared after the ACK. 8. The slave software loads the transmit data into SSPxBUF. 9. CKP bit is set releasing SCL, allowing the master to clock the data out of the slave. 10. SSPxIF is set after the ACK response from the master is loaded into the ACKSTAT register. 11. SSPxIF bit is cleared. 12. The slave software checks the ACKSTAT bit to see if the master wants to clock out more data. Note 1: If the master ACKs the clock will be stretched. 2: ACKSTAT is the only bit updated on the rising edge of SCL (9th) rather than the falling. 13. Steps 9-13 are repeated for each transmitted byte. 14. If the master sends a not ACK; the clock is not held, but SSPxIF is still set. 15. The master sends a Restart condition or a Stop. 16. The slave is no longer addressed. 2015-2016 Microchip Technology Inc. 2015-2016 Microchip Technology Inc. FIGURE 32-18: I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0) Master sends Stop condition Receiving Address SDA SCL S R/W = 1 Automatic ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 8 1 1 2 3 4 5 6 7 9 Transmitting Data 2 3 4 5 6 Automatic ACK A7 A6 A5 A4 A3 A2 A1 7 8 9 Transmitting Data 2 3 4 5 6 7 8 9 P SSPxIF Cleared by software BF Received address is read from SSPxBUF Data to transmit is loaded into SSPxBUF BF is automatically cleared after 8th falling edge of SCL CKP When R/W is set SCL is always held low after 9th SCL falling edge Set by software CKP is not held for not ACK ACKSTAT R/W R/W is copied from the matching address byte D/A Indicates an address has been received DS40001819B-page 463 S P PIC16(L)F1777/8/9 Masters not ACK is copied to ACKSTAT PIC16(L)F1777/8/9 32.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPxCON3 register enables additional clock stretching and interrupt generation after the eighth falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPxIF interrupt is set. Figure 32-19 displays a standard waveform of a 7-bit address slave transmission with AHEN enabled. 1. 2. Bus starts Idle. Master sends Start condition; the S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 3. Master sends matching address with R/W bit set. After the eighth falling edge of the SCL line the CKP bit is cleared and SSPxIF interrupt is generated. 4. Slave software clears SSPxIF. 5. Slave software reads ACKTIM bit of the SSPxCON3 register, and R/W and D/A of the SSPxSTAT register to determine the source of the interrupt. 6. Slave reads the address value from the SSPxBUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets the ACKDT bit of the SSPxCON2 register accordingly. 8. Slave sets the CKP bit releasing SCL. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSPxIF after the ACK if the R/W bit is set. 11. Slave software clears SSPxIF. 12. Slave loads value to transmit to the master into SSPxBUF setting the BF bit. Note: SSPxBUF cannot be loaded until after the ACK. 13. Slave sets the CKP bit releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the ninth SCL pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit of the SSPxCON2 register. 16. Steps 10-15 are repeated for each byte transmitted to the master from the slave. 17. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCL line to receive a Stop. DS40001819B-page 464 2015-2016 Microchip Technology Inc. 2015-2016 Microchip Technology Inc. I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1) FIGURE 32-19: Master sends Stop condition Master releases SDA to slave for ACK sequence Receiving Address SDA SCL S 1 2 3 4 5 6 Automatic R/W = 1 ACK A7 A6 A5 A4 A3 A2 A1 7 8 9 Transmitting Data Automatic D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 1 2 3 4 5 6 7 8 9 Transmitting Data 2 3 4 5 6 7 ACK 8 9 P SSPxIF Cleared by software BF Received address is read from SSPxBUF Data to transmit is loaded into SSPxBUF BF is automatically cleared after 8th falling edge of SCL ACKDT Slave clears ACKDT to ACK address ACKSTAT Master's ACK response is copied to SSPxSTAT When AHEN = 1; CKP is cleared by hardware after receiving matching address. ACKTIM DS40001819B-page 465 R/W D/A ACKTIM is set on 8th falling edge of SCL When R/W = 1; CKP is always cleared after ACK Set by software, releases SCL ACKTIM is cleared on 9th rising edge of SCL CKP not cleared after not ACK PIC16(L)F1777/8/9 CKP PIC16(L)F1777/8/9 32.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 10-bit Addressing mode. Figure 32-20 is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle. Master sends Start condition; S bit of SSPxSTAT is set; SSPxIF is set if Interrupt on Start detect is enabled. Master sends matching high address with R/W bit clear; UA bit of the SSPxSTAT register is set. Slave sends ACK and SSPxIF is set. Software clears the SSPxIF bit. Software reads received address from SSPxBUF clearing the BF flag. Slave loads low address into SSPxADD, releasing SCL. Master sends matching low address byte to the slave; UA bit is set. 32.5.5 10-BIT ADDRESSING WITH ADDRESS OR DATA HOLD Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSPxADD register using the UA bit. All functionality, specifically when the CKP bit is cleared and SCL line is held low are the same. Figure 32-21 can be used as a reference of a slave in 10-bit addressing with AHEN set. Figure 32-22 shows a standard waveform for a slave transmitter in 10-bit Addressing mode. Note: Updates to the SSPxADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSPxIF is set. Note: If the low address does not match, SSPxIF and UA are still set so that the slave software can set SSPxADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSPxIF. 11. Slave reads the received matching address from SSPxBUF clearing BF. 12. Slave loads high address into SSPxADD. 13. Master clocks a data byte to the slave and clocks out the slaves ACK on the ninth SCL pulse; SSPxIF is set. 14. If SEN bit of SSPxCON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSPxIF. 16. Slave reads the received byte from SSPxBUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCL. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission. DS40001819B-page 466 2015-2016 Microchip Technology Inc. 2015-2016 Microchip Technology Inc. I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 32-20: Master sends Stop condition Receive Second Address Byte Receive First Address Byte SDA SCL S 1 1 1 1 0 A9 A8 1 2 3 4 5 6 7 ACK 8 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 2 3 4 5 6 7 8 Receive Data Receive Data 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 9 P SCL is held low while CKP = 0 SSPxIF Set by hardware on 9th falling edge Cleared by software BF Receive address is read from SSPxBUF If address matches SSPxADD it is loaded into SSPxBUF Data is read from SSPxBUF When UA = 1; SCL is held low Software updates SSPxADD and releases SCL CKP Set by software, When SEN = 1; releasing SCL CKP is cleared after 9th falling edge of received byte DS40001819B-page 467 PIC16(L)F1777/8/9 UA Receive First Address Byte SDA SCL S Receive Second Address Byte R/W = 0 1 1 1 1 0 A9 A8 1 2 3 4 5 6 7 ACK 8 9 UA Receive Data A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 2 3 4 5 6 7 8 9 UA Receive Data D7 D6 D5 D4 D3 D2 D1 1 2 3 4 5 6 7 D0 ACK D7 8 9 1 D6 D5 2 SSPxIF Set by hardware on 9th falling edge Cleared by software Cleared by software BF SSPxBUF can be read anytime before the next received byte Received data is read from SSPxBUF ACKDT Slave software clears ACKDT to ACK the received byte UA 2015-2016 Microchip Technology Inc. Update to SSPxADD is not allowed until 9th falling edge of SCL CKP If when AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared ACKTIM ACKTIM is set by hardware on 8th falling edge of SCL Update of SSPxADD, clears UA and releases SCL Set CKP with software releases SCL PIC16(L)F1777/8/9 DS40001819B-page 468 I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0) FIGURE 32-21: 2015-2016 Microchip Technology Inc. FIGURE 32-22: I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0) Master sends Restart event Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK SDA SCL S 1 2 3 4 5 6 7 8 9 Master sends not ACK Receiving Second Address Byte Receive First Address Byte A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 1 2 3 4 5 6 7 8 1 9 2 3 4 5 6 7 8 Transmitting Data Byte ACK 9 Master sends Stop condition ACK = 1 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 P Sr SSPxIF Set by hardware Cleared by software Set by hardware BF SSPxBUF loaded with received address Received address is read from SSPxBUF Data to transmit is loaded into SSPxBUF UA UA indicates SSPxADD must be updated CKP After SSPxADD is updated, UA is cleared and SCL is released High address is loaded back into SSPxADD Set by software releases SCL Masters not ACK is copied R/W R/W is copied from the matching address byte D/A DS40001819B-page 469 Indicates an address has been received PIC16(L)F1777/8/9 When R/W = 1; CKP is cleared on 9th falling edge of SCL ACKSTAT PIC16(L)F1777/8/9 32.5.6 CLOCK STRETCHING 32.5.6.2 Clock stretching occurs when a device on the bus holds the SCL line low, effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCL. The CKP bit of the SSPxCON1 register is used to control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. Setting CKP will release SCL and allow more communication. 32.5.6.1 Normal Clock Stretching Following an ACK if the R/W bit of SSPxSTAT is set, a read request, the slave hardware will clear CKP. This allows the slave time to update SSPxBUF with data to transfer to the master. If the SEN bit of SSPxCON2 is set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP is set by software and communication resumes. Note 1: The BF bit has no effect on if the clock will be stretched or not. This is different than previous versions of the module that would not stretch the clock, clear CKP, if SSPxBUF was read before the ninth falling edge of SCL. 2: Previous versions of the module did not stretch the clock for a transmission if SSPxBUF was loaded before the ninth falling edge of SCL. It is now always cleared for read requests. FIGURE 32-23: 10-bit Addressing Mode In 10-bit Addressing mode, when the UA bit is set the clock is always stretched. This is the only time the SCL is stretched without CKP being cleared. SCL is released immediately after a write to SSPxADD. Note: Previous versions of the module did not stretch the clock if the second address byte did not match. 32.5.6.3 Byte NACKing When AHEN bit of SSPxCON3 is set; CKP is cleared by hardware after the eighth falling edge of SCL for a received matching address byte. When DHEN bit of SSPxCON3 is set; CKP is cleared after the eighth falling edge of SCL for received data. Stretching after the eighth falling edge of SCL allows the slave to look at the received address or data and decide if it wants to ACK the received data. 32.5.6.4 Clock Synchronization and the CKP Bit Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 32-23). CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX - 1 DX SCL CKP Master device asserts clock Master device releases clock WR SSPxCON1 DS40001819B-page 470 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 32.5.7 GENERAL CALL ADDRESS SUPPORT If the AHEN bit of the SSPxCON3 register is set, just as with any other address reception, the slave hardware will stretch the clock after the eighth falling edge of SCL. The slave must then set its ACKDT value and release the clock with communication progressing as it would normally. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. 32.5.8 An SSP Mask (SSPxMSK) register (Register 32-5) is available in I2C Slave mode as a mask for the value held in the SSPSR register during an address comparison operation. A zero (`0') bit in the SSPxMSK register has the effect of making the corresponding bit of the received address a "don't care". The general call address is a reserved address in the I2C protocol, defined as address 0x00. When the GCEN bit of the SSPxCON2 register is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSPxADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave software can read SSPxBUF and respond. Figure 32-24 shows a general call reception sequence. This register is reset to all `1's upon any Reset condition and, therefore, has no effect on standard SSP operation until written with a mask value. The SSP Mask register is active during: * 7-bit Address mode: address compare of A<7:1>. In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. FIGURE 32-24: SSP MASK REGISTER 10-bit Address mode: address compare of A<7:0> only. The SSP mask has no effect during the reception of the first (high) byte of the address. SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 General Call Address SDA SCL S 1 2 3 4 5 6 7 8 9 1 Receiving Data ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 SSPxIF BF (SSPxSTAT<0>) Cleared by software GCEN (SSPxCON2<7>) SSPxBUF is read '1' 2015-2016 Microchip Technology Inc. DS40001819B-page 471 PIC16(L)F1777/8/9 32.6 I2C Master Mode 32.6.1 I2C MASTER MODE OPERATION Master mode is enabled by setting and clearing the appropriate SSPM bits in the SSPxCON1 register and by setting the SSPEN bit. In Master mode, the SDA and SCK pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary to drive the pins low. The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic `0'. Serial data is transmitted eight bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on Start and Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other communication is done by the user software directly manipulating the SDA and SCL lines. The following events will cause the SSP Interrupt Flag bit, SSPxIF, to be set (SSP interrupt, if enabled): * * * * Start condition detected Stop condition detected Data transfer byte transmitted/received Acknowledge transmitted/received * Repeated Start generated Note 1: The MSSP module, when configured in I2C Master mode, does not allow queuing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete. In this case, the SSPxBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPxBUF did not occur In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic `1'. Thus, the first byte transmitted is a 7-bit slave address followed by a `1' to indicate the receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received eight bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. A Baud Rate Generator is used to set the clock frequency output on SCL. See Section 32.7 "Baud Rate Generator" for more detail. 2: Master mode suspends Start/Stop detection when sending the Start/Stop condition by means of the SEN/PEN control bits. The SSPxIF bit is set at the end of the Start/Stop generation when hardware clears the control bit. DS40001819B-page 472 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 32.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 32-25). FIGURE 32-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX - 1 DX SCL deasserted but slave holds SCL low (clock arbitration) SCL allowed to transition high SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place and BRG starts its count BRG Reload 32.6.3 WCOL STATUS FLAG If the user writes the SSPxBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it indicates that an action on SSPxBUF was attempted while the module was not idle. Note: Because queuing of events is not allowed, writing to the lower five bits of SSPxCON2 is disabled until the Start condition is complete. 2015-2016 Microchip Technology Inc. DS40001819B-page 473 PIC16(L)F1777/8/9 32.6.4 I2C MASTER MODE START CONDITION TIMING by hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. To initiate a Start condition (Figure 32-26), the user sets the Start Enable bit, SEN bit of the SSPxCON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high is the Start condition and causes the S bit of the SSPxSTAT1 register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit of the SSPxCON2 register will be automatically cleared FIGURE 32-26: Note 1: If at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. 2: The Philips I2C specification states that a bus collision cannot occur on a Start. FIRST START BIT TIMING Write to SEN bit occurs here Set S bit (SSPxSTAT<3>) At completion of Start bit, hardware clears SEN bit and sets SSPxIF bit SDA = 1, SCL = 1 TBRG TBRG Write to SSPxBUF occurs here SDA 2nd bit 1st bit TBRG SCL S DS40001819B-page 474 TBRG 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 32.6.5 I2C MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. A Repeated Start condition (Figure 32-27) occurs when the RSEN bit of the SSPxCON2 register is programmed high and the master state machine is no longer active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG while SCL is high. SCL is asserted low. Following this, the RSEN bit of the SSPxCON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit of the SSPxSTAT register will be set. The SSPxIF bit will not be set until the Baud Rate Generator has timed out. FIGURE 32-27: 2: A bus collision during the Repeated Start condition occurs if: * SDA is sampled low when SCL goes from low-to-high. * SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data `1'. REPEATED START CONDITION WAVEFORM S bit set by hardware Write to SSPxCON2 occurs here SDA = 1, SCL (no change) At completion of Start bit, hardware clears RSEN bit and sets SSPxIF SDA = 1, SCL = 1 TBRG TBRG TBRG 1st bit SDA Write to SSPxBUF occurs here TBRG SCL Sr TBRG Repeated Start 2015-2016 Microchip Technology Inc. DS40001819B-page 475 PIC16(L)F1777/8/9 32.6.6 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted. SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCL is released high. When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKSTAT bit on the rising edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPxIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPxBUF, leaving SCL low and SDA unchanged (Figure 32-28). After the write to the SSPxBUF, each bit of the address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will release the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT Status bit of the SSPxCON2 register. Following the falling edge of the ninth clock transmission of the address, the SSPxIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPxBUF takes place, holding SCL low and allowing SDA to float. 32.6.6.1 BF Status Flag 32.6.6.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit of the SSPxCON2 register is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 32.6.6.4 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Typical Transmit Sequence: The user generates a Start condition by setting the SEN bit of the SSPxCON2 register. SSPxIF is set by hardware on completion of the Start. SSPxIF is cleared by software. The MSSP module will wait the required start time before any other operation takes place. The user loads the SSPxBUF with the slave address to transmit. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPxCON2 register. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. The user loads the SSPxBUF with eight bits of data. Data is shifted out the SDA pin until all eight bits are transmitted. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPxCON2 register. Steps 8-11 are repeated for all transmitted data bytes. The user generates a Stop or Restart condition by setting the PEN or RSEN bits of the SSPxCON2 register. Interrupt is generated once the Stop/Restart condition is complete. In Transmit mode, the BF bit of the SSPxSTAT register is set when the CPU writes to SSPxBUF and is cleared when all eight bits are shifted out. 32.6.6.2 WCOL Status Flag If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission. DS40001819B-page 476 2015-2016 Microchip Technology Inc. 2015-2016 Microchip Technology Inc. FIGURE 32-28: I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) Write SSPxCON2<0> SEN = 1 Start condition begins From slave, clear ACKSTAT bit SSPxCON2<6> SEN = 0 Transmit Address to Slave SDA A7 A6 A5 A4 ACKSTAT in SSPxCON2 = 1 A3 A2 Transmitting Data or Second Half of 10-bit Address R/W = 0 A1 ACK = 0 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 SCL held low while CPU responds to SSPxIF 2 3 4 5 6 7 8 SSPxBUF written with 7-bit address and R/W start transmit SCL S 1 2 3 4 5 6 7 8 9 9 P SSPxIF Cleared by software Cleared by software service routine from SSP interrupt Cleared by software BF (SSPxSTAT<0>) SSPxBUF written SSPxBUF is written by software SEN After Start condition, SEN cleared by hardware R/W DS40001819B-page 477 PIC16(L)F1777/8/9 PEN PIC16(L)F1777/8/9 32.6.7 I2C MASTER MODE RECEPTION Master mode reception (Figure 32-29) is enabled by programming the Receive Enable bit, RCEN bit of the SSPxCON2 register. Note: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/low-to-high) and data is shifted into the SSPSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPSR are loaded into the SSPxBUF, the BF flag bit is set, the SSPxIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCL low. The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable, ACKEN bit of the SSPxCON2 register. 32.6.7.1 BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPxBUF from SSPSR. It is cleared when the SSPxBUF register is read. 32.6.7.2 SSPOV Status Flag 32.6.7.4 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. In receive operation, the SSPOV bit is set when eight bits are received into the SSPSR and the BF flag bit is already set from a previous reception. 13. 14. 32.6.7.3 15. WCOL Status Flag If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). DS40001819B-page 478 Typical Receive Sequence: The user generates a Start condition by setting the SEN bit of the SSPxCON2 register. SSPxIF is set by hardware on completion of the Start. SSPxIF is cleared by software. User writes SSPxBUF with the slave address to transmit and the R/W bit set. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPxCON2 register. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. User sets the RCEN bit of the SSPxCON2 register and the master clocks in a byte from the slave. After the eighth falling edge of SCL, SSPxIF and BF are set. Master clears SSPxIF and reads the received byte from SSPxBUF, clears BF. Master sets ACK value sent to slave in ACKDT bit of the SSPxCON2 register and initiates the ACK by setting the ACKEN bit. Master's ACK is clocked out to the slave and SSPxIF is set. User clears SSPxIF. Steps 8-13 are repeated for each received byte from the slave. Master sends a not ACK or Stop to end communication. 2015-2016 Microchip Technology Inc. 2015-2016 Microchip Technology Inc. I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) FIGURE 32-29: Write to SSPxCON2<4> to start Acknowledge sequence SDA = ACKDT (SSPxCON2<5>) = 0 Write to SSPxCON2<0>(SEN = 1), begin Start condition SEN = 0 Write to SSPxBUF occurs here, ACK from Slave start XMIT RCEN = 1, next receive RCEN cleared automatically Transmit Address to Slave start PEN bit = 1 written here RCEN cleared automatically Receiving Data from Slave Receiving Data from Slave A7 A6 A5 A4 A3 A2 A1 R/W ACK SDA Set ACKEN, start Acknowledge sequence SDA = ACKDT = 1 ACK from Master SDA = ACKDT = 0 Master configured as a receiver by programming SSPxCON2<3> (RCEN = 1) D7 D6 D5 D4 D3 D2 D1 ACK D0 D7 D6 D5 D4 D3 D2 D1 D0 ACK ACK SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 Data shifted in on falling edge of CLK Set SSPxIF interrupt at end of receive 1 Cleared by software Cleared by software Cleared by software BF (SSPxSTAT<0>) 9 8 Cleared by software Bus master terminates transfer P Set SSPxIF at end of receive Set SSPxIF interrupt at end of Acknowledge sequence SSPxIF SDA = 0, SCL = while CPU responds to SSPxIF is not sent Cleared in software Set SSPxIF interrupt at end of Acknowledge sequence Set P bit (SSPxSTAT<4>) and SSPxIF Last bit is shifted into SSPSR and contents are unloaded into SSPxBUF SSPOV is set because SSPxBUF is still full ACKEN DS40001819B-page 479 RCEN Master configured as a receiver by programming SSPxCON2<3> (RCEN = 1) RCEN cleared automatically ACK from Master SDA = ACKDT = 0 RCEN cleared automatically PIC16(L)F1777/8/9 SSPOV PIC16(L)F1777/8/9 32.6.8 ACKNOWLEDGE SEQUENCE TIMING 32.6.9 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPxCON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to `0'. When the Baud Rate Generator times out, the SCL pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDA pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit of the SSPxSTAT register is set. A TBRG later, the PEN bit is cleared and the SSPxIF bit is set (Figure 32-31). An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN bit of the SSPxCON2 register. When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). When the SCL pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode (Figure 32-30). 32.6.8.1 32.6.9.1 WCOL Status Flag If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL Status Flag If the user writes the SSPxBUF when an Acknowledge sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). FIGURE 32-30: STOP CONDITION TIMING ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, write to SSPxCON2 ACKEN = 1, ACKDT = 0 ACKEN automatically cleared TBRG TBRG SDA ACK D0 SCL 8 9 SSPxIF SSPxIF set at the end of receive Cleared in software Cleared in software SSPxIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 32-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPxSTAT<4>) is set. Write to SSPxCON2, set PEN PEN bit (SSPxCON2<2>) is cleared by hardware and the SSPxIF bit is set Falling edge of 9th clock TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. DS40001819B-page 480 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 32.6.10 SLEEP OPERATION 32.6.13 2 While in Sleep mode, the I C slave module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 32.6.11 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 32.6.12 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit of the SSPxSTAT register is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed by hardware with the result placed in the BCLIF bit. The states where arbitration can be lost are: * * * * * Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a `1' on SDA, by letting SDA float high and another master asserts a `0'. When the SCL pin floats high, data should be stable. If the expected data on SDA is a `1' and the data sampled on the SDA pin is `0', then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF and reset the I2C port to its Idle state (Figure 32-32). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are deasserted and the SSPxBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPxCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSPxIF bit will be set. A write to the SSPxBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPxSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 32-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data does not match what is driven by the master. Bus collision has occurred. SDA SCL Set bus collision interrupt (BCLIF) BCLIF 2015-2016 Microchip Technology Inc. DS40001819B-page 481 PIC16(L)F1777/8/9 32.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 32-33). SCL is sampled low before SDA is asserted low (Figure 32-34). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: * the Start condition is aborted, * the BCLIF flag is set and * the MSSP module is reset to its Idle state (Figure 32-33). collision occurs because it is assumed that another master is attempting to drive a data `1' during the Start condition. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 32-35). If, however, a `1' is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCL pin is sampled as `0' during this time, a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high, the Baud Rate Generator is loaded and counts down. If the SCL pin is sampled low while SDA is high, a bus FIGURE 32-33: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPxIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start condition if SDA = 1, SCL = 1 SEN cleared automatically because of bus collision. SSP module reset into Idle state. SEN BCLIF SDA sampled low before Start condition. Set BCLIF. S bit and SSPxIF set because SDA = 0, SCL = 1. SSPxIF and BCLIF are cleared by software S SSPxIF SSPxIF and BCLIF are cleared by software DS40001819B-page 482 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 32-34: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared by software S '0' '0' SSPxIF '0' '0' FIGURE 32-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG SDA Set SSPxIF TBRG SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time-out SEN BCLIF Set SEN, enable Start sequence if SDA = 1, SCL = 1 '0' S SSPxIF SDA = 0, SCL = 1, set SSPxIF 2015-2016 Microchip Technology Inc. Interrupts cleared by software DS40001819B-page 483 PIC16(L)F1777/8/9 32.6.13.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data `0', Figure 32-36). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from low level to high level (Case 1). SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data `1' (Case 2). If SCL goes from high-to-low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data `1' during the Repeated Start condition, see Figure 32-37. When the user releases SDA and the pin is allowed to float high, the BRG is loaded with SSPxADD and counts down to zero. The SCL pin is then deasserted and when sampled high, the SDA pin is sampled. FIGURE 32-36: If, at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared by software S '0' SSPxIF '0' FIGURE 32-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL BCLIF SCL goes low before SDA, set BCLIF. Release SDA and SCL. Interrupt cleared by software RSEN S '0' SSPxIF DS40001819B-page 484 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 32.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD and counts down to zero. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data `0' (Figure 32-38). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data `0' (Figure 32-39). Bus collision occurs during a Stop condition if: a) b) After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed out (Case 1). After the SCL pin is deasserted, SCL is sampled low before SDA goes high (Case 2). FIGURE 32-38: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA SDA sampled low after TBRG, set BCLIF SDA asserted low SCL PEN BCLIF P '0' SSPxIF '0' FIGURE 32-39: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA Assert SDA SCL SCL goes low before SDA goes high, set BCLIF PEN BCLIF P '0' SSPxIF '0' 2015-2016 Microchip Technology Inc. DS40001819B-page 485 PIC16(L)F1777/8/9 TABLE 32-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH I2C OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: ANSELA -- -- ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177 ANSELB -- -- ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 -- -- 187 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133 PIE2 OSFIE C2IE C1IE COG1IE BCL1IE C4IE C3IE CCP2IE 134 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139 PIR2 OSFIF C2IF C1IF COG1IF BCL1IF C4IF C3IF CCP2IF 140 RxyPPS -- -- SSPCLKPPS -- SSPDATPPS -- SSPSSPPS -- -- RxyPPS<5:0> 205 -- SSPCLKPPS<5:0> 205, 207 -- SSPDATPPS<5:0> 205, 207 SSPSSPPS<5:0> 205, 207 SSP1ADD SSP1BUF SSP1CON1 ADD<7:0> 492 Synchronous Serial Port Receive Buffer/Transmit Register 444* WCOL SSPOV SSPEN CKP SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 490 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 491 SMP CKE D/A P R/W UA BF 488 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186 SSP1MSK SSP1STAT Legend: * SSPM<3:0> 489 MSK<7:0> 492 S 2 -- = unimplemented location, read as `0'. Shaded cells are not used by the MSSP module in I C mode. Page provides register information. DS40001819B-page 486 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 32.7 BAUD RATE GENERATOR The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPxADD register (Register 32-6). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. module clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSP is being operated in. Table 32-4 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD. EQUATION 32-1: FOSC FCLOCK = ------------------------------------------------ SSPxADD + 1 4 An internal signal "Reload" in Figure 32-40 triggers the value from SSPxADD to be loaded into the BRG counter. This occurs twice for each oscillation of the FIGURE 32-40: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPM<3:0> Reload SSPxADD<7:0> Reload Control SCL SSPCLK BRG Down Counter FOSC/2 Note: Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. TABLE 32-4: Note: MSSP CLOCK RATE W/BRG FOSC FCY BRG Value FCLOCK (2 Rollovers of BRG) 32 MHz 8 MHz 13h 400 kHz 32 MHz 8 MHz 19h 308 kHz 32 MHz 8 MHz 4Fh 100 kHz 16 MHz 4 MHz 09h 400 kHz 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz Refer to the I/O port electrical specifications in Table 36-10 and Figure 32-7 to ensure the system is designed to support I/O requirements. 2015-2016 Microchip Technology Inc. DS40001819B-page 487 PIC16(L)F1777/8/9 32.8 Register Definitions: MSSP Control REGISTER 32-1: SSP1STAT: SSP STATUS REGISTER R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I2 C Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only) In SPI Master or Slave mode: 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state In I2 C mode only: 1 = Enable input logic so that thresholds are compliant with SMBus specification 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is `0' on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is `0' on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I2 C Slave mode: 1 = Read 0 = Write In I2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSP1ADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSP1BUF is full 0 = Receive not complete, SSP1BUF is empty Transmit (I2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSP1BUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSP1BUF is empty DS40001819B-page 488 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 32-2: SSP1CON1: SSP CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 WCOL SSPOV(1) SSPEN CKP R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSPM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSP1BUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSP1BUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSP1BUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSP1BUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF register (must be cleared in software). 0 = No overflow 2 In I C mode: 1 = A byte is received while the SSP1BUF register is still holding the previous byte. SSPOV is a "don't care" in Transmit mode (must be cleared in software). 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins In I2C mode: 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2C Slave mode: SCL release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I2C Master mode: Unused in this mode bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1101 = Reserved 1100 = Reserved 1011 = I2C firmware controlled Master mode (slave idle) 1010 = SPI Master mode, clock = FOSC/(4 * (SSP1ADD+1))(5) 1001 = Reserved 1000 = I2C Master mode, clock = FOSC / (4 * (SSP1ADD+1))(4) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0011 = SPI Master mode, clock = T2_match/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note 1: 2: 3: 4: 5: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF register. When enabled, these pins must be properly configured as input or output. Use SSPSSPPS, SSPCLKPPS, SSPDATPPS, and RxyPPS to select the pins. When enabled, the SDA and SCL pins must be configured as inputs. Use SSPCLKPPS, SSPDATPPS, and RxyPPS to select the pins. SSP1ADD values of 0, 1 or 2 are not supported for I2C mode. SSP1ADD value of `0' is not supported. Use SSPM = 0000 instead. 2015-2016 Microchip Technology Inc. DS40001819B-page 489 PIC16(L)F1777/8/9 SSP1CON2: SSP CONTROL REGISTER 2(1) REGISTER 32-3: R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received bit 5 ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle bit 3 RCEN: Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only) SCKMSSP Release Control: 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable/Stretch Enable bit In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSP1BUF may not be written (or writes to the SSP1BUF are disabled). DS40001819B-page 490 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 32-4: SSP1CON3: SSP CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM(3) PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on eighth falling edge of SCL clock 0 = Not an Acknowledge sequence, cleared on ninth rising edge of SCL clock bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C slave mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) bit 5 SCIE: Start Condition Interrupt Enable bit (I2C slave mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) bit 4 BOEN: Buffer Overwrite Enable bit In SPI Slave mode:(1) 1 = SSP1BUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSP1STAT register already set, SSPOV bit of the SSP1CON1 register is set, and the buffer is not updated In I2C Master mode and SPI Master mode: This bit is ignored. In I2C Slave mode: 1 = SSP1BUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSPOV bit only if the BF bit = 0. 0 = SSP1BUF is only updated when SSPOV is clear bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only) 1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL 0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If, on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCL1IF bit of the PIR2 register is set, and bus goes idle 1 = Enable slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the eighth falling edge of SCL for a matching received address byte; CKP bit of the SSP1CON1 register will be cleared and the SCL will be held low. 0 = Address holding is disabled bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the eighth falling edge of SCL for a received data byte; slave hardware clears the CKP bit of the SSP1CON1 register and SCL is held low. 0 = Data holding is disabled Note 1: 2: 3: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSP1BUF. This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set. 2015-2016 Microchip Technology Inc. DS40001819B-page 491 PIC16(L)F1777/8/9 REGISTER 32-5: R/W-1/1 SSP1MSK: SSP MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSP1ADD<n> to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSPM<3:0> = 0111 or 1111): 1 = The received address bit 0 is compared to SSP1ADD<0> to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address, the bit is ignored REGISTER 32-6: R/W-0/0 SSP1ADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared Master mode: bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC 10-Bit Slave mode - Most Significant Address Byte: bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a "don't care". Bit pattern sent by master is fixed by I2C specification and must be equal to `11110'. However, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address bit 0 Not used: Unused in this mode. Bit state is a "don't care". 10-Bit Slave mode - Least Significant Address Byte: bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD<7:1>: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a "don't care". DS40001819B-page 492 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 33.0 The EUSART module includes the following capabilities: ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) * * * * * * * * * * Full-duplex asynchronous transmit and receive Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Address detection in 9-bit mode Input buffer overrun error detection Received character framing error detection Half-duplex synchronous master Half-duplex synchronous slave Programmable clock polarity in synchronous modes * Sleep operation The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The EUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. The EUSART module implements the following additional features, making it ideally suited for use in Local Interconnect Network (LIN) bus systems: * Automatic detection and calibration of the baud rate * Wake-up on Break reception * 13-bit Break character transmit Block diagrams of the EUSART transmitter and receiver are shown in Figure 33-1 and Figure 33-2. The EUSART transmit output (TX_out) is available to the TX/CK pin and internally to the following peripherals: * Configurable Logic Cell (CLC) * Data signal modulator (DSM) FIGURE 33-1: EUSART TRANSMIT BLOCK DIAGRAM Data Bus SYNC CSRC 8 TXEN LSb (8) 0 * * * CKPPS TRMT PPS TX9 n Multiplier SYNC TX_out /n BRG16 SPxBRGH SPxBRGL RX/DT pin SYNC FOSC +1 Pin Buffer and Control Transmit Shift Register (TSR) 0 Note 1: RxyPPS(1) MSb 1 Baud Rate Generator Interrupt TXIF TXxREG Register CK pin PPS TXIE x4 x16 x64 1 X 0 0 TX9D BRGH X 1 1 0 0 BRG16 X 1 0 1 0 In Synchronous mode the DT output and RX input PPS selections should enable the same pin. 2015-2016 Microchip Technology Inc. TX/CK pin 0 0 PPS 1 RxyPPS SYNC CSRC DS40001819B-page 493 PIC16(L)F1777/8/9 FIGURE 33-2: EUSART RECEIVE BLOCK DIAGRAM SPEN RX/DT pin CREN RXPPS(1) RSR Register MSb PPS Pin Buffer and Control Baud Rate Generator Data Recovery FOSC BRG16 +1 SPxBRGH SPxBRGL Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 Stop (8) *** 7 1 LSb 0 Start RX9 /n n FERR RX9D RCxREG Register 8 Note 1: RCIDL OERR In Synchronous mode the DT output and RX input PPS selections should enable the same pin. FIFO Data Bus RCIF RCIE Interrupt The operation of the EUSART module is controlled through three registers: * Transmit Status and Control (TXxSTA) * Receive Status and Control (RCxSTA) * Baud Rate Control (BAUDxCON) These registers are detailed in Register 33-1, Register 33-2 and Register 33-3, respectively. The RX and CK input pins are selected with the RXPPS and CKPPS registers, respectively. TX, CK, and DT output pins are selected with each pin's RxyPPS register. Since the RX input is coupled with the DT output in Synchronous mode, it is the user's responsibility to select the same pin for both of these functions when operating in Synchronous mode. The EUSART control logic will control the data direction drivers automatically. DS40001819B-page 494 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 33.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH Mark state which represents a `1' data bit, and a VOL Space state which represents a `0' data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the Mark state. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data format is eight bits. Each transmitted bit persists for a period of 1/(baud rate). An on-chip dedicated 8-bit/16-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table 33-5 for examples of baud rate configurations. The EUSART transmits and receives the LSb first. The EUSART's transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. 33.1.1 EUSART ASYNCHRONOUS TRANSMITTER The EUSART transmitter block diagram is shown in Figure 33-1. The heart of the transmitter is the serial Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the TXxREG register. 33.1.1.1 Enabling the Transmitter The EUSART transmitter is enabled for asynchronous operations by configuring the following three control bits: * TXEN = 1 * SYNC = 0 * SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the TXEN bit of the TXxSTA register enables the transmitter circuitry of the EUSART. Clearing the SYNC bit of the TXxSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCxSTA register enables the EUSART and automatically configures the TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Note: 33.1.1.2 Transmitting Data A transmission is initiated by writing a character to the TXxREG register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXxREG is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the TXxREG until the Stop bit of the previous character has been transmitted. The pending character in the TXxREG is then transferred to the TSR in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXxREG. 33.1.1.3 Transmit Data Polarity The polarity of the transmit data can be controlled with the SCKP bit of the BAUDxCON register. The default state of this bit is `0', which selects high true transmit idle and data bits. Setting the SCKP bit to `1' will invert the transmit data resulting in low true idle and data bits. The SCKP bit controls transmit data polarity in Asynchronous mode only. In Synchronous mode, the SCKP bit has a different function. See Section 33.5.1.2 "Clock Polarity". 33.1.1.4 Transmit Interrupt Flag The TXIF interrupt flag bit of the PIR1 register is set whenever the EUSART transmitter is enabled and no character is being held for transmission in the TXxREG. In other words, the TXIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the TXxREG. The TXIF flag bit is not cleared immediately upon writing TXxREG. TXIF becomes valid in the second instruction cycle following the write execution. Polling TXIF immediately following the TXxREG write will return invalid results. The TXIF bit is read-only, it cannot be set or cleared by software. The TXIF interrupt can be enabled by setting the TXIE interrupt enable bit of the PIE1 register. However, the TXIF flag bit will be set whenever the TXxREG is empty, regardless of the state of the TXIE enable bit. To use interrupts when transmitting data, set the TXIE bit only when there is more data to send. Clear the TXIE interrupt enable bit upon writing the last character of the transmission to the TXxREG. The TXIF Transmitter Interrupt flag is set when the TXEN enable bit is set. 2015-2016 Microchip Technology Inc. DS40001819B-page 495 PIC16(L)F1777/8/9 33.1.1.5 TSR Status 33.1.1.7 The TRMT bit of the TXxSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXxREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 33.1.1.6 1. 2. 3. The TSR register is not mapped in data memory, so it is not available to the user. Transmitting 9-Bit Characters The EUSART supports 9-bit character transmissions. When the TX9 bit of the TXxSTA register is set, the EUSART will shift nine bits out for each character transmitted. The TX9D bit of the TXxSTA register is the ninth, and Most Significant data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the eight Least Significant bits into the TXxREG. All nine bits of data will be transferred to the TSR shift register immediately after the TXxREG is written. A special 9-bit Address mode is available for use with multiple receivers. See Section 33.1.2.7 "Address Detection" for more information on the Address mode. FIGURE 33-3: Write to TXxREG BRG Output (Shift Clock) TX/CK pin TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) DS40001819B-page 496 4. 5. 6. 7. 8. Asynchronous Transmission Set-up: Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 33.4 "EUSART Baud Rate Generator (BRG)"). Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the eight Least Significant data bits are an address when the receiver is set for address detection. Set the SCKP bit if inverted transmit is desired. Enable the transmission by setting the TXEN control bit. This will cause the TXIF interrupt bit to be set. If interrupts are desired, set the TXIE interrupt enable bit of the PIE1 register. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are also set. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. Load 8-bit data into the TXxREG register. This will start the transmission. ASYNCHRONOUS TRANSMISSION Word 1 Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 1 TCY Word 1 Transmit Shift Reg. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 33-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXxREG Word 1 BRG Output (Shift Clock) TX/CK pin Word 2 Start bit bit 0 bit 1 Word 1 1 TCY TXIF bit (Transmit Buffer Reg. Empty Flag) bit 7/8 Stop bit Start bit Word 2 bit 0 1 TCY Word 1 Transmit Shift Reg. TRMT bit (Transmit Shift Reg. Empty Flag) Word 2 Transmit Shift Reg. This timing diagram shows two consecutive transmissions. Note: TABLE 33-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page 177 ANSELA -- -- ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 ANSELB -- -- ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 -- -- 187 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 505 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139 RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 504 RxyPPS -- -- BAUD1CON INTCON 205, 207 RxyPPS<5:0> SP1BRGL SP1BRG<7:0> SP1BRGH 506* SP1BRG<15:8> 506* TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 TRISC TX1REG TX1STA Legend: * EUSART Transmit Data Register CSRC TX9 TXEN 186 495* SYNC SENDB BRGH TRMT TX9D 503 -- = unimplemented location, read as `0'. Shaded cells are not used for asynchronous transmission. Page provides register information. 2015-2016 Microchip Technology Inc. DS40001819B-page 497 PIC16(L)F1777/8/9 33.1.2 EUSART ASYNCHRONOUS RECEIVER The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 33-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate. When all eight or nine bits of the character have been shifted in, they are immediately transferred to a two character First-In-First-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the EUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCxREG register. 33.1.2.1 Enabling the Receiver The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits: * CREN = 1 * SYNC = 0 * SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the CREN bit of the RCxSTA register enables the receiver circuitry of the EUSART. Clearing the SYNC bit of the TXxSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCxSTA register enables the EUSART. The programmer must set the corresponding TRIS bit to configure the RX/DT I/O pin as an input. Note: If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. 33.1.2.2 Receiving Data The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting `0' or `1' is shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is always a `1'. If the data recovery circuit samples a `0' in the Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. See Section 33.1.2.4 "Receive Framing Error" for more information on framing errors. Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the EUSART receive FIFO and the RCIF interrupt flag bit of the PIR1 register is set. The top character in the FIFO is transferred out of the FIFO by reading the RCxREG register. Note: 33.1.2.3 If the receive FIFO is overrun, no additional characters will be received until the overrun condition is cleared. See Section 33.1.2.5 "Receive Overrun Error" for more information on overrun errors. Receive Interrupts The RCIF interrupt flag bit of the PIR1 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCIF interrupts are enabled by setting all of the following bits: * RCIE, Interrupt Enable bit of the PIE1 register * PEIE, Peripheral Interrupt Enable bit of the INTCON register * GIE, Global Interrupt Enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. DS40001819B-page 498 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 33.1.2.4 Receive Framing Error Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCxSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCxREG. The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. The FERR bit can be forced clear by clearing the SPEN bit of the RCxSTA register which resets the EUSART. Clearing the CREN bit of the RCxSTA register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Note: 33.1.2.5 33.1.2.7 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCxSTA register. Address detection requires 9-bit character reception. When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCIF interrupt bit. All other characters will be ignored. Upon receiving an address character, user software determines if the address matches its own. Upon address match, user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user software detects the end of the message, determined by the message protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN bit. If all receive characters in the receive FIFO have framing errors, repeated reads of the RCxREG will not clear the FERR bit. Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCxSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCxSTA register or by resetting the EUSART by clearing the SPEN bit of the RCxSTA register. 33.1.2.6 Receiving 9-Bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCxSTA register is set the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCxSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCxREG. 2015-2016 Microchip Technology Inc. DS40001819B-page 499 PIC16(L)F1777/8/9 33.1.2.8 Asynchronous Reception Set-up 33.1.2.9 1. Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 33.4 "EUSART Baud Rate Generator (BRG)"). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5. If 9-bit reception is desired, set the RX9 bit. 6. Enable reception by setting the CREN bit. 7. The RCIF interrupt flag bit will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. 8. Read the RCxSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 9. Get the received eight Least Significant data bits from the receive buffer by reading the RCxREG register. 10. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. FIGURE 33-5: Rcv Shift Reg Rcv Buffer Reg. RCIDL This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 33.4 "EUSART Baud Rate Generator (BRG)"). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5. Enable 9-bit reception by setting the RX9 bit. 6. Enable address detection by setting the ADDEN bit. 7. Enable reception by setting the CREN bit. 8. The RCIF interrupt flag bit will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. 9. Read the RCxSTA register to get the error flags. The ninth data bit will always be set. 10. Get the received eight Least Significant data bits from the receive buffer by reading the RCxREG register. Software determines if this is the device's address. 11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 12. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. ASYNCHRONOUS RECEPTION Start bit bit 0 RX/DT pin 9-bit Address Detection Mode Set-up bit 1 bit 7/8 Stop bit Start bit Word 1 RCxREG bit 0 bit 7/8 Stop bit Start bit bit 7/8 Stop bit Word 2 RCxREG Read Rcv Buffer Reg. RCxREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCxREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. DS40001819B-page 500 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 33-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA -- -- ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177 ANSELB -- -- ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 -- -- 187 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 505 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139 RC1STA SPEN RX9 SREN OERR RX9D RxyPPS -- -- BAUD1CON INTCON RC1REG EUSART Receive Data Register ADDEN 498* FERR SP1BRG<7:0> SP1BRGH 506 SP1BRG<15:8> TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 504 205 RxyPPS<5:0> SP1BRGL TRISA CREN 506 TRISA2 TRISA1 TRISA0 176 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 503 TX1STA Legend: * -- = unimplemented location, read as `0'. Shaded cells are not used for asynchronous reception. Page provides register information. 2015-2016 Microchip Technology Inc. DS40001819B-page 501 PIC16(L)F1777/8/9 33.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source. See Section 5.2.2.3 "Internal Oscillator Frequency Adjustment" for more information. The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud Detect feature (see Section 33.4.1 "Auto-Baud Detect"). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. DS40001819B-page 502 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 33.3 Register Definitions: EUSART Control REGISTER 33-1: R/W-/0 TX1STA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0/0 CSRC TX9 R/W-0/0 TXEN (1) R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0 SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don't care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don't care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. 2015-2016 Microchip Technology Inc. DS40001819B-page 503 PIC16(L)F1777/8/9 REGISTER 33-2: RC1STA: RECEIVE STATUS AND CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don't care Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave Don't care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don't care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCxREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. DS40001819B-page 504 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 REGISTER 33-3: BAUD1CON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don't care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don't care bit 5 Unimplemented: Read as `0' bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Transmit inverted data to the TX/CK pin 0 = Transmit non-inverted data to the TX/CK pin Synchronous mode: 1 = Data is clocked on rising edge of the clock 0 = Data is clocked on falling edge of the clock bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used bit 2 Unimplemented: Read as `0' bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE will automatically clear after RCIF is set. 0 = Receiver is operating normally Synchronous mode: Don't care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don't care 2015-2016 Microchip Technology Inc. DS40001819B-page 505 PIC16(L)F1777/8/9 33.4 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDxCON register selects 16-bit mode. The SPxBRGH:SPxBRGL register pair determines the period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by both the BRGH bit of the TXxSTA register and the BRG16 bit of the BAUDxCON register. In Synchronous mode, the BRGH bit is ignored. Table 33-3 contains the formulas for determining the baud rate. Example 33-1 provides a sample calculation for determining the baud rate and baud rate error. Typical baud rates and error values for various Asynchronous modes have been computed for your convenience and are shown in Table 33-5. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. EXAMPLE 33-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: F OS C Desired Baud Rate = -----------------------------------------------------------------------64 [SPBRGH:SPBRGL] + 1 Solving for SPxBRGH:SPxBRGL: FOSC --------------------------------------------Desired Baud Rate X = --------------------------------------------- - 1 64 16000000 -----------------------9600 = ------------------------ - 1 64 = 25.042 = 25 16000000 Calculated Baud Rate = --------------------------64 25 + 1 = 9615 Calc. Baud Rate - Desired Baud Rate Error = -------------------------------------------------------------------------------------------Desired Baud Rate 9615 - 9600 = ---------------------------------- = 0.16% 9600 Writing a new value to the SPxBRGH:SPxBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is idle before changing the system clock. DS40001819B-page 506 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 33-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 x 16-bit/Synchronous SYNC BRG16 BRGH 0 0 0 1 Legend: FOSC/[4 (n+1)] x = Don't care, n = value of SPxBRGH:SPxBRGL register pair. TABLE 33-4: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Bit 7 BAUD1CON ABDOVF RC1STA SPEN Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page RCIDL -- SCKP BRG16 -- WUE ABDEN 505 RX9 SREN CREN ADDEN FERR OERR RX9D 504 SP1BRGL SP1BRG<7:0> SP1BRGH TX1STA FOSC/[16 (n+1)] 506 SP1BRG<15:8> CSRC TX9 TXEN SYNC SENDB 506 BRGH TRMT TX9D 503 Legend: -- = unimplemented location, read as `0'. Shaded cells are not used for the Baud Rate Generator. * Page provides register information. 2015-2016 Microchip Technology Inc. DS40001819B-page 507 PIC16(L)F1777/8/9 TABLE 33-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 32.000 MHz Actual Rate % Error SPxBRG value (decimal) FOSC = 20.000 MHz Actual Rate % Error SPxBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPxBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPxBRG value (decimal) 300 -- -- -- -- -- -- -- -- -- -- -- -- 1200 -- -- -- 1221 1.73 255 1200 0.00 239 1200 0.00 143 2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71 9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17 10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 57.6k 55.55k -3.55 3 -- -- -- 57.60k 0.00 7 57.60k 0.00 2 115.2k -- -- -- -- -- -- -- -- -- -- -- -- SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPxBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPxBRG value (decimal) FOSC = 3.6864 MHz Actual Rate % Error SPxBRG value (decimal) FOSC = 1.000 MHz Actual Rate % Error SPxBRG value (decimal) 300 -- -- -- 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 -- -- -- 9600 9615 0.16 12 -- -- -- 9600 0.00 5 -- -- -- 10417 10417 0.00 11 10417 0.00 5 -- -- -- -- -- -- 19.2k -- -- -- -- -- -- 19.20k 0.00 2 -- -- -- 57.6k -- -- -- -- -- -- 57.60k 0.00 0 -- -- -- 115.2k -- -- -- -- -- -- -- -- -- -- -- -- SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 32.000 MHz Actual Rate % Error SPxBRG value (decimal) FOSC = 20.000 MHz Actual Rate % Error SPxBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPxBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPxBRG value (decimal) 300 -- -- -- -- -- -- -- -- -- -- -- -- 1200 -- -- -- -- -- -- -- -- -- -- -- -- 2400 -- -- -- -- -- -- -- -- -- -- -- -- 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5 DS40001819B-page 508 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 33-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPxBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPxBRG value (decimal) FOSC = 3.6864 MHz Actual Rate FOSC = 1.000 MHz % Error SPxBRG value (decimal) Actual Rate % Error SPxBRG value (decimal) 300 1200 -- -- -- -- -- -- -- 1202 -- 0.16 -- 207 -- 1200 -- 0.00 -- 191 300 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 -- 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 -- -- 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 -- -- -- 57.6k 55556 -3.55 8 -- -- -- 57.60k 0.00 3 -- -- -- 115.2k -- -- -- -- -- -- 115.2k 0.00 1 -- -- -- SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 32.000 MHz Actual Rate FOSC = 20.000 MHz % Error SPxBRG value (decimal) Actual Rate FOSC = 18.432 MHz % Error SPxBRG value (decimal) Actual Rate FOSC = 11.0592 MHz % Error SPxBRG value (decimal) Actual Rate % Error SPxBRG value (decimal) 300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303 1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575 2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5 SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate FOSC = 4.000 MHz % Error SPxBRG value (decimal) Actual Rate FOSC = 3.6864 MHz % Error SPxBRG value (decimal) Actual Rate FOSC = 1.000 MHz % Error SPxBRG value (decimal) Actual Rate % Error SPxBRG value (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 -- -- -- 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 -- -- -- 57.6k 55556 -3.55 8 -- -- -- 57.60k 0.00 3 -- -- -- 115.2k -- -- -- -- -- -- 115.2k 0.00 1 -- -- -- 2015-2016 Microchip Technology Inc. DS40001819B-page 509 PIC16(L)F1777/8/9 TABLE 33-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz Actual Rate % Error SPxBRG value (decimal) 300 1200 300.0 1200 0.00 0.00 26666 6666 300.0 1200 0.00 -0.01 16665 4166 300.0 1200 0.00 0.00 15359 3839 300.0 1200 0.00 0.00 9215 2303 2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 Actual Rate % Error SPxBRG value (decimal) Actual Rate % Error SPxBRG value (decimal) Actual Rate % Error SPxBRG value (decimal) 9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287 10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264 19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate FOSC = 4.000 MHz % Error SPxBRG value (decimal) Actual Rate FOSC = 3.6864 MHz % Error SPxBRG value (decimal) Actual Rate FOSC = 1.000 MHz % Error SPxBRG value (decimal) Actual Rate % Error SPxBRG value (decimal) 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 -- -- -- 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 -- -- -- DS40001819B-page 510 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 33.4.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII "U") which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge. Setting the ABDEN bit of the BAUDxCON register starts the auto-baud calibration sequence. While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of the receive line, after the Start bit, the SPxBRG begins counting up using the BRG counter clock as shown in Figure 33-6. The fifth rising edge will occur on the RX pin at the end of the eighth bit period. At that time, an accumulated value totaling the proper BRG period is left in the SPxBRGH:SPxBRGL register pair, the ABDEN bit is automatically cleared and the RCIF interrupt flag is set. The value in the RCxREG needs to be read to clear the RCIF interrupt. RCxREG content should be discarded. When calibrating for modes that do not use the SPxBRGH register the user can verify that the SPxBRGL register did not overflow by checking for 00h in the SPxBRGH register. The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table 33-6. During ABD, both the SPxBRGH and SPxBRGL registers are used as a 16-bit counter, independent of the BRG16 bit setting. While calibrating the baud rate period, the SPxBRGH and SPxBRGL registers are clocked at Note 1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see Section 33.4.3 "Auto-Wake-up on Break"). 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible. 3: During the auto-baud process, the auto-baud counter starts counting at one. Upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the SPxBRGH:SPxBRGL register pair. TABLE 33-6: BRG COUNTER CLOCK RATES BRG16 BRGH BRG Base Clock BRG ABD Clock 0 0 FOSC/64 FOSC/512 0 1 FOSC/16 FOSC/128 1 0 FOSC/16 FOSC/128 1 1 FOSC/4 FOSC/32 During the ABD sequence, SPxBRGL and SPxBRGH registers are both used as a 16-bit counter, independent of the BRG16 setting. Note: AUTOMATIC BAUD RATE CALIBRATION(1) FIGURE 33-6: XXXXh BRG Value 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. 0000h RX pin 001Ch Start Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 Edge #5 Stop bit BRG Clock Auto Cleared Set by User ABDEN bit RCIDL RCIF bit (Interrupt) Read RCxREG SPxBRGL XXh 1Ch SPxBRGH XXh 00h Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode. 2015-2016 Microchip Technology Inc. DS40001819B-page 511 PIC16(L)F1777/8/9 33.4.2 AUTO-BAUD OVERFLOW During the course of automatic baud detection, the ABDOVF bit of the BAUDxCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPxBRGH:SPxBRGL register pair. The overflow condition will set the RCIF flag. The counter continues to count until the fifth rising edge is detected on the RX pin. The RCIDL bit will remain false (`0') until the fifth rising edge at which time the RCIDL bit will be set. If the RCREG is read after the overflow occurs but before the fifth rising edge then the fifth rising edge will set the RCIF again. Terminating the auto-baud process early to clear an overflow condition will prevent proper detection of the sync character fifth rising edge. If any falling edges of the sync character have not yet occurred when the ABDEN bit is cleared then those will be falsely detected as Start bits. The following steps are recommended to clear the overflow condition: 1. 2. 3. Read RCREG to clear RCIF. If RCIDL is zero then wait for RCIF and repeat step 1. Clear the ABDOVF bit. 33.4.3 AUTO-WAKE-UP ON BREAK During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit of the BAUDxCON register. Once set, the normal receive sequence on RX/DT is disabled, and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) 33.4.3.1 Special Considerations Break Character To avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. When the wake-up is enabled the function works independent of the low time on the data stream. If the WUE bit is set and a valid non-zero character is received, the low time from the Start bit to the first rising edge will be interpreted as the wake-up event. The remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. Therefore, the initial character in the transmission must be all `0's. This must be ten or more bit times, 13-bit times recommended for LIN bus, or any number of bit times for standard RS-232 devices. Oscillator Start-up Time Oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS/PLL mode). The Sync Break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. WUE Bit The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared in hardware by a rising edge on RX/DT. The interrupt condition is then cleared in software by reading the RCxREG register and discarding its contents. To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. The EUSART module generates an RCIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU operating modes (Figure 33-7), and asynchronously if the device is in Sleep mode (Figure 33-8). The interrupt condition is cleared by reading the RCxREG register. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character. DS40001819B-page 512 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 33-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit(1) RX/DT Line RCIF Note 1: Cleared due to User Read of RCxREG The EUSART remains in Idle while the WUE bit is set. FIGURE 33-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 OSC1 Auto Cleared Bit Set by User WUE bit(2) RX/DT Line Note 1 RCIF Sleep Command Executed Note 1: 2: Sleep Ends Cleared due to User Read of RCxREG If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set. 2015-2016 Microchip Technology Inc. DS40001819B-page 513 PIC16(L)F1777/8/9 33.4.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 `0' bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXxSTA register. The Break character transmission is then initiated by a write to the TXxREG. The value of data written to TXxREG will be ignored and all `0's will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). The TRMT bit of the TXxSTA register indicates when the transmit operation is active or idle, just as it does during normal transmission. See Figure 33-9 for the timing of the Break character sequence. 33.4.4.1 Break and Sync Transmit Sequence The following sequence will start a message frame header made up of a Break, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus master. 1. 2. 3. 4. 5. 33.4.5 RECEIVING A BREAK CHARACTER The Enhanced EUSART module can receive a Break character in two ways. The first method to detect a Break character uses the FERR bit of the RCxSTA register and the received data as indicated by RCxREG. The Baud Rate Generator is assumed to have been initialized to the expected baud rate. A Break character has been received when: * RCIF bit is set * FERR bit is set * RCxREG = 00h The second method uses the Auto-Wake-up feature described in Section 33.4.3 "Auto-Wake-up on Break". By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCIF interrupt, and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of the BAUDxCON register before placing the EUSART in Sleep mode. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to enable the Break sequence. Load the TXxREG with a dummy character to initiate transmission (the value is ignored). Write `55h' to TXxREG to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXxREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXxREG. FIGURE 33-9: Write to TXxREG SEND BREAK CHARACTER SEQUENCE Dummy Write BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB (send Break control bit) DS40001819B-page 514 SENDB Sampled Here Auto Cleared 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 33.5 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. The EUSART can operate as either a master or slave device. Start and Stop bits are not used in synchronous transmissions. 33.5.1 SYNCHRONOUS MASTER MODE Clearing the SCKP bit sets the Idle state as low. When the SCKP bit is cleared, the data changes on the rising edge of each clock. 33.5.1.3 Data is transferred out of the device on the RX/DT pin. The RX/DT and TX/CK pin output drivers are automatically enabled when the EUSART is configured for synchronous master transmit operation. A transmission is initiated by writing a character to the TXxREG register. If the TSR still contains all or part of a previous character the new character data is held in the TXxREG until the last bit of the previous character has been transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXxREG is immediately transferred to the TSR. The transmission of the character commences immediately following the transfer of the data to the TSR from the TXxREG. Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. Note: The TSR register is not mapped in data memory, so it is not available to the user. 33.5.1.4 Synchronous Master Transmission Set-up: The following bits are used to configure the EUSART for synchronous master operation: * * * * * SYNC = 1 CSRC = 1 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 Setting the SYNC bit of the TXxSTA register configures the device for synchronous operation. Setting the CSRC bit of the TXxSTA register configures the device as a master. Clearing the SREN and CREN bits of the RCxSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCxSTA register enables the EUSART. 33.5.1.1 33.5.1.2 1. 2. 3. 4. 5. 6. Master Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TX/CK line. The TX/CK pin output driver is automatically enabled when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits. Synchronous Master Transmission 7. 8. Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 33.4 "EUSART Baud Rate Generator (BRG)"). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Disable Receive mode by clearing bits SREN and CREN. Enable Transmit mode by setting the TXEN bit. If 9-bit transmission is desired, set the TX9 bit. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. Start transmission by loading data to the TXxREG register. Clock Polarity A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit of the BAUDxCON register. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock. 2015-2016 Microchip Technology Inc. DS40001819B-page 515 PIC16(L)F1777/8/9 FIGURE 33-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXxREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit Note: `1' `1' Sync Master mode, SPxBRGL = 0, continuous transmission of two 8-bit words. FIGURE 33-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 TX/CK pin Write to TXxREG reg TXIF bit TRMT bit TXEN bit DS40001819B-page 516 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 33-7: Name SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA -- -- ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177 ANSELB -- -- ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 -- -- 187 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 505 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139 RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 504 RxyPPS -- -- BAUD1CON INTCON 205 RxyPPS<5:0> SP1BRGL SP1BRG<7:0> 506 SP1BRGH SP1BRG<15:8> 506 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186 CSRC TX9 TXEN TRMT TX9D EUSART Transmit Data Register TX1REG TX1STA Legend: * SYNC SENDB 495* BRGH 503 -- = unimplemented location, read as `0'. Shaded cells are not used for synchronous master transmission. Page provides register information. 2015-2016 Microchip Technology Inc. DS40001819B-page 517 PIC16(L)F1777/8/9 33.5.1.5 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCxSTA register) or the Continuous Receive Enable bit (CREN of the RCxSTA register). When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the completion of the first character and CREN takes precedence. To initiate reception, set either SREN or CREN. Data is sampled at the RX/DT pin on the trailing edge of the TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR, the RCIF bit is set and the character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are available in RCxREG. The RCIF bit remains set as long as there are unread characters in the receive FIFO. Note: 33.5.1.6 If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. Slave Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a slave receives the clock on the TX/CK line. The TX/CK pin output driver is automatically disabled when the device is configured for synchronous slave transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles should be received as there are data bits. Note: If the device is configured as a slave and the TX/CK function is on an analog pin, the corresponding ANSEL bit must be cleared. DS40001819B-page 518 33.5.1.7 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCxREG is read to access the FIFO. When this happens the OERR bit of the RCxSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCxREG. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. 33.5.1.8 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCxSTA register is set, the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCxSTA register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCxREG. 33.5.1.9 Synchronous Master Reception Set-up: 1. Initialize the SPxBRGH:SPxBRGL register pair for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 4. Ensure bits CREN and SREN are clear. 5. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 6. If 9-bit reception is desired, set bit RX9. 7. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 8. Interrupt flag bit RCIF will be set when reception of a character is complete. An interrupt will be generated if the enable bit RCIE was set. 9. Read the RCxSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. Read the 8-bit received data by reading the RCxREG register. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 33-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit `0' `0' RCIF bit (Interrupt) Read RCxREG Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. Note: TABLE 33-8: Name SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA -- -- ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177 ANSELB -- -- ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 -- -- 187 -- SCKP BRG16 -- WUE ABDEN 505 BAUD1CON ABDOVF RCIDL CKPPS -- -- INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139 RC1STA SPEN RX9 SREN OERR RX9D RXPPS -- -- RXPPS<5:0> 205, 207 RxyPPS -- -- RxyPPS<5:0> 205 RC1REG CKPPS<5:0> 205, 207 EUSART Receive Data Register CREN ADDEN 498* FERR 504 SP1BRGL SP1BRG<7:0> 506* SP1BRGH SP1BRG<15:8> 506* TRISA TRISA5 TRISA4 TRISA5 TRISA4 TRISA5 TRISA2 TRISA1 TRISA0 176 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 503 TX1STA Legend: * -- = unimplemented location, read as `0'. Shaded cells are not used for synchronous master reception. Page provides register information. 2015-2016 Microchip Technology Inc. DS40001819B-page 519 PIC16(L)F1777/8/9 33.5.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for synchronous slave operation: * * * * * SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 Setting the SYNC bit of the TXxSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXxSTA register configures the device as a slave. Clearing the SREN and CREN bits of the RCxSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCxSTA register enables the EUSART. 33.5.2.1 33.5.2.2 1. 2. 3. 4. 5. 6. 7. 8. Synchronous Slave Transmission Set-up: Set the SYNC and SPEN bits and clear the CSRC bit. Clear the ANSEL bit for the CK pin (if applicable). Clear the CREN and SREN bits. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is desired, set the TX9 bit. Enable transmission by setting the TXEN bit. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. Start transmission by writing the Least Significant eight bits to the TXxREG register. EUSART Synchronous Slave Transmit The operation of the Synchronous Master and Slave modes are identical (see Section 33.5.1.3 "Synchronous Master Transmission"), except in the case of the Sleep mode. If two words are written to the TXxREG and then the SLEEP instruction is executed, the following will occur: 1. 2. 3. 4. 5. The first character will immediately transfer to the TSR register and transmit. The second word will remain in the TXxREG register. The TXIF bit will not be set. After the first character has been shifted out of TSR, the TXxREG register will transfer the second character to the TSR and the TXIF bit will now be set. If the PEIE and TXIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine. DS40001819B-page 520 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 33-9: Name SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA -- -- ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177 ANSELB -- -- ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 -- -- 187 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN -- -- BAUD1CON CKPPS CKPPS<5:0> 505 205, 207 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133 PIR1 INTCON TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139 RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 504 RXPPS -- -- RXPPS<5:0> 205, 207 RxyPPS -- -- RxyPPS<5:0> 205 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186 TX1REG TX1STA Legend: * EUSART Transmit Data Register CSRC TX9 TXEN SYNC SENDB 495* BRGH TRMT TX9D 503 -- = unimplemented location, read as `0'. Shaded cells are not used for synchronous slave transmission. Page provides register information. 2015-2016 Microchip Technology Inc. DS40001819B-page 521 PIC16(L)F1777/8/9 33.5.2.3 EUSART Synchronous Slave Reception 33.5.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 33.5.1.5 "Synchronous Master Reception"), with the following exceptions: * Sleep * CREN bit is always set, therefore the receiver is never idle * SREN bit, which is a "don't care" in Slave mode 1. 2. 3. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCxREG register. If the RCIE enable bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector. 4. 5. 6. 7. 8. 9. Synchronous Slave Reception Set-up: Set the SYNC and SPEN bits and clear the CSRC bit. Clear the ANSEL bit for both the CK and DT pins (if applicable). If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit. Set the CREN bit to enable reception. The RCIF bit will be set when reception is complete. An interrupt will be generated if the RCIE bit was set. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCxSTA register. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCxREG register. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. TABLE 33-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name ANSELA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- -- ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177 ANSELB -- -- ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 -- -- 187 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 505 BAUD1CON CKPPS -- -- INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF RC1REG CKPPS<5:0> 205, 207 EUSART Receive Data Register RC1STA SPEN RX9 RXPPS -- -- TRISA TRISA7 TRISA6 SREN CREN ADDEN FERR OERR RX9D RXPPS<5:0> TRISA5 TRISA4 TRISA3 139 498* TRISA2 504 205, 207 TRISA1 TRISA0 176 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 503 TX1STA Legend: * -- = unimplemented location, read as `0'. Shaded cells are not used for synchronous slave reception. Page provides register information. DS40001819B-page 522 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 33.6 EUSART Operation During Sleep The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 33.6.1 SYNCHRONOUS RECEIVE DURING SLEEP To receive during Sleep, all the following conditions must be met before entering Sleep mode: * RCxSTA and TXxSTA Control registers must be configured for Synchronous Slave Reception (see Section 33.5.2.4 "Synchronous Slave Reception Set-up:"). * If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. * The RCIF interrupt flag must be cleared by reading RCxREG to unload any pending characters in the receive buffer. Upon entering Sleep mode, the device will be ready to accept data and clocks on the RX/DT and TX/CK pins, respectively. When the data word has been completely clocked in by the external device, the RCIF interrupt flag bit of the PIR1 register will be set. Thereby, waking the processor from Sleep. 33.6.2 SYNCHRONOUS TRANSMIT DURING SLEEP To transmit during Sleep, all the following conditions must be met before entering Sleep mode: * The RCxSTA and TXxSTA Control registers must be configured for synchronous slave transmission (see Section 33.5.2.2 "Synchronous Slave Transmission Set-up:"). * The TXIF interrupt flag must be cleared by writing the output data to the TXxREG, thereby filling the TSR and transmit buffer. * If interrupts are desired, set the TXIE bit of the PIE1 register and the PEIE bit of the INTCON register. * Interrupt enable bits TXIE of the PIE1 register and PEIE of the INTCON register must set. Upon entering Sleep mode, the device will be ready to accept clocks on TX/CK pin and transmit data on the RX/DT pin. When the data word in the TSR has been completely clocked out by the external device, the pending byte in the TXxREG will transfer to the TSR and the TXIF flag will be set. Thereby, waking the processor from Sleep. At this point, the TXxREG is available to accept another character for transmission, which will clear the TXIF flag. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit is also set then the Interrupt Service Routine at address 0004h will be called. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called. 2015-2016 Microchip Technology Inc. DS40001819B-page 523 PIC16(L)F1777/8/9 34.0 IN-CIRCUIT SERIAL PROGRAMMINGTM (ICSPTM) ICSPTM programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process, allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSPTM programming: * ICSPCLK * ICSPDAT * MCLR/VPP * VDD * VSS In Program/Verify mode the program memory, User IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSPTM refer to the "PIC16(L)F177X Memory Programming Specification" (DS40001792). 34.1 High-Voltage Programming Entry Mode The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. 34.2 Low-Voltage Programming Entry Mode The Low-Voltage Programming Entry mode allows the PIC(R) Flash MCUs to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Words is set to `1', the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to `0'. Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2. MCLR is brought to VIL. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. 34.3 Common Programming Interfaces Connection to a target device is typically done through an ICSPTM header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6-pin, 6-connector) configuration. See Figure 34-1. FIGURE 34-1: VDD ICD RJ-11 STYLE CONNECTOR INTERFACE ICSPDAT NC 2 4 6 ICSPCLK 1 3 5 Target VPP/MCLR VSS PC Board Bottom Side Pin Description* 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect Another connector often found in use with the PICkitTM programmers is a standard 6-pin header with 0.1 inch spacing. Refer to Figure 34-2. For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 34-3 for more information. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be disabled. See Section 6.5 "MCLR" for more information. The LVP bit can only be reprogrammed to `0' by using the High-Voltage Programming mode. DS40001819B-page 524 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 34-2: PICkitTM PROGRAMMER STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description* 1 = VPP/MCLR 1 2 3 4 5 6 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect * FIGURE 34-3: The 6-pin header (0.100" spacing) accepts 0.025" square pins. TYPICAL CONNECTION FOR ICSPTM PROGRAMMING External Programming Signals Device to be Programmed VDD VDD VDD VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required). 2015-2016 Microchip Technology Inc. DS40001819B-page 525 PIC16(L)F1777/8/9 35.0 INSTRUCTION SET SUMMARY 35.1 Read-Modify-Write Operations * Byte Oriented * Bit Oriented * Literal and Control Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register. The literal and control category contains the most varied instruction word format. TABLE 35-1: Each instruction is a 14-bit word containing the operation code (opcode) and all required operands. The opcodes are broken into three broad categories. Table 35-3 lists the instructions recognized by the MPASMTM assembler. All instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles: * Subroutine takes two cycles (CALL, CALLW) * Returns from interrupts or subroutines take two cycles (RETURN, RETLW, RETFIE) * Program branching takes two cycles (GOTO, BRA, BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) * One additional instruction cycle will be used when any instruction references an indirect file register and the file select register is pointing to program memory. One instruction cycle consists of four oscillator cycles; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution rate of 1 MHz. All instruction examples use the format `0xhh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit. OPCODE FIELD DESCRIPTIONS Field f Description Register file address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. n FSR or INDF number. (0-1) mm Pre-post increment-decrement mode selection TABLE 35-2: ABBREVIATION DESCRIPTIONS Field Program Counter TO Time-Out bit C DC Z PD DS40001819B-page 526 Description PC Carry bit Digit Carry bit Zero bit Power-Down bit 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 35-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (literal) k = 11-bit immediate value MOVLP instruction only 13 OPCODE 7 6 0 k (literal) k = 7-bit immediate value MOVLB instruction only 13 OPCODE 5 4 0 k (literal) k = 5-bit immediate value BRA instruction only 13 OPCODE 9 8 0 k (literal) k = 9-bit immediate value FSR Offset instructions 13 OPCODE 7 6 n 5 0 k (literal) n = appropriate FSR k = 6-bit immediate value FSR Increment instructions 13 OPCODE 3 2 1 0 n m (mode) n = appropriate FSR m = 2-bit mode value OPCODE only 13 0 OPCODE 2015-2016 Microchip Technology Inc. DS40001819B-page 527 PIC16(L)F1777/8/9 TABLE 35-3: INSTRUCTION SET 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear f Clear W Complement f Decrement f Increment f Inclusive OR W with f Move f Move W to f Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Subtract with Borrow W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 11 00 11 11 11 00 00 00 00 00 00 00 00 00 00 00 11 00 00 0111 1101 0101 0111 0101 0110 0001 0001 1001 0011 1010 0100 1000 0000 1101 1100 0010 1011 1110 0110 dfff dfff dfff dfff dfff dfff lfff 0000 dfff dfff dfff dfff dfff 1fff dfff dfff dfff dfff dfff dfff ffff ffff ffff ffff ffff ffff ffff 00xx ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z C, DC, Z Z C, Z C, Z C, Z Z Z Z Z Z Z Z C C C, DC, Z C, DC, Z Z 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 BYTE ORIENTED SKIP OPERATIONS DECFSZ INCFSZ f, d f, d Decrement f, Skip if 0 Increment f, Skip if 0 BCF BSF f, b f, b Bit Clear f Bit Set f 1(2) 1(2) 00 00 1, 2 1, 2 1011 dfff ffff 1111 dfff ffff BIT-ORIENTED FILE REGISTER OPERATIONS 1 1 00bb bfff ffff 01bb bfff ffff 2 2 01 01 10bb bfff ffff 11bb bfff ffff 1, 2 1, 2 11 11 11 00 11 11 11 11 1110 1001 1000 0000 0001 0000 1100 1010 01 01 BIT-ORIENTED SKIP OPERATIONS BTFSC BTFSS f, b f, b Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 (2) 1 (2) ADDLW ANDLW IORLW MOVLB MOVLP MOVLW SUBLW XORLW k k k k k k k k Add literal and W AND literal with W Inclusive OR literal with W Move literal to BSR Move literal to PCLATH Move literal to W Subtract W from literal Exclusive OR literal with W Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. LITERAL OPERATIONS 2: DS40001819B-page 528 1 1 1 1 1 1 1 1 kkkk kkkk kkkk 001k 1kkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z Z Z C, DC, Z Z 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 35-3: INSTRUCTION SET (CONTINUED) 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes CONTROL OPERATIONS BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k - k - k k k - Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine 2 2 2 2 2 2 2 2 CLRWDT NOP OPTION RESET SLEEP TRIS - - - - - f Clear Watchdog Timer No Operation Load OPTION_REG register with W Software device Reset Go into Standby mode Load TRIS register with W ADDFSR MOVIW n, k n mm MOVWI k[n] n mm Add Literal k to FSRn Move Indirect FSRn to W with pre/post inc/dec modifier, mm Move INDFn to W, Indexed Indirect. Move W to Indirect FSRn with pre/post inc/dec modifier, mm Move W to INDFn, Indexed Indirect. 11 00 10 00 10 00 11 00 001k 0000 0kkk 0000 1kkk 0000 0100 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 1011 kkkk 1010 kkkk 1001 kkkk 1000 00 00 00 00 00 00 0000 0000 0000 0000 0000 0000 0110 0000 0110 0000 0110 0110 0100 TO, PD 0000 0010 0001 0011 TO, PD 0fff INHERENT OPERATIONS 1 1 1 1 1 1 C-COMPILER OPTIMIZED k[n] Note 1: 2: 3: 1 1 11 00 0001 0nkk kkkk 0000 0001 0nmm Z 2, 3 1 1 11 00 1111 0nkk kkkk Z 0000 0001 1nmm 2 2, 3 1 11 1111 1nkk kkkk 2 If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. See Table in the MOVIW and MOVWI instruction descriptions. 2015-2016 Microchip Technology Inc. DS40001819B-page 529 PIC16(L)F1777/8/9 35.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32 k 31 n [ 0, 1] Operands: 0 k 255 Operation: FSR(n) + k FSR(n) Status Affected: None Description: The signed 6-bit literal `k' is added to the contents of the FSRnH:FSRnL register pair. k Operation: (W) .AND. (k) (W) Status Affected: Z Description: The contents of W register are AND'ed with the 8-bit literal `k'. The result is placed in the W register. ANDWF AND W with f FSRn is limited to the range 0000h-FFFFh. Moving beyond these bounds will cause the FSR to wrap-around. ADDLW Add literal and W Syntax: [ label ] ADDLW Operands: 0 k 255 Operation: Status Affected: Syntax: [ label ] ANDWF Operands: 0 f 127 d 0,1 (W) + k (W) Operation: (W) .AND. (f) (destination) C, DC, Z Status Affected: Z Description: The contents of the W register are added to the 8-bit literal `k' and the result is placed in the W register. Description: AND the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. ASRF Arithmetic Right Shift ADDWF Add W and f Syntax: [ label ] ADDWF Operands: 0 f 127 d 0,1 Operation: (W) + (f) (destination) Status Affected: C, DC, Z Description: Add the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. ADDWFC k f,d ADD W and CARRY bit to f Syntax: [ label ] ADDWFC Operands: 0 f 127 d [0,1] Operation: (W) + (f) + (C) dest Syntax: [ label ] ASRF Operands: 0 f 127 d [0,1] f {,d} Operation: (f<7>) dest<7> (f<7:1>) dest<6:0>, (f<0>) C, Status Affected: C, Z Description: The contents of register `f' are shifted one bit to the right through the Carry flag. The MSb remains unchanged. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f'. register f C f {,d} Status Affected: C, DC, Z Description: Add W, the Carry flag and data memory location `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in data memory location `f'. DS40001819B-page 530 f,d 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 BCF Bit Clear f Syntax: [ label ] BCF BTFSC f,b Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0 f 127 0b7 Operands: 0 f 127 0b7 Operands: Operation: 0 (f<b>) Operation: skip if (f<b>) = 0 Status Affected: None Status Affected: None Description: Bit `b' in register `f' is cleared. Description: If bit `b' in register `f' is `1', the next instruction is executed. If bit `b', in register `f', is `0', the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. BRA Relative Branch BTFSS Bit Test f, Skip if Set Syntax: [ label ] BRA label [ label ] BRA $+k Syntax: [ label ] BTFSS f,b Operands: Operands: -256 label - PC + 1 255 -256 k 255 0 f 127 0b<7 Operation: skip if (f<b>) = 1 Operation: (PC) + 1 + k PC Status Affected: None Status Affected: None Description: Description: Add the signed 9-bit literal `k' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + k. This instruction is a 2-cycle instruction. This branch has a limited range. If bit `b' in register `f' is `0', the next instruction is executed. If bit `b' is `1', then the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction. BRW Relative Branch with W Syntax: [ label ] BRW Operands: None Operation: (PC) + (W) PC Status Affected: None Description: Add the contents of W (unsigned) to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + (W). This instruction is a 2-cycle instruction. BSF Bit Set f Syntax: [ label ] BSF Operands: 0 f 127 0b7 f,b Operation: 1 (f<b>) Status Affected: None Description: Bit `b' in register `f' is set. 2015-2016 Microchip Technology Inc. DS40001819B-page 531 PIC16(L)F1777/8/9 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 k 2047 Operands: None Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<6:3>) PC<14:11> Operation: Status Affected: None 00h WDT 0 WDT prescaler, 1 TO 1 PD Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The 11-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a 2-cycle instruction. Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. CALLW Subroutine Call With W COMF Complement f Syntax: [ label ] CALLW Syntax: [ label ] COMF Operands: None Operands: Operation: (PC) +1 TOS, (W) PC<7:0>, (PCLATH<6:0>) PC<14:8> 0 f 127 d [0,1] Operation: (f) (destination) Status Affected: Z Description: The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. DECF Decrement f Syntax: [ label ] DECF f,d Status Affected: None Description: Subroutine call with W. First, the return address (PC + 1) is pushed onto the return stack. Then, the contents of W is loaded into PC<7:0>, and the contents of PCLATH into PC<14:8>. CALLW is a 2-cycle instruction. CLRF Clear f Syntax: [ label ] CLRF f f,d Operands: 0 f 127 Operands: Operation: 00h (f) 1Z 0 f 127 d [0,1] Operation: (f) - 1 (destination) Status Affected: Z Status Affected: Z Description: The contents of register `f' are cleared and the Z bit is set. Description: Decrement register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h (W) 1Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set. DS40001819B-page 532 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register `f' are decremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', then a NOP is executed instead, making it a 2-cycle instruction. Description: The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', a NOP is executed instead, making it a 2-cycle instruction. GOTO Unconditional Branch IORLW Inclusive OR literal with W Syntax: [ label ] Syntax: [ label ] GOTO k INCFSZ f,d IORLW k Operands: 0 k 2047 Operands: 0 k 255 Operation: k PC<10:0> PCLATH<6:3> PC<14:11> Operation: (W) .OR. k (W) Status Affected: Z Status Affected: None Description: Description: GOTO is an unconditional branch. The 11-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a 2-cycle instruction. The contents of the W register are OR'ed with the 8-bit literal `k'. The result is placed in the W register. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] Operands: 0 f 127 d [0,1] Syntax: [ label ] Operands: 0 f 127 d [0,1] INCF f,d Operation: (f) + 1 (destination) Operation: (W) .OR. (f) (destination) Status Affected: Z Status Affected: Z Description: The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. Description: Inclusive OR the W register with register `f'. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. 2015-2016 Microchip Technology Inc. IORWF f,d DS40001819B-page 533 PIC16(L)F1777/8/9 LSLF Logical Left Shift MOVF f {,d} Move f Syntax: [ label ] LSLF Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f<7>) C (f<6:0>) dest<7:1> 0 dest<0> Operation: (f) (dest) Status Affected: C, Z Description: The contents of register `f' are shifted one bit to the left through the Carry flag. A `0' is shifted into the LSb. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f'. C register f 0 Status Affected: Z Description: The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. Words: 1 Cycles: 1 Example: Logical Right Shift Syntax: [ label ] LSRF Operands: 0 f 127 d [0,1] Operation: 0 dest<7> (f<7:1>) dest<6:0>, (f<0>) C, Status Affected: C, Z Description: The contents of register `f' are shifted one bit to the right through the Carry flag. A `0' is shifted into the MSb. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f'. DS40001819B-page 534 f {,d} register f MOVF FSR, 0 After Instruction W = value in FSR register Z = 1 LSRF 0 MOVF f,d C 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 MOVIW Move INDFn to W Syntax: [ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn] Operands: n [0,1] mm [00,01, 10, 11] -32 k 31 Operation: INDFn W Effective address is determined by * FSR + 1 (preincrement) * FSR - 1 (predecrement) * FSR + k (relative offset) After the Move, the FSR value will be either: * FSR + 1 (all increments) * FSR - 1 (all decrements) * Unchanged Status Affected: MOVLP Syntax: [ label ] MOVLP k Operands: 0 k 127 Operation: k PCLATH Status Affected: None Description: The 7-bit literal `k' is loaded into the PCLATH register. MOVLW Move literal to W Syntax: [ label ] Operands: 0 k 255 k (W) Status Affected: None Description: The 8-bit literal `k' is loaded into W register. The "don't cares" will assemble as `0's. Words: 1 1 Mode Syntax mm Cycles: Preincrement ++FSRn 00 Example: --FSRn 01 Postincrement FSRn++ 10 Postdecrement FSRn-- 11 Description: This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it. Note: The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the FSRn. FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap-around. MOVLB Move literal to BSR Syntax: [ label ] MOVLB k Operands: 0 k 31 Operation: k BSR Status Affected: None Description: The 5-bit literal `k' is loaded into the Bank Select Register (BSR). 2015-2016 Microchip Technology Inc. MOVLW k Operation: Z Predecrement Move literal to PCLATH MOVLW 0x5A After Instruction W = MOVWF Move W to f Syntax: [ label ] MOVWF Operands: 0 f 127 Operation: (W) (f) 0x5A f Status Affected: None Description: Move data from W register to register `f'. Words: 1 Cycles: 1 Example: MOVWF OPTION_REG Before Instruction OPTION_REG = 0xFF W = 0x4F After Instruction OPTION_REG = 0x4F W = 0x4F DS40001819B-page 535 PIC16(L)F1777/8/9 MOVWI Move W to INDFn Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn [ label ] MOVWI FSRn++ [ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn] Operands: Operation: Status Affected: n [0,1] mm [00,01, 10, 11] -32 k 31 W INDFn Effective address is determined by * FSR + 1 (preincrement) * FSR - 1 (predecrement) * FSR + k (relative offset) After the Move, the FSR value will be either: * FSR + 1 (all increments) * FSR - 1 (all decrements) Unchanged None No Operation Syntax: [ label ] Operands: None Operation: No operation Status Affected: None No operation. Words: 1 Cycles: 1 Example: NOP OPTION Load OPTION_REG Register with W Syntax: [ label ] OPTION Operands: None Operation: (W) OPTION_REG Status Affected: None Description: Move data from W register to OPTION_REG register. 1 Syntax Preincrement ++FSRn 00 Predecrement --FSRn 01 Postincrement FSRn++ 10 Words: Postdecrement FSRn-- 11 Cycles: 1 Example: OPTION Before Instruction OPTION_REG = 0xFF W = 0x4F After Instruction OPTION_REG = 0x4F W = 0x4F This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it. Note: The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the FSRn. FSRn is limited to the range 0000h-FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap-around. The increment/decrement operation on FSRn WILL NOT affect any Status bits. DS40001819B-page 536 NOP Description: Mode Description: mm NOP RESET Software Reset Syntax: [ label ] RESET Operands: None Operation: Execute a device Reset. Resets the RI flag of the PCON register. Status Affected: None Description: This instruction provides a way to execute a hardware Reset by software. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 RETFIE Return from Interrupt Syntax: [ label ] RETFIE k RETURN Return from Subroutine Syntax: [ label ] None RETURN Operands: None Operands: Operation: TOS PC, 1 GIE Operation: TOS PC Status Affected: None Status Affected: None Description: Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a 2-cycle instruction. Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a 2-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = GIE = TOS 1 RETLW Return with literal in W Syntax: [ label ] Operands: 0 k 255 Operation: k (W); TOS PC Status Affected: None Description: The W register is loaded with the 8-bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a 2-cycle instruction. Words: 1 Cycles: 2 Example: TABLE RETLW k RLF Rotate Left f through Carry Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: See description below Status Affected: C Description: The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is stored back in register `f'. RLF C CALL TABLE;W contains table ;offset value * ;W now has table value * * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table Before Instruction W = After Instruction W = 2015-2016 Microchip Technology Inc. Words: 1 Cycles: 1 Example: RLF f,d Register f REG1,0 Before Instruction REG1 C After Instruction REG1 W C = = 1110 0110 0 = = = 1110 0110 1100 1100 1 0x07 value of k8 DS40001819B-page 537 PIC16(L)F1777/8/9 SUBLW Subtract W from literal Syntax: [ label ] RRF Rotate Right f through Carry Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: Description: The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. The W register is subtracted (2's complement method) from the 8-bit literal `k'. The result is placed in the W register. RRF f,d C SUBLW k Operands: 0 k 255 Operation: k - (W) W) Register f C=0 Wk C=1 Wk DC = 0 W<3:0> k<3:0> DC = 1 W<3:0> k<3:0> SLEEP Enter Sleep mode SUBWF Subtract W from f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] SLEEP Operands: None Operation: 00h WDT, 0 WDT prescaler, 1 TO, 0 PD Status Affected: TO, PD Description: The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. DS40001819B-page 538 SUBWF f,d Operation: (f) - (W) destination) Status Affected: C, DC, Z Description: Subtract (2's complement method) W register from register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f. C=0 Wf C=1 Wf DC = 0 W<3:0> f<3:0> DC = 1 W<3:0> f<3:0> SUBWFB Subtract W from f with Borrow Syntax: SUBWFB Operands: 0 f 127 d [0,1] Operation: (f) - (W) - (B) dest f {,d} Status Affected: C, DC, Z Description: Subtract W and the BORROW flag (CARRY) from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 255 (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR'ed with the 8-bit literal `k'. The result is placed in the W register. Operation: SWAPF f,d Status Affected: None Description: The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed in register `f'. XORWF TRIS Load TRIS Register with W XORLW k Exclusive OR W with f Syntax: [ label ] Operands: 0 f 127 d [0,1] XORWF f,d (W) .XOR. (f) destination) Syntax: [ label ] TRIS f Operands: 5f7 Operation: Operation: (W) TRIS register `f' Status Affected: Z Status Affected: None Description: Description: Move data from W register to TRIS register. When `f' = 5, TRISA is loaded. When `f' = 6, TRISB is loaded. When `f' = 7, TRISC is loaded. Exclusive OR the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. 2015-2016 Microchip Technology Inc. DS40001819B-page 539 PIC16(L)F1777/8/9 36.0 ELECTRICAL SPECIFICATIONS 36.1 Absolute Maximum Ratings() Ambient temperature under bias ...................................................................................................... -40C to +125C Storage temperature ........................................................................................................................ -65C to +150C Voltage on pins with respect to VSS on VDD pin PIC16F1777/8/9 ........................................................................................................ -0.3V to +6.5V PIC16LF1777/8/9 ...................................................................................................... -0.3V to +4.0V on MCLR pin ........................................................................................................................... -0.3V to +9.0V on all other pins ............................................................................................................ -0.3V to (VDD + 0.3V) Maximum current on VSS pin(1) -40C TA +85C .............................................................................................................. 350 mA -40C TA +125C ............................................................................................................ 120 mA on VDD pin(1) PIC16(L)F1778 only -40C TA +85C .............................................................................................................. 250 mA -40C TA +125C .............................................................................................................. 85 mA on VDD pin(1) PIC16(L)F1777/9 only -40C TA +85C .............................................................................................................. 350 mA -40C TA +125C ............................................................................................................ 120 mA Sunk by any standard I/O pin ............................................................................................................... 50 mA Sourced by any standard I/O pin .......................................................................................................... 50 mA Sunk by any High Current I/O pin ....................................................................................................... 100 mA Sourced by any High Current I/O pin .................................................................................................. 100 mA Sourced by any Op Amp output pin .................................................................................................... 100 mA Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA Total power dissipation(2) ...............................................................................................................................800 mW Note 1: 2: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be limited by the device package power dissipation characterizations, see Table 36-6: Thermal Characteristics to calculate device specifications. Power dissipation is calculated as follows: Pdis = VDD* {Idd- Ioh} + {VDD-Voh)*Ioh} + (Vol*IoI). NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. DS40001819B-page 540 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 36.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: Operating Temperature: VDDMIN VDD VDDMAX TA_MIN TA TA_MAX VDD -- Operating Supply Voltage(1) PIC16LF1777/8/9 VDDMIN (Fosc 16 MHz) ......................................................................................................... +1.8V VDDMIN (Fosc 16 MHz) ......................................................................................................... +2.5V VDDMAX .................................................................................................................................... +3.6V PIC16F1777/8/9 VDDMIN (Fosc 16 MHz) ......................................................................................................... +2.3V VDDMIN (Fosc 16 MHz).......................................................................................................... +2.5V VDDMAX .................................................................................................................................... +5.5V TA -- Operating Ambient Temperature Range Industrial Temperature TA_MIN ...................................................................................................................................... -40C TA_MAX .................................................................................................................................... +85C Extended Temperature TA_MIN ...................................................................................................................................... -40C TA_MAX .................................................................................................................................. +125C Note 1: See Parameter D001, DS Characteristics: Supply Voltage. 2015-2016 Microchip Technology Inc. DS40001819B-page 541 PIC16(L)F1777/8/9 VOLTAGE FREQUENCY GRAPH, -40C TA +125C, PIC16F1777/8/9 ONLY FIGURE 36-1: VDD (V) 5.5 2.5 2.3 0 10 4 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 36-7 for each Oscillator mode's supported frequencies. VOLTAGE FREQUENCY GRAPH, -40C TA +125C, PIC16LF1777/8/9 ONLY VDD (V) FIGURE 36-2: 3.6 2.5 1.8 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 36-7 for each Oscillator mode's supported frequencies. DS40001819B-page 542 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 36.3 DC Characteristics TABLE 36-1: SUPPLY VOLTAGE PIC16LF1777/8/9 Standard Operating Conditions (unless otherwise stated) PIC16F1777/8/9 Param. No. D001 Sym. VDD Characteristic PIC16F1777/8/9 VDR Max. Units Conditions VDDMIN 1.8 2.5 -- -- VDDMAX 3.6 3.6 V V FOSC 16 MHz FOSC 32 MHz 2.3 2.5 -- -- 5.5 5.5 V V FOSC 16 MHz FOSC 32 MHz 1.5 -- -- V Device in Sleep mode 1.7 -- -- V Device in Sleep mode -- 1.6 -- V -- 1.6 -- V V RAM Data Retention Voltage(1) D002* D002A* VPOR Typ Supply Voltage D001 D002* Min. Power-on Reset Release Voltage D002A* D002B* VPORR* Power-on Reset Rearm Voltage(2) -- 0.8 -- D002B* -- 1.5 -- V D003 VFVR Fixed Voltage Reference Voltage(3) -4 -4 -7 -- -- -- +4 +4 +7 % % % D004* SVDD VDD Rise Rate 0.05 -- -- V/ms 1x gain, 1.024, VDD 2.5V, -40C to +85C 2x gain, 2.048, VDD 2.5V, -40C to +85C 4x gain, 4.096, VDD 4.5V, -40C to +85C Ensures that the Power-on Reset signal is released properly. * Note These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: See Figure 36-3: POR and POR Rearm with Slow Rising VDD. 3: Industrial temperature range only. 2015-2016 Microchip Technology Inc. DS40001819B-page 543 PIC16(L)F1777/8/9 FIGURE 36-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR SVDD VSS NPOR(1) POR REARM VSS TVLOW(2) Note 1: 2: 3: DS40001819B-page 544 TPOR(3) When NPOR is low, the device is held in Reset. TVLOW 1 s typical. TPOR 2.7 s typical. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 36-2: SUPPLY CURRENT (IDD)(1,2) PIC16LF1777/8/9 Standard Operating Conditions (unless otherwise stated) PIC16F1777/8/9 Param No. Device Characteristics LDO Regulator D009 D010 D010 D012 D012 D014 D014 D015 D015 Note 1: 2: 3: 4: 5: Conditions Min. Typ Max. Units Note VDD -- 75 -- A -- High-Power mode, normal operation -- 15 -- A -- Sleep, VREGCON<1> = 0 -- 0.3 -- A -- Sleep, VREGCON<1> = 1 -- 8 25 A 1.8 -- 12 30 A 3.0 FOSC = 32 kHz, LP Oscillator mode (Note 4), -40C TA +85C -- 21 30 A 2.3 -- 25 34 A 3.0 -- 26 35 A 5.0 -- 210 440 A 1.8 -- 390 620 A 3.0 -- 320 530 A 2.3 -- 430 680 A 3.0 -- 530 790 A 5.0 -- 170 380 A 1.8 -- 320 550 A 3.0 -- 250 513 A 2.3 -- 360 645 A 3.0 -- 430 735 A 5.0 -- 2.5 3.8 mA 3.0 -- 3.1 4.0 mA 3.6 -- 2.5 4.3 mA 3.0 -- 2.7 4.6 mA 5.0 FOSC = 32 kHz, LP Oscillator mode (Note 4,5) -40C TA +85C FOSC = 4 MHz, XT Oscillator mode FOSC = 4 MHz, XT Oscillator mode (Note 5) FOSC = 4 MHz, External Clock (ECM), Medium Power mode FOSC = 4 MHz, External Clock (ECM), Medium Power mode FOSC = 32 MHz, External Clock (ECH), High-Power mode (Note 5) FOSC = 32 MHz, External Clock (ECH), High-Power mode (Note 5) Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. For EXTRC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k FVR and BOR are disabled. 8 MHz crystal/oscillator with 4x PLL enabled. 2015-2016 Microchip Technology Inc. DS40001819B-page 545 PIC16(L)F1777/8/9 TABLE 36-2: SUPPLY CURRENT (IDD)(1,2) (CONTINUED) PIC16LF1777/8/9 Standard Operating Conditions (unless otherwise stated) PIC16F1777/8/9 Param No. Device Characteristics D017 D017 D019 D019 D020 D020 D022 D022 Note 1: 2: 3: 4: 5: Conditions Min. Typ Max. Units Note VDD -- 115 190 A 1.8 -- 145 320 A 3.0 -- 160 215 A 2.3 -- 180 340 A 3.0 -- 230 420 A 5.0 -- 0.9 1.5 mA 1.8 -- 1.5 2.3 mA 3.0 -- 1.2 2.0 mA 2.3 -- 1.5 2.5 mA 3.0 -- 1.7 2.6 mA 5.0 -- 2.9 4.2 mA 3.0 -- 3.5 4.3 mA 3.6 -- 2.9 4.2 mA 3.0 -- 3.0 5.0 mA 5.0 -- 2.8 4 mA 3.0 -- 3.4 4.7 mA 3.6 -- 2.9 4 mA 3.0 -- 3.1 4.5 mA 5.0 FOSC = 500 kHz, MFINTOSC mode FOSC = 500 kHz, MFINTOSC mode FOSC = 16 MHz, HFINTOSC mode FOSC = 16 MHz, HFINTOSC mode FOSC = 32 MHz, HFINTOSC mode (Note 5) FOSC = 32 MHz, HFINTOSC mode (Note 5) FOSC = 32 MHz, HS Oscillator mode (Note 5) FOSC = 32 MHz HS Oscillator mode (Note 5) Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. For EXTRC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k FVR and BOR are disabled. 8 MHz crystal/oscillator with 4x PLL enabled. DS40001819B-page 546 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 36-3: POWER-DOWN CURRENTS (IPD)(1,2) PIC16LF1777/8/9 Operating Conditions: (unless otherwise stated) Low-Power Sleep Mode PIC16F1777/8/9 Low-Power Sleep Mode, VREGPM = 1 Param No. Device Characteristics D023 Base IPD D023 Base IPD D023A Base IPD D024 D024 D025 D025 D025A D025A Min. Typ Max. +85C Conditions Max. +125C Units VDD -- 0.05 1.0 8.0 A 1.8 -- 0.08 2.0 9.0 A 3.0 -- 0.3 2.4 10 A 2.3 -- 0.4 4 12 A 3.0 -- 0.5 6 15 A 5.0 -- 9.8 17 28 A 2.3 -- 10.3 20 40 A 3.0 -- 11.5 22 44 A 5.0 -- 0.5 6 14 A 1.8 -- 0.8 7 17 A 3.0 -- 0.8 6 15 A 2.3 -- 0.9 7 20 A 3.0 -- 1.0 8 22 A 5.0 -- 15 28 30 A 1.8 -- 24 35 38 A 3.0 -- 18 33 35 A 2.3 -- 24 35 40 A 3.0 -- 26 37 44 A 5.0 -- 25 50 55 A 1.8 -- 30 65 70 A 3.0 -- 30 55 66 A 2.3 -- 32 68 82 A 3.0 Note WDT, BOR, FVR, and SOSC disabled, all Peripherals Inactive WDT, BOR, FVR, and SOSC disabled, all Peripherals Inactive, Low-Power Sleep mode WDT, BOR, FVR and SOSC disabled, all Peripherals inactive, Normal Power Sleep mode VREGPM = 0 WDT Current WDT Current FVR Current (ADC) FVR Current (ADC) FVR Current (DAC) FVR Current (DAC) -- 35 77 90 A 5.0 D026 -- 7.5 25 28 A 3.0 BOR Current D026 -- 10 25 28 A 3.0 BOR Current -- 12 28 31 A 5.0 D027 -- 0.5 4 10 A 3.0 LPBOR Current D027 -- 0.8 6 15 A 3.0 LPBOR Current -- 1 8 17 A 5.0 -- 0.5 5 9 A 1.8 -- 0.8 8.5 12 A 3.0 -- 1.1 6 10 A 2.3 -- 1.3 8.5 20 A 3.0 -- 1.4 10 25 A 5.0 D028 D028 * Note 1: 2: 3: SOSC Current SOSC Current These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS. ADC clock source is FRC. 2015-2016 Microchip Technology Inc. DS40001819B-page 547 PIC16(L)F1777/8/9 TABLE 36-3: POWER-DOWN CURRENTS (IPD)(1,2) (CONTINUED) PIC16LF1777/8/9 Operating Conditions: (unless otherwise stated) Low-Power Sleep Mode PIC16F1777/8/9 Low-Power Sleep Mode, VREGPM = 1 Param No. Device Characteristics D029 D029 D030 D030 Conditions Min. Typ Max. +85C Max. +125C Units -- 0.05 2 9 A 1.8 -- 0.08 3 10 A 3.0 -- 0.3 4 12 A 2.3 -- 0.4 5 13 A 3.0 -- 0.5 7 16 A 5.0 -- 250 -- -- A 1.8 -- 250 -- -- A 3.0 -- 280 -- -- A 2.3 -- 280 -- -- A 3.0 VDD Note ADC Current (Note 3), no conversion in progress ADC Current (Note 3), no conversion in progress ADC Current (Note 3), conversion in progress ADC Current (Note 3), conversion in progress -- 280 -- -- A 5.0 D031 -- 250 650 -- A 3.0 Op Amp (High power) D031 -- 250 650 -- A 3.0 Op Amp (High power) -- 350 850 -- A 5.0 -- 250 600 -- A 1.8 -- 300 650 -- A 3.0 -- 280 600 -- A 2.3 -- 300 650 -- A 3.0 -- 310 650 -- A 5.0 D032 D032 * Note 1: 2: 3: Comparator, CxSP = 0 Comparator, CxSP = 0 VREGPM = 0 These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS. ADC clock source is FRC. DS40001819B-page 548 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 36-4: I/O PORTS Standard Operating Conditions (unless otherwise stated) Param No. Sym. VIL Characteristic Min. Typ Max. Units Conditions Input Low Voltage I/O PORT: D034 with TTL buffer D034A D035 -- -- 0.8 V 4.5V VDD 5.5V -- -- 0.15 VDD V 1.8V VDD 4.5V 2.0V VDD 5.5V with Schmitt Trigger buffer -- -- 0.2 VDD V with I2C levels -- -- 0.3 VDD V with SMBus levels -- -- 0.8 V 2.7V VDD 5.5V D036 MCLR, OSC1 (EXTRC mode) -- -- 0.2 VDD V (Note 1) D036A OSC1 (HS mode) -- -- 0.3 VDD V VIH Input High Voltage I/O ports: D040 2.0 -- -- V 4.5V VDD 5.5V 0.25 VDD + 0.8 -- -- V 1.8V VDD 4.5V with Schmitt Trigger buffer 0.8 VDD -- -- V 2.0V VDD 5.5V with I2C levels 0.7 VDD -- -- V with TTL buffer D040A D041 with SMBus levels D042 MCLR 2.1 -- -- V 0.8 VDD -- -- V 2.7V VDD 5.5V D043A OSC1 (HS mode) 0.7 VDD -- -- V D043B OSC1 (EXTRC oscillator) 0.9 VDD -- -- V VDD 2.0V (Note 1) -- 5 125 nA VSS VPIN VDD, Pin at high-impedance, 85C -- 5 1000 nA VSS VPIN VDD, Pin at high-impedance, 125C -- 5 200 nA VSS VPIN VDD, Pin at high-impedance, 85C 25 100 200 A VDD = 3.3V, VPIN = VSS -- -- 0.6 V IOL = 8mA, VDD = 5V IOL = 6mA, VDD = 3.3V IOL = 1.8mA, VDD = 1.8V -- -- -- -- 0.6 0.6 0.6 -- -- V V V IOH = 10mA, VDD = 2.3V, HIDCX = 1 IOH = 32mA, VDD = 3.0V, HIDCX = 1 IOH = 51mA, VDD = 5.0V, HIDCX = 1 VDD - 0.7 -- -- V IOH = 3.5mA, VDD = 5V IOH = 3mA, VDD = 3.3V IOH = 1mA, VDD = 1.8V VDD - 0.7 -- -- -- VDD - 0.7 VDD - 0.7 -- -- -- V V V IOH = 10mA, VDD = 2.3V, HIDCX = 1 IOH = 37mA, VDD = 3.0V, HIDCX = 1 IOH = 54mA, VDD = 5.0V, HIDCX = 1 IIL D060 Input Leakage Current(2) I/O Ports MCLR(3) D061 IPUR Weak Pull-up Current VOL Output Low Voltage(4) D070* D080 Standard I/O ports D080A High Drive I/O ports VOH D090 Output High Voltage(4) Standard I/O ports D090A * Note 1: 2: 3: 4: High Drive I/O ports These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in EXTRC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Including OSC2 in CLKOUT mode. 2015-2016 Microchip Technology Inc. DS40001819B-page 549 PIC16(L)F1777/8/9 TABLE 36-4: I/O PORTS (CONTINUED) (CONTINUED) Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ Max. Units -- -- 15 pF -- -- 50 pF Conditions Capacitive Loading Specs on Output Pins D101* COSC2 OSC2 pin D101A* CIO * Note 1: 2: 3: 4: All I/O pins In XT, HS and LP modes when external clock is used to drive OSC1 These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in EXTRC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Including OSC2 in CLKOUT mode. DS40001819B-page 550 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 36-5: MEMORY PROGRAMMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ Max. Units Conditions Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP pin 8.0 -- 9.0 V D111 IDDP Supply Current during Programming -- -- 10 mA D112 VBE VDD for Bulk Erase D113 VPEW VDD for Write or Row Erase D114 2.7 -- VDDMAX V VDDMIN -- VDDMAX V IPPPGM Current on MCLR/VPP during Erase/Write -- 1.0 -- mA D115 IDDPGM Current on VDD during Erase/Write -- 5.0 -- mA D121 EP Cell Endurance 10K -- -- E/W (Note 2, Note 3) Program Flash Memory -40C TA +85C (Note 1) D122 VPRW VDD for Read/Write VDDMIN -- VDDMAX V D123 TIW Self-timed Write Cycle Time -- 2 2.5 ms D124 TRETD Characteristic Retention -- 40 -- Year Provided no other specifications are violated D125 EHEFC High-Endurance Flash Cell 100K -- -- E/W -0C TA +60C, Lower byte last 128 addresses Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Self-write and Block Erase. 2: Required only if single-supply programming is disabled. 3: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the ICD 2 VPP voltage must be placed between the ICD 2 and target system when programming or debugging with the ICD 2. 2015-2016 Microchip Technology Inc. DS40001819B-page 551 PIC16(L)F1777/8/9 TABLE 36-6: THERMAL CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param No. TH01 TH02 TH03 TH04 TH05 Sym. Characteristic JA Thermal Resistance Junction to Ambient JC TJMAX PD Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Typ. Units Conditions 60.0 C/W 28-pin SPDIP package 80.0 C/W 28-pin SOIC package 90.0 C/W 28-pin SSOP package 48 C/W 28-pin UQFN 4x4mm package 47.2 C/W 40-pin PDIP package 46.0 C/W 44-pin TQFP package 41.0 C/W 40-pin UQFN 5x5mm package 31.4 C/W 28-pin SPDIP package 24 C/W 28-pin SOIC package 24 C/W 28-pin SSOP package 12 C/W 28-pin UQFN 4x4mm package 24.70 C/W 40-pin PDIP package 14.5 C/W 44-pin TQFP package 40-pin UQFN 5x5mm package 5.5 C/W 150 C -- W PD = PINTERNAL + PI/O -- W PINTERNAL = IDD x VDD(1) TH06 PI/O I/O Power Dissipation -- W PI/O = (IOL * VOL) + (IOH * (VDD - VOH)) TH07 PDER Derated Power -- W PDER = PDMAX (TJ - TA)/JA(2) Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature, TJ = Junction Temperature DS40001819B-page 552 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 36.4 AC Characteristics Timing Parameter Symbology has been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O PORT mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low FIGURE 36-4: T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid High-impedance LOAD CONDITIONS Rev. 10-000133A 8/1/2013 Load Condition Pin CL VSS Legend: CL=50 pF for all pins 2015-2016 Microchip Technology Inc. DS40001819B-page 553 PIC16(L)F1777/8/9 FIGURE 36-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS12 OS02 OS11 OS03 CLKOUT (CLKOUT Mode) Note 1: See Table 36-10. TABLE 36-7: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param No. OS01 Sym. FOSC Characteristic Min. Typ Max. Units External CLKIN Frequency(1) DC DC -- -- 0.5 4 MHz MHz DC -- 32 MHz Conditions External Clock (ECL) External Clock (ECM) External Clock (ECH) -- 32.768 -- kHz LP Oscillator 0.1 -- 4 MHz XT Oscillator 1 -- 4 MHz HS Oscillator 1 -- 20 MHz HS Oscillator, VDD > 2.7V DC -- 4 MHz EXTRC, VDD > 2.0V OS02 TOSC External CLKIN Period(1) 27 -- s LP Oscillator 250 -- ns XT Oscillator 50 -- ns HS Oscillator 50 -- ns External Clock (EC) Oscillator Period(1) -- 30.5 -- s LP Oscillator 250 -- 10,000 ns XT Oscillator 50 -- 1,000 ns HS Oscillator 31.25 -- -- ns EXTRC OS03 TCY Instruction Cycle Time(1) 125 TCY DC ns TCY = 4/FOSC OS04* TosH, External CLKIN High, 2 -- -- s LP Oscillator TosL External CLKIN Low 100 -- -- ns XT Oscillator 20 -- -- ns HS Oscillator OS05* TosR, External CLKIN Rise, 0 -- ns LP Oscillator TosF External CLKIN Fall 0 -- ns XT Oscillator 0 -- ns HS Oscillator * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. Oscillator Frequency(1) DS40001819B-page 554 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 36-8: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Freq. Tolerance Min. Typ Max. Units Conditions OS08 HFOSC Internal Calibrated HFINTOSC Frequency(1) 2% -- 16.0 -- MHz VDD = 3.0V, TA = 25C, (Note 2) OS08A MFOSC Internal Calibrated MFINTOSC Frequency(1) 2% -- 500 -- kHz VDD = 3.0V, TA = 25C, (Note 2) OS09 LFOSC Internal LFINTOSC Frequency -- -- 31 -- kHz -40C TA +125C OS10* TWARM HFINTOSC Wake-up from Sleep Start-up Time -- -- 3.2 8 s MFINTOSC Wake-up from Sleep Start-up Time -- -- 24 35 s TLFOSC ST LFINTOSC Wake-up from Sleep Start-up Time -- -- 0.5 -- ms * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 2: See Figure 36-6: HFINTOSC Frequency Accuracy Over Device VDD and Temperature, Figure 37-75: Wake From Sleep, VREGPM = 0., and Figure 36-6: HFINTOSC Frequency Accuracy Over Device VDD and Temperature. 3: See Figure 37-58: LFINTOSC Frequency, PIC16LF1777/8/9 Only., and Figure 37-59: LFINTOSC Frequency, PIC16F1777/8/9 Only.. HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE FIGURE 36-6: 125 5% 85 Temperature (C) 3% 60 2% 25 0 -20 -40 1.8 5% 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2015-2016 Microchip Technology Inc. DS40001819B-page 555 PIC16(L)F1777/8/9 TABLE 36-9: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param No. Sym. F10 Characteristic Min. Typ Max. Units FOSC Oscillator Frequency Range 4 -- 8 MHz F11 FSYS On-Chip VCO System Frequency 16 -- 32 MHz F12 TRC PLL Start-up Time (Lock Time) F13* CLK CLKOUT Stability (Jitter) -- -- 2 ms -0.25% -- +0.25% % Conditions * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40001819B-page 556 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 36-7: Cycle CLKOUT AND I/O TIMING Write Fetch Q1 Q4 Read Execute Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 36-10: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ Max. Units Conditions OS11 TosH2ckL FOSC to CLKOUT (1) -- -- 70 ns 3.3V VDD 5.0V OS12 TosH2ckH FOSC to CLKOUT (1) -- -- 72 ns 3.3V VDD 5.0V OS13 TckL2ioV CLKOUT to Port out valid OS14 TioV2ckH Port input valid before CLKOUT(1) OS15 TosH2ioV OS16 (1) -- -- 20 ns TOSC + 200 ns -- -- ns Fosc (Q1 cycle) to Port out valid -- 50 70* ns 3.3V VDD 5.0V TosH2ioI Fosc (Q2 cycle) to Port input invalid (I/O in hold time) 50 -- -- ns 3.3V VDD 5.0V OS17 TioV2osH Port input valid to Fosc(Q2 cycle) (I/O in setup time) 20 -- -- ns OS18* TioR Port output rise time(2) -- -- 40 15 72 32 ns VDD = 1.8V 3.3V VDD 5.0V OS19* TioF Port output fall time(2) -- -- 28 15 55 30 ns VDD = 1.8V 3.3V VDD 5.0V OS20* Tinp INT pin input high or low time 25 -- -- ns OS21* Tioc Interrupt-on-change new input level time 25 -- -- ns * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. Note 1: Measurements are taken in EXTRC mode where CLKOUT output is 4 x TOSC. 2: Slew rate limited. 2015-2016 Microchip Technology Inc. DS40001819B-page 557 PIC16(L)F1777/8/9 FIGURE 36-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR PWRT Time-out 33 32 OSC Start-up Time Internal Reset(1) Watchdog Timer Reset(1) 34 31 34 I/O pins Note 1: Asserted low. DS40001819B-page 558 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 36-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ Max. Units 2 -- -- s 10 16 27 ms Conditions 30 TMCL 31 TWDTLP Low-Power Watchdog Timer Time-out Period 32 TOST Oscillator Start-up Timer Period(1) -- 1024 -- Tosc 33* TPWRT Power-up Timer Period, PWRTE = 0 40 65 140 ms 34* TIOZ I/O high-impedance from MCLR Low or Watchdog Timer Reset -- -- 2.0 s 35 VBOR Brown-out Reset Voltage(2) 2.55 2.70 2.85 V BORV = 0 2.30 1.80 2.45 1.90 2.60 2.10 V V BORV = 1 (PIC16F1777/8/9) BORV = 1 (PIC16LF1777/8/9) 1.8 2.1 2.5 V LPBOR = 1 0 25 75 mV -40C TA +85C 1 3 35 s VDD VBOR MCLR Pulse Width (low) 35A VLPBOR Low-Power Brown-out 36* VHYST 37* TBORDC Brown-out Reset DC Response Time Brown-out Reset Hysteresis VDD = 3.3V-5V 1:512 Prescaler used * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency. 2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 2015-2016 Microchip Technology Inc. DS40001819B-page 559 PIC16(L)F1777/8/9 FIGURE 36-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 FIGURE 36-10: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset (due to BOR) 33(1) Note 1: The delay, (TPWRT) releasing Reset, only occurs when the Power-up Timer is enabled, (PWRTE = 0). DS40001819B-page 560 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 36-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. 40* Sym. TT0H Characteristic T0CKI High Pulse Width Min. No Prescaler With Prescaler TT0L 41* T0CKI Low Pulse Width No Prescaler With Prescaler Typ Max. Units 0.5 TCY + 20 -- -- ns 10 -- -- ns 0.5 TCY + 20 -- -- ns 10 -- -- ns Greater of: 20 or TCY + 40 N -- -- ns 42* TT0P T0CKI Period 45* TT1H T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler 0.5 TCY + 20 -- -- ns 15 -- -- ns Asynchronous 30 -- -- ns Synchronous, No Prescaler 0.5 TCY + 20 -- -- ns Synchronous, with Prescaler 15 -- -- ns Asynchronous 30 -- -- ns Greater of: 30 or (TCY + 40)*N -- -- ns TT1L 46* T1CKI Low Time 47* TT1P T1CKI Input Synchronous Period 48 FT1 Secondary Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN) 49* TCKEZTMR1 Delay from External Clock Edge to Timer Increment Asynchronous * 60 -- -- ns 32.4 32.768 33.1 kHz 2 TOSC -- 7 TOSC -- Conditions N = prescale value N = prescale value Timers in Sync mode These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2015-2016 Microchip Technology Inc. DS40001819B-page 561 PIC16(L)F1777/8/9 FIGURE 36-11: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCPx (Capture mode) CC01 CC02 CC03 Note: Refer to Figure 36-4 for load conditions. TABLE 36-13: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Param Sym. No. CC01* TccL Characteristic CCPx Input Low Time No Prescaler With Prescaler CC02* TccH CCPx Input High Time CC03* TccP CCPx Input Period No Prescaler With Prescaler * Min. Typ Max. Units 0.5TCY + 20 -- -- ns 20 -- -- ns 0.5TCY + 20 -- -- ns 20 -- -- ns (3TCY + 40)*N -- -- ns Conditions N = prescale value These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40001819B-page 562 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 36-12: CLC PROPAGATION TIMING CLCxINn CLC Input time CLCxINn CLC Input time LCx_in[n](1) LCx_in[n](1) CLC Module LCx_out(1) CLC Output time CLCx CLC Module LCx_out(1) CLC Output time CLCx CLC01 Note 1: CLC02 CLC03 See Figure 28-1 to identify specific CLC signals. TABLE 36-14: CONFIGURATION LOGIC CELL (CLC) CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param. No. Sym. Characteristic Min. Typ Max. Units Conditions CLC01* TCLCIN CLC input time -- 7 OS17 ns (Note 1) CLC02* TCLC CLC module input to output progagation time -- -- 24 12 -- -- ns ns VDD = 1.8V VDD > 3.6V -- OS18 -- ns (Note 1) -- OS19 -- ns (Note 1) -- 45 -- MHz CLC03* TCLCOUT CLC output time Rise Time Fall Time CLC04* FCLCMAX CLC maximum switching frequency * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: See Table 36-10 for OS17, OS18 and OS19 rise and fall times. 2015-2016 Microchip Technology Inc. DS40001819B-page 563 PIC16(L)F1777/8/9 TABLE 36-15: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1,2,3,4): Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25C, Single-ended, 2 s TAD, VREF+ = 3V, VREF- = VSS Param Sym. No. Characteristic Min. Typ Max. Units Conditions AD01 NR Resolution -- -- 10 AD02 EIL Integral Error -- -- 1.7 AD03 EDL Differential Error -- -- 1 AD04 EOFF Offset Error -- -- 2.5 LSb VREF = 3.0V AD05 EGN Gain Error -- -- 2.0 LSb VREF = 3.0V AD06 VREF Reference Voltage 1.8 -- VDD VSS -- VREF V -- -- 10 k AD07 VAIN Full-Scale Range AD08 ZAIN Recommended Impedance of Analog Voltage Source * Note 1: 2: 3: 4: bit LSb VREF = 3.0V LSb No missing codes, VREF = 3.0V V VREF = (VREF+ minus VREF-) Can go higher if external 0.01F capacitor is present on input pin. These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Total Absolute Error includes integral, differential, offset and gain errors. The ADC conversion result never decreases with an increase in the input voltage and has no missing codes. ADC VREF is from external VREF+ pin, VDD pin or FVR, whichever is selected as reference input. See Section 31.0 "DC and AC Characteristics Graphs and Charts" for operating characterization. TABLE 36-16: ADC CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param Sym. No. AD130* TAD AD131 TCNV Characteristic Min. Typ Max. Units Conditions ADC Clock Period (TADC) 1.0 -- 9.0 s FOSC-based ADC Internal FRC Oscillator Period (TFRC) 1.0 2.5 6.0 s ADCS<1:0> = 11 (ADC FRC mode) Conversion Time (not including Acquisition Time)(1) -- 13 -- TAD Set GO/DONE bit to conversion complete s AD132* TACQ Acquisition Time -- 5.0 -- AD133* THCD Holding Capacitor Disconnect Time -- 1/2 TAD -- ADCS<2:0> x11 (FOSC-based) -- 1/2 TAD + 1TCY -- ADCS<2:0> = x11 (FRC-based) * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following TCY cycle. DS40001819B-page 564 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 36-13: ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED) BSF ADCON0, GO AD133 1 TCY AD131 Q4 AD130 ADC_clk 9 ADC Data 8 7 6 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO Sample DONE Sampling Stopped AD132 FIGURE 36-14: ADC CONVERSION TIMING (ADC CLOCK FROM FRC) BSF ADCON0, GO AD133(1) 1 TCY AD131 Q4 AD130 ADC_clk 9 ADC Data 8 7 6 OLD_DATA ADRES 2 1 0 NEW_DATA 1 TCY ADIF GO Sample 3 DONE AD132 Sampling Stopped Note 1: If the ADC clock source is selected as FRC, a time of TCY is added before the ADC clock starts. This allows the SLEEP instruction to be executed. 2015-2016 Microchip Technology Inc. DS40001819B-page 565 PIC16(L)F1777/8/9 TABLE 36-17: OPERATIONAL AMPLIFIER (OPA) Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25C, OPAxSP = 1 (High GBWP mode) Param No. Symbol OPA01* GBWP Parameters Min. Typ. Max. Units Gain Bandwidth Product -- 3.5 -- MHz OPA02* TON Turn-on Time -- 10 -- s OPA03* PM Phase Margin -- 40 -- degrees OPA04* SR Slew Rate -- 3 -- V/s OPA05 OFF Offset -- 3 9 mV OPA06 CMRR Common-Mode Rejection Ratio 52 70 -- dB OPA07* AOL Open Loop Gain -- 90 -- dB OPA08 VICM Input Common-Mode Voltage 0 -- VDD V OPA09* PSRR Power Supply Rejection Ratio -- 80 -- dB HZ High-Impedance On/Off Time -- 50 -- ns OPA10* * Conditions VDD > 2.5V These parameters are characterized but not tested. TABLE 36-18: PROGRAMMABLE RAMP GENERATOR (PRG) SPECIFICATIONS Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25C (unless otherwise stated) Param No. Sym. Characteristics Min. Typ. Max. Units Comments PRG01 RRR Rising Ramp Rate(1) -- 1 -- V/s PRGxCON2 = 10h PRG02 FRR Falling Ramp Rate -- 1 -- V/s PRGxCON2 = 10h * Note 1: These parameters are characterized but not tested. Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. (1) TABLE 36-19: COMPARATOR SPECIFICATIONS Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25C See Section 31.0 "DC and AC Characteristics Graphs and Charts" for operating characterization. Param No. Sym. Characteristics Input Offset Voltage Min. Typ. Max. Units -- 2.5 5 mV CM01 VIOFF CM02 VICM Input Common-Mode Voltage 0 -- VDD V CM03 CMRR Common-Mode Rejection Ratio 40 50 -- dB Comments VICM = VDD/2 CM04A Response Time Rising Edge -- 60 125 ns CxSP = 1 CM04B Response Time Falling Edge -- 60 110 ns CxSP = 1 CM04C Tresp(1) CM04D Response Time Rising Edge -- 85 -- ns CxSP = 0 Response Time Falling Edge -- 85 -- ns CxSP = 0 Comparator Mode Change to Output Valid* -- -- 10 s 20 45 75 mV CM05 TMC2OV CM06 CHYSTER Comparator Hysteresis * Note 1: These parameters are characterized but not tested. Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. DS40001819B-page 566 CxHYS = 1 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 36-20: 10-BIT DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25C See Section 31.0 "DC and AC Characteristics Graphs and Charts" for operating characterization. Param No. DAC01* Sym. CLSB Characteristics Min. Typ. Max. Units -- VDD/1024 -- V Step Size DAC02 CINL Integral Error -- -- 2.0 LSb DAC03 CDNL Differential Error(2) -- -- 1 LSb DAC04 COFF Offset Error(2) -- -- 3 LSb DAC05 CGN Gain Error(2) -- -- 3 LSb (2) Comments For codes 0x004 to 0x3FB DAC06* CR Unit Resistor Value (R) -- 300 -- DAC07* CST Settling Time(1) -- -- 10 s * Note 1: 2: These parameters are characterized but not tested. Settling time measured while DACR<9:0> transitions from `0x000' to `0x3FF'. Buffered by op amp in unity gain. TABLE 36-21: 5-BIT DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25C See Section 31.0 "DC and AC Characteristics Graphs and Charts" for operating characterization. Param No. DAC10* Sym. CLSB Characteristics Min. Typ. Max. Units -- VDD/32 -- V Step Size DAC11 CACC Absolute -- -- 0.5 LSb DAC12* CR Unit Resistor Value (R) -- 6000 -- DAC13* CST Time(1) -- -- 10 s * Note 1: 2: These parameters are characterized but not tested. Settling time measured while DACR<4:0> transitions from `0x00' to `0x1F'. Buffered by op amp in unity gain. Settling Accuracy(2) Comments TABLE 36-22: ZERO CROSS PIN SPECIFICATIONS Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25C Param. No. Sym. Characteristics Min. Typ. Max. Units ZC01 ZCPINV Voltage on Zero Cross Pin -- 0.75 -- V ZC02 ZCDRV Maximum source or sink current -- -- 600 A ZC04 ZCISW ZC05 ZCOUT * Response Time Rising Edge -- 1 -- s Response Time Falling Edge -- 1 -- s Response Time Rising Edge -- 1 -- s Response Time Falling Edge -- 1 -- s Comments These parameters are characterized but not tested. 2015-2016 Microchip Technology Inc. DS40001819B-page 567 PIC16(L)F1777/8/9 FIGURE 36-15: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US122 US120 Note: Refer to Figure 36-4 for load conditions. TABLE 36-23: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol US120 TCKH2DTV US121 US122 Characteristic TCKRF TDTRF FIGURE 36-16: Min. Max. Units Conditions SYNC XMIT (Master and Slave) Clock high to data-out valid -- 80 ns 3.0V VDD 5.5V -- 100 ns 1.8V VDD 5.5V Clock out rise time and fall time (Master mode) -- 45 ns 3.0V VDD 5.5V -- 50 ns 1.8V VDD 5.5V Data-out rise time and fall time -- 45 ns 3.0V VDD 5.5V -- 50 ns 1.8V VDD 5.5V EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CK US125 DT US126 Note: Refer to Figure 36-4 for load conditions. TABLE 36-24: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol Characteristic US125 TDTV2CKL SYNC RCV (Master and Slave) Data-setup before CK (DT hold time) US126 TCKL2DTL Data-hold after CK (DT hold time) DS40001819B-page 568 Min. Max. Units 10 -- ns 15 -- ns Conditions 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 FIGURE 36-17: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS SP81 SCK (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 36-4 for load conditions. FIGURE 36-18: SPI MASTER MODE TIMING (CKE = 1, SMP = 1) SS SP81 SCK (CKP = 0) SP71 SP72 SP79 SP73 SCK (CKP = 1) SP80 SDO MSb bit 6 - - - - - -1 SP78 LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 36-4 for load conditions. 2015-2016 Microchip Technology Inc. DS40001819B-page 569 PIC16(L)F1777/8/9 FIGURE 36-19: SPI SLAVE MODE TIMING (CKE = 0) SS SP70 SCK (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 MSb SDO LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 36-4 for load conditions. FIGURE 36-20: SS SPI SLAVE MODE TIMING (CKE = 1) SP82 SP70 SP83 SCK (CKP = 0) SP71 SP72 SCK (CKP = 1) SP80 SDO MSb bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 36-4 for load conditions. DS40001819B-page 570 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 36-25: SPI MODE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param No. Symbol Characteristic Min. Typ Max. Units 2.25 TCY -- -- ns SP70* TSSL2SCH, TSSL2SCL SS to SCK or SCK input SP71* TSCH SCK input high time (Slave mode) TCY + 20 -- -- ns SCK input low time (Slave mode) TCY + 20 -- -- ns SP72* TSCL Conditions SP73* TDIV2SCH, TDIV2SCL Setup time of SDI data input to SCK edge 100 -- -- ns SP74* TSCH2DIL, TSCL2DIL Hold time of SDI data input to SCK edge 100 -- -- ns SP75* TDOR SDO data output rise time -- 10 25 ns 3.0V VDD 5.5V -- 25 50 ns 1.8V VDD 5.5V SP76* TDOF SDO data output fall time -- 10 25 ns SP77* TSSH2DOZ SS to SDO output high-impedance 10 -- 50 ns SP78* TSCR SCK output rise time (Master mode) -- 10 25 ns 3.0V VDD 5.5V -- 25 50 ns 1.8V VDD 5.5V SP79* TSCF SCK output fall time (Master mode) -- 10 25 ns SP80* TSCH2DOV, TSCL2DOV SDO data output valid after SCK edge -- -- 50 ns 3.0V VDD 5.5V 1.8V VDD 5.5V SP81* TDOV2SCH, SDO data output setup to SCK edge TDOV2SCL SP82* TSSL2DOV SDO data output valid after SS edge SP83* TSCH2SSH, TSCL2SSH SS after SCK edge -- -- 145 ns 1 Tcy -- -- ns -- -- 50 ns 1.5 TCY + 40 -- -- ns * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2015-2016 Microchip Technology Inc. DS40001819B-page 571 PIC16(L)F1777/8/9 I2C BUS START/STOP BITS TIMING FIGURE 36-21: SCL SP93 SP91 SP90 SP92 SDA Stop Condition Start Condition Note: Refer to Figure 36-4 for load conditions. TABLE 36-26: I2C BUS START/STOP BITS REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param No. Symbol Characteristic SP90* TSU:STA Start condition SP91* THD:STA SP92* TSU:STO SP93 THD:STO Stop condition 100 kHz mode 4700 Typ. Max. Units -- -- Setup time 400 kHz mode 600 -- -- Start condition 100 kHz mode 4000 -- -- Hold time 400 kHz mode 600 -- -- Stop condition 100 kHz mode 4700 -- -- Setup time Hold time * Min. 400 kHz mode 600 -- -- 100 kHz mode 4000 -- -- 400 kHz mode 600 -- -- Conditions ns Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated ns ns These parameters are characterized but not tested. FIGURE 36-22: I2C BUS DATA TIMING SP103 SCL SP100 SP90 SP102 SP101 SP106 SP107 SP91 SDA In SP92 SP110 SP109 SP109 SDA Out Note: Refer to Figure 36-4 for load conditions. DS40001819B-page 572 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 TABLE 36-27: I2C BUS DATA REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol SP100* THIGH Characteristic Clock high time Min. Max. Units 100 kHz mode 4.0 -- s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 -- s Device must operate at a minimum of 10 MHz 1.5TCY -- 100 kHz mode 4.7 -- s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 -- s Device must operate at a minimum of 10 MHz 1.5TCY -- SSP module SP101* TLOW Clock low time SSP module SP102* TR SP103* TF SDA and SCL rise time 100 kHz mode -- 1000 ns 400 kHz mode 20 + 0.1CB 300 ns SDA and SCL fall time 100 kHz mode -- 250 ns 400 kHz mode 20 + 0.1CB 250 ns 0 -- ns SP106* THD:DAT Data input hold time 100 kHz mode 400 kHz mode 0 0.9 s SP107* TSU:DAT Data input setup time 100 kHz mode 250 -- ns 400 kHz mode 100 -- ns SP109* TAA Output valid from clock 100 kHz mode -- 3500 ns 400 kHz mode -- -- ns SP110* Bus free time 100 kHz mode 4.7 -- s 400 kHz mode 1.3 -- s -- 400 pF SP111 * Note 1: 2: TBUF CB Conditions Bus capacitive loading CB is specified to be from 10-400 pF CB is specified to be from 10-400 pF (Note 2) (Note 1) Time the bus must be free before a new transmission can start These parameters are characterized but not tested. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. 2015-2016 Microchip Technology Inc. DS40001819B-page 573 PIC16(L)F1777/8/9 NOTES: DS40001819B-page 574 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 37.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Unless otherwise noted, all graphs apply to both the L and LF devices. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. "Typical" represents the mean of the distribution at 25C. "Maximum", "Max.", "Minimum" or "Min." represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over each temperature range. 2015-2016 Microchip Technology Inc. DS40001819B-page 575 PIC16(L)F1777/8/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. 35 16 Max: 85C + 3i Typical: 25C Max: 85C + 3i Typical: 25C 14 Max. 12 Typical Typical IDD (A) IDD (A) Max. 30 10 8 25 20 6 15 4 10 2 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.0 3.8 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 37-1: IDD, LP Oscillator Mode, Fosc = 32 kHz, PIC16LF1777/8/9 Only. FIGURE 37-2: IDD, LP Oscillator Mode, Fosc = 32 kHz, PIC16F1777/8/9 Only. 500 600 450 Typical: 25C 4 MHz XT Max: 85C + 3i 500 400 4 MHz XT 350 IDD (A) IDD (A) 400 300 250 200 300 1 MHz XT 1 MHz XT 200 150 100 100 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 0 3.8 1.6 1.8 2.0 2.2 2.4 VDD (V) 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 37-3: IDD Typical, XT and EXTRC Oscillator, PIC16LF1777/8/9 Only. FIGURE 37-4: IDD Maximum, XT and EXTRC Oscillator, PIC16LF1777/8/9 Only. 800 600 Max: 85C + 3i 4 MHz XT Typical: 25C 4 MHz XT 700 500 600 500 300 IDD (A) IDD (A) 400 1 MHz XT 400 1 MHz XT 300 200 200 100 100 0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 37-5: IDD Typical, XT and EXTRC Oscillator, PIC16F1777/8/9 Only. DS40001819B-page 576 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 37-6: IDD Maximum, XT and EXTRC Oscillator, PIC16F1777/8/9 Only. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. 12 26 Max: 85C + 3i Typical: 25C 10 Max. Max: 85C + 3i Typical: 25C 24 Max. 22 Typical 8 IDD (A) IDD (A) Typical 6 20 18 16 4 14 2 12 0 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 37-7: IDD, EC Oscillator LP Mode, Fosc = 32 kHz, PIC16LF1777/8/9 Only. FIGURE 37-8: IDD, EC Oscillator LP Mode, Fosc = 32 kHz, PIC16F1777/8/9 Only. 50 80 45 Max. 40 70 35 65 Max. Max: 85C + 3i Typical: 25C 75 Max: 85C + 3i Typical: 25C IDD (A) IDD (A) Typical Typical 30 60 25 55 20 50 15 45 40 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.0 3.8 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 37-9: IDD, EC Oscillator LP Mode, Fosc = 500 kHz, PIC16LF1777/8/9 Only. FIGURE 37-10: IDD, EC Oscillator LP Mode, Fosc = 500 kHz, PIC16F1777/8/9 Only. 500 450 Typical: 25C 400 450 4 MHz Max: 85C + 3i 4 MHz 400 350 350 IDD (A) IDD (A) 300 250 200 300 250 200 1 MHz 150 1 MHz 150 100 100 50 50 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VDD (V) FIGURE 37-11: IDD Typical, EC Oscillator MP Mode, PIC16LF1777/8/9 Only. Microchip Technology Inc. 3.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 37-12: IDD Maximum, EC Oscillator MP Mode, PIC16LF1777/8/9 Only. DS40001819B-page 577 PIC16(L)F1777/8/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. 700 600 Max: 85C + 3i 600 Typical: 25C 500 4 MHz 4 MHz 500 IDD (A) IDD (A) 400 300 1 MHz 400 1 MHz 300 200 200 100 100 0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 4.0 FIGURE 37-13: IDD Typical, EC Oscillator MP Mode, PIC16F1777/8/9 Only. 5.0 5.5 6.0 FIGURE 37-14: IDD Maximum, EC Oscillator MP Mode, PIC16F1777/8/9 Only. 3.5 3.5 Typical: 25C 32 MHz 3.0 32 MHz Max: 85C + 3i 3.0 2.5 2.5 IDD (mA) IDD (mA) 4.5 VDD (V) VDD (V) 2.0 1.5 16 MHz 2.0 16 MHz 1.5 1.0 1.0 8 MHz 8 MHz 0.5 0.5 0.0 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 1.6 3.8 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 37-15: IDD Typical, EC Oscillator HP Mode, PIC16LF1777/8/9 Only. FIGURE 37-16: IDD Maximum, EC Oscillator HP Mode, PIC16LF1777/8/9 Only. 4.0 4.0 32 MHz Typical: 25C 3.5 Max: 85C + 3i 3.5 3.0 2.5 2.5 2.0 IDD (mA) IDD (mA) 32 MHz 3.0 16 MHz 16 MHz 2.0 1.5 1.5 8 MHz 8 MHz 1.0 1.0 0.5 0.5 0.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 37-17: IDD Typical, EC Oscillator HP Mode, PIC16F1777/8/9 Only. DS40001819B-page 578 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 37-18: IDD Maximum, EC Oscillator HP Mode, PIC16F1777/8/9 Only. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. 9 26 Max. Max. 8 Max: 85C + 3i Typical: 25C 24 7 Typical 22 Typical IDD (A) IDD (A) 6 5 20 18 4 16 3 14 2 Max: 85C + 3i Typical: 25C 12 1 0 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 37-19: IDD, LFINTOSC Mode, Fosc = 31 kHz, PIC16LF1777/8/9 Only. FIGURE 37-20: IDD, LFINTOSC Mode, Fosc = 31 kHz, PIC16F1777/8/9 Only. 220 280 Max. Max: 85C + 3i Typical: 25C 200 Max: 85C + 3i Typical: 25C 260 Max. Typical Typical 240 IDD (A) IDD (A) 180 160 220 200 140 180 120 160 100 140 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 37-21: IDD, MFINTOSC Mode, Fosc = 500 kHz, PIC16LF1777/8/9 Only. FIGURE 37-22: IDD, MFINTOSC Mode, Fosc = 500 kHz, PIC16F1777/8/9 Only. 4.2 3.7 32 MHz PLL 3.7 Typical: 25C 3.2 Max: 85C + 3i 32 MHz PLL 3.2 IDD (mA) IDD (mA) 2.7 2.2 16 MHz 2.7 2.2 16 MHz 1.7 1.7 8 MHz 1.2 8 MHz 1.2 4 MHz 0.7 4 MHz 2 MHz 0.7 2 MHz 1 MHz 1 MHz 0.2 0.2 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VDD (V) FIGURE 37-23: IDD Typical, HFINTOSC Mode, PIC16LF1777/8/9 Only. Microchip Technology Inc. 3.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 37-24: IDD Maximum, HFINTOSC Mode, PIC16LF1777/8/9 Only. DS40001819B-page 579 PIC16(L)F1777/8/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. 3.7 4.2 32 MHz PLL 32 MHz PLL Typical: 25C 3.2 3.7 Max: 85C + 3i 3.2 2.7 IDD (mA) IDD (mA) 2.7 2.2 16 MHz 1.7 16 MHz 2.2 1.7 8 MHz 8 MHz 1.2 4 MHz 1.2 4 MHz 2 MHz 0.7 1 MHz 0.2 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2 MHz 0.7 1 MHz 0.2 6.0 2.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 6.0 VDD (V) FIGURE 37-25: IDD Typical, HFINTOSC Mode, PIC16F1777/8/9 Only. FIGURE 37-26: IDD Maximum, HFINTOSC Mode, PIC16F1777/8/9 Only. 2.5 2.5 Typical: 25C Max: 85C + 3i 20 MHz 20 MHz 2.0 2.0 16 MHz 16 MHz 1.5 IDD (mA) IDD (mA) 1.5 1.0 1.0 8 MHz 8 MHz 0.5 0.5 4 MHz 4 MHz 0.0 0.0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.4 2.6 2.8 3.0 VDD (V) 3.2 3.4 3.6 3.8 VDD (V) FIGURE 37-27: IDD Typical, HS Oscillator, 25C, PIC16LF1777/8/9 Only. FIGURE 37-28: IDD Maximum, HS Oscillator, PIC16LF1777/8/9 Only. 3.0 4.0 Typical: 25C Max. 3.0 16 MHz 2.0 Typical IDD (mA) IDD (mA) 3.5 20 MHz 2.5 1.5 2.5 2.0 8 MHz 1.0 1.5 4 MHz 0.5 Typical: 25C Max: 85C + 3i 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 37-29: IDD Typical, HS Oscillator, 25C, PIC16F1777/8/9 Only. DS40001819B-page 580 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 37-30: IDD, HS Oscillator (8 MHz + 4x PLL), PIC16LF1777/8/9 Only. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. 4.5 450 400 4.0 Max. Max. 350 3.5 300 IDD (nA) Typical IDD (mA) 3.0 2.5 250 Max: 85C + 3i Typical: 25C 200 150 2.0 100 Typical: 25C Max: 85C + 3i 1.5 50 Typical 0 1.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.6 6.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 37-31: IDD, HS Oscillator, 32 MHz (8 MHz + 4x PLL), PIC16F1777/8/9 Only. FIGURE 37-32: IPD Base, LP Sleep Mode, PIC16LF1777/8/9 Only. 3.0 1.0 Max: 85C + 3i Typical: 25C Max. 0.9 2.5 0.8 Max. 2.0 0.6 IPD (A) IPD (A) 0.7 Max: 85C + 3i Typical: 25C 0.5 1.5 Typical 0.4 1.0 0.3 Typical 0.2 0.5 0.1 0.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.6 6.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 37-33: IPD Base, LP Sleep Mode (VREGPM = 1), PIC16F1777/8/9 Only. FIGURE 37-34: IPD, Watchdog Timer (WDT), PIC16LF1777/8/9 Only. 35 2.5 Max: 85C + 3i Typical: 25C Max: 85C + 3i Typical: 25C 2.0 30 Max. Max. 1.5 IDD (nA) IPD (A) 25 20 1.0 Typical 15 Typical 0.5 10 0.0 5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 37-35: IPD, Watchdog Timer (WDT), PIC16F1777/8/9 Only. Microchip Technology Inc. 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VDD (V) FIGURE 37-36: IPD, Fixed Voltage Reference (FVR), ADC, PIC16LF1777/8/9 Only. DS40001819B-page 581 PIC16(L)F1777/8/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. 35 40 Max: 85C + 3i Typical: 25C Max. 35 30 Max. 25 Typical IDD (nA) IDD (nA) 30 25 20 Typical 20 15 Max: 85C + 3i Typical: 25C 15 10 10 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5 6.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VDD (V) VDD (V) FIGURE 37-37: IPD, Fixed Voltage Reference (FVR), ADC, PIC16F1777/8/9 Only. FIGURE 37-38: IPD, Fixed Voltage Reference (FVR), DAC/Comparator, PIC16LF1777/8/9 Only. 40 11 Max: 85C + 3i Typical: 25C 10 Max. 35 Max. 9 IDD (nA) IDD (nA) 30 Typical 25 8 Typical 7 20 6 Max: 85C + 3i Typical: 25C 15 5 10 4 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.9 3.0 3.1 3.2 VDD (V) 3.3 3.4 3.5 3.6 3.7 VDD (V) FIGURE 37-39: IPD, Fixed Voltage Reference (FVR), DAC/Comparator, PIC16F1777/8/9 Only. FIGURE 37-40: IPD, Brown-Out Reset (BOR), BORV = 1, PIC16LF1777/8/9 Only. 1.8 13 Max: 85C + 3i Typical: 25C 12 Max. 1.6 11 1.4 10 1.2 9 IDD (nA) IDD (nA) Max. Typical 8 Max: 85C + 3i Typical: 25C 1.0 0.8 7 0.6 6 0.4 5 0.2 Typical 4 0.0 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 VDD (V) FIGURE 37-41: IPD, Brown-Out Reset (BOR), BORV = 1, PIC16F1777/8/9 Only. DS40001819B-page 582 5.4 5.6 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 VDD (V) FIGURE 37-42: IPD, LP Brown-Out Reset (LPBOR = 0), PIC16LF1777/8/9 Only. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. 7 1.8 Max: 85C + 3i Typical: 25C 1.6 Max: 85C + 3i Typical: 25C 6 Max. Max. 1.4 5 IDD (A) IDD (A) 1.2 1.0 0.8 4 3 Typical 0.6 2 Typical 0.4 1 0.2 0 0.0 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 1.6 5.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 37-43: IPD, LP Brown-Out Reset (LPBOR = 0), PIC16F1777/8/9 Only. FIGURE 37-44: IPD, Timer1 Oscillator, FOSC = 32 kHz, PIC16LF1777/8/9 Only. 700 12 Max: 85C + 3i Typical: 25C Max: 85C + 3i Typical: 25C 600 10 Max. 500 IDD (A) IDD (A) Max. 8 6 Typical 4 400 Typical 300 200 2 100 0 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.6 6.0 1.8 2.0 2.2 2.4 FIGURE 37-45: IPD, Timer1 Oscillator, FOSC = 32 kHz, PIC16F1777/8/9 Only. 2.8 3.0 3.2 3.4 3.6 3.8 FIGURE 37-46: IPD, Op Amp, NP Mode (VREFPM = 0), PIC16LF1777/8/9 Only. 900 500 Max: 85C + 3i Typical: 25C 800 Max: 85C + 3i Typical: 25C 450 Max. 700 Max. 400 350 600 300 500 IDD (nA) IDD (A) 2.6 VDD (V) VDD (V) Typical 400 250 200 300 150 200 100 100 50 0 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 37-47: IPD, Op Amp, NP Mode (VREFPM = 0), PIC16F1777/8/9 Only. Microchip Technology Inc. 6.0 Typical 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 37-48: IPD, ADC Non-Converting, PIC16LF1777/8/9 Only. DS40001819B-page 583 PIC16(L)F1777/8/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. 1.4 400 Max: 85C + 3i Typical: 25C 1.2 Max. Max: -40C + 3i Typical: 25C 380 Max. 360 1.0 340 IDD (A) IDD (A) 0.8 0.6 Typical 320 300 280 260 0.4 Typical 240 0.2 220 0.0 200 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.6 1.8 2.0 2.2 2.4 2.6 VDD (V) 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 37-49: IPD, ADC Non-Converting, PIC16F1777/8/9 Only. FIGURE 37-50: IPD, Comparator, NP Mode (VREGPM = 0), PIC16LF1777/8/9 Only. 6 450 Graph represents 3i Limits Max: -40C + 3i Typical: 25C Max. 5 400 4 350 VOH (V) IDD (A) Typical -40C 3 300 125C 2 Typical 250 1 200 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -30 -25 -20 VDD (V) -15 -10 -5 0 IOH (mA) FIGURE 37-51: IPD, Comparator, NP Mode (VREGPM = 0), PIC16F1777/8/9 Only. FIGURE 37-52: VOL vs. IOL Over Temperature, VDD = 5.0V, PIC16F1777/8/9 Only. 3.5 5 Graph represents 3i Limits Graph represents 3i Limits 3.0 4 2.5 VOH (V) VOL (V) 3 -40C 2 2.0 1.5 125C Typical Typical 1.0 125C -40C 1 0.5 0.0 0 0 10 20 30 40 IOL (mA) 50 60 70 80 FIGURE 37-53: VOH vs. IOH Over Temperature, VDD = 5.0V, PIC16F1777/8/9 Only. DS40001819B-page 584 -14 -12 -10 -8 -6 -4 -2 0 IOH (mA) FIGURE 37-54: VOL vs. IOL Over Temperature, VDD = 3.0V. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. 2.0 3.0 Graph represents 3i Limits Graph represents 3i Limits 1.8 2.5 1.6 1.4 VOH (V) VOL (V) 2.0 -40C Typical 1.5 1.2 125C 1.0 0.8 125C Typical 1.0 -40C 0.6 0.4 0.5 0.2 0.0 -4.0 0.0 0 5 10 15 20 25 30 -3.5 -3.0 -2.5 -2.0 IOL (mA) -1.5 -1.0 -0.5 0.0 IOH (mA) FIGURE 37-55: VOH vs. IOH Over Temperature, VDD = 3.0V. FIGURE 37-56: VOL vs. IOL Over Temperature, VDD = 1.8V, PIC16LF1777/8/9 Only. 40,000 1.8 Graph represents 3i Limits 38,000 1.6 Max. 36,000 1.4 34,000 Typical Frequency (Hz) VOL (V) 1.2 1.0 125C Typical 0.8 -40C 0.6 32,000 30,000 Min. 28,000 26,000 0.4 24,000 0.2 22,000 Max: Typical + 3i (-40C to +125C) Typical; statistical mean @ 25C Min: Typical - 3i (-40C to +125C) 20,000 0.0 0 1 2 3 4 5 6 7 8 9 1.6 10 1.8 2.0 2.2 FIGURE 37-57: VOL vs. IOL Over Temperature, VDD = 1.8V, PIC16LF1777/8/9 Only. q 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) IOL (mA) FIGURE 37-58: LFINTOSC Frequency, PIC16LF1777/8/9 Only. y 40,000 24 38,000 22 Max. 36,000 Max. 20 Typical 32,000 Time (ms) Frequency (Hz) 34,000 30,000 Min. 28,000 18 Typical 16 Min. 26,000 14 24,000 Max: Typical + 3i (-40C to +125C) Typical; statistical mean @ 25C Min: Typical - 3i (-40C to +125C) 22,000 Max: Typical + 3i (-40C to +125C) Typical; statistical mean @ 25C Min: Typical - 3i (-40C to +125C) 12 20,000 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 37-59: LFINTOSC Frequency, PIC16F1777/8/9 Only. Microchip Technology Inc. 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 37-60: WDT Time-Out Period, PIC16F1777/8/9 Only. DS40001819B-page 585 PIC16(L)F1777/8/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. 24 2.00 22 Max. Max. 1.95 20 Voltage (V) Time (ms) Typical 18 Typical 16 1.90 Min. Min. 14 1.85 Max: Typical + 3i Typical: statistical mean Min: Typical - 3i Max: Typical + 3i (-40C to +125C) Typical; statistical mean @ 25C Min: Typical - 3i (-40C to +125C) 12 10 1.80 1.6 1.8 2.0 2.2 2.4 2.6 VDD (V) 2.8 3.0 3.2 3.4 3.6 3.8 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (C) FIGURE 37-61: WDT Time-Out Period, PIC16LF1777/8/9 Only. FIGURE 37-62: Brown-Out Reset Voltage, Low Trip Point (BORV = 1), PIC16LF1777/8/9 Only. 70 2.60 Max: Typical + 3i Typical: statistical mean Min: Typical - 3i 60 2.55 Max. Typical Max. 50 Voltage (V) Voltage (mV) 2.50 40 30 Min. 2.45 Typical 2.40 20 Min. Max: Typical + 3i Typical: statistical mean Min: Typical - 3i 2.35 10 2.30 0 -60 -40 -20 0 20 40 60 80 100 120 -60 140 -40 -20 0 20 40 FIGURE 37-63: Brown-Out Reset Hysteresis, Low Trip Point (BORV = 1), PIC16LF1777/8/9 Only. 80 100 120 140 FIGURE 37-64: Brown-Out Reset Voltage, Low Trip Point (BORV = 1), PIC16F1773/6 Only. 2.85 70.0 Max: Typical + 3i Typical: statistical mean Min: Typical - 3i 60.0 Max: Typical + 3i Typical: statistical mean Min: Typical - 3i 2.80 Max. Max. Voltage (V) 50.0 Voltage (mV) 60 Temperature (C) Temperature (C) 40.0 Typical 30.0 2.75 Typical Min. 2.70 20.0 Min. 2.65 10.0 2.60 0.0 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (C) FIGURE 37-65: Brown-Out Reset Hysteresis, Low Trip Point (BORV = 1), PIC16F1773/6 Only. DS40001819B-page 586 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (C) FIGURE 37-66: Brown-Out Reset Voltage, High Trip Point (BORV = 0). 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. 2.7 80 Max: Typical + 3i Typical: statistical mean Min: Typical - 3i 70 2.5 Max. 60 Max. 2.4 50 Voltage (V) Voltage (mV) Max: Typical + 3i Typical: statistical mean Min: Typical - 3i 2.6 Typical 40 2.3 2.2 Typical 2.1 30 2.0 20 1.9 Min. 10 Min. 1.8 1.7 0 -60 -40 -20 0 20 40 60 80 100 120 -60 140 -40 -20 0 20 FIGURE 37-67: Brown-Out Reset Hysteresis, High Trip Point (BORV = 0). FIGURE 37-68: 60 80 100 120 140 LPBOR Reset Voltage. 100 50 Max: Typical + 3i Typical: statistical mean 45 Max: Typical + 3i (-40C to +125C) Typical; statistical mean @ 25C Min: Typical - 3i (-40C to +125C) 90 Max. 40 Max. 35 80 Time (ms) Voltage (mV) 40 Temperature (C) Temperature (C) 30 25 Typical 70 20 Min. 60 Typical 15 10 50 5 40 0 -60 -40 -20 0 20 40 60 80 100 120 2 140 2.5 3 FIGURE 37-69: 3.5 4 4.5 5 5.5 6 100 125 150 VDD (V) Temperature (C) LPBOR Reset Hysteresis. FIGURE 37-70: PWRT Period, PIC16F1777/8/9 Only. 100 1.70 Max: Typical + 3i (-40C to +125C) Typical; statistical mean @ 25C Min: Typical - 3i (-40C to +125C) 90 1.68 Max. 1.66 Max. 1.64 Typical Voltage (V) Time (ms) 80 Typical 70 60 Min. 1.62 1.60 Min. 1.58 1.56 1.54 50 Max: Typical + 3i Typical: statistical mean Min: Typical - 3i 1.52 40 1.50 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 -50 -25 FIGURE 37-71: PWRT Period, PIC16LF1773/6 Only. Microchip Technology Inc. 0 25 50 75 Temperature (C) VDD (V) FIGURE 37-72: POR Release Voltage. DS40001819B-page 587 PIC16(L)F1777/8/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. 1.58 1.58 1.4 Max: Typical + 3i Typical: 25C Min: Typical - 3i 1.56 1.56 1.3 Max. 1.2 Typical 1.52 1.52 Voltage (V) Voltage Voltage (V) (V) Max. 1.54 1.54 1.5 1.50 Typical 1.0 0.9 Min. 1.48 1.48 1.1 Min. 0.8 1.46 Max: Typical + 3i 0 1.46 -40 Typical:-20 statistical mean 20 40 60 80 100 120 75 100 125 150 Max: Typical + 3i Typical: statistical mean Min: Typical - 3i 0.7 Temperature (C) Min: Typical - 3i 0.6 1.44 -50 -25 0 25 50 -50 -25 0 25 50 75 100 125 150 Temperature (C) Temperature (C) FIGURE 37-73: POR Rearm Voltage, NP Mode (VREGPM1 = 0), PIC16F1773/6 Only. FIGURE 37-74: POR Rearm Voltage, NP Mode, PIC16LF1777/8/9 Only. 12 50 Max: Typical + 3i (-40C to +125C) Typical; statistical mean @ 25C Min: Typical - 3i (-40C to +125C) 10 45 40 Max. 35 Time (s) Time (s) 8 Max. 6 Typical 30 Typical 25 20 4 15 2 10 Max: Typical + 3i (-40C to +125C) Typical; statistical mean @ 25C Min: Typical - 3i (-40C to +125C) 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 6.0 1.5 2.0 2.5 3.0 3.5 VDD (V) FIGURE 37-75: VREGPM = 0. 4.0 4.5 5.0 5.5 6.0 VDD (V) Wake From Sleep, FIGURE 37-76: VREGPM = 1. Wake From Sleep, 1.0 40 Max: Typical + 3i Typical: statistical mean @ 25C 35 0.5 Max. DNL (LSb) Time (s) 30 Typical 25 0.0 20 -0.5 Note: The FVR Stabiliztion Period applies when coming out of RESET or exiting sleep mode. 15 -1.0 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VDD (mV) FIGURE 37-77: FVR Stabilization Period, PIC16LF1777/8/9 Only. DS40001819B-page 588 3.8 0 128 256 384 512 640 768 896 1024 Output Code FIGURE 37-78: ADC 10-bit Mode, Single-Ended DNL, VDD = 3.0V, TAD = 1 S, 25C. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 1.0 1.0 0.5 0.5 INL (LSb) DNL (LSb) Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. 0.0 -0.5 0.0 -0.5 -1.0 -1.0 0 128 256 384 512 640 768 896 1024 0 128 256 384 Output Code 512 640 768 896 1024 Output Code FIGURE 37-79: ADC 10-bit Mode, Single-Ended DNL, VDD = 3.0V, TAD = 4 S, 25C. FIGURE 37-80: ADC 10-bit Mode, Single-Ended INL, VDD = 3.0V, TAD = 1 S, 25C. 2.0 1.0 2.5 1.5 2.0 1.5 0.5 0.5 Min. 125C 1.0 Min. -40C 0.5 Min. 25C 0.0 DNL (LSB) INL DNL (LSb)(LSb) 1.0 -0.5 0.0 -1.0 -1.5 0.0 Min. 25C -0.5 Min. 125C -1.0 -0.5 -2.0 0 512 1024 1536 2048 2560 3072 3584 4096 640 768 896 1024 Min. -40C -1.5 Output Code -2.0 -1.0 0 128 256 384 512 -2.5 5.0E-07 1.0E-06 Output Code FIGURE 37-81: ADC 10-bit Mode, Single-Ended INL, VDD = 3.0V, TAD = 4 S, 25C. , , , 2.0E-06 TADs 4.0E-06 8.0E-06 FIGURE 37-82: ADC 10-bit Mode, Single-Ended DNL, VDD = 3.0V, VREF = 3.0V. , 2.0 2.0 1.5 Max. 125C 1.5 1.0 Max. 125C 0.5 Max. 25C 0.0 Min. 25C -0.5 Min. -40C -1.0 Min. 125C 1.0 Max. -40C Max. 25C DNL (LSB) INL (LSB) Max. -40C 0.5 0.0 Min. -40C -0.5 Min. 25C -1.5 -1.0 Min. 125C -1.5 -2.0 5.0E-07 1.0E-06 2.0E-06 TADs 4.0E-06 8.0E-06 FIGURE 37-83: ADC 10-bit Mode, Single-Ended INL, VDD = 3.0V, VREF = 3.0V. Microchip Technology Inc. -2.0 1.8 2.3 VREF 3.0 FIGURE 37-84: ADC 10-bit Mode, Single-Ended DNL, VDD = 3.0V, TAD = 1 S. DS40001819B-page 589 PIC16(L)F1777/8/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. 2.0 800 1.5 1.0 ADC Output Codes INL (LSB) Typical 0.0 Min. -40C -0.5 Min. 25C -1.0 Min. 125C -1.5 Max. 600 Max. 25C 0.5 ADC VREF+ SET TO VDD ADC VREF- SET TO GND 700 Max. -40C Max. 125C 500 Min. 400 300 200 -2.0 Max: Typical + 3i Typical; statistical mean Min: Typical - 3i 100 -2.5 0 -3.0 2.5 1.8 2.3 VREF 3.0 3.5 4.0 4.5 5.0 5.5 6.0 3.0 VDD (V) FIGURE 37-85: ADC 10-bit Mode, Single-Ended INL, VDD = 3.0V, TAD = 1 S. FIGURE 37-86: Temperature Indicator Initial Offset, High Range, Temp. = 20C, PIC16F1777/8/9 only. 800 900 ADC VREF+ SET TO VDD ADC VREF- SET TO GND ADC VREF+ SET TO VDD ADC VREF- SET TO GND Max. 800 Max. 700 Typical Typical Min. 600 Min. ADC Output Codes ADC Output Codes 700 600 500 Max: Typical + 3i Typical; statistical mean Min: Typical - 3i 400 500 400 300 Max: Typical + 3i Typical; statistical mean Min: Typical - 3i 200 100 300 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.5 6.0 1.8 2.1 2.4 FIGURE 37-87: Temperature Indicator Initial Offset, Low Range, Temp. = 20C, PIC16F1777/8/9 only. 3.0 3.3 3.6 3.9 FIGURE 37-88: Temperature Indicator Initial Offset, Low Range, Temp. = 20C, PIC16LF1773/6 only. 150 250 Max. Typical ADC VREF+ SET TO VDD ADC VREF- SET TO GND 125 2.7 VDD (V) VDD (V) ADC VREF+ SET TO VDD ADC VREF- SET TO GND 200 Max. Typical 100 150 Min. Min. ADC Output Codes ADC Output Codes 75 50 25 0 -25 Max: Typical + 3i Typical; statistical mean Min: Typical - 3i -50 100 50 0 -50 Max: Typical + 3i Typical; statistical mean Min: Typical - 3i -100 -150 -75 -50 -25 0 25 50 75 Temperature (C) 100 125 150 FIGURE 37-89: Temperature Indicator Slope Normalized to 20C, PIC16F1777/8/9 only. DS40001819B-page 590 -50 -25 0 25 50 75 100 125 150 Temperature (C) FIGURE 37-90: Temperature Indicator Slope Normalized to 20C, High Range, VDD = 3.6V, PIC16F1777/8/9 only. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. 150 250 Max. ADC VREF+ SET TO VDD ADC VREF- SET TO GND 125 Typical 200 Min. 150 Max. ADC VREF+ SET TO VDD ADC VREF- SET TO GND Typical 100 Min. ADC Output Codes ADC Output Codes 75 50 25 0 -25 Max: Typical + 3i Typical; statistical mean Min: Typical - 3i -50 -25 0 25 50 75 100 125 50 0 -50 Max: Typical + 3i Typical; statistical mean Min: Typical - 3i -100 -75 -50 100 -150 150 -50 -25 0 25 Temperature (C) FIGURE 37-91: Temperature Indicator Slope Normalized to 20C, Low Range, VDD = 3.0V, PIC16F1777/8/9 only. 75 100 125 150 FIGURE 37-92: Temp. Indicator Slope Normalized to 20C, Low Range, VDD = 1.8V, PIC16LF1773/6 Only. 150 250 ADC VREF+ SET TO VDD ADC VREF- SET TO GND ADC VREF+ SET TO VDD ADC VREF- SET TO GND Max. 200 Typical 100 Max. Typical Min. 150 50 ADC Output Codes ADC Output Codes 50 Temperature (C) 0 Min. 100 50 0 -50 -50 Max: Typical + 3i Typical; statistical mean Min: Typical - 3i Max: Typical + 3i Typical; statistical mean Min: Typical - 3i -100 -100 -150 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 Temperature (C) 50 75 100 125 150 Temperature (C) FIGURE 37-93: Temp. Indicator Slope Normalized to 20C, Low Range, VDD = 3.0V, PIC16LF1773/6 Only. FIGURE 37-94: Temp. Indicator Slope Normalized to 20C, High Range, VDD = 3.6V, PIC16LF1773/6 Only. 35% 80 -40C Sample Size = 3,200 25C 30% 75 85C Max. 125C 25% Percent of Units CMRR (dB) 70 65 Typical 60 55 Min. 20% 15% 10% 50 Max: Typical + 3i Typical; statistical mean Min: Typical - 3i 45 5% 40 -50 -25 0 25 50 Temperature (C) 75 100 125 FIGURE 37-95: Op Amp, Common Mode Rejection Ratio (CMRR), VDD = 3.0V. Microchip Technology Inc. 150 0% -7 -5 -4 -3 -2 -1 0 1 2 Offset Voltage (mV) 3 4 5 6 7 FIGURE 37-96: Op Amp, Offset Voltage Histogram, VDD = 3.0V, VCM = VDD/2. DS40001819B-page 591 PIC16(L)F1777/8/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. 8 8 Max. Max. 6 6 4 Offset Voltage (V) Offset Voltage (V) 4 Typical 2 0 Min. -2 Typical 2 0 -2 -4 -4 Min. Max: Typical + 3i Typical; statistical mean Min: Typical - 3i -6 -8 -0.3 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 Max: Typical + 3i Typical; statistical mean Min: Typical - 3i -6 3.0 -8 -0.5 3.3 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 FIGURE 37-97: Op Amp, Offset over Common Mode Voltage, VDD = 3.0V, Temp. = 25C 5.5 FIGURE 37-98: Op Amp, Offset over Common Mode Voltage, VDD = 5.0V, Temp. = 25C, PIC16F1777/8/9 Only. 5.4 3.8 VDD = 3.6V 5.2 3.7 5.0 VDD = 2.3V Slew Rate (V/s) 3.6 Slew Rate (V/s) 5.0 Common Mode Voltage (V) Common Mode Voltage (V) VDD = 5.5V 3.5 3.4 VDD = 2.3V 3.3 4.8 4.6 4.4 3.2 4.0 3.1 3.8 3.0 3.6 -60 -40 -20 0 20 40 60 80 100 120 VDD = 3.6V 4.2 VDD = 3V VDD = 5.5V VDD = 3V -60 140 -40 -20 0 20 40 60 80 100 120 140 Temperature (C) Temperature (C) FIGURE 37-99: Op Amp, Output Slew Rate, Rising Edge, PIC16F1777/8/9 Only. FIGURE 37-100: Op Amp, Output Slew Rate, Falling Edge, PIC16F1777/8/9 Only. 45 6.0 43 -40C 41 VIN = 5V Hysteresis (mV) Output Voltage (V) 5.0 4.0 VIN = 3V 3.0 VIN = 2.3V 2.0 39 25C 37 85C 35 125C 33 31 29 1.0 27 25 0.0 0 20 40 60 80 100 Drive Current (mA) FIGURE 37-101: Op Amp, Output Drive Strength, VDD = 5.0V, Temp. = 25C, PIC16F1777/8/9 Only. DS40001819B-page 592 120 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Common Mode Voltage (V) FIGURE 37-102: Comparator Hysteresis, NP Mode (CxSP = 1), VDD = 3.0V, Typical Measured Values. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. 30 30 25 25 Max. 20 20 15 Offset Voltage (mV) Offset Voltage (mV) Max. 10 5 0 Min. -5 15 10 5 0 Min. -5 -10 -10 -15 -15 -20 -20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 3.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Common Mode Voltage (V) Common Mode Voltage (V) FIGURE 37-103: Comparator Offset, NP Mode (CxSP = 1), VDD = 3.0V, Typical Measured Values at 25C. FIGURE 37-104: Comparator Offset, NP Mode (CxSP = 1), VDD = 3.0V, Typical Measured Values from -40C to 125C. 30 50 25 45 25C 85C 35 125C Hysteresis (mV) Hysteresis (mV) 40 Max. 20 -40C 30 15 10 5 0 Min. -5 -10 25 -15 -20 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 6.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Voltage (V) Common Mode Voltage (V) FIGURE 37-105: Comparator Hysteresis, NP Mode (CxSP = 1), VDD = 5.5V, Typical Measured Values, PIC16F1777/8/9 only. FIGURE 37-106: Comparator Offset, NP Mode (CxSP = 1), VDD = 5.0V, Typical Measured Values at 25C, PIC16F1777/8/9 only. 140 40 Max: Typical + 3i (-40C to +125C) Typical; statistical mean @ 25C Min: Typical - 3i (-40C to +125C) 120 30 Max. Time (ns) Offset Voltage (mV) 100 20 10 80 60 Max. 0 Typical 40 Min. Min. -10 20 -20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Common Mode Voltage (V) FIGURE 37-107: Comparator Offset, NP Mode (CxSP = 1), VDD = 5.5V, Typical Measured Values from -40C to 125C, PIC16F1777/8/9 only. Microchip Technology Inc. 5.0 5.5 0 1.5 2.0 2.5 3.0 3.5 4.0 VDD (V) FIGURE 37-108: Comparator Response Time Over Voltage, NP Mode (CxSP = 1), Typical Measured Values. DS40001819B-page 593 PIC16(L)F1777/8/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. 1,400 90 Max: Typical + 3i (-40C to +125C) Typical; statistical mean @ 25C Min: Typical - 3i (-40C to +125C) 80 Max: Typical + 3i (-40C to +125C) Typical; statistical mean @ 25C Min: Typical - 3i (-40C to +125C) 1,200 70 1,000 Time (ns) Time (ns) 60 50 Max. 40 800 600 Typical 30 Min. 400 Max. 20 Typical 200 10 Min. 0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.5 6.0 2.0 2.5 VDD (V) FIGURE 37-109: Comparator Response Time Over Voltage, NP Mode (CxSP = 1), Typical Measured Values, PIC16F1777/8/9 Only. ( 3.0 3.5 4.0 VDD (V) FIGURE 37-110: Comparator Output Filter Delay Time Over Temp., NP Mode (CxSP = 1), Typical Measured Values, PIC16LF1777/8/9 Only. ) 0.025 800 -40C Max: Typical + 3i (-40C to +125C) Typical; statistical mean @ 25C Min: Typical - 3i (-40C to +125C) 700 0.020 25C 85C 0.015 125C 600 500 DNL (LSb) Time (ns) 0.010 400 0.005 0.000 300 -0.005 Max. 200 -0.010 Typical 100 Min. -0.015 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -0.020 6.0 0 VDD (V) FIGURE 37-111: Comparator Output Filter Delay Time Over Temp., NP Mode (CxSP = 1), Typical Measured Values, PIC16F1777/8/9 Only. 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 Output Code FIGURE 37-112: Typical DAC DNL Error, VDD = 3.0V, VREF = External 3V. 0.020 0.00 -40C -0.05 25C 0.015 85C -0.10 125C 0.010 DNL (LSb) INL (LSb) -0.15 -0.20 -0.25 0.005 0.000 -0.30 -0.005 -40C -0.35 25C -0.010 85C -0.40 125C -0.015 -0.45 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 Output Code FIGURE 37-113: Typical DAC INL Error, VDD = 3.0V, VREF = External 3V. DS40001819B-page 594 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 Output Code FIGURE 37-114: Typical DAC DNL Error, VDD = 5.0V, VREF = External 5V, PIC16F1777/8/9 Only. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. , 0.00 24 -0.05 Max. 22 -0.10 20 DNL (LSb) INL (LSb) -0.15 -0.20 -0.25 18 Typical 16 -0.30 14 -40C -0.35 Min. 25C 12 125C 10 -0.45 0 16 32 48 64 80 96 1.6 112 128 144 160 176 192 208 224 240 Output Code VREF = EXT. 1.8V Vref = Int. Vdd Vref = Ext. 1.8V 0.2 Vref = Ext. 2.0V 0.15 0.2 Vref = Ext. 3.0V 0.1 0.05 Absolute Absolute INL (LSb) INL (LSb) Absolute Absolute DNL (LSb) DNL (LSb) VREF = EXT. 3.0V 0.25 2.6 2.8 3 3.2 3.4 3.6 3.8 VREF = INT. VDD VREF = EXT. 1.8V VREF = EXT. 2.0V -2.5 VREF = EXT. 3.0V -40 0.86 -2.7 25 -2.9 0.84 -3.1 85 125 -3.3 0.82 -3.5 -50 0 50 Temperature (C) 100 150 0.0 0.80 0.0 1.0 2.0 3.0 Temperature (C) 4.0 5.0 0.78 -60 -40 -20 0 20 40 60 Temperature (C) 80 100 120 140 FIGURE 37-117: Absolute Value of DAC DNL Error, VDD = 3.0V, VREF = VDD. -60 -40 -20 0 20 40 60 Temperature (C) 80 100 120 140 FIGURE 37-118: Absolute Value of DAC INL Error, VDD = 3.0V, VREF = VDD. 0.90 0.30 0.3 VREF = INT. VDD -2.1 VREF = EXT. 1.8V 0.88 -2.3 0.26 0.2 VREF = EXT. 2.0V VREF = EXT. 3.0V 0.15 0.22 -40 VREF = EXT. 5.0V 25 85 0.1 125 0.18 0.05 Absolute INL (LSb) Absolute INL (LSb) 0.25 Absolute Absolute DNL (LSb) DNL (LSb) 2.4 -2.3 0.88 VREF = EXT. 2.0V 0.3 0.3 2.2 0.90 -2.1 VREF = INT. VDD 0.35 2 FIGURE 37-116: DAC INL Error, VDD = 3.0V, PIC16LF1773/6 Only. 0.4 0.45 0.4 1.8 Output Code FIGURE 37-115: Typical DAC INL Error, VDD = 5.0V, VREF = External 5V, PIC16F1777/8/9 Only. 0.10 Max: Typical + 3i (-40C to +125C) Typical; statistical mean @ 25C Min: Typical - 3i (-40C to +125C) 85C -0.40 VREF = INT. VDD VREF = EXT. 1.8V VREF = EXT. 2.0V VREF = EXT. 3.0V -2.5 0.86 VREF = EXT. 5.0V -40 -2.7 25 -2.9 0.84 85 -3.1 125 0.82 -3.3 0 0.14 0.0 1.0 2.0 3.0 4.0 Temperature (C) 5.0 -3.5 0.80 0.0 6.0 1.0 2.0 3.0 4.0 Temperature (C) 5.0 6.0 0.78 0.10 -60 -40 -20 0 20 40 60 Temperature (C) 80 100 120 140 FIGURE 37-119: Absolute Value of DAC DNL Error, VDD = 5.0V, VREF = VDD, PIC16F1777/8/9 Only. Microchip Technology Inc. -60 -40 -20 0 20 40 60 Temperature (C) 80 100 120 140 FIGURE 37-120: Absolute Value of DAC INL Error, VDD = 5.0V, VREF = VDD, PIC16F1777/8/9 Only. DS40001819B-page 595 PIC16(L)F1777/8/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. 0.50 2.50 Typical: 25C Typical: 25C Max: 85C + 3i 0.40 Max: 85C + 3i 2.00 0.30 INL (LSb) DNL (LSb) 1.50 0.20 0.10 1.00 0.50 0.00 0.00 -0.10 -0.50 -0.20 0 128 256 384 512 Output Code 640 768 0 896 FIGURE 37-121: DAC DNL Error, VDD = 3.0V, VREF = External 3V. 128 512 Output Code 640 768 896 2.50 Typical: 25C Typical: 25C Max: 85C + 3i Max: 85C + 3i 0.30 2.00 0.20 1.50 INL (LSb) DNL (LSb) 384 FIGURE 37-122: DAC INL Error, VDD = 3.0V, VREF = External 3V. 0.40 0.10 1.00 0.00 0.50 -0.10 0.00 -0.50 -0.20 0 128 256 384 512 Output Code 640 768 0 896 FIGURE 37-123: DAC DNL Error, VDD = 5.0V, VREF = External 5V, PIC16F1777/8/9 Only. 128 256 384 512 Output Code 640 0.6 0.7 Vref = Int. Vdd 0.5 0.6 0.4 Vref = Ext. 1.8V Vref = Ext. 2.0V 0.5 0.3 Vref = Ext. 3.0V 0.2 0.4 0.1 0.3 0 VREF = INT. VDD 0.2 -50 0 50 Temperature (C) 100 Absolute Absolute INL (LSb) INL (LSb) 2.80 -2.1 0.9 0.9 0.8 0.8 0.7 896 VREF = INT. VDD VREF = EXT. 1.8V -2.3 2.30 -2.5 VREF = EXT. 2.0V VREF = EXT. 3.0V -2.7 1.80 -2.9 -40 -3.1 125 25 85 1.30 -3.3 -3.5 VREF = EXT. 1.8V 150 0.800.0 1.0 2.0 3.0 Temperature (C) VREF = EXT. 2.0V 0.1 768 FIGURE 37-124: Typical DAC INL Error, VDD = 5.0V, VREF = External 5V, PIC16F1777/8/9 Only. 1 1.0 Absolute Absolute DNL (LSb) DNL (LSb) 256 4.0 5.0 VREF = EXT. 3.0V 0.0 0.30 -60 -40 -20 0 20 40 60 Temperature (C) 80 100 120 140 FIGURE 37-125: Absolute Value of DAC DNL Error, VDD = 3.0V, VREF = VDD. DS40001819B-page 596 -60 -40 -20 0 20 40 60 Temperature (C) 80 100 120 140 FIGURE 37-126: Absolute Value of DAC INL Error, VDD = 3.0V, VREF = VDD. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. , 1 1.00 VREF = EXT. 1.8V 0.7 0.80 VREF = EXT. 3.0V VREF = EXT. 1.8V -2.3 1.60 VREF = EXT. 5.0V 0.6 0.70 0.5 VREF = INT. VDD -2.1 1.80 VREF = EXT. 2.0V -40 25 0.4 0.60 85 0.3 0.50 0.2 125 0.1 0.40 VREF = EXT. 2.0V Absolute INL (LSb) Absolute INL (LSb) Absolute Absolute DNL (LSb) DNL (LSb) 0.9 0.90 0.8 VREF = EXT. 3.0V -2.5 1.40 VREF = EXT. 5.0V -40 -2.7 1.20 25 -2.9 1.00 85 -3.1 0.80 125 -3.3 0.60 0 0.300.0 1.0 2.0 3.0 4.0 Temperature (C) 5.0 6.0 -3.5 0.40 0.0 0.20 1.0 2.0 3.0 4.0 Temperature (C) 0.20 0.10 -60 , 2.00 VREF = INT. VDD -40 -20 0 20 40 60 Temperature (C) 80 100 120 6.0 0.00 140 FIGURE 37-127: Absolute Value of DAC DNL Error, VDD = 5.0V, VREF = VDD, PIC16F1777/8/9 Only. 5.0 -60 -40 -20 0 20 40 60 Temperature (C) 80 100 120 140 FIGURE 37-128: Absolute Value of DAC INL Error, VDD = 5.0V, VREF = VDD, PIC16F1777/8/9 Only. 1.4 0.85 Fall-2.3V 1.2 Fall-3.0V 0.80 Fall-5.5V 1.0 0.75 Time (s) ZCD Pin Voltage (V) -40C 25C 0.70 85C 0.8 0.6 0.4 Rise-2.3V Rise-3.0V Rise-5.5V 125C 0.65 0.2 0.60 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 6.0 -50 -25 0 25 VDD (V) FIGURE 37-129: ZCD Pin Voltage, Typical Measured Values. 50 75 Temperature (C) 100 125 150 FIGURE 37-130: ZCD Response Time over Voltage, Typical Measured Values. Title TYPICAL MEASURED VALUES FROM 40 C to 125 C 8.0 1.00 0.90 0.80 2.3V 4.0 0.70 1.8V 2.0 0.0 Time (s) ZCD Source/Sink Current (mA) 5.5V 3.0V 6.0 0.60 0.50 0.40 0.30 1.8V 0.20 3.0V -2.0 2.3V 5.5V -4.0 -0.20 0.10 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20 ZCD Pin Voltage (V) FIGURE 37-131: ZCD Pin Current over ZCD Pin Voltage, Typical Measured Values from -40C to 125C. Microchip Technology Inc. 0 100 200 300 400 500 ZCD Source/Sink Current (uA) FIGURE 37-132: ZCD Pin Response Time over Current, Typical Measured Values from -40C to 125C. DS40001819B-page 597 PIC16(L)F1777/8/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 F, TA = 25C. Title TYPICAL MEASURED VALUES 9.0 0.28 8.5 0.26 8.0 7.5 Time (ns) Time (s) 0.24 0.22 7.0 6.5 0.20 6.0 0.18 125C 85C 25C -40C 0.16 5.5 125C 85C 25C -40C 5.0 4.5 0.14 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.5 6.0 2.0 2.5 3.0 VDD (V) 4.0 4.5 5.0 5.5 FIGURE 37-134: COG Dead-Band Delay, DBR/DBF Delay per Step, Typical Measured Values. TYPICAL MEASURED VALUES 0.45 0.07 0.40 Max: Typical + 3i Typical; statistical mean Min: Typical - 3i 0.35 Max. Max. Max: Typical + 3i Typical; statistical mean Min: Typical - 3i 0.06 Typical Typical 0.05 0.30 Min. Min. 0.25 Time (s) Time (s) 6.0 VDD (V) FIGURE 37-133: COG Dead-Band Delay, DBR/DBF = 32, Typical Measured Values. Title 3.5 0.20 0.04 0.03 0.15 0.02 0.10 0.01 0.05 0.00 0 10 20 30 40 50 60 70 DBR/DBF Value FIGURE 37-135: COG Dead-Band Delay per Step, Typical Measured Values. DS40001819B-page 598 0.00 0 1 2 3 4 5 6 DBR/DBF Value 7 8 9 10 11 FIGURE 37-136: COG Dead-Band Delay per Step, Zoomed to First 10 Codes, Typical Measured Values. 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 38.0 DEVELOPMENT SUPPORT The PIC(R) microcontrollers (MCU) and dsPIC(R) digital signal controllers (DSC) are supported with a full range of software and hardware development tools: * Integrated Development Environment - MPLAB(R) X IDE Software * Compilers/Assemblers/Linkers - MPLAB XC Compiler - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families * Simulators - MPLAB X SIM Software Simulator * Emulators - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debuggers/Programmers - MPLAB ICD 3 - PICkitTM 3 * Device Programmers - MPLAB PM3 Device Programmer * Low-Cost Demonstration/Development Boards, Evaluation Kits and Starter Kits * Third-party development tools 38.1 MPLAB X Integrated Development Environment Software The MPLAB X IDE is a single, unified graphical user interface for Microchip and third-party software, and hardware development tool that runs on Windows(R), Linux and Mac OS(R) X. Based on the NetBeans IDE, MPLAB X IDE is an entirely new IDE with a host of free software components and plug-ins for highperformance application development and debugging. Moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. With complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new users. With the ability to support multiple tools on multiple projects with simultaneous debugging, MPLAB X IDE is also suitable for the needs of experienced users. Feature-Rich Editor: * Color syntax highlighting * Smart code completion makes suggestions and provides hints as you type * Automatic code formatting based on user-defined rules * Live parsing User-Friendly, Customizable Interface: * Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. * Call graph window Project-Based Workspaces: * * * * Multiple projects Multiple tools Multiple configurations Simultaneous debugging sessions File History and Bug Tracking: * Local file history feature * Built-in support for Bugzilla issue tracker 2015-2016 Microchip Technology Inc. DS40001819B-page 599 PIC16(L)F1777/8/9 38.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip's 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE. The free MPLAB XC Compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. MPLAB XC Compilers include an assembler, linker and utilities. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to produce its object file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility 38.3 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code, and COFF files for debugging. The MPASM Assembler features include: 38.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction 38.5 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC DSC devices. MPLAB XC Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility * Integration into MPLAB X IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multipurpose source files * Directives that allow complete control over the assembly process DS40001819B-page 600 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 38.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB X SIM Software Simulator fully supports symbolic debugging using the MPLAB XC Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 38.7 MPLAB REAL ICE In-Circuit Emulator System The MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs all 8, 16 and 32-bit MCU, and DSC devices with the easy-to-use, powerful graphical user interface of the MPLAB X IDE. The emulator is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradeable through future firmware downloads in MPLAB X IDE. MPLAB REAL ICE offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables. 2015-2016 Microchip Technology Inc. 38.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost-effective, high-speed hardware debugger/programmer for Microchip Flash DSC and MCU devices. It debugs and programs PIC Flash microcontrollers and dsPIC DSCs with the powerful, yet easy-to-use graphical user interface of the MPLAB IDE. The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a highspeed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 38.9 PICkit 3 In-Circuit Debugger/ Programmer The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB IDE. The MPLAB PICkit 3 is connected to the design engineer's PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the Reset line to implement in-circuit debugging and In-Circuit Serial ProgrammingTM (ICSPTM). 38.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various package types. The ICSP cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications. DS40001819B-page 601 PIC16(L)F1777/8/9 38.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. 38.12 Third-Party Development Tools Microchip also offers a great collection of tools from third-party vendors. These tools are carefully selected to offer good value and unique functionality. * Device Programmers and Gang Programmers from companies, such as SoftLog and CCS * Software Tools from companies, such as Gimpel and Trace Systems * Protocol Analyzers from companies, such as Saleae and Total Phase * Demonstration Boards from companies, such as MikroElektronika, Digilent(R) and Olimex * Embedded Ethernet Solutions from companies, such as EZ Web Lynx, WIZnet and IPLogika(R) The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS40001819B-page 602 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 39.0 PACKAGING INFORMATION 39.1 Package Marking Information 28-Lead SOIC (7.50 mm) XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX Example PIC16F1778-SO e3 1548017 YYWWNNN 28-Lead SPDIP (.300") Example PIC16F1778-SP 1548017 28-Lead SSOP (5.30 mm) e3 Example PIC16F1778 -SS e3 1548017 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC(R) designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC(R) designator e( 3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2015-2016 Microchip Technology Inc. DS40001819B-page 603 PIC16(L)F1777/8/9 Package Marking Information (Continued) 28-Lead UQFN (6x6 mm) PIN 1 Example PIN 1 XXXXXXXX XXXXXXXX YYWWNNN 16F1778 /ML e3 1548017 40-Lead PDIP (600 mil) XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN Example PIC16F1777 /P e3 1526017 40-Lead UQFN (5x5x0.5 mm) PIN 1 Example PIN 1 PIC16 F1779 /MV e 1526017 3 44-Lead QFN (8x8x0.9 mm) PIN 1 Example PIN 1 XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN DS40001819B-page 604 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 Package Marking Information (Continued) 44-Lead TQFP (10x10x1 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 2015-2016 Microchip Technology Inc. Example 16F1779 /PT e3 1526017 DS40001819B-page 605 PIC16(L)F1777/8/9 39.2 Package Details The following sections give the technical details of the packages. "# ! 5 ( ) #( $ ( 6% ,#* ##( (( 477,,,) )7 6 ! 6 ' ( (%( N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 8(# )# ;)(# 9$)+ '!# 9 !( 9.:0 9 = > ( (! 9< 3. ? ? %%! 6 6## / 3#( (! ? ? 0 / // $% ( $% @%( %%! 6@%( 0 > <" ;( / /B ( (! ; / > + + > 3 ? ? ;% 6## 8 ;%@%( ; , ;%@%( <" , - / "# !"#$%&'($ )" *+$()$#(+ (%,( ( ( % -' (. ( #( / )# #%0% ( $%) %'# ( $# # %'# ( $# ## (& %1 #% )# %( 02 3.4 3# )# ( & ("$# ,,( $(( # DS40001819B-page 606 , .3 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2015-2016 Microchip Technology Inc. DS40001819B-page 607 PIC16(L)F1777/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001819B-page 608 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2015-2016 Microchip Technology Inc. DS40001819B-page 609 PIC16(L)F1777/8/9 $% "# & '( 5 ( ) #( $ ( 6% ,#* ##( (( 477,,,) )7 6 &! ! 6 ' ( (%( D N E E1 1 2 NOTE 1 b e c A2 A A1 L L1 8(# )# ;)(# 9$)+ '!# ;;00 9 9 9< = > !( <" : ( ? ? %%! 6 6## B > (% '' ? ? <" @%( 0 > > %%! 6@%( 0 / B <" ;( 5 (;( ; 5 ( ( ; ;% 6## 5 ( ;%@%( B3. 05 ? D D >D + ? /> "# !"#$%&'($ )" *+$()$#(+ (%,( ( ( % )# #%0% ( $%) %'# ( $# # %'# ( $# ## (& %)) #% / )# %( 02 3.4 3# )# ( & ("$# ,,( $(( # 054 ' )# *$#$,( $(( *' ' )( $ ## DS40001819B-page 610 , ./3 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2015-2016 Microchip Technology Inc. DS40001819B-page 611 PIC16(L)F1777/8/9 28-Lead Plastic Quad Flat, No Lead Package (MX) - 6x6x0.5mm Body [UQFN] Ultra-Thin with 0.40 x 0.60 mm Terminal Width/Length and Corner Anchors Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N NOTE 1 1 2 (DATUM A) E (DATUM B) 2X 0.15 C 2X 0.15 C TOP VIEW A C 0.10 C SEATING PLANE (A3) A1 NOTE 4 0.08 C SIDE VIEW 4x b1 4x b2 0.10 D2 0.10 C A B 4x b1 C A B 4x b2 E2 K 2 1 L NOTE 4 N b e 0.10 0.05 C A B C BOTTOM VIEW Microchip Technology Drawing C04-0209 Rev C Sheet 1 of 2 DS40001819B-page 612 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch A Overall Height Standoff A1 (A3) Terminal Thickness E Overall Width E2 Exposed Pad Width D Overall Length D2 Exposed Pad Length b Terminal Width Corner Pad b1 b2 Corner Pad, Metal Free Zone L Terminal Length Terminal-to-Exposed Pad K MIN 0.40 0.00 0.35 0.55 0.15 0.55 0.20 MILLIMETERS NOM 28 0.65 BSC 0.50 0.02 0.127 REF 6.00 BSC 4.00 6.00 BSC 4.00 0.40 0.60 0.20 0.60 - MAX 0.60 0.05 0.45 0.65 0.25 0.65 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 4. Outermost portions of corner structures may vary slightly. Microchip Technology Drawing C04-0209 Rev C Sheet 2 of 2 2015-2016 Microchip Technology Inc. DS40001819B-page 613 PIC16(L)F1777/8/9 28-Lead Plastic Quad Flat, No Lead Package (MX) - 6x6 mm Body [UQFN] With 0.60mm Contact Length And Corner Anchors Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 W1 Y2 E G C2 T2 Y1 X1 SILK SCREEN RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width W1 Optional Center Pad Length T2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X28) X1 Contact Pad Length (X28) Y1 Corner Pad Width (X4) X2 Corner Pad Length (X4) Y2 Distance Between Pads G MIN MILLIMETERS NOM 0.65 BSC MAX 4.05 4.05 5.70 5.70 0.45 1.00 0.90 0.90 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2209B DS40001819B-page 614 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 ) * ! "# 5 ( ) #( $ ( 6% ,#* ##( (( 477,,,) )7 6 ! 6 ' ( (%( N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 8(# )# ;)(# 9$)+ '!# 9 !( 9.:0 9 = ( (! 9< 3. ? ? %%! 6 6## ? 3#( (! ? ? 0 ? B $% ( $% @%( %%! 6@%( 0 > ? > <" ;( > ? ( (! ; ? > ? + / ? + ? / 3 ? ? ;% 6## 8 ;%@%( ; , ;%@%( <" , - "# !"#$%&'($ )" *+$()$#(+ (%,( ( ( % -' (. ( #( / )# #%0% ( $%) %'# ( $# # %'# ( $# ## (& %1 #% )# %( 02 3.4 3# )# ( & ("$# ,,( $(( # 2015-2016 Microchip Technology Inc. , .B3 DS40001819B-page 615 PIC16(L)F1777/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001819B-page 616 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2015-2016 Microchip Technology Inc. DS40001819B-page 617 PIC16(L)F1777/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001819B-page 618 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N NOTE 1 1 2 E (DATUM B) (DATUM A) 2X 0.20 C 2X TOP VIEW 0.20 C 0.10 C C SEATING PLANE A1 A 44X A3 0.08 C SIDE VIEW L 0.10 C A B D2 0.10 C A B E2 K 2 1 NOTE 1 N 44X b 0.07 0.05 e C A B C BOTTOM VIEW Microchip Technology Drawing C04-103D Sheet 1 of 2 2015-2016 Microchip Technology Inc. DS40001819B-page 619 PIC16(L)F1777/8/9 44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch A Overall Height Standoff A1 A3 Terminal Thickness Overall Width E E2 Exposed Pad Width D Overall Length D2 Exposed Pad Length b Terminal Width Terminal Length L K Terminal-to-Exposed-Pad MIN 0.80 0.00 6.25 6.25 0.20 0.30 0.20 MILLIMETERS NOM 44 0.65 BSC 0.90 0.02 0.20 REF 8.00 BSC 6.45 8.00 BSC 6.45 0.30 0.40 - MAX 1.00 0.05 6.60 6.60 0.35 0.50 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-103D Sheet 2 of 2 DS40001819B-page 620 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 EV 44 G2 1 2 OV EV C2 Y2 G1 Y1 E SILK SCREEN X1 RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X44) X1 Contact Pad Length (X44) Y1 Contact Pad to Contact Pad (X40) G1 Contact Pad to Center Pad (X44) G2 Thermal Via Diameter V Thermal Via Pitch EV MIN MILLIMETERS NOM 0.65 BSC MAX 6.60 6.60 8.00 8.00 0.35 0.85 0.30 0.28 0.33 1.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing No. C04-2103C 2015-2016 Microchip Technology Inc. DS40001819B-page 621 PIC16(L)F1777/8/9 44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A D1 NOTE 2 B (DATUM A) (DATUM B) E1 A NOTE 1 2X 0.20 H A B E A N 2X 1 2 3 0.20 H A B TOP VIEW 4X 11 TIPS 0.20 C A B A A2 C SEATING PLANE 0.10 C SIDE VIEW A1 1 2 3 N NOTE 1 44 X b 0.20 e C A B BOTTOM VIEW Microchip Technology Drawing C04-076C Sheet 1 of 2 DS40001819B-page 622 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging H c L (L1) SECTION A-A Notes: Units Dimension Limits N Number of Leads e Lead Pitch A Overall Height Standoff A1 A2 Molded Package Thickness E Overall Width Molded Package Width E1 D Overall Length D1 Molded Package Length b Lead Width c Lead Thickness Lead Length L Footprint L1 Foot Angle MIN 0.05 0.95 0.30 0.09 0.45 0 MILLIMETERS NOM 44 0.80 BSC 1.00 12.00 BSC 10.00 BSC 12.00 BSC 10.00 BSC 0.37 0.60 1.00 REF 3.5 MAX 1.20 0.15 1.05 0.45 0.20 0.75 7 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Exact shape of each corner is optional. 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-076C Sheet 2 of 2 2015-2016 Microchip Technology Inc. DS40001819B-page 623 PIC16(L)F1777/8/9 44-Lead Plastic Thin Quad Flatpack (PT) - 10X10X1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 44 1 2 G C2 Y1 X1 E SILK SCREEN RECOMMENDED LAND PATTERN Units Dimension Limits Contact Pitch E Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X44) X1 Contact Pad Length (X44) Y1 Distance Between Pads G MIN MILLIMETERS NOM 0.80 BSC 11.40 11.40 MAX 0.55 1.50 0.25 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2076B DS40001819B-page 624 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (11/2015) Initial release of this document. Revision B (10/2016) Updated Figures 14-1, 23-3, 23-8, 23-9, and 23-10; Registers 7-5, 7-11, 18-1, 19-1, 24-6, 27-11, 31-3, 31-4, 31-5, 31-6, 31-7, and 32-4; Section 32.6; Tables 3, 4, 3-4, 3-6, 3-7, 3-14, 3-15, 3-18, 12-1, 12-2, 12-3, 24-4, 25-5, 27-5, 27-6, 28-1, 32-4, 36-1, 36-2, 36-7 and 36-8. Updated the Cover page. Section 20.5 rewritten. Added Characterization Data. 2015-2016 Microchip Technology Inc. DS40001819B-page 625 PIC16(L)F1777/8/9 THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our website at www.microchip.com. This website is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the website contains the following information: Users of Microchip products can receive assistance through several channels: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the website at: http://www.microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip website at www.microchip.com. Under "Support", click on "Customer Change Notification" and follow the registration instructions. DS40001819B-page 626 2015-2016 Microchip Technology Inc. PIC16(L)F1777/8/9 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . [X](1) PART NO. Device - X Tape and Reel Temperature Option Range /XX XXX Package Pattern Examples: a) b) Device: PIC16F1777, PIC16LF1777, PIC16F1778, PIC16LF1778, PIC16F1779, PIC16F1779 Tape and Reel Option: Blank T = Standard packaging (tube or tray) = Tape and Reel(1) Temperature Range: I E = -40C to +85C = -40C to +125C Package:(2) MV MX P PT ML SO SP SS = = = = = = = = PIC16LF1777-I/P Industrial temperature PDIP package PIC16F1779-E/SS Extended temperature SSOP package (Industrial) (Extended) UQFN, 40-pin 5x5x0.5 mm UQFN, 28-pin 6x6x0.5 mm PDIP, 40-pin TQFN, 44-pin 10x10 mm QFN, 44-pin 8x8 mm SOIC, 28-pin SPDIP, 28-pin SSOP, 28-pin Note 1: 2: Pattern: QTP, SQTP, Code or Special Requirements (blank otherwise) 2015-2016 Microchip Technology Inc. Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Small form-factor packaging options may be available. Please check www.microchip.com/packaging for small-form factor package availability, or contact your local Sales Office. DS40001819B-page 627 PIC16(L)F1777/8/9 NOTES: DS40001819B-page 628 2015-2016 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2015-2016 Microchip Technology Inc. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2015-2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. 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