2015-2016 Microchip Technology Inc. DS40001819B-page 1
PIC16(L)F1777/8/9
Description
PIC16(L)F1777/8/9 microcontrollers feature a high level of integration of intelligent analog and digital peripherals for a
wide range of applications, such as lighting, power supplies, battery charging, motor control and other general purpose
applications. These devices deliver multiple op amps, 5-/10-bit DACs, high-speed comparators, 10-bit ADC, 10-/16-bit
PWMs, programmable ramp generator (PRG) and other peripherals that can be connected internally to create closed-
loop systems without using pins or the printed circuit board (PCB) area. The 10-/16-bit PWMs, digital signal modulators
and tri-state output op amp can be used together to create a LED dimming engine for lighting applications. The
peripheral pin select (PPS) functionality provides flexibility, eases PCB layout and peripheral utilization by allowing
digital peripheral pin mapping to an I/O.
Core Features
• C Compiler Optimized RISC Architecture
• Only 49 Instructions
• Operating Speed:
- DC – 32 MHz clock input
- 125 ns minimum instruction cycle
• Interrupt Capability
• 16-Level Deep Hardware Stack
•Five 8-Bit Timers
• Three 16-Bit Timers
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRT)
• Brown-out Reset (BOR) with Selectable Trip Point
• Extended Watchdog Timer (EWDT):
- Low-power 31 kHz WDT
- Software selectable prescaler
- Software selectable enable
Memory
• Up to 28 Kbytes Program Flash Memory (PFM)
• Up to 2 Kbytes Data RAM
• Direct, Indirect and Relative Addressing modes
• High-Endurance Flash (HEF):
- 128B of nonvolatile data storage
- 100K Erase/Write cycles
Operating Characteristics
• Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF1777/8/9)
- 2.3V to 5.5V (PIC16F1777/8/9)
• Temperature Range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
eXtreme Low-Power (XLP) Features
• Sleep mode: 50 nA @ 1.8V, typical
• Watchdog Timer: 500 nA @ 1.8V, typical
• Secondary Oscillator: 500 nA @ 32 kHz
• Operating Current:
- 8 uA @ 31 kHz, 1.8V, typical
- 32 uA/MHz @ 1.8V, typical
Intelligent Analog Peripherals
• 10-Bit Analog-to-Digital Converter (ADC):
- Up to 28 external channels
- Conversion available during Sleep
• Four Operational Amplifiers (OPA):
- Selectable internal and external channels
- Tri-state output
- Part of LED dimming engine
- Selectable internal and external channels
• Eight High-Speed Comparators (HS Comp):
- Up to nine external inverting inputs
- Up to 12 external non-inverting inputs
- Fixed Voltage Reference at inverting and
non-inverting input(s)
- Comparator outputs externally accessible
• Digital-to-Analog Converters (DAC):
- Four 10-bit resolution DACs
- 10-bit resolution, rail-to-rail
- Conversion during Sleep
- Internal connections to ADCs and HS
Comparators
• Voltage Reference:
- Fixed Voltage Reference (FVR)
- 1.024V, 2.048V and 4.096V output levels
• Zero-Cross Detector (ZCD):
- Detect high-voltage AC signal
• Four Programmable Ramp Generators (PRG):
- Slope compensation
- Ramp generation
• High-Current Drive I/Os:
- Up to 100 mA sink or source @ 5V
28/40/44- Pin, 8-Bit Flash Microcontr oller
PIC16(L)F1777/8/9
DS40001819B-page 2 2015-2016 Microchip Technology Inc.
Digital Peripherals
• Four Configurable Logic Cells (CLC):
- Integrated combinational and state logic
• Four Complementary Output Generators (COG):
- Push-pull, Full-Bridge and Steering modes
• Four Capture/Compare/PWM (CCP) Modules
• Pulse-Width Modulator (PWM):
- Four 16-bit PWMs
- Independent timers
- Multiple output modes (Edge-, Center-
Aligned, set and toggle on register match)
- User settings for phase, duty cycle, period,
offset and polarity
- 16-bit timer capability
- Three 10-bit PWMs
• Digital Signal Modulator (DSM):
- Modulates a carrier signal with a digital data
to create custom carrier synchronized output
waveforms
- Part of LED dimming engine
• Peripheral Pin Select (PPS):
- I/O remapping of digital peripherals
• Serial Communications:
- Enhanced USART (EUSART)
- SPI, I2C, RS-232, RS-485, LIN compatible
- Auto-Baud Detect, auto-wake-up on start
• Up to 25 I/O Pins:
- Individually programmable pull-ups
- Slew rate control
- Interrupt-on-change with edge-select
Clocking Structure
• Precision Internal Oscillator:
- ±1% at calibration
- Selectable frequency range 32 MHz to
31 kHz
• 31 kHz Low-Power Internal Oscillator
• 4x Phase-Locked Loop (PLL) for up to 32 MHz
Internal Operation
• External Oscillator Block with Three External
Clock modes up to 32 MHz
TABLE 1: PIC16(L)F1773/6/7/8/9 FAMILY TYPES
Device
Data Sheet Index
Program Fla s h Memory
(bytes)
Program Fla s h Memory
(word)
High Endurance Flash (B)
Data SRAM (Bytes)
I/O Pin s (1)
8-Bit/16-Bit Timers
High-Speed Comparator
10-bit ADC (ch)
5/10-bit DAC
CCP
10-bit/16-bit PWM
COG
CLC
Op Am p
Zero Cross Detect
Program m a ble R a m p Gen
High-Current I/Os
Peripheral Pin Select
EUSART
I2C/SPI
Debug(2)
PIC16(L)F1773 (A) 7K 4K 128 512 25 5/3 617 3/3 33/3 3 4 3 1 3 2 Y 1 1 I
PIC16(L)F1776 (A) 14K 8K 128 1K 25 5/3 617 3/3 33/3 3 4 3 1 3 2 Y 1 1 I
PIC16(L)F1777 (B) 14K 8K 128 1K 36 5/3 828 4/4 44/4 4 4 4 1 4 2 Y 1 1 I
PIC16(L)F1778 (B) 28K 16K 128 2K 25 5/3 617 3/3 33/3 3 4 3 1 3 2 Y 1 1 I
PIC16(L)F1779 (B) 28K 16K 128 2K 36 5/3 828 4/4 44/4 4 4 4 1 4 2 Y 1 1 I
Note 1: One pin is input-only.
2: I – Debugging integrated on chip.
Data Sheet Index:
A: DS40001810 PIC16(L)F1773/6 Data Sheet, 28-Pin, 8-bit Flash Microcontrollers
B: DS40001819 PIC16(L)F1777/8/9 Data Sheet, 28/40/44-Pin, 8-bit Flash Microcontrollers
Note: For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
2015-2016 Microchip Technology Inc. DS40001819B-page 3
PIC16(L)F1777/8/9
TABLE 2: PACKAGES
Packages SPDIP PDIP SOIC SSOP UQFN QFN TQFP
PIC16(L)F1778 
PIC16(L)F1777/9 
Note: Pin details are subject to change.
PIC16(L)F1777/8/9
DS40001819B-page 4 2015-2016 Microchip Technology Inc.
PIN DIAGRAMS
FIGURE 1: 28-PIN SPDIP, SOIC, SSOP
FIGURE 2: 28-PIN UQFN (6x6x0.5 mm)
PIC16(L)F1778
1
2
3
4
5
6
7
8
9
10
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
RA4
RA5
RB6/ICSPCLK
RB5
RB4
RB3
RB2
RB1
RB0
VDD
VSS
11
12
13
14 15
16
17
18
19
20
28
27
26
25
24
23
22
21
VSS
RA7
RA6
RC0
RC1
RC2
RC3
RC5
RC4
RC7
RC6
RB7/ICSPDAT
Note: See Table 3 for location of all peripheral functions.
2
3
6
1
18
19
20
21
15
7
16
17
RC0
5
4
RB7/ICSPDAT
RB6/ICSPCLK
RB5
RB4
RB0
VDD
VSS
RC7
RC6
RC5
RC4
RE3/MCLR/VPP
RA0
RA1
RA2
RA3
RA4
RA5
VSS
RA7
RA6
RC1
RC2
RC3
910 138141211
27 26 2328 2224
25
RB3
RB2
RB1
PIC16(L)F1778
Note: See Tabl e 3 for location of all peripheral functions.
2015-2016 Microchip Technology Inc. DS40001819B-page 5
PIC16(L)F1777/8/9
FIGURE 3: 40-P IN PDIP
FIGURE 4: 40-PIN UQFN (5x5x0.5 mm)
2
3
4
5
6
7
8
9
10
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
RA4
RA5
RE0
RE1
RE2
RB6/ICSPCLK
RB5
RB4
RB0
VDD
VSS
RD2
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
VSS
RA7
RA6
RC0
RC1
RC2
RC3
RD0
RD1
RC5
RC4
RD3
RD4
RC7
RC6
RD7
RD6
RD5
RB7/ICSPDAT
1
RB3
RB2
RB1
PIC16(L)F1777/9
Note: See Tabl e 4 for location of all peripheral functions.
10
11
2
3
4
5
6
1
18 19 20
21
22
12 13 14 15
38
8
7
40 39
16 17
29
30
31
32
33
23
24
25
26
27
28
36 34
35
9
37
RA1
RA0
VPP/MCLR/RE3
RB3
ICSPDAT/RB7
ICSPCLK/RB6
RB5
RB4 RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
RA3
RA2
PIC16(L)F1777/9
Note: See Table 4 for location of all peripheral functions.
PIC16(L)F1777/8/9
DS40001819B-page 6 2015-2016 Microchip Technology Inc.
FIGURE 5: 44-PIN TQFP (10x10 mm)
FIGURE 6: 44-PIN QFN (8X8 mm)
10
11
2
3
6
1
18 19 20 21 22
12 13 14 15
38
8
7
44 43 42 41 40 39
16 17
29
30
31
32
33
23
24
25
26
27
28
36 3435
9
37
5
4
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0
AN1/RA1
AN0/RA0
VPP/MCLR/RE3
RB3
ICSPDAT/RB7
ICSPCLK/RB6
RB5
RB4
NC
RA3
RA2
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
RA6
RA7
VSS
NC
VDD
RE2
RE1
RE0
RA5
RA4
NC
NC
PIC16(L)F1777/9
Note: See Tabl e 4 for location of all peripheral functions.
RA6
RA7
N/C
AV
SS
N/C
V
DD
RE2
RE1
RE0
RA5
RA4
RC7
RD4
RD5
RD6
RD7
V
SS
V
DD
AV
DD
RB0
RB1
RB2
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0
RB3
N/C
RB4
RB5
ICSPCLK/RB6
ICSPDAT/RB7
V
PP
/MCLR/RE3
RA0
RA1
RA2
RA3
PIC16F1777/9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Note: See Table 4 for location of all peripheral functions.
2015-2016 Microchip Technology Inc. DS40001819B-page 7
PIC16(L)F1777/8/9
PIN ALLOCATION TABLES
TABLE 3: 28-PIN ALLOCATION TABLE (PIC16(L)F1778)
I/O
28-Pin SPDIP/SOIC/SSOP
28-Pin UQFN
ADC
VREF
DAC
Op Amp
Comparator
ZCD
PRG
Timers
PWM
CCP
COG
CLC
Modulator
EUSART
MSSP
Interrupt
Pull-ups
High Cu rr ent
Basic
RA0 227 AN0 — — — C1IN0-
C2IN0-
C3IN0-
C4IN0-
C5IN0-
C6IN0-
— — — — — — CLCIN0(1) — — — IOC Y — —
RA1 3 28 AN1 — — OPA1OUT
OPA2IN1+
OPA2IN1-
C1IN1-
C2IN1-
C3IN1-
C4IN1-
— PRG1IN0
PRG2IN1
— — — — CLCIN1(1) — — — IOC Y — —
RA2 4 1 AN2
VREF-
DAC1REF0-
DAC2REF0-
DAC3REF0-
DAC4REF0-
DAC5REF0-
DAC7REF0-
DAC1OUT1 —C1IN0+
C2IN0+
C3IN0+
C4IN0+
C5IN0+
C6IN0+
— — — — — — — — — — IOC Y — —
RA3 5 2 AN3
VREF+
DAC1REF0+
DAC2REF0+
DAC3REF0+
DAC4REF0+
DAC5REF0+
DAC7REF0+
— — C1IN1+ — — — — — — — MD1CL(1) — — IOC Y — —
RA4 6 3 — — DAC4OUT1 OPA1IN0+ — — PRG1R(1) T0CKI — — — — MD1CH(1) — — IOC Y — —
RA5 7 4 AN4 — DAC2OUT1 OPA1IN0- — — PRG1F(1) ——— — —MD1MOD
(1) —SSIOC Y — —
RA6 10 7 — — — — C6IN1+ — — — — — — — — — — IOC Y — OSC2
CLKOUT
RA7 9 6 — — — — — — — — — — — — — — — IOC Y — OSC1
CLKIN
RB0 21 18 AN12 — — — C2IN1+ ZCD — — — — COG1IN(1) — — — — IOC
INT
YHIB0 —
RB1 22 19 AN10 — — OPA2OUT
OPA1IN1+
OPA1IN1-
C1IN3-
C2IN3-
C3IN3-
C4IN3-
— PRG2IN0
PRG1IN1
———COG2IN
(1) — — — — IOC Y HIB1 —
RB2 23 20 AN8 —DAC3OUT1 OPA2IN0- — — — — — — COG3IN(1) — — — — IOC Y — —
RB3 24 21 AN9 — — OPA2IN0+ C1IN2-
C2IN2-
C3IN2-
—— — — — — —MD3CL
(1) — — IOC Y — —
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection register.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
PIC16(L)F1777/8/9
DS40001819B-page 8 2015-2016 Microchip Technology Inc.
RB4 25 22 AN11 — — — C3IN1+ — — T5G — — — — MD3CH(1) — — IOC Y — —
RB5 26 23 AN13 DAC5REF1-
DAC7REF1-
——C4IN2- ——T1G—CCP7
(1) ——MD3MOD
(1) — — IOC Y — —
RB6 27 24 —DAC5REF1+
DAC7REF1+
— — C4IN1+ — — — — — — CLCIN2(1) — — — IOC Y — ICSPCLK
RB7 28 25 — — DAC1OUT2
DAC2OUT2
DAC3OUT2
DAC4OUT2
DAC5OUT2
DAC7OUT2
—C5IN1+ ——T6IN
(1) —— —CLCIN3
(1) — — — IOC Y — ICSPDAT
RC0 11 8 — — DAC5OUT1 — — — — T1CKI(1)
T3CKI(1)
T3G(1)
SOSCO
— — — — — — — IOC Y — —
RC1 12 9 — — DAC7OUT1 — — — PRG2R(1) SOSCI — CCP2(1) — — — — — IOC Y — —
RC2 13 10 AN14 — — — C5IN2-
C6IN2-
—PRG2F(1) T5CKI —CCP1(1) — — — — — IOC Y — —
RC3 14 11 AN15 — — — C1IN4-
C2IN4-
C3IN4-
C4IN4-
C5IN4-
C6IN4-
——T2IN
(1) —— — —MD2CL
(1) — SCL IOC Y — —
RC4 15 12 AN16 — — — C5IN3-
C6IN3-
—PRG3R(1) T8IN(1) — — — — MD2CH(1) —SDA IOC Y — —
RC5 16 13 AN17 — — OPA3IN0+ — — PRG3F(1) T4IN(1) —— — —MD2MOD
(1) — — IOC Y — —
RC6 17 14 AN18 — — OPA3OUT C5IN1-
C6IN1-
—PRG3IN0 — — — — — — — — IOC Y — —
RC7 18 15 AN19 — — OPA3IN0- — — — — — — — — — — — IOC Y — —
RE3 126 — — — — — — — — — — — — — — — IOC — — MCLR
VPP
VDD 2017— — — — —— — — — — — — — — — — —— VDD
VSS 8 5 — — — — — — — — — — — — — — — — — — VSS
VSS 1916— — — — —— — — — — — — — — — — —— VSS
TABLE 3: 28-PIN ALLOCATION TABLE (PIC16(L)F1778) (CONTINUED)
I/O
28-Pin SPDIP/SOIC/SSOP
28-Pin UQFN
ADC
VREF
DAC
Op Amp
Comparator
ZCD
PRG
Timers
PWM
CCP
COG
CLC
Modulator
EUSART
MSSP
Interrupt
Pull-ups
High Current
Basic
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection register.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
2015-2016 Microchip Technology Inc. DS40001819B-page 9
PIC16(L)F1777/8/9
OUT(2) —— — — — — C1OUT
C2OUT
C3OUT
C4OUT
C5OUT
C6OUT
—— —PWM3
PWM4
PWM5
PWM6
PWM9
PWM11
CCP1
CCP2
CCP7
COG1A
COG1B
COG1C
COG1D
COG2A
COG2B
COG2C
COG2D
COG3A
COG3B
COG3C
COG3D
CLC1OUT
CLC2OUT
CLC3OUT
CLC4OUT
MD1OUT
MD2OUT
MD3OUT
DT(3)
TX
CK
SDO
SDA(3)
SCK
SCL(3)
——— —
TABLE 3: 28-PIN ALLOCATION TABLE (PIC16(L)F1778) (CONTINUED)
I/O
28-Pin SPDIP/SOIC/SSOP
28-Pin UQFN
ADC
VREF
DAC
Op Amp
Comparator
ZCD
PRG
Timers
PWM
CCP
COG
CLC
Modulator
EUSART
MSSP
Interrupt
Pull-ups
High Current
Basic
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection register.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
PIC16(L)F1777/8/9
DS40001819B-page 10 2015-2016 Microchip Technology Inc.
TABLE 4: 40/44-PIN ALLOCATION TABLE (PIC16(L)F1777/9)
I/O
40-Pin PDIP
40-Pin (U)QFN
44-Pi n TQFP
44-Pin QFN
ADC
VREF
DAC
Op Amp
Comparator
ZCD
PRG
Timers
PWM
CCP
COG
CLC
Modulator
EUSART
MSSP
Interrupt
Pull-ups
High Current
Basic
RA0 217 19 19 AN0 — — — C1IN0-
C2IN0-
C3IN0-
C4IN0-
C5IN0-
C6IN0-
C7IN0-
C8IN0-
— — — — — — CLCIN0(1) — — — IOC Y — —
RA1 3 18 20 20 AN1 — — OPA1OUT
OPA2IN1+
OPA2IN1-
C1IN1-
C2IN1-
C3IN1-
C4IN1-
— PRG1IN0
PRG2IN1
— — — — CLCIN1(1) — — — IOC Y — —
RA2 419 21 21 AN2 DAC1REF0-
DAC2REF0-
DAC3REF0-
DAC4REF0-
DAC5REF0-
DAC6REF0-
DAC7REF0-
DAC8REF0-
DAC1OUT1 —C1IN0+
C2IN0+
C3IN0+
C4IN0+
C5IN0+
C6IN0+
C7IN0+
C8IN0+
— — — — — — — — — — IOC Y — —
RA3 5 20 22 22 AN3 DAC1REF0+
DAC2REF0+
DAC3REF0+
DAC4REF0+
DAC5REF0+
DAC6REF0+
DAC7REF0+
DAC8REF0+
— — C1IN1+ — — — — — — — MD1CL(1) — — IOC Y — —
RA4 621 23 23 — — — OPA1IN0+ — — PRG1R(1) — — — — — MD1CH(1) — — IOC Y — —
RA5 7 22 24 24 AN4 — DAC2OUT1 OPA1IN0- — — PRG1F(1) ——— — —MD1MOD
(1) —SSIOC Y — —
RA6 14 29 31 33 — — — — C6IN1+ — — — — — — — — — — IOC Y — OSC2
CLKOUT
RA7 13 28 30 32 — — — — — — — — — — — — — — — IOC Y — OSC1
CLKIN
RB0 33 8 8 9 AN12 — — — C2IN1+ ZCD — — — CCP8(1) COG1IN(1) —MD4CL(1) — — IOC
INT
YHIB0 —
RB1 34 9 9 10 AN10 — — OPA2OUT
OPA1IN1+
OPA1IN1-
C1IN3-
C2IN3-
C3IN3-
C4IN3-
— PRG2IN0
PRG1IN1
PRG4R(1)
— — — COG2IN(1) — MD4CH(1) — — IOC Y HIB1 —
RB2 35 10 10 11 AN8 —DAC3OUT1 OPA2IN0- — — PRG4F(1) — — — COG3IN(1) —MD4MOD(1) — — IOC Y — —
RB3 36 11 11 12 AN9 — — OPA2IN0+ C1IN2-
C2IN2-
C3IN2-
— — — — — — — MD3CL(1) — — IOC Y — —
RB4 37 12 14 14 AN11 — — — C3IN1+ — — — — — — — MD3CH(1) — — IOC Y — —
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection register.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
2015-2016 Microchip Technology Inc. DS40001819B-page 11
PIC16(L)F1777/8/9
RB5 38 13 15 15 AN13 DAC5REF1-
DAC7REF1-
— — C4IN2- — — — — CCP7(1) ——MD3MOD
(1) — — IOC Y — —
RB6 39 14 16 16 —DAC5REF1+
DAC7REF1+
— — C4IN1+ — — — — — — CLCIN2(1) — — — IOC Y — ICSPCLK
RB7 40151717 — — DAC1OUT2
DAC2OUT2
DAC3OUT2
DAC4OUT2
DAC5OUT2
DAC6OUT2
DAC7OUT2
DAC8OUT2
—C5IN1+ ——T6IN
(1) —— —CLCIN3
(1) — — — IOC Y — ICSPDAT
RC0 15 30 32 34 — — DAC5OUT1 — — — — T1CKI(1)
T3CKI(1)
T3G(1)
SOSCO
— — — — — — — IOC Y — —
RC1 16 31 35 35 — — DAC7OUT1 — — — PRG2R(1) SOSCI — CCP2(1) — — — — — IOC Y — —
RC2 17 32 36 36 AN14 — — — C5IN2-
C6IN2-
—PRG2F(1) — — CCP1(1) — — — — — IOC Y — —
RC3 18 33 37 37 AN15 — — — — — — T2IN(1) —— — —MD2CL
(1) — SCL IOC Y — —
RC4 23 38 42 42 AN16 — — — C5IN3-
C6IN3-
—PRG3R(1) T8IN(1) — — — — MD2CH(1) —SDA IOC Y — —
RC5 24 39 43 43 AN17 — — OPA3IN0+ — — PRG3F(1) T4IN(1) —— — —MD2MOD
(1) — — IOC Y — —
RC6 25 40 44 44 AN18 — — OPA3OUT
OPA4IN1+
OPA4IN1-
C5IN1-
C6IN1-
C7IN1-
C8IN1-
—PRG3IN0
PRG4IN1
— — — — — — — — IOC Y — —
RC7 26 1 1 1 AN19 — — OPA3IN0- — — — — — — — — — — — IOC Y — —
RD0 19 34 38 38 AN20 — — OPA4IN0+ — — — — — — — — — — — — Y — —
RD1 20 35 39 39 AN21 — — OPA4OUT
OPA3IN1+
OPA3IN1-
C1IN4-
C2IN4-
C3IN4-
C4IN4-
C5IN4-
C6IN4-
C7IN4-
C8IN4-
— PRG3IN1
PRG4IN0
——— — — — ———Y——
RD2 21 36 40 40 AN22 —DAC4OUT1 OPA4IN0- — — — — — — — — — — — — Y — —
RD3 22 37 41 41 AN23 — — — C8IN2- — — — — — — — — — — — Y — —
RD4 27 2 2 2 AN24 — — — C7IN2- — — — — — — — — — — — Y — —
RD5 28 3 3 3 AN25 — — — C7IN3-
C8IN3-
—— — — — — — — — — —Y— —
RD6 29 4 4 4 AN26 — — — C7IN1+ — — — — — — — — — — — Y — —
RD7 30 5 5 5 AN27 — — — C8IN1+ — — — — — — — — — — — Y — —
TABLE 4: 40/44-PIN ALLOCATION TABLE (PIC1 6( L)F1777/9) (CON TINUED)
I/O
40-Pin PDIP
40-Pin (U)QF N
44-Pin TQFP
44-Pin QFN
ADC
VREF
DAC
Op Amp
Comparator
ZCD
PRG
Timers
PWM
CCP
COG
CLC
Modulator
EUSART
MSSP
Interrupt
Pull-ups
High Current
Basic
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection register.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
PIC16(L)F1777/8/9
DS40001819B-page 12 2015-2016 Microchip Technology Inc.
RE0 823 25 25 AN5 DAC6REF1+
DAC8REF1+
— — — — — — — — — — — — — — Y — —
RE1 9 24 26 26 AN6 DAC6REF1-
DAC8REF1-
DAC6OUT1 — — — — — — — — — — — — — Y — —
RE2 10 25 27 27 AN7 —DAC8OUT1 — — — — — — — — — — — — — Y — —
RE3 1 16 18 18 — — — — — — — — — — — — — — — IOC Y — MCLR
VPP
VDD 11 7 7 7,8 — — — — — — — — — — — — — — — — — — VDD
VDD 32 26 28 28 — — — — — — — — — — — — — — — — — — VDD
VSS 12 6 6 6 — — — — — — — — — — — — — — — — — — VSS
VSS 31 27 29 30 — — — — — — — — — — — — — — — — — — VSS
OUT(2) ——— — — — — C1OUT
C2OUT
C3OUT
C4OUT
C5OUT
C6OUT
C7OUT
C8OUT
—— —PWM3
PWM4
PWM5
PWM6
PWM9
PWM10
PWM11
PWM12
CCP1
CCP2
CCP7
CCP8
COG1A
COG1B
COG1C
COG1D
COG2A
COG2B
COG2C
COG2D
COG3A
COG3B
COG3C
COG3D
COG4A
COG4B
COG4C
COG4D
CLC1OUT
CLC2OUT
CLC3OUT
CLC4OUT
MD1OUT
MD2OUT
MD3OUT
MD4OUT
DT(3)
TX
CK
SDO
SDA(3)
SCK
SCL(3)
——— —
TABLE 4: 40/44-PIN ALLOCATION TABLE (PIC1 6( L)F1777/9) (CON TINUED)
I/O
40-Pin PDIP
40-Pin (U)QF N
44-Pin TQFP
44-Pin QFN
ADC
VREF
DAC
Op Amp
Comparator
ZCD
PRG
Timers
PWM
CCP
COG
CLC
Modulator
EUSART
MSSP
Interrupt
Pull-ups
High Current
Basic
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection register.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
2015-2016 Microchip Technology Inc. DS40001819B-page 13
PIC16(L)F1777/8/9
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 15
2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 34
3.0 Memory Organization ................................................................................................................................................................. 36
4.0 Device Configuration.................................................................................................................................................................. 94
5.0 Oscillator Module (with Fail-Safe Clock Monitor) ..................................................................................................................... 101
6.0 Resets ...................................................................................................................................................................................... 119
7.0 Interrupts .................................................................................................................................................................................. 127
8.0 Power-Down Mode (Sleep) ...................................................................................................................................................... 146
9.0 Watchdog Timer (WDT) ........................................................................................................................................................... 151
10.0 Flash Program Memory Control ............................................................................................................................................... 156
11.0 I/O Ports ................................................................................................................................................................................... 173
12.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 203
13.0 Interrupt-On-Change ................................................................................................................................................................ 213
14.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 221
15.0 Temperature Indicator Module ................................................................................................................................................. 224
16.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 226
17.0 5-Bit Digital-to-Analog Converter (DAC) Module...................................................................................................................... 241
18.0 10-bit Digital-to-Analog Converter (DAC) Module .................................................................................................................... 246
19.0 Comparator Module.................................................................................................................................................................. 252
20.0 Zero-Cross Detection (ZCD) Module........................................................................................................................................ 265
21.0 Timer0 Module ......................................................................................................................................................................... 272
22.0 Timer1/3/5 Module with Gate Control....................................................................................................................................... 275
23.0 Timer2/4/6/8 Module ................................................................................................................................................................ 286
24.0 Capture/Compare/PWM Modules ............................................................................................................................................ 311
25.0 10-Bit Pulse-Width Modulation (PWM) Module ........................................................................................................................ 325
26.0 16-bit Pulse-Width Modulation (PWM) Module ........................................................................................................................ 332
27.0 Complementary Output Generator (COG) Modules................................................................................................................. 359
28.0 Configurable Logic Cell (CLC).................................................................................................................................................. 391
29.0 Operational Amplifier (OPA) Modules ...................................................................................................................................... 406
30.0 Programmable Ramp Generator (PRG) Module ...................................................................................................................... 413
31.0 Data Signal Modulator (DSM) .................................................................................................................................................. 427
32.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 440
33.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 493
34.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 524
35.0 Instruction Set Summary.......................................................................................................................................................... 526
36.0 Electrical Specifications............................................................................................................................................................ 540
37.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 575
38.0 Development Support............................................................................................................................................................... 599
39.0 Packaging Information.............................................................................................................................................................. 603
Appendix A: Data Sheet Revision History ......................................................................................................................................... 625
PIC16(L)F1777/8/9
DS40001819B-page 14 2015-2016 Microchip Technology Inc.
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2015-2016 Microchip Technology Inc. DS40001819B-page 15
PIC16(L)F1777/8/9
1.0 DEVICE OVERVIEW
The PIC16(L)F1777/8/9 are described within this data
sheet. See Table 2 for available package configurations.
Figure 1-1 shows a block diagram of the
PIC16(L)F1777/8/9 devices. Ta ble 1 -2 shows the pinout
descriptions.
Refer to Table 1-1 for peripherals available per device.
TABLE 1-1: DEVICE PERIPHERAL
SUMMARY
Peripheral
PIC16(L)F1778
PIC16(L)F1777/9
Analog-to-Digital Converter (ADC) ●●
Fixed Voltage Reference (FVR) ●●
Zero-Cross Detection (ZCD) ●●
Temperature Indicator ●●
Complementary Output Generator (COG)
COG1 ●●
COG2 ●●
COG3 ●●
COG4 ●
Programmable Ramp Generator (PRG)
PRG1 ●●
PRG2 ●●
PRG3 ●●
PRG4 ●
10-bit Digital-to-Analog Converter (DAC)
DAC1 ●●
DAC2 ●●
DAC5 ●●
DAC6 ●
5-bit Digital-to-Analog Converter (DAC)
DAC3 ●●
DAC4 ●●
DAC7 ●●
DAC8 ●
Capture/Compare/PWM (CCP/ECCP) Modules
CCP1 ●●
CCP2 ●●
CCP7 ●●
CCP8 ●
Comparators
C1 ●●
C2 ●●
C3 ●●
C4 ●●
C5 ●●
C6 ●●
C7 ●
C8 ●
Configurable Logic Cell (CLC)
CLC1 ●●
CLC2 ●●
CLC3 ●●
CLC4 ●●
Data Signal Modulator (DSM)
DSM1 ●●
DSM2 ●●
DSM3 ●●
DSM4 ●
Enhanced Universal Synchronous/Asynchronous
Receiver/Transmitter (EUSART)
EUSART ●●
Master Synchronous Serial Ports
MSSP ●●
Op Amps
OPA1 ●●
OPA2 ●●
OPA3 ●●
OPA4 ●
10-bit Pulse-Width Modulator (PWM)
PWM3 ●●
PWM4 ●●
PWM9 ●●
PWM10 ●
16-bit Pulse-Width Modulator (PWM)
PWM5 ●●
PWM6 ●●
PWM11 ●●
PWM12 ●
8-bit Timers
Timer0 ●●
Timer2 ●●
Timer4 ●●
Timer6 ●●
Timer8 ●●
16-bit Timers
Timer1 ●●
Timer3 ●●
Timer5 ●●
TABLE 1-1: DEVICE PERIPHERAL
SUMMARY
Peripheral
PIC16(L)F177 8
PIC16(L)F1777/9
PIC16(L)F1777/8/9
DS40001819B-page 16 2015-2016 Microchip Technology Inc.
1.1 Register and Bit nam ing
conventions
1.1.1 REGISTER NAMES
When there are multiple instances of the same
peripheral in a device, the peripheral control registers
will be depicted as the concatenation of a peripheral
identifier, peripheral instance, and control identifier.
The control registers section will show just one
instance of all the register names with an ‘x’ in the place
of the peripheral instance number. This naming
convention may also be applied to peripherals when
there is only one instance of that peripheral in the
device to maintain compatibility with other devices in
the family that contain more than one.
1.1.2 BIT NAMES
There are two variants for bit names:
• Short name: Bit function abbreviation
• Long name: Peripheral abbreviation + short name
1.1.2.1 Short Bit Names
Short bit names are an abbreviation for the bit function.
For example, some peripherals are enabled with the
EN bit. The bit names shown in the registers are the
short name variant.
Short bit names are useful when accessing bits in C
programs. The general format for accessing bits by the
short name is RegisterNamebits.ShortName. For
example, the enable bit, EN, in the COG1CON0 regis-
ter can be set in C programs with the instruction
COG1CON0bits.EN = 1.
Short names are generally not useful in assembly
programs because the same name may be used by
different peripherals in different bit positions. When this
occurs, during the include file generation, all instances
of that short bit name are appended with an underscore
plus the name of the register in which the bit resides to
avoid naming contentions.
1.1.2.2 Long Bit Names
Long bit names are constructed by adding a peripheral
abbreviation prefix to the short name. The prefix is
unique to the peripheral, thereby making every long bit
name unique. The long bit name for the COG1 enable
bit is the COG1 prefix, G1, appended with the enable
bit short name, EN, resulting in the unique bit name
G1EN.
Long bit names are useful in both C and assembly pro-
grams. For example, in C the COG1CON0 enable bit
can be set with the G1EN = 1 instruction. In assembly,
this bit can be set with the BSF COG1CON0,G1EN
instruction.
1.1.2.3 Bit Fields
Bit fields are two or more adjacent bits in the same
register. Bit fields adhere only to the short bit naming
convention. For example, the three Least Significant
bits of the COG1CON0 register contain the mode
control bits. The short name for this field is MD. There
is no long bit name variant. Bit field access is only
possible in C programs. The following example
demonstrates a C program instruction for setting the
COG1 to the Push-Pull mode:
COG1CON0bits.MD = 0x5;
Individual bits in a bit field can also be accessed with
long and short bit names. Each bit is the field name
appended with the number of the bit position within the
field. For example, the Most Significant mode bit has
the short bit name MD2 and the long bit name is
G1MD2. The following two examples demonstrate
assembly program sequences for setting the COG1 to
the Push-Pull mode:
EXAMPL E 1-1:
EXAMPL E 1-2:
1.1.3 REGISTER AND BIT NAMING
EXCEPTIONS
1.1.3.1 Status, Interrupt, and Mirror Bits
Status, interrupt enables, interrupt flags, and mirror bits
are contained in registers that span more than one
peripheral. In these cases, the bit name shown is
unique so there is no prefix or short name variant.
1.1.3.2 Legacy Peripherals
There are some peripherals that do not strictly adhere
to these naming conventions. Peripherals that have
existed for many years and are present in almost every
device are the exceptions. These exceptions were
necessary to limit the adverse impact of the new
conventions on legacy code. Peripherals that do
adhere to the new convention will include a table in the
registers section indicating the long name prefix for
each peripheral instance. Peripherals that fall into the
exception category will not have this table. These
peripherals include, but are not limited to, the following:
• EUSART
• MSSP
MOVLW ~(1<<G1MD1)
ANDWF COG1CON0,F
MOVLW 1<<G1MD2 | 1<<G1MD0
IORWF COG1CON0,F
BSF COG1CON0,G1MD2
BCF COG1CON0,G1MD1
BSF COG1CON0,G1MD0
2015-2016 Microchip Technology Inc. DS40001819B-page 17
PIC16(L)F1777/8/9
FIGURE 1-1: PIC16(L)F1777/8/9 BLOCK DIAGRAM
PORTA
PORTB
PORTC
Note 1: See applicable chapters for more information on peripherals.
CPU
Program
Flash Memory
RAM
Timing
Generation
LFINTOSC
Oscillator
MCLR
Figure 1-1
CLKIN
CLKOUT
ADC
10-Bit FVR
Temp .
Indicator EUSART
Comparators
MSSP
TimersTimers
DACs CCPs
PWMsOp Amps
HFINTOSC/
CLCs
COG
ZCD
DSMs
PRGs
8-bit 16-bit
DACs
5-bit
10-bit
PORTD
PORTE
PIC16(L)F1777/8/9
DS40001819B-page 18 2015-2016 Microchip Technology Inc.
TABLE 1-2: PIC16(L)F1778 PINOUT DESCRIPTION
Name Function Input
Type Output
Type Description
RA0/AN0/C1IN0-/C2IN0-/
C3IN0-/C4IN0-/C5IN0-/
C6IN0-/CLCIN0(1)
RA0 TTL/ST CMOS General purpose I/O.
AN0 AN — ADC Channel 0 input.
C1IN0- AN — Comparator 1 negative input.
C2IN0- AN — Comparator 2 negative input.
C3IN0- AN — Comparator 3 negative input.
C4IN0- AN — Comparator 4 negative input.
C5IN0- AN — Comparator 5 negative input.
C6IN0- AN — Comparator 6 negative input.
CLCIN0(1) TTL/ST — CLC input 0.
RA1/AN1/C1IN1-/C2IN1-/
C3IN1-/C4IN1-/PRG1IN0/
PRG2IN1/OPA1OUT/OPA2IN1+/
OPA2IN1-/CLCIN1(1)
RA1 TTL/ST CMOS General purpose I/O.
AN1 AN — Channel 1 input.
C1IN1- AN — Comparator 1 negative input.
C2IN1- AN — Comparator 2 negative input.
C3IN1- AN — Comparator 3 negative input.
C4IN1- AN — Comparator 4 negative input.
PRG1IN0 AN — Ramp generator 1 reference voltage input.
PRG2IN1 AN — Ramp generator 2 reference voltage input.
OPA1OUT — AN Operational amplifier 1 output.
OPA2IN1+ AN — Operational amplifier 2 non-inverting input.
OPA2IN1- AN — Operational amplifier 2 inverting input.
CLCIN1(1) TTL/ST — CLC input 1.
RA2/AN2/VREF-/DAC1REF0-/
DAC2REF0-/DAC3REF0-/
DAC4REF0-/DAC5REF0-/
DAC7REF0-/C1IN0+/C2IN0+/
C3IN0+/C4IN0+/C5IN0+/
C6IN0+/DAC1OUT1
RA2 TTL/ST CMOS General purpose I/O.
AN2 AN — ADC Channel 2 input.
VREF- AN — ADC negative reference.
DAC1REF0- AN — DAC1 negative reference.
DAC2REF0- AN — DAC2 negative reference.
DAC3REF0- AN — DAC3 negative reference.
DAC4REF0- AN — DAC4 negative reference.
DAC5REF0- AN — DAC5 negative reference.
DAC7REF0- AN — DAC7 negative reference.
C1IN0+ AN — Comparator 1 positive input.
C2IN0+ AN — Comparator 2 positive input.
C3IN0+ AN — Comparator 3 positive input.
C4IN0+ AN — Comparator 4 positive input.
C5IN0+ AN — Comparator 5 positive input.
C6IN0+ AN — Comparator 6 positive input.
DAC1OUT1 — AN DAC1 voltage output.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HP = High Power XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with
the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
2015-2016 Microchip Technology Inc. DS40001819B-page 19
PIC16(L)F1777/8/9
RA3/AN3/VREF+/DAC1REF0+/
DAC2REF0+/DAC3REF0+/
DAC4REF0+/DAC5REF0+/
DAC7REF0+/C1IN1+/MD1CL
RA3 TTL/ST CMOS General purpose I/O.
AN3 AN — ADC Channel 3 input.
VREF+ AN — ADC positive reference.
DAC1REF0+ AN — DAC1 positive reference.
DAC2REF0+ AN — DAC2 positive reference.
DAC3REF0+ AN — DAC3 positive reference.
DAC4REF0+ AN — DAC4 positive reference.
DAC5REF0+ AN — DAC5 positive reference.
DAC7REF0+ AN — DAC7 positive reference.
C1IN1+ AN — Comparator 1 positive input.
MD1CL(1) TTL/ST — Data signal modulator 1 low carrier input.
RA4/OPA1IN0+/PRG1R/
MD1CH/DAC4OUT1/T0CKI
RA4 TTL/ST CMOS General purpose I/O.
OPA1IN0+ AN — Operational Amplifier 1 non-inverting input.
PRG1R(1) TTL/ST — Ramp generator set_rising input.
MD1CH(1) TTL/ST — Data signal modulator 1 high carrier input.
DAC4OUT1 — AN DAC4 voltage output.
T0CKI(1) TTL/ST — Timer0 clock input.
RA5/AN4/OPA1IN0-/
DAC2OUT1/PRG1F/
MD1MOD/SS
RA5 TTL/ST CMOS General purpose I/O.
AN4 AN — ADC Channel 4 input.
OPA1IN0- AN — Operational amplifier 1 inverting input.
DAC2OUT1 — AN DAC2 voltage output.
PRG1F(1) TTL/ST — Ramp generator set_falling input.
MD1MOD(1) TTL/ST — Data signal modulator modulation input.
SS ST — Slave Select input.
RA6/CLKOUT/C6IN1+/OSC2 RA6 TTL/ST CMOS General purpose I/O.
CLKOUT — CMOS FOSC/4 output.
C6IN1+ AN — Comparator 6 positive input.
OSC2 XTAL — Crystal/Resonator (LP, XT, HS modes).
RA7/CLKIN/OSC1 RA7 TTL/ST CMOS General purpose I/O.
CLKIN TTL/ST — CLC input.
OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).
RB0/AN12/ZCD/HIB0/C2IN1+/
COG1IN
RB0 TTL/ST CMOS General purpose I/O.
AN12 AN — ADC Channel 12 input.
ZCD AN — Zero-cross detection input.
HIB0 HP HP High-Power output.
C2IN1+ AN — Comparator 2 positive input.
COG1IN(1) TTL/ST — Complementary output generator 1 input.
TABLE 1-2: PIC16(L)F1778 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HP = High Power XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with
the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
PIC16(L)F1777/8/9
DS40001819B-page 20 2015-2016 Microchip Technology Inc.
RB1/AN10/PRG1IN1/PRG2IN0/
HIB1/C1IN3-/C2IN3-/C3IN3-/
C4IN3-/OPA2OUT/OPA1IN1+/
OPA1IN1-/COG2IN
RB1 TTL/ST CMOS General purpose I/O.
AN10 AN — ADC Channel 10 input.
PRG1IN1 AN — Ramp generator 1 reference voltage input.
PRG2IN0 AN — Ramp generator 2 reference voltage input.
HIB1 HP HP High-Power output.
C1IN3- AN — Comparator 1 negative input.
C2IN3- AN — Comparator 2 negative input.
C3IN3- AN — Comparator 3 negative input.
C4IN3- AN — Comparator 4 negative input.
OPA2OUT — AN Operational amplifier 2 output.
OPA1IN1+ AN — Operational amplifier 1 non-inverting input.
OPA1IN1- AN — Operational amplifier 1 inverting input.
COG2IN(1) TTL/ST — Complementary output generator 2 input.
RB2/AN8/OPA2IN0-/
DAC3OUT1/COG3IN
RB2 TTL/ST CMOS General purpose I/O.
AN8 AN — ADC Channel 8 input.
OPA2IN0- AN — Operational amplifier 2 inverting input.
DAC3OUT1 — AN DAC3 voltage output.
COG3IN(1) TTL/ST — Complementary output generator 3 input.
RB3/AN9/C1IN2-/C2IN2-/
C3IN2-/OPA2IN0+/MD3CL
RB3 TTL/ST CMOS General purpose I/O.
AN9 AN — ADC Channel 9 input.
C1IN2- AN — Comparator 1 negative input.
C2IN2- AN — Comparator 2 negative input.
C3IN2- AN — Comparator 3 negative input.
OPA2IN0+ AN Operational amplifier 2 non-inverting input.
MD3CL(1) TTL/ST — Data signal modulator 3 low carrier input.
RB4/AN11/C3IN1+/T5G/MD3CH RB4 TTL/ST CMOS General purpose I/O.
AN11 AN — ADC Channel 11 input.
C3IN1+ AN — Comparator 3 positive input.
T5G(1) TTL/ST — Timer5 gate input.
MD3CH(1) TTL/ST — Data signal modulator 3 high carrier input.
RB5/AN13/DAC5REF1-/
DAC7REF1-/C4IN2-/T1G/CCP7/
MD3MOD
RB5 TTL/ST CMOS General purpose I/O.
AN13 AN — ADC Channel 11 input.
DAC5REF1- AN — DAC5 negative reference.
DAC7REF1- AN — DAC7 negative reference.
C4IN2- AN — Comparator 4 negative input.
T1G(1) TTL/ST — Timer1 gate input.
CCP7(1) TTL/ST — CCP7 capture input.
MD3MOD(1) TTL/ST — Data signal modulator modulation input.
TABLE 1-2: PIC16(L)F1778 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HP = High Power XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with
the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
2015-2016 Microchip Technology Inc. DS40001819B-page 21
PIC16(L)F1777/8/9
RB6/DAC5REF1+/DAC7REF1+/
C4IN1+/CLCIN2/ICSPCLK
RB6 TTL/ST CMOS General purpose I/O.
DAC5REF1+ AN — DAC5 positive reference.
DAC7REF1+ AN — DAC7 positive reference.
C4IN1+ AN — Comparator 2 positive input.
CLCIN2(1) TTL/ST — CLC input 2.
ICSPCLK ST — Serial Programming Clock.
RB7/C5IN1+/DAC1OUT2/
DAC2OUT2/DAC3OUT2/
DAC4OUT2/DAC5OUT2/
DAC7OUT2/T6IN/CLCIN3/
ICSPDAT
RB7 TTL/ST CMOS General purpose I/O.
C5IN1+ AN — Comparator 5 positive input.
DAC1OUT2 — AN DAC1 voltage output.
DAC2OUT2 — AN DAC2 voltage output.
DAC3OUT2 — AN DAC3 voltage output.
DAC4OUT2 — AN DAC4 voltage output.
DAC5OUT2 — AN DAC5 voltage output.
DAC7OUT2 — AN DAC7 voltage output.
T6IN(1) TTL/ST — Timer6 gate input.
CLCIN3(1) TTL/ST — CLC input 3.
ICSPDAT ST CMOS ICSP™ Data I/O.
RC0/DAC5OUT1/T1CKI/T3CKI/
T3G/SOSCO
RC0 TTL/ST CMOS General purpose I/O.
DAC5OUT1 — AN DAC5 voltage output.
T1CKI(1) AN — Comparator 4 negative input.
T3CKI(1) TTL/ST — Timer3 clock input.
T3G(1) TTL/ST — Timer3 gate input.
SOSCO — XTAL Secondary oscillator output.
RC1/DAC7OUT1/PRG2R/CCP2/
SOSCI
RC1 TTL/ST CMOS General purpose I/O.
DAC7OUT1 — AN DAC7 voltage output.
PRG2R(1) TTL/ST — Ramp generator set_rising input.
CCP2(1) TTL/ST — CCP2 capture input.
SOSCI XTAL — Secondary oscillator input.
RC2/AN14/C5IN2-/C6IN2-/
PRG2F/CCP1/T5CKI
RC2 TTL/ST CMOS General purpose I/O.
AN14 AN — ADC Channel 14 input.
C5IN2- AN — Comparator 5 negative input.
C6IN2- AN — Comparator 6 negative input.
PRG2F(1) TTL/ST — Ramp generator set_falling input.
CCP1(1) TTL/ST — CCP1 capture input.
T5CKI(1) TTL/ST — Timer5 clock input.
TABLE 1-2: PIC16(L)F1778 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HP = High Power XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with
the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
PIC16(L)F1777/8/9
DS40001819B-page 22 2015-2016 Microchip Technology Inc.
RC3/AN15/C1IN4-/C2IN4-/
C3IN4-/C4IN4-/C5IN4-/C6IN4-/
T2IN//MD2CL/SCL
RC3 TTL/ST CMOS General purpose I/O.
AN15 AN — ADC Channel 15 input.
C1IN4- AN — Comparator 1 negative input.
C2IN4- AN — Comparator 2 negative input.
C3IN4- AN — Comparator 3 negative input.
C4IN4- AN — Comparator 4 negative input.
C5IN4- AN — Comparator 5 negative input.
C6IN4- AN — Comparator 6 negative input.
T2IN(1) TTL/ST — Timer2 gate input.
MD2CL(1) TTL/ST — Data signal modulator 2 low carrier input.
SCL I2CODI
2C clock.
RC4/AN16/C5IN3-/C6IN3-/T8IN/
PRG3R/MD2CH/SDA
RC4 TTL/ST CMOS General purpose I/O.
AN16 AN — ADC Channel 16 input.
C5IN3- AN — Comparator 5 negative input.
C6IN3- AN — Comparator 6 negative input.
T8IN(1) TTL/ST — Timer8 gate input.
PRG3R(1) TTL/ST — Ramp generator set_rising input.
MD2CH(1) TTL/ST — Data signal modulator 2 high carrier input.
SDA I2CODI
2C data input/output.
RC5/AN17/OPA3IN0+/T4IN/
PRG3F/MD2MOD
RC5 TTL/ST CMOS General purpose I/O.
AN17 AN — ADC Channel 17 input.
OPA3IN0+ AN — Operational amplifier 3 inverting input.
T4IN(1) TTL/ST — Timer4 gate input.
PRG3F(1) TTL/ST — Ramp generator set_falling input.
MD2MOD(1) TTL/ST — Data signal modulator modulation input.
RC6/AN18/PRG3IN0/C5IN1-/
C6IN1-/OPA3OUT
RC6 TTL/ST CMOS General purpose I/O.
AN18 AN — ADC Channel 18 input.
PRG3IN0 AN — Ramp generator 3 reference voltage input.
C5IN1- AN — Comparator 5 negative input.
C6IN1- AN — Comparator 6 negative input.
OPA3OUT — AN Operational amplifier 3 output.
RC7/AN19/OPA3IN0- RC7 TTL/ST CMOS General purpose I/O.
AN19 AN — ADC Channel 19 input.
OPA3IN0- AN — Operational amplifier 3 non-inverting input.
RE3/MCLR RE3 TTL/ST CMOS General purpose input.
MCLR ST — Master clear input.
VDD VDD Power — Positive supply.
VSS VSS Power — Ground reference.
TABLE 1-2: PIC16(L)F1778 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HP = High Power XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with
the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
2015-2016 Microchip Technology Inc. DS40001819B-page 23
PIC16(L)F1777/8/9
OUT(2) C1OUT CMOS Comparator 1 output.
C2OUT CMOS Comparator 2 output.
C3OUT CMOS Comparator 3 output.
C4OUT CMOS Comparator 4 output.
C5OUT CMOS Comparator 5 output.
C6OUT CMOS Comparator 6 output.
CCP1 CMOS Compare/PWM1 output.
CCP2 CMOS Compare/PWM2 output.
CCP7 CMOS Compare/PWM7 output.
MD1OUT CMOS Data signal modulator 1 output.
MD2OUT CMOS Data signal modulator 2 output.
MD3OUT CMOS Data signal modulator 3 output.
PWM3OUT CMOS PWM3 output.
PWM4OUT CMOS PWM4 output.
PWM5OUT CMOS PWM5 output.
PWM6OUT CMOS PWM6 output.
PWM9OUT CMOS PWM9 output.
PWM11OUT CMOS PWM11 output.
COG1A CMOS Complementary output generator 1 output A.
COG1B CMOS Complementary output generator 1 output B.
COG1C CMOS Complementary output generator 1 output C.
COG1D CMOS Complementary output generator 1 output D.
COG2A CMOS Complementary output generator 2 output A.
COG2B CMOS Complementary output generator 2 output B.
COG2C CMOS Complementary output generator 2 output C.
COG2D CMOS Complementary output generator 2 output D.
COG3A CMOS Complementary output generator 3 output A.
COG3B CMOS Complementary output generator 3 output B.
COG3C CMOS Complementary output generator 3 output C.
COG3D CMOS Complementary output generator 3 output D.
SDA(3) OD I2C data output.
SCK CMOS SPI clock output.
SCL(3) OD I2C clock output.
SDO CMOS SPI data output.
TX CMOS EUSART asynchronous TX data out.
CK CMOS EUSART synchronous clock out.
DT(3) CMOS EUSART synchronous data output.
CLC1OUT CMOS Configurable logic cell 1 output.
CLC2OUT CMOS Configurable logic cell 2 output.
CLC3OUT CMOS Configurable logic cell 3 output.
CLC4OUT CMOS Configurable logic cell 4 output.
TABLE 1-2: PIC16(L)F1778 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HP = High Power XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with
the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
PIC16(L)F1777/8/9
DS40001819B-page 24 2015-2016 Microchip Technology Inc.
TABLE 1-3: PIC16(L)F1777/9 PINOUT DESCRIPTION
Name Function Input
Type Output
Type Description
RA0/AN0/C1IN0-/C2IN0-/
C3IN0-/C4IN0-/C5IN0-/
C6IN0-/C7IN0-/C8IN0-/CLCIN0
RA0 TTL/ST CMOS General purpose I/O.
AN0 AN — ADC Channel 0 input.
C1IN0- AN — Comparator 1 negative input.
C2IN0- AN — Comparator 2 negative input.
C3IN0- AN — Comparator 3 negative input.
C4IN0- AN — Comparator 4 negative input.
C5IN0- AN — Comparator 5 negative input.
C6IN0- AN — Comparator 6 negative input.
C7IN0- AN — Comparator 7 negative input.
C8IN0- AN — Comparator 8 negative input.
CLCIN0(1) TTL/ST — CLC input 0.
RA1/AN1/C1IN1-/C2IN1-/
C3IN1-/C4IN1-/PRG1IN0/
PRG2IN1/OPA1OUT/OPA2IN1+/
OPA2IN1-/CLCIN1
RA1 TTL/ST CMOS General purpose I/O.
AN1 AN — Channel 1 input.
C1IN1- AN — Comparator 1 negative input.
C2IN1- AN — Comparator 2 negative input.
C3IN1- AN — Comparator 3 negative input.
C4IN1- AN — Comparator 4 negative input.
PRG1IN0 AN — Ramp generator 1 reference voltage input.
PRG2IN1 AN — Ramp generator 2 reference voltage input.
OPA1OUT — AN Operational amplifier 1 output.
OPA2IN1+ AN — Operational amplifier 2 non-inverting input.
OPA2IN1- AN — Operational amplifier 2 inverting input.
CLCIN1(1) TTL/ST — CLC input 0.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HP = High Power XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with
the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
2015-2016 Microchip Technology Inc. DS40001819B-page 25
PIC16(L)F1777/8/9
RA2/AN2/DAC1REF0-/
DAC2REF0-/DAC3REF0-/
DAC4REF0-/DAC5REF0-/
DAC6REF0-/DAC7REF0-/
DAC8REF0-/C1IN0+/C2IN0+/
C3IN0+/C4IN0+/C5IN0+/
C6IN0+/C7IN0+/C8IN0+/
DAC1OUT1
RA2 TTL/ST CMOS General purpose I/O.
AN2 AN — ADC Channel 2 input.
DAC1REF0- AN — DAC1 negative reference.
DAC2REF0- AN — DAC2 negative reference.
DAC3REF0- AN — DAC3 negative reference.
DAC4REF0- AN — DAC4 negative reference.
DAC5REF0- AN — DAC5 negative reference.
DAC6REF0- AN — DAC6 negative reference.
DAC7REF0- AN — DAC7 negative reference.
DAC8REF0- AN — DAC8 negative reference.
C1IN0+ AN — Comparator 1 positive input.
C2IN0+ AN — Comparator 2 positive input.
C3IN0+ AN — Comparator 3 positive input.
C4IN0+ AN — Comparator 4 positive input.
C5IN0+ AN — Comparator 5 positive input.
C6IN0+ AN — Comparator 6 positive input.
C7IN0+ AN — Comparator 7 positive input.
C8IN0+ AN — Comparator 8 positive input.
DAC1OUT1 — AN DAC1 voltage output.
RA3/AN3/DAC1REF0+/
DAC2REF0+/DAC3REF0+/
DAC4REF0+/DAC5REF0+/
DAC6REF0+/DAC7REF0+/
DAC8REF0+/C1IN1+/MD1CL
RA3 TTL/ST CMOS General purpose I/O.
AN3 AN — ADC Channel 3 input.
VREF+ AN — ADC positive reference.
DAC1REF0+ AN — DAC1 positive reference.
DAC2REF0+ AN — DAC2 positive reference.
DAC3REF0+ AN — DAC3 positive reference.
DAC4REF0+ AN — DAC4 positive reference.
DAC5REF0+ AN — DAC5 positive reference.
DAC6REF0+ AN — DAC6 positive reference.
DAC7REF0+ AN — DAC7 positive reference.
DAC8REF0+ AN — DAC8 positive reference.
C1IN1+ AN — Comparator 1 positive input.
MD1CL(1) TTL/ST — Data signal modulator 1 low carrier input.
RA4/OPA1IN0+/PRG1R/MD1CH RA4 TTL/ST CMOS General purpose I/O.
OPA1IN0+ AN — Operational Amplifier 1 non-inverting input.
PRG1R(1) TTL/ST — Ramp generator set_rising input.
MD1CH(1) TTL/ST — Data signal modulator 1 high carrier input.
TABLE 1-3: PIC16(L)F1777/9 PINOUT DE SCRIPTION (CONT IN U ED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HP = High Power XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with
the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
PIC16(L)F1777/8/9
DS40001819B-page 26 2015-2016 Microchip Technology Inc.
RA5/AN4/OPA1IN0-/
DAC2OUT1/PRG1F/
MD1MOD/SS
RA5 TTL/ST CMOS General purpose I/O.
AN4 AN — ADC Channel 4 input.
OPA1IN0- AN — Operational amplifier 1 inverting input.
DAC2OUT1 — AN DAC2 voltage output.
PRG1F(1) TTL/ST — Ramp generator set_falling input.
MD1MOD(1) TTL/ST — Data signal modulator modulation input.
SS ST — Slave Select input.
RA6/CLKOUT/C6IN1+/OSC2 RA6 TTL/ST CMOS General purpose I/O.
CLKOUT — CMOS FOSC/4 output.
C6IN1+ AN — Comparator 6 positive input.
OSC2 XTAL — Crystal/Resonator (LP, XT, HS modes).
RA7/CLKIN/OSC1 RA7 TTL/ST CMOS General purpose I/O.
CLKIN TTL/ST — CLC input.
OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).
RB0/AN12/ZCD/HIB0/C2IN1+/
CCP8/COG1IN/MD4CL/
INT
RB0 TTL/ST CMOS General purpose I/O.
AN12 AN — ADC Channel 12 input.
ZCD AN — Zero-cross detection input.
HIB0 HP HP High-Power output.
C2IN1+ AN — Comparator 2 positive input.
CCP8(1) TTL/ST — CCP8 capture input.
COG1IN(1) TTL/ST — Complementary output generator 1 input.
MD4CL(1) TTL/ST — Data signal modulator 4 low carrier input.
INT TTL/ST — External interrupt.
RB1/AN10/PRG1IN1/PRG2IN0/
PRG4R/HIB1/C1IN3-/C2IN3-/
C3IN3-/C4IN3-/OPA2OUT/
OPA1IN1+/OPA1IN1-/COG2IN/
MD4CH
RB1 TTL/ST CMOS General purpose I/O.
AN10 AN — ADC Channel 10 input.
PRG1IN1 AN — Ramp generator 1 reference voltage input.
PRG2IN0 AN — Ramp generator 2 reference voltage input.
PRG4R(1) TTL/ST — Ramp generator set_rising input.
HIB1 HP HP High-Power output.
C1IN3- AN — Comparator 1 negative input.
C2IN3- AN — Comparator 2 negative input.
C3IN3- AN — Comparator 3 negative input.
C4IN3- AN — Comparator 4 negative input.
OPA2OUT — AN Operational amplifier 2 output.
OPA1IN1+ AN — Operational amplifier 1 non-inverting input.
OPA1IN1- AN — Operational amplifier 1 inverting input.
COG2IN(1) TTL/ST — Complementary output generator 2 input.
MD4CH(1) TTL/ST — Data signal modulator 4 high carrier input.
TABLE 1-3: PIC16(L)F1777/9 PINOUT DESCRIPT IO N (CO NT IN UED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HP = High Power XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with
the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
2015-2016 Microchip Technology Inc. DS40001819B-page 27
PIC16(L)F1777/8/9
RB2/AN8/OPA2IN0-/
DAC3OUT1/PRG4F/COG3IN/
MD4MOD
RB2 TTL/ST CMOS General purpose I/O.
AN8 AN — ADC Channel 8 input.
OPA2IN0- AN — Operational amplifier 2 inverting input.
DAC3OUT1 — AN DAC3 voltage output.
PRG4F(1) TTL/ST — Ramp generator set_falling input.
COG3IN(1) TTL/ST — Complementary output generator 3 input.
MD4MOD(1) TTL/ST — Data signal modulator modulation input.
RB3/AN9/C1IN2-/C2IN2-/
C3IN2-/OPA2IN0+/MD3CL
RB3 TTL/ST CMOS General purpose I/O.
AN9 AN — ADC Channel 9 input.
C1IN2- AN — Comparator 1 negative input.
C2IN2- AN — Comparator 2 negative input.
C3IN2- AN — Comparator 3 negative input.
OPA2IN0+ AN Operational amplifier 2 non-inverting input.
MD3CL(1) TTL/ST — Data signal modulator 3 low carrier input.
RB4/AN11/C3IN1+/MD3CH RB4 TTL/ST CMOS General purpose I/O.
AN11 AN — ADC Channel 11 input.
C3IN1+ AN — Comparator 3 positive input.
MD3CH(1) TTL/ST — Data signal modulator 3 high carrier input.
RB5/AN13/DAC5REF1-/
DAC7REF1-/C4IN2-/CCP7/
MD3MOD
RB5 TTL/ST CMOS General purpose I/O.
AN13 AN — ADC Channel 11 input.
DAC5REF1- AN — DAC5 negative reference.
DAC7REF1- AN — DAC7 negative reference.
C4IN2- AN — Comparator 4 negative input.
CCP7(1) TTL/ST — CCP7 capture input.
MD3MOD(1) TTL/ST — Data signal modulator modulation input.
RB6/DAC5REF1+/DAC7REF1+/
C4IN1+/CLCIN2/ICSPCLK
RB6 TTL/ST CMOS General purpose I/O.
DAC5REF1+ AN — DAC5 positive reference.
DAC7REF1+ AN — DAC7 positive reference.
C4IN1+ AN — Comparator 2 positive input.
CLCIN2(1) TTL/ST — CLC input 2.
ICSPCLK ST — Serial Programming Clock.
TABLE 1-3: PIC16(L)F1777/9 PINOUT DE SCRIPTION (CONT IN U ED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HP = High Power XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with
the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
PIC16(L)F1777/8/9
DS40001819B-page 28 2015-2016 Microchip Technology Inc.
RB7/C5IN1+/DAC1OUT2/
DAC2OUT2/DAC3OUT2/
DAC4OUT2/DAC5OUT2/
DAC6OUT2/DAC7OUT2/
DAC8OUT2/T6IN/CLCIN3/
ICSPDAT
RB7 TTL/ST CMOS General purpose I/O.
C5IN1+ AN — Comparator 5 positive input.
DAC1OUT2 — AN DAC1 voltage output.
DAC2OUT2 — AN DAC2 voltage output.
DAC3OUT2 — AN DAC3 voltage output.
DAC4OUT2 — AN DAC4 voltage output.
DAC5OUT2 — AN DAC5 voltage output.
DAC6OUT2 — AN DAC6 voltage output.
DAC7OUT2 — AN DAC7 voltage output.
DAC8OUT2 — AN DAC8 voltage output.
T6IN(1) TTL/ST — Timer6 gate input.
CLCIN3(1) TTL/ST — CLC input 3.
ICSPDAT ST CMOS ICSP™ Data I/O.
RC0/DAC5OUT1/T1CKI/T3CKI/
T3G/SOSCO
RC0 TTL/ST CMOS General purpose I/O.
DAC5OUT1 — AN DAC5 voltage output.
T1CKI(1) AN — Comparator 4 negative input.
T3CKI(1) TTL/ST — Timer3 clock input.
T3G(1) TTL/ST — Timer3 gate input.
SOSCO — XTAL Secondary oscillator output.
RC1/DAC7OUT1/PRG2R/CCP2/
SOSCI
RC1 TTL/ST CMOS General purpose I/O.
DAC7OUT1 — AN DAC7 voltage output.
PRG2R(1) TTL/ST — Ramp generator set_rising input.
CCP2(1) TTL/ST — CCP2 capture input.
SOSCI XTAL — Secondary oscillator input.
RC2/AN14/C5IN2-/C6IN2-/
PRG2F/CCP1
RC2 TTL/ST CMOS General purpose I/O.
AN14 AN — ADC Channel 14 input.
C5IN2- AN — Comparator 5 negative input.
C6IN2- AN — Comparator 6 negative input.
RC3/AN15/C1IN4-/C2IN4-/
C3IN4-/C4IN4-/C5IN4-/C6IN4-/
C7IN4-/C8IN4-/T2IN/MD2CL/
SCL
RC3 TTL/ST CMOS General purpose I/O.
AN15 AN — ADC Channel 15 input.
C1IN4- AN — Comparator 1 negative input.
C2IN4- AN — Comparator 2 negative input.
C3IN4- AN — Comparator 3 negative input.
C4IN4- AN — Comparator 4 negative input.
C5IN4- AN — Comparator 5 negative input.
C6IN4- AN — Comparator 6 negative input.
C7IN4- AN — Comparator 7 negative input.
C8IN4- AN — Comparator 8 negative input.
T2IN(1) TTL/ST — Timer2 gate input.
MD2CL(1) TTL/ST — Data signal modulator 2 low carrier input.
SCL I2CODI
2C clock.
TABLE 1-3: PIC16(L)F1777/9 PINOUT DESCRIPT IO N (CO NT IN UED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HP = High Power XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with
the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
2015-2016 Microchip Technology Inc. DS40001819B-page 29
PIC16(L)F1777/8/9
RC4/AN16/C5IN3-/C6IN3-/
PRG3R/T8IN/MD2CH/SDA
RC4 TTL/ST CMOS General purpose I/O.
AN16 AN — ADC Channel 16 input.
C5IN3- AN — Comparator 5 negative input.
C6IN3- AN — Comparator 6 negative input.
PRG3R(1) TTL/ST — Ramp generator set_rising input.
T8IN(1) TTL/ST — Timer8 gate input.
MD2CH(1) TTL/ST — Data signal modulator 2 high carrier input.
SDA I2CODI
2C data input/output.
RC5/AN17/OPA3IN0+/PRG3F/
T4IN/MD2MOD
RC5 TTL/ST CMOS General purpose I/O.
AN17 AN — ADC Channel 17 input.
OPA3IN0 AN — Operational amplifier 3 inverting input.
PRG3F(1) TTL/ST — Ramp generator set_falling input.
T4IN(1) TTL/ST — Timer4 gate input.
MD2MOD(1) TTL/ST — Data signal modulator modulation input.
RC6/AN18/PRG3IN0/PRG4IN1/
C5IN1-/C6IN1-/C7IN1-/C8IN1-/
OPA3OUT/OPA4IN1+/OPA4IN1-
RC6 TTL/ST CMOS General purpose I/O.
AN18 AN — ADC Channel 18 input.
PRG3IN0 AN — Ramp generator 3 reference voltage input.
PRG4IN1 AN — Ramp generator 4 reference voltage input.
C5IN1- AN — Comparator 5 negative input.
C6IN1- AN — Comparator 6 negative input.
C7IN1- AN — Comparator 7 negative input.
C8IN1- AN — Comparator 8 negative input.
OPA3OUT — AN Operational amplifier 3 output.
OPA4IN1+ AN — Operational amplifier 4 non-inverting input.
OPA4IN1- AN — Operational amplifier 4 inverting input.
RC7/AN19/OPA3IN0- RC7 TTL/ST CMOS General purpose I/O.
AN19 AN — ADC Channel 19 input.
OPA3IN0- AN — Operational amplifier 3 non-inverting input.
RD0/AN20/OPA4IN0+ RD0 TTL/ST CMOS General purpose I/O.
AN20 AN — ADC Channel 20 input.
OPA4IN0+ AN — Operational amplifier 4 non-inverting input.
TABLE 1-3: PIC16(L)F1777/9 PINOUT DE SCRIPTION (CONT IN U ED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HP = High Power XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with
the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
PIC16(L)F1777/8/9
DS40001819B-page 30 2015-2016 Microchip Technology Inc.
RD1/AN21/PRG3IN1/PRG4IN0/
C1IN4-/C2IN4-/C3IN4-/C4IN4-/
C5IN4-/C6IN4-/C7IN4-/C8IN4-/
OPA4OUT/OPA3IN1+/OPA3IN1-
RD1 TTL/ST CMOS General purpose I/O.
AN21 AN — ADC Channel 21 input.
PRG3IN1 AN — Ramp generator 3 reference voltage input.
PRG4IN0 AN — Ramp generator 4 reference voltage input.
C1IN4- AN — Comparator 1 negative input.
C2IN4- AN — Comparator 2 negative input.
C3IN4- AN — Comparator 3 negative input.
C4IN4- AN — Comparator 4 negative input.
C5IN4- AN — Comparator 5 negative input.
C6IN4- AN — Comparator 6 negative input.
C7IN4- AN — Comparator 7 negative input.
C8IN4- AN — Comparator 8 negative input.
OPA4OUT — AN Operational amplifier 4 output.
OPA3IN1+ AN — Operational amplifier 3 non-inverting input.
OPA3IN1- AN — Operational amplifier 3 inverting input.
RD2/AN22/DAC4OUT1/
OPA4IN0-
RD2 TTL/ST CMOS General purpose I/O.
AN22 AN — ADC Channel 22 input.
DAC4OUT1 — AN DAC4 voltage output.
OPA4IN0- AN — Operational amplifier 4 inverting input.
RD3/AN23/C8IN2- RD3 TTL/ST CMOS General purpose I/O.
AN23 AN — ADC Channel 23 input.
C8IN2- AN — Comparator 8 negative input.
RD4/AN24/C7IN2- RD4 TTL/ST CMOS General purpose I/O.
AN24 AN — ADC Channel 24 input.
C7IN2- AN — Comparator 8 negative input.
RD5/AN25/C7IN3-/C8IN3- RD5 TTL/ST CMOS General purpose I/O.
AN25 AN — ADC Channel 25 input.
C7IN3- AN — Comparator 7 negative input.
C8IN3- AN — Comparator 8 negative input.
RD6/AN26/C7IN1+ RD6 TTL/ST CMOS General purpose I/O.
AN26 AN — ADC Channel 26 input.
C7IN1+ AN — Comparator 7 positive input.
RD7/AN27/C8IN1+ RD7 TTL/ST CMOS General purpose I/O.
AN27 AN — ADC Channel 27 input.
C8IN1+ AN — Comparator 8 positive input.
RE0/AN5/DAC6REF1+/
DAC8REF1+
RE0 TTL/ST CMOS General purpose I/O.
AN5 AN — ADC Channel 5 input.
DAC6REF1+ AN — DAC6 positive reference.
DAC8REF1+ AN — DAC8 positive reference.
TABLE 1-3: PIC16(L)F1777/9 PINOUT DESCRIPT IO N (CO NT IN UED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HP = High Power XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with
the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
2015-2016 Microchip Technology Inc. DS40001819B-page 31
PIC16(L)F1777/8/9
RE1/AN6/DAC6OUT1/
DAC6REF1-/DAC8REF1-
RE1 TTL/ST CMOS General purpose I/O.
AN6 AN — ADC Channel 6 input.
DAC6OUT1 — AN DAC6 voltage output.
DAC6REF1- AN — DAC6 negative reference.
DAC8REF1- AN — DAC8 negative reference.
RE2/AN7/DAC8OUT1 RE2 TTL/ST CMOS General purpose I/O.
AN7 AN — ADC Channel 7 input.
DAC8OUT1 — AN DAC8 voltage output.
RE3/MCLR/VPP RE3 TTL/ST CMOS General purpose input.
MCLR ST — Master clear input.
VDD VDD Power — Positive supply.
VSS VSS Power — Ground reference.
OUT(2) C1OUT CMOS Comparator 1 output.
C2OUT CMOS Comparator 2 output.
C3OUT CMOS Comparator 3 output.
C4OUT CMOS Comparator 4 output.
C5OUT CMOS Comparator 5 output.
C6OUT CMOS Comparator 6 output.
C7OUT CMOS Comparator 7 output.
C8OUT CMOS Comparator 8 output.
CCP1 CMOS Compare/PWM1 output.
CCP2 CMOS Compare/PWM2 output.
CCP7 CMOS Compare/PWM7 output.
CCP8 CMOS Compare/PWM8 output.
MD1OUT CMOS Data signal modulator 1 output.
MD2OUT CMOS Data signal modulator 2 output.
MD3OUT CMOS Data signal modulator 3 output.
MD4OUT CMOS Data signal modulator 4 output.
PWM3OUT CMOS PWM3 output.
PWM4OUT CMOS PWM4 output.
PWM5OUT CMOS PWM5 output.
PWM6OUT CMOS PWM6 output.
PWM9OUT CMOS PWM9 output.
PWM10OUT CMOS PWM10 output.
PWM11OUT CMOS PWM11 output.
PWM12OUT CMOS PWM12 output.
COG1A CMOS Complementary output generator 1 output A.
COG1B CMOS Complementary output generator 1 output B.
COG1C CMOS Complementary output generator 1 output C.
COG1D CMOS Complementary output generator 1 output D.
COG2A CMOS Complementary output generator 2 output A.
TABLE 1-3: PIC16(L)F1777/9 PINOUT DE SCRIPTION (CONT IN U ED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HP = High Power XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with
the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
PIC16(L)F1777/8/9
DS40001819B-page 32 2015-2016 Microchip Technology Inc.
1.2 Peripher al Connection Matrix
Input selection multiplexers on many of the peripherals
enable selecting the output of another peripheral such
that the signal path is contained entirely within the
device. Although the peripheral output can also be
routed to a pin, with the PPS selection feature, it is not
necessary to do so. Tab le 1-4 shows all the possible
inter-peripheral signal connections. Please refer to cor-
responding peripheral section to obtain the multiplexer
selection codes for the desired connection.
OUT(2) (Cont.) COG2B CMOS Complementary output generator 2 output B.
COG2C CMOS Complementary output generator 2 output C.
COG2D CMOS Complementary output generator 2 output D.
COG3A CMOS Complementary output generator 3 output A.
COG3B CMOS Complementary output generator 3 output B.
COG3C CMOS Complementary output generator 3 output C.
COG3D CMOS Complementary output generator 3 output D.
COG4A CMOS Complementary output generator 4 output A.
COG4B CMOS Complementary output generator 4 output B.
COG4C CMOS Complementary output generator 4 output C.
COG4D CMOS Complementary output generator 4 output D.
SDA(3) OD I2C data output.
SCK CMOS SPI clock output.
SCL(3) OD I2C clock output.
SDO CMOS SPI data output.
TX CMOS EUSART asynchronous TX data out.
CK CMOS EUSART synchronous clock out.
DT(3) CMOS EUSART synchronous data output.
CLC1OUT CMOS Configurable logic cell 1 output.
CLC2OUT CMOS Configurable logic cell 2 output.
CLC3OUT CMOS Configurable logic cell 3 output.
CLC4OUT CMOS Configurable logic cell 4 output.
TABLE 1-3: PIC16(L)F1777/9 PINOUT DESCRIPT IO N (CO NT IN UED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HP = High Power XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with
the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
2015-2016 Microchip Technology Inc. DS40001819B-page 33
PIC16(L)F1777/8/9
TABLE 1-4: PERIPHERAL CONNECTION MATRIX
Peripheral Input
Peripheral Outp ut
ADC Trigger
COG Clock
COG Rising/Falling
COG Shutdown
10-bit DAC
5-bit DAC
PRG Analog Input
PRG Rising/Falling
Comparator +
Comparator -
CLC
DSM CH
DSM CL
DSM Mod
Op Amp +
Op Amp -
Op Amp Override
10-bit PWM
16-bit PWM
CCP Capture
CCP Clock
Timer2/4/6/8 Clock
Timer2/4/6/8 Reset
Timer1/3/5 Gate
Timer0 Clock
FVR ●●●●● ●●
ZCD ● ● ●
PRG ●●●
10-bit DAC ● ● ●●
5-bit DAC ● ● ●●
CCP ● ● ● ●●●● ● ●
Comparator (sync) ● ● ● ● ● ●●
Comparator (async) ●● ●
CLC ●●● ●●●● ● ● ● ●
DSM
COG ●
EUSART TX/CK ● ●
EUSART DT ● ●
MSSP SCK/SCL ● ●
MSSP SDO/SDA ● ●
Op Amp ●
10-bit PWM ● ● ● ●●●● ● ●
16-bit PWM ● ● ● ●●●● ● ●
Timer0 overflow ● ● ●
Timer2 = T2PR ● ● ● ● ●
Timer4 = T4PR ● ● ● ● ●
Timer6 = T6PR ● ● ● ● ●
Timer8 = T8PR ● ● ● ● ●
Timer2 Postscale ● ● ● ● ● ●
Timer4 Postscale ● ● ● ● ● ●
Timer6 Postscale ● ● ● ● ● ●
Timer8 Postscale ● ● ● ● ● ●
Timer1 overflow ● ● ● ●
Timer3 overflow ● ● ● ●
Timer5 overflow ● ● ● ●
SOSC ● ●
FOSC/4 ● ●
FOSC ●●●● ● ●
HFINTOSC ●●●● ● ●
LFINTOSC ● ● ●
MFINTOSC ●
IOCIF ● ● ●
PPS Input pin ●● ● ● ●● ●●●●●●
PIC16(L)F1777/8/9
DS40001819B-page 34 2015-2016 Microchip Technology Inc.
2.0 ENHANCED MID-RANGE CPU
This family of devices contain an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
Relative Addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.
• Automatic Interrupt Context Saving
• 16-level Stack with Overflow and Underflow
• File Select Registers
• Instruction Set
FIGURE 2-1: CORE BLOCK DIAGRAM
Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr 7
12
Addr MUX
FSR reg
STATUS reg
MUX
ALU
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
VDD
8
8
Brown-out
Reset
12
3
VSS
Internal
Oscillator
Block
Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr 7
Addr MUX
FSR reg
STATUS reg
MUX
ALU
W reg
Instruction
Decode &
Control
Timing
Generation
VDD
8
8
3
VSS
Internal
Oscillator
Block
15 Data Bus 8
14
Program
Bus
Instruction Reg
Program Counter
16-Level Stack
(15-bit)
Direct Addr 7
RAM Addr
Addr MUX
Indirect
Addr
FSR0 Reg
STATUS Reg
MUX
ALU
Instruction
Decode and
Control
Timing
Generation
VDD
8
8
3
VSS
Internal
Oscillator
Block
RAM
FSR regFSR reg
FSR1 Reg
15
15
MUX
15
Program Memory
Read (PMR)
12
FSR regFSR reg
BSR Reg
5
ConfigurationConfigurationConfiguration
Flash
Program
Memory
2015-2016 Microchip Technology Inc. DS40001819B-page 35
PIC16(L)F1777/8/9
2.1 Automatic Interrupt Context
Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”
for more information.
2.2 16-Level Stack with Overflow and
Underflow
These devices have a hardware stack memory 15 bits
wide and 16 words deep. A Stack Overflow or Under-
flow will set the appropriate bit (STKOVF or STKUNF)
in the PCON register, and if enabled, will cause a soft-
ware Reset. See Section 3.6 “S ta ck” for more details.
2.3 File Select Regis ters
There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See
Section 3.7 “Indirect Addressing” for more details.
2.4 Instruction Set
There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 35.0 “Instruction Set Summary” for more
details.
PIC16(L)F1777/8/9
DS40001819B-page 36 2015-2016 Microchip Technology Inc.
3.0 MEMORY ORGANIZATION
These devices contain the following types of memory:
• Program Memory
- Configuration Words
-Device ID
-User ID
- Flash Program Memory
• Data Memory
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM
The following features are associated with access and
control of program memory and data memory:
• PCL and PCLATH
•Stack
• Indirect Addressing
3.1 Program Memory Organization
The enhanced mid-range core has a 15-bit program
counter capable of addressing a 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented for the PIC16(L)F1777/8/9 family.
Accessing a location above these boundaries will cause
a wrap-around within the implemented memory space.
The Reset vector is at 0000h and the interrupt vector is
at 0004h (see Figures 3-1 and 3-2).
3.2 High-Endurance Flash
This device has a 128-byte section of high-endurance
program Flash memory (PFM) in lieu of data EEPROM.
This area is especially well suited for nonvolatile data
storage that is expected to be updated frequently over
the life of the end product. See Section 10.2 “Flash
Program Memory Overview” for more information on
writing data to PFM. See Section 3.2.1.2 “Indirect
Read with FSR” for more information about using the
FSR registers to read byte data stored in PFM.
Note 1: The method to access Flash memory
through the PMCON registers is described
in Section 10.0 “Flash Program Memory
Control”.
TABLE 3-1: DEVICE SIZES AND ADDRESSES
Device Pr ogram Mem ory S pace
(Words) Last Program Memory
Address High-Endurance Flash
Memory Address Range(1)
PIC16(L)F1777 8,192 1FFFh 1F80h-1FFFh
PIC16(L)F1778/9 16,384 3FFFh 3F80h-3FFFh
Note 1: High-endurance Flash applies to the low byte of each address in the range.
2015-2016 Microchip Technology Inc. DS40001819B-page 37
PIC16(L)F1777/8/9
FIGURE 3-1: PROGRAM MEMORY MAP
AND STACK FOR
PIC16(L)F1777
FIGURE 3-2: PROGRAM MEMORY MAP
AND STACK FOR
PIC16(L)F1778/9
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
On-chip
Program
Memory
Stack Level 0
Stack Level 15
Stack Level 1
Reset Vector
PC<14:0>
Interrupt Vector
Page 1
Page 0
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
7FFFh
Rollover to Page 0
Rollover to Page 3
Page 2
Page 3
17FFh
1800h
1FFFh
2000h
15
Rev. 10-000040B
7/30/2013
PIC16(L)F1777/8/9
DS40001819B-page 38 2015-2016 Microchip Technology Inc.
3.2.1 READING PROGRAM MEMORY AS
DATA
There are two methods of accessing constants in
program memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.
3.2.1.1 RETLW Instruction
The RETLW instruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 3-1.
EXAMPL E 3-1: RETLW INSTRUCTION
The BRW instruction makes this type of table very
simple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.
3.2.1.2 Indirect Read with FSR
The program memory can be accessed as data by
setting bit 7 of the FSRxH register and reading the
matching INDFx register. The MOVIW instruction will
place the lower eight bits of the addressed word in the
W register. Writes to the program memory cannot be
performed via the INDF registers. Instructions that
access the program memory via the FSR require one
extra instruction cycle to complete. Example 3-2
demonstrates accessing the program memory via an
FSR.
The high directive will set bit<7> if a label points to a
location in program memory.
EXAMPLE 3-2: ACCE SS ING PROGRAM
MEMORY VIA FSR
constants
BRW ;Add Index in W to
;program counter to
;select data
RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3
my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
call constants
;… THE CONSTANT IS IN W
constants
DW DATA0 ;First constant
DW DATA1 ;Second constant
DW DATA2
DW DATA3
my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
ADDLW LOW constants
MOVWF FSR1L
MOVLW HIGH constants;MSb sets
automatically
MOVWF FSR1H
BTFSC STATUS, C ;carry from ADDLW?
INCF FSR1H, f ;yes
MOVIW 0[FSR1]
;THE PROGRAM MEMORY IS IN W
2015-2016 Microchip Technology Inc. DS40001819B-page 39
PIC16(L)F1777/8/9
3.3 Data Memory Organizati on
The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure 3-3):
• 12 core registers
• 20 Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.7 “Indirect
Addressing” for more information.
Data memory uses a 12-bit address. The upper five bits
of the address define the Bank address and the lower
seven bits select the registers/RAM in that bank.
3.3.1 CORE REGISTERS
The core registers contain the registers that directly
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These
registers are listed below in Ta bl e 3- 2 . For detailed
information, see Tabl e 3-17.
TABLE 3-2: CORE REGISTERS
3.3.1.1 STATUS Register
The STATUS register, shown in Register 3-1, contains:
• the arithmetic status of the ALU
• the Reset status
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 35.0
“Instruction Set Summary”).
Addresses BANKx
x00h or x80h INDF0
x01h or x81h INDF1
x02h or x82h PCL
x03h or x83h STATUS
x04h or x84h FSR0L
x05h or x85h FSR0H
x06h or x86h FSR1L
x07h or x87h FSR1H
x08h or x88h BSR
x09h or x89h WREG
x0Ah or x8Ah PCLATH
x0Bh or x8Bh INTCON
Note: The C and DC bits operate as Borrow and
Digit Borrow out bits, respectively, in
subtraction.
PIC16(L)F1777/8/9
DS40001819B-page 40 2015-2016 Microchip Technology Inc.
3.4 Regist er D e fi nitio n s : Status
REGISTER 3-1: STATUS: STATUS REGIS TER
U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u
— — —TOPD ZDC
(1) C(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-5 Unimplemented: Read as ‘0’
bit 4 TO: Time-Out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT Time-out occurred
bit 3 PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand.
2015-2016 Microchip Technology Inc. DS40001819B-page 41
PIC16(L)F1777/8/9
3.4.1 SPECIAL FUNCTION REGISTER
The Special Function Registers (SFR) are registers
used by the application to control the desired operation
of peripheral functions in the device. The SFR occupies
the 20 bytes after the core registers of every data
memory bank (addresses x0Ch/x8Ch through
x1Fh/x9Fh). The registers associated with the operation
of each peripheral are described in the corresponding
peripheral chapters of this data sheet.
3.4.2 GENERAL PURPOSE RAM
There are up to 80 bytes of General Purpose Registers
(GPR) in each data memory bank. The GPR occupies
the space immediately after the SFR of selected data
memory banks. The number of banks selected depends
on the total amount of GPR space available in the
device.
3.4.2.1 Linear Access to GPR
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.7.2
“Linear Data Memory” for more information.
3.4.3 COMMON RAM
There are 16 bytes of common RAM accessible from all
banks.
FIGURE 3-3: BANKED MEMORY
PARTITIONING
3.4.4 DEVICE MEMORY MAPS
The memory maps for the device family are as shown
in Tables 3-3 through 3-16.
0Bh
0Ch
1Fh
20h
6Fh
70h
7Fh
00h
Common RAM
(16 bytes)
General Purpose RAM
(80 bytes maximum)
Core Registers
(12 bytes)
Special Function Registers
(20 bytes maximum)
Memory Region
7-bit Bank Offset
2015-2016 Microchip Technology Inc. DS40001819B-page 42
PIC16(L)F1777/8/9
TABLE 3-3: PIC16(L)F1778 MEMORY MAP (BANKS 0-7)
Legend: = Unimplemented data memory locations, read as ‘0’.
Note 1: Unimplemented on PIC16LF1778.
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h
Core Registers
(Tab l e 3- 2 )
080h
Core Registers
(Tab l e 3- 2 )
100h
Core Registers
(Table 3-2)
180h
Core Registers
(Table 3-2)
200h
Core Registers
(Table 3-2)
280h
Core Registers
(Table 3-2)
300h
Core Registers
(Table 3-2)
380h
Core Registers
(Table 3-2)
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh ODCONB 30Dh SLRCONB 38Dh INLVLB
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh WPUC 28Eh ODCONC 30Eh SLRCONC 38Eh INLVLC
00Fh —08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—
010h PORTE 090h TRISE 110h —190h— 210h WPUE 290h — 310h — 390h INLVLE
011h PIR1 091h PIE1 111h CMOUT 191h PMADRL 211h SSP1BUF 291h CCPR1L 311h — 391h IOCAP
012h PIR2 092h PIE2 112h CM1CON0 192h PMADRH 212h SSP1ADD 292h CCPR1H 312h — 392h IOCAN
013h PIR3 093h PIE3 113h CM1CON1 193h PMDATL 213h SSP1MSK 293h CCP1CON 313h — 393h IOCAF
014h PIR4 094h PIE4 114h CM1NSEL 194h PMDATH 214h SSP1STAT 294h CCP1CAP 314h — 394h IOCBP
015h PIR5 095h PIE5 115h CM1PSEL 195h PMCON1 215h SSP1CON1 295h CCPR2L 315h MD1CON0 395h IOCBN
016h PIR6 096h PIE6 116h CM2CON0 196h PMCON2 216h SSP1CON2 296h CCPR2H 316h MD1CON1 396h IOCBF
017h TMR0 097h OPTION_REG 117h CM2CON1 197h VREGCON(1) 217h SSP1CON3 297h CCP2CON 317h MD1SRC 397h IOCCP
018h TMR1L 098h PCON 118h CM2NSEL 198h —218h— 298h CCP2CAP 318h MD1CARL 398h IOCCN
019h TMR1H 099h WDTCON 119h CM2PSEL 199h RC1REG 219h — 299h CCPR7L 319h MD1CARH 399h IOCCF
01Ah T1CON 09Ah OSCTUNE 11Ah CM3CON0 19Ah TX1REG 21Ah — 29Ah CCPR7H 31Ah —39Ah—
01Bh T1GCON 09Bh OSCCON 11Bh CM3CON1 19Bh SP1BRGL 21Bh MD3CON0 29Bh CCP7CON 31Bh MD2CON0 39Bh —
01Ch TMR3L 09Ch OSCSTAT 11Ch CM3NSEL 19Ch SP1BRGH 21Ch MD3CON1 29Ch CCP7CAP 31Ch MD2CON1 39Ch —
01Dh TMR3H 09Dh BORCON 11Dh CM3PSEL 19Dh RC1STA 21Dh MD3SRC 29Dh — 31Dh MD2SRC 39Dh IOCEP
01Eh T3CON 09Eh FVRCON 11Eh — 19Eh TX1STA 21Eh MD3CARL 29Eh CCPTMRS1 31Eh MD2CARL 39Eh IOCEN
01Fh T3GCON 09Fh ZCD1CON 11Fh — 19Fh BAUD1CON 21Fh MD3CARH 29Fh CCPTMRS2 31Fh MD2CARH 39Fh IOCEF
020h
General
Purpose
Register
80 Bytes
0A0h
General
Purpose
Register
80 Bytes
120h
General
Purpose
Register
80 Bytes
1A0h
General
Purpose
Register
80 Bytes
220h
General
Purpose
Register
80 Bytes
2A0h
General
Purpose
Register
80 Bytes
320h
General
Purpose
Register
80 Bytes
3A0h
General
Purpose
Register
80 Bytes
32Fh
330h
06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh
070h
Common RAM
70h – 7Fh
0F0h
Accesses
70h – 7Fh
170h
Accesses
70h – 7Fh
1F0h
Accesses
70h – 7Fh
270h
Accesses
70h – 7Fh
2F0h
Accesses
70h – 7Fh
370h
Accesses
70h – 7Fh
3F0h
Accesses
70h – 7Fh
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh
PIC16(L)F1777/8/9
DS40001819B-page 43 2015-2016 Microchip Technology Inc.
TABLE 3-4: PIC16(L)F1777/9 MEMORY MAP (BANKS 0-7)
Legend: = Unimplemented data memory locations, read as ‘0’.
Note 1: Unimplemented on PIC16LF1777/9.
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h
Core Registers
(Tab l e 3- 2 )
080h
Core Registers
(Tab l e 3- 2 )
100h
Core Registers
(Table 3-2)
180h
Core Registers
(Table 3-2)
200h
Core Registers
(Table 3-2)
280h
Core Registers
(Table 3-2)
300h
Core Registers
(Table 3-2)
380h
Core Registers
(Table 3-2)
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh ODCONB 30Dh SLRCONB 38Dh INLVLB
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh WPUC 28Eh ODCONC 30Eh SLRCONC 38Eh INLVLC
00Fh PORTD 08Fh TRISD 10Fh LATD 18Fh ANSELD 20Fh WPUD 28Fh ODCOND 30Fh SLRCOND 38Fh INLVLD
010h PORTE 090h TRISE 110h LATE 190h ANSELE 210h WPUE 290h ODCONE 310h SLRCONE 390h INLVLE
011h PIR1 091h PIE1 111h CMOUT 191h PMADRL 211h SSP1BUF 291h CCPR1L 311h CCPR8L 391h IOCAP
012h PIR2 092h PIE2 112h CM1CON0 192h PMADRH 212h SSP1ADD 292h CCPR1H 312h CCPR8H 392h IOCAN
013h PIR3 093h PIE3 113h CM1CON1 193h PMDATL 213h SSP1MSK 293h CCP1CON 313h CCP8CON 393h IOCAF
014h PIR4 094h PIE4 114h CM1NSEL 194h PMDATH 214h SSP1STAT 294h CCP1CAP 314h CCP8CAP 394h IOCBP
015h PIR5 095h PIE5 115h CM1PSEL 195h PMCON1 215h SSP1CON1 295h CCPR2L 315h MD1CON0 395h IOCBN
016h PIR6 096h PIE6 116h CM2CON0 196h PMCON2 216h SSP1CON2 296h CCPR2H 316h MD1CON1 396h IOCBF
017h TMR0 097h OPTION_REG 117h CM2CON1 197h VREGCON(1) 217h SSP1CON3 297h CCP2CON 317h MD1SRC 397h IOCCP
018h TMR1L 098h PCON 118h CM2NSEL 198h —218h— 298h CCP2CAP 318h MD1CARL 398h IOCCN
019h TMR1H 099h WDTCON 119h CM2PSEL 199h RC1REG 219h — 299h CCPR7L 319h MD1CARH 399h IOCCF
01Ah T1CON 09Ah OSCTUNE 11Ah CM3CON0 19Ah TX1REG 21Ah — 29Ah CCPR7H 31Ah —39Ah—
01Bh T1GCON 09Bh OSCCON 11Bh CM3CON1 19Bh SP1BRGL 21Bh MD3CON0 29Bh CCP7CON 31Bh MD2CON0 39Bh —
01Ch TMR3L 09Ch OSCSTAT 11Ch CM3NSEL 19Ch SP1BRGH 21Ch MD3CON1 29Ch CCP7CAP 31Ch MD2CON1 39Ch —
01Dh TMR3H 09Dh BORCON 11Dh CM3PSEL 19Dh RC1STA 21Dh MD3SRC 29Dh — 31Dh MD2SRC 39Dh IOCEP
01Eh T3CON 09Eh FVRCON 11Eh — 19Eh TX1STA 21Eh MD3CARL 29Eh CCPTMRS1 31Eh MD2CARL 39Eh IOCEN
01Fh T3GCON 09Fh ZCD1CON 11Fh — 19Fh BAUD1CON 21Fh MD3CARH 29Fh CCPTMRS2 31Fh MD2CARH 39Fh IOCEF
020h
General
Purpose
Register
80 Bytes
0A0h
General
Purpose
Register
80 Bytes
120h
General
Purpose
Register
80 Bytes
1A0h
General
Purpose
Register
80 Bytes
220h
General
Purpose
Register
80 Bytes
2A0h
General
Purpose
Register
80 Bytes
320h
General
Purpose
Register
80 Bytes
3A0h
General
Purpose
Register
80 Bytes
06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh
070h
Common RAM
70h – 7Fh
0F0h
Accesses
70h – 7Fh
170h
Accesses
70h – 7Fh
1F0h
Accesses
70h – 7Fh
270h
Accesses
70h – 7Fh
2F0h
Accesses
70h – 7Fh
370h
Accesses
70h – 7Fh
3F0h
Accesses
70h – 7Fh
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh
2015-2016 Microchip Technology Inc. DS40001819B-page 44
PIC16(L)F1777/8/9
TABLE 3-5: PIC16(L)F1778 MEMORY MAP, BANK 8-15
BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15
400h
40Bh
Core Registers
(Tab l e 3- 2 )
480h
48Bh
Core Registers
(Tab l e 3- 2 )
500h
50Bh
Core Registers
(Table 3-2)
580h
58Bh
Core Registers
(Table 3-2)
600h
60Bh
Core Registers
(Table 3-2)
680h
68Bh
Core Registers
(Table 3-2)
700h
70Bh
Core Registers
(Table 3-2)
780h
78Bh
Core Registers
(Table 3-2)
40Ch — 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 70Ch — 78Ch —
40Dh HIDRVB 48Dh — 50Dh — 58Dh DACLD 60Dh — 68Dh COG1PHR 70Dh COG2PHR 78Dh —
40Eh — 48EhADRESL50Eh — 58Eh DAC1CON0 60Eh —68Eh
COG1PHF 70Eh COG2PHF 78Eh PRG1RTSS
40Fh TMR5L 48Fh ADRESH 50Fh OPA1NCHS 58Fh DAC1REFL 60Fh —68Fh
COG1BLKR 70Fh COG2BLKR 78Fh PRG1FTSS
410h TMR5H 490h ADCON0 510h OPA1PCHS 590h DAC1REFH 610h —690h
COG1BLKF 710h COG2BLKF 790h PRG1INS
411h T5CON 491h ADCON1 511h OPA1CON 591h DAC2CON0 611h —691h
COG1DBR 711h COG2DBR 791h PRG1CON0
412h T5GCON 492h ADCON2 512h OPA1ORS 592h DAC2REFL 612h —692h
COG1DBF 712h COG2DBF 792h PRG1CON1
413h T4TMR 493h T2TMR 513h OPA2NCHS 593h DAC2REFH 613h —693h
COG1CON0 713h COG2CON0 793h PRG1CON2
414h T4PR 494h T2PR 514h OPA2PCHS 594h DAC3CON0 614h PWM3DCL 694h COG1CON1 714h COG2CON1 794h PRG2RTSS
415h T4CON 495h T2CON 515h OPA2CON 595h DAC3REF 615h PWM3DCH 695h COG1RIS0 715h COG2RIS0 795h PRG2FTSS
416h T4HLT 496h T2HLT 516h OPA2ORS 596h DAC4CON0 616h PWM3CON 696h COG1RIS1 716h COG2RIS1 796h PRG2INS
417h T4CLKCON 497h T2CLKCON 517h OPA3NCHS 597h DAC4REF 617h PWM4DCL 697h COG1RSIM0 717h COG2RSIM0 797h PRG2CON0
418h T4RST 498h T2RST 518h OPA3PCHS 598h DAC5CON0 618h PWM4DCH 698h COG1RSIM1 718h COG2RSIM1 798h PRG2CON1
419h —499h— 519h OPA3CON 599h DAC5REFL 619h PWM4CON 699h COG1FIS0 719h COG2FIS0 799h PRG2CON2
41Ah T6TMR 49Ah T8TMR 51Ah OPA3ORS 59Ah DAC5REFH 61Ah PWM9DCL 69Ah COG1FIS1 71Ah COG2FIS1 79Ah PRG3RTSS
41Bh T6PR 49Bh T8PR 51Bh —59Bh— 61Bh PWM9DCH 69Bh COG1FSIM0 71Bh COG2FSIM0 79Bh PRG3FTSS
41Ch T6CON 49Ch T8CON 51Ch — 59Ch — 61Ch PWM9CON 69Ch COG1FSIM1 71Ch COG2FSIM1 79Ch PRG3INS
41Dh T6HLT 49Dh T8HLT 51Dh — 59Dh — 61Dh — 69Dh COG1ASD0 71Dh COG2ASD0 79Dh PRG3CON0
41Eh T6CLKCON 49Eh T8CLKCON 51Eh — 59Eh DAC7CON0 61Eh —69Eh
COG1ASD1 71Eh COG2ASD1 79Eh PRG3CON1
41Fh T6RST 49Fh T8RST 51Fh — 59Fh DA73REF 61Fh —69Fh
COG1STR 71Fh COG2STR 79Fh PRG3CON2
420h
General
Purpose
Register
80 Bytes
4A0h
General
Purpose
Register
80 Bytes
520h
General
Purpose
Register
80 Bytes
5A0h
General
Purpose
Register
80 Bytes
620h
General
Purpose
Register
80 Bytes
6A0h
General
Purpose
Register
80 Bytes
720h
General
Purpose
Register
80 Bytes
7A0h
General
Purpose
Register
80 Bytes
46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh
470h
Accesses
70h – 7Fh
4F0h
Accesses
70h – 7Fh
570h
Accesses
70h – 7Fh
5F0h
Accesses
70h – 7Fh
670h
Accesses
70h – 7Fh
6F0h
Accesses
70h – 7Fh
770h
Accesses
70h – 7Fh
7F0h
Accesses
70h – 7Fh
47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh
Legend: = Unimplemented data memory locations, read as ‘0’.
PIC16(L)F1777/8/9
DS40001819B-page 45 2015-2016 Microchip Technology Inc.
TABLE 3-6: PIC16(L)F1777 MEMORY MAP, BANK 8-15
BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15
400h
40Bh
Core Registers
(Tab l e 3- 2 )
480h
48Bh
Core Registers
(Tab l e 3- 2 )
500h
50Bh
Core Registers
(Table 3-2)
580h
58Bh
Core Registers
(Table 3-2)
600h
60Bh
Core Registers
(Table 3-2)
680h
68Bh
Core Registers
(Table 3-2)
700h
70Bh
Core Registers
(Table 3-2)
780h
78Bh
Core Registers
(Table 3-2)
40Ch — 48Ch — 50Ch — 58Ch — 60Ch DAC8CON0 68Ch — 70Ch — 78Ch —
40Dh HIDRVB 48Dh — 50Dh — 58Dh DACLD 60Dh DAC8REFL 68Dh COG1PHR 70Dh COG2PHR 78Dh —
40Eh — 48EhADRESL50Eh — 58Eh DAC1CON0 60Eh PRG4RTSS 68Eh COG1PHF 70Eh COG2PHF 78Eh PRG1RTSS
40Fh TMR5L 48Fh ADRESH 50Fh OPA1NCHS 58Fh DAC1REFL 60Fh PRG4FTSS 68Fh COG1BLKR 70Fh COG2BLKR 78Fh PRG1FTSS
410h TMR5H 490h ADCON0 510h OPA1PCHS 590h DAC1REFH 610h PRG4INS 690h COG1BLKF 710h COG2BLKF 790h PRG1INS
411h T5CON 491h ADCON1 511h OPA1CON 591h DAC2CON0 611h PRG4CON0 691h COG1DBR 711h COG2DBR 791h PRG1CON0
412h T5GCON 492h ADCON2 512h OPA1ORS 592h DAC2REFL 612h PRG4CON1 692h COG1DBF 712h COG2DBF 792h PRG1CON1
413h T4TMR 493h T2TMR 513h OPA2NCHS 593h DAC2REFH 613h PRG4CON2 693h COG1CON0 713h COG2CON0 793h PRG1CON2
414h T4PR 494h T2PR 514h OPA2PCHS 594h DAC3CON0 614h PWM3DCL 694h COG1CON1 714h COG2CON1 794h PRG2RTSS
415h T4CON 495h T2CON 515h OPA2CON 595h DAC3REF 615h PWM3DCH 695h COG1RIS0 715h COG2RIS0 795h PRG2FTSS
416h T4HLT 496h T2HLT 516h OPA2ORS 596h DAC4CON0 616h PWM3CON 696h COG1RIS1 716h COG2RIS1 796h PRG2INS
417h T4CLKCON 497h T2CLKCON 517h OPA3NCHS 597h DAC4REF 617h PWM4DCL 697h COG1RSIM0 717h COG2RSIM0 797h PRG2CON0
418h T4RST 498h T2RST 518h OPA3PCHS 598h DAC5CON0 618h PWM4DCH 698h COG1RSIM1 718h COG2RSIM1 798h PRG2CON1
419h —499h— 519h OPA3CON 599h DAC5REFL 619h PWM4CON 699h COG1FIS0 719h COG2FIS0 799h PRG2CON2
41Ah T6TMR 49Ah T8TMR 51Ah OPA3ORS 59Ah DAC5REFH 61Ah PWM9DCL 69Ah COG1FIS1 71Ah COG2FIS1 79Ah PRG3RTSS
41Bh T6PR 49Bh T8PR 51Bh OPA4NCHS 59Bh DAC6CON0 61Bh PWM9DCH 69Bh COG1FSIM0 71Bh COG2FSIM0 79Bh PRG3FTSS
41Ch T6CON 49Ch T8CON 51Ch OPA4PCHS 59Ch DAC6REFL 61Ch PWM9CON 69Ch COG1FSIM1 71Ch COG2FSIM1 79Ch PRG3INS
41Dh T6HLT 49Dh T8HLT 51Dh OPA4CON 59Dh DAC6REFH 61Dh PWM10DCL 69Dh COG1ASD0 71Dh COG2ASD0 79Dh PRG3CON0
41Eh T6CLKCON 49Eh T8CLKCON 51Eh OPA4ORS 59Eh DAC7CON0 61Eh PWM10DCH 69Eh COG1ASD1 71Eh COG2ASD1 79Eh PRG3CON1
41Fh T6RST 49Fh T8RST 51Fh — 59Fh DA73REF 61Fh PWM10CON 69Fh COG1STR 71Fh COG2STR 79Fh PRG3CON2
420h
General
Purpose
Register
80 Bytes
4A0h
General
Purpose
Register
80 Bytes
520h
General
Purpose
Register
80 Bytes
5A0h
General
Purpose
Register
80 Bytes
620h General Purpose
Register 48 Bytes
6A0h
Unimplemented
Read as ‘0’
720h
Unimplemented
Read as ‘0’
7A0h
Unimplemented
Read as ‘0’
64Fh
650h Unimplemented
Read as ‘0’
46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh
470h
Accesses
70h – 7Fh
4F0h
Accesses
70h – 7Fh
570h
Accesses
70h – 7Fh
5F0h
Accesses
70h – 7Fh
670h
Accesses
70h – 7Fh
6F0h
Accesses
70h – 7Fh
770h
Accesses
70h – 7Fh
7F0h
Accesses
70h – 7Fh
47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh
Legend: = Unimplemented data memory locations, read as ‘0’.
2015-2016 Microchip Technology Inc. DS40001819B-page 46
PIC16(L)F1777/8/9
TABLE 3-7: PIC16(L)F1779 MEMORY MAP, BANK 8-15
BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15
400h
40Bh
Core Registers
(Tab l e 3- 2 )
480h
48Bh
Core Registers
(Tab l e 3- 2 )
500h
50Bh
Core Registers
(Table 3-2)
580h
58Bh
Core Registers
(Table 3-2)
600h
60Bh
Core Registers
(Table 3-2)
680h
68Bh
Core Registers
(Table 3-2)
700h
70Bh
Core Registers
(Table 3-2)
780h
78Bh
Core Registers
(Table 3-2)
40Ch — 48Ch — 50Ch — 58Ch — 60Ch DAC8CON0 68Ch — 70Ch — 78Ch —
40Dh HIDRVB 48Dh — 50Dh — 58Dh DACLD 60Dh DAC8REFL 68Dh COG1PHR 70Dh COG2PHR 78Dh —
40Eh — 48EhADRESL50Eh — 58Eh DAC1CON0 60Eh PRG4RTSS 68Eh COG1PHF 70Eh COG2PHF 78Eh PRG1RTSS
40Fh TMR5L 48Fh ADRESH 50Fh OPA1NCHS 58Fh DAC1REFL 60Fh PRG4FTSS 68Fh COG1BLKR 70Fh COG2BLKR 78Fh PRG1FTSS
410h TMR5H 490h ADCON0 510h OPA1PCHS 590h DAC1REFH 610h PRG4INS 690h COG1BLKF 710h COG2BLKF 790h PRG1INS
411h T5CON 491h ADCON1 511h OPA1CON 591h DAC2CON0 611h PRG4CON0 691h COG1DBR 711h COG2DBR 791h PRG1CON0
412h T5GCON 492h ADCON2 512h OPA1ORS 592h DAC2REFL 612h PRG4CON1 692h COG1DBF 712h COG2DBF 792h PRG1CON1
413h T4TMR 493h T2TMR 513h OPA2NCHS 593h DAC2REFH 613h PRG4CON2 693h COG1CON0 713h COG2CON0 793h PRG1CON2
414h T4PR 494h T2PR 514h OPA2PCHS 594h DAC3CON0 614h PWM3DCL 694h COG1CON1 714h COG2CON1 794h PRG2RTSS
415h T4CON 495h T2CON 515h OPA2CON 595h DAC3REF 615h PWM3DCH 695h COG1RIS0 715h COG2RIS0 795h PRG2FTSS
416h T4HLT 496h T2HLT 516h OPA2ORS 596h DAC4CON0 616h PWM3CON 696h COG1RIS1 716h COG2RIS1 796h PRG2INS
417h T4CLKCON 497h T2CLKCON 517h OPA3NCHS 597h DAC4REF 617h PWM4DCL 697h COG1RSIM0 717h COG2RSIM0 797h PRG2CON0
418h T4RST 498h T2RST 518h OPA3PCHS 598h DAC5CON0 618h PWM4DCH 698h COG1RSIM1 718h COG2RSIM1 798h PRG2CON1
419h —499h— 519h OPA3CON 599h DAC5REFL 619h PWM4CON 699h COG1FIS0 719h COG2FIS0 799h PRG2CON2
41Ah T6TMR 49Ah T8TMR 51Ah OPA3ORS 59Ah DAC5REFH 61Ah PWM9DCL 69Ah COG1FIS1 71Ah COG2FIS1 79Ah PRG3RTSS
41Bh T6PR 49Bh T8PR 51Bh OPA4NCHS 59Bh DAC6CON0 61Bh PWM9DCH 69Bh COG1FSIM0 71Bh COG2FSIM0 79Bh PRG3FTSS
41Ch T6CON 49Ch T8CON 51Ch OPA4PCHS 59Ch DAC6REFL 61Ch PWM9CON 69Ch COG1FSIM1 71Ch COG2FSIM1 79Ch PRG3INS
41Dh T6HLT 49Dh T8HLT 51Dh OPA4CON 59Dh DAC6REFH 61Dh PWM10DCL 69Dh COG1ASD0 71Dh COG2ASD0 79Dh PRG3CON0
41Eh T6CLKCON 49Eh T8CLKCON 51Eh OPA4ORS 59Eh DAC7CON0 61Eh PWM10DCH 69Eh COG1ASD1 71Eh COG2ASD1 79Eh PRG3CON1
41Fh T6RST 49Fh T8RST 51Fh — 59Fh DA73REF 61Fh PWM10CON 69Fh COG1STR 71Fh COG2STR 79Fh PRG3CON2
420h
General
Purpose
Register
80 Bytes
4A0h
General
Purpose
Register
80 Bytes
520h
General
Purpose
Register
80 Bytes
5A0h
General
Purpose
Register
80 Bytes
620h
General
Purpose
Register
80 Bytes
6A0h
General
Purpose
Register
80 Bytes
720h
General
Purpose
Register
80 Bytes
7A0h
General
Purpose
Register
80 Bytes
46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh
470h
Accesses
70h – 7Fh
4F0h
Accesses
70h – 7Fh
570h
Accesses
70h – 7Fh
5F0h
Accesses
70h – 7Fh
670h
Accesses
70h – 7Fh
6F0h
Accesses
70h – 7Fh
770h
Accesses
70h – 7Fh
7F0h
Accesses
70h – 7Fh
47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh
Legend: = Unimplemented data memory locations, read as ‘0’.
2015-2016 Microchip Technology Inc. DS40001819B-page 47
PIC16(L)F1777/8/9
TABLE 3-8: PIC16(L)F1778 MEMORY MAP, BANK 16-23
BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23
800h
80Bh
Core Registers
(Tab l e 3- 2 )
880h
88Bh
Core Registers
(Tab l e 3- 2 )
900h
90Bh
Core Registers
(Table 3-2)
980h
98Bh
Core Registers
(Table 3-2)
A00h
A0Bh
Core Registers
(Table 3-2)
A80h
A8Bh
Core Registers
(Table 3-2)
B00h
B0Bh
Core Registers
(Table 3-2)
B80h
B8Bh
Core Registers
(Table 3-2)
80Ch —88Ch
Unimplemented
Read as ‘0’
90Ch CM4CON0 98Ch
Unimplemented
Read as ‘0’
A0Ch
Unimplemented
Read as ‘0’
A8Ch
Unimplemented
Read as ‘0’
B0Ch
Unimplemented
Read as ‘0’
B8Ch
Unimplemented
Read as ‘0’
80Dh COG3PHR 90Dh CM4CON1
80Eh COG3PHF 90Eh CM4NSEL
80Fh COG3BLKR 90Fh CM4PSEL
810h COG3BLKF 910h CM5CON0
811h COG3DBR 911h CM5CON1
812h COG3DBF 912h CM5NSEL
813h COG3CON0 913h CM5PSEL
814h COG3CON1 914h CM6CON0
815h COG3RIS0 915h CM6CON1
816h COG3RIS1 916h CM6NSEL
817h COG3RSIM0 917h CM6PSEL
818h COG3RSIM1 918h
Unimplemented
Read as ‘0’
819h COG3FIS0
81Ah COG3FIS1
81Bh COG3FSIM0
81Ch COG3FSIM1
81Dh COG3ASD0
81Eh COG3ASD1
81Fh COG3STR 89Fh 91Fh 99Fh A1Fh A9Fh B1Fh B9Fh
820h
General Purpose
Register 48 Bytes
8A0h
General Purpose
Register 48 Bytes
920h
General Purpose
Register 48 Bytes
9A0h
General Purpose
Register 48 Bytes
A20h
General Purpose
Register 48 Bytes
AA0h
General Purpose
Register 48 Bytes
B20h
General Purpose
Register 48 Bytes
BA0h
General Purpose
Register 48 Bytes
86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh
870h
Accesses
70h – 7Fh
8F0h
Accesses
70h – 7Fh
970h
Accesses
70h – 7Fh
9F0h
Accesses
70h – 7Fh
A70h
Accesses
70h – 7Fh
AF0h
Accesses
70h – 7Fh
B70h
Accesses
70h – 7Fh
BF0h
Accesses
70h – 7Fh
87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh
Legend: = Unimplemented data memory locations, read as ‘0’.
2015-2016 Microchip Technology Inc. DS40001819B-page 48
PIC16(L)F1777/8/9
TABLE 3-9: PIC16(L)F1777 MEMORY MAP, BANK 16-23
BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23
800h
80Bh
Core Registers
(Tab l e 3- 2 )
880h
88Bh
Core Registers
(Tab l e 3- 2 )
900h
90Bh
Core Registers
(Table 3-2)
980h
98Bh
Core Registers
(Table 3-2)
A00h
A0Bh
Core Registers
(Table 3-2)
A80h
A8Bh
Core Registers
(Table 3-2)
B00h
B0Bh
Core Registers
(Table 3-2)
B80h
B8Bh
Core Registers
(Table 3-2)
80Ch —88Ch —90Ch CM4CON0 98Ch
Unimplemented
Read as ‘0’
A0Ch
Unimplemented
Read as ‘0’
A8Ch
Unimplemented
Read as ‘0’
B0Ch
Unimplemented
Read as ‘0’
B8Ch
Unimplemented
Read as ‘0’
80Dh COG3PHR COG4PHR 90Dh CM4CON1
80Eh COG3PHF COG4PHF 90Eh CM4NSEL
80Fh COG3BLKR COG4BLKR 90Fh CM4PSEL
810h COG3BLKF COG4BLKF 910h CM5CON0
811h COG3DBR COG4DBR 911h CM5CON1
812h COG3DBF COG4DBF 912h CM5NSEL
813h COG3CON0 COG4CON0 913h CM5PSEL
814h COG3CON1 COG4CON1 914h CM6CON0
815h COG3RIS0 COG4RIS0 915h CM6CON1
816h COG3RIS1 COG4RIS1 916h CM6NSEL
817h COG3RSIM0 COG4RSIM0 917h CM6PSEL
818h COG3RSIM1 COG4RSIM1 918h CM7CON0
819h COG3FIS0 COG4FIS0 CM7CON1
81Ah COG3FIS1 COG4FIS1 CM7NSEL
81Bh COG3FSIM0 COG4FSIM0 CM7PSEL
81Ch COG3FSIM1 COG4FSIM1 CM8CON0
81Dh COG3ASD0 COG4ASD0 CM8CON1
81Eh COG3ASD1 COG4ASD1 CM8NSEL
81Fh COG3STR 89Fh COG4STR 91Fh CM8PSEL
820h
Unimplemented
Read as ‘0’
8A0h
Unimplemented
Read as ‘0’
920h
Unimplemented
Read as ‘0’
86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh
870h
Accesses
70h – 7Fh
8F0h
Accesses
70h – 7Fh
970h
Accesses
70h – 7Fh
9F0h
Accesses
70h – 7Fh
A70h
Accesses
70h – 7Fh
AF0h
Accesses
70h – 7Fh
B70h
Accesses
70h – 7Fh
BF0h
Accesses
70h – 7Fh
87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh
Legend: = Unimplemented data memory locations, read as ‘0’.
PIC16(L)F1777/8/9
DS40001819B-page 49 2015-2016 Microchip Technology Inc.
TABLE 3-10: PIC16(L)F1779 MEMORY MAP, BANK 16-23
BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23
800h
80Bh
Core Registers
(Tab l e 3- 2 )
880h
88Bh
Core Registers
(Tab l e 3- 2 )
900h
90Bh
Core Registers
(Table 3-2)
980h
98Bh
Core Registers
(Table 3-2)
A00h
A0Bh
Core Registers
(Table 3-2)
A80h
A8Bh
Core Registers
(Table 3-2)
B00h
B0Bh
Core Registers
(Table 3-2)
B80h
B8Bh
Core Registers
(Table 3-2)
80Ch —88Ch —90Ch CM4CON0 98Ch
Unimplemented
Read as ‘0’
A0Ch
Unimplemented
Read as ‘0’
A8Ch
Unimplemented
Read as ‘0’
B0Ch
Unimplemented
Read as ‘0’
B8Ch
Unimplemented
Read as ‘0’
80Dh COG3PHR COG4PHR 90Dh CM4CON1
80Eh COG3PHF COG4PHF 90Eh CM4NSEL
80Fh COG3BLKR COG4BLKR 90Fh CM4PSEL
810h COG3BLKF COG4BLKF 910h CM5CON0
811h COG3DBR COG4DBR 911h CM5CON1
812h COG3DBF COG4DBF 912h CM5NSEL
813h COG3CON0 COG4CON0 913h CM5PSEL
814h COG3CON1 COG4CON1 914h CM6CON0
815h COG3RIS0 COG4RIS0 915h CM6CON1
816h COG3RIS1 COG4RIS1 916h CM6NSEL
817h COG3RSIM0 COG4RSIM0 917h CM6PSEL
818h COG3RSIM1 COG4RSIM1 918h CM7CON0
819h COG3FIS0 COG4FIS0 CM7CON1
81Ah COG3FIS1 COG4FIS1 CM7NSEL
81Bh COG3FSIM0 COG4FSIM0 CM7PSEL
81Ch COG3FSIM1 COG4FSIM1 CM8CON0
81Dh COG3ASD0 COG4ASD0 CM8CON1
81Eh COG3ASD1 COG4ASD1 CM8NSEL
81Fh COG3STR 89Fh COG4STR 91Fh CM8PSEL 99Fh A1Fh A9Fh B1Fh B9Fh
820h
General Purpose
Register 48 Bytes
8A0h
General Purpose
Register 48 Bytes
920h
General Purpose
Register 48 Bytes
9A0h
General Purpose
Register 48 Bytes
A20H
General Purpose
Register 48 Bytes
AA0h
General Purpose
Register 48 Bytes
B20h
General Purpose
Register 48 Bytes
BA0h
General Purpose
Register 48 Bytes
86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh
870h
Accesses
70h – 7Fh
8F0h
Accesses
70h – 7Fh
970h
Accesses
70h – 7Fh
9F0h
Accesses
70h – 7Fh
A70h
Accesses
70h – 7Fh
AF0h
Accesses
70h – 7Fh
B70h
Accesses
70h – 7Fh
BF0h
Accesses
70h – 7Fh
87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh
Legend: = Unimplemented data memory locations, read as ‘0’.
2015-2016 Microchip Technology Inc. DS40001819B-page 50
PIC16(L)F1777/8/9
TABLE 3-11: PIC16(L)F1778 MEMORY MAP, BANK 24-31
Legend: = Unimplemented data memory locations, read as ‘0’.
BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31
C00h
C0Bh
Core Registers
(Ta b l e 3 - 2 )
C80h
C8Bh
Core Registers
(Ta b l e 3 - 2 )
D00h
D0Bh
Core Registers
(Ta b l e 3 - 2 )
D80h
D8Bh
Core Registers
(Ta b l e 3 - 2 )
E00h
E0Bh
Core Registers
(Ta b l e 3 - 2 )
E80h
E8Bh
Core Registers
(Ta b l e 3 - 2 )
F00h
F0Bh
Core Registers
(Ta b l e 3 - 2 )
F80h
F8Bh
Core Registers
(Ta b l e 3 - 2 )
C0Ch —C8Ch—D0Ch—
See Ta b le 3 - 14
for register map-
ping details
See Ta b le 3 - 14
for register map-
ping details
See Tab l e 3-1 4
for register map-
ping details
See Tab l e 3-1 4
for register map-
ping details
See Tab l e 3-1 6
for register map-
ping details
C0Dh —C8Dh—D0Dh—
C0Eh —C8Eh—D0Eh—
C0Fh —C8Fh—D0Fh—
C10h —C90h—D10h—
C11h —C91h—D11h—
C12h —C92h—D12h—
C13h —C93h—D13h—
C14h —C94h—D14h—
C15h —C95h—D15h—
C16h —C96h—D16h—
C17h —C97h—D17h—
C18h —C98h—D18h—
C19h —C99h—D19h—
C1Ah —C9Ah—D1Ah—
C1Bh —C9Bh—D1Bh—
C1Ch —C9Ch—D1Ch—
C1Dh —C9Dh—D1Dh—
C1Eh —C9Eh—D1Eh—
C1Fh —C9Fh—D1Fh—
C20h
General
Purpose
Register
80 Bytes
CA0h General Purpose
Register 32 Bytes
D20h
Unimplemented
Read as ‘0’
CBFh
CC0h Unimplemented
Read as ‘0’
C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh
C70h
Accesses
70h – 7Fh
CF0h
Accesses
70h – 7Fh
D70h
Accesses
70h – 7Fh
DF0h
Accesses
70h – 7Fh
E70h
Accesses
70h – 7Fh
EF0h
Accesses
70h – 7Fh
F70h
Accesses
70h – 7Fh
FF0h
Accesses
70h – 7Fh
CFFh CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh
2015-2016 Microchip Technology Inc. DS40001819B-page 51
PIC16(L)F1777/8/9
TABLE 3-12: PIC16(L)F1777 MEMORY MAP, BANK 24-31
Legend: = Unimplemented data memory locations, read as ‘0’.
BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31
C00h
C0Bh
Core Registers
(Ta b l e 3 - 2 )
C80h
C8Bh
Core Registers
(Ta b l e 3 - 2 )
D00h
D0Bh
Core Registers
(Ta b l e 3 - 2 )
D80h
D8Bh
Core Registers
(Ta b l e 3 - 2 )
E00h
E0Bh
Core Registers
(Ta b l e 3 - 2 )
E80h
E8Bh
Core Registers
(Ta b l e 3 - 2 )
F00h
F0Bh
Core Registers
(Ta b l e 3 - 2 )
F80h
F8Bh
Core Registers
(Ta b l e 3 - 2 )
C0Ch —C8Ch—D0Ch—
See Ta b le 3 - 15
for register map-
ping details
See Ta b le 3 - 15
for register map-
ping details
See Tab l e 3-1 5
for register map-
ping details
See Tab l e 3-1 5
for register map-
ping details
See Tab l e 3-1 6
for register map-
ping details
C0Dh —C8Dh—D0Dh—
C0Eh —C8Eh—D0Eh—
C0Fh —C8Fh—D0Fh—
C10h —C90h—D10h—
C11h —C91h—D11h—
C12h —C92h—D12h—
C13h —C93h—D13h—
C14h —C94h—D14h—
C15h —C95h—D15h—
C16h —C96h—D16h—
C17h —C97h—D17h—
C18h —C98h—D18h—
C19h —C99h—D19h—
C1Ah —C9Ah—D1Ah—
C1Bh —C9Bh— D1Bh MD4CON0
C1Ch —C9Ch— D1Ch MD4CON1
C1Dh —C9Dh—D1DhMD4SRC
C1Eh —C9Eh— D1Eh MD4CARL
C1Fh —C9Fh— D1Fh MD4CARH
C20h
Unimplemented
Read as ‘0’
CA0h
Unimplemented
Read as ‘0’
D20h
Unimplemented
Read as ‘0’
CBFh
CC0h
C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh
C70h
Accesses
70h – 7Fh
CF0h
Accesses
70h – 7Fh
D70h
Accesses
70h – 7Fh
DF0h
Accesses
70h – 7Fh
E70h
Accesses
70h – 7Fh
EF0h
Accesses
70h – 7Fh
F70h
Accesses
70h – 7Fh
FF0h
Accesses
70h – 7Fh
CFFh CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh
PIC16(L)F1777/8/9
DS40001819B-page 52 2015-2016 Microchip Technology Inc.
TABLE 3-13: PIC16(L)F1779 MEMORY MAP, BANK 24-31
Legend: = Unimplemented data memory locations, read as ‘0’.
BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31
C00h
C0Bh
Core Registers
(Ta b l e 3 - 2 )
C80h
C8Bh
Core Registers
(Ta b l e 3 - 2 )
D00h
D0Bh
Core Registers
(Ta b l e 3 - 2 )
D80h
D8Bh
Core Registers
(Ta b l e 3 - 2 )
E00h
E0Bh
Core Registers
(Ta b l e 3 - 2 )
E80h
E8Bh
Core Registers
(Ta b l e 3 - 2 )
F00h
F0Bh
Core Registers
(Ta b l e 3 - 2 )
F80h
F8Bh
Core Registers
(Ta b l e 3 - 2 )
C0Ch —C8Ch—D0Ch—
See Ta b le 3 - 15
for register map-
ping details
See Ta b le 3 - 15
for register map-
ping details
See Tab l e 3-1 5
for register map-
ping details
See Tab l e 3-1 5
for register map-
ping details
See Tab l e 3-1 6
for register map-
ping details
C0Dh —C8Dh—D0Dh—
C0Eh —C8Eh—D0Eh—
C0Fh —C8Fh—D0Fh—
C10h —C90h—D10h—
C11h —C91h—D11h—
C12h —C92h—D12h—
C13h —C93h—D13h—
C14h —C94h—D14h—
C15h —C95h—D15h—
C16h —C96h—D16h—
C17h —C97h—D17h—
C18h —C98h—D18h—
C19h —C99h—D19h—
C1Ah —C9Ah—D1Ah—
C1Bh —C9Bh— D1Bh MD4CON0
C1Ch —C9Ch— D1Ch MD4CON1
C1Dh —C9Dh—D1DhMD4SRC
C1Eh —C9Eh— D1Eh MD4CARL
C1Fh —C9Fh— D1Fh MD4CARH
C20h
General
Purpose
Register
80 Bytes
CA0h General Purpose
Register 32 Bytes
D20h
Unimplemented
Read as ‘0’
CBFh
CC0h Unimplemented
Read as ‘0’
C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh
C70h
Accesses
70h – 7Fh
CF0h
Accesses
70h – 7Fh
D70h
Accesses
70h – 7Fh
DF0h
Accesses
70h – 7Fh
E70h
Accesses
70h – 7Fh
EF0h
Accesses
70h – 7Fh
F70h
Accesses
70h – 7Fh
FF0h
Accesses
70h – 7Fh
CFFh CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh
2015-2016 Microchip Technology Inc. DS40001819B-page 53
PIC16(L)F1777/8/9
TABLE 3-14: PIC16(L)F1778 MEMORY MAP, BANK 27-30
Legend: = Unimplemented data memory locations, read as ‘0’,
Bank 27 Bank 28 Ba nk 29 Bank 30
D8Ch — E0Ch PPSLOCK E8Ch —F0Ch —
D8Dh — E0Dh INTPPS E8Dh —F0Dh —
D8Eh PWMEN E0Eh T0CKIPPS E8Eh —F0Eh —
D8Fh PWMLD E0Fh T1CKIPPS E8Fh — F0Fh CLCDATA
D90h PWMOUT E10h T1GPPS E90h RA0PPS F10h CLC1CON
D91h PWM5PHL E11h T3CKIPPS E91h RA1PPS F11h CLC1POL
D92h PWM5PHH E12h T3GPPS E92h RA2PPS F12h CLC1SEL0
D93h PWM5DCL E13h T5CKIPPS E93h RA3PPS F13h CLC1SEL1
D94h PWM5DCH E14h T5GPPS E94h RA4PPS F14h CLC1SEL2
D95h PWM5PRL E15h T2INPPS E95h RA5PPS F15h CLC1SEL3
D96h PWM5PRH E16h T4INPPS E96h RA6PPS F16h CLC1GLS0
D97h PWM5OFL E17h T6INPPS E97h RA7PPS F17h CLC1GLS1
D98h PWM5OFH E18h T8INPPS E98h RB0PPS F18h CLC1GLS2
D99h PWM5TMRL E19h CCP1PPS E99h RB1PPS F19h CLC1GLS3
D9Ah PWM5TMRH E1Ah CCP2PPS E9Ah RB2PPS F1Ah CLC2CON
D9Bh PWM5CON E1Bh CCP7PPS E9Bh RB3PPS F1Bh CLC2POL
D9Ch PWM5INTE E1Ch — E9Ch RB4PPS F1Ch CLC2SEL0
D9Dh PWM5INTF E1Dh COG1INPPS E9Dh RB5PPS F1Dh CLC2SEL1
D9Eh PWM5CLKCON E1Eh COG2INPPS E9Eh RB6PPS F1Eh CLC2SEL2
D9Fh PWM5LDCON E1Fh COG3INPPS E9Fh RB7PPS F1Fh CLC2SEL3
DA0h PWM5OFCON E20h — EA0h RC0PPS F20h CLC2GLS0
DA1h PWM6PHL E21h MD1CLPPS EA1h RC1PPS F21h CLC2GLS1
DA2h PWM6PHH E22h MD1CHPPS EA2h RC2PPS F22h CLC2GLS2
DA3h PWM6DCL E23h MD1MODPPS EA3h RC3PPS F23h CLC2GLS3
DA4h PWM6DCH E24h MD2CLPPS EA4h RC4PPS F24h CLC3CON
DA5h PWM6PRL E25h MD2CHPPS EA5h RC5PPS F25h CLC3POL
DA6h PWM6PRH E26h MD2MODPPS EA6h RC6PPS F26h CLC3SEL0
DA7h PWM6OFL E27h MD3CLPPS EA7h RC7PPS F27h CLC3SEL1
DA8h PWM6OFH E28h MD3CHPPS EA8h — F28h CLC3SEL2
DA9h PWM6TMRL E29h MD3MODPPS EA9h — F29h CLC3SEL3
DAAh PWM6TMRH E2Ah —EAAh —F2Ah CLC3GLS0
DABh PWM6CON E2Bh — EABh — F2Bh CLC3GLS1
DACh PWM6INTE E2Ch — EACh — F2Ch CLC3GLS2
DADh PWM6INTF E2Dh PRG1RPPS EADh — F2Dh CLC3GLS3
DAEh PWM6CLKCON E2Eh PRG1FPPS EAEh — F2Eh CLC4CON
DAFh PWM6LDCON E2Fh PRG2RPPS EAFh — F2Fh CLC4POL
DB0h PWM6OFCON E30h PRG2FPPS EB0h — F30h CLC4SEL0
DB1h PWM11PHL E31h PRG3FPPS EB1h — F31h CLC4SEL1
DB2h PWM11PHH E32h PRG3RPPS EB2h — F32h CLC4SEL2
DB3h PWM11DCL E33h EB3h — F33h CLC4SEL3
DB4h PWM11DCH E34h EB4h — F34h CLC4GLS0
DB5h PWM11PRL E35h CLCIN0PPS EB5h — F35h CLC4GLS1
DB6h PWM11PRH E36h CLCIN1PPS EB6h — F36h CLC4GLS2
DB7h PWM11OFL E37h CLCIN2PPS EB7h — F37h CLC4GLS3
DB8h PWM11OFH E38h CLCIN3PPS EB8h — F38h —
DB9h PWM11TMRL E39h ADCACTPPS EB9h — F39h —
DBAh PWM11TMRH E3Ah SSPCLKPPS EBAh —F3Ah —
DBBh PWM11CON E3Bh SSPDATPPS EBBh —F3Bh —
DBCh PWM11INTE E3Ch SSPSSPPS EBCh —F3Ch —
DBDh PWM11INTF E3Dh RXPPS EBDh —F3Dh —
DBEh PWM11CLKCON E3Eh CKPPS EBEh —F3Eh —
DBFh PWM11LDCON E3Fh — EBFh —F3Fh —
DC0h PWM11OFCON E40h
—
EC0h
—
F40h
—
DC1h
—
DEFh E6Fh EEFh F6Fh
PIC16(L)F1777/8/9
DS40001819B-page 54 2015-2016 Microchip Technology Inc.
TABLE 3-15: PIC16(L)F1777/9 MEMORY MAP, BANK 27-30
Legend: = Unimplemented data memory locations, read as ‘0’,
Bank 2 7 Bank 28 Bank 29 Bank 30
D8Ch — E0Ch PPSLOCK E8Ch —F0Ch —
D8Dh —E0DhINTPPSE8Dh—F0Dh —
D8Eh PWMEN E0Eh T0CKIPPS E8Eh —F0Eh —
D8Fh PWMLD E0Fh T1CKIPPS E8Fh — F0Fh CLCDATA
D90h PWMOUT E10h T1GPPS E90h RA0PPS F10h CLC1CON
D91h PWM5PHL E11h T3CKIPPS E91h RA1PPS F11h CLC1POL
D92h PWM5PHH E12h T3GPPS E92h RA2PPS F12h CLC1SEL0
D93h PWM5DCL E13h T5CKIPPS E93h RA3PPS F13h CLC1SEL1
D94h PWM5DCH E14h T5GPPS E94h RA4PPS F14h CLC1SEL2
D95h PWM5PRL E15h T2INPPS E95h RA5PPS F15h CLC1SEL3
D96h PWM5PRH E16h T4INPPS E96h RA6PPS F16h CLC1GLS0
D97h PWM5OFL E17h T6INPPS E97h RA7PPS F17h CLC1GLS1
D98h PWM5OFH E18h T8INPPS E98h RB0PPS F18h CLC1GLS2
D99h PWM5TMRL E19h CCP1PPS E99h RB1PPS F19h CLC1GLS3
D9Ah PWM5TMRH E1Ah CCP2PPS E9Ah RB2PPS F1Ah CLC2CON
D9Bh PWM5CON E1Bh CCP7PPS E9Bh RB3PPS F1Bh CLC2POL
D9Ch PWM5INTE E1Ch CCP8PPS E9Ch RB4PPS F1Ch CLC2SEL0
D9Dh PWM5INTF E1Dh COG1INPPS E9Dh RB5PPS F1Dh CLC2SEL1
D9Eh PWM5CLKCON E1Eh COG2INPPS E9Eh RB6PPS F1Eh CLC2SEL2
D9Fh PWM5LDCON E1Fh COG3INPPS E9Fh RB7PPS F1Fh CLC2SEL3
DA0h PWM5OFCON E20h COG4INPPS EA0h RC0PPS F20h CLC2GLS0
DA1h PWM6PHL E21h MD1CLPPS EA1h RC1PPS F21h CLC2GLS1
DA2h PWM6PHH E22h MD1CHPPS EA2h RC2PPS F22h CLC2GLS2
DA3h PWM6DCL E23h MD1MODPPS EA3h RC3PPS F23h CLC2GLS3
DA4h PWM6DCH E24h MD2CLPPS EA4h RC4PPS F24h CLC3CON
DA5h PWM6PRL E25h MD2CHPPS EA5h RC5PPS F25h CLC3POL
DA6h PWM6PRH E26h MD2MODPPS EA6h RC6PPS F26h CLC3SEL0
DA7h PWM6OFL E27h MD3CLPPS EA7h RC7PPS F27h CLC3SEL1
DA8h PWM6OFH E28h MD3CHPPS EA8h RD0PPS F28h CLC3SEL2
DA9h PWM6TMRL E29h MD3MODPPS EA9h RD1PPS F29h CLC3SEL3
DAAh PWM6TMRH E2Ah MD4CLPPS EAAh RD2PPS F2Ah CLC3GLS0
DABh PWM6CON E2Bh MD4CHPPS EABh RD3PPS F2Bh CLC3GLS1
DACh PWM6INTE E2Ch MD4MODPPS EACh RD4PPS F2Ch CLC3GLS2
DADh PWM6INTF E2Dh PRG1RPPS EADh RD5PPS F2Dh CLC3GLS3
DAEh PWM6CLKCON E2Eh PRG1FPPS EAEh RD6PPS F2Eh CLC4CON
DAFh PWM6LDCON E2Fh PRG2RPPS EAFh RD7PPS F2Fh CLC4POL
DB0h PWM6OFCON E30h PRG2FPPS EB0h RE0PPS F30h CLC4SEL0
DB1h PWM11PHL E31h PRG3FPPS EB1h RE1PPS F31h CLC4SEL1
DB2h PWM11PHH E32h PRG3RPPS EB2h RE2PPS F32h CLC4SEL2
DB3h PWM11DCL E33h PRG4FPPS EB3h
—
F33h CLC4SEL3
DB4h PWM11DCH E34h PRG4RPPS EB4h F34h CLC4GLS0
DB5h PWM11PRL E35h CLCIN0PPS EB5h F35h CLC4GLS1
DB6h PWM11PRH E36h CLCIN1PPS EB6h F36h CLC4GLS2
DB7h PWM11OFL E37h CLCIN2PPS EB7h F37h CLC4GLS3
DB8h PWM11OFH E38h CLCIN3PPS EB8h F38h
—
DB9h PWM11TMRL E39h ADCACTPPS EB9h F39h
DBAh PWM11TMRH E3Ah SSPCLKPPS EBAh F3Ah
DBBh PWM11CON E3Bh SSPDATPPS EBBh F3Bh
DBCh PWM11INTE E3Ch SSPSSPPS EBCh F3Ch
DBDh PWM11INTF E3Dh RXPPS EBDh F3Dh
DBEh PWM11CLKCON E3Eh CKPPS EBEh F3Eh
DBFh PWM11LDCON E3Fh
—
EBFh F3Fh
DC0h PWM11OFCON E40h EC0h F40h
DC1h PWM12PHL E31h EB1h F31h
DC2h PWM12PHH E32h EB2h F32h
DC3h PWM12DCL E33h EB3h F33h
DC4h PWM12DCH E34h EB4h F34h
DC5h PWM12PRL E35h EB5h F35h
DC6h PWM12PRH E36h EB6h F36h
DC7h PWM12OFL E37h EB7h F37h
DC8h PWM12OFH E38h EB8h F38h
DC9h PWM12TMRL E39h EB9h F39h
DCAh PWM12TMRH E3Ah EBAh F3Ah
DCBh PWM12CON E3Bh EBBh F3Bh
DCCh PWM12INTE E3Ch EBCh F3Ch
DCDh PWM12INTF E3Dh EBDh F3Dh
DCEh PWM12CLKCON E3Eh EBEh F3Eh
DCFh PWM12LDCON E3Fh EBFh F3Fh
DCFh PWM12LDCON E3Fh EBFh F3Fh
DD0h PWM12OFCON E6Fh EEFh F6Fh
DD1h - —E6Fh EEFh F6Fh
DEFh E6Fh EEFh F6Fh
2015-2016 Microchip Technology Inc. DS40001819B-page 55
PIC16(L)F1777/8/9
TABLE 3-16: PIC16(L)F1777/8/9 MEMORY
MAP, BANK 31
Legend: = Unimplemented data memory locations,
read as ‘0’,
Bank 31
F8Ch Unimplemented
Read as ‘0’
FE3h
FE4h STATUS_SHAD
FE5h WREG_SHAD
FE6h BSR_SHAD
FE7h PCLATH_SHAD
FE8h FSR0L_SHAD
FE9h FSR0H_SHAD
FEAh FSR1L_SHAD
FEBh FSR1H_SHAD
FECh —
FEDh STKPTR
FEEh TOSL
FEFh TOSH
PIC16(L)F1777/8/9
DS40001819B-page 56 2015-2016 Microchip Technology Inc.
3.4.5 CORE FUNCTION REGISTERS
SUMMARY
The Core Function registers listed in Table 3- 17 can
be addressed from any Bank.
TABLE 3-17: CORE FUNCTION REGISTERS SUMMARY(1)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
Bank 0-31
x00h or
x80h INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register) xxxx xxxx uuuu uuuu
x01h or
x81h INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register) xxxx xxxx uuuu uuuu
x02h or
x82h PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
x03h or
x83h STATUS — — —TOPD ZDCC---1 1000 ---q quuu
x04h or
x84h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
x05h or
x85h FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
x06h or
x86h FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
x07h or
x87h FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
x08h or
x88h BSR — — — BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000
x09h or
x89h WREG Working Register 0000 0000 uuuu uuuu
x0Ah or
x8Ah PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
x0Bh or
x8Bh INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2015-2016 Microchip Technology Inc. DS40001819B-page 57
PIC16(L)F1777/8/9
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Bank 0
00Ch PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx x xxx uuuu uuuu
00Dh PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
00Eh PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx x xxx uuuu uuuu
00Fh PORTD(3) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu
010h PORTE ————RE3RE2
(3) RE1(3) RE0(3) ---- xxxx ---- uuuu
011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
012h PIR2 OSFIF C2IF C1IF COG1IF BCL1IF C4IF C3IF CCP2IF 0000 0000 0000 0000
013h PIR3 —— COG2IF ZCDIF CLC4IF CLC3IF CLC2IF CLC1IF --00 0000 --00 0000
014h PIR4 — TMR8IF TMR5GIF TMR5IF TMR3GIF TMR3IF TMR6IF TRM4IF -000 0000 -000 0000
015h PIR5 CCP8IF(3) CCP7IF COG4IF(3) COG3IF C8IF(3) C7IF(3) C6IF C5IF 0000 - -00 0000 --00
016h PIR6 ————PWM12IF
(3) PWM11IF PWM6IF PWM5IF ---- 0000 ---- 0000
017h TMR0 Timer0 Module Register 0000 0000 0000 0000
018h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
019h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
01Ah T1CON CS<1:0> CKPS<1:0> OSCEN SYNC —ON0000 00-0 uuuu uu-u
01Bh T1GCON GE GPOL GTM GSPM GGO/DONE GVAL GSS<1:0> 0000 0x00 uuuu uxuu
01Ch TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx x xxx uuuu uuuu
01Dh TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu
01Eh T3CON CS<1:0> CKPS<1:0> OSCEN SYNC —ON0000 00-0 uuuu uu-u
01Fh T3GCON GE GPOL GTM GSPM GGO/DONE GVAL GSS<1:0> 0000 0x00 u uuu u xuu
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
PIC16(L)F1777/8/9
DS40001819B-page 58 2015-2016 Microchip Technology Inc.
Bank 1
08Ch TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
08Dh TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
08Eh TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1 111 1111 1111
08Fh TRISD(3) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111
090h TRISE — — — — —(1) TRISE2(3) TRISE1(3) TRISE0(3) - --- 1 111 ---- 1111
091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0 000 0 000 0000 0000
092h PIE2 OSFIE C2IE C1IE COG1IE BCL1IE C4IE C3IE CCP2IE 0000 0000 0000 0000
093h PIE3 —— COG2IE ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE --00 0000 --00 0000
094h PIE4 — TMR8IE TMR5GIE TMR5IE TMR3GIE TMR3IE TMR6IE TRM4IE -000 0000 -000 0000
095h PIE5 CCP8IE(3) CCP7IE COG4IE(3) COG3IE C8IE(3) C7IE(3) C6IE C5IE 0000 0000 0000 0000
096h PIE6 ————PWM12IE
(3) PWM11IE PWM6IE PWM5IE ---- 0000 ---- 0000
097h
OPTION_REG
WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111
098h PCON STKOVF STKUNF —RWDTRMCLR RI POR BOR 00-1 1 1qq qq-q qquu
099h WDTCON ——WDTPS<4:0>SWDTEN--01 0110 --01 0110
09Ah OSCTUNE —— TUN<5:0> --00 0000 --00 0000
09Bh OSCCON SPLLEN IRCF<3:0> —SCS<1:0>0011 1 -00 0011 1-00
09Ch OSCSTAT SOSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 0qq0 0q0q qqqq qq0q
09Dh BORCON SBOREN BORFS ————— BORRDY 10-- - --q uu-- ---u
09Eh FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000
09Fh ZCD1CON EN —OUTPOL—— INTP INTN 0-x0 - -00 0-x0 --00
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
2015-2016 Microchip Technology Inc. DS40001819B-page 59
PIC16(L)F1777/8/9
Bank 2
10Ch LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx xxxx uuuu uuuu
10Dh LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 x xxx x xxx uuuu uuuu
10Eh LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 x xxx x xxx uuuu uuuu
10Fh LATD(3) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 x xxx xxxx u uuu u uuu
110h LATE(3) ————— LAT E2 LATE1 LATE0 ---- -111 ---- -111
111h CMOUT MC8OUT(3) MC7OUT(3) MC6OUT MC5OUT MC4OUT MC3OUT MC2OUT MC1OUT 0000 0000 0000 0000
112h CM1CON0 ON OUT —POL ZLF Reserved HYS SYNC 0 0-0 0 100 00-0 0100
113h CM1CON1 — — — — — — INTP INTN ---- - -00 ---- --00
114h CM1NSEL — — — — NCH<3:0> ---- 0000 ---- 0000
115h CM1PSEL — — — — PCH<3:0> ---- 0000 ---- 0000
116h CM2CON0 ON OUT —POL ZLF Reserved HYS SYNC 0 0-0 0 100 00-0 0100
117h CM2CON1 — — — — — — INTP INTN ---- - -00 ---- --00
118h CM2NSEL — — — — NCH<3:0> ---- 0000 ---- 0000
119h CM2PSEL — — — — PCH<3:0> ---- 0000 ---- 0000
11Ah CM3CON0 ON OUT —POL ZLF Reserved HYS SYNC 00-0 0100 00-0 0100
11Bh CM3CON1 — — — — — — INTP INTN ---- - -00 ---- --00
11Ch CM3NSEL — — — — NCH<3:0> ---- 0000 ---- 0000
11Dh CM3PSEL — — — — PCH<3:0> ---- 0 000 ---- 0000
11Eh —Unimplemented — —
11Fh —Unimplemented — —
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
PIC16(L)F1777/8/9
DS40001819B-page 60 2015-2016 Microchip Technology Inc.
Bank 3
18Ch ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 - -11 1 111 --11 1111
18Dh ANSELB —— ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111
18Eh ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 1111 11-- 1111 11--
18Fh ANSELD(3) ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 1111 1111 1111 1111
190h ANSELE(3) ————— ANSE2 ANSE1 ANSE0 - --- - 111 ---- -111
191h PMADRL Program Memory Address Register Low Byte 0000 0000 0000 0000
192h PMADRH —(1) Program Memory Address Register High Byte 1000 0000 1000 0000
193h PMDATL Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu
194h PMDATH —— Program Memory Read Data Register High Byte --xx xxxx --uu uuuu
195h PMCON1 —(1) CFGS LWLO FREE WRERR WREN WR RD 1000 x000 1000 q000
196h PMCON2 Program Memory Control Register 2 0000 0000 0000 0000
197h VREGCON ——————VREGPM
(2) Reserved - --- - -01 ---- --01
198h —Unimplemented — —
198h —Unimplemented — —
199h RC1REG EUSART Receive Data Register 0000 0000 0000 0000
19Ah TX1REG EUSART Transmit Data Register 0000 0000 0000 0000
19Bh SP1BRGL SP1BRG<7:0> 0000 0 000 0000 0000
19Ch SP1BRGH SP1BRG<15:8> 0000 0000 0000 0000
19Dh RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 0000 0000 0000
19Eh TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
19Fh BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0 -00 01-0 0-00
199h
—
19Fh —Unimplemented — —
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
2015-2016 Microchip Technology Inc. DS40001819B-page 61
PIC16(L)F1777/8/9
Bank 4
20Ch WPUA WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 1111 1111 1111 1111
20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111
20Eh WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 1111 1111 1111 1111
20Fh WPUD(3) WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 1111 1111 1111 1111
210h WPUE ————WPUE3WPUE2
(3) WPUE1(3) WPUE0(3) ---- 1111 ---- 1111
211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
212h SSP1ADD ADD<7:0> 0000 0000 0000 0000
213h SSP1MSK MSK<7:0> 1111 1111 1111 1111
214h SSP1STAT SMP CKE D/A PSR/WUA BF 0000 0 000 0000 0000
215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0 000 0000 0000
216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0 000
217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0 000 0 000 0000 0000
218h
—
21Ah —Unimplemented — —
21Bh MD3CON0 EN — OUT OPOL — — —BIT0-00 ---0 0-00 ---0
21Ch MD3CON1 —— CHPOL CHSYNC —— CLPOL CLSYNC --00 --00 --00 --00
21Dh MD3SRC — — —MS<4:0>- --0 0 000 ---0 0000
21Eh MD3CARL — — — CL<4:0> ---0 0000 ---0 0000
21Fh MD3CARH — — — CH<4:0> ---0 0000 ---0 0000
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
PIC16(L)F1777/8/9
DS40001819B-page 62 2015-2016 Microchip Technology Inc.
Bank 5
28Ch ODCONA ODA7 ODA6 ODA5 ODA4 ODA3 ODA2 ODA1 ODA0 0000 0 000 0000 0000
28Dh ODCONB ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 0000 0 000 0000 0000
28Eh ODCONC ODC7 ODC6 ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 0000 0000 0000 0000
28Fh ODCOND(3) ODD7 ODD6 ODD5 ODD4 ODD3 ODD2 ODD1 ODD0 0000 0000 0000 0000
290h ODCONE(3) ————— ODE2 ODE1 ODE0 ---- -000 --- - 000
291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
293h CCP1CON EN — OUT FMT MODE<3:0> 0-00 0000 0-00 0000
294h CCP1CAP ————CTS<3:0>---- 0 000 ---- 0000
295h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
296h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu
297h CCP2CON EN — OUT FMT MODE<3:0> 0-00 0000 0-00 0000
298h CCP2CAP ————CTS<3:0>---- 0 000 ---- 0000
299h CCPR7L Capture/Compare/PWM Register 7 (LSB) xxxx xxxx uuuu uuuu
29Ah CCPR7H Capture/Compare/PWM Register 7 (MSB) xxxx xxxx uuuu uuuu
29Bh CCP7CON EN — OUT FMT MODE<3:0> 0-00 0000 0-00 0000
29Ch CCP7CAP ————CTS<3:0>---- 0000 ---- 0000
29Dh —Unimplemented — —
29Eh CCPTMRS1 C8TSEL<1:0>(3) C7TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> --00 0000 --00 0000
29Fh CCPTMRS2 P10TSEL<1:0>(3) P9TSEL<1:0> P4TSEL<1:0> P3TSEL<1:0> --00 0000 --00 0000
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
2015-2016 Microchip Technology Inc. DS40001819B-page 63
PIC16(L)F1777/8/9
Bank 6
30Ch SLRCONA SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 1111 1111 1111 1111
30Dh SLRCONB SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 1111 1111 1111 1111
30Eh SLRCONC SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 1111 1111 1111 1111
30Fh SLRCOND(3) SLRD7 SLRD6 SLRD5 SLRD4 SLRD3 SLRD2 SLRD1 SLRD0 1111 1111 1111 1111
310h SLRCONE(3) ————— SLRE2 SLRE1 SLRE0 ---- -111 ---- -111
311h CCPR8L Capture/Compare/PWM Register 8 (LSB) xxxx xxxx uuuu uuuu
312h CCPR8H Capture/Compare/PWM Register 8 (MSB) xxxx xxxx uuuu uuuu
313h CCP8CON EN — OUT FMT MODE<3:0> 0-00 0000 0-00 0000
314h CCP8CAP ————CTS<3:0>---- 0000 ---- 0000
315h MD1CON0 EN — OUT OPOL — — —BIT0-00 ---0 0-00 ---0
316h MD1CON1 —— CHPOL CHSYNC —— CLPOL CLSYNC --00 --00 - -00 - -00
317h MD1SRC — — —MS<4:0>---0 0000 ---0 0 000
318h MD1CARL — — — CL<4:0> ---0 0000 ---0 0000
319h MD1CARH — — — CH<4:0> ---0 0000 ---0 0000
31Ah —Unimplemented — —
31Bh MD2CON0 EN — OUT OPOL — — —BIT0-00 ---0 0-00 ---0
31Ch MD2CON1 —— CHPOL CHSYNC —— CLPOL CLSYNC --00 - -00 --00 --00
31Dh MD2SRC — — —MS<4:0>---0 0000 ---0 0000
31Eh MD2CARL — — — CL<4:0> ---0 0000 ---0 0000
31Fh MD2CARH — — — CH<4:0> ---0 0000 ---0 0000
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
PIC16(L)F1777/8/9
DS40001819B-page 64 2015-2016 Microchip Technology Inc.
Bank 7
38Ch INLVLA INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 1111 1111 1111 1111
38Dh INLVLB INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0 1111 1111 1111 1111
38Eh INLVLC INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 1111 1111 1111 1111
38Fh INLVLD(3) INLVLD7 INLVLD6 INLVLD5 INLVLD4 INLVLD3 INLVLD2 INLVLD1 INLVLD0 1111 1111 1111 1111
390h INLVLE(3) ———— INLVLE3 INLVLE2 INLVLE1 INLVLE0 ---- 1111 ---- 1111
391h IOCAP IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 0000 0000 0000 0000
392h IOCAN IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 0000 0000 0000 0000
393h IOCAF IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 0000 0000 0000 0000
394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 0000 0000 0000 0000
395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 0000 0000 0000 0000
396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0000 0000 0000 0000
397h IOCCP IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 0000 0 000 0000 0000
398h IOCCN IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 0000 0000 0000 0000
399h IOCCF IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 0000 0000 0000 0000
39Ah —Unimplemented — —
39Bh —Unimplemented — —
39Ch —Unimplemented — —
39Dh IOCEP ———— IOCEP3 ———---- 0--- ---- 0---
39Eh IOCEN ———— IOCEN3 ———---- 0--- ---- 0---
39Fh IOCEF ———— IOCEF3 ———---- 0--- ---- 0---
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
2015-2016 Microchip Technology Inc. DS40001819B-page 65
PIC16(L)F1777/8/9
Bank 8
40Ch
—
40Ch —Unimplemented — —
40Dh HIDRVB —————— HIDB1 HIDB0 ---- - -00 ---- --00
40Eh —Unimplemented — —
40Fh TMR5L Holding Register for the Least Significant Byte of the 16-bit TMR5 Register xxxx x xxx uuuu uuuu
410h TMR5H Holding Register for the Most Significant Byte of the 16-bit TMR5 Register xxxx xxxx uuuu uuuu
411h T5CON CS<1:0> CKPS<1:0> OSCEN SYNC —ON0000 00-0 uuuu uu-u
412h T5GCON GE GPOL GTM GSPM GGO/
DONE
GVAL GSS<1:0> 0000 0 x00 uuuu uxuu
413h T4TMR Holding Register for the 8-bit TMR4 Register 0000 0000 0000 0000
414h T4PR TMR4 Period Register 1111 1111 1111 1111
415h T4CON ON CKPS<2:0> OUTPS<3:0> 0000 0000 0000 0000
416h T4HLT PSYNC CKPOL CKSYNC MODE<4:0> - --0 0000 - --0 0 000
417h T4CLKCON ————CS<3:0>---- 0000 ---- 0000
418h T4RST — — — RSEL<4:0> - --0 0000 - --0 0 000
419h —Unimplemented — —
41Ah T6TMR Holding Register for the 8-bit TMR6 Register 0000 0000 0000 0000
41Bh T6PR TMR6 Period Register 1 111 1 111 1111 1111
41Ch T6CON ON CKPS<2:0> OUTPS<3:0> 0000 0000 0000 0000
41Dh T6HLT PSYNC CKPOL CKSYNC MODE<4:0> ---0 0000 ---0 0000
41Eh T6CLKCON ————CS<3:0>---- 0 000 ---- 0000
41Fh T6RST — — — RSEL<4:0> ---0 0000 ---0 0000
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
PIC16(L)F1777/8/9
DS40001819B-page 66 2015-2016 Microchip Technology Inc.
Bank 9
48Ch
to
48Dh
—Unimplemented — —
48Eh ADRESL ADC Result Register Low xxxx xxxx uuuu uuuu
48Fh ADRESH ADC Result Register High xxxx xxxx uuuu uuuu
490h ADCON0 CHS<5:0>
GO/DONE
ADON 0000 0 000 0000 0000
491h ADCON1 ADFM ADCS<2:0> — ADNREF ADPREF<1:0> 0000 -000 0000 -000
492h ADCON2 —— TRIGSEL<5:0> --00 0000 --00 0000
493h T2TMR Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000
494h T2PR TMR2 Period Register 1111 1111 1111 1111
495h T2CON ON CKPS<2:0> OUTPS<3:0> 0000 0000 0000 0000
496h T2HLT PSYNC CKPOL CKSYNC MODE<4:0> 0 000 0000 0 000 0 000
497h T2CLKCON ————CS<3:0>---- 0000 ---- 0000
498h T2RST — — — RSEL<4:0> - --0 0000 - --0 0 000
499h —Unimplemented — —
49Ah T8TMR Holding Register for the 8-bit TMR8 Register 0000 0000 0000 0000
49Bh T8PR TMR8 Period Register 1 111 1 111 1111 1111
49Ch T8CON ON CKPS<2:0> OUTPS<3:0> 0000 0000 0000 0000
49Dh T8HLT PSYNC CKPOL CKSYNC MODE<4:0> 0000 0000 0000 0000
49Eh T8CLKCON ————CS<3:0>---- 0 000 ---- 0000
49Fh T8RST — — — RSEL<4:0> ---0 0000 ---0 0000
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
2015-2016 Microchip Technology Inc. DS40001819B-page 67
PIC16(L)F1777/8/9
Bank 10
50Ch
—
50Eh —Unimplemented — —
50Fh OPA1NCHS ———— NCH<3:0> ---- 0000 - --- 0 000
510h OPA1PCHS ———— PCH<3:0> ---- 0 000 ---- 0000
511h OPA1CON EN ——UG— ORPOL ORM<1:0> 0--0 -000 0--0 -000
512h OPA1ORS — — —ORS<4:0>---0 0000 ---0 0000
513h OPA2NCHS ———— NCH<3:0> ---- 0000 - --- 0 000
514h OPA2PCHS ———— PCH<3:0> ---- 0 000 ---- 0000
515h OPA2CON EN ——UG— ORPOL ORM<1:0> 0--0 -000 0--0 -000
516h OPA2ORS — — —ORS<4:0>---0 0000 ---0 0000
517h OPA3NCHS ———— NCH<3:0> ---- 0000 - --- 0 000
518h OPA3PCHS ———— PCH<3:0> ---- 0 000 ---- 0000
519h OPA3CON EN SP —UG— ORPOL ORM<1:0> 00-0 -000 00-0 -000
51Ah OPA3ORS — — —ORS<4:0>---0 0000 ---0 0000
51Bh OPA4NCHS(3) ———— NCH<3:0> - --- 0 000 ---- 0000
51Ch OPA4PCHS(3) ———— PCH<3:0> ---- 0000 ---- 0000
51Dh OPA4CON(3) EN SP —UG— ORPOL ORM<1:0> 00-0 - 000 00-0 -000
51Eh OPA4ORS(3) — — —ORS<4:0>---0 0000 ---0 0000
51Fh —Unimplemented — —
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
PIC16(L)F1777/8/9
DS40001819B-page 68 2015-2016 Microchip Technology Inc.
Bank 1 1
58Ch —Unimplemented — —
58Dh DACLD —— DAC6LD(3) DAC5LD —— DAC2LD DAC1LD --00 --00 --00 --00
58Eh DAC1CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 0000 0000 0000 0000
58Fh DAC1REFL REF<7:0> 00000 0000 0000 0000
590h DAC1REFH REF<15:8> 00000 0000 0000 0000
591h DAC2CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 0000 0000 0000 0000
592h DAC2REFL REF<7:0> 00000 0000 0000 0000
593h DAC2REFH REF<15:8> 00000 0000 0000 0000
594h DAC3CON0 EN — OE1 OE2 PSS<1:0> NSS<1:0> 0-00 0000 0-00 0000
595h DAC3REF — — —REF<4:0>---0 0000 ---0 0 000
596h DAC4CON0 EN — OE1 OE2 PSS<1:0> NSS<1:0> 0-00 0000 0-00 0000
597h DAC4REF — — —REF<4:0>---0 0000 0000 0 000
598h DAC5CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 0000 0000 0000 0000
599h DAC5REFL REF<7:0> 00000 0000 0000 0000
59Ah DAC5REFH REF<15:8> 00000 0000 0000 0000
59Bh DAC6CON0(3) EN FM OE1 OE2 PSS<1:0> NSS<1:0> 0000 0000 0000 0000
59Ch DAC6REFL(3) REF<7:0> 00000 0000 0000 0000
59Dh DAC6REFH(3) REF<15:8> 00000 0000 0000 0000
59Eh DAC7CON0 EN — OE1 OE2 PSS<1:0> NSS<1:0> 0-00 0000 0-00 0000
59Fh DAC7REF — — —REF<4:0>---0 0000 0000 0000
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
2015-2016 Microchip Technology Inc. DS40001819B-page 69
PIC16(L)F1777/8/9
Bank 12
60Ch
to
613h
—Unimplemented — —
60Ch DAC8CON0(3) EN — OE1 OE2 PSS<1:0> NSS1 NSS0 0-00 0 000 0-00 0000
60Dh DAC8REF(3) — — —REF<4:0>---0 0000 0000 0000
60Eh PRG4RTSS(3) ———— RTSS<3:0> ---- 0000 ---- 0000
60Fh PRG4FTSS(3) ———— FTSS<3:0> ---- 0000 ---- 0000
610h PRG4INS(3) ————INS<3:0>---- 0000 ---- 0000
611h PRG4CON0(3) EN — FEDG REDG MODE<1:0> OS GO 0-000 0000 0-00 0000
612h PRG4CON1(3) ————— RDY FPOL RPOL - --- - 000 ---- -000
613h PRG4CON2(3) — — —ISET<4:0>---0 0000 ---0 0000
614h PWM3DCL DC<1:0> ——————xx-- ---- uu-- ----
615h PWM3DCH DC<9:2> xxxx xxxx uuuu uuuu
616h PWM3CON EN —OUTPOL— — — — 0-00 ---- 0-00 ----
617h PWM4DCL DC<1:0> ——————xx-- ---- uu-- ----
618h PWM4DCH DC<9:2> xxxx xxxx uuuu uuuu
619h PWM4CON EN —OUTPOL— — — — 0-00 ---- 0-00 ----
61Ah PWM9DCL DC<1:0> ——————xx-- ---- uu-- ----
61Bh PWM9DCH DC<9:2> xxxx xxxx u uuu u uuu
61Ch PWM9CON EN —OUTPOL— — — — 0-00 ---- 0-00 ----
61Dh PWM10DCL(3) DC<1:0> ——————xx-- ---- uu-- ----
61Eh PWM10DCH(3) DC<9:2> xxxx x xxx uuuu uuuu
61Fh PWM10CON(3) EN —OUTPOL— — — — 0-00 ---- 0-00 ----
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
PIC16(L)F1777/8/9
DS40001819B-page 70 2015-2016 Microchip Technology Inc.
Bank 13
68Ch —Unimplemented — —
68Dh COG1PHR — — COG Rising Edge Phase Delay Count Register --00 0000 --00 0000
68Eh COG1PHF — — COG Falling Edge Phase Delay Count Register --00 0000 --00 0000
68Fh COG1BLKR — — COG Rising Edge Blanking Count Register --00 0000 --00 0000
690h COG1BLKF — — COG Falling Edge Blanking Count Register --00 0000 --00 0000
691h COG1DBR — — COG Rising Edge Dead-band Count Register --00 0000 --00 0000
692h COG1DBF — — COG Falling Edge Dead-band Count Register --00 0000 --00 0000
693h COG1CON0 EN LD —CS<1:0> MD<2:0> 00-0 0000 00-0 0000
694h COG1CON1 RDBS FDBS —— POLD POLC POLB POLA 00-- 0000 00-- 0000
695h COG1RIS0 RIS7 RIS6 RIS5 RIS4 RIS3 RIS2 RIS1 RIS0 0000 0000 0000 0000
696h COG1RIS1 RIS15 RIS14 RIS13 RIS12 RIS11 RIS10 RIS9 RIS8 0000 0 000 0000 0000
697h COG1RSIM0 RSIM7 RSIM6 RSIM5 RSIM4 RSIM3 RSIM2 RSIM1 RSIM0 0000 0 000 0000 0000
698h COG1RSIM1 RSIM15 RSIM14 RSIM13 RSIM12 RSIM11 RSIM10 RSIM9 RSIM8 0000 0000 0000 0000
699h COG1FIS0 FIS7 FIS6 FIS5 FIS4 FIS3 FIS2 FIS1 FIS0 0000 0 000 0000 0000
69Ah COG1FIS1 FIS15 FIS14 FIS13 FIS12 FIS11 FIS10 FIS9 FIS8 0000 0000 0000 0000
69Bh COG1FSIM0 FSIM7 FSIM6 FSIM5 FSIM4 FSIM3 FSIM2 FSIM1 FSIM0 0000 0000 0000 0000
69Ch COG1FSIM1 FSIM15 FSIM14 FSIM13 FSIM12 FSIM11 FSIM10 FSIM9 FSIM8 0000 0000 0 000 0 000
69Dh COG1ASD0 ASE ARSEN ASDBD<1:0> ASDAC<1:0> — — 0001 01-- 0001 01--
69Eh COG1ASD1 AS7E AS6E AS5E AS4E AS3E AS2E AS1E AS0E 0000 0000 0000 0000
69Fh COG1STR SDATD SDATC SDATB SDATA STRD STRC STRB STRA 0000 0000 0000 0000
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
2015-2016 Microchip Technology Inc. DS40001819B-page 71
PIC16(L)F1777/8/9
Bank 14
70Ch —Unimplemented — —
70Dh COG2PHR — — COG Rising Edge Phase Delay Count Register --00 0000 --00 0000
70Eh COG2PHF — — COG Falling Edge Phase Delay Count Register --00 0000 --00 0000
70Fh COG2BLKR — — COG Rising Edge Blanking Count Register --00 0000 --00 0000
710h COG2BLKF — — COG Falling Edge Blanking Count Register --00 0000 --00 0000
711h COG2DBR — — COG Rising Edge Dead-band Count Register --00 0000 --00 0000
712h COG2DBF — — COG Falling Edge Dead-band Count Register --00 0000 --00 0000
713h COG2CON0 EN LD —CS<1:0> MD<2:0> 00-0 0000 00-0 0000
714h COG2CON1 RDBS FDBS —— POLD POLC POLB POLA 00-- 0000 00-- 0000
715h COG2RIS0 RIS7 RIS6 RIS5 RIS4 RIS3 RIS2 RIS1 RIS0 0000 0000 0000 0000
716h COG2RIS1 RIS15 RIS14 RIS13 RIS12 RIS11 RIS10 RIS9 RIS8 0000 0 000 0000 0000
717h COG2RSIM0 RSIM7 RSIM6 RSIM5 RSIM4 RSIM3 RSIM2 RSIM1 RSIM0 0000 0 000 0000 0000
718h COG2RSIM1 RSIM15 RSIM14 RSIM13 RSIM12 RSIM11 RSIM10 RSIM9 RSIM8 0000 0000 0000 0000
719h COG2FIS0 FIS7 FIS6 FIS5 FIS4 FIS3 FIS2 FIS1 FIS0 0000 0 000 0000 0000
71Ah COG2FIS1 FIS15 FIS14 FIS13 FIS12 FIS11 FIS10 FIS9 FIS8 0000 0000 0000 0000
71Bh COG2FSIM0 FSIM7 FSIM6 FSIM5 FSIM4 FSIM3 FSIM2 FSIM1 FSIM0 0000 0000 0000 0000
71Ch COG2FSIM1 FSIM15 FSIM14 FSIM13 FSIM12 FSIM11 FSIM10 FSIM9 FSIM8 0000 0000 0 000 0 000
71Dh COG2ASD0 ASE ARSEN ASDBD<1:0> ASDAC<1:0> — — 0001 01-- 0001 01--
71Eh COG2ASD1 AS7E AS6E AS5E AS4E AS3E AS2E AS1E AS0E 0000 0000 0000 0000
71Fh COG2STR SDATD SDATC SDATB SDATA STRD STRC STRB STRA 0000 0000 0000 0000
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
PIC16(L)F1777/8/9
DS40001819B-page 72 2015-2016 Microchip Technology Inc.
Bank 15
78Ch
—
78Dh
—Unimplemented — —
78Eh PRG1RTSS ———— RTSS<3:0> ---- 0000 ---- 0000
78Fh PRG1FTSS ———— FTSS<3:0> ---- 0000 ---- 0000
790h PRG1INS ————INS<3:0>---- 0000 ---- 0000
791h PRG1CON0 EN — FEDG REDG MODE<1:0> OS GO 0-000 0000 0-00 0000
792h PRG1CON1 ————— RDY FPOL RPOL - --- - 000 ---- -000
793h PRG1CON2 — — —ISET<4:0>---0 0000 ---0 0000
794h PRG2RTSS ———— RTSS<3:0> ---- 0000 ---- 0000
795h PRG2FTSS ———— FTSS<3:0> ---- 0000 ---- 0000
796h PRG2INS ————INS<3:0>---- 0000 ---- 0000
797h PRG2CON0 EN — FEDG REDG MODE<1:0> OS GO 0-000 0000 0-00 0000
798h PRG2CON1 ————— RDY FPOL RPOL - --- - 000 ---- -000
799h PRG2CON2 — — —ISET<4:0>---0 0000 ---0 0000
79Ah PRG3RTSS ———— RTSS<3:0> ---- 0000 ---- 0000
79Bh PRG3FTSS ———— FTSS<3:0> ---- 0000 ---- 0000
79Ch PRG3INS ————INS<3:0>---- 0000 ---- 0000
79Dh PRG3CON0 EN — FEDG REDG MODE<1:0> OS GO 0- 000 0000 0-00 0000
79Eh PRG3CON1 ————— RDY FPOL RPOL ---- -000 ---- -000
79Fh PRG3CON2 — — —ISET<4:0>---0 0000 ---0 0000
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
2015-2016 Microchip Technology Inc. DS40001819B-page 73
PIC16(L)F1777/8/9
Bank 16
80Ch —Unimplemented — —
80Dh COG3PHR — — COG Rising Edge Phase Delay Count Register --00 0000 --00 0000
80Eh COG3PHF — — COG Falling Edge Phase Delay Count Register --00 0000 --00 0000
80Fh COG3BLKR — — COG Rising Edge Blanking Count Register --00 0000 --00 0000
810h COG3BLKF — — COG Falling Edge Blanking Count Register --00 0000 --00 0000
811h COG3DBR — — COG Rising Edge Dead-band Count Register --00 0000 --00 0000
812h COG3DBF — — COG Falling Edge Dead-band Count Register --00 0000 --00 0000
813h COG3CON0 EN LD —CS<1:0> MD<2:0> 00-0 0000 00-0 0000
814h COG3CON1 RDBS FDBS —— POLD POLC POLB POLA 00-- 0000 00-- 0000
815h COG3RIS0 RIS7 RIS6 RIS5 RIS4 RIS3 RIS2 RIS1 RIS0 0000 0000 0000 0000
816h COG3RIS1 RIS15 RIS14 RIS13 RIS12 RIS11 RIS10 RIS9 RIS8 0000 0000 0000 0000
817h COG3RSIM0 RSIM7 RSIM6 RSIM5 RSIM4 RSIM3 RSIM2 RSIM1 RSIM0 0 000 0000 0 000 0 000
818h COG3RSIM1 RSIM15 RSIM14 RSIM13 RSIM12 RSIM11 RSIM10 RSIM9 RSIM8 0000 0 000 0000 0000
819h COG3FIS0 FIS7 FIS6 FIS5 FIS4 FIS3 FIS2 FIS1 FIS0 0000 0000 0000 0000
81Ah COG3FIS1 FIS15 FIS14 FIS13 FIS12 FIS11 FIS10 FIS9 FIS8 0000 0000 0000 0000
81Bh COG3FSIM0 FSIM7 FSIM6 FSIM5 FSIM4 FSIM3 FSIM2 FSIM1 FSIM0 0000 0000 0000 0000
81Ch COG3FSIM1 FSIM15 FSIM14 FSIM13 FSIM12 FSIM11 FSIM10 FSIM9 FSIM8 0 000 0 000 0000 0000
81Dh COG3ASD0 ASE ARSEN ASDBD<1:0> ASDAC<1:0> — — 0001 01-- 0001 01--
81Eh COG3ASD1 AS7E AS6E AS5E AS4E AS3E AS2E AS1E AS0E 0000 0000 0000 0000
81Fh COG3STR SDATD SDATC SDATB SDATA STRD STRC STRB STRA 0000 0000 0000 0000
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
PIC16(L)F1777/8/9
DS40001819B-page 74 2015-2016 Microchip Technology Inc.
Bank 17
88Ch —Unimplemented — —
88Dh COG4PHR(3) — — COG Rising Edge Phase Delay Count Register --00 0 000 --00 0000
88Eh COG4PHF(3) — — COG Falling Edge Phase Delay Count Register --00 0000 --00 0000
88Fh COG4BLKR(3) — — COG Rising Edge Blanking Count Register --00 0 000 --00 0000
890h COG4BLKF(3) — — COG Falling Edge Blanking Count Register - -00 0 000 --00 0000
891h COG4DBR(3) — — COG Rising Edge Dead-band Count Register --00 0 000 --00 0000
892h COG4DBF(3) — — COG Falling Edge Dead-band Count Register --00 0000 --00 0000
893h COG4CON0(3) EN LD —CS<1:0> MD<2:0> 00-0 0000 00-0 0000
894h COG4CON1(3) RDBS FDBS —— POLD POLC POLB POLA 00-- 0 000 00-- 0000
895h COG4RIS0(3) RIS7 RIS6 RIS5 RIS4 RIS3 RIS2 RIS1 RIS0 0000 0000 0000 0000
896h COG4RIS1(3) RIS15 RIS14 RIS13 RIS12 RIS11 RIS10 RIS9 RIS8 0000 0000 0000 0000
897h COG4RSIM0(3) RSIM7 RSIM6 RSIM5 RSIM4 RSIM3 RSIM2 RSIM1 RSIM0 0 000 0 000 0000 0000
898h COG4RSIM1(3) RSIM15 RSIM14 RSIM13 RSIM12 RSIM11 RSIM10 RSIM9 RSIM8 0000 0000 0000 0000
899h COG4FIS0(3) FIS7 FIS6 FIS5 FIS4 FIS3 FIS2 FIS1 FIS0 0000 0000 0 000 0 000
89Ah COG4FIS1(3) FIS15 FIS14 FIS13 FIS12 FIS11 FIS10 FIS9 FIS8 0000 0000 0000 0000
89Bh COG4FSIM0(3) FSIM7 FSIM6 FSIM5 FSIM4 FSIM3 FSIM2 FSIM1 FSIM0 0000 0000 0000 0000
89Ch COG4FSIM1(3) FSIM15 FSIM14 FSIM13 FSIM12 FSIM11 FSIM10 FSIM9 FSIM8 0 000 0 000 0000 0000
89Dh COG4ASD0(3) ASE ARSEN ASDBD<1:0> ASDAC<1:0> — — 0001 01-- 0001 01--
89Eh COG4ASD1(3) AS7E AS6E AS5E AS4E AS3E AS2E AS1E AS0E 0000 0000 0000 0000
89Fh COG4STR(3) SDATD SDATC SDATB SDATA STRD STRC STRB STRA 0000 0 000 0000 0000
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
2015-2016 Microchip Technology Inc. DS40001819B-page 75
PIC16(L)F1777/8/9
Bank 18
90Ch CM4CON0 ON OUT —POL ZLF Reserved HYS SYNC 00-0 0 100 00-0 0100
90Dh CM4CON1 — — — — — — INTP INTN ---- --00 ---- --00
90Eh CM4NSEL — — — — NCH<3:0> ---- 0 000 ---- 0000
90Fh CM4PSEL — — — — PCH<3:0> ---- 0000 ---- 0000
910h CM5CON0 ON OUT —POL ZLF Reserved HYS SYNC 00-0 0 100 00-0 0100
911h CM5CON1 — — — — — — INTP INTN ---- --00 ---- - -00
912h CM5NSEL — — — — NCH<3:0> ---- 0 000 ---- 0000
913h CM5PSEL — — — — PCH<3:0> ---- 0000 ---- 0000
914h CM6CON0 ON OUT —POL ZLF Reserved HYS SYNC 00-0 0 100 00-0 0100
915h CM6CON1 — — — — — — INTP INTN ---- --00 ---- --00
916h CM6NSEL — — — — NCH<3:0> ---- 0 000 ---- 0000
917h CM6PSEL — — — — PCH<3:0> ---- 0000 ---- 0000
918h CM7CON0(3) ON OUT —POL ZLF Reserved HYS SYNC 00-0 0100 00-0 0100
919h CM7CON1(3) — — — — — — INTP INTN ---- - -00 ---- --00
91Ah CM7NSEL(3) — — — — NCH<3:0> ---- 0000 ---- 0 000
91Bh CM7PSEL(3) — — — — PCH<3:0> ---- 0 000 ---- 0000
91Ch CM8CON0(3) ON OUT —POL ZLF Reserved HYS SYNC 00-0 0100 00-0 0100
91Dh CM8CON1(3) — — — — — — INTP INTN ---- --00 ---- --00
91Eh CM8NSEL(3) — — — — NCH<3:0> ---- 0000 ---- 0 000
91Fh CM8PSEL(3) — — — — PCH<3:0> ---- 0000 ---- 0000
Bank 19-25
x0Ch/
x8Ch
—
x1Fh/
x9Fh
—Unimplemented — —
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
PIC16(L)F1777/8/9
DS40001819B-page 76 2015-2016 Microchip Technology Inc.
Bank 26
D0Ch
—
D1Ah
—Unimplemented — —
D1Bh MD4CON0(3) EN — OUT OPOL — — —BIT0-00 ---0 0-00 ---0
D1Ch MD4CON1(3) —— CHPOL CHSYNC —— CLPOL CLSYNC --00 --00 - -00 - -00
D1Dh MD4SRC(3) — — —MS<4:0>---0 0 000 ---0 0000
D1Eh MD4CARL(3) — — — CL<4:0> ---0 0000 ---0 0000
D1Fh MD4CARH(3) — — — CH<4:0> ---0 0 000 ---0 0000
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
PIC16(L)F1777/8/9
DS40001819B-page 77 2015-2016 Microchip Technology Inc.
Bank 27
D8Ch —Unimplemented — —
D8Dh —Unimplemented — —
D8Eh PWMEN ————MPWM12EN
(3) MPWM11EN MPWM6EN MPWM5EN - --- 0000 - --- 0 000
D8Fh PWMLD ———— MPWM12LD(3) MPWM11LD MPWM6LD MPWM5LD ---- 0000 ---- 0000
D90h PWMOUT ———— MPWM12OUT(3) MPWM11OUT MPWM6OUT MPWM5OUT ---- 0000 - --- 0 000
D91h PWM5PHL PH<7:0> x xxx x xxx uuuu uuuu
D92h PWM5PHH PH<15:8> xxxx xxxx uuuu uuuu
D93h PWM5DCL DC<7:0> x xxx x xxx uuuu uuuu
D94h PWM5DCH DC<15:8> xxxx xxxx uuuu uuuu
D95h PWM5PRL PR<7:0> x xxx x xxx uuuu uuuu
D96h PWM5PRH PR<15:8> xxxx xxxx uuuu uuuu
D97h PWM5OFL OF<7:0> xxxx xxxx uuuu uuuu
D98h PWM5OFH OF<15:8> xxxx xxxx uuuu uuuu
D99h PWM5TMRL TMR<7:0> 0000 0000 0000 0000
D9Ah PWM5TMRH TMR<15:8> 0000 0000 0000 0000
D9Bh PWM5CON EN — OUT POL MODE<1:0> — — 0-00 00-- 0-00 00--
D9Ch PWM5INTE ———— OFIE PHIE DCIE PRIE ---- 0000 ---- 0000
D9Dh PWM5INTF ———— OFIF PHIF DCIF PRIF ---- 0 000 ---- 0000
D9Eh PWM5CLKCON — PS<2:0> ——CS<1:0>-000 --00 -000 --00
D9Fh PWM5LDCON LDA LDT ————LDS<1:0>00-- --00 00-- --00
DA0h PWM5OFCON — OFM<1:0> OFO ——OFS<1:0>-000 --00 -000 --00
DA1h PWM6PHL PH<7:0> xxxx x xxx uuuu uuuu
DA2h PWM6PHH PH<15:8> xxxx x xxx uuuu uuuu
DA3h PWM6DCL DC<7:0> xxxx xxxx uuuu uuuu
DA4h PWM6DCH DC<15:8> xxxx x xxx uuuu uuuu
DA5h PWM6PRL PR<7:0> xxxx xxxx uuuu uuuu
DA6h PWM6PRH PR<15:8> xxxx x xxx uuuu uuuu
DA7h PWM6OFL OF<7:0> xxxx xxxx uuuu uuuu
DA8h PWM6OFH OF<15:8> xxxx xxxx uuuu uuuu
DA9h PWM6TMRL TMR<7:0> 0000 0000 0000 0000
DAAh PWM6TMRH TMR<15:8> 0000 0000 0000 0000
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
2015-2016 Microchip Technology Inc. DS40001819B-page 78
PIC16(L)F1777/8/9
Bank 27 (Continued)
DABh PWM6CON EN — OUT POL MODE<1:0> — — 0-00 00-- 0-00 00--
DACh PWM6INTE ———— OFIE PHIE DCIE PRIE ---- 0 000 ---- 0000
DADh PWM6INTF ———— OFIF PHIF DCIF PRIF - --- 0 000 ---- 0000
DAEh PWM6CLKCON — PS<2:0> ——CS<1:0>-000 --00 -000 --00
DAFh PWM6LDCON LDA LDT ————LDS<1:0>00-- --00 00-- --00
DB0h PWM6OFCON — OFM<1:0> OFO ——OFS<1:0>-000 --00 -000 --00
DB1h PWM11PHL PH<7:0> xxxx xxxx uuuu uuuu
DB2h PWM11PHH PH<15:8> xxxx x xxx uuuu uuuu
DB3h PWM11DCL DC<7:0> xxxx xxxx uuuu uuuu
DB4h PWM11DCH DC<15:8> xxxx xxxx uuuu uuuu
DB5h PWM11PRL PR<7:0> xxxx xxxx uuuu uuuu
DB6h PWM11PRH PR<15:8> xxxx x xxx uuuu uuuu
DB7h PWM11OFL OF<7:0> xxxx xxxx uuuu uuuu
DB8h PWM11OFH OF<15:8> xxxx xxxx uuuu uuuu
DB9h PWM11TMRL TMR<7:0> 0000 0000 0000 0000
DBAh PWM11TMRH TMR<15:8> 0000 0000 0000 0000
DBBh PWM11CON EN — OUT POL MODE<1:0> — — 0-00 00-- 0-00 00--
DBCh PWM11INTE ———— OFIE PHIE DCIE PRIE ---- 0000 ---- 0000
DBDh PWM11INTF ———— OFIF PHIF DCIF PRIF ---- 0000 ---- 0000
DBEh PWM11CLKCON — PS<2:0> ——CS<1:0>-000 --00 -000 --00
DBFh PWM11LDCON LDA LDT ————LDS<1:0>00-- --00 00-- --00
DC0h PWM11OFCON — OFM<1:0> OFO ——OFS<1:0>-000 --00 -000 --00
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
PIC16(L)F1777/8/9
DS40001819B-page 79 2015-2016 Microchip Technology Inc.
Bank 27 (Continued)
DC1h PWM12PHL(3) PH<7:0> xxxx xxxx uuuu uuuu
DC2h PWM12PHH(3) PH<15:8> xxxx xxxx uuuu uuuu
DC3h PWM12DCL(3) DC<7:0> x xxx x xxx uuuu uuuu
DC4h PWM12DCH(3) DC<15:8> xxxx xxxx uuuu uuuu
DC5h PWM12PRL(3) PR<7:0> xxxx xxxx uuuu uuuu
DC6h PWM12PRH(3) PR<15:8> xxxx xxxx uuuu uuuu
DC7h PWM12OFL(3) OF<7:0> xxxx xxxx uuuu uuuu
DC8h PWM12OFH(3) OF<15:8> xxxx x xxx uuuu uuuu
DC9h PWM12TMRL(3) TMR<7:0> 0000 0000 0000 0000
DCAh PWM12TMRH(3) TMR<15:8> 0000 0000 0000 0000
DCBh PWM12CON(3) EN — OUT POL MODE<1:0> — — 0-00 0 0-- 0-00 00--
DCCh PWM12INTE(3) ———— OFIE PHIE DCIE PRIE ---- 0 000 ---- 0000
DCDh PWM12INTF(3) ———— OFIF PHIF DCIF PRIF - --- 0 000 ---- 0000
DCEh PWM12CLKCON(3) — PS<2:0> ——CS<1:0>-000 --00 -000 --00
DCFh PWM12LDCON(3) LDA LDT ————LDS<1:0>00-- --00 00-- --00
DD0h PWM12OFCON(3) — OFM<1:0> OFO ——OFS<1:0>-000 --00 -000 --00
DD1h
to
DEFh
—Unimplemented — —
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
2015-2016 Microchip Technology Inc. DS40001819B-page 80
PIC16(L)F1777/8/9
Bank 28
E0Ch
—
E0Bh
—Unimplemented — —
E0Ch PPSLOCK ——————— PPSLOCKED ---- ---0 ---- ---0
E0Dh INTPPS —— INTPPS<5:0> --00 1000 --uu uuuu
E0Eh T0CKIPPS —— T0CKIPPS<5:0> --00 0100 --uu uuuu
E0Fh T1CKIPPS —— T1CKIPPS<5:0> --01 0000 --uu uuuu
E10h T1GPPS —— T1GPPS<5:0> --00 1101 --uu uuuu
E11h T3CKIPPS —— T3CKIPPS<5:0> --01 0000 --uu uuuu
E12h T3GPPS —— T3GPPS<5:0> --01 0000 --uu uuuu
E13h T5CKIPPS —— T5CKIPPS<5:0> --01 0000 --uu uuuu
E14h T5GPPS —— T5GPPS<5:0> --00 1100 --uu uuuu
E15h T2INPPS —— T2INPPS<5:0> --01 0011 --uu uuuu
E16h T4INPPS —— T4INPPS<5:0> --01 0101 --uu uuuu
E17h T6INPPS —— T6INPPS<5:0> --01 0100 --uu uuuu
E18h T8INPPS —— T8INPPS<5:0> --01 0010 --uu uuuu
E19h CCP1PPS —— CCP1PPS<5:0> --01 0010 --uu uuuu
E1Ah CCP2PPS —— CCP2PPS<5:0> --01 0001 --uu uuuu
E1Bh CCP7PPS —— CCP7PPS<5:0> --00 1101 --uu uuuu
E1Ch CCP8PPS(3) —— CCP8PPS<5:0> --00 1101 --uu uuuu
E1Dh COGIN1PPS —— COG1PPS<5:0> --00 1000 --uu uuuu
E1Eh COG2INPPS —— COG2PPS<5:0> --00 1001 --uu uuuu
E1Fh COG3INPPS —— COG3PPS<5:0> --00 1010 --uu uuuu
E20h COG4INPPS(3) —— COG4PPS<5:0> --00 1010 --uu uuuu
E21h MD1CLPPS —— MD1CLPPS<5:0> --00 0100 --uu uuuu
E22h MD1CHPPS —— MD1CHPPS<5:0> --00 0011 --uu uuuu
E23h MD1MODPPS —— MD1MODPPS<5:0> --00 0101 --uu uuuu
E24h MD2CLPPS —— MD2CLPPS<5:0> --00 0100 --uu uuuu
E25h MD2CHPPS —— MD2CHPPS<5:0> --00 0011 --uu uuuu
E26h MD2MODPPS — — MD2MODPPS<5:0> - -00 0 101 --uu uuuu
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
PIC16(L)F1777/8/9
DS40001819B-page 81 2015-2016 Microchip Technology Inc.
Bank 28 (Continued)
E27h MD3CLPPS —— MD3CLPPS<5:0> --00 1100 --uu uuuu
E28h MD3CHPPS —— MD3CHPPS<5:0> --00 1011 --uu uuuu
E29h MD3MODPPS —— MD3MODPPS<5:0> --00 0101 --uu uuuu
E2Ah MD4CLPPS(3) —— MD4CLPPS<5:0> --00 1100 --uu uuuu
E2Bh MD4CHPPS(3) —— MD4CHPPS<5:0> --00 1011 --uu uuuu
E2Ch MD4MODPPS(3) —— MD4MODPPS<5:0> --00 0101 --uu uuuu
E2Dh PRG1RPPS —— PRG1RPPS<5:0> --00 0100 --uu uuuu
E2Eh PRG1FPPS —— PRG1FPPS<5:0> --00 0101 --uu uuuu
E2Fh PRG2RPPS —— PRG2RPPS<5:0> --01 0001 --uu uuuu
E30h PRG2FPPS —— PRG2FPPS<5:0> --01 0010 --uu uuuu
E31h PRG3RPPS —— PRG3RPPS<5:0> --01 0100 --uu uuuu
E32h PRG3FPPS —— PRG3FPPS<5:0> --01 0101 --uu uuuu
E33h PRG4RPPS(3) —— PRG4RPPS<5:0> --01 0100 --uu uuuu
E34h PRG4FPPS(3) —— PRG4FPPS<5:0> --01 0101 --uu uuuu
E35h CLC1IN0PPS —— CLCIN0PPS<5:0> --00 0000 --uu uuuu
E36h CLC1IN1PPS —— CLCIN1PPS<5:0> --00 0001 --uu uuuu
E37h CLC1IN2PPS —— CLCIN2PPS<5:0> --00 1110 --uu uuuu
E38h CLC1IN3PPS —— CLCIN3PPS<5:0> --00 1111 --uu uuuu
E39h ADCACTPPS —— ADCACTPPS<5:0> --00 1100 --uu uuuu
E3Ah SSPCLKPPS —— SSPCLKPPS<5:0> --01 0011 --uu uuuu
E3Bh SSPDATPPS —— SSPDATPPS<5:0> --01 0100 --uu uuuu
E3Ch SSPSSPPS —— SSPSSPPS<5:0> --00 0101 --uu uuuu
E3Dh RXPPS —— RXPPS<5:0> --01 0111 --uu uuuu
E3Eh CKPPS —— CKPPS<5:0> --01 0110 --uu uuuu
E3Fh
—
E6Fh
—Unimplemented — —
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
2015-2016 Microchip Technology Inc. DS40001819B-page 82
PIC16(L)F1777/8/9
Bank 29
E8Ch
—
E8Fh
—Unimplemented — —
E90h RA0PPS —— RA0PPS<4:0> --00 0 000 --uu uuuu
E91h RA1PPS —— RA1PPS<4:0> --00 0 000 --uu uuuu
E92h RA2PPS —— RA2PPS<4:0> --00 0 000 --uu uuuu
E93h RA3PPS —— RA3PPS<4:0> --00 0 000 --uu uuuu
E94h RA4PPS —— RA4PPS<4:0> --00 0 000 --uu uuuu
E95h RA5PPS —— RA5PPS<4:0> --00 0 000 --uu uuuu
E96h RA6PPS —— RA6PPS<4:0> --00 0 000 --uu uuuu
E97h RA7PPS —— RA7PPS<4:0> --00 0 000 --uu uuuu
E98h RB0PPS —— RB0PPS<5:0> --00 0000 --uu uuuu
E99h RB1PPS —— RB1PPS<5:0> --00 0000 --uu uuuu
E9Ah RB2PPS —— RB2PPS<5:0> --00 0000 --uu uuuu
E9Bh RB3PPS —— RB3PPS<5:0> --00 0000 --uu uuuu
E9Ch RB4PPS —— RB4PPS<5:0> --00 0 000 --uu uuuu
E9Dh RB5PPS —— RB5PPS<5:0> --00 0 000 --uu uuuu
E9Eh RB6PPS —— RB6PPS<5:0> --00 0000 --uu uuuu
E9Fh RB7PPS —— RB7PPS<5:0> - -00 0 000 --uu uuuu
EA0h RC0PPS —— RC0PPS<5:0> --00 0000 --uu uuuu
EA1h RC1PPS —— RC1PPS<5:0> --00 0000 --uu uuuu
EA2h RC2PPS —— RC2PPS<5:0> --00 0000 --uu uuuu
EA3h RC3PPS —— RC3PPS<5:0> --00 0000 --uu uuuu
EA4h RC4PPS —— RC4PPS<5:0> --00 0000 --uu uuuu
EA5h RC5PPS —— RC5PPS<5:0> --00 0000 --uu uuuu
EA6h RC6PPS —— RC6PPS<5:0> --00 0000 --uu uuuu
EA7h RC7PPS —— RC7PPS<5:0> --00 0000 --uu uuuu
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
PIC16(L)F1777/8/9
DS40001819B-page 83 2015-2016 Microchip Technology Inc.
Bank 29 (Cont.)
EA8h RD0PPS(3) —— RD0PPS<5:0> --00 0 000 --uu uuuu
EA9h RD1PPS(3) —— RD1PPS<5:0> --00 0 000 --uu uuuu
EAAh RD2PPS(3) —— RD2PPS<5:0> - -00 0 000 --uu uuuu
EABh RD3PPS(3) —— RD3PPS<5:0> - -00 0 000 --uu uuuu
EACh RD4PPS(3) —— RD4PPS<5:0> --00 0 000 --uu uuuu
EADh RD5PPS(3) —— RD5PPS<5:0> --00 0 000 --uu uuuu
EAEh RD6PPS(3) —— RD6PPS<5:0> - -00 0 000 --uu uuuu
EAFh RD7PPS(3) —— RD7PPS<5:0> --00 0000 - -uu u uuu
EB0h RE0PPS(3) —— RE0PPS<5:0> --00 0 000 --uu uuuu
EB1h RE1PPS(3) —— RE1PPS<5:0> --00 0 000 --uu uuuu
EB2h RE2PPS(3) —— RE2PPS<5:0> --00 0 000 --uu uuuu
EB3h
to
EEFh
—Unimplemented — —
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
2015-2016 Microchip Technology Inc. DS40001819B-page 84
PIC16(L)F1777/8/9
Bank 30
F0Ch
—
F0Eh
—Unimplemented — —
F0Fh CLCDATA ———— MLC4OUT MLC3OUT MLC2OUT MLC1OUT ---- x000 ---- u000
F10h CLC1CON EN — OUT INTP INTN MODE<2:0> 0-00 0000 0-00 0000
F11h CLC1POL POL — — — G4POL G3POL G2POL G1POL 0--- xxxx 0 --- u uuu
F12h CLC1SEL0 ——D1S<5:0>--xx xxxx --uu uuuu
F13h CLC1SEL1 ——D2S<5:0>--xx xxxx --uu uuuu
F14h CLC1SEL2 ——D3S<5:0>--xx xxxx --uu uuuu
F15h CLC1SEL3 ——D4S<5:0>--xx xxxx --uu uuuu
F16h CLC1GLS0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N xxxx xxxx uuuu uuuu
F17h CLC1GLS1 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N xxxx xxxx uuuu uuuu
F18h CLC1GLS2 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N xxxx xxxx uuuu uuuu
F19h CLC1GLS3 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N xxxx xxxx uuuu uuuu
F1Ah CLC2CON EN — OUT INTP INTN MODE<2:0> 0-00 0000 0-00 0000
F1Bh CLC2POL POL — — — G4POL G3POL G2POL G1POL 0--- xxxx 0--- uuuu
F1Ch CLC2SEL0 ——D1S<5:0>--xx xxxx --uu uuuu
F1Dh CLC2SEL1 ——D2S<5:0>--xx xxxx --uu uuuu
F1Eh CLC2SEL2 ——D3S<5:0>--xx xxxx --uu uuuu
F1Fh CLC2SEL3 ——D4S<5:0>--xx xxxx --uu uuuu
F20h CLC2GLS0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N xxxx xxxx uuuu uuuu
F21h CLC2GLS1 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N xxxx xxxx uuuu uuuu
F22h CLC2GLS2 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N xxxx xxxx uuuu uuuu
F23h CLC2GLS3 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N xxxx xxxx uuuu uuuu
F24h CLC3CON EN — OUT INTP INTN MODE<2:0> 0-00 0000 0-00 0000
F25h CLC3POL POL — — — G4POL G3POL G2POL G1POL 0--- xxxx 0--- uuuu
F26h CLC3SEL0 ——D1S<5:0>--xx xxxx --uu uuuu
F27h CLC3SEL1 ——D2S<5:0>--xx xxxx --uu uuuu
F28h CLC3SEL2 ——D3S<5:0>--xx xxxx --uu uuuu
F29h CLC3SEL3 ——D4S<5:0>--xx xxxx --uu uuuu
F2Ah CLC3GLS0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N xxxx xxxx uuuu uuuu
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
PIC16(L)F1777/8/9
DS40001819B-page 85 2015-2016 Microchip Technology Inc.
Bank 30 (Continued)
F2Bh CLC3GLS1 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N xxxx xxxx uuuu uuuu
F2Ch CLC3GLS2 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N xxxx x xxx uuuu uuuu
F2Dh CLC3GLS3 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N xxxx x xxx uuuu uuuu
F2Eh CLC4CON EN OE OUT INTP INTN MODE<2:0> 0000 0000 0000 0000
F2Fh CLC4POL POL — — — G4POL G3POL G2POL G1POL 0--- xxxx 0--- uuuu
F30h CLC4SEL0 D1S<7:0> xxxx xxxx uuuu u uuu
F31h CLC4SEL1 D2S<7:0> xxxx xxxx uuuu u uuu
F32h CLC4SEL2 D3S<7:0> xxxx xxxx uuuu u uuu
F33h CLC4SEL3 D4S<7:0> xxxx xxxx uuuu u uuu
F34h CLC4GLS0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N xxxx xxxx uuuu uuuu
F35h CLC4GLS1 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N xxxx xxxx uuuu uuuu
F36h CLC4GLS2 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N xxxx xxxx uuuu uuuu
F37h CLC4GLS3 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N xxxx xxxx uuuu uuuu
F2Eh
—
F6Fh
—Unimplemented — —
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
2015-2016 Microchip Technology Inc. DS40001819B-page 86
PIC16(L)F1777/8/9
Bank 31
F8Ch
to
FE3h
—Unimplemented — —
FE4h STATUS_SHAD —————ZDCC- --- -xxx - --- - uuu
FE5h WREG_SHAD Working Register Shadow xxxx xxxx uuuu uuuu
FE6h BSR_SHAD — — — Bank Select Register Shadow ---x xxxx ---u uuuu
FE7h PCLATH_SHAD — Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu
FE8h FSR0L_SHAD Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu
FE9h FSR0H_SHAD Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu
FEAh FSR1L_SHAD Indirect Data Memory Address 1 Low Pointer Shadow xxxx x xxx uuuu uuuu
FEBh FSR1H_SHAD Indirect Data Memory Address 1 High Pointer Shadow xxxx x xxx uuuu uuuu
FECh —Unimplemented — —
FEDh STKPTR — — — Current Stack Pointer ---1 1111 ---1 1111
FEEh TOSL Top of Stack Low byte xxxx xxxx uuuu uuuu
FEFh TOSH — Top of Stack High byte -xxx xxxx -uuu uuuu
TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR V alue on all
other Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16LF1777/8/9.
3: Unimplemented on PIC16(L)F1778.
2015-2016 Microchip Technology Inc. DS40001819B-page 87
PIC16(L)F1777/8/9
3.5 PCL and PCLATH
The Program Counter (PC) is 15 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<14:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 3-4 shows the five
situations for the loading of the PC.
FIGURE 3-4: LOADING OF PC IN
DIFFERENT SITUATIONS
3.5.1 MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<14:8> bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the program counter to be changed by
writing the desired upper seven bits to the PCLATH
register. When the lower eight bits are written to the
PCL register, all 15 bits of the program counter will
change to the values contained in the PCLATH register
and those being written to the PCL register.
3.5.2 COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to
the program counter (ADDWF PCL). When performing a
table read using a computed GOTO method, care should
be exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to Application
Note AN556, “Implementing a Table Read” (DS00556).
3.5.3 COMPUTED FUNCTION CALLS
A computed function CALL allows programs to maintain
tables of functions and provide another way to execute
state machines or look-up tables. When performing a
table read using a computed function CALL, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block).
If using the CALL instruction, the PCH<2:0> and PCL
registers are loaded with the operand of the CALL
instruction. PCH<6:3> is loaded with PCLATH<6:3>.
The CALLW instruction enables computed calls by com-
bining PCLATH and W to form the destination address.
A computed CALLW is accomplished by loading the W
register with the desired address and executing CALLW.
The PCL register is loaded with the value of W and
PCH is loaded with PCLATH.
3.5.4 BRANCHING
The branching instructions add an offset to the PC.
This allows relocatable code and code that crosses
page boundaries. There are two forms of branching,
BRW and BRA. The PC will have incremented to fetch
the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
crossed.
If using BRW, load the W register with the desired
unsigned address and execute BRW. The entire PC will
be loaded with the address PC + 1 + W.
If using BRA, the entire PC will be loaded with PC + 1 +,
the signed value of the operand of the BRA instruction.
PCLPCH 0
14
PC
06 7
ALU Result
8
PCLATH
PCLPCH 0
14
PC
06 4
OPCODE <10:0>
11
PCLATH
PCLPCH 0
14
PC
06 7
W
8
PCLATH
Instruction with
PCL as
Destination
GOTO, CALL
CALLW
PCL
PCH 0
14
PC
PC + W
15
BRW
PCLPCH 0
14
PC
PC + OPCODE <8:0>
15
BRA
PIC16(L)F1777/8/9
DS40001819B-page 88 2015-2016 Microchip Technology Inc.
3.6 Stack
All devices have a 16-level x 15-bit wide hardware
stack (refer to Figures 3-1 and 3-2). The stack space is
not part of either program or data space. The PC is
PUSHed onto the stack when CALL or CALLW instruc-
tions are executed or an interrupt causes a branch. The
stack is POPed in the event of a RETURN, RETLW or a
RETFIE instruction execution. PCLATH is not affected
by a PUSH or POP operation.
The stack operates as a circular buffer if the STVREN
bit is programmed to ‘0‘ (Configuration Words). This
means that after the stack has been PUSHed sixteen
times, the seventeenth PUSH overwrites the value that
was stored from the first PUSH. The eighteenth PUSH
overwrites the second PUSH (and so on). The
STKOVF and STKUNF flag bits will be set on an Over-
flow/Underflow, regardless of whether the Reset is
enabled.
3.6.1 ACCESSING THE STACK
The stack is available through the TOSH, TOSL and
STKPTR registers. STKPTR is the current value of the
Stack Pointer. The TOSH:TOSL register pair points to
the TOP of the stack. Both registers are read/writable.
TOS is split into TOSH and TOSL due to the 15-bit size
of the PC. To access the stack, adjust the value of
STKPTR, which will position TOSH:TOSL, then
read/write to TOSH:TOSL. STKPTR is five bits to allow
detection of overflow and underflow.
During normal program operation, CALL, CALLW and
Interrupts will increment STKPTR while RETLW,
RETURN, and RETFIE will decrement STKPTR. At any
time, STKPTR can be inspected to see how much
stack is left. The STKPTR always points at the currently
used place on the stack. Therefore, a CALL or CALLW
will increment the STKPTR and then write the PC, and
a return will unload the PC and then decrement the
STKPTR.
Reference Figure 3-5 through Figure 3-8 for examples
of accessing the stack.
FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1
Note: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL,
CALLW, RETURN, RETLW and RETFIE
instructions or the vectoring to an interrupt
address.
Note: Care should be taken when modifying the
STKPTR while interrupts are enabled.
STKPTR = 0x1F Stack Reset Disabled
(STVREN = 0)
Stack Reset Enabled
(STVREN = 1)
Initial Stack Configuration:
After Reset, the stack is empty. The
empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
Overflow/Underflow Reset is enabled, the
TOSH/TOSL register will return ‘0’.Ifthe
Stack Overflow/Underflow Reset is
disabled, the TOSH/TOSL register will
return the contents of stack address
0x0F.
0x0000 STKPTR = 0x1F
TOSH:TOSL 0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x04
0x05
0x03
0x02
0x01
0x00
0x1F
TOSH:TOSL
Rev. 10-000043A
7/30/2013
2015-2016 Microchip Technology Inc. DS40001819B-page 89
PIC16(L)F1777/8/9
FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2
FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3
STKPTR = 0x00
Return Address
This figure shows the stack configuration
after the first CALL or a single interrupt.
If a RETURN instruction is executed, the
return address will be placed in the
Program Counter and the Stack Pointer
decremented to the empty state (0x1F).
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x04
0x05
0x03
0x02
0x01
0x00
TOSH:TOSL
Rev. 10-000043B
7/30/2013
STKPTR = 0x06
After seven CALLsorsixCALLs and an
interrupt, the stack looks like the figure on
the left. A series of RETURN instructions will
repeatedly place the return addresses into
the Program Counter and pop the stack.
Return Address
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x04
0x05
0x03
0x02
0x01
0x00
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
TOSH:TOSL
Rev. 10-000043C
7/30/2013
PIC16(L)F1777/8/9
DS40001819B-page 90 2015-2016 Microchip Technology Inc.
FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4
3.6.2 OVERFLOW/UNDERFLOW RESET
If the STVREN bit in Configuration Words is
programmed to ‘1’, the device will be reset if the stack
is PUSHed beyond the sixteenth level or POPed
beyond the first level, setting the appropriate bits
(STKOVF or STKUNF, respectively) in the PCON
register.
3.7 Indirect Addressing
The INDFn registers are not physical registers. Any
instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will
return ‘0’ and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair FSRnH and FSRnL.
The FSR registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into three memory regions:
• Traditional Data Memory
• Linear Data Memory
• Program Flash Memory
STKPTR = 0x10
When the stack is full, the next CALL or
an interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00 so
the stack will wrap and overwrite the
return address at 0x00. If the Stack
Overflow/Underflow Reset is enabled, a
Reset will occur and location 0x00 will
not be overwritten.
Return Address0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x04
0x05
0x03
0x02
0x01
0x00
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
TOSH:TOSL
Rev. 10-000043D
7/30/2013
2015-2016 Microchip Technology Inc. DS40001819B-page 91
PIC16(L)F1777/8/9
FIGURE 3-9: INDIRECT ADDRESSING
0x0000
0x0FFF
0x0000
0x7FFF0xFFFF
0x0000
0x0FFF
0x1000
0x1FFF
0x2000
0x29AF
0x29B0
0x7FFF
0x8000
Reserved
Reserved
Traditional
Data Memory
Linear
Data Memory
Program
Flash Memory
FSR
Address
Range
Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.
Rev. 10-000044A
7/30/2013
PIC16(L)F1777/8/9
DS40001819B-page 92 2015-2016 Microchip Technology Inc.
3.7.1 TRADITIONAL DATA MEMORY
The traditional data memory is a region from FSR
address 0x000 to FSR address 0xFFF. The addresses
correspond to the absolute addresses of all SFR, GPR
and common registers.
FIGURE 3-10: TRAD ITIO NAL DATA MEMORY MAP
Direct Addressing
40BSR 60
From Opcode
0
07FSRxH
000
07FSRxL
Indirect Addressing
00000 00001 00010 11111
Bank Select Location Select
0x00
0x7F
Bank Select Location Select
Bank 0 Bank 1 Bank 2 Bank 31
Rev. 10-000056A
7/31/2013
2015-2016 Microchip Technology Inc. DS40001819B-page 93
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3.7.2 LINEAR DATA MEMORY
The linear data memory is the region from FSR
address 0x2000 to FSR address 0x29AF. This region is
a virtual region that points back to the 80-byte blocks of
GPR memory in all the banks.
Unimplemented memory reads as 0x00. Use of the
linear data memory region allows buffers to be larger
than 80 bytes because incrementing the FSR beyond
one bank will go directly to the GPR memory of the next
bank.
The 16 bytes of common memory are not included in
the linear data memory region.
FIGURE 3-11: LINEAR DATA MEMORY
MAP
3.7.3 PROGRAM FLASH MEMORY
To make constant data access easier, the entire
program Flash memory is mapped to the upper half of
the FSR address space. When the MSB of FSRnH is
set, the lower 15 bits are the address in program
memory which will be accessed through INDF. Only the
lower eight bits of each memory location is accessible
via INDF. Writing to the program Flash memory cannot
be accomplished via the FSR/INDF interface. All
instructions that access program Flash memory via the
FSR/INDF interface will require one additional
instruction cycle to complete.
FIGURE 3-12: PROGRAM FLASH
MEMORY MAP
0x020
Bank 0
0x06F
0x0A0
Bank 1
0x0EF
0x120
Bank 2
0x16F
0xF20
Bank 30
0xF6F
001
0077FSRnH FSRnL
Location Select 0x2000
0x29AF
Rev. 10-000057A
7/31/2013
0x0000
Program
Flash
Memory
(low 8 bits)
0x7FFF
1
0077FSRnH FSRnL
Location Select 0x8000
0xFFFF
Rev. 10-000058A
7/31/2013
PIC16(L)F1777/8/9
DS40001819B-page 94 2015-2016 Microchip Technology Inc.
4.0 DEVICE CONFIGURATION
Device configuration consists of Configuration Words,
Code Protection and Device ID.
4.1 Configuration Words
There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1 at
8007h and Configuration Word 2 at 8008h.
Note: The DEBUG bit in Configuration Words is
managed automatically by device
development tools including debuggers
and programmers. For normal device
operation, this bit should be maintained as
a ‘1’.
2015-2016 Microchip Technology Inc. DS40001819B-page 95
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4.2 Register Definitions: Configuration Words
REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1
FCMEN IESO CLKOUTEN BOREN<1:0> —
bit 13 bit 8
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
CP(1) MCLRE PWRTE WDTE<1:0> FOSC<2:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase
bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit
1 = ON Fail-Safe Clock Monitor and internal/external switchover are both enabled
0 = OFF Fail-Safe Clock Monitor is disabled
bit 12 IESO: Internal External Switchover bit
1 = ON Internal/External Switchover mode is enabled
0 = OFF Internal/External Switchover mode is disabled
bit 11 CLKOUTEN: Clock Out Enable bit
If FOSC Configuration bits are set to LP, XT, HS modes:
This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin.
All other FOSC modes:
1 = ON CLKOUT function is disabled. I/O function on the CLKOUT pin.
0 = OFF CLKOUT function is enabled on the CLKOUT pin.
bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits
11 = ON BOR enabled
10 = NSLEEP BOR enabled during operation and disabled in Sleep
01 = SBODEN BOR controlled by SBOREN bit of the BORCON register
00 = OFF BOR disabled
bit 8 Unimplemented: Read as ‘1’
bit 7 CP: Code Protection bit(1)
1 = OFF Program memory code protection is disabled
0 = ON Program memory code protection is enabled
bit 6 MCLRE: MCLR/VPP Pin Function Select bit
If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1 = ON MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0 = OFF MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under
control of WPUA3 bit.
bit 5 PWRTE: Power-up Timer Enable bit
1 = OFF PWRT disabled
0 = ON PWRT enabled
bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit
11 = ON WDT enabled
10 = NSLEEP WDT enabled while running and disabled in Sleep
01 = SWDTEN WDT controlled by the SWDTEN bit in the WDTCON register
00 = OFF WDT disabled
PIC16(L)F1777/8/9
DS40001819B-page 96 2015-2016 Microchip Technology Inc.
bit 2-0 FOSC<2:0>: Oscillator Selection bits
111 = ECH External Clock, High-Power mode: CLKIN supplied to OSC1/CLKIN pin
110 = ECM External Clock, Medium Power mode: CLKIN supplied to OSC1/CLKIN pin
101 = ECL External Clock, Low-Power mode: CLKIN supplied to OSC1/CLKIN pin
100 = INTOSC Internal HFINTOSC. I/O function on CLKIN pin
011 = EXTRC External RC circuit connected to CLKIN pin
010 = HS High-speed crystal/resonator connected between OSC1 and OSC2 pins
001 = XT Crystal/resonator connected between OSC1 and OSC2 pins
000 = LP Low-power crystal connected between OSC1 and OSC2 pins
Note 1: The entire Flash program memory will be erased when the code protection is turned off during an erase.
When a Bulk Erase Program Memory command is executed, the entire program Flash memory and
configuration memory will be erased.
REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 (CONTINUED)
2015-2016 Microchip Technology Inc. DS40001819B-page 97
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REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
LVP(1) DEBUG(2) LPBOR BORV(3) STVREN PLLEN
bit 13 bit 8
R/P-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1 R/P-1
ZCD — — — — PPS1WAY WRT<1:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase
bit 13 LVP: Low-Voltage Programming Enable bit(1)
1 = ON Low-voltage programming enabled
0 = OFF High-voltage on MCLR must be used for programming
bit 12 DEBUG: In-Circuit Debugger Mode bit(2)
1 = OFF In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins
0 = ON In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger
bit 11 LPBOR: Low-Power BOR Enable bit
1 = OFF Low-Power Brown-out Reset is disabled
0 = ON Low-Power Brown-out Reset is enabled
bit 10 BORV: Brown-out Reset Voltage Selection bit(3)
1 = LO Brown-out Reset voltage (VBOR), low trip point selected
0 = HI Brown-out Reset voltage (VBOR), high trip point selected
bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit
1 = ON Stack Overflow or Underflow will cause a Reset
0 = OFF Stack Overflow or Underflow will not cause a Reset
bit 8 PLLEN: PLL Enable bit
1 = ON 4xPLL enabled
0 = OFF 4xPLL disabled
bit 7 ZCD: ZCD Enable bit
1 = OFF ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
0 = ON ZCD always enabled
bit 6-3 Unimplemented: Read as ‘1’
bit 2 PPS1WAY: PPSLOCK Bit One-Way Set Enable bit
1 = ON The PPSLOCK bit can only be set once after an unlocking sequence is executed; once PPSLOCK
is set, all future changes to PPS registers are prevented
0 = OFF The PPSLOCK bit can be set and cleared as needed (provided an unlocking sequence is executed)
bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits
4 kW Flash memory (PIC16(L)F1764/8)
11 = OFF Write protection off
10 = BOOT 0000h to 01FFh write protected, 0200h to 0FFFh may be modified by PMCON control
01 = HALF 0000h to 07FFh write protected, 0800h to 0FFFh may be modified by PMCON control
00 = ALL 0000h to 0FFFh write protected, no addresses may be modified by PMCON control
8 kW Flash memory (PIC16(L)F1765/9)
11 = OFF Write protection off
10 = BOOT 0000h to 01FFh write protected, 0200h to 1FFFh may be modified by PMCON control
01 = HALF 0000h to 0FFFh write protected, 1000h to 1FFFh may be modified by PMCON control
00 = ALL 0000h to 1FFFh write protected, no addresses may be modified by PMCON control
Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
2: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers
and programmers. For normal device operation, this bit should be maintained as a ‘1’.
3: See VBOR parameter for specific trip point voltages.
PIC16(L)F1777/8/9
DS40001819B-page 98 2015-2016 Microchip Technology Inc.
4.3 Code Protection
Code protection allows the device to be protected from
unauthorized access. Program memory protection is
controlled independently. Internal access to the
program memory is unaffected by any code protection
setting.
4.3.1 PROGRAM MEMORY PROTECTION
The entire program memory space is protected from
external reads and writes by the CP bit in Configuration
Words. When CP = 0, external reads and writes of
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Writing the
program memory is dependent upon the write
protection setting. See Section 4.4 “Write
Protection” for more information.
4.4 Write Prote c tion
Write protection allows the device to be protected from
unintended self-writes. Applications, such as boot
loader software, can be protected while allowing other
regions of the program memory to be modified.
The WRT<1:0> bits in Configuration Words define the
size of the program memory block that is protected.
4.5 User ID
Four memory locations (8000h-8003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
readable and writable during normal execution. See
Section 10.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations. For more information on
checksum calculation, see the “PIC16(L)F170X
Memory Programming Specification” (DS41683).
2015-2016 Microchip Technology Inc. DS40001819B-page 99
PIC16(L)F1777/8/9
4.6 Device ID and Revision ID
The 14-bit device ID word is located at 8006h and the
14-bit revision ID is located at 8005h. These locations
are read-only and cannot be erased or modified. See
Section 10.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations.
Development tools, such as device programmers and
debuggers, may be used to read the Device ID and
Revision ID.
4.7 Register Defi nitions: Device and Revision
REGISTER 4-3: DEVID: DEVICE ID REGISTER
RRRRRR
DEV<13:8>
bit 13 bit 8
RRRRRRRR
DEV<7:0>
bit 7 bit 0
Legend:
R = Readable bit
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 13-0 DEV<13:0>: Device ID bits
Device DEVID<13:0> Valu es
PIC16F1777 11 0000 1000 1110 (308E)
PIC16F1778 11 0000 1000 1111 (308F)
PIC16F1779 11 0000 1001 0000 (3090)
PIC16LF1777 11 0000 1001 0001 (3091)
PIC16LF1778 11 0000 1001 0010 (3092)
PIC16LF1779 11 0000 1001 0011 (3093)
PIC16(L)F1777/8/9
DS40001819B-page 100 2015-2016 Microchip Technology Inc.
REGISTER 4-4: REVID: REVISION ID REGISTER
RRRRRR
REV<13:8>
bit 13 bit 8
RRRRRRRR
REV<7:0>
bit 7 bit 0
Legend:
R = Readable bit
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 13-0 REV<13:0>: Revision ID bits
2015-2016 Microchip Technology Inc. DS40001819B-page 101
PIC16(L)F1777/8/9
5.0 OSCILLATOR MODULE (WITH
FAIL-SAFE CLOCK MONITOR)
5.1 Overview
The oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applications while maximizing perfor-
mance and minimizing power consumption. Figure 5-1
illustrates a block diagram of the oscillator module.
Clock sources can be supplied from external oscillators,
quartz crystal resonators, ceramic resonators and
Resistor-Capacitor (RC) circuits. In addition, the system
clock source can be supplied from one of two internal
oscillators and PLL circuits, with a choice of speeds
selectable via software. Additional clock features
include:
• Selectable system clock source between external
or internal sources via software.
• Two-Speed Start-up mode, which minimizes
latency between external oscillator start-up and
code execution.
• Fail-Safe Clock Monitor (FSCM) designed to
detect a failure of the external clock source (LP,
XT, HS, ECH, ECM, ECL or EXTRC modes) and
switch automatically to the internal oscillator.
• Oscillator Start-up Timer (OST) ensures stability
of crystal oscillator sources.
The oscillator module can be configured in one of the
following clock modes.
1. ECL – External Clock Low-Power mode
(0 MHz to 0.5 MHz)
2. ECM – External Clock Medium Power mode
(0.5 MHz to 4 MHz)
3. ECH – External Clock High-Power mode
(4 MHz to 32 MHz)
4. LP – 32 kHz Low-Power Crystal mode.
5. XT – Medium Gain Crystal or Ceramic Resonator
Oscillator mode (up to 4 MHz)
6. HS – High Gain Crystal or Ceramic Resonator
mode (4 MHz to 20 MHz)
7. EXTRC – External Resistor-Capacitor
8. INTOSC – Internal oscillator (31 kHz to 32 MHz)
Clock Source modes are selected by the FOSC<2:0>
bits in the Configuration Words. The FOSC bits
determine the type of oscillator that will be used when
the device is first powered.
The ECH, ECM, and ECL clock modes rely on an
external logic level signal as the device clock source.
The LP, XT, and HS clock modes require an external
crystal or resonator to be connected to the device.
Each mode is optimized for a different frequency range.
The EXTRC clock mode requires an external resistor
and capacitor to set the oscillator frequency.
The INTOSC internal oscillator block produces low,
medium, and high-frequency clock sources,
designated LFINTOSC, MFINTOSC and HFINTOSC.
(see Internal Oscillator Block, Figure 5-1). A wide
selection of device clock frequencies may be derived
from these three clock sources.
PIC16(L)F1777/8/9
DS40001819B-page 102 2015-2016 Microchip Technology Inc.
FIGURE 5-1: SI MPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
Secondary
T1OSCEN
Enable
Oscillator
SOSCO
SOSCI
Timer1 Clock Source Option
for other modules
OSC1
OSC2
Sleep
LP, XT, HS, RC, EC
T1OSC
To CPU and
Postscaler
MUX
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
250 kHz
500 kHz
IRCF<3:0>
31 kHz
500 kHz
Source
Internal
Oscillator
Block
WDT, PWRT, Fail-Safe Clock Monitor
16 MHz
INTOSC
(HFINTOSC)
SCS<1:0>
HFPLL
31 kHz (LFINTOSC)
Two-Speed Start-up and other modules
Oscillator
31 kHz
Source
500 kHz
(MFINTOSC)
125 kHz
31.25 kHz
62.5 kHz
Peripherals
Sleep
External
Timer1
4 x PLL
1X
01
00
1
0
0
1
PRIMUX
PLLMUX
0000
1111
Inputs Outputs
SCS FOSC<2:0> PLLE N or
SPLLEN IRCF PRIMUX PLLMUX
=00
=100
0x10
1=1110 1 1
≠1110 1 0
≠100 0x00
1x01
≠00 X X X X X
FOSC
Oscillator
2015-2016 Microchip Technology Inc. DS40001819B-page 103
PIC16(L)F1777/8/9
5.2 Clock Source Types
Clock sources can be classified as external or internal.
External clock sources rely on external circuitry for the
clock source to function. Examples are: oscillator
modules (ECH, ECM, ECL mode), quartz crystal reso-
nators or ceramic resonators (LP, XT and HS modes)
and Resistor-Capacitor (EXTRC) mode circuits.
Internal clock sources are contained within the
oscillator module. The internal oscillator block has two
internal oscillators and a dedicated Phase Lock Loop
(HFPLL) that are used to generate three internal
system clock sources: the 16 MHz High-Frequency
Internal Oscillator (HFINTOSC), 500 kHz (MFINTOSC)
and the 31 kHz Low-Frequency Internal Oscillator
(LFINTOSC).
The system clock can be selected between external or
internal clock sources via the System Clock Select
(SCS) bits in the OSCCON register. See Section 5.3
“Clock Switching” for additional information.
5.2.1 EXTERNAL CLOCK SOURCES
An external clock source can be used as the device
system clock by performing one of the following
actions:
• Program the FOSC<2:0> bits in the Configuration
Words to select an external clock source that will
be used as the default system clock upon a
device Reset.
• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to:
- Secondary oscillator during run-time, or
- An external clock source determined by the
value of the FOSC bits.
See Section 5.3 “Clock Switching” for more informa-
tion.
5.2.1.1 EC Mode
The External Clock (EC) mode allows an externally
generated logic level signal to be the system clock
source. When operating in this mode, an external clock
source is connected to the OSC1 input.
OSC2/CLKOUT is available for general purpose I/O or
CLKOUT. Figure 5-2 shows the pin connections for EC
mode.
EC mode has three power modes to select from through
Configuration Words:
• ECH – High power, 4-32 MHz
• ECM – Medium power, 0.5-4 MHz
• ECL – Low power, 0-0.5 MHz
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC® MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
FIGURE 5-2: EXTERNAL CLOCK (EC)
MODE OPERATION
5.2.1.2 LP, XT, HS Modes
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 5-3). The three modes select
a low, medium or high gain setting of the internal
inverter-amplifier to support various resonator types
and speed.
LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier. LP mode current consumption
is the least of the three modes. This mode is designed to
drive only 32.768 kHz tuning-fork type crystals (watch
crystals).
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
This mode is best suited to drive resonators with a
medium drive level specification.
HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier. HS mode current consumption
is the highest of the three modes. This mode is best
suited for resonators that require a high drive setting.
Figure 5-3 and Figure 5-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.
Clock from
Ext. system
F
OSC
/4 or I/O(1)
OSC1/CLKIN
PIC®MCU
OSC2/CLKOUT
Note 1: Output depends upon the CLKOUTEN bit
of the Configuration Words.
Rev. 10-000045A
7/30/2013
PIC16(L)F1777/8/9
DS40001819B-page 104 2015-2016 Microchip Technology Inc.
FIGURE 5-3: QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
FIGURE 5-4: CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
5.2.1.3 Oscillator Start-up Timer (OST)
If the oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended,
unless either FSCM or Two-Speed Start-Up are
enabled. In this case, code will continue to execute at
the selected INTOSC frequency while the OST is
counting. The OST ensures that the oscillator circuit,
using a quartz crystal resonator or ceramic resonator,
has started and is providing a stable system clock to
the oscillator module.
In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Clock
Start-up mode can be selected (see Section 5.4
“Two-Speed Clock Start-up Mode”).
Note 1: Quartz crystal characteristics vary
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Application Notes:
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
• AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Y our Oscillator Work”
(DS00949)
RS(1)
OSC1/CLKIN
PIC®MCU
OSC2/CLKOUT
Note 1: A series resistor (Rs) may be required for
quartz crystals with low drive level.
2: The value of RFvaries with the Oscillator mode
selected (typically between 2 MΩ and 10 MΩ).
RF(2)
C2
C1 To Internal
Logic
Sleep
Quartz
Crystal
Rev. 10-000059A
7/30/2013
RS(1)
OSC1/CLKIN
PIC®MCU
OSC2/CLKOUT
Note 1: A series resistor (Rs) may be required for
ceramic resonators with low drive level.
2: The value of RFvaries with the Oscillator mode
selected (typically between 2 MΩ and 10 MΩ).
3. An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
RF(2)
C2
C1 To Internal
Logic
Sleep
RP(3)
Ceramic
Resonator
Rev. 10-000060A
7/30/2013
2015-2016 Microchip Technology Inc. DS40001819B-page 105
PIC16(L)F1777/8/9
5.2.1.4 4x PLL
The oscillator module contains a 4x PLL that can be
used with both external and internal clock sources to
provide a system clock source. The input frequency for
the 4x PLL must fall within specifications. See the PLL
Clock Timing Specifications in Table 36-9.
The 4x PLL may be enabled for use by one of two
methods:
1. Program the PLLEN bit in Configuration Words
to a ‘1’.
2. Write the SPLLEN bit in the OSCCON register to
a ‘1’. If the PLLEN bit in Configuration Words is
programmed to a ‘1’, then the value of SPLLEN
is ignored.
5.2.1.5 Secondary Oscillator
The secondary oscillator is a separate crystal oscillator
that is associated with the Timer1 peripheral. It is
optimized for timekeeping operations with a 32.768
kHz crystal connected between the SOSCO and
SOSCI device pins.
The secondary oscillator can be used as an alternate
system clock source and can be selected during
run-time using clock switching. Refer to Section 5.3
“Clock Switching” for more information.
FIGURE 5-5: QUARTZ CRYSTAL
OPERATION
(SECONDARY
OSCILLATOR)
SOSCI
PIC®MCU
SOSCO
C2
C1 To Internal
Logic
32.768 kHz
Quartz
Crystal
Rev. 10-000061A
7/30/2013
Note 1: Quartz crystal characteristics vary
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Application Notes:
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
• AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work”
(DS00949)
• TB097, “Interfacing a Micro Crystal
MS1V -T1K 32.768 kHz Tuning Fork
Crystal to a PIC16F690/SS” (DS91097)
• AN1288, “Design Practices for
Low-Power External Oscillators”
(DS01288)
PIC16(L)F1777/8/9
DS40001819B-page 106 2015-2016 Microchip Technology Inc.
5.2.1.6 External RC Mode
The external Resistor-Capacitor (EXTRC) mode sup-
ports the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required.
The RC circuit connects to OSC1. OSC2/CLKOUT is
available for general purpose I/O or CLKOUT. The
function of the OSC2/CLKOUT pin is determined by the
CLKOUTEN bit in Configuration Words.
Figure 5-6 shows the external RC mode connections.
FIGURE 5-6: EXTERNAL RC MODES
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) values
and the operating temperature. Other factors affecting
the oscillator frequency are:
• threshold voltage variation
• component tolerances
• packaging variations in capacitance
The user also needs to take into account variation due
to tolerance of external RC components used.
5.2.2 INTERNAL CLOCK SOURCES
The device may be configured to use the internal
oscillator block as the system clock by performing one
of the following actions:
• Program the FOSC<2:0> bits in Configuration
Words to select the INTOSC clock source, which
will be used as the default system clock upon a
device Reset.
• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to the internal
oscillator during run-time. See Section 5.3
“Clock Switching” for more information.
In INTOSC mode, OSC1/CLKIN is available for general
purpose I/O. OSC2/CLKOUT is available for general
purpose I/O or CLKOUT.
The function of the OSC2/CLKOUT pin is determined
by the CLKOUTEN bit in Configuration Words.
The internal oscillator block has two independent
oscillators and a dedicated Phase Lock Loop, HFPLL,
that can produce one of three internal system clock
sources.
1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at
16 MHz. The HFINTOSC source is generated
from the 500 kHz MFINTOSC source and the
dedicated Phase Lock Loop, HFPLL. The
frequency of the HFINTOSC can be
user-adjusted via software using the OSCTUNE
register (Register 5-3).
2. The MFINTOSC (Medium-Frequency Internal
Oscillator) is factory calibrated and operates at
500 kHz. The frequency of the MFINTOSC can
be user-adjusted via software using the
OSCTUNE register (Register 5-3).
3. The LFINTOSC (Low-Frequency Internal
Oscillator) is uncalibrated and operates at
31 kHz.
F
OSC
/4
or I/O(1)
PIC® MCU
OSC2/CLKOUT
Note 1: Output depends upon the CLKOUTEN bit of the
Configuration Words.
OSC1/CLKIN Internal
Clock
VSS
CEXT
REXT
Recommended values:10 k REXT 100 k, <3V
3 k REXT 100 k, 3-5V
CEXT > 20 pF, 2-5V
Rev. 10-000062A
7/31/2013
V
DD
2015-2016 Microchip Technology Inc. DS40001819B-page 107
PIC16(L)F1777/8/9
5.2.2.1 HFINTOSC
The High-Frequency Internal Oscillator (HFINTOSC) is
a factory calibrated 16 MHz internal clock source. The
frequency of the HFINTOSC can be altered via
software using the OSCTUNE register (Register 5-3).
The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). One of multiple
frequencies derived from the HFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section 5.2.2.7 “Internal
Oscillator Clock Switch Timing” for more information.
The HFINTOSC is enabled by:
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and
•FOSC<2:0> = 100, or
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’.
A fast start-up oscillator allows internal circuits to power
up and stabilize before switching to HFINTOSC.
The High-Frequency Internal Oscillator Ready bit
(HFIOFR) of the OSCSTAT register indicates when the
HFINTOSC is running.
The High-Frequency Internal Oscillator Status Locked
bit (HFIOFL) of the OSCSTAT register indicates when
the HFINTOSC is running within 2% of its final value.
The High-Frequency Internal Oscillator Stable bit
(HFIOFS) of the OSCSTAT register indicates when the
HFINTOSC is running within 0.5% of its final value.
5.2.2.2 MFINTOSC
The Medium-Frequency Internal Oscillator
(MFINTOSC) is a factory calibrated 500 kHz internal
clock source. The frequency of the MFINTOSC can be
altered via software using the OSCTUNE register
(Register 5-3).
The output of the MFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). One of nine
frequencies derived from the MFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section 5.2.2.7 “Internal
Oscillator Clock Switch Timing” for more information.
The MFINTOSC is enabled by:
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and
•FOSC<2:0> = 100, or
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’.
The Medium-Frequency Internal Oscillator Ready bit
(MFIOFR) of the OSCSTAT register indicates when the
MFINTOSC is running.
5.2.2.3 Internal Oscillator Frequency
Adjustment
The 500 kHz internal oscillator is factory calibrated.
This internal oscillator can be adjusted in software by
writing to the OSCTUNE register (Register 5-3). Since
the HFINTOSC and MFINTOSC clock sources are
derived from the 500 kHz internal oscillator, a change
in the OSCTUNE register value will apply to both.
The default value of the OSCTUNE register is ‘0’. The
value is a 6-bit two’s complement number. A value of
1Fh will provide an adjustment to the maximum
frequency. A value of 20h will provide an adjustment to
the minimum frequency.
When the OSCTUNE register is modified, the oscillator
frequency will begin shifting to the new frequency. Code
execution continues during this shift. There is no
indication that the shift has occurred.
OSCTUNE does not affect the LFINTOSC frequency.
Operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock
Monitor (FSCM) and peripherals, are not affected by the
change in frequency.
5.2.2.4 LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is
an uncalibrated 31 kHz internal clock source.
The output of the LFINTOSC connects to a multiplexer
(see Figure 5-1). Select 31 kHz, via software, using the
IRCF<3:0> bits of the OSCCON register. See
Section 5.2.2.7 “Internal Oscillator Clock Switch
Timing” for more information. The LFINTOSC is also
the frequency for the Power-up Timer (PWRT),
Watchdog Timer (WDT) and Fail-Safe Clock Monitor
(FSCM).
The LFINTOSC is enabled by selecting 31 kHz
(IRCF<3:0> bits of the OSCCON register = 000) as the
system clock source (SCS bits of the OSCCON
register = 1x), or when any of the following are
enabled:
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired LF frequency, and
•FOSC<2:0> = 100, or
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’.
Peripherals that use the LFINTOSC are:
• Power-up Timer (PWRT)
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor (FSCM)
The Low-Frequency Internal Oscillator Ready bit
(LFIOFR) of the OSCSTAT register indicates when the
LFINTOSC is running.
PIC16(L)F1777/8/9
DS40001819B-page 108 2015-2016 Microchip Technology Inc.
5.2.2.5 Internal Oscillator Frequency
Selection
The system clock speed can be selected via software
using the Internal Oscillator Frequency Select bits
IRCF<3:0> of the OSCCON register.
The postscaled output of the 16 MHz HFINTOSC,
500 kHz MFINTOSC, and 31 kHz LFINTOSC connect
to a multiplexer (see Figure 5-1). The Internal Oscillator
Frequency Select bits IRCF<3:0> of the OSCCON
register select the frequency output of the internal
oscillators. One of the following frequencies can be
selected via software:
- 32 MHz (requires 4x PLL)
-16 MHz
-8 MHz
-4 MHz
-2 MHz
-1 MHz
- 500 kHz (default after Reset)
- 250 kHz
- 125 kHz
- 62.5 kHz
- 31.25 kHz
- 31 kHz (LFINTOSC)
The IRCF<3:0> bits of the OSCCON register allow
duplicate selections for some frequencies. These
duplicate choices can offer system design trade-offs.
Lower power consumption can be obtained when
changing oscillator sources for a given frequency.
Faster transition times can be obtained between
frequency changes that use the same oscillator source.
5.2.2.6 32 MHz Internal Oscillator
Frequency Selection
The Internal Oscillator Block can be used with the
4x PLL associated with the External Oscillator Block to
produce a 32 MHz internal system clock source. The
following settings are required to use the 32 MHz
internal clock source:
• The FOSC bits in Configuration Words must be
set to use the INTOSC source as the device
system clock (FOSC<2:0> = 100).
• The SCS bits in the OSCCON register must be
cleared to use the clock determined by
FOSC<2:0> in Configuration Words
(SCS<1:0> = 00).
• The IRCF bits in the OSCCON register must be
set to the 8 MHz HFINTOSC set to use
(IRCF<3:0> = 1110).
• The SPLLEN bit in the OSCCON register must be
set to enable the 4x PLL, or the PLLEN bit of the
Configuration Words must be programmed to a
‘1’.
The 4x PLL is not available for use with the internal
oscillator when the SCS bits of the OSCCON register
are set to ‘1x’. The SCS bits must be set to ‘00’ to use
the 4x PLL with the internal oscillator.
Note: Following any Reset, the IRCF<3:0> bits
of the OSCCON register are set to ‘0111’
and the frequency selection is set to
500 kHz. The user can modify the IRCF
bits to select a different frequency.
Note: When using the PLLEN bit of the
Configuration Words, the 4x PLL cannot
be disabled by software and the SPLLEN
option will not be available.
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5.2.2.7 Internal Oscillator Clock Switch
Timing
When switching between the HFINTOSC, MFINTOSC
and the LFINTOSC, the new oscillator may already be
shut down to save power (see Figure 5-7). If this is the
case, there is a delay after the IRCF<3:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The OSCSTAT register will
reflect the current active status of the HFINTOSC,
MFINTOSC and LFINTOSC oscillators. The sequence
of a frequency selection is as follows:
1. IRCF<3:0> bits of the OSCCON register are
modified.
2. If the new clock is shut down, a clock start-up
delay is started.
3. Clock switch circuitry waits for a falling edge of
the current clock.
4. The current clock is held low and the clock
switch circuitry waits for a rising edge in the new
clock.
5. The new clock is now active.
6. The OSCSTAT register is updated as required.
7. Clock switch is complete.
See Figure 5-7 for more details.
If the internal oscillator speed is switched between two
clocks of the same source, there is no start-up delay
before the new frequency is selected. Clock switching
time delays are shown in Table 5-1.
Start-up delay specifications are located in the
oscillator tables of Section 36.0 “Electrical
Specifications”.
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FIGURE 5-7: INTERNAL OSCILLATOR SWITCH TIMING
HFINTOSC/
LFINTOSC
IRCF <3:0>
System Clock
HFINTOSC/
LFINTOSC
IRCF <3:0>
System Clock
00
00
Start-up Time 2-cycle Sync Running
2-cycle Sync Running
HFINTOSC/ LFINTOSC (FSCM and WDT disabled)
HFINTOSC/ LFINTOSC (Either FSCM or WDT enabled)
LFINTOSC
HFINTOSC/
IRCF <3:0>
System Clock
= 0 0
Start-up Time 2-cycle Sync Running
LFINTOSC HFINTOSC/MFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled
MFINTOSC
MFINTOSC
MFINTOSC
MFINTOSC
MFINTOSC
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5.3 Clock Switching
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bits of the OSCCON
register. The following clock sources can be selected
using the SCS bits:
• Default system oscillator determined by FOSC
bits in Configuration Words
• Timer1 32 kHz crystal oscillator
• Internal Oscillator Block (INTOSC)
5.3.1 SYSTEM CLOCK SELECT (SCS)
BITS
The System Clock Select (SCS) bits of the OSCCON
register select the system clock source that is used for
the CPU and peripherals.
• When the SCS bits of the OSCCON register = 00,
the system clock source is determined by the
value of the FOSC<2:0> bits in the Configuration
Words.
• When the SCS bits of the OSCCON register = 01,
the system clock source is the secondary oscillator.
• When the SCS bits of the OSCCON register = 1x,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0>
bits of the OSCCON register. After a Reset, the
SCS bits of the OSCCON register are always
cleared.
When switching between clock sources, a delay is
required to allow the new clock to stabilize. These
oscillator delays are shown in Table 5-1.
5.3.2 OSCILLATOR START-UP TIMER
STATUS (OSTS) BIT
The Oscillator Start-up Timer Status (OSTS) bit of the
OSCSTAT register indicates whether the system clock
is running from the external clock source, as defined by
the FOSC<2:0> bits in the Configuration Words, or
from the internal clock source. In particular, OSTS
indicates that the Oscillator Start-up Timer (OST) has
timed out for LP, XT or HS modes. The OST does not
reflect the status of the secondary oscillator.
5.3.3 SECONDARY OSCILLATOR
The secondary oscillator is a separate crystal oscillator
associated with the Timer1 peripheral. It is optimized
for timekeeping operations with a 32.768 kHz crystal
connected between the SOSCO and SOSCI device
pins.
The secondary oscillator is enabled using the OSCEN
control bit in the T1CON register. See Section 22.0
“Timer1/3/5 Module with Gate Control” for more
information about the Timer1 peripheral.
5.3.4 SECONDARY OSCILLATOR READY
(SOSCR) BIT
The user must ensure that the secondary oscillator is
ready to be used before it is selected as a system clock
source. The Secondary Oscillator Ready (SOSCR) bit
of the OSCSTAT register indicates whether the
secondary oscillator is ready to be used. After the
SOSCR bit is set, the SCS bits can be configured to
select the secondary oscillator.
5.3.5 CLOCK SWITCH BEFORE SLEEP
When a clock switch from an old clock to a new clock is
requested just prior to entering Sleep mode, it is
necessary to confirm that the switch is complete before
the sleep instruction is executed. Failure to do so may
result in an incomplete switch and consequential loss
of the system clock altogether. Clock switching is
confirmed by monitoring the clock status bits in the
OSCSTAT register. Switch confirmation can be
accomplished by sensing that the ready bit for the new
clock is set or the ready bit for the old clock is cleared.
For example, when switching between the internal
oscillator with the PLL and the internal oscillator without
the PLL, monitor the PLLR bit. When PLLR is set, the
switch to 32 MHz operation is complete. Conversely,
when PLLR is cleared the switch from 32 MHz
operation to the selected internal clock is complete.
Note: Any automatic clock switch, which may
occur from Two-Speed Start-up or
Fail-Safe Clock Monitor, does not update
the SCS bits of the OSCCON register. The
user can monitor the OSTS bit of the
OSCSTAT register to determine the current
system clock source.
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5.4 Two-Speed Clock Start-up Mode
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device. This mode
allows the application to wake-up from Sleep, perform
a few instructions using the INTOSC internal oscillator
block as the clock source and go back to Sleep without
waiting for the external oscillator to become stable.
Two-Speed Start-up provides benefits when the oscil-
lator module is configured for LP, XT or HS modes.
The Oscillator Start-up Timer (OST) is enabled for
these modes and must count 1024 oscillations before
the oscillator can be used as the system clock source.
If the oscillator module is configured for any mode
other than LP, XT or HS mode, then Two-Speed
Start-up is disabled. This is because the external clock
oscillator does not require any stabilization time after
POR or an exit from Sleep.
If the OST count reaches 1024 before the device
enters Sleep mode, the OSTS bit of the OSCSTAT
register is set and program execution switches to the
external oscillator. However, the system may never
operate from the external oscillator if the time spent
awake is very short.
5.4.1 TWO-SPEED START-UP MODE
CONFIGURATION
Two-Speed Start-up mode is configured by the
following settings:
• IESO (of the Configuration Words) = 1;
Internal/External Switchover bit (Two-Speed
Start-up mode enabled).
• SCS (of the OSCCON register) = 00.
• FOSC<2:0> bits in the Configuration Words
configured for LP, XT or HS mode.
Two-Speed Start-up mode is entered after:
• Power-on Reset (POR) and, if enabled, after
Power-up Timer (PWRT) has expired, or
• Wake-up from Sleep.
TABLE 5-1: OSCILLATOR SWITCHING DELAYS
Note: Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCSTAT register to
remain clear.
Switch From Switch To Frequency Oscillator Delay
Sleep
LFINTOSC(1)
MFINTOSC(1)
HFINTOSC(1)
31 kHz
31.25 kHz-500 kHz
31.25kHz-16MHz
Oscillator Warm-up Delay (TWARM)(2)
Sleep/POR EC, RC(1) DC – 32 MHz 2 cycles
LFINTOSC EC, RC(1) DC – 32 MHz 1 cycle of each
Sleep/POR Secondary Oscillator
LP, XT, HS(1) 32 kHz-20 MHz 1024 Clock Cycles (OST)
Any clock source MFINTOSC(1)
HFINTOSC(1) 31.25 kHz-500 kHz
31.25kHz-16MHz 2s (approx.)
Any clock source LFINTOSC(1) 31 kHz 1 cycle of each
Any clock source Secondary Oscillator 32 kHz 1024 Clock Cycles (OST)
PLL inactive PLL active 16-32 MHz 2 ms (approx.)
Note 1: PLL inactive.
2: See Section 36.0 “Electrical Specifications”.
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5.4.2 TWO-SPEED START-UP
SEQUENCE
1. Wake-up from Power-on Reset or Sleep.
2. Instructions begin execution by the internal
oscillator at the frequency set in the IRCF<3:0>
bits of the OSCCON register.
3. OST enabled to count 1024 clock cycles.
4. OST timed out, wait for falling edge of the
internal oscillator.
5. OSTS is set.
6. System clock held low until the next falling edge
of new clock (LP, XT or HS mode).
7. System clock is switched to external clock
source.
5.4.3 CHECKING TWO-SPEED CLOCK
STATUS
Checking the state of the OSTS bit of the OSCSTAT
register will confirm if the microcontroller is running
from the external clock source, as defined by the
FOSC<2:0> bits in the Configuration Words, or the
internal oscillator.
FIGURE 5-8: TWO-SPEED STA R T-U P
0 1 1022 1023
PC + 1
TOSTT
INTOSC
OSC1
OSC2
Program Counter
System Clock
PC - N PC
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5.5 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue operating should the external oscillator fail.
The FSCM can detect oscillator failure any time after
the Oscillator Start-up Timer (OST) has expired. The
FSCM is enabled by setting the FCMEN bit in the
Configuration Words. The FSCM is applicable to all
external Oscillator modes (LP, XT, HS, EC, Secondary
Oscillator and RC).
FIGURE 5-9: FSCM BLOCK DIAGRAM
5.5.1 FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by
comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 5-9. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire
half-cycle of the sample clock elapses before the
external clock goes low.
5.5.2 FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSFIF of the PIR2 register. Setting this flag will
generate an interrupt if the OSFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation.
The internal clock source chosen by the FSCM is
determined by the IRCF<3:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.
5.5.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe condition is cleared after a Reset,
executing a SLEEP instruction or changing the SCS bits
of the OSCCON register. When the SCS bits are
changed, the OST is restarted. While the OST is
running, the device continues to operate from the
INTOSC selected in OSCCON. When the OST times
out, the Fail-Safe condition is cleared after successfully
switching to the external clock source. The OSFIF bit
should be cleared prior to switching to the external
clock source. If the Fail-Safe condition still exists, the
OSFIF flag will again become set by hardware.
5.5.4 RESET OR WAKE-UP FROM SLEEP
The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. When
the FSCM is enabled, the Two-Speed Start-up is also
enabled. Therefore, the device will always be executing
code while the OST is operating.
External
LFINTOSC ÷ 64
S
R
Q
31 kHz
(~32 s)
488 Hz
(~2 ms)
Clock Monitor
Latch
Clock
Failure
Detected
Oscillator
Clock
Q
Sample Clock
Note: Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
Status bits in the OSCSTAT register to
verify the oscillator start-up and that the
system clock switchover has successfully
completed.
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FIGURE 5-10: FSCM TIMING DIAGRAM
OSCFIF
System
Clock
Output
Sample Clock
Failure
Detected
Oscillator
Failure
Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
(Q)
Te s t Test Test
Clock Monitor Output
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5.6 Register Definitions: Oscillator Control
REGISTER 5-1: OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0
SPLLEN IRCF<3:0> —SCS<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 SPLLEN: Software PLL Enable bit
If PLLEN in Configuration Words = 1:
SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements)
If PLLEN in Configuration Words = 0:
1 = 4x PLL Is enabled
0 = 4x PLL is disabled
bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits
1111 = 16 MHz HF
1110 = 8 MHz or 32 MHz HF(2)
1101 =4MHz HF
1100 =2MHz HF
1011 =1MHz HF
1010 = 500 kHz HF(1)
1001 = 250 kHz HF(1)
1000 = 125 kHz HF(1)
0111 = 500 kHz MF (default upon Reset)
0110 = 250 kHz MF
0101 = 125 kHz MF
0100 = 62.5 kHz MF
0011 = 31.25 kHz HF(1)
0010 = 31.25 kHz MF
000x =31kHz LF
bit 2 Unimplemented: Read as ‘0’
bit 1-0 SCS<1:0>: System Clock Select bits
1x = Internal oscillator block
01 = Secondary oscillator
00 = Clock determined by FOSC<2:0> in Configuration Words
Note 1: Duplicate frequency derived from HFINTOSC.
2: 32 MHz when SPLLEN bit is set. Refer to Section 5.2.2.6 “32 MHz Internal Oscillator Frequency
Selection”.
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REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER
R-1/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q
SOSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional
bit 7 SOSCR: Secondary Oscillator Ready bit
If T1OSCEN = 1:
1 = Secondary oscillator is ready
0 = Secondary oscillator is not ready
If T1OSCEN = 0:
1 = Secondary clock source is always ready
bit 6 PLLR 4x PLL Ready bit
1 = 4x PLL is ready
0 = 4x PLL is not ready
bit 5 OSTS: Oscillator Start-up Timer Status bit
1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Words
0 = Running from an internal oscillator (FOSC<2:0> = 100)
bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit
1 = HFINTOSC is ready
0 = HFINTOSC is not ready
bit 3 HFIOFL: High-Frequency Internal Oscillator Locked bit
1 = HFINTOSC is at least 2% accurate
0 = HFINTOSC is not 2% accurate
bit 2 MFIOFR: Medium-Frequency Internal Oscillator Ready bit
1 = MFINTOSC is ready
0 = MFINTOSC is not ready
bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit
1 = LFINTOSC is ready
0 = LFINTOSC is not ready
bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit
1 = HFINTOSC is at least 0.5% accurate
0 = HFINTOSC is not 0.5% accurate
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TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
TABLE 5-3: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES
REGISTER 5-3: OSCTUNE: OSCILLATOR TUNING REGISTER
U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
—— TUN<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 TUN<5:0>: Frequency Tuning bits
100000 = Minimum frequency
•
•
•
111111 =
000000 = Oscillator module is running at the factory-calibrated frequency
000001 =
•
•
•
011110 =
011111 = Maximum frequency
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
OSCCON SPLLEN IRCF<3:0> —SCS<1:0>116
OSCSTAT SOSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 117
OSCTUNE ——TUN<5:0>118
PIR2 OSFIF C2IF C1IF COG1IF BCL1IF C4IF C3IF CCP2IF 140
PIE2 OSFIE C2IE C1IE COG1IE BCL1IE C4IE C3IE CCP2IE 134
T1CON CS<1:0> CKPS<1:0> OSCEN SYNC —ON 283
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register
on Page
CONFIG1 13:8 —— FCMEN IESO CLKOUTEN BOREN<1:0> —95
7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
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6.0 RESETS
There are multiple ways to reset this device:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Low-Power Brown-out Reset (LPBOR)
•MCLR Reset
•WDT Reset
•RESET instruction
• Stack Overflow
• Stack Underflow
• Programming mode exit
To allow VDD to stabilize, an optional Power-up Timer
can be enabled to extend the Reset time after a BOR
or POR event.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 6-1.
FIGURE 6-1: SIMPLI FIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Device
Reset
Power-on
Reset
WDT
Time-out
Brown-out
Reset
LPBOR
Reset
RESET Instruction
MCLRE
Sleep
BOR
Active(1)
PWRTE
LFINTOSC
VDD
ICSP™ Programming Mode Exit
Stack Underflow
Stack Overlfow
VPP/MCLR
RPower-up
Timer
Rev. 10-000006A
8/14/2013
Note 1: See Table 6.2.1 for BOR active conditions.
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6.1 Power-On Reset (POR)
The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising VDD, fast operating speeds or analog
performance may require greater than minimum VDD.
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.
6.1.1 POWER-UP TIMER (PWRT)
The Power-up Timer provides a nominal 64 ms
time-out on POR or Brown-out Reset.
The device is held in Reset as long as PWRT is active.
The PWRT delay allows additional time for the VDD to
rise to an acceptable level. The Power-up Timer is
enabled by clearing the PWRTE bit in Configuration
Words.
The Power-up Timer starts after the release of the POR
and BOR.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
6.2 Brown-Out Reset ( BOR)
The BOR circuit holds the device in Reset when VDD
reaches a selectable minimum level. Between the
POR and BOR, complete voltage range coverage for
execution protection can be implemented.
The Brown-out Reset module has four operating
modes controlled by the BOREN<1:0> bits in Configu-
ration Words. The four operating modes are:
• BOR is always on
• BOR is off when in Sleep
• BOR is controlled by software
• BOR is always off
Refer to Tab le 6 .2 .1 for more information.
The Brown-out Reset voltage level is selectable by
configuring the BORV bit in Configuration Words.
A VDD noise rejection filter prevents the BOR from
triggering on small events. If VDD falls below VBOR for
a duration greater than parameter TBORDC, the device
will reset. See Figure 6-2 for more information.
6.2.1 BOR IS ALWAYS ON
When the BOREN bits of Configuration Words are
programmed to ‘11’, the BOR is always on. The device
start-up will be delayed until the BOR is ready and VDD
is higher than the BOR threshold.
BOR protection is active during Sleep. The BOR does
not delay wake-up from Sleep.
6.2.2 BOR IS OFF IN SLEEP
When the BOREN bits of Configuration Words are
programmed to ‘10’, the BOR is on, except in Sleep.
The device start-up will be delayed until the BOR is
ready and VDD is higher than the BOR threshold.
BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.
6.2.3 BOR CONTROLLED BY SOFTWARE
When the BOREN bits of Configuration Words are
programmed to ‘01’, the BOR is controlled by the
SBOREN bit of the BORCON register. The device
start-up is not delayed by the BOR ready condition or
the VDD level.
BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
BORRDY bit of the BORCON register.
BOR protection is unchanged by Sleep.
TABLE 6-1: BOR OPERATING MODES
BOREN<1:0> SBOREN Device Mode BOR Mode Instruction Execution upon:
Release of POR or Wake-up from Sleep
11 X X Active Waits for BOR ready(1) (BORRDY = 1)
10 X Awake Active Waits for BOR ready (BORRDY = 1)
Sleep Disabled
01 1X Active Waits for BOR ready(1) (BORRDY = 1)
0XDisabled
Begins immediately (BORRDY = x)
00 X XDisabled
Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR
ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR
circuit is forced on by the BOREN<1:0> bits.
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FIGURE 6-2: BROWN-OUT SITUATIONS
6.3 Register De finition s : B OR C o ntrol
REGISTER 6-1: BORCON: BROWN-OUT RESET CONTROL REGISTER
R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u
SBOREN BORFS(1) — — — — — BORRDY
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7 SBOREN: Software Brown-out Reset Enable bit
If BOREN <1:0> in Configuration Words 01:
SBOREN is read/write, but has no effect on the BOR.
If BOREN <1:0> in Configuration Words = 01:
1 =BOR Enabled
0 =BOR Disabled
bit 6 BORFS: Brown-out Reset Fast Start bit(1)
If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off)
BORFS is Read/Write, but has no effect.
If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control):
1 = Band gap is forced on always (covers sleep/wake-up/operating cases)
0 = Band gap operates normally, and may turn off
bit 5-1 Unimplemented: Read as ‘0’
bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit
1 = The Brown-out Reset circuit is active
0 = The Brown-out Reset circuit is inactive
Note 1: BOREN<1:0> bits are located in Configuration Words.
TPWRT(1)
VBOR
VDD
Internal
Reset
VBOR
VDD
Internal
Reset TPWRT(1)
< TPWRT
TPWRT(1)
VBOR
VDD
Internal
Reset
Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.
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6.4 Low-Power Brown-Out Reset
(LPBOR)
The Low-Power Brown-out Reset (LPBOR) is an
essential part of the Reset subsystem. Refer to
Figure 6-1 to see how the BOR interacts with other
modules.
The LPBOR is used to monitor the external VDD pin.
When too low of a voltage is detected, the device is
held in Reset. When this occurs, a register bit (BOR) is
changed to indicate that a BOR Reset has occurred.
The same bit is set for both the BOR and the LPBOR.
Refer to Register 6-2.
6.4.1 ENABLING LPBOR
The LPBOR is controlled by the LPBOR bit of
Configuration Words. When the device is erased, the
LPBOR module defaults to disabled.
6.4.1.1 LPBOR Module Output
The output of the LPBOR module is a signal indicating
whether or not a Reset is to be asserted. This signal is
OR’d together with the Reset signal of the BOR
module to provide the generic BOR signal, which goes
to the PCON register and to the power control block.
6.5 MCLR
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE bit of Configuration Words and the LVP bit of
Configuration Words (Table 6-2).
6.5.1 MCLR ENABLED
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
VDD through an internal weak pull-up.
The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
6.5.2 MCLR DISABLED
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control. See Section 11.1 “PORTA Regis-
ters” for more information.
6.6 Watchdog Timer (WDT) Reset
The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDT instruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 9.0
“Watchdog Timer (WDT)” for more information.
6.7 RESET Instruction
A RESET instruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See Table 6 -4
for default conditions after a RESET instruction has
occurred.
6.8 Stack Overflow/Underflow Reset
The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration
Words. See Section 3.6.2 “Overflow/Underflow
Reset” for more information.
6.9 Programming Mode Exit
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
6.10 Power-Up Timer
The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow VDD to stabilize before allowing the device to start
running.
The Power-up Timer is controlled by the PWRTE bit of
Configuration Words.
6.11 Start-up Sequence
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
1. Power-up Timer runs to completion (if enabled).
2. Oscillator start-up timer runs to completion (if
required for oscillator source).
3. MCLR must be released (if enabled).
The total time-out will vary based on oscillator configu-
ration and Power-up Timer configuration. See
Section 5.0 “Oscillator Module (with Fail-Safe
Clock Monitor)” for more information.
The Power-up Timer and oscillator start-up timer run
independently of MCLR Reset. If MCLR is kept low
long enough, the Power-up Timer and oscillator
start-up timer will expire. Upon bringing MCLR high, the
device will begin execution after 10 FOSC cycles (see
Figure 6-3). This is useful for testing purposes or to
synchronize more than one device operating in parallel.
TABLE 6-2: MCLR CONFIGURATION
MCLRE LVP MCLR
x1Enabled
10Enabled
00Disabled
Note: A Reset does not drive the MCLR pin low.
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FIGURE 6-3: RESET START-UP SEQUENCE
TOST
TMCLR
TPWRT
VDD
Internal POR
Power-up Timer
MCLR
Internal RESET
Oscillator Modes
Oscillator Start-up Timer
Oscillator
FOSC
Internal Oscillator
Oscillator
FOSC
External Clock (EC)
CLKIN
FOSC
External Cryst al
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6.12 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON registers are updated to indicate the cause of
the Reset. Tab le 6- 3 and Tab le 6 -4 show the Reset
conditions of these registers.
TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE
TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS
STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition
0 0 1 1 10 x11Power-on Reset
0 0 1 1 10 x0xIllegal, TO is set on POR
0 0 1 1 10 xx0Illegal, PD is set on POR
0 0 u 1 1u 011Brown-out Reset
u u 0 u uu u0uWDT Reset
u u u u uu u00WDT Wake-up from Sleep
u u u u uu u10Interrupt Wake-up from Sleep
u u u 0 uu uuuMCLR Reset during normal operation
u u u 0 uu u10MCLR Reset during Sleep
u u u u 0 u u u u RESET Instruction Executed
1 u u u uu uuuStack Overflow Reset (STVREN = 1)
u 1 u u uu uuuStack Underflow Reset (STVREN = 1)
Condition Program
Counter STATUS
Register PCON
Register
Power-on Reset 0000h ---1 1000 00-- 110x
MCLR Reset during normal operation 0000h ---u uuuu uu-- 0uuu
MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu
WDT Reset 0000h ---0 uuuu uu-- uuuu
WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu
Brown-out Reset 0000h ---1 1uuu 00-- 11u0
Interrupt Wake-up from Sleep PC + 1(1) ---1 0uuu uu-- uuuu
RESET Instruction Executed 0000h ---u uuuu uu-- u0uu
Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu
Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
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6.13 Power Control (PCON) Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Reset Instruction Reset (RI)
•MCLR Reset (RMCLR)
• Watchdog Timer Reset (RWDT)
• Stack Underflow Reset (STKUNF)
• Stack Overflow Reset (STKOVF)
The PCON register bits are shown in Register 6-2.
6.14 Register Definitions: Power Control
REGISTER 6-2: PCON: POWER CONTROL REGISTER
R/W/HS-0/q R/W/HS-0/q U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u
STKOVF STKUNF —RWDT RMCLR RI POR BOR
bit 7 bit 0
Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7 STKOVF: Stack Overflow Flag bit
1 = A Stack Overflow occurred
0 = A Stack Overflow has not occurred or cleared by firmware
bit 6 STKUNF: Stack Underflow Flag bit
1 = A Stack Underflow occurred
0 = A Stack Underflow has not occurred or cleared by firmware
bit 5 Unimplemented: Read as ‘0’
bit 4 RWDT: Watchdog Timer Reset Flag bit
1 = A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware
0 = A Watchdog Timer Reset has occurred (cleared by hardware)
bit 3 RMCLR: MCLR Reset Flag bit
1 = A MCLR Reset has not occurred or set to ‘1’ by firmware
0 = A MCLR Reset has occurred (cleared by hardware)
bit 2 RI: RESET Instruction Flag bit
1 = A RESET instruction has not been executed or set to ‘1’ by firmware
0 = A RESET instruction has been executed (cleared by hardware)
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
occurs)
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TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
BORCON SBOREN BORFS ————— BORRDY 121
PCON STKOVF STKUNF —RWDTRMCLR RI POR BOR 125
STATUS — — —TOPD ZDC C40
WDTCON —— WDTPS<4:0> SWDTEN 154
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.
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7.0 INTERRUPTS
The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.
This chapter contains the following information for
Interrupts:
• Operation
• Interrupt Latency
• Interrupts During Sleep
•INT Pin
• Automatic Context Saving
Many peripherals produce interrupts. Refer to the
corresponding chapters for details.
A block diagram of the interrupt logic is shown in
Figure 7-1.
FIGURE 7-1: INTERRUPT LOGIC
TMR0IF
TMR0IE
INTF
INTE
IOCIF
IOCIE Interrupt
to CPU
Wake-up
(If in Sleep mode)
GIE
(TMR1IF) PIR1<0>
PIRn<7>
PEIE
(TMR1IE) PIE1<0>
Peripheral Interrupts
PIEn<7>
Rev. 10-000010A
1/13/2014
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7.1 Operation
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
• GIE bit of the INTCON register
• Interrupt Enable bit(s) for the specific interrupt
event(s)
• PEIE bit of the INTCON register (if the Interrupt
Enable bit of the interrupt event is contained in the
PIE1 or PIE2 registers)
The INTCON, PIR1 and PIR2 registers record individ-
ual interrupts via interrupt flag bits. Interrupt flag bits will
be set, regardless of the status of the GIE, PEIE and
individual interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
stack
• Critical registers are automatically saved to the
shadow registers (See “Sec tion 7.5 “Auto mati c
Context Savi ng”)
• PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
7.2 Interrupt Latency
Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is three or four instruction cycles. For
asynchronous interrupts, the latency is three to five
instruction cycles, depending on when the interrupt
occurs. See Figure 7-2 and Figure 7-3 for more details.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
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FIGURE 7-2: INTERRUPT LATENCY
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKR
PC 0004h 0005h
PC
Inst(0004h)NOP
GIE
Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4
1 Cycle Instruction at PC
PC
Inst(0004h)NOP
2 Cycle Instruction at PC
FSR ADDR PC+1 PC+2 0004h 0005h
PC
Inst(0004h)NOP
GIE
PCPC-1
3 Cycle Instruction at PC
Execute
Interrupt
Inst(PC)
Interrupt Sampled
during Q1
Inst(PC)
PC-1 PC+1
NOP
PC New PC/
PC+1 0005hPC-1 PC+1/FSR
ADDR 0004h
NOP
Interrupt
GIE
Interrupt
INST(PC) NOPNOP
FSR ADDR PC+1 PC+2 0004h 0005h
PC
Inst(0004h)NOP
GIE
PCPC-1
3 Cycle Instruction at PC
Interrupt
INST(PC) NOPNOP NOP
Inst(0005h)
Execute
Execute
Execute
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FIGURE 7-3: INT PIN INTERRUPT TIMING
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
OSC1
CLKOUT
INT pin
INTF
GIE
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Interrupt Latency
PC PC + 1 PC + 1 0004h 0005h
Inst (0004h) Inst (0005h)
Forced NOP
Inst (PC) Inst (PC + 1)
Inst (PC – 1) Inst (0004h)
Forced NOP
Inst (PC)
—
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT not available in all oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 36.0 “Electrical Specifications””.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
(1) (2)
(3) (4)
(5)
(1)
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7.3 Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to Section 8.0
“Power-Down Mode (Sleep)” for more details.
7.4 INT Pin
The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION_REG register determines on
which edge the interrupt will occur. When the INTEDG
bit is set, the rising edge will cause the interrupt. When
the INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.
7.5 Automatic Context Saving
Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the shadow registers:
• W register
• STATUS register (except for TO and PD)
• BSR register
• FSR registers
• PCLATH register
Upon exiting the Interrupt Service Routine, these regis-
ters are automatically restored. Any modifications to
these registers during the ISR will be lost. If modifica-
tions to any of these registers are desired, the corre-
sponding shadow register should be modified and the
value will be restored when exiting the ISR. The
shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s
application, other registers may also need to be saved.
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7.6 Regist er D e finiti o ns: Inte rru pt C on t rol
REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0
GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all active interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all active peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4 INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
bit 3 IOCIE: Interrupt-on-Change Enable bit
1 = Enables the interrupt-on-change
0 = Disables the interrupt-on-change
bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed
0 = TMR0 register did not overflow
bit 1 INTF: INT External Interrupt Flag bit
1 = The INT external interrupt occurred
0 = The INT external interrupt did not occur
bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit(1)
1 = When at least one of the interrupt-on-change pins changed state
0 = None of the interrupt-on-change pins have changed state
Note 1: The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCxF registers
have been cleared by software.
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
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REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit
1 = Enables the Timer1 gate acquisition interrupt
0 = Disables the Timer1 gate acquisition interrupt
bit 6 ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5 RCIE: EUSART Receive Interrupt Enable bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
bit 4 TXIE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
bit 3 SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to T2PR Match Interrupt Enable bit
1 = Enables the Timer2 to T2PR match interrupt
0 = Disables the Timer2 to T2PR match interrupt
bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
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REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
OSFIE C2IE C1IE COG1IE BCL1IE C4IE C3IE CCP2IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables the Oscillator Fail interrupt
0 = Disables the Oscillator Fail interrupt
bit 6 C2IE: Comparator C2 Interrupt Enable bit
1 = Enables the Comparator C2 interrupt
0 = Disables the Comparator C2 interrupt
bit 5 C1IE: Comparator C1 Interrupt Enable bit
1 = Enables the Comparator C1 interrupt
0 = Disables the Comparator C1 interrupt
bit 4 COG1IE: COG1 Auto-Shutdown Interrupt Enable bit
1 = COG1 interrupt enabled
0 = COG1 interrupt disabled
bit 3 BCL1IE: MSSP Bus Collision Interrupt Enable bit
1 = Enables the MSSP Bus Collision interrupt
0 = Disables the MSSP Bus Collision interrupt
bit 2 C4IE: TMR6 to T6PR Match Interrupt Enable bit
1 = Enables the Comparator C4 interrupt
0 = Disables the Comparator C4 interrupt
bit 1 C3IE: TMR4 to T4PR Match Interrupt Enable bit
1 = Enables the Comparator C3 interrupt
0 = Disables the Comparator C3 interrupt
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
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REGISTER 7-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
—— COG2IE ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 Unimplemented: Read as ‘0’
bit 5 COG2IE: COG2 Auto-Shutdown Interrupt Enable bit
1 = COG2 interrupt enabled
0 = COG2 interrupt disabled
bit 4 ZCDIE: Zero-Cross Detection Interrupt Enable bit
1 = ZCD interrupt enabled
0 = ZCD interrupt disabled
bit 3 CLC4IE: CLC4 Interrupt Enable bit
1 = CLC4 interrupt enabled
0 = CLC4 interrupt disabled
bit 2 CLC3IE: CLC3 Interrupt Enable bit
1 = CLC3 interrupt enabled
0 = CLC3 interrupt disabled
bit 1 CLC2IE: CLC2 Interrupt Enable bit
1 = CLC2 interrupt enabled
0 = CLC2 interrupt disabled
bit 0 CLC1IE: CLC1 Interrupt Enable bit
1 = CLC1 interrupt enabled
0 = CLC1 interrupt disabled
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
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REGISTER 7-5: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— TMR8IE TMR5GIE TMR5IE TMR3GIE TMR3IE TMR6IE TRM4IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 Unimplemented: Read as ‘0’
bit 6 TMR8IE: TMR8 to T8PR Match Interrupt Enable bit
1 = Enables the Timer8 to T8PR match interrupt
0 = Disables the Timer8 to T8PR match interrupt
bit 5 TMR5GIE: Timer5 Gate Interrupt Enable bit
1 = Enables the Timer5 gate acquisition interrupt
0 = Disables the Timer5 gate acquisition interrupt
bit 4 TMR5IE: TMR5 to Overflow Interrupt Enable bit
1 = Enables the Timer5 to T5PR match interrupt
0 = Disables the Timer5 to T5PR match interrupt
bit 3 TMR3GIE: Timer3 Gate Interrupt Enable bit
1 = Enables the Timer3 gate acquisition interrupt
0 = Disables the Timer3 gate acquisition interrupt
bit 2 TMR3IE: TMR3 to Overflow Interrupt Enable bit
1 = Enables the Timer3 to T3PR match interrupt
0 = Disables the Timer3 to T3PR match interrupt
bit 1 TMR6IE: TMR6 to T6PR Match Interrupt Enable bit
1 = Enables the Timer6 to T6PR match interrupt
0 = Disables the Timer6 to T6PR match interrupt
bit 0 TMR4IE: TMR4 to T4PR Match Interrupt Enable bit
1 = Enables the Timer4 to T4PR match interrupt
0 = Disables the Timer4 to T4PR match interrupt
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REGISTER 7-6: PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
CCP8IE(1) CCP7IE COG4IE COG3IE C8IE(1) C7IE(1) C6IE C5IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 CCP8IE: CCP8 Interrupt Enable bit(1)
1 = Enables the CCP8 interrupt
0 = Disables the CCP8 interrupt
bit 6 CCP7IE: CCP7 Interrupt Enable bit
1 = Enables the CCP7 interrupt
0 = Disables the CCP7 interrupt
bit 5 COG4IE: COG4 Auto-Shutdown Interrupt Enable bit
1 = COG4 interrupt enabled
0 = COG4 interrupt disabled
bit 4 COG3IE: COG3 Auto-Shutdown Interrupt Enable bit
1 = COG3 interrupt enabled
0 = COG3 interrupt disabled
bit 3 C8IE: Comparator C8 Interrupt Enable bit(1)
1 = Enables the Comparator C8 interrupt
0 = Disables the Comparator C8 interrupt
bit 2 C7IE: Comparator C7 Interrupt Enable bit(1)
1 = Enables the Comparator C7 interrupt
0 = Disables the Comparator C7 interrupt
bit 1 C6IE: Comparator C6 Interrupt Enable bit
1 = Enables the Comparator C6 interrupt
0 = Disables the Comparator C6 interrupt
bit 0 C5IE: Comparator C5 Interrupt Enable bit
1 = Enables the Comparator C5 interrupt
0 = Disables the Comparator C5 interrupt
Note 1: PIC16(L)F1777/9 only.
PIC16(L)F1777/8/9
DS40001819B-page 138 2015-2016 Microchip Technology Inc.
REGISTER 7-7: PIE6: PERIPHERAL INTERRUPT ENABLE REGISTER 6
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — —PWM12IE
(1) PWM11IE PWM6IE PWM5IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 Unimplemented: Read as ‘0’
bit 3 PWM12IE: PWM12 Interrupt Enable bit(1)
1 = PWM12 interrupt enabled
0 = PWM12 interrupt disabled
bit 2 PWM11IE: PWM11 Interrupt Enable bit
1 = PWM11 interrupt enabled
0 = PWM11 interrupt disabled
bit 1 PWM6IE: PWM6 Interrupt Enable bit
1 = PWM6 interrupt enabled
0 = PWM6 interrupt disabled
bit 0 PWM5IE: PWM5 Interrupt Enable bit
1 = PWM5 interrupt enabled
0 = PWM5 interrupt disabled
Note 1: PIC16(L)F1777/9 only.
2015-2016 Microchip Technology Inc. DS40001819B-page 139
PIC16(L)F1777/8/9
REGISTER 7-8: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 6 ADIF: Analog-to-Digital Converter (ADC) Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 5 RCIF: EUSART Receive Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4 TXIF: EUSART Transmit Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 3 SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 2 CCP1IF: CCP1 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 1 TMR2IF: Timer2 to T2PR Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
PIC16(L)F1777/8/9
DS40001819B-page 140 2015-2016 Microchip Technology Inc.
REGISTER 7-9: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
OSFIF C2IF C1IF COG1IF BCL1IF C4IF C3IF CCP2IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 OSFIF: Oscillator Fail Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 6 C2IF: Comparator C2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 5 C1IF: Comparator C1 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4 COG1IF: COG1 Auto-Shutdown Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 3 BCL1IF: MSSP Bus Collision Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 2 C4IF: Comparator C4 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 1 C3IF: Comparator C3 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0 CCP2IF: CCP2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
2015-2016 Microchip Technology Inc. DS40001819B-page 141
PIC16(L)F1777/8/9
REGISTER 7-10: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
—— COG2IF ZCDIF CLC4IF CLC3IF CLC2IF CLC1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 Unimplemented: Read as ‘0’
bit 5 COG2IF: COG2 Auto-Shutdown Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4 ZCDIF: Zero-Cross Detection Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 3 CLC4IF: CLC4 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 2 CLC3IF: CLC3 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 1 CLC2IF: CLC2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0 CLC1IF: CLC1 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
PIC16(L)F1777/8/9
DS40001819B-page 142 2015-2016 Microchip Technology Inc.
REGISTER 7-11: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— TMR8IF TMR5GIF TMR5IF TMR3GIF TMR3IF TMR6IF TRM4IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 Unimplemented: Read as ‘0’
bit 6 TMR8IF: TMR8 to T8PR Match Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 5 TMR5GIF: Timer5 Gate Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4 TMR5IF: TMR5 to Overflow Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 3 TMR3GIF: Timer3 Gate Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 2 TMR3IF: TMR3 to Overflow Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 1 TMR6IF: TMR6 to T6PR Match Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0 TMR4IF: TMR4 to T4PR Match Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
2015-2016 Microchip Technology Inc. DS40001819B-page 143
PIC16(L)F1777/8/9
REGISTER 7-12: PIR5: PERIPHERAL INTERRUPT REQUEST REGISTER 5
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
CCP8IF(1) CCP7IF COG4IF COG3IF C8IF(1) C7IF(1) C6IF C5IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 CCP8IF: CCP8 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 6 CCP7IF: CCP7 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 5 COG4IF: COG4 Auto-Shutdown Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4 COG3IF: COG3 Auto-Shutdown Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 3 C8IF: Comparator C8 Interrupt Flag bit(1)
1 = Interrupt is pending
0 = Interrupt is not pending
bit 2 C7IF: Comparator C7 Interrupt Flag bit(1)
1 = Interrupt is pending
0 = Interrupt is not pending
bit 1 C6IF: Comparator C6 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0 C5IF: Comparator C5 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Note 1: PIC16(L)F1777/9 only.
PIC16(L)F1777/8/9
DS40001819B-page 144 2015-2016 Microchip Technology Inc.
REGISTER 7-13: PIR6: PERIPHERAL INTERRUPT REQUEST REGISTER 6
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — —PWM12IF
(1) PWM11IF PWM6IF PWM5IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 Unimplemented: Read as ‘0’
bit 3 PWM12IF: PWM12 Interrupt Flag bit(1)
1 = Interrupt is pending
0 = Interrupt is not pending
bit 2 PWM11IF: PWM11 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 1 PWM6IF: PWM6 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0 PWM5IF: PWM5 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Note 1: PIC16(L)F1777/9 only.
2015-2016 Microchip Technology Inc. DS40001819B-page 145
PIC16(L)F1777/8/9
TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 274
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133
PIE2 OSFIE C2IE C1IE COG1IE BCL1IE C4IE C3IE CCP2IE 134
PIE3 —— COG2IE ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE 135
PIE4 — TMR8IE TMR5GIE TMR5IE TMR3GIE TMR3IE TMR6IE TRM4IE 136
PIE5 CCP8IE(1) CCP7IE COG4IE(1) COG3IE C8IE(1) C7IE(1) C6IE C5IE 137
PIE6 — — — — PWM12IE(1) PWM11IE PWM6IE PWM5IE 138
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139
PIR2 OSFIF C2IF C1IF COG1IF BCL1IF C4IF C3IF CCP2IF 140
PIR3 —— COG2IF ZCDIF CLC4IF CLC3IF CLC2IF CLC1IF 141
PIR4 — TMR8IF TMR5GIF TMR5IF TMR3GIF TMR3IF TMR6IF TRM4IF 142
PIR5 CCP8IF(1) CCP7IF COG4IF(1) COG3IF C8IF(1) C7IF(1) C6IF C5IF 143
PIR6 — — — — PWM12IF(1) PWM11IF PWM6IF PWM5IF 144
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts.
Note 1: PIC16(L)F1777/9 only.
PIC16(L)F1777/8/9
DS40001819B-page 146 2015-2016 Microchip Technology Inc.
8.0 POWER-DOWN MODE (SLEEP)
The Power-Down mode is entered by executing a
SLEEP instruction.
Upon entering Sleep mode, the following conditions
exist:
1. WDT will be cleared but keeps running, if
enabled for operation during Sleep.
2. PD bit of the STATUS register is cleared.
3. TO bit of the STATUS register is set.
4. CPU clock is disabled.
5. 31 kHz LFINTOSC is unaffected and peripherals
that operate from it may continue operation in
Sleep.
6. Timer1 and peripherals that operate from
Timer1 continue operation in Sleep when the
Timer1 clock source selected is:
•LFINTOSC
•T1CKI
• Secondary oscillator
7. ADC is unaffected, if the dedicated FRC
oscillator is selected.
8. I/O ports maintain the status they had before
SLEEP was executed (driving high, low or
high-impedance).
9. Resets other than WDT are not affected by
Sleep mode.
Refer to individual chapters for more details on
peripheral operation during Sleep.
To minimize current consumption, the following
conditions should be considered:
• I/O pins should not be floating
• External circuitry sinking current from I/O pins
• Internal circuitry sourcing current from I/O pins
• Current draw from pins with internal weak pull-ups
• Modules using 31 kHz LFINTOSC
• Modules using secondary oscillator
I/O pins that are high-impedance inputs should be
pulled to VDD or VSS externally to avoid switching
currents caused by floating inputs.
Examples of internal circuitry that might be sourcing
current include modules such as the DAC and FVR
modules. See Section 17.0 “5-Bit Digital-to-Analog
Converter (DAC) Module” and Section 14.0 “Fixed
Voltage Reference (FVR)” for more information on
these modules.
8.1 Wake-up from Sleep
The device can wake-up from Sleep through one of the
following events:
1. External Reset input on MCLR pin, if enabled
2. BOR Reset, if enabled
3. POR Reset
4. Watchdog Timer, if enabled
5. Any external interrupt
6. Interrupts by peripherals capable of running
during Sleep (see individual peripheral for more
information)
The first three events will cause a device Reset. The
last three events are considered a continuation of
program execution. To determine whether a device
Reset or wake-up event occurred, refer to
Section 6.12 “Determining the Cause of a Reset”.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEP instruction, the device will then call the Interrupt
Service Routine. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
2015-2016 Microchip Technology Inc. DS40001819B-page 147
PIC16(L)F1777/8/9
8.1.1 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction
-SLEEP instruction will execute as a NOP
- WDT and WDT prescaler will not be cleared
-TO
bit of the STATUS register will not be set
-PD
bit of the STATUS register will not be
cleared
• If the interrupt occurs during or after the execu-
tion of a SLEEP instruction
-SLEEP instruction will be completely
executed
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
-TO
bit of the STATUS register will be set
-PD bit of the STATUS register will be cleared
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
FIGURE 8-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN(1)
CLKOUT(2)
Interrupt flag
GIE bit
(INTCON reg.)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
PC PC + 1 PC + 2
Inst(PC) = Sleep
Inst(PC - 1)
Inst(PC + 1)
Sleep
Processor in
Sleep
Interrupt Latency(4)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Forced NOP
PC + 2 0004h 0005h
Forced NOP
TOST(3)
PC + 2
Note 1: External clock. High, Medium, Low mode assumed.
2: CLKOUT is shown here for timing reference.
3: TOST = 1024 TOSC. This delay does not apply to EC, RC and INTOSC Oscillator modes or Two-Speed Start-up (see Section 5.4
“Two-Speed Clock Start- up Mode”.
4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
PIC16(L)F1777/8/9
DS40001819B-page 148 2015-2016 Microchip Technology Inc.
8.2 Low-Power Sleep Mode
The PIC16F1773/6 devices contain an internal Low
Dropout (LDO) voltage regulator, which allows the
device I/O pins to operate at voltages up to 5.5V while
the internal device logic operates at a lower voltage.
The LDO and its associated reference circuitry must
remain active when the device is in Sleep mode. The
PIC16F1773/6 allow the user to optimize the operating
current in Sleep, depending on the application
requirements.
A Low-Power Sleep mode can be selected by setting
the VREGPM bit of the VREGCON register. With this
bit set, the LDO and reference circuitry are placed in a
low-power state when the device is in Sleep.
8.2.1 SLEEP CURRENT VS. WAKE-UP
TIME
In the Default Operating mode, the LDO and reference
circuitry remain in the normal configuration while in
Sleep. The device is able to exit Sleep mode quickly
since all circuits remain active. In Low-Power Sleep
mode, when waking up from Sleep, an extra delay time
is required for these circuits to return to the normal
configuration and stabilize.
The Low-Power Sleep mode is beneficial for applica-
tions that stay in Sleep mode for long periods of time.
The Normal mode is beneficial for applications that
need to wake from Sleep quickly and frequently.
8.2.2 PERIPHERAL USAGE IN SLEEP
Some peripherals that can operate in Sleep mode will
not operate properly with the Low-Power Sleep mode
selected. The Low-Power Sleep mode is intended for
use with the following peripherals only:
• Brown-out Reset (BOR)
• Watchdog Timer (WDT)
• External interrupt pin/interrupt-on-change pins
• Timer1 (with external clock source < 100 kHz)
Note: The PIC16LF1777/8/9 do not have a
configurable Low-Power Sleep mode.
PIC16LF1777/8/9 are unregulated devices
and are always in the lowest power state
when in Sleep, with no wake-up time
penalty. These devices have a lower
maximum VDD and I/O voltage than the
PIC16F1777/8/9. See Section 36.0
“Electrical Specifications” for more
information.
2015-2016 Microchip Technology Inc. DS40001819B-page 149
PIC16(L)F1777/8/9
8.3 Register Defi nitions: Voltage Regulator Control
REGISTER 8-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1
— — — — — —VREGPMReserved
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-2 Unimplemented: Read as ‘0’
bit 1 VREGPM: Voltage Regulator Power Mode Selection bit
1 = Low-Power Sleep mode enabled in Sleep(2)
Draws lowest current in Sleep, slower wake-up
0 = Normal Power mode enabled in Sleep(2)
Draws higher current in Sleep, faster wake-up
bit 0 Reserved: Read as ‘1’. Maintain this bit set.
Note 1: PIC16F1777/8/9 only.
2: See Section 36.0 “Electrical Specifications”.
PIC16(L)F1777/8/9
DS40001819B-page 150 2015-2016 Microchip Technology Inc.
TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Registe r
on Page
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132
IOCAP IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 215
IOCAN IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 215
IOCAF IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 215
IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 216
IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 216
IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 216
IOCCP IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 216
IOCCN IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 216
IOCCF IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 216
IOCEP — — — — IOCEP3 — — — 219
IOCEN — — — —IOCEN3— — — 219
IOCEF — — — — IOCEF3 — — — 220
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133
PIE2 OSFIE C2IE C1IE COG1IE BCL1IE C4IE C3IE CCP2IE 134
PIE3 —— COG2IE ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE 135
PIE4 — TMR8IE TMR5GIE TMR5IE TMR3GIE TMR3IE TMR6IE TRM4IE 136
PIE5 CCP8IE(1) CCP7IE COG4IE(1) COG3IE C8IE(1) C7IE(1) C6IE C5IE 137
PIE6 — — — — PWM12IE(1) PWM11IE PWM6IE PWM5IE 138
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139
PIR2 OSFIF C2IF C1IF COG1IF BCL1IF C4IF C3IF CCP2IF 140
PIR3 —— COG2IF ZCDIF CLC4IF CLC3IF CLC2IF CLC1IF 141
PIR4 — TMR8IF TMR5GIF TMR5IF TMR3GIF TMR3IF TMR6IF TRM4IF 142
PIR5 CCP8IF(1) CCP7IF COG4IF(1) COG3IF C8IF(1) C7IF(1) C6IF C5IF 143
PIR6 — — — — PWM12IF(1) PWM11IF PWM6IF PWM5IF 144
STATUS — — —TOPD ZDC C40
VREGCON(1) — — — — — —VREGPM
(2) Reserved 149
WDTCON —— WDTPS<4:0> SWDTEN 154
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode.
Note 1: PIC16(L)F1777/9 only.
2: Unimplemented on PIC16LF1777/8/9.
2015-2016 Microchip Technology Inc. DS40001819B-page 151
PIC16(L)F1777/8/9
9.0 WATCHDOG TIMER (WDT)
The Watchdog Timer is a system timer that generates
a Reset if the firmware does not issue a CLRWDT
instruction within the time-out period. The Watchdog
Timer is typically used to recover the system from
unexpected events.
The WDT has the following features:
• Independent clock source
• Multiple operating modes
- WDT is always on
- WDT is off when in Sleep
- WDT is controlled by software
- WDT is always off
• Configurable time-out period is from 1 ms to 256
seconds (nominal)
• Multiple Reset conditions
• Operation during Sleep
FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM
WDTE<1:0> = 01
SWDTEN
WDTE<1:0> = 11
WDTE<1:0> = 10
23-%it Programmable
Prescaler WDT
LFINTOSC
WDTPS<4:0>
WDT
Time-out
Sleep
Rev. 10-000141A
7/30/2013
PIC16(L)F1777/8/9
DS40001819B-page 152 2015-2016 Microchip Technology Inc.
9.1 Independent Clock Source
The WDT derives its time base from the 31 kHz
LFINTOSC internal oscillator. Time intervals in this
chapter are based on a nominal interval of 1 ms. See
Table 36-8: Oscillator Parameters for the LFINTOSC
specification.
9.2 WDT Operating Modes
The Watchdog Timer module has four operating modes
controlled by the WDTE<1:0> bits in Configuration
Words. See Ta bl e 9- 1.
9.2.1 WDT IS ALWAYS ON
When the WDTE bits of Configuration Words are set to
‘11’, the WDT is always on.
WDT protection is active during Sleep.
9.2.2 WDT IS OFF IN SLEEP
When the WDTE bits of Configuration Words are set to
‘10’, the WDT is on, except in Sleep.
WDT protection is not active during Sleep.
9.2.3 WDT CONTROLLED BY SOFTWARE
When the WDTE bits of Configuration Words are set to
‘01’, the WDT is controlled by the SWDTEN bit of the
WDTCON register.
WDT protection is unchanged by Sleep. See Table 9-1
for more details.
TABLE 9-1: WDT OPERATING MODES
9.3 T ime-Out Period
The WDTPS bits of the WDTCON register set the
time-out period from 1 ms to 256 seconds (nominal).
After a Reset, the default time-out period is two
seconds.
9.4 Clearing the WDT
The WDT is cleared when any of the following
conditions occur:
•Any Reset
•CLRWDT instruction is executed
• Device enters Sleep
• Device wakes up from Sleep
• Oscillator fail
• WDT is disabled
• Oscillator Start-up Timer (OST) is running
See Table 9-2 for more information.
9.5 Operation During Sleep
When the device enters Sleep, the WDT is cleared. If
the WDT is enabled during Sleep, the WDT resumes
counting.
When the device exits Sleep, the WDT is cleared
again. The WDT remains clear until the OST, if
enabled, completes. See Section 5.0 “Oscillator
Module (with Fail-Safe Clock Monitor)” for more
information on the OST.
When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO and PD bits
in the STATUS register are changed to indicate the
event. See STATUS Register (Register 3-1) for more
information.
WDTE<1:0> SWDTEN Device
Mode WDT
Mode
11 X XActive
10 X Awake Active
Sleep Disabled
01 1XActive
0Disabled
00 X XDisabled
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TABLE 9-2: WDT CLEARING CONDITIONS
Conditions WDT
WDTE<1:0> = 00
Cleared
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST
Change INTOSC divider (IRCF bits) Unaffected
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9.6 Register Defi nitions: Watchdog Control
REGISTER 9-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0
—— WDTPS<4:0>(1) SWDTEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 Unimplemented: Read as ‘0’
bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits(1)
Bit Value = Prescale Rate
11111 = Reserved. Results in minimum interval (1:32)
•
•
•
10011 = Reserved. Results in minimum interval (1:32)
10010 = 1:8388608 (223) (Interval 256s nominal)
10001 = 1:4194304 (222) (Interval 128s nominal)
10000 = 1:2097152 (221) (Interval 64s nominal)
01111 = 1:1048576 (220) (Interval 32s nominal)
01110 = 1:524288 (219) (Interval 16s nominal)
01101 = 1:262144 (218) (Interval 8s nominal)
01100 = 1:131072 (217) (Interval 4s nominal)
01011 = 1:65536 (Interval 2s nominal) (Reset value)
01010 = 1:32768 (Interval 1s nominal)
01001 = 1:16384 (Interval 512 ms nominal)
01000 = 1:8192 (Interval 256 ms nominal)
00111 = 1:4096 (Interval 128 ms nominal)
00110 = 1:2048 (Interval 64 ms nominal)
00101 = 1:1024 (Interval 32 ms nominal)
00100 = 1:512 (Interval 16 ms nominal)
00011 = 1:256 (Interval 8 ms nominal)
00010 = 1:128 (Interval 4 ms nominal)
00001 = 1:64 (Interval 2 ms nominal)
00000 = 1:32 (Interval 1 ms nominal)
bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit
If WDTE<1:0> = 1x:
This bit is ignored.
If WDTE<1:0> = 01:
1 = WDT is turned on
0 = WDT is turned off
If WDTE<1:0> = 00:
This bit is ignored.
Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.
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TABLE 9-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
TABLE 9-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
OSCCON SPLLEN IRCF<3:0> —SCS<1:0>
116
STATUS — — —TOPD ZDC C40
WDTCON —— WDTPS<4:0> SWDTEN 154
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
Watchdog Timer.
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register
on Page
CONFIG1 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> —95
7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.
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10.0 FLASH PROGRAM MEMORY
CONTROL
The Flash program memory is readable and writable
during normal operation over the full VDD range.
Program memory is indirectly addressed using Special
Function Registers (SFRs). The SFRs used to access
program memory are:
•PMCON1
•PMCON2
•PMDATL
•PMDATH
• PMADRL
•PMADRH
When accessing the program memory, the
PMDATH:PMDATL register pair forms a 2-byte word
that holds the 14-bit data for read/write, and the
PMADRH:PMADRL register pair forms a 2-byte word
that holds the 15-bit address of the program memory
location being read.
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip charge
pump rated to operate over the operating voltage range
of the device.
The Flash program memory can be protected in two
ways; by code protection (CP bit in Configuration Words)
and write protection (WRT<1:0> bits in Configuration
Words).
Code protection (CP = 0)(1), disables access, reading
and writing, to the Flash program memory via external
device programmers. Code protection does not affect
the self-write and erase functionality. Code protection
can only be reset by a device programmer performing
a Bulk Erase to the device, clearing all Flash program
memory, Configuration bits and User IDs.
Write protection prohibits self-write and erase to a
portion or all of the Flash program memory as defined
by the bits, WRT<1:0>. Write protection does not affect
a device programmers ability to read, write or erase the
device.
10.1 PMADRL and PMADRH Registers
The PMADRH:PMADRL register pair can address up
to a maximum of 32K words of program memory. When
selecting a program address value, the MSB of the
address is written to the PMADRH register and the LSB
is written to the PMADRL register.
10.1.1 PMCON1 AND PMCON2
REGISTERS
PMCON1 is the control register for Flash program
memory accesses.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared by hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write operation to
occur. On power-up, the WREN bit is clear. The
WRERR bit is set when a write operation is interrupted
by a Reset during normal operation. In these situations,
following Reset, the user can check the WRERR bit
and execute the appropriate error handling routine.
The PMCON2 register is a write-only register. Attempting
to read the PMCON2 register will return all ‘0’s.
To enable writes to the program memory, a specific
pattern (the unlock sequence), must be written to the
PMCON2 register. The required unlock sequence
prevents inadvertent writes to the program memory
write latches and Flash program memory.
10.2 Flash Program Memory Overview
It is important to understand the Flash program memory
structure for erase and programming operations. Flash
program memory is arranged in rows. A row consists of
a fixed number of 14-bit program memory words. A row
is the minimum size that can be erased by user software.
After a row has been erased, the user can reprogram
all or a portion of this row. Data to be written into the
program memory row is written to 14-bit wide data write
latches. These write latches are not directly accessible
to the user, but may be loaded via sequential writes to
the PMDATH:PMDATL register pair.
See Table 10-1 for Erase Row size and the number of
write latches for Flash program memory.
Note 1: Code protection of the entire Flash
program memory array is enabled by
clearing the CP bit of Configuration Words.
Note: If the user wants to modify only a portion
of a previously programmed row, then the
contents of the entire row must be read
and saved in RAM prior to the erase.
Then, new data and retained data can be
written into the write latches to reprogram
the row of Flash program memory. How-
ever, any unprogrammed locations can be
written without first erasing the row. In this
case, it is not necessary to save and
rewrite the other previously programmed
locations.
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10.2.1 READING THE FLASH PROGRAM
MEMORY
To read a program memory location, the user must:
1. Write the desired address to the
PMADRH:PMADRL register pair.
2. Clear the CFGS bit of the PMCON1 register.
3. Then, set control bit RD of the PMCON1 register.
Once the read control bit is set, the program memory
Flash controller will use the second instruction cycle to
read the data. This causes the second instruction
immediately following the “BSF PMCON1,RD” instruction
to be ignored. The data is available in the very next cycle,
in the PMDATH:PMDATL register pair; therefore, it can
be read as two bytes in the following instructions.
The PMDATH:PMDATL register pair will hold this value
until another read or until it is written to by the user.
FIGURE 10-1: FLASH PROGRAM
MEMORY READ
FLOWCHART
TABLE 10-1: FLASH MEMORY
ORGANIZATION BY DEVICE
Device Row Erase
(words)
Write
Latches
(words)
PIC16(L)F1778 32 32
PIC16(L)F1777/9
Note: The two instructions following a program
memory read are required to be NOPs.
This prevents the user from executing a
2-cycle instruction on the next instruction
after the RD bit is set.
Start
Read Operation
Select
Program or Configuration Memory
(CFGS)
Select
Word Address
(PMADRH:PMADRL)
Initiate Read operation
(RD = 1)
Instruction fetched ignored
NOP execution forced
Data read now in
PMDATH:PMDATL
Instruction fetched ignored
NOP execution forced
End
Read Operation
Rev. 10-000046A
7/30/2013
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FIGURE 10-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION
EXAMPLE 10-1: FLASH PROGRAM MEMORY READ
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
BSF PMCON1,RD
executed here
INSTR(PC + 1)
executed here
PC
PC + 1 PMADRH,PMADRL PC+3 PC + 5
Flash ADDR
RD bit
PMDATH,PMDATL
PC + 3 PC + 4
INSTR (PC + 1)
INSTR(PC - 1)
executed here INSTR(PC + 3)
executed here INSTR(PC + 4)
executed here
Flash Data
PMDATH
PMDATL
Register
INSTR (PC) INSTR (PC + 3) INSTR (PC + 4)
instruction ignored
Forced NOP
INSTR(PC + 2)
executed here
instruction ignored
Forced NOP
* This code block will read 1 word of program
* memory at the memory address:
PROG_ADDR_HI : PROG_ADDR_LO
* data will be returned in the variables;
* PROG_DATA_HI, PROG_DATA_LO
BANKSEL PMADRL ; Select Bank for PMCON registers
MOVLW PROG_ADDR_LO ;
MOVWF PMADRL ; Store LSB of address
MOVLW PROG_ADDR_HI ;
MOVWF PMADRH ; Store MSB of address
BCF PMCON1,CFGS ; Do not select Configuration Space
BSF PMCON1,RD ; Initiate read
NOP ; Ignored (Figure 10-1)
NOP ; Ignored (Figure 10-1)
MOVF PMDATL,W ; Get LSB of word
MOVWF PROG_DATA_LO ; Store in user location
MOVF PMDATH,W ; Get MSB of word
MOVWF PROG_DATA_HI ; Store in user location
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10.2.2 FLASH MEMORY UNLOCK
SEQUENCE
The unlock sequence is a mechanism that protects the
Flash program memory from unintended self-write pro-
gramming or erasing. The sequence must be executed
and completed without interruption to successfully
complete any of the following operations:
• Row Erase
• Load program memory write latches
• Write of program memory write latches to
program memory
• Write of program memory write latches to User
IDs
The unlock sequence consists of the following steps:
1. Write 55h to PMCON2
2. Write AAh to PMCON2
3. Set the WR bit in PMCON1
4. NOP instruction
5. NOP instruction
Once the WR bit is set, the processor will always force
two NOP instructions. When an Erase Row or Program
Row operation is being performed, the processor will stall
internal operations (typical 2 ms), until the operation is
complete and then resume with the next instruction.
When the operation is loading the program memory write
latches, the processor will always force the two NOP
instructions and continue uninterrupted with the next
instruction.
Since the unlock sequence must not be interrupted,
global interrupts should be disabled prior to the unlock
sequence and re-enabled after the unlock sequence is
completed.
FIGURE 10-3: FLASH PROGRAM
MEMORY UNLOCK
SEQUENCE FLOWCHART
Start
Unlock Sequence
End
Unlock Sequence
Write 0x55 to
PMCON2
Write 0xAA to
PMCON2
Initiate
Write or Erase operation
(WR = 1)
Instruction fetched ignored
NOP execution forced
Instruction fetched ignored
NOP execution forced
Rev. 10-000047A
7/30/2013
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10.2.3 ERASING FLASH PROGRAM
MEMORY
While executing code, program memory can only be
erased by rows. To erase a row:
1. Load the PMADRH:PMADRL register pair with
any address within the row to be erased.
2. Clear the CFGS bit of the PMCON1 register.
3. Set the FREE and WREN bits of the PMCON1
register.
4. Write 55h, then AAh, to PMCON2 (Flash
programming unlock sequence).
5. Set control bit WR of the PMCON1 register to
begin the erase operation.
See Example 10-2.
After the “BSF PMCON1,WR” instruction, the processor
requires two cycles to set up the erase operation. The
user must place two NOP instructions immediately fol-
lowing the WR bit set instruction. The processor will
halt internal operations for the typical 2 ms erase time.
This is not Sleep mode as the clocks and peripherals
will continue to run. After the erase cycle, the processor
will resume operation with the third instruction after the
PMCON1 write instruction.
FIGURE 10-4: FLASH PROGRAM
MEMORY ERASE
FLOWCHART
Start
Erase Operation
End
Erase Operation
Disable Interrupts
(GIE = 0)
Select
Program or Configuration Memory
(CFGS)
Select Erase Operation
(FREE = 1)
Select Row Address
(PMADRH:PMADRL)
Enable Write/Erase Operation
(WREN = 1)
Unlock Sequence
(See Note 1)
Re-enable Interrupts
(GIE = 1)
Disable Write/Erase Operation
(WREN = 0)
CPU stalls while
Erase operation completes
(2 ms typical)
Rev. 10-000048A
7/30/2013
Note 1: See Figure 10-3.
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EXAMPLE 10-2: ERASING ONE ROW OF PROGRAM MEMORY
; This row erase routine assumes the following:
; 1. A valid address within the erase row is loaded in ADDRH:ADDRL
; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
BCF INTCON,GIE ; Disable ints so required sequences will execute properly
BANKSEL PMADRL
MOVF ADDRL,W ; Load lower 8 bits of erase address boundary
MOVWF PMADRL
MOVF ADDRH,W ; Load upper 6 bits of erase address boundary
MOVWF PMADRH
BCF PMCON1,CFGS ; Not configuration space
BSF PMCON1,FREE ; Specify an erase operation
BSF PMCON1,WREN ; Enable writes
MOVLW 55h ; Start of required sequence to initiate erase
MOVWF PMCON2 ; Write 55h
MOVLW 0AAh ;
MOVWF PMCON2 ; Write AAh
BSF PMCON1,WR ; Set WR bit to begin erase
NOP ; NOP instructions are forced as processor starts
NOP ; row erase of program memory.
;
; The processor stalls until the erase process is complete
; after erase processor continues with 3rd instruction
BCF PMCON1,WREN ; Disable writes
BSF INTCON,GIE ; Enable interrupts
Required
Sequence
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10.2.4 WRITING TO FLASH PROGRAM
MEMORY
Program memory is programmed using the following
steps:
1. Load the address in PMADRH:PMADRL of the
row to be programmed.
2. Load each write latch with data.
3. Initiate a programming operation.
4. Repeat steps 1 through 3 until all data is written.
Before writing to program memory, the word(s) to be
written must be erased or previously unwritten.
Program memory can only be erased one row at a time.
No automatic erase occurs upon the initiation of the
write.
Program memory can be written one or more words at
a time. The maximum number of words written at one
time is equal to the number of write latches. See
Figure 10-5 (row writes to program memory with 32
write latches) for more details.
The write latches are aligned to the Flash row address
boundary defined by the upper ten bits of
PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:5>)
with the lower five bits of PMADRL, (PMADRL<4:0>)
determining the write latch being loaded. Write opera-
tions do not cross these boundaries. At the completion
of a program memory write operation, the data in the
write latches is reset to contain 0x3FFF.
The following steps should be completed to load the
write latches and program a row of program memory.
These steps are divided into two parts. First, each write
latch is loaded with data from the PMDATH:PMDATL
using the unlock sequence with LWLO = 1. When the
last word to be loaded into the write latch is ready, the
LWLO bit is cleared and the unlock sequence
executed. This initiates the programming operation,
writing all the latches into Flash program memory.
1. Set the WREN bit of the PMCON1 register.
2. Clear the CFGS bit of the PMCON1 register.
3. Set the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘1’, the write sequence will only load the write
latches and will not initiate the write to Flash
program memory.
4. Load the PMADRH:PMADRL register pair with
the address of the location to be written.
5. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
6. Execute the unlock sequence (Section 10.2.2
“Flash Memory Unlock Sequence”). The write
latch is now loaded.
7. Increment the PMADRH:PMADRL register pair
to point to the next location.
8. Repeat steps 5 through 7 until all but the last
write latch has been loaded.
9. Clear the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘0’, the write sequence will initiate the write to
Flash program memory.
10. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
11. Execute the unlock sequence (Section 10.2.2
“Flash Memory Unlock Sequence”). The
entire program memory latch content is now
written to Flash program memory.
An example of the complete write sequence is shown in
Example 10-3. The initial address is loaded into the
PMADRH:PMADRL register pair; the data is loaded
using indirect addressing.
Note: The special unlock sequence is required
to load a write latch with data or initiate a
Flash programming operation. If the
unlock sequence is interrupted, writing to
the latches or program memory will not be
initiated.
Note: The program memory write latches are
reset to the blank state (0x3FFF) at the
completion of every write or erase
operation. As a result, it is not necessary
to load all the program memory write
latches. Unloaded latches will remain in
the blank state.
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FIGURE 10-5: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES
6 8
14
1414
Write Latch #31
1Fh
1414
Program Memory Write Latches
14 14 14
PMADRH<6:0>:
PMADRL<7:5>
Flash Program Memory
Row
Row
Address
Decode
Addr
Write Latch #30
1Eh
Write Latch #1
01h
Write Latch #0
00h
Addr Addr Addr
000h 001Fh
001Eh
0000h 0001h
001h 003Fh
003Eh
0020h 0021h
002h 005Fh005Eh0040h 0041h
3FEh 7FDFh7FDEh
7FC0h 7FC1h
3FFh 7FFFh7FFEh7FE0h 7FE1h
14
PMADRL<4:0>
400h 8009h - 801Fh8000h - 8003h
Configuration
Words
USER ID 0 - 3
8007h –8008h8006h
DEVICE ID
Dev / Rev
reserved reserved
Configuration Memory
CFGS = 0
CFGS = 1
PMADRH PMADRL
76 07 54 0
c4 c3 c2 c1 c0r9 r8 r7 r6 r5 r4 r3-r1 r0r2
5
10
PMDATH PMDATL
75 07 0
--
8004h –8005h
Rev. 10-000004A
7/30/2013
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FIGURE 10-6: FLASH PROGRAM MEMORY WRITE FLOWCHART
Disable Interrupts
(GIE = 0)
Start
Write Operation
Select
Program or Config. Memory
(CFGS)
Select Row Address
(PMADRH:PMADRL)
Select Write Operation
(FREE = 0)
Enable Write/Erase
Operation (WREN = 1)
Unlock Sequence
(Figure x-x)
Disable
Write/Erase Operation
(WREN = 0)
Re-enable Interrupts
(GIE = 1)
End
Write Operation
No delay when writing to
Program Memory Latches
Determine number of words
to be written into Program or
Configuration Memory.
The number of words cannot
exceed the number of words
per row.
(word_cnt) Load the value to write
(PMDATH:PMDATL)
Update the word counter
(word_cnt--)
Last word to
write ?
Increment Address
(PMADRH:PMADRL++)
Unlock Sequence
(Figure x-x)
CPU stalls while Write
operation completes
(2ms typical)
Load Write Latches Only
(LWLO = 1)
Write Latches to Flash
(LWLO = 0)
No
Yes
Figure 10-3
Figure 10-3
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EXAMPLE 10-3: WRITING TO FLASH PROGRAM MEMORY
; This write routine assumes the following:
; 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR
; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
; stored in little endian format
; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL
; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
;BCF INTCON,GIE ; Disable ints so required sequences will execute properly
BANKSEL PMADRH ; Bank 3
MOVF ADDRH,W ; Load initial address
MOVWF PMADRH ;
MOVF ADDRL,W ;
MOVWF PMADRL ;
MOVLW LOW DATA_ADDR ; Load initial data address
MOVWF FSR0L ;
MOVLW HIGH DATA_ADDR ; Load initial data address
MOVWF FSR0H ;
BCF PMCON1,CFGS ; Not configuration space
BSF PMCON1,WREN ; Enable writes
BSF PMCON1,LWLO ; Only Load Write Latches
LOOP MOVIW FSR0++ ; Load first data byte into lower
MOVWF PMDATL ;
MOVIW FSR0++ ; Load second data byte into upper
MOVWF PMDATH ;
MOVF PMADRL,W ; Check if lower bits of address are '00000'
XORLW 0x1F ; Check if we're on the last of 32 addresses
ANDLW 0x1F ;
BTFSC STATUS,Z ; Exit if last of 32 words,
GOTO START_WRITE ;
MOVLW 55h ; Start of required write sequence:
MOVWF PMCON2 ; Write 55h
MOVLW 0AAh ;
MOVWF PMCON2 ; Write AAh
BSF PMCON1,WR ; Set WR bit to begin write
NOP ; NOP instructions are forced as processor
; loads program memory write latches
NOP ;
INCF PMADRL,F ; Still loading latches Increment address
GOTO LOOP ; Write next latches
START_WRITE
BCF PMCON1,LWLO ; No more loading latches - Actually start Flash program
; memory write
MOVLW 55h ; Start of required write sequence:
MOVWF PMCON2 ; Write 55h
MOVLW 0AAh ;
MOVWF PMCON2 ; Write AAh
BSF PMCON1,WR ; Set WR bit to begin write
NOP ; NOP instructions are forced as processor writes
; all the program memory write latches simultaneously
NOP ; to program memory.
; After NOPs, the processor
; stalls until the self-write process in complete
; after write processor continues with 3rd instruction
BCF PMCON1,WREN ; Disable writes
BSF INTCON,GIE ; Enable interrupts
Required
Sequence
Required
Sequence
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10.3 Modifying Flash Program Memory
When modifying existing data in a program memory
row, and data within that row must be preserved, it must
first be read and saved in a RAM image. Program
memory is modified using the following steps:
1. Load the starting address of the row to be
modified.
2. Read the existing data from the row into a RAM
image.
3. Modify the RAM image to contain the new data
to be written into program memory.
4. Load the starting address of the row to be
rewritten.
5. Erase the program memory row.
6. Load the write latches with data from the RAM
image.
7. Initiate a programming operation.
FIGURE 10-7: FLASH PROGRAM
MEMORY MODIFY
FLOWCHART
Start
Modify Operation
End
Modify Operation
Read Operation
(See Note 1)
An image of the entire row
read must be stored in RAM
Erase Operation
(See Note 2)
Modify Image
The words to be modified are
changed in the RAM image
Write Operation
Use RAM image
(See Note 3)
Rev. 10-000050A
7/30/2013
Note 1: See Figure 10-1.
2: See Figure 10-4.
3: See Figure 10-6.
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10.4 User ID, Device ID and
Configurati on Word Access
Instead of accessing program memory, the User ID’s,
Device ID/Revision ID and Configuration Words can be
accessed when CFGS = 1 in the PMCON1 register.
This is the region that would be pointed to by
PC<15> = 1, but not all addresses are accessible.
Different access may exist for reads and writes. Refer
to Tab le 1 0- 2.
When read access is initiated on an address outside
the parameters listed in Table 1 0- 2, the
PMDATH:PMDATL register pair is cleared, reading
back ‘0’s.
TABLE 10-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)
EXAMPLE 10-4: CONFIGURATION WORD AND DEVICE ID ACCESS
Address Function Read Access Write Access
8000h-8003h User IDs Yes Yes
8005h-8006h Device ID/Revision ID Yes No
8007h-8008h Configuration Words 1 and 2 Yes No
* This code block will read 1 word of program memory at the memory address:
* PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;
* PROG_DATA_HI, PROG_DATA_LO
BANKSEL PMADRL ; Select correct Bank
MOVLW PROG_ADDR_LO ;
MOVWF PMADRL ; Store LSB of address
CLRF PMADRH ; Clear MSB of address
BSF PMCON1,CFGS ; Select Configuration Space
BCF INTCON,GIE ; Disable interrupts
BSF PMCON1,RD ; Initiate read
NOP ; Executed (See Figure 10-2)
NOP ; Ignored (See Figure 10-2)
BSF INTCON,GIE ; Restore interrupts
MOVF PMDATL,W ; Get LSB of word
MOVWF PROG_DATA_LO ; Store in user location
MOVF PMDATH,W ; Get MSB of word
MOVWF PROG_DATA_HI ; Store in user location
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10.5 Write/Verify
It is considered good programming practice to verify that
program memory writes agree with the intended value.
Since program memory is stored as a full page then the
stored program memory contents are compared with the
intended data stored in RAM after the last write is
complete.
FIGURE 10-8: FLASH PROGRAM
MEMORY VERIFY
FLOWCHART
Start
Verify Operation
This routine assumes that the last
row of data written was from an
image saved on RAM. This image
will be used to verify the data
currently stored in Flash Program
Memory
Fail
Verify Operation
Last word ?
PMDAT =
RAM image ?
Read Operation
(See Note 1)
End
Verify Operation
No
No
Yes
Yes
Rev. 10-000051A
7/30/2013
Note 1: See Figure 10-1.
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10.6 Register Definitions: Flash Program Memory Control
REGISTER 10-1: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
PMDAT<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 PMDAT<7:0>: Read/write value for Least Significant bits of program memory
REGISTER 10-2: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER
U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
——PMDAT<13:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 PMDAT<13:8>: Read/write value for Most Significant bits of program memory
REGISTER 10-3: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
PMADR<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 PMADR<7:0>: Specifies the Least Significant bits for program memory address
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REGISTER 10-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER
U-1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
—(1) PMADR<14:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 Unimplemented: Read as ‘1’
bit 6-0 PMADR<14:8>: Specifies the Most Significant bits for program memory address
Note 1: Unimplemented, read as ‘1’.
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REGISTER 10-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER
U-1 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q(2) R/W-0/0 R/S/HC-0/0 R/S/HC-0/0
—(1) CFGS LWLO(3) FREE WRERR WREN WR RD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware
bit 7 Unimplemented: Read as ‘1’
bit 6 CFGS: Configuration Select bit
1 = Access Configuration, User ID and Device ID Registers
0 = Access Flash program memory
bit 5 LWLO: Load Write Latches Only bit(3)
1 = Only the addressed program memory write latch is loaded/updated on the next WR command
0 = The addressed program memory write latch is loaded/updated and a write of all program memory write
latches will be initiated on the next WR command
bit 4 FREE: Program Flash Erase Enable bit
1 = Performs an erase operation on the next WR command (hardware cleared upon completion)
0 = Performs a write operation on the next WR command
bit 3 WRERR: Program/Erase Error Flag bit
1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automat-
ically on any set attempt (write ‘1’) of the WR bit).
0 = The program or erase operation completed normally
bit 2 WREN: Program/Erase Enable bit
1 = Allows program/erase cycles
0 = Inhibits programming/erasing of program Flash
bit 1 WR: Write Control bit
1 = Initiates a program Flash program/erase operation.
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
0 = Program/erase operation to the Flash is complete and inactive
bit 0 RD: Read Control bit
1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set
(not cleared) in software.
0 = Does not initiate a program Flash read
Note 1: Unimplemented bit, read as ‘1’.
2: The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1).
3: The LWLO bit is ignored during a program memory erase operation (FREE = 1).
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TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY
TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY
REGISTER 10-6: PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER
W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0
Program Memory Control Register 2
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 Flash Memo ry Unlock Pattern bit s
To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
PMCON1 register. The value written to this register is used to unlock the writes. There are specific
timing requirements on these writes.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132
PMCON1 —(1) CFGS LWLO FREE WRERR WREN WR RD 171
PMCON2 Program Memory Control Register 2 172
PMADRL PMADRL<7:0> 169
PMADRH —(1) PMADRH<6:0> 170
PMDATL PMDATL<7:0> 169
PMDATH ——PMDATH<5:0>169
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.
Note 1: Unimplemented, read as ‘1’.
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register
on Page
CONFIG1 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> —95
7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
CONFIG2 13:8 — — LVP DEBUG LPBOR BORV STVREN PLLEN 97
7:0 ZCD — — — — PPS1WAY WRT<1:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.
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11.0 I/O PORTS
Each port has six standard registers for its operation.
These registers are:
• TRISx registers (data direction)
• PORTx registers (reads the levels on the pins of
the device)
• LATx registers (output latch)
• INLVLx (input level control)
• ODCONx registers (open-drain)
• SLRCONx registers (slew rate
Some ports may have one or more of the following
additional registers. These registers are:
• ANSELx (analog select)
• WPUx (weak pull-up)
In general, when a peripheral is enabled on a port pin,
that pin cannot be used as a general purpose output.
However, the pin can still be read.
The Data Latch (LATx registers) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
A write operation to the LATx register has the same
effect as a write to the corresponding PORTx register.
A read of the LATx register reads of the values held in
the I/O PORT latches, while a read of the PORTx
register reads the actual I/O pin value.
Ports that support analog inputs have an associated
ANSELx register. When an ANSEL bit is set, the digital
input buffer associated with that bit is disabled.
Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 11-1.
FIGURE 11-1: GENERIC I/O PORT
OPERATION
TABLE 11-1: PORT AVAILABILITY PER
DEVICE
Device
PORTA
PORTB
PORTC
PORTD
PORTE
PIC16(L)F1778 ●●● ●
PIC16(L)F1777/9 ●●●●●
Write LATx
Write PORTx
Data bus
Read PORTx
To digital peripherals
To analog peripherals
Data Register
TRISx
VSS
I/O pin
ANSELx
DQ
CK
Read LATx
VDD
Rev. 10-000052A
7/30/2013
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11.1 PORTA Registers
11.1.1 DATA REGISTER
PORTA is a 6-bit wide, bidirectional port. The
corresponding data direction register is TRISA
(Register 11-2). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). The exception is RA3, which is
input-only and its TRIS bit will always read as ‘1’.
Example 11-1 shows how to initialize PORTA.
Reading the PORTA register (Register 11-1) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch (LATA).
11.1.2 DIRECTION CONTROL
The TRISA register (Register 11-2) controls the
PORTA pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISA register are maintained set when using
them as analog inputs. I/O pins configured as analog
inputs always read ‘0’.
11.1.3 OPEN-DRAIN CONTROL
The ODCONA register (Register 11-6) controls the
open-drain feature of the port. Open-drain operation is
independently selected for each pin. When an
ODCONA bit is set, the corresponding port output
becomes an open-drain driver capable of sinking
current only. When an ODCONA bit is cleared, the
corresponding port output pin is the standard push-pull
drive capable of sourcing and sinking current.
11.1.4 SLEW RATE CONTROL
The SLRCONA register (Register 11-7) controls the
slew rate option for each port pin. Slew rate control is
independently selectable for each port pin. When an
SLRCONA bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCONA bit is cleared,
The corresponding port pin drive slews at the maximum
rate possible.
11.1.5 INPUT THRESHOLD CONTROL
The INLVLA register (Register 11-8) controls the input
voltage threshold for each of the available PORTA input
pins. A selection between the Schmitt Trigger CMOS or
the TTL Compatible thresholds is available. The input
threshold is important in determining the value of a read
of the PORTA register and also the level at which an
interrupt-on-change occurs, if that feature is enabled.
See Table 36-4: I/O Ports for more information on
threshold levels.
11.1.6 ANALOG CONTROL
The ANSELA register (Register 11-4) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELA bits has no effect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
EXAMPL E 11 -1 : INIT IALIZI NG PORTA
Note: Changing the input threshold selection
should be performed while all peripheral
modules are disabled. Changing the
threshold level during the time a module is
active may inadvertently generate a
transition associated with an input pin,
regardless of the actual voltage level on
that pin.
Note: The ANSELA bits default to the Analog
mode after reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
; This code example illustrates
; initializing the PORTA register. The
; other ports are initialized in the same
; manner.
BANKSEL PORTA ;
CLRF PORTA ;Init PORTA
BANKSEL LATA ;Data Latch
CLRF LATA ;
BANKSEL ANSELA ;
CLRF ANSELA ;digital I/O
BANKSEL TRISA ;
MOVLW B'00111000' ;Set RA<5:3> as inputs
MOVWF TRISA ;and set RA<2:0> as
;outputs
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11.1.7 PORTA FUNCTIONS AND OUTPUT
PRIORITIES
Each PORTA pin is multiplexed with other functions.
Each pin defaults to the PORT latch data after reset.
Other functions are selected with the peripheral pin
select logic. See Section 12.0 “Peri phera l Pin Sele ct
(PPS) Module” for more information.
Analog input functions, such as ADC and comparator
inputs are not shown in the peripheral pin select lists.
These inputs are active when the I/O pin is set for
Analog mode using the ANSELA register. Digital output
functions may continue to control the pin when it is in
Analog mode.
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11.2 Re g is ter D e finiti ons : PO R TA
REGISTER 11-1: PORTA: PORTA REGISTER
R/W-x/x R/W-x/x R/W-x/x R/W-x/x R-x/x R/W-x/x R/W-x/x R/W-x/x
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 RA<7:0>: PORTA I/O Value bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
REGISTER 11-2: TRISA: PORTA TRI-STATE REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 TRISA<7:0>: PORTA Tri-State Control bit
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
REGISTER 11-3: LATA: PORTA DATA LATCH REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 LATA<7:0>: RA<7:0> Output Latch Value bits(1)
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
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REGISTER 11-4: ANSELA: PORTA ANALOG SELECT REGISTER
U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
—— ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 ANSA<5:0>: Analog Select between Analog or Digital Function on pins RA<5:0>
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
REGISTER 11-5: WPUA: WEAK PULL-UP PORTA REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 WPUA<7:0>: Weak Pull-up Register bits(1),(2)
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.
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REGISTER 11-6: ODCONA: PORTA OPEN-DRAIN CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ODA7 ODA6 ODA5 ODA4 ODA3 ODA2 ODA1 ODA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ODA<7:0>: PORTA Open-Drain Enable bits
For RA<7:0> pins
1 = Port pin operates as open-drain drive (sink current only)
0 = Port pin operates as standard push-pull drive (source and sink current)
REGISTER 11-7: SLRCONA: PORTA SLEW RATE CONTROL REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 SLRA<7:0>: PORTA Slew Rate Enable bits
For RA<7:0> pins
1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate
REGISTER 11-8: INLVLA: PORTA INPUT LEVEL CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 INLVLA<7:0>: PORTA Input Level Select bits
For RA<7:0> pins
1 = Port pin digital input operates with ST thresholds
0 = Port pin digital input operates with TTL thresholds
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TABLE 11-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
TABLE 11-3: SUMMARY OF CONFIGURATION WORD WITH PORTA
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ANSELA —— ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177
INLVLA INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 178
LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 176
ODCONA ODA7 ODA6 ODA5 ODA4 ODA3 ODA2 ODA1 ODA0 178
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 274
PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 176
SLRCONA SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 178
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176
WPUA WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 177
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTA.
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 B it 8/0 Register
on Page
CONFIG1 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> —95
7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.
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11.3 PORTB Registers
11.3.1 DATA REGISTER
PORTB is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISB
(Register 11-10). Setting a TRISB bit (= 1) will make the
corresponding PORTB pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISB bit (= 0) will make the corresponding
PORTB pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 11-1 shows how to initialize an I/O port.
Reading the PORTB register (Register 11-9) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATB).
11.3.2 DIRECTION CONTROL
The TRISB register (Register 11-10) controls the
PORTB pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits in
the TRISB register are maintained set when using them
as analog inputs. I/O pins configured as analog inputs
always read ‘0’.
11.3.3 OPEN-DRAIN CONTROL
The ODCONB register (Register 11-14) controls the
open-drain feature of the port. Open-drain operation is
independently selected for each pin. When an
ODCONB bit is set, the corresponding port output
becomes an open-drain driver capable of sinking
current only. When an ODCONB bit is cleared, the
corresponding port output pin is the standard push-pull
drive capable of sourcing and sinking current.
11.3.4 SLEW RATE CONTROL
The SLRCONB register (Register 11-15) controls the
slew rate option for each port pin. Slew rate control is
independently selectable for each port pin. When an
SLRCONB bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCONB bit is cleared,
The corresponding port pin drive slews at the maximum
rate possible.
11.3.5 INPUT THRESHOLD CONTROL
The INLVLB register (Register 11-16) controls the input
voltage threshold for each of the available PORTB input
pins. A selection between the Schmitt Trigger CMOS or
the TTL Compatible thresholds is available. The input
threshold is important in determining the value of a read
of the PORTB register and also the level at which an
interrupt-on-change occurs, if that feature is enabled.
See Table 36-4: I/O Ports for more information on
threshold levels.
11.3.6 ANALOG CONTROL
The ANSELB register (Register 11-12) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELB bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELB bits has no effect on digital out-
put functions. A pin with TRIS clear and ANSELB set will
still operate as a digital output, but the Input mode will be
analog. This can cause unexpected behavior when exe-
cuting read-modify-write instructions on the affected
port.
11.3.7 PORTB FUNCTIONS AND OUTPUT
PRIORITIES
Each pin defaults to the PORT latch data after reset.
Other functions are selected with the peripheral pin
select logic. See Sectio n 12.0 “ Perip hera l Pin Sele ct
(PPS) Module” for more information. Analog input
functions, such as ADC and op amp inputs, are not
shown in the peripheral pin select lists. These inputs
are active when the I/O pin is set for Analog mode using
the ANSELB register. Digital output functions may
continue to control the pin when it is in Analog mode.
11.3.8 HIGH CURRENT DRIVE CONTROL
The output drivers on RB1 and RB0 are capable of
sourcing and sinking up to 100 mA. This extra drive
capacity can be enabled and disabled with the control
bits in the HIDRVB register (Register 11-17).
Note: Changing the input threshold selection
should be performed while all peripheral
modules are disabled. Changing the
threshold level during the time a module is
active may inadvertently generate a
transition associated with an input pin,
regardless of the actual voltage level on
that pin.
Note: The ANSELB bits default to the Analog
mode after reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
2015-2016 Microchip Technology Inc. DS40001819B-page 181
PIC16(L)F1777/8/9
11.4 Re g is ter D e finiti ons : PO R T B
REGISTER 11-9: PORTB: PORTB REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 RB<7:0>: PORTB General Purpose I/O Pin bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
REGISTER 11-10: TRISB: PORTB TRI-STATE REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 TRISB<7:0>: PORTB Tri-State Control bits
1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output
REGISTER 11-11: LATB: PORTB DATA LATCH REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 LATB<7:0>: PORTB Output Latch Value bits(1)
Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
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DS40001819B-page 182 2015-2016 Microchip Technology Inc.
REGISTER 11-12: ANSELB: PORTB ANALOG SELECT REGISTER
U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
—— ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 ANSB<5:0>: Analog Select between Analog or Digital Function on pins RB<5:0>
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
REGISTER 11-13: WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 WPUB<7:0>: Weak Pull-up Register bits(1,2)
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.
2015-2016 Microchip Technology Inc. DS40001819B-page 183
PIC16(L)F1777/8/9
REGISTER 11-14: ODCONB: PORTB OPEN-DRAIN CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ODB<7:0>: PORTB Open-Drain Enable bits
For RB<7:0> pins
1 = Port pin operates as open-drain drive (sink current only)
0 = Port pin operates as standard push-pull drive (source and sink current)
REGISTER 11-15: SLRCONB: PORTB SLEW RATE CONTROL REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 SLRB<7:0>: PORTB Slew Rate Enable bits
For RB<7:0> pins
1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate
REGISTER 11-16: INLVLB: PORTB INPUT LEVEL CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 INLVLB<7:0>: PORTB Input Level Select bits
For RB<7:0> pins
1 = Port pin digital input operates with ST thresholds
0 = Port pin digital input operates with TTL thresholds
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DS40001819B-page 184 2015-2016 Microchip Technology Inc.
TABLE 11-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
REGISTER 11-17: HIDRVB: PORTB HIGH DRIVE CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0
— — — — — — HIDB1 HIDB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-2 Unimplemen ted: Read as ‘0’
bit 1-0 HIDB<1:0>: PORTB High Drive Enable bits
For RB<1:0> pins
1 = High current source and sink enabled
0 = Standard current source and sink
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ANSELB —— ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182
HIDRVB — — — — — — HIDB1 HIDB0 184
INLVLB INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0 183
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 181
ODCONB ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 183
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 181
SLRCONB SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 183
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 183
WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 182
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTB.
2015-2016 Microchip Technology Inc. DS40001819B-page 185
PIC16(L)F1777/8/9
11.5 PORTC Registers
11.5.1 DATA REGISTER
PORTC is an 8-bit wide bidirectional port in the
PIC16(L)F1777/8/9 devices. The corresponding data
direction register is TRISC (Register 11-19). Setting a
TRISC bit (= 1) will make the corresponding PORTC pin
an input (i.e., put the corresponding output driver in a
High-Impedance mode). Clearing a TRISC bit (= 0) will
make the corresponding PORTC pin an output (i.e.,
enable the output driver and put the contents of the
output latch on the selected pin). Example 11-1 shows
how to initialize an I/O port.
Reading the PORTC register (Register 11-18) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATC).
11.5.2 DIRECTION CONTROL
The TRISC register (Register 11-19) controls the
PORTC pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits in
the TRISC register are maintained set when using them
as analog inputs. I/O pins configured as analog inputs
always read ‘0’.
11.5.3 INPUT THRESHOLD CONTROL
The INLVLC register (Register 11-25) controls the input
voltage threshold for each of the available PORTC
input pins. A selection between the Schmitt Trigger
CMOS or the TTL Compatible thresholds is available.
The input threshold is important in determining the
value of a read of the PORTC register and also the
level at which an interrupt-on-change occurs, if that
feature is enabled. See Table 36-4: I/O Ports for more
information on threshold levels.
11.5.4 OPEN-DRAIN CONTROL
The ODCONC register (Register 11-23) controls the
open-drain feature of the port. Open-drain operation is
independently selected for each pin. When an
ODCONC bit is set, the corresponding port output
becomes an open-drain driver capable of sinking
current only. When an ODCONC bit is cleared, the
corresponding port output pin is the standard push-pull
drive capable of sourcing and sinking current.
11.5.5 SLEW RATE CONTROL
The SLRCONC register (Register 11-24) controls the
slew rate option for each port pin. Slew rate control is
independently selectable for each port pin. When an
SLRCONC bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCONC bit is cleared,
The corresponding port pin drive slews at the maximum
rate possible.
11.5.6 ANALOG CONTROL
The ANSELC register (Register 11-21) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELC bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELC bits has no effect on digital out-
put functions. A pin with TRIS clear and ANSELC set will
still operate as a digital output, but the Input mode will be
analog. This can cause unexpected behavior when exe-
cuting read-modify-write instructions on the affected
port.
11.5.7 PORTC FUNCTIONS AND OUTPUT
PRIORITIES
Each pin defaults to the PORT latch data after reset.
Other functions are selected with the peripheral pin
select logic. See Sectio n 12.0 “ Perip hera l Pin Sele ct
(PPS) Module” for more information.
Analog input functions, such as ADC and comparator
inputs, are not shown in the peripheral pin select lists.
These inputs are active when the I/O pin is set for
Analog mode using the ANSELC register. Digital output
functions may continue to control the pin when it is in
Analog mode.
Note: Changing the input threshold selection
should be performed while all peripheral
modules are disabled. Changing the
threshold level during the time a module is
active may inadvertently generate a
transition associated with an input pin,
regardless of the actual voltage level on
that pin.
Note: The ANSELC bits default to the Analog
mode after reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
PIC16(L)F1777/8/9
DS40001819B-page 186 2015-2016 Microchip Technology Inc.
11.6 Re g is ter D e finiti ons : PO R T C
REGISTER 11-18: PORTC: PORTC REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
return of actual I/O pin values.
REGISTER 11-19: TRISC: PORTC TRI-STATE REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits
1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
2015-2016 Microchip Technology Inc. DS40001819B-page 187
PIC16(L)F1777/8/9
REGISTER 11-20: LATC: PORTC DATA LATCH REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 LATC<7:0>: PORTC Output Latch Value bits
REGISTER 11-21: ANSELC: PORTC ANALOG SELECT REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0
ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-2 ANSC<7:2>: Analog Select between Analog or Digital Function on pins RC<7:2>(1)
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
bit 1-0 Unimplemented: Read as ‘0’
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
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DS40001819B-page 188 2015-2016 Microchip Technology Inc.
REGISTER 11-22: WPUC: WEAK PULL-UP PORTC REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 WPUC<7:0>: Weak Pull-up Register bits(1, 2)
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.
REGISTER 11-23: ODCONC: PORTC OPEN-DRAIN CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ODC7 ODC6 ODC5 ODC4 ODC3 ODC2 ODC1 ODC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ODC<7:0>: PORTC Open-Drain Enable bits
For RC<7:0> pins
1 = Port pin operates as open-drain drive (sink current only)
0 = Port pin operates as standard push-pull drive (source and sink current)
2015-2016 Microchip Technology Inc. DS40001819B-page 189
PIC16(L)F1777/8/9
REGISTER 11-24: SLRCONC: PORTC SLEW RATE CONTROL REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 SLRC<7:0>: PORTC Slew Rate Enable bits
For RC<7:0> pins
1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate
REGISTER 11-25: INLVLC: PORTC INPUT LEVEL CONTROL REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 INLVLC<7:0>: PORTC Input Level Select bits
For RC<7:0> pins
1 = Port pin digital input operates with ST thresholds
0 = Port pin digital input operates with TTL thresholds
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DS40001819B-page 190 2015-2016 Microchip Technology Inc.
TABLE 11-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 187
INLVLC INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 189
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 187
ODCONC ODC7 ODC6 ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 188
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 186
SLRCONC SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 189
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186
WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 188
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTC.
2015-2016 Microchip Technology Inc. DS40001819B-page 191
PIC16(L)F1777/8/9
11.7 PORTD Registers
(PIC16(L)F1777/9 only)
11.7.1 DATA REGISTER
PORTD is an 8-bit wide bidirectional port in the
PIC16(L)F1777/8/9 devices. The corresponding data
direction register is TRISD (Register 11-27). Setting a
TRISD bit (= 1) will make the corresponding PORTD pin
an input (i.e., put the corresponding output driver in a
High-Impedance mode). Clearing a TRISD bit (= 0) will
make the corresponding PORTD pin an output (i.e.,
enable the output driver and put the contents of the
output latch on the selected pin). Example 11-1 shows
how to initialize an I/O port.
Reading the PORTD register (Register 11-26) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATD).
11.7.2 DIRECTION CONTROL
The TRISD register (Register 11-27) controls the
PORTD pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits in
the TRISD register are maintained set when using them
as analog inputs. I/O pins configured as analog inputs
always read ‘0’.
11.7.3 INPUT THRESHOLD CONTROL
The INLVLD register (Register 11-33) controls the input
voltage threshold for each of the available PORTD
input pins. A selection between the Schmitt Trigger
CMOS or the TTL Compatible thresholds is available.
The input threshold is important in determining the
value of a read of the PORTD register and also the
level at which an interrupt-on-change occurs, if that
feature is enabled. See Table 36-4: I/O Ports for more
information on threshold levels.
11.7.4 OPEN-DRAIN CONTROL
The ODCOND register (Register 11-31) controls the
open-drain feature of the port. Open-drain operation is
independently selected for each pin. When an
ODCOND bit is set, the corresponding port output
becomes an open-drain driver capable of sinking
current only. When an ODCOND bit is cleared, the
corresponding port output pin is the standard push-pull
drive capable of sourcing and sinking current.
11.7.5 SLEW RATE CONTROL
The SLRCOND register (Register 11-32) controls the
slew rate option for each port pin. Slew rate control is
independently selectable for each port pin. When an
SLRCOND bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCOND bit is cleared,
The corresponding port pin drive slews at the maximum
rate possible.
11.7.6 ANALOG CONTROL
The ANSELD register (Register 11-29) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELD bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELD bits has no effect on digital out-
put functions. A pin with TRIS clear and ANSELD set will
still operate as a digital output, but the Input mode will be
analog. This can cause unexpected behavior when exe-
cuting read-modify-write instructions on the affected
port.
11.7.7 PORTD FUNCTIONS AND OUTPUT
PRIORITIES
Each pin defaults to the PORT latch data after reset.
Other functions are selected with the peripheral pin
select logic. See Sectio n 12.0 “ Perip hera l Pin Sele ct
(PPS) Module” for more information.
Analog input functions, such as ADC and comparator
inputs, are not shown in the peripheral pin select lists.
These inputs are active when the I/O pin is set for
Analog mode using the ANSELD register. Digital output
functions may continue to control the pin when it is in
Analog mode.
Note: Changing the input threshold selection
should be performed while all peripheral
modules are disabled. Changing the
threshold level during the time a module is
active may inadvertently generate a
transition associated with an input pin,
regardless of the actual voltage level on
that pin.
Note: The ANSELD bits default to the Analog
mode after reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
PIC16(L)F1777/8/9
DS40001819B-page 192 2015-2016 Microchip Technology Inc.
11.8 Re g is ter D e finiti ons : PO R T D
REGISTER 11-26: PORTD: PORTD REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 RD<7:0>: PORTD General Purpose I/O Pin bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1: Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is
return of actual I/O pin values.
REGISTER 11-27: TRISD: PORTD TRI-STATE REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 TRISD<7:0>: PORTD Tri-State Control bits
1 = PORTD pin configured as an input (tri-stated)
0 = PORTD pin configured as an output
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REGISTER 11-28: LATD: PORTD DATA LATCH REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 LATD<7:0>: PORTD Output Latch Value bits
REGISTER 11-29: ANSELD: PORTD ANALOG SELECT REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ANSD<7:0>: Analog Select between Analog or Digital Function on pins RD<7:0>(1)
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
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DS40001819B-page 194 2015-2016 Microchip Technology Inc.
REGISTER 11-30: WPUD: WEAK PULL-UP PORTD REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 WPUD<7:0>: Weak Pull-up Register bits(1, 2)
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.
REGISTER 11-31: ODCOND: PORTD OPEN-DRAIN CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ODD7 ODD6 ODD5 ODD4 ODD3 ODD2 ODD1 ODD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ODD<7:0>: PORTD Open-Drain Enable bits
For RD<7:0> pins
1 = Port pin operates as open-drain drive (sink current only)
0 = Port pin operates as standard push-pull drive (source and sink current)
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REGISTER 11-32: SLRCOND: PORTD SLEW RATE CONTROL REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
SLRD7 SLRD6 SLRD5 SLRD4 SLRD3 SLRD2 SLRD1 SLRD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 SLRD<7:0>: PORTD Slew Rate Enable bits
For RD<7:0> pins
1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate
REGISTER 11-33: INLVLD: PORTD INPUT LEVEL CONTROL REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
INLVLD7 INLVLD6 INLVLD5 INLVLD4 INLVLD3 INLVLD2 INLVLD1 INLVLD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 INLVLD<7:0>: PORTD Input Level Select bits
For RD<7:0> pins
1 = Port pin digital input operates with ST thresholds
0 = Port pin digital input operates with TTL thresholds
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DS40001819B-page 196 2015-2016 Microchip Technology Inc.
TABLE 11-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD(1)
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 193
INLVLD INLVLD7 INLVLD6 INLVLD5 INLVLD4 INLVLD3 INLVLD2 INLVLD1 INLVLD0 195
LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 193
ODCOND ODD7 ODD6 ODD5 ODD4 ODD3 ODD2 ODD1 ODD0 194
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 195
SLRCOND SLRD7 SLRD6 SLRD5 SLRD4 SLRD3 SLRD2 SLRD1 SLRD0 195
TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 192
WPUD WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 194
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTD.
Note 1: PIC16(L)F1777/9 only.
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11.9 PORTE Registers
11.9.1 DATA REGISTER
PORTE is a 4-bit wide, bidirectional port. The
corresponding data direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE pin
an input (i.e., put the corresponding output driver in a
High-Impedance mode). Clearing a TRISE bit (= 0) will
make the corresponding PORTE pin an output (i.e.,
enable the output driver and put the contents of the
output latch on the selected pin). The exception is RE3,
which is input only and its TRIS bit will always read as
‘1’. Example 11-1 shows how to initialize an I/O port.
Reading the PORTE register (Register 11-34) reads
the status of the pins, whereas writing to it will write to
the PORT latch. All write operations are
read-modify-write operations. Therefore, a write to a
port implies that the port pins are read, this value is
modified and then written to the PORT data latch
(LATE). RE3 reads ‘0’ when MCLRE = 1.
11.9.2 DIRECTION CONTROL
The TRISE register (Register 11-35) controls the
PORTE pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits in
the TRISE register are maintained set when using them
as analog inputs. I/O pins configured as analog inputs
always read ‘0’.
11.9.3 INPUT THRESHOLD CONTROL
The INLVLE register (Register 11-41) controls the input
voltage threshold for each of the available PORTE
input pins. A selection between the Schmitt Trigger
CMOS or the TTL Compatible thresholds is available.
The input threshold is important in determining the
value of a read of the PORTE register and also the level
at which an interrupt-on-change occurs, if that feature
is enabled. See Table 36-4: I/O Ports for more informa-
tion on threshold levels.
11.9.4 OPEN-DRAIN CONTROL(1)
The ODCONE register (Register 11-39) controls the
open-drain feature of the port. Open-drain operation is
independently selected for each pin. When an
ODCONE bit is set, the corresponding port output
becomes an open-drain driver capable of sinking
current only. When an ODCONE bit is cleared, the
corresponding port output pin is the standard push-pull
drive capable of sourcing and sinking current.
11.9.5 SLEW RATE CONTROL(1)
The SLRCONE register (Register 11-40) controls the
slew rate option for each port pin. Slew rate control is
independently selectable for each port pin. When an
SLRCONE bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCONE bit is cleared,
The corresponding port pin drive slews at the maximum
rate possible.
11.9.6 ANALOG CONTROL(1)
The ANSELE register (Register 11-37) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELE bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELE bits has no effect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
The TRISE register (Register 11-35) controls the PORTE
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISE register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
Note: The RE<2:0>, TRISE<2:0>, INLVL<2:0>
and WPUE<2:0> pins are available on
PIC16(L)F1777/9 only.
Note: Changing the input threshold selection
should be performed while all peripheral
modules are disabled. Changing the
threshold level during the time a module is
active may inadvertently generate a
transition associated with an input pin,
regardless of the actual voltage level on
that pin.
Note 1: Implemented on PIC16(L)F1777/9 only.
Note 1: Implemented on PIC16(L)F1777/9 only.
Note 1: Implemented on PIC16(L)F1777/9 only.
2: The ANSELE bits default to the Analog
mode after Reset. To use any pins as dig-
ital general purpose or peripheral inputs,
the corresponding ANSEL bits must be
initialized to ‘0’ by user software.
PIC16(L)F1777/8/9
DS40001819B-page 198 2015-2016 Microchip Technology Inc.
11.9.7 PORTE FUNCTIONS AND OUTPUT
PRIORITIES
Each pin defaults to the PORT latch data after Reset.
Other functions are selected with the peripheral pin
select logic. See Section 12.0 “Peripheral Pin Select
(PPS) Module” for more information.
Analog input functions, such as ADC and comparator
inputs, are not shown in the peripheral pin select lists.
These inputs are active when the I/O pin is set for Analog
mode using the ANSELE register. Digital output
functions may continue to control the pin when it is in
Analog mode.
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11.10 Regis t er D e finiti o n s : P O R T E
REGISTER 11-34: PORTE: PORTE REGISTER
U-0 U-0 U-0 U-0 R-x/u R/W-x/u R/W-x/u R/W-x/u
— — — — RE3 RE2(1) RE1(1) RE0(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 RE<3:0>: PORTE I/O Pin bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1: RE<2:0> are not implemented on the PIC16(L)F1778. Read as ‘0’. Writes to RE<2:0> are actually written
to corresponding LATE register. Reads from PORTE register is the return of actual I/O pin values.
REGISTER 11-35: TRISE: PORTE TRI-STATE REGISTER
U-0 U-0 U-0 U-0 U-1(2) R/W-1 R/W-1 R/W-1
— — — — — TRISE2(1) TRISE1(1) TRISE0(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 Unimplemented: Read as ‘0’
bit 3 Unimplemented: Read as ‘1’
bit 2-0 TRISE<2:0>: RE<2:0> Tri-State Control bits(1)
1 = PORTE pin configured as an input (tri-stated)
0 = PORTE pin configured as an output
Note 1: TRISE<2:0> are not implemented on the PIC16(L)F1778.
2: Unimplemented, read as ‘1’.
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REGISTER 11-36: LATE: PORTE DATA LATCH REGISTER(1)
U-0 U-0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u
— — — — — LATE2 LATE1 LATE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-3 Unimplemented: Read as ‘0’
bit 2-0 LATE<2:0>: PORTE Output Latch Value bits
Note 1: The LATE register is not implemented on the PIC16(L)F1778. Writes to RE<2:0> are actually written to
corresponding LATE register. Reads from PORTE register is the return of actual I/O pin values.
REGISTER 11-37: ANSELE: PORTE ANALOG SELECT REGISTER(2)
U-0 U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1
— — — — — ANSE2 ANSE1 ANSE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-3 Unimplemented: Read as ‘0’
bit 2-0 ANSE<2:0>: Analog Select between Analog or Digital Function on pins RE<2:0>(1)
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
2: The ANSELE register is not implemented on the PIC16(L)F1778.
2015-2016 Microchip Technology Inc. DS40001819B-page 201
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REGISTER 11-38: WPUE: WEAK PULL-UP PORTE REGISTER
U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — — — WPUE3 WPUE2(3) WPUE1(3) WPUE0(3)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 WPUE<3:0>: Weak Pull-up Register bit(3)
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
3: WPUE<2:0> is not implemented on the PIC16(L)F1778.
REGISTER 11-39: ODCONE: PORTE OPEN-DRAIN CONTROL REGISTER(1)
U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — — ODE2 ODE1 ODE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-3 Unimplemented: Read as ‘0’
bit 2-0 ODE<2:0>: PORTE Open-Drain Enable bits
For RE<2:0> pins
1 = Port pin operates as open-drain drive (sink current only)
0 = Port pin operates as standard push-pull drive (source and sink current)
Note 1: The ODCONE register is not implemented on the PIC16(L)F1778.
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DS40001819B-page 202 2015-2016 Microchip Technology Inc.
TABLE 11-7: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
REGISTER 11-40: SLRCONE: PORTE SLEW RATE CONTROL REGISTER(1)
U-0 U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1
— — — — — SLRE2 SLRE1 SLRE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-3 Unimplemen ted: Read as ‘0’
bit 2-0 SLRE<2:0>: PORTE Slew Rate Enable bits
For RE<2:0> pins
1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate
Note 1: The SLRCONE register is not implemented on the PIC16(L)F1778.
REGISTER 11-41: INLVLE: PORTE INPUT LEVEL CONTROL REGISTER
U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — — — INLVLE3 INLVLE2(1) INLVLE1(1) INLVLE0(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 Unimplemen ted: Read as ‘0’
bit 3-0 INLVLE<3:0>: PORTE Input Level Select bit
1 = ST input used for PORT reads and interrupt-on-change
0 = TTL input used for PORT reads and interrupt-on-change
Note 1: INLVLE<2:0> are not implemented on the PIC16(L)F1778.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ANSELE(2) ———— — ANSELE2 ANSELE1 ANSELE0 200
INLVLE ———— INLVLE3 INLVLE2(2) INLVLE1(2) INLVLE0(2) 202
LATE(2) ———— — LATE2 LATE1 LATE0 200
ODCONE(2) ———— — ODE2 ODE1 ODE0 201
PORTE ————RE3RE2
(2) RE1(2) RE0(2) 199
SLRCONE(2) ———— — SLRE2 SLRE1 SLRE0 202
TRISE —————(1) TRISE2(2) TRISE1(2) TRISE0(2) 199
WPUE ———— WPUE3 WPUE2(2) WPUE1(2) WPUE0(2) 201
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1777/9 only.
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12.0 PERIPHERAL PIN S ELECT
(PPS) MODULE
The Peripheral Pin Select (PPS) module connects
peripheral inputs and outputs to the device I/O pins.
Only digital signals are included in the selections. All
analog inputs and outputs remain fixed to their
assigned pins. Input and output selections are
independent as shown in the simplified block diagram
Figure 12-1.
12.1 PPS Inputs
Each peripheral has a PPS register with which the
inputs to the peripheral are selected. Inputs include the
device pins.
Multiple peripherals can operate from the same source
simultaneously. Port reads always return the pin level
regardless of peripheral PPS selection. If a pin also has
associated analog functions, the ANSEL bit for that pin
must be cleared to enable the digital input buffer.
Although every peripheral has its own PPS input selec-
tion register, the selections are identical for every
peripheral as shown in Register 12-1.
12.2 PPS Outputs
Each I/O pin has a PPS register with which the pin
output source is selected. With few exceptions, the port
TRIS control associated with that pin retains control
over the pin output driver. Peripherals that control the
pin output driver as part of the peripheral operation will
override the TRIS control as needed. These
peripherals include:
• EUSART (synchronous operation)
• MSSP (I2C)
• COG (auto-shutdown)
Although every pin has its own PPS peripheral
selection register, the selections are identical for every
pin as shown in Register 12-2.
FIGURE 12-1: SIMPL I FI ED PPS BLOCK DIAGRAM
Note: The notation “xxx” in the register name is
a place holder for the peripheral identifier.
For example, CLC1PPS.
Note: The notation “Rxy” is a place holder for the
pin identifier. For example, RA0PPS.
RA0
Rxy
RA0PPS
RxyPPS
RC7
RC7PPS
PPS Outputs
PPS Inputs
Peripheral abc
Peripheral xyz
abcPPS
xyzPPS
RA0
RC7
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12.3 Bidirectional Pins
PPS selections for peripherals with bidirectional
signals on a single pin must be made so that the PPS
input and PPS output select the same pin. Peripherals
that have bidirectional signals include:
• EUSART (synchronous operation)
• MSSP (I2C)
12.4 PPS Lock
The PPS includes a mode in which all input and output
selections can be locked to prevent inadvertent
changes. PPS selections are locked by setting the
PPSLOCKED bit of the PPSLOCK register. Setting and
clearing this bit requires a special sequence as an extra
precaution against inadvertent changes. Examples of
setting and clearing the PPSLOCKED bit are shown in
Example 12-1.
EXAMPLE 12-1: PPS LOCK/UNLOCK
SEQUENCE
12.5 PPS Permanent Lock
The PPS can be permanently locked by setting the
PPS1WAY Configuration bit. When this bit is set, the
PPSLOCKED bit can only be cleared and set one time
after a device Reset. This allows for clearing the
PPSLOCKED bit so that the input and output selections
can be made during initialization. When the
PPSLOCKED bit is set after all selections have been
made, it will remain set and cannot be cleared until after
the next device Reset event.
12.6 Operation During Sleep
PPS input and output selections are unaffected by
Sleep.
12.7 Effects of a Reset
A device Power-on Reset (POR) clears all PPS input
and output selections to their default values. All other
Resets leave the selections unchanged. Default input
selections are shown in Table 12-1.
Note: The I2C default input pins are I2C and
SMBus compatible and are the only pins
on the device with this compatibility.
; suspend interrupts
bcf INTCON,GIE
; BANKSEL PPSLOCK ; set bank
; required sequence, next 5 instructions
movlw 0x55
movwf PPSLOCK
movlw 0xAA
movwf PPSLOCK
; Set PPSLOCKED bit to disable writes or
; Clear PPSLOCKED bit to enable writes
bsf PPSLOCK,PPSLOCKED
; restore interrupts
bsf INTCON,GIE
2015-2016 Microchip Technology Inc. DS40001819B-page 205
PIC16(L)F1777/8/9
12.8 Register Definitions: PPS Input S election
REGISTER 12-1: xxxPPS: PERIPHERAL xxx INPUT SELECTION
U-0 U-0 R/W-q/u R/W-q/u R/W-q/u R/W-q/u R/W-q/u R/W-q/u
—— xxxPPS<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on peripheral
bit 7-6 Unimplemented: Read as ‘0’
bit 5-3 xxxPPS<5:3>: Peripheral xxx Input PORT Selection bits
100 = Peripheral input is PORTE
011 = Peripheral input is PORTD(1)
010 = Peripheral input is PORTC
001 = Peripheral input is PORTB
000 = Peripheral input is PORTA
bit 2-0 xxxPPS<2:0>: Peripheral xxx Input Bit Selection bits(1)
111 = Peripheral input is from PORTx Bit 7 (Rx7)
110 = Peripheral input is from PORTx Bit 6 (Rx6)
101 = Peripheral input is from PORTx Bit 5 (Rx5)
100 = Peripheral input is from PORTx Bit 4 (Rx4)
011 = Peripheral input is from PORTx Bit 3 (Rx3)
010 = Peripheral input is from PORTx Bit 2 (Rx2)
001 = Peripheral input is from PORTx Bit 1 (Rx1)
000 = Peripheral input is from PORTx Bit 0 (Rx0)
Note 1: See Table 12-1 for xxxPPS register list and Reset values.
2: PIC16(L)F1777/9 only.
REGISTER 12-2: RxyPPS: PIN Rxy OUTPUT SOURCE SELECTION REGISTER
U-0 U-0 R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u
—— RxyPPS<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RxyPPS<5:0>: Pin Rxy Output Source Selection bits
Selection code determines the output signal on the port pin.
See Table 12-2 for the selection codes
PIC16(L)F1777/8/9
DS40001819B-page 206 2015-2016 Microchip Technology Inc.
REGISTER 12-3: PPSLOCK: PPS LOCK REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0
——————— PPSLOCKED
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-1 Unimplemented: Read as ‘0’
bit 0 PPSLOCKED: PPS Locked bit
1 = PPS is locked. PPS selections can not be changed.
0 = PPS is not locked. PPS selections can be changed.
2015-2016 Microchip Technology Inc. DS40001819B-page 207
PIC16(L)F1777/8/9
TABLE 12-1: PPS INPUT REGISTER RESET VALUES
Peripheral xxxPPS
Register
Default Pin
Selection Reset Value
(xxxPPS<5:0>) Port Selection
PIC16(L)F1777/9 Port Selection
PIC16(L)F1778
PIC16(L)F1777/8/9 PIC16(L)F1777/8/9 A B C D E A B C
Interrupt-on-change INTPPS RB0 001000  
Timer0clock T0CKIPPS RA4 000100  
Timer1clock T1CKIPPS RC0 010000  
Timer1 gate T1GPPS RB5 001101  
Timer3 clock T3CKIPPS RC0 010000  
Timer3 gate T3GPPS RC0 010000  
Timer5 clock T5CKIPPS RC2 010010  
Timer5 gate T5GPPS RB4 001100 
Timer2 input T2INPPS RC3 010011  
Timer4 input T4INPPS RC5 010101  
Timer6 input T6INPPS RB7 001111 
Timer8 input T8INPPS RC4 010100 
CCP1 CCP1PPS RC2 010010  
CCP2 CCP2PPS RC1 010001  
CCP7 CCP7PPS RB5 001101 
CCP8(1) CCP8PPS RB0 001000 
COG1 COG1INPPS RB0 001000 
COG2 COG2INPPS RB1 001001 
COG3 COG3INPPS RB2 001010 
COG4(1) COG4INPPS RB3 001011 
DSM1 low carrier MD1CLPPS RA3 000011 
DSM1 high carrier MD1CHPPS RA4 000100 
DSM1 modulation MD1MODPPS RA5 000101 
DSM2 low carrier MD2CLPPS RC3 010011 
DSM2 high carrier MD2CHPPS RC4 010100 
DSM2 modulation MD2MODPPS RC5 010101 
DSM3 low carrier MD3CLPPS RB3 001011 
DSM3 high carrier MD3CHPPS RB4 001100 
DSM3 modulation MD3MODPPS RB5 001101 
DSM4 low carrier(1) MD4CLPPS RB0 001000 
DSM4 high carrier(1) MD4CHPPS RB1 001001 
DSM4 modulation(1) MD4MODPPS RB2 001010 
PRG1 set rising PRG1RPPS RA4 000100 
PRG1 set falling PRG1FPPS RA5 000101 
PRG2 set rising PRG2RPPS RC1 010001 
PRG2 set falling PRG2FPPS RC2 010010 
PRG3 set rising PRG3RPPS RC4 010100 
PRG3 set falling PRG3FPPS RC5 010101 
PRG4 set rising(1) PRG4RPPS RB1 010100 
PRG4set falling(1) PRG4FPPS RB2 010101 
ADC trigger ADCACTPPS RB4 001100 
Example: CCP1PPS = 0x13 selects RC3 as the CCP1 input.
Note 1: PIC16(L)F1777/9 only
PIC16(L)F1777/8/9
DS40001819B-page 208 2015-2016 Microchip Technology Inc.
SPI and I2C clock SSPCLKPPS RC3 010011  
SPI and I2C data SSPDATPPS RC4 010100  
SPI slave select SSPSSPPS RA5 000101 
EUSART RX RXPPS RC7 010111  
EUSART CK CKPPS RC6 010110  
All CLCs CLCIN0PPS RA0 000000  
All CLCs CLCIN1PPS RA1 000001  
All CLCs CLCIN2PPS RB6 001110 
All CLCs CLCIN3PPS RB7 001111 
TA BLE 12-1: PPS INPUT REGISTER RESET VALUES (CONTINUED)
Peripheral xxxPPS
Register
Default Pin
Selection Reset Value
(xxxPPS<5:0>) Port Selection
PIC16(L)F1777/9 Port Selection
PIC16(L)F1778
PIC16(L)F1777/8/9 PIC16(L)F1777/8/9 A B C D E A B C
Example: CCP1PPS = 0x13 selects RC3 as the CCP1 input.
Note 1: PIC16(L)F1777/9 only
2015-2016 Microchip Technology Inc. DS40001819B-page 209
PIC16(L)F1777/8/9
TABLE 12-2: AVAILABLE PORTS FOR OUTPUT BY PERIPHERAL(2)
RxyPPS<5:0> Output Signal PIC16(L)F1778 PIC16(L)F1777/9
ABCABCDE
110001 MD4_out(3) ——
110000 MD3_out ———
101111 MD2_out —— —
101110 MD1_out —— —
101101 sync_C8OUT(3) ———
101100 sync_C7OUT(3) ———
101011 sync_C6OUT ———
101010 sync_C5OUT —— —
101001 sync_C4OUT ———
101000 sync_C3OUT ———
100111 sync_C2OUT ——
100110 sync_C1OUT —— —
100101 DT ———
100100 TX/CK ———
100011 SDO ———
100010 SDA ———
100001 SCK/SCL(1) ———
100000 PWM12_out(3) ———
011111 PWM11_out ———
011110 PWM6_out —— —
011101 PWM5_out ——
011100 PWM10_out(3) ———
011011 PWM9_out ——
011010 PWM4_out ——
011001 PWM3_out ——
011000 CCP8_out(3) ———
010111 CCP7_out ———
010110 CCP2_out ———
010101 CCP1_out ———
010100 COG4D(1,3) ——
010011 COG4C(1,3) ——
010010 COG4B(1,3) ——
010001 COG4A(1,3) ——
010000 COG3D(1) —— —
001111 COG3C(1) —— —
001110 COG3B(1) ———
001101 COG3A(1) ———
001100 COG2D(1) ———
001011 COG2C(1) ———
001010 COG2B(1) 
Note 1: TRIS control is overridden by the peripheral as required.
2: Unsupported peripherals will output a ‘0’.
3: PIC16(L)F1777/9 only.
PIC16(L)F1777/8/9
DS40001819B-page 210 2015-2016 Microchip Technology Inc.
001001 COG2A(1)  
001000 COG1D(1) 
000111 COG1C(1) 
000110 COG1B(1) 
000101 COG1A(1)  
000100 LC4_out 
000011 LC3_out 
000010 LC2_out 
000001 LC1_out 
000000 LATxy 
TABLE 12-2: AVAILABLE PORTS FOR OUTPUT BY PERIPHERAL(2) (CONTINUED)
RxyPPS<5:0> Output Signal PIC16(L)F1778 PIC16(L)F1777/9
ABCABCDE
Note 1: TRIS control is overridden by the peripheral as required.
2: Unsupported peripherals will output a ‘0’.
3: PIC16(L)F1777/9 only.
2015-2016 Microchip Technology Inc. DS40001819B-page 211
PIC16(L)F1777/8/9
TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE
Name Bit 7 Bit 6 B it 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on page
PPSLOCK — — — — — — —PPSLOCKED 206
INTPPS — — INTPPS<5:0> 205
T0CKIPPS — — T0CKIPPS<5:0> 205
T1CKIPPS — — T1CKIPPS<5:0> 205
T1GPPS — — T1GPPS<5:0> 205
T3CKIPPS — — T3CKIPPS<5:0> 205
T3GPPS — — T3GPPS<5:0> 205
T5CKIPPS — — T5CKIPPS<5:0> 205
T5GPPS — — T5GPPS<5:0> 205
T2INPPS — — T2INPPS<5:0> 205
T4INPPS — — T4INPPS<5:0> 205
T6INPPS — — T6INPPS<5:0> 205
T8INPPS — — T8INPPS<5:0> 205
CCP1PPS — — CCP1PPS<5:0> 205
CCP2PPS — — CCP2PPS<5:0> 205
CCP7PPS — — CCP7PPS<5:0> 205
CCP8PPS(1) — — CCP8PPS<5:0> 205
COGIN1PPS — — COG1PPS<5:0> 205
COG2INPPS — — COG2PPS<5:0> 205
COG3INPPS — — COG3PPS<5:0> 205
COG4INPPS(1) — — COG4PPS<5:0> 205
MD1CLPPS — — MD1CLPPS<5:0> 205
MD1CHPPS — — MD1CHPPS<5:0> 205
MD1MODPPS — — MD1MODPPS<5:0> 205
MD2CLPPS — — MD2CLPPS<5:0> 205
MD2CHPPS — — MD2CHPPS<5:0> 205
MD2MODPPS — — MD2MODPPS<5:0> 205
MD3CLPPS — — MD3CLPPS<5:0> 205
MD3CHPPS — — MD3CHPPS<5:0> 205
MD3MODPPS — — MD3MODPPS<5:0> 205
MD4CLPPS(1) — — MD4CLPPS<5:0> 205
MD4CHPPS(1) — — MD4CHPPS<5:0> 205
MD4MODPPS(1) — — MD4MODPPS<5:0> 205
PRG1RPPS — — PRG1RPPS<5:0> 205
PRG1FPPS — — PRG1FPPS<5:0> 205
PRG2RPPS — — PRG2RPPS<5:0> 205
PRG2FPPS — — PRG2FPPS<5:0> 205
PRG3RPPS — — PRG3RPPS<5:0> 205
PRG3FPPS — — PRG3FPPS<5:0> 205
PRG4RPPS — — PRG4RPPS<5:0> 205
PRG4FPPS — — PRG4FPPS<5:0> 205
CLC1IN0PPS — — CLCIN0PPS<5:0> 205
PIC16(L)F1777/8/9
DS40001819B-page 212 2015-2016 Microchip Technology Inc.
CLC1IN1PPS — — CLCIN1PPS<5:0> 205
CLC1IN2PPS — — CLCIN2PPS<5:0> 205
CLC1IN3PPS — — CLCIN3PPS<5:0> 205
ADCACTPPS — — ADCACTPPS<5:0> 205
SSPCLKPPS — — SSPCLKPPS<5:0> 205
SSPDATPPS — — SSPDATPPS<5:0> 205
SSPSSPPS — — SSPSSPPS<5:0> 205
RXPPS — — RXPPS<5:0> 205
CKPPS — — CKPPS<5:0> 205
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the PPS module.
Note 1: PIC16(L)F1777/9 only.
TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE (CONTINUED)
Name Bit 7 Bit 6 B it 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on page
2015-2016 Microchip Technology Inc. DS40001819B-page 213
PIC16(L)F1777/8/9
13.0 INTERRUPT-ON-CHANGE
All pins on all ports can be configured to operate as
Interrupt-on-Change (IOC) pins. An interrupt can be
generated by detecting a signal that has either a rising
edge or a falling edge. Any individual pin, or combination
of pins, can be configured to generate an interrupt. The
interrupt-on-change module has the following features:
• Interrupt-on-Change enable (Master Switch)
• Individual pin configuration
• Rising and falling edge detection
• Individual pin interrupt flags
Figure 13-1 is a block diagram of the IOC module.
13.1 Enabling the Module
To allow individual pins to generate an interrupt, the
IOCIE bit of the INTCON register must be set. If the
IOCIE bit is disabled, the edge detection on the pin will
still occur, but an interrupt will not be generated.
13.2 Individual Pin Configuration
For each pin, a rising edge detector and a falling edge
detector are present. To enable a pin to detect a rising
edge, the associated bit of the IOCxP register is set. To
enable a pin to detect a falling edge, the associated bit
of the IOCxN register is set.
A pin can be configured to detect rising and falling
edges simultaneously by setting the associated bits in
both of the IOCxP and IOCxN registers.
13.3 Interrupt Flags
The bits located in the IOCxF registers are status flags
that correspond to the Interrupt-on-Change pins of each
port. If an expected edge is detected on an appropriately
enabled pin, then the status flag for that pin will be set,
and an interrupt will be generated if the IOCIE bit is set.
The IOCIF bit of the INTCON register reflects the status
of all IOCxF bits.
13.4 Clearing Interrupt Flags
The individual status flags, (IOCxF register bits), can be
cleared by resetting them to zero. If another edge is
detected during this clearing operation, the associated
status flag will be set at the end of the sequence,
regardless of the value actually being written.
In order to ensure that no detected edge is lost while
clearing flags, only AND operations masking out known
changed bits should be performed. The following
sequence is an example of what should be performed.
EXAMPLE 13-1: CLEARING INTERRUPT
FLAGS
(PORTA EXAMPLE)
13.5 Operation in Sleep
The Interrupt-on-Change interrupt sequence will wake
the device from Sleep mode, if the IOCIE bit is set.
If an edge is detected while in Sleep mode, the affected
IOCxF register will be updated prior to the first instruction
executed out of Sleep.
MOVLW 0xff
XORWF IOCAF, W
ANDWF IOCAF, F
PIC16(L)F1777/8/9
DS40001819B-page 214 2015-2016 Microchip Technology Inc.
FIGURE 13-1: INTERRUP T-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE)
IOCANx
IOCAPx
Q2
Q4Q1
data bus =
0 or 1
write IOCAFx
IOCIE
to data bus
IOCAFx
edge
detect
IOC interrupt
to CPU core
from all other
IOCnFx individual
pin detectors
DQ
S
DQ
R
DQ
R
RAx
Q1
Q2
Q3
Q4
Q4Q1
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q4Q1 Q4Q1Q4Q1
FOSC
Rev . 10-000 037A
6/2/201 4
2015-2016 Microchip Technology Inc. DS40001819B-page 215
PIC16(L)F1777/8/9
13.6 Register Definitions: Interrupt -on-Change Control
REGISTER 13-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 IOCAP<7:0>: Interrupt-on-Change PORTA Positive Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCAFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
REGISTER 13-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 IOCAN<7:0>: Interrupt-on-Change PORTA Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCAFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
PIC16(L)F1777/8/9
DS40001819B-page 216 2015-2016 Microchip Technology Inc.
REGISTER 13-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware
bit 7-0 IOCAF<7:0>: Interrupt-on-Change PORTA Flag bits
1 = An enabled change was detected on the associated pin.
Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling
edge was detected on RAx.
0 = No change was detected, or the user cleared the detected change.
REGISTER 13-4: IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 IOCBP<7:0>: Interrupt-on-Change PORTB Positive Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCBFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
REGISTER 13-5: IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 IOCBN<7:0>: Interrupt-on-Change PORTB Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCBFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
2015-2016 Microchip Technology Inc. DS40001819B-page 217
PIC16(L)F1777/8/9
REGISTER 13-6: IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware
bit 7-0 IOCBF<7:0>: Interrupt-on-Change PORTB Flag bits
1 = An enabled change was detected on the associated pin.
Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling
edge was detected on RBx.
0 = No change was detected, or the user cleared the detected change.
PIC16(L)F1777/8/9
DS40001819B-page 218 2015-2016 Microchip Technology Inc.
REGISTER 13-7: IOCCP: INTERRUPT-ON-CHANGE PORTC POSITIVE EDGE REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 IOCCP<7:0>: Interrupt-on-Change PORTC Positive Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCCFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
REGISTER 13-8: IOCCN: INTERRUPT-ON-CHANGE PORTC NEGATIVE EDGE REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 IOCCN<7:0>: Interrupt-on-Change PORTC Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCCFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
REGISTER 13-9: IOCCF: INTERRUPT-ON-CHANGE PORTC FLAG REGISTER
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware
bit 7-0 IOCCF<7:0>: Interrupt-on-Change PORTC Flag bits
1 = An enabled change was detected on the associated pin.
Set when IOCCPx = 1 and a rising edge was detected on RCx, or when IOCCNx = 1 and a falling
edge was detected on RCx.
0 = No change was detected, or the user cleared the detected change.
2015-2016 Microchip Technology Inc. DS40001819B-page 219
PIC16(L)F1777/8/9
REGISTER 13-10: IOCEP: INTERRUPT-ON-CHANGE PORTE POSITIVE EDGE REGISTER
U-0 U-0 U-0 U-0 R/W-0/0 U-0 U-0 U-0
— — — — IOCEP3 — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 Unimplemented: Read as ‘0’
bit 3 IOCEP3: Interrupt-on-Change PORTE Positive Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCEFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
bit 2-0 Unimplemented: Read as ‘0’
REGISTER 13-11: IOCEN: INTERRUPT-ON-CHANGE PORTE NEGATIV E EDGE REGISTER
U-0 U-0 U-0 U-0 R/W-0/0 U-0 U-0 U-0
— — — —IOCEN3 — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 Unimplemented: Read as ‘0’
bit 3 IOCEN3: Interrupt-on-Change PORTE Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCEFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
bit 2-0 Unimplemented: Read as ‘0’
PIC16(L)F1777/8/9
DS40001819B-page 220 2015-2016 Microchip Technology Inc.
TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
REGISTER 13-12: IOCEF: INTERRUPT-ON-CHANGE PORTE FLAG REGISTER
U-0 U-0 U-0 U-0 R/W/HS-0/0 U-0 U-0 U-0
— — — —IOCEF3 — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware
bit 7-4 Unimplemented: Read as ‘0’
bit 3 IOCEF3: Interrupt-on-Change PORTE Flag bits
1 = An enabled change was detected on the associated pin.
Set when IOCEPx = 1 and a rising edge was detected on REx, or when IOCENx = 1 and a falling
edge was detected on REx.
0 = No change was detected, or the user cleared the detected change.
bit 2-0 Unimplemented: Read as ‘0’
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ANSELA —— ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177
ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182
ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 187
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132
IOCAF IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 216
IOCAN IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 215
IOCAP IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 215
IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 217
IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 216
IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 216
IOCCF IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 218
IOCCN IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 218
IOCCP IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 218
IOCEP — — — — IOCEP3 ———219
IOCEN — — — —IOCEN3———219
IOCEF — — — —IOCEF3———220
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186
TRISE — — — — —(1) TRISE2(2) TRISE1(2) TRISE0(2) 199
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change.
Note 1: Unimplemented, read as ‘1’.
2: Unimplemented on PIC16(L)F1778.
2015-2016 Microchip Technology Inc. DS40001819B-page 221
PIC16(L)F1777/8/9
14.0 FIXED VOLTAGE REFERENCE
(FVR)
The Fixed Voltage Reference, or FVR, is a stable
voltage reference, independent of VDD, with 1.024V,
2.048V or 4.096V selectable output levels. The output
of the FVR can be configured to supply a reference
voltage to the following:
• ADC input channel
• ADC positive reference
• Comparator positive input
• Digital-to-Analog Converter (DAC)
The FVR can be enabled by setting the FVREN bit of
the FVRCON register.
14.1 Independent Gain Amplifiers
The output of the FVR supplied to the ADC,
Comparators, and DAC is routed through two
independent programmable gain amplifiers. Each
amplifier can be programmed for a gain of 1x, 2x or 4x,
to produce the three possible voltage levels.
The ADFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the ADC module.
Reference Section 16.0 “Analog-to-Digital Con-
verter (ADC) Module” for additional information.
The CDAFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the DAC and comparator
module. Reference Section 17.0 “5-Bit Digi-
tal-to-Analog Converter (DAC) Module” and
Section 19.0 “Comparator Module” for additional
information.
14.2 FVR Stabilization Period
When the Fixed Voltage Reference module is enabled, it
requires time for the reference and amplifier circuits to
stabilize. Once the circuits stabilize and are ready for use,
the FVRRDY bit of the FVRCON register will be set. See
Figure 37-77: FVR Stabilization Period,
PIC16LF1777/8/9 Only..
14.3 FVR Buffer Stabilization Period
When either FVR Buffer1 or Buffer2 is enabled then the
buffer amplifier circuits require 30 s to stabilize.This
stabilization time is required even when the FVR is
already operating and stable.
PIC16(L)F1777/8/9
DS40001819B-page 222 2015-2016 Microchip Technology Inc.
FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM
ADFVR<1:0>
CDA1FVR<1:0>
X1
X2
X4
X1
X2
X4
2
2
ADFVR
(To ADC Module)
CDA1FVR
(To Comparators, DAC)
+
_
FVREN FVRRDY
Any peripheral requiring the
Fixed Reference
(See Table 14-1)
To B OR, L DO
HFINTOSC Enable
HFINTOSC
CDA2FVR<1:0>
X1
X2
X4
2
CDA2FVR
(To Comparators, DAC)
TABLE 14-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR)
Peripheral Conditions Description
HFINTOSC FOSC<2:0> = 100 and
IRCF<3:0> 000x INTOSC is active and device is not in Sleep
BOR
BOREN<1:0> = 11 BOR always enabled
BOREN<1:0> = 10 and BORFS = 1BOR disabled in Sleep mode, BOR Fast Start enabled
BOREN<1:0> = 01 and BORFS = 1BOR under software control, BOR Fast Start enabled
LDO All PIC16F1773/6 devices, when
VREGPM = 1 and not in Sleep
The device runs off of the ULP regulator when in Sleep mode
2015-2016 Microchip Technology Inc. DS40001819B-page 223
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14.4 Register Definitions: FVR Control
TABLE 14-2: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE
REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER
R/W-0/0 R-q/q R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
FVREN FVRRDY(1) TSEN(3) TSRNG(3) CDAFVR<1:0> ADFVR<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7 FVREN: Fixed Voltage Reference Enable bit
1 = Fixed Voltage Reference is enabled
0 = Fixed Voltage Reference is disabled
bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
1 = Fixed Voltage Reference output is ready for use
0 = Fixed Voltage Reference output is not ready or not enabled
bit 5 TSEN: Temperature Indicator Enable bit(3)
1 = Temperature Indicator is enabled
0 = Temperature Indicator is disabled
bit 4 TSRNG: Temperature Indicator Range Selection bit(3)
1 =VOUT = VDD - 4VT (High Range)
0 =V
OUT = VDD - 2VT (Low Range)
bit 3-2 CDAFVR<1:0>: Comparator/DAC FVR Buffer Gain Selection bits
11 = Comparator/DAC FVR Buffer Gain is 4x, with output VCDAFVR = 4x VFVR(2)
10 = Comparator/DAC FVR Buffer Gain is 2x, with output VCDAFVR = 2x VFVR(2)
01 = Comparator/DAC FVR Buffer Gain is 1x, with output VCDAFVR = 1x VFVR
00 = Comparator/DAC FVR Buffer is off
bit 1-0 ADFVR<1:0>: ADC FVR Buffer Gain Selection bits
11 = ADC FVR Buffer Gain is 4x, with output VADFVR = 4x VFVR(2)
10 = ADC FVR Buffer Gain is 2x, with output VADFVR = 2x VFVR(2)
01 = ADC FVR Buffer Gain is 1x, with output VADFVR = 1x VFVR
00 = ADC FVR Buffer is off
Note 1: FVRRDY is always ‘1’ on PIC16F1773/6 only.
2: Fixed Voltage Reference output cannot exceed VDD.
3: See Section 15.0 “Temperature Indicator Module” for additional information.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on page
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 223
Legend: Shaded cells are not used with the Fixed Voltage Reference.
PIC16(L)F1777/8/9
DS40001819B-page 224 2015-2016 Microchip Technology Inc.
15.0 TEMPERATURE INDICATOR
MODULE
This family of devices is equipped with a temperature
circuit designed to measure the operating temperature
of the silicon die. The circuit’s range of operating
temperature falls between -40°C and +85°C. The
output is a voltage that is proportional to the device
temperature. The output of the temperature indicator is
internally connected to the device ADC.
The circuit may be used as a temperature threshold
detector or a more accurate temperature indicator,
depending on the level of calibration performed. A one-
point calibration allows the circuit to indicate a
temperature closely surrounding that point. A two-point
calibration allows the circuit to sense the entire range
of temperature more accurately. Reference Application
Note AN1333, “Use and Calibration of the Internal
Temperature Indicator” (DS01333) for more details
regarding the calibration process.
15.1 Circuit Operation
Figure 15-1 shows a simplified block diagram of the
temperature circuit. The proportional voltage output is
achieved by measuring the forward voltage drop across
multiple silicon junctions.
Equation 15-1 describes the output characteristics of
the temperature indicator.
EQUATION 15-1: VOUT RANGES
The temperature sense circuit is integrated with the
Fixed Voltage Reference (FVR) module. See
Section 14.0 “Fixed Voltage Reference (FVR)” for
more information.
The circuit is enabled by setting the TSEN bit of the
FVRCON register. When disabled, the circuit draws no
current.
The circuit operates in either high or low range. The high
range, selected by setting the TSRNG bit of the
FVRCON register, provides a wider output voltage. This
provides more resolution over the temperature range,
but may be less consistent from part to part. This range
requires a higher bias voltage to operate and thus, a
higher VDD is needed.
The low range is selected by clearing the TSRNG bit of
the FVRCON register. The low range generates a lower
voltage drop and thus, a lower bias voltage is needed to
operate the circuit. The low range is provided for low
voltage operation.
FIGURE 15-1: TEMPERATURE CIRCUIT
DIAGRAM
15.2 Minimum Operating VDD
When the temperature circuit is operated in low range,
the device may be operated at any operating voltage
that is within specifications.
When the temperature circuit is operated in high range,
the device operating voltage, VDD, must be high
enough to ensure that the temperature circuit is
correctly biased.
Table 15-1 shows the recommended minimum VDD vs.
range setting.
TABLE 15-1: RECOMMENDED VDD VS.
RANGE
15.3 Temperature Output
The output of the circuit is measured using the internal
Analog-to-Digital Converter. A channel is reserved for
the temperature circuit output. Refer to Section 16.0
“Analog-to-Digital Converter (ADC) Module” for
detailed information.
High Range: VOUT = VDD - 4VT
Low R ange: VOUT = VDD - 2VT
Min. VDD, TSRNG = 1Min. VDD, TSRNG = 0
3.6V 1.8V
VOUT
Temp. Indicator To ADC
TSRNG
TSEN
Rev. 10-000069A
7/31/2013
VDD
2015-2016 Microchip Technology Inc. DS40001819B-page 225
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15.4 ADC Acquisition Time
To ensure accurate temperature measurements, the
user must wait at least 200 s after the ADC input
multiplexer is connected to the temperature indicator
output before the conversion is performed. In addition,
the user must wait 200 s between sequential
conversions of the temperature indicator output.
TABLE 15-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE T E MPERATURE INDICATOR
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on page
FVRCON FVREN FVRRDY TSEN TSRNG CDFVR<1:0> ADFVR<1:0> 223
Legend: Shaded cells are unused by the temperature indicator module.
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DS40001819B-page 226 2015-2016 Microchip Technology Inc.
16.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESH:ADRESL register pair).
Figure 16-1 shows the block diagram of the ADC.
The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
FIGURE 16-1: ADC B LOCK DIAGRAM
VRPOSVRNEG
Enable
DACx_output
FVR_buffer1
Temp Indicator
CHS<4:0>
External
Channel
Inputs
GO/DONE
complete
start
ADC
Sample Circuit
Write to bit
GO/DONE
VSS
VDD
VREF+pin
VDD
ADPREF<1:0>
10-bit Result
ADRESH ADRESL
16
ADFM
10
Internal
Channel
Inputs
AN0
ANa
ANz
set bit ADIF
VSS
ADON
sampled
input
Q1
Q2
Q4
Fosc
Divider FOSC
FOSC/n
FRC
ADC
Clock
Select
ADC_clk
ADCS<2:0>
FRC
ADC CLOCK SOURCE
AUTO CONVERSION
TRIGGER
Positive
Reference
Select
Rev. 10-000033E
6/11/2015
ANb
VREF-pin
ADNREF
Negative
Reference
Select
Trigger Select
Trigger Sources
. . .
TRIGSEL<5:0>
FVR BUFFER
RESERVED
2015-2016 Microchip Technology Inc. DS40001819B-page 227
PIC16(L)F1777/8/9
16.1 ADC Configuration
When configuring and using the ADC the following
functions must be considered:
• Port configuration
• Channel selection
• ADC voltage reference selection
• ADC conversion clock source
• Interrupt control
• Result formatting
16.1.1 PORT CONFIGURATION
The ADC can be used to convert both analog and
digital signals. When converting analog signals, the I/O
pin should be configured for analog by setting the
associated TRIS and ANSEL bits. Refer to
Section 11.0 “I/O Ports” for more information.
16.1.2 CHANNEL SELECTION
There are up to 27 channel selections available:
• AN<4:0> pins (PIC16(L)F1778 only)
• AN<11:8> pins (PIC16(L)F1778 only)
• AN<27:0> pins (PIC16(L)F1777/9 only)
• Temperature Indicator
• DAC1_output and DAC3_output
• DAC2_output and DAC4_output
(PIC16(L)F1777/9 only)
• FVR_buffer1
The CHS bits of the ADCON0 register (Register 16-1)
determine which channel is connected to the sample
and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 16.2
“ADC Operation” for more information.
16.1.3 ADC POSITIVE VOLTAGE
REFERENCE
The ADPREF bits of the ADCON1 register provide
control of the positive voltage reference. The positive
voltage reference can be:
•V
REF+ pin
•V
DD
• FVR 2.048V
• FVR 4.096V (Not available on LF devices)
•V
SS
See Section 16.0 “Analog-to-Digital Converter
(ADC) Module” for more details on the Fixed Voltage
Reference.
16.1.4 ADC NEGATIVE VOLTAGE
REFERENCE
The ADNREF bit of the ADCON1 register provides
control of the negative voltage reference. The negative
voltage reference can be:
•V
REF- pin
•VSS
16.1.5 CONVERSION CLOCK
The source of the conversion clock is software select-
able via the ADCS bits of the ADCON1 register. There
are seven possible clock options:
•F
OSC/2
•F
OSC/4
•FOSC/8
•F
OSC/16
•F
OSC/32
•FOSC/64
• FRC (internal RC oscillator)
The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 11.5 TAD
periods as shown in Figure 16-2.
For correct conversion, the appropriate TAD specification
must be met. Refer to Table 36-16: ADC Conversion
Requirements for more information. Table 16-1 gives
examples of appropriate ADC clock selections.
Note: Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
Note: Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
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DS40001819B-page 228 2015-2016 Microchip Technology Inc.
TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
FIGURE 16-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
ADC Clock Period (TAD) Device Frequency (FOSC)
ADC
Clock Source ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz
FOSC/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s
FOSC/4 100 125 ns(2) 200 ns(2) 250 ns(2) 500 ns(2) 1.0 s4.0 s
FOSC/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) 1.0 s2.0 s8.0 s(3)
FOSC/16 101 800 ns 800 ns 1.0 s2.0 s4.0 s16.0 s(3)
FOSC/32 010 1.0 s1.6 s2.0 s4.0 s8.0 s(3) 32.0 s(2)
FOSC/64 110 2.0 s3.2 s4.0 s8.0 s(3) 16.0 s(2) 64.0 s(2)
FRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: See TAD parameter for FRC source typical TAD value.
2: These values violate the required TAD time.
3: Outside the recommended TAD time.
4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the
system clock FOSC. However, the FRC oscillator source must be used when conversions are to be performed with the
device in Sleep mode.
TAD1TAD2TAD3TAD4TAD5TAD6TAD7TAD8TAD9TAD10 TAD11
SetGObit
Conversion Starts
Holding capacitor disconnected
from analog input (THCD).
On the following cycle:
ADRESH:ADRESL is loaded,
GO bit is cleared,
ADIF bit is set,
holding capacitor is reconnected to analog input.
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Enable ADC (ADON bit)
and
Select channel (ACS bits)
THCD
TACQ
Rev. 10-000035A
7/30/2013
2015-2016 Microchip Technology Inc. DS40001819B-page 229
PIC16(L)F1777/8/9
16.1.6 INTERRUPTS
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC Interrupt Flag is the ADIF bit in
the PIR1 register. The ADC Interrupt Enable is the
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the ADIE bit of the PIE1 register and the
PEIE bit of the INTCON register must both be set and
the GIE bit of the INTCON register must be cleared. If
all three of these bits are set, the execution will switch
to the Interrupt Service Routine.
16.1.7 RESULT FORMATTING
The 10-bit ADC conversion result can be supplied in
two formats, left justified or right justified. The ADFM bit
of the ADCON1 register controls the output format.
Figure 16-3 shows the two output formats.
FIGURE 16-3: 10-BIT ADC CONVERSION RESULT FORMAT
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
MSB
MSB
LSB
LSB
(ADFM = 0)
(ADFM = 1)
bit 7 bit 7
bit 7bit 7
bit 0
bit 0
bit 0
bit 0
10-bit ADC Result
10-bit ADC Result
Unimplemented: Read as ‘0’
Unimplemented: Read as ‘0’
ADRESH ADRESL
Rev. 10-000054A
7/30/2013
PIC16(L)F1777/8/9
DS40001819B-page 230 2015-2016 Microchip Technology Inc.
16.2 ADC Operation
16.2.1 STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the
GO/DONE bit of the ADCON0 register to a ‘1’ will start
the Analog-to-Digital conversion.
16.2.2 COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF Interrupt Flag bit
• Update the ADRESH and ADRESL registers with
new conversion result
16.2.3 TERMINATING A CONVERSION
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared in software. The
ADRESH and ADRESL registers will be updated with
the partially complete Analog-to-Digital conversion
sample. Incomplete bits will match the last bit
converted.
16.2.4 ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC oscillator source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conver-
sion to be aborted and the ADC module is turned off,
although the ADON bit remains set.
16.2.5 AUTO-CONVERSION TRIGGER
The Auto-conversion Trigger allows periodic ADC mea-
surements without software intervention. When a rising
edge of the selected source occurs, the GO/DONE bit
is set by hardware.
The Auto-conversion Trigger source is selected with
the TRIGSEL<5:0> bits of the ADCON2 register.
Using the Auto-conversion Trigger does not assure
proper ADC timing. It is the user’s responsibility to
ensure that the ADC timing requirements are met.
See Table 16-2 for auto-conversion sources.
Note: The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 16.2.6 “ADC Conver-
sion Procedure”.
Note: A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
TABLE 16-2: AUTO-CONVERSION
SOURCES
Source Pe r ipheral Signal Name
CCP1 CCP1_trigger
CCP2 CCP2_trigger
CCP7 CCP7_trigger
CCP8(1) CCP8_trigger
Timer0 T0_overflow
Timer1 T1_overflow
Timer3 T3_overflow
Timer5 T5_overflow
Timer2 T2_postscaled
Timer4 T4_postscaled
Timer6 T6_postscaled
Timer8 T8_postscaled
Comparator C1 sync_C1OUT
Comparator C2 sync_C2OUT
Comparator C3 sync_C3OUT
Comparator C4 sync_C4OUT
Comparator C5 sync_C5OUT
Comparator C6 sync_C6OUT
Comparator C7(1) sync_C7OUT
Comparator C8(1) sync_C8OUT
CLC1 LC1_out
CLC2 LC2_out
CLC3 LC3_out
CLC4 LC4_out
PWM3 PWM3OUT
PWM4 PWM4OUT
PWM9 PWM9OUT
PWM9 PR/PH/OF/DC9_match
PWM5 PR/PH/OF/DC5_match
PWM6 PR/PH/OF/DC6_match
PWM10(1) PR/PH/OF/DC10_match
PWM11 PR/PH/OF/DC11_match
PWM12(1) PR/PH/OF/DC12_match
ADCACT ADCACTPPS Pin
Note 1: PIC16(L)F1777/9 only.
2015-2016 Microchip Technology Inc. DS40001819B-page 231
PIC16(L)F1777/8/9
16.2.6 ADC CONVERSION PROCEDURE
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
1. Configure Port:
• Disable pin output driver (refer to the TRIS
register)
• Configure pin as analog (refer to the ANSEL
register)
• Disable weak pull-ups either globally (refer to
the OPTION_REG register) or individually
(refer to the appropriate WPUx register)
2. Configure the ADC module:
• Select ADC conversion clock
• Configure voltage reference
• Select ADC input channel
• Turn on ADC module
3. Configure ADC interrupt (optional):
• Clear ADC interrupt flag
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
4. Wait the required acquisition time(2).
5. Start conversion by setting the GO/DONE bit.
6. Wait for ADC conversion to complete by one of
the following:
• Polling the GO/DONE bit
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result.
8. Clear the ADC interrupt flag (required if interrupt
is enabled).
EXAMPLE 16-1: ADC CONVERSION
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 16.4 “ADC Acquisi-
tion Re quireme nts”.
;This code block configures the ADC
;for polling, Vdd and Vss references, FRC
;oscillator and AN0 input.
;
;Conversion start & polling for completion
; are included.
;
BANKSEL ADCON1 ;
MOVLW B’11110000’ ;Right justify, FRC
;oscillator
MOVWF ADCON1 ;Vdd and Vss Vref
BANKSEL TRISA ;
BSF TRISA,0 ;Set RA0 to input
BANKSEL ANSEL ;
BSF ANSEL,0 ;Set RA0 to analog
BANKSEL WPUA
BCF WPUA,0 ;Disable weak
;pull-up on RA0
BANKSEL ADCON0 ;
MOVLW B’00000001’ ;Select channel AN0
MOVWF ADCON0 ;Turn ADC On
CALL SampleTime ;Acquisiton delay
BSF ADCON0,ADGO ;Start conversion
BTFSC ADCON0,ADGO ;Is conversion done?
GOTO $-1 ;No, test again
BANKSEL ADRESH ;
MOVF ADRESH,W ;Read upper 2 bits
MOVWF RESULTHI ;store in GPR space
BANKSEL ADRESL ;
MOVF ADRESL,W ;Read lower 8 bits
MOVWF RESULTLO ;Store in GPR space
PIC16(L)F1777/8/9
DS40001819B-page 232 2015-2016 Microchip Technology Inc.
16.3 Register Definitions: ADC Control
REGISTER 16-1: ADCON0: ADC CONTROL REGISTER 0
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
CHS<5:0> GO/DONE ADON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-2 CHS<5:0>: Analog Channel Select bits
111111 = FVR (Fixed Voltage Reference) Buffer 1 Output(2)
111110 = DAC1_output(1)
111101 = Temperature Indicator(3)
111100 = DAC2_output(1)
111011 = DAC3_output(4)
111010 = DAC4_output(4)
111001 = DAC5_output(4)
111000 = DAC6_output(4,6)
110111 = DAC7_output(4)
110110 = DAC8_output(1,6)
110101 = Reserved. No channel connected.
110010 = Switched AN18(5)
110001 = Reserved. No channel connected.
•
•
•
101011 = Reserved. No channel connected.
101010 = Switched AN10(5)
101001 = Reserved. No channel connected.
•
•
•
100010 = Reserved. No channel connected.
100001 = Switched AN1(5)
011100 = Reserved. No channel connected.
011011 = AN27(6)
011010 = AN26(6)
011001 = AN25(6)
011000 = AN24(6)
010111 = AN23(6)
010110 = AN22(6)
010101 = AN21(6)
010100 = AN20(6)
010011 = AN19
010010 = AN18
010001 = AN17
010000 = AN16
001111 = AN15
001110 = AN14
001101 = AN13
001100 = AN12
001011 = AN11
001010 = AN10
001001 = AN9
001000 = AN8
000111 = AN7(6)
000110 = AN6(6)
000101 = AN5(6)
000100 = AN4
000011 = AN3
000010 = AN2
000001 = AN1
000000 = AN0
2015-2016 Microchip Technology Inc. DS40001819B-page 233
PIC16(L)F1777/8/9
bit 1 GO/DONE: ADC Conversion Status bit
1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle.
This bit is automatically cleared by hardware when the ADC conversion has completed.
0 = ADC conversion completed/not in progress
bit 0 ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
Note 1: See Section 17.0 “5-Bit Digital-to-Analog Converter (DAC) Module” for more information.
2: See Section 14.0 “Fixed Voltage Reference (FVR)” for more information.
3: See Se ct ion 15.0 “Temperat ur e Ind ica to r Mo dule” for more information.
4: See Section 18.0 “10-bit Digital-to-Analog Converter (DAC) Module” for more information.
5: Input source is switched off when op amp override is forcing tri-state. See Section 29.3 “Override Control”
6: PIC16(L)F1777/9 only.
REGISTER 16-1: ADCON0: ADC CONTROL REGISTER 0 (CONTINUED)
PIC16(L)F1777/8/9
DS40001819B-page 234 2015-2016 Microchip Technology Inc.
REGISTER 16-2: ADCON1: ADC CONTROL REGISTER 1
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
ADFM ADCS<2:0> — ADNREF ADPREF<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 ADFM: ADC Result Format Select bit
1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is
loaded.
0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is
loaded.
bit 6-4 ADCS<2:0>: ADC Conversion Clock Select bits
111 = FRC (clock supplied from an internal RC oscillator)
110 =F
OSC/64
101 =F
OSC/16
100 =F
OSC/4
011 = FRC (clock supplied from an internal RC oscillator)
010 =F
OSC/32
001 =F
OSC/8
000 =F
OSC/2
bit 3 Unimplemented: Read as ‘0’
bit 2 ADNREF: ADC Negative Voltage Reference Configuration bit
1 =VREF- is connected to external VREF- pin
0 =V
REF- is connected to VSS
bit 1-0 ADPREF<1:0>: ADC Positive Voltage Reference Configuration bits
11 =V
REF+ is connected to internal Fixed Voltage Reference (FVR) module(1)
10 =VREF+ is connected to external VREF+ pin(1)
01 = Reserved
00 =V
REF+ is connected to VDD
Note 1: When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage
specification exists. See Table 36-16: ADC Conversion Requirements for details.
2015-2016 Microchip Technology Inc. DS40001819B-page 235
PIC16(L)F1777/8/9
REGISTER 16-3: ADCON2: ADC CONTROL REGISTER 2
U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
—— TRIGSEL<5:0>(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 TRIGSEL<5:0>: Auto-Conversion Trigger Selection bits(1)
101101 = PWM12 – OF12_match(2)
101100 = PWM12 – PH12_match(2)
101011 = PWM12 – PR12_match(2)
101010 = PWM12 – DC12_match(2)
101001 = PWM11 – OF11_match
101000 = PWM11 – PH11_match
100111 = PWM11 – PR11_match
100110 = PWM11 – DC11_match
100101 = PWM6 – OF6_match
100100 = PWM6 – PH6_match
100011 = PWM6 – PR6_match
100010 = PWM6 – DC6_match
100001 = PWM5 – PH5_match
100000 = PWM5 – PH5_match
011111 = PWM5 – PH5_match
011110 = PWM5 – PH5_match
011101 = PWM10 – PWM10OUT(2)
011100 = PWM9 – PWM9OUT
011011 = PWM4 – PWM4OUT
011010 = PWM3 – PWM3OUT
011001 = CCP8 – CCP8_trigger(2)
011000 = CCP7 – CCP7_trigger
010111 = CCP2 – CCP2_trigger
010110 = CCP1 – CCP1_trigger
010101 = CLC4 – LC4_out
010100 = CLC3 – LC3_out
010011 = CLC2 – LC2_out
010010 = CLC1 – LC1_out
010001 = Comparator C8 – sync_C8OUT(2)
010000 = Comparator C7 – sync_C7OUT(2)
001111 = Comparator C6 – sync_C6OUT
001110 = Comparator C5 – sync_C5OUT
001101 = Comparator C4 – sync_C4OUT
001100 = Comparator C3 – sync_C3OUT
001011 = Comparator C2 – sync_C2OUT
001010 = Comparator C1 – sync_C1OUT
001001 = Timer8 – T8_postscaled
001000 = Timer6 – T6_postscaled
000111 = Timer5 – T5_overflow
000110 = Timer4 – T4_postscaled
000101 = Timer3 – T3_overflow
000100 = Timer2 – T2_postscaled
000011 = Timer1 – T1_overflow
000010 = Timer0 – T0_overflow
000001 = ADCACT – ADCACTPPS Pin
000000 = No Auto-conversion Trigger selected
Note 1: This is a rising edge sensitive input for all sources.
2: PIC16(L)F1777/9 only.
PIC16(L)F1777/8/9
DS40001819B-page 236 2015-2016 Microchip Technology Inc.
REGISTER 16-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
ADRES<9:2>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ADRES<9:2>: ADC Result Register bits
Upper eight bits of 10-bit conversion result
REGISTER 16-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
ADRES<1:0> — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 ADRES<1:0>: ADC Result Register bits
Lower two bits of 10-bit conversion result
bit 5-0 Reserved: Do not use.
2015-2016 Microchip Technology Inc. DS40001819B-page 237
PIC16(L)F1777/8/9
REGISTER 16-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — — — — — ADRES<9:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-2 Reserved: Do not use.
bit 1-0 ADRES<9:8>: ADC Result Register bits
Upper two bits of 10-bit conversion result
REGISTER 16-7: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
ADRES<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ADRES<7:0>: ADC Result Register bits
Lower eight bits of 10-bit conversion result
PIC16(L)F1777/8/9
DS40001819B-page 238 2015-2016 Microchip Technology Inc.
16.4 ADC Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 16-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), refer
to Figure 16-4. The maximum recommended
impedance for analog sources is 10 k. As the
source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
selected (or changed), an ADC acquisition must be
done before the conversion can be started. To calculate
the minimum acquisition time, Equation 16-1 may be
used. This equation assumes that 1/2 LSb error is used
(1,024 steps for the ADC). The 1/2 LSb error is the
maximum error allowed for the ADC to meet its
specified resolution.
EQUATION 16-1: ACQUISITION TIME EXAMPLE(1,2,3)
TACQ Amplifier Settling Time Hold Capacitor Charging Time Temperature Co efficient++=
TAMP TCTCOFF++=
2µs TCTemperature - 25°C0.05µs/°C++=
TCCHOLD RIC RSS RS++ ln(1/2047)–=
10pF 1k
7k
10k
++– ln(0.0004885)=
1.37=µs
VAPPLIED 1e
Tc–
RC
---------
–



VAPPLIED 11
2n1+
1–
--------------------------–


=
VAPPLIED 11
2n1+
1–
--------------------------–


VCHOLD=
VAPPLIED 1e
TC–
RC
----------
–



VCHOLD=
;[1] VCHOLD charged to within 1/2 lsb
;[2] VCHOLD char ge response to VAPPLIED
;combining [1] and [2]
The value for TC can be approximated with the following equations:
Solving for TC:
Therefore:
Temperature 50°C and external impedance of 10k
5.0V V DD=
Assumptions:
Note: Where n = number of bits of the ADC.
TACQ 2µs 892ns 50°C- 25°C0.05µs/°C++=
4.62µs=
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
2015-2016 Microchip Technology Inc. DS40001819B-page 239
PIC16(L)F1777/8/9
FIGURE 16-4: ANALOG INPUT MODEL
FIGURE 16-5: ADC TRANSFER FUN CTION
CPIN
VA
Rs
Analog
5 pF
VDD
VT 0.6V
VT 0.6V I LEAKAGE(1)
RIC 1k
Sampling
Switch
SS Rss
CHOLD = 10 pF
Ref-
6V
Sampling Switch
5V
4V
3V
2V
567891011
(k)
VDD
Legend:
CPIN
VT
I LEAKAGE
RIC
SS
CHOLD
= Input Capacitance
= Threshold Voltage
= Leakage current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance
various junctions
RSS
Note 1: Refer to Table 36-4: I/O Ports (parameter D060).
RSS = Resistance of Sampling Switch
Input
pin
3FFh
3FEh
ADC Output Code
3FDh
3FCh
03h
02h
01h
00h
Full-Scale
3FBh
0.5 LSB
Ref- Zero-Scale
Transition Ref+
Transition
1.5 LSB
Full-Scale Range
Analog Input Voltage
PIC16(L)F1777/8/9
DS40001819B-page 240 2015-2016 Microchip Technology Inc.
TABLE 16-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Name B it 7 Bit 6 B it 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ADCON0 CHS<5:0> GO/DONE ADON 232
ADCON1 ADFM ADCS<2:0> — ADNREF ADPREF<1:0> 234
ADCON2 —— TRIGSEL<5:0> 235
ADRESH ADC Result Register High 236, 237
ADRESL ADC Result Register Low 236, 237
ANSELA —— ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177
ANSELB —— ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182
ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 187
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 223
DAC1CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 244
DAC2CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 244
DAC5CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 244
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB6 TRISB6 TRISB1 TRISB0 181
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not
used for the ADC module.
2015-2016 Microchip Technology Inc. DS40001819B-page 241
PIC16(L)F1777/8/9
17.0 5-BIT DIGITAL-TO-ANALOG
CONVERTER (DAC) MODULE
The Digital-to-Analog Converter supplies a variable
voltage reference, ratiometric with the input source,
with 32 selectable output levels.
The input of the DAC can be connected to:
•External V
REF pins
•VDD supply voltage
• FVR (Fixed Voltage Reference)
The output of the DAC can be configured to supply a
reference voltage to the following:
• Comparator positive input
• Operational amplifier inverting and non-inverting
inputs
• ADC input channel
•DAC
XOUTX pin
The Digital-to-Analog Converter (DAC) is enabled by
setting the EN bit of the DACxCON0 register.
17.1 Output Voltage Selection
The DAC has 32 voltage level ranges. The 32 levels
are set with the REF<4:0> bits of the DACxREF
register.
The DAC output voltage is determined by Equation 17-1:
EQUATION 17-1: DAC OUTPUT VOLTAGE
17.2 Ratiometric Output Level
The DAC output value is derived using a resistor ladder
with each end of the ladder tied to a positive and
negative voltage reference input source. If the voltage
of either input source fluctuates, a similar fluctuation will
result in the DAC output value.
The value of the individual resistors within the ladder
can be found in Table 36-20: 10-bit Digital-to-Analog
Converter (DAC) Specifications.
17.3 DAC Voltage Reference Output
The DAC voltage can be output to the DACxOUTx pin
by setting the OEx bit of the DACxCON0 register.
Selecting the DAC voltage for output on the
DACXOUTX pin automatically overrides the digital
output buffer and digital input threshold detector
functions of that pin. Reading the DACXOUTX pin when
it has been configured for DAC voltage output will
always return a ‘0’.
Due to the limited current drive capability, a buffer must
be used on the DAC voltage output for external
connections to the DACXOUTX pin. Figure 17-2 shows
an example buffering technique.
TABLE 17-1: AVAILABLE 5-BIT DACS
Device DAC3 DAC4 DAC7 DAC8
PIC16(L)F1778 ●●●
PIC16(L)F1777/9 ●●●●
IF DACxEN = 1
VSOURCE+ = VDD, VREF, or FVR BUFFER 2
VSOURCE- = VSS
VOUT VSOURCE+VSOURCE-–
DACxR 4:0
25
---------------------------------



VSOURCE-+=
PIC16(L)F1777/8/9
DS40001819B-page 242 2015-2016 Microchip Technology Inc.
FIGURE 17-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
FIGURE 17-2: VOLT AGE REFERENCE OUTPUT BUFFER EXAMPLE
32-to-1 MUX
R<4:0>
R
Reserved
NSS<1:0>
R
R
R
R
R
R
32 DACX_Output
DACXOUT1
5
(To Comparator and
ADC Modules)
OE1
VDD
VREF+
PSS<1:0> 2
EN
Steps
Digital-to-Ana log Converter (DAC)
FVR_buffer2
R
VSOURCE-
VSOURCE+
DACXOUT2
OE2
VREF0-
VSS
VREF1-
DACXOUTXBuffered DAC Output
+
–
DAC
Module
Voltage
Reference
Output
Impedance
R
PIC® MCU
2015-2016 Microchip Technology Inc. DS40001819B-page 243
PIC16(L)F1777/8/9
17.4 Operation During Sleep
The DAC continues to function during Sleep. When the
device wakes up from Sleep through an interrupt or a
Watchdog Timer time-out, the contents of the
DACxCON0 register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
17.5 Effects of a Reset
A device Reset affects the following:
• DAC is disabled.
• DAC output voltage is removed from the
DACXOUTX pin.
• The REF<4:0> voltage reference control bits are
cleared.
PIC16(L)F1777/8/9
DS40001819B-page 244 2015-2016 Microchip Technology Inc.
17.6 Register Definitions: DAC Control
Long bit name prefixes for the 5-bit DAC peripherals
are shown in Tabl e 17-2. Refer to Section 1.1 “ R eg is-
ter and Bit naming conventions” for more informa-
tion
TABLE 17-2:
Peripheral Bit Name Prefix
DAC3 DAC3
DAC4 DAC4
DAC7 DAC7
DAC8(1) DAC8
Note 1: PIC16(L)F1777/9 only.
REGISTER 17-1: DACxCON0: DACx CONTROL REGISTER 0
R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0
EN — OE1 OE2 PSS<1:0> NSS<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 EN: DAC Enable bit
1 = DAC is enabled
0 = DAC is disabled
bit 6 Unimplemented: Read as ‘0’
bit 5 OE1: DAC Voltage Output Enable bit
1 = DAC voltage level is also an output on the DACxOUT1 pin
0 = DAC voltage level is disconnected from the DACxOUT1 pin
bit 4 OE2: DAC Voltage Output Enable bit
1 = DAC voltage level is also an output on the DACxOUT2 pin
0 = DAC voltage level is disconnected from the DACxOUT2 pin
bit 3-2 PSS<1:0>: DAC Positive Source Select bits
11 = Reserved, do not use
10 = FVR Buffer2 output
01 =V
REF+ pin
00 =V
DD
bit 1-0 NSS<1:0>: DAC Negative Source Select bits
11 = Reserved, do not use
10 = DACxREF1- (DAC7/8) or Reserved (DAC3/4)
01 = DACxREF0-
00 =AG
ND (AVSS)
2015-2016 Microchip Technology Inc. DS40001819B-page 245
PIC16(L)F1777/8/9
TABLE 17-3: SUMMARY OF REGISTERS ASSOCIATED WITH THE DACx MODULE
REGISTER 17-2: DACxREF: DACx REFERENCE VOLT AGE OUTPUT SELECT REGISTER
U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — —REF<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 REF<4:0>: DACx Reference Voltage Output Select bits (See Equation 17-1)
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on page
DAC3CON0 EN — OE1 OE2 PSS<1:0> NSS<1:0> 244
DAC4CON0 EN --- OE1 OE2 PSS<1:0> NSS<1:0> 244
DAC7CON0 EN --- OE1 OE2 PSS<1:0> NSS<1:0> 244
DAC8CON0(1) EN --- OE1 OE2 PSS<1:0> NSS<1:0> 244
DAC3REF --- --- --- REF<4:0> 245
DAC4REF --- --- --- REF<4:0> 245
DAC7REF --- --- --- REF<4:0> 245
DAC8REF(1) --- --- --- REF<4:0> 245
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used with the DACx module.
Note 1: PIC16LF1777/9 only.
PIC16(L)F1777/8/9
DS40001819B-page 246 2015-2016 Microchip Technology Inc.
18.0 10-BIT DIGITAL-TO-ANALOG
CONVERTER (DAC) MODULE
The 10-bit Digital-to-Analog Converter (DAC) supplies
a variable voltage reference, ratiometric with the input
source, with 1024 selectable output levels.
The input of the DAC can be connected to:
•External V
REF pins
•VDD supply voltage
• FVR (Fixed Voltage Reference)
The output of the DAC can be configured to supply a
reference voltage to the following:
• Comparator positive input
• ADC input channel
•DAC
XOUT1 pin
•Op Amp
The Digital-to-Analog Converter is enabled by setting
the EN bit of the DACxCON0 register.
18.1 Output Voltage Level Selection
The DAC has 1024 voltage levels that are set by the
10-bit reference selection word contained in the
DACxREFH and DACxREFL registers. This 10-bit
word can be left or right justified. See Section 18.4
“DAC Reference Selection Justification” for more
detail.
The DAC output voltage can be determined with
Equation 18-1.
18.2 Ratiometric Output Voltage
The DAC output voltage is derived using a resistor
ladder with each end of the ladder tied to a positive and
negative voltage source. If the voltage of either input
source fluctuates, a similar fluctuation will result in the
DAC output value.
The value of the individual resistors within the ladder
can be found in Table 36-20.
18.3 DAC Output
The DAC voltage is always available to the internal
peripherals that use it. The DAC voltage can be output
to the DACxOUTx pin by setting the OEx bit of the
DACxCON0 register. Selecting the DAC voltage for
output on the DACxOUTx pin automatically overrides
the digital output buffer and digital input threshold
detector functions of that pin. Reading the DACXOUTX
pin when it has been configured for DAC voltage output
will always return a ‘0’.
Due to the limited current drive capability, a buffer must
be used on the DAC voltage output for external
connections to either DACXOUTX pin. Figure 18-3
shows a buffering technique example.
18.4 DAC Reference Selection
Justification
The DAC reference selection can be configured to be left
or right justified. When the FM bit of the DACxCON0
register is set, the 10-bit word is left justified such that the
eight Most Significant bits fill the DACxREFH register
and the two Least Significant bits are left justified in the
DACxREFL register. When the FM bit is cleared, the
10-bit word is right justified such that the eight Least
Significant bits fill the DACxREFL register and the two
Most Significant bits are right justified in the DACxREFH
register. Refer to Figure 18-1.
The DACxREFL and DACxREFH registers are double
buffered. Writing to either register does not take effect
immediately. Writing a ‘1’ to the DACxLD bit of the
DACLD register transfers the contents of the
DACxREFH and DACxREFL registers to the buffers,
thereby changing all 10-bits of the DAC reference
selection simultaneously.
EQUATION 18-1: DAC OUTPUT VOLTAGE
TABLE 18-1: AVAILABLE 10-BIT DACS
Device DAC1 DAC2 DAC5 DAC6
PIC16(L)F1778 ●●●
PIC16(L)F1777/9 ●●●●
IF EN = 1
VSOURCE+ = VDD, VREF+, or FVR_buffer2
VSOURCE- = VSS OR VREF-
DACx_output VSOURCE+VSOURCE-–
DACxR 9:0
210
--------------------------------


VSOURCE-+=
2015-2016 Microchip Technology Inc. DS40001819B-page 247
PIC16(L)F1777/8/9
FIGURE 18-1: DAC JUSTIFICATION
FIGURE 18-2: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
Rev . 10 -000 225A
4/ 29 /201 4
R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0 0 0 0 0 0
DACxREFH DACxREFL
0 0 0 0 0 0 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
DACxREFH DACxREFL
FM = 1
FM = 0
R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
DACxREF
07
07
0707
VREF+
VDD
FVR_buffer2
Reserved
PSS<1:0>
VSOURCE+
VSOURCE-
2
VSS
R
1024
Steps
R
R
R
R
R
R
1024-to-1 MUX
To Peripherals
DACxOUT1
OE1
DACx_output
EN
10
DACxREFH DACxREFL
write 1 to
DACxLD bit
10-bit Latch
(not visible to user)
Notes:
Rev. 10-000219B
6/17/2015
VREF0-
NSS<1:0>
DACxOUT2
OE2
Reserved
VREF1-(1)
2
Note 1: DAC5 only, DAC1/2 is Reserved.
PIC16(L)F1777/8/9
DS40001819B-page 248 2015-2016 Microchip Technology Inc.
FIGURE 18-3: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
18.5 Operation Duri ng Sleep
When the device wakes up from Sleep as the result of
an interrupt or a Watchdog Timer time-out, the contents
of the DACxCON0 register are not affected. To
minimize current consumption in Sleep mode, the
voltage reference should be disabled.
18.6 Effects of a Reset
A device Reset affects the following:
• DAC is disabled
• DAC output voltage is removed from the
DACXOUTX pin
• The REF<9:0> reference selection bits are
cleared
DACXOUTXBuffered DAC Output
+
–
DAC
Module
Voltage
Reference
Output
Impedance
R
PIC® MCU
2015-2016 Microchip Technology Inc. DS40001819B-page 249
PIC16(L)F1777/8/9
18.7 Register Definitions: DAC Control
Long bit name prefixes for the 10-bit DAC peripherals
are shown in Table 18-2. Refer to Section 1.1 “ Reg is-
ter and Bit naming conventions” for more informa-
tion
TABLE 18-2:
Peripheral Bit Name Prefix
DAC1 DAC1
DAC2 DAC2
DAC5 DAC5
DAC6(1) DAC6
Note 1: PIC16(L)F1777/9 only.
REGISTER 18-1: DACxCON0: DAC CONTROL REGISTER 0
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
EN FM OE1 OE2 PSS<1:0> NSS<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 EN: DAC Enable bit
1 = DACx is enabled
0 = DACx is disabled
bit 6 FM: DAC Reference Format bit
1 = DACx reference selection is left justified
0 = DACx reference selection is right justified
bit 5 OE1: DAC Voltage Output Enable bit
1 = DACx voltage level is also an output on the DACxOUT1 pin
0 = DACx voltage level is disconnected from the DACxOUT1 pin
bit 4 OE2: DAC Voltage Output Enable bit
1 = DACx voltage level is also an output on the DACxOUT2 pin
0 = DACx voltage level is disconnected from the DACxOUT2 pin
bit 3-2 PSS<1:0>: DAC Positive Source Select bits
11 = DACxREF1+ (DAC5/6) or Reserved (DAC1/2)
10 = FVR_buffer2
01 =DAC
XREF0+
00 =V
DD
bit 1-0 NSS<1:0>: DAC Negative Source Select bit
11 = Reserved. Do not use.
10 = DACxREF1- (DAC5/6) or Reserved (DAC1/2)
01 = DACxREF0-
00 =AGND (AVSS)
PIC16(L)F1777/8/9
DS40001819B-page 250 2015-2016 Microchip Technology Inc.
REGISTER 18-2: DACxREFH: DAC REFERENCE VOLTAGE SELECT HIGH REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
REF<9:x> (x Depends on FM bit)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
When FM = 1 (left justified)
bit 7-0 REF<9:2>: DAC Reference Voltage Output Select bits
DACxOUT1 = f(REF<9:0>) (See Equation 18-1)
When FM = 0 (right justified)
bit 7-2 Unimplemented: Read as ‘0’
bit 1-0 REF<9:8>: DAC Reference Voltage Output Select bits
DACxOUT1 = f(REF<9:0>) (See Equation 18-1)
REGISTER 18-3: DACxREFL: DAC REFERENCE VOLTAGE SELECT LOW REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
REF<x-1:0> (x Depends on FM bit)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
When FM = 1 (left justified)
bit 7-6 REF<1:0>: DAC Reference Voltage Output Select bits
DACxOUT1 = f(REF<9:0>) (See Equation 18-1)
bit 5-0 Unimplemented: Read as ‘0’
When FM = 0 (right justified)
bit 7-0 REF<7:0>: DAC Reference Voltage Output Select bits
DACxOUT1 = f(REF<9:0>) (See Equation 18-1)
2015-2016 Microchip Technology Inc. DS40001819B-page 251
PIC16(L)F1777/8/9
TABLE 18-3: SUMMARY OF REGISTERS ASSOCIATED WITH THE DACx MODULE
REGISTER 18-4: DACLD: DAC BUFFER LOAD REGISTER
U-0 U-0 U-0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
—— DAC6LD(1) DAC5LD —— DAC2LD DAC1LD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on configuration bits
bit 7-6 Unimplemented: Read as ‘0’
bit 5 DAC6LD: DAC6 Double Buffer Load bit(1)
1 = DAC6REFHL:DAC6REFL values are transfered to the double buffer. Bit is cleared automatically
by hardware.
0 = DAC6REFHL:DAC6REFL double buffers remain unchanged.
bit 4 DAC5LD: DAC5 Double Buffer Load bit
1 = DAC5REFHL:DAC5REFL values are transfered to the double buffer. Bit is cleared automatically
by hardware.
0 = DAC5REFHL:DAC5REFL double buffers remain unchanged.
bit 3-2 Unimplemented: Read as ‘0’
bit 1 DAC2LD: DAC2 Double Buffer Load bit
1 = DAC2REFHL:DAC2REFL values are transfered to the double buffer. Bit is cleared automatically
by hardware.
0 = DAC2REFHL:DAC2REFL double buffers remain unchanged.
bit 0 DAC1LD: DAC1 Double Buffer Load bit
1 = DAC1REFHL:DAC1REFL values are transfered to the double buffer. Bit is cleared automatically
by hardware.
0 = DAC1REFHL:DAC1REFL double buffers remain unchanged.
Note 1: PIC16LF1777/9 only.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B i t 2 Bit 1 B it 0 Register
on Page
DAC1CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 249
DAC2CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 249
DAC5CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 249
DAC6CON0(1) EN FM OE1 OE2 PSS<1:0> NSS<1:0> 249
DAC1REFH REF<9:x> (x Depends on FM bit) 250
DAC2REFH REF<9:x> (x Depends on FM bit) 250
DAC5REFH REF<9:x> (x Depends on FM bit) 250
DAC6REFH(1) REF<9:x> (x Depends on FM bit) 250
DAC1REFL REF<x-1:0> (x Depends on FM bit) 250
DAC2REFL REF<x-1:0> (x Depends on FM bit) 250
DAC5REFL REF<x-1:0> (x Depends on FM bit) 250
DAC6REFL(1) REF<x-1:0> (x Depends on FM bit) 250
DACLD — — — DAC5LD — — DAC2LD DAC1LD 251
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used with the DACx module.
Note 1: PIC16LF1777/9 only.
PIC16(L)F1777/8/9
DS40001819B-page 252 2015-2016 Microchip Technology Inc.
19.0 COMPARATOR MODULE
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and
providing a digital indication of their relative magnitudes.
Comparators are very useful mixed signal building
blocks because they provide analog functionality
independent of program execution. The analog
comparator module includes the following features:
• Independent comparator control
• Programmable input selection
• Comparator output is available internally/externally
• Programmable output polarity
• Interrupt-on-change
• Wake-up from Sleep
• Programmable Speed/Power optimization
•PWM shutdown
• Programmable and Fixed Voltage Reference
19.1 Comparator Overview
A single comparator is shown in Figure 19-1 along with
the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.
The comparators available for this device are located in
Table 19-1.
FIGURE 19-1: SINGLE COMPARATOR
TABLE 19-1: AVAILABLE COMPARATORS
Device C1 C2 C3 C4 C5 C6 C7 C8
PIC16(L)F1778 ●●●●●●
PIC16(L)F1777/9 ●●●●●●●●
–
+
VIN+
VIN-Output
Output
VIN+
VIN-
Note: The black areas of the output of the
comparator represents the uncertainty
due to input offsets and response time.
2015-2016 Microchip Technology Inc. DS40001819B-page 253
PIC16(L)F1777/8/9
FIGURE 19-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM
Note 1: When CxON = 0, the comparator will produce a ‘0’ at the output.
2: When CxON = 0, all multiplexer inputs are disconnected.
MUX
Cx
CxON(1)
CxNCH<2:0>
3
CXPCH<3:0>
MUX
-
+
CxVN
CxVP Q1
D
EN
Q
Set CxIF
C
X
SYNC
CXOUT
DQ
CxHYS
det
Interrupt
det
Interrupt
CxINTN
CxINTP
4TRIS bit
CxON
(2)
(2)
From Timer1
tmr1_clk sync_CxOUT
to CMXCON0 (CXOUT)
and CM2CON1 (MCXOUT)
CXPOL
0
1
CxZLF
ZLF
0
1
PPS
RXYPPS
See Table 19-4
See Table 19-5
PIC16(L)F1777/8/9
DS40001819B-page 254 2015-2016 Microchip Technology Inc.
19.2 Comparator Control
Each comparator has two control registers: CMxCON0
and CMxCON1.
The CMxCON0 register (see Register 19-1) contains
Control and Status bits for the following:
• Enable
•Output
• Output polarity
• Zero latency filter
• Speed/Power selection
• Hysteresis enable
• Output synchronization
The CMxCON1 register (see Register 19-2) contains
Control bits for the following:
• Interrupt enable
• Interrupt edge polarity
• Positive input channel selection
• Negative input channel selection
19.2.1 COMPARATOR ENABLE
Setting the ON bit of the CMxCON0 register enables
the comparator for operation. Clearing the ON bit
disables the comparator resulting in minimum current
consumption.
19.2.2 COMPARATOR OUTPUT
SELECTION
The output of the comparator can be monitored by
reading either the OUT bit of the CMxCON0 register or
the MCxOUT bit of the CMOUT register. In order to
make the output available for an external connection,
the following conditions must be true:
• Desired pin PPS control
• Corresponding TRIS bit must be cleared
• ON bit of the CMxCON0 register must be set
19.2.3 COMPARATOR OUTPUT POLARITY
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the POL bit of the CMxCON0 register. Clearing
the POL bit results in a non-inverted output.
Table 19-2 shows the output state versus input
conditions, including polarity control.
Note 1: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external out-
puts are not latched.
TABLE 19-2: COMPARATOR OUTPUT
STATE VS. INPUT
CONDITIONS
Input Condition CxPOL CxOUT
CxVN > CxVP00
CxVN < CxVP01
CxVN > CxVP11
CxVN < CxVP10
2015-2016 Microchip Technology Inc. DS40001819B-page 255
PIC16(L)F1777/8/9
19.3 Comparator Hysteresis
A selectable amount of separation voltage can be
added to the input pins of each comparator to provide a
hysteresis function to the overall operation. Hysteresis
is enabled by setting the HYS bit of the CMxCON0
register.
See Comparator Specifications in Table 36-19:
Comparator Specifications for more information.
19.4 Timer1 Gate Operation
The output resulting from a comparator operation can
be used as a source for gate control of Timer1. See
Section 22.6 “Timer1 Gate” for more information.
This feature is useful for timing the duration or interval
of an analog event.
It is recommended that the comparator output be
synchronized to Timer1. This ensures that Timer1 does
not increment while a change in the comparator is
occurring.
19.4.1 COMPARATOR OUTPUT
SYNCHRONIZATION
The output from a comparator can be synchronized
with Timer1 by setting the SYNC bit of the CMxCON0
register.
Once enabled, the comparator output is latched on the
falling edge of the Timer1 source clock. If a prescaler is
used with Timer1, the comparator output is latched after
the prescaling function. To prevent a race condition, the
comparator output is latched on the falling edge of the
Timer1 clock source and Timer1 increments on the
rising edge of its clock source. See the Comparator
Block Diagram (Figure 19-2) and the Timer1 Block
Diagram (Figure 22-1) for more information.
19.5 Comparator Interrupt
An interrupt can be generated upon a change in the
output value of the comparator for each comparator, a
rising edge detector and a falling edge detector are
present.
When either edge detector is triggered and its associ-
ated enable bit is set (INTP and/or INTN bits of the
CMxCON1 register), the Corresponding Interrupt Flag
bit (CxIF bit of the PIR2 register) will be set.
To enable the interrupt, you must set the following bits:
• ON and POL bits of the CMxCON0 register
• CxIE bit of the PIE2 register
• INTP bit of the CMxCON1 register (for a rising
edge detection)
• INTN bit of the CMxCON1 register (for a falling
edge detection)
• PEIE and GIE bits of the INTCON register
The associated interrupt flag bit, CxIF bit of the PIR2
register, must be cleared in software. If another edge is
detected while this flag is being cleared, the flag will still
be set at the end of the sequence.
19.6 Comparator Positive Input
Selection
Configuring the PCH<3:0> bits of the CMxPSEL
register directs an internal voltage reference or an
analog pin to the non-inverting input of the comparator:
• CxIN+ analog pin
• Programmable ramp generator output
• DAC output
• FVR (Fixed Voltage Reference)
•V
SS (Ground)
See Section 14.0 “Fixed Voltage Reference (FVR)”
for more information on the Fixed Voltage Reference
module.
See Section 17.0 “5-Bit Digit al-to-An alog Converter
(DAC) Module” for more information on the DAC input
signal.
Any time the comparator is disabled (CxON = 0), all
comparator inputs are disabled.
19.7 Comparator Negative Input
Selection
The NCH<3:0> bits of the CMxNSEL register direct an
analog input pin and internal reference voltage or ana-
log ground to the inverting input of the comparator:
•CxIN- pin
• FVR (Fixed Voltage Reference)
• Analog Ground
Some inverting input selections share a pin with the
operational amplifier output function. Enabling both
functions at the same time will direct the operational
amplifier output to the comparator inverting input.
Note: Although a comparator is disabled, an
interrupt can be generated by changing
the output polarity with the POL bit of the
CMxCON0 register, or by switching the
comparator on or off with the ON bit of the
CMxCON0 register.
Note: To use CxINy+ and CxINy- pins as analog
input, the appropriate bits must be set in
the ANSEL register and the correspond-
ing TRIS bits must also be set to disable
the output drivers.
PIC16(L)F1777/8/9
DS40001819B-page 256 2015-2016 Microchip Technology Inc.
19.8 Comparator Response Time
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new reference voltage. This period is referred to as
the response time. The response time of the comparator
differs from the settling time of the voltage reference.
Therefore, both of these times must be considered when
determining the total response time to a comparator
input change. See the Comparator and Voltage
Reference Specifications in Table 36-19: Comparator
Specifications for more details.
19.9 Zero Latency Filter
In high-speed operation, and under proper circuit
conditions, it is possible for the comparator output to
oscillate. This oscillation can have adverse effects on
the hardware and software relying on this signal.
Therefore, a digital filter has been added to the
comparator output to suppress the comparator output
oscillation. Once the comparator output changes, the
output is prevented from reversing the change for a
nominal time of 20 ns. This allows the comparator
output to stabilize without affecting other dependent
devices. Refer to Figure 19-3.
FIGURE 19-3: COMPARATOR ZERO LATENCY FILTER OPERATION
CxOUT From Comparator
CxOUT From ZLF TZLF
Output waiting for TZLF to expire before an output change is allowed.
TZLF has expired so output change of ZLF is immediate based on
comparator output change.
2015-2016 Microchip Technology Inc. DS40001819B-page 257
PIC16(L)F1777/8/9
19.10 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 19-4. Since the analog input pins share their
connection with a digital input, they have reverse
biased ESD protection diodes to VDD and VSS. The
analog input, therefore, must be between VSS and VDD.
If the input voltage deviates from this range by more
than 0.6V in either direction, one of the diodes is
forward biased and a latch-up may occur.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage current to
minimize inaccuracies introduced.
FIGURE 19-4: ANALOG INPUT MODEL
Note 1: When reading a PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
2: Analog levels on any pin defined as a
digital input, may cause the input buffer to
consume more current than is specified.
VA
RS < 10K
VDD
Analog
Input pin
CPIN
5pF VT § 0.6V
VT § 0.6V
ILEAKAGE(1)
VSS
RIC
To Comparator
Legend: CPIN = Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS= Source Impedance
VA= Analog Voltage
VT= Threshold Voltage
Rev. 10-000071A
8/2/2013
Note 1: See I/O Ports in Table 36-4: I/O Ports.
PIC16(L)F1777/8/9
DS40001819B-page 258 2015-2016 Microchip Technology Inc.
19.11 Register Definitions: Comparator Control
Long bit name prefixes for the Comparator peripherals
are shown in Table 19-3. Refer to Section 1.1.2.2
“Long Bit Names” for more information
TABLE 19-3:
Peripheral B it Name Prefix
Comparator 1 C1
Comparator 2 C2
Comparator 3 C3
Comparator 4 C4
Comparator 5 C5
Comparator 6 C6
Comparator 7(1) C7
Comparator 8(1) C8
Note 1: PIC16(L)F1777/9 only.
REGISTER 19-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0
R/W-0/0 R-0/0 U-0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-0/0
ON OUT —POL ZLF —HYS SYNC
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 ON: Comparator Enable bit
1 = Comparator is enabled
0 = Comparator is disabled and consumes no active power
bit 6 OUT: Comparator Output bit
If POL = 1 (inverted polarity):
1 = CxVP < CxVN
0 = CxVP > CxVN
If POL = 0 (non-inverted polarity):
1 = CxVP > CxVN
0 = CxVP < CxVN
bit 5 Reserved: Read as ‘1’. Maintain this bit set.
bit 4 POL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 3 ZLF: Comparator Zero Latency Filter Enable bit
1 = Comparator output is filtered
0 = Comparator output is unfiltered
bit 2 Reserved: Read as ‘1’. Maintain this bit set.
bit 1 HYS: Comparator Hysteresis Enable bit
1 = Comparator hysteresis enabled
0 = Comparator hysteresis disabled
bit 0 SYNC: Comparator Output Synchronous Mode bit
1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output
updated on the falling edge of Timer1 clock source.
0 = Comparator output to Timer1 and I/O pin is asynchronous
2015-2016 Microchip Technology Inc. DS40001819B-page 259
PIC16(L)F1777/8/9
REGISTER 19-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0
— — — — — — INTP INTN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-2 Unimplemented: Read as ‘0’
bit 1 INTP: Comparator Interrupt on Positive Going Edge Enable bits
1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit
0 = No interrupt flag will be set on a positive going edge of the CxOUT bit
bit 0 INTN: Comparator Interrupt on Negative Going Edge Enable bits
1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit
0 = No interrupt flag will be set on a negative going edge of the CxOUT bit
PIC16(L)F1777/8/9
DS40001819B-page 260 2015-2016 Microchip Technology Inc.
REGISTER 19-3: CMxNSEL: COMPARATOR Cx NEGATIVE CHANNEL SELECT REGISTER
U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — NCH<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 NCH<3:0>: Comparator Negative Input Channel Select bits
CxVN connects to input source indicated by Table 19-4: Negative Input Sources
TABLE 19-4: NEGATIVE INPUT SOURCES
NCH<3:0> C1 , C2, C3, C4 C5, C6, C7(1), C8(1)
1111 Reserved. Do not use Reserved. Do not use
1110 Reserved. Do not use Reserved. Do not use
1101 Reserved. Do not use Reserved. Do not use
1100 Reserved. Do not use Reserved. Do not use
1011 Reserved. Do not use Reserved. Do not use
1010 OPA2IN- pin OPA4IN- pin(1)
1001 OPA1IN- pin OPA3IN- pin
1000 AGND AGND
0111 PRG2_out PRG4_out(1)
0110 PRG1_out PRG3_out
0101 FVR_Buffer2 FVR_Buffer2
0100 CxIN4- pin CxIN4- (OPA4OUT) pin(1)
0011 CxIN3- (OPA2OUT) pin CxIN3- pin
0010 CxIN2- pin CxIN2- pin
0001 CxIN1- (OPA1OUT) pin CxIN1- (OPA3OUT) pin
0000 CxIN0- pin CxIN0- pin
Note 1: PIC16(L)F1777/9 only.
2015-2016 Microchip Technology Inc. DS40001819B-page 261
PIC16(L)F1777/8/9
REGISTER 19-4: CMxPSEL: COMPARATOR Cx POSITIVE CHANNEL SELECT REGISTER 1
U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — PCH<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 PCH<3:0>: Comparator Positive Input Channel Select bits
CxVP connects to input source indicated by Table 19-5: Positive Input Sources
TABLE 19-5: POSITIVE INPUT SOURCES
PCH<3:0> C1, C2, C3, C4 C5, C6, C7(1), C8(1)
1111 Reserved. Do not use Reserved. Do not use
1110 Reserved. Do not use Reserved. Do not use
1101 Reserved. Do not use Reserved. Do not use
1100 Reserved. Do not use Reserved. Do not use
1011 Reserved. Do not use Reserved. Do not use
1010 Reserved. Do not use Reserved. Do not use
1001 AGND AGND
1000 DAC4_out DAC8_out(1)
0111 DAC3_out DAC7_out
0110 DAC2_out DAC6_out(1)
0101 DAC1_out DAC5_out
0100 PRG2_out PRG4_out(1)
0011 PRG1_out PRG3_out
0010 FVR_Buffer2 FVR_Buffer2
0001 CxIN1+ pin CxIN1+ pin
0000 CxIN0+ pin CxIN0+ pin
Note 1: PIC16(L)F1777/9 only.
PIC16(L)F1777/8/9
DS40001819B-page 262 2015-2016 Microchip Technology Inc.
Note: There are no long and short bit name variants for the following mirror register
REGISTER 19-5: CMOUT: COMPARATOR OUTPUT REGISTER
R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0
MC8OUT(1) MC7OUT(1) MC6OUT MC5OUT MC4OUT MC3OUT MC2OUT MC1OUT
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 MC8OUT: Mirror Copy of C8OUT bit(1)
bit 6 MC7OUT: Mirror Copy of C7OUT bit(1)
bit 5 MC6OUT: Mirror Copy of C6OUT bit
bit 4 MC5OUT: Mirror Copy of C5OUT bit
bit 3 MC4OUT: Mirror Copy of C4OUT bit
bit 2 MC3OUT: Mirror Copy of C3OUT bit
bit 1 MC2OUT: Mirror Copy of C2OUT bit
bit 0 MC1OUT: Mirror Copy of C1OUT bit
Note 1: PIC16LF1777/9 only.
2015-2016 Microchip Technology Inc. DS40001819B-page 263
PIC16(L)F1777/8/9
TABLE 19-6: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Pag e
ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177
ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182
ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 187
CM1CON0 ON OUT —POLZLFReserved HYS SYNC 258
CM2CON0 ON OUT —POLZLFReserved HYS SYNC 258
CM3CON0 ON OUT —POLZLFReserved HYS SYNC 258
CM4CON0 ON OUT —POLZLFReserved HYS SYNC 258
CM5CON0 ON OUT —POLZLFReserved HYS SYNC 258
CM6CON0 ON OUT —POLZLFReserved HYS SYNC 258
CM1CON1 —————— INTP INTN 259
CM2CON1 —————— INTP INTN 259
CM3CON1 —————— INTP INTN 259
CM4CON1 —————— INTP INTN 259
CM5CON1 —————— INTP INTN 259
CM6CON1 —————— INTP INTN 259
CM7CON1(1) —————— INTP INTN 259
CM8CON1(1) —————— INTP INTN 259
CM1NSEL ———— NCH<3:0> 260
CM2NSEL ———— NCH<3:0> 260
CM3NSEL ———— NCH<3:0> 260
CM4NSEL ———— NCH<3:0> 260
CM5NSEL ———— NCH<3:0> 260
CM6NSEL ———— NCH<3:0> 260
CM7NSEL(1) ———— NCH<3:0> 260
CM8NSEL(1) ———— NCH<3:0> 260
CM1PSEL ———— PCH<3:0> 261
CM2PSEL ———— PCH<3:0> 261
CM3PSEL ———— PCH<3:0> 261
CM4PSEL ———— PCH<3:0> 261
CM5PSEL ———— PCH<3:0> 261
CM6PSEL ———— PCH<3:0> 261
CM7PSEL(1) ———— PCH<3:0> 261
CM8PSEL(1) ———— PCH<3:0> 261
CMOUT MC8OUT(1) MC7OUT(1) MC6OUT MC5OUT MC4OUT MC3OUT MC2OUT MC1OUT 262
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 223
DAC1CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 249
DAC2CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 249
DAC5CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 249
DAC6CON0(1) EN FM OE1 OE2 PSS<1:0> NSS<1:0> 249
DAC3CON0 EN — OE1 OE2 PSS<1:0> NSS<1:0> 244
DAC4CON0 EN — OE1 OE2 PSS<1:0> NSS<1:0> 244
DAC7CON0 EN — OE1 OE2 PSS<1:0> NSS<1:0> 244
DAC8CON0(1) EN — OE1 OE2 PSS<1:0> NSS<1:0> 244
DAC3REF --- --- --- REF<4:0> 245
DAC4REF --- --- --- REF<4:0> 245
DAC7REF --- --- --- REF<4:0> 245
DAC8REF(1) --- --- --- REF<4:0> 245
DAC1REFH REF<9:x> (x Depends on FM bit) 250
Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.
Note 1: PIC16LF1777/9 only.
PIC16(L)F1777/8/9
DS40001819B-page 264 2015-2016 Microchip Technology Inc.
TABLE 19-4: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE (CONT.)
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Regis ter
on Pa ge
DAC2REFH REF<9:x> (x Depends on FM bit) 250
DAC5REFH REF<9:x> (x Depends on FM bit) 250
DAC6REFH(1) REF<9:x> (x Depends on FM bit) 250
DAC1REFL REF<x-1:0> (x Depends on FM bit) 250
DAC2REFL REF<x-1:0> (x Depends on FM bit) 250
DAC5REFL REF<x-1:0> (x Depends on FM bit) 250
DAC6REFL(1) REF<x-1:0> (x Depends on FM bit) 250
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132
PIE2 OSFIE C2IE C1IE COG1IE BCL1IE C4IE C3IE CCP2IE 134
PIE5 CCP8IE(1) CCP7IE COG4IE(1) COG3IE C8IE(1) C7IE(1) C6IE C5IE 137
PIR2 OSFIF C2IF C1IF COG1IF BCL1IF C4IF C3IF CCP2IF 140
PIR5 CCP8IF(1) CCP7IF COG4IF(1) COG3IF C8IF(1) C7IF(1) C6IF C5IF 143
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186
Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.
Note 1: PIC16LF1777/9 only.
2015-2016 Microchip Technology Inc. DS40001819B-page 265
PIC16(L)F1777/8/9
20.0 ZERO-CROSS DETE CTION
(ZCD) MODULE
The ZCD module detects when an A/C signal crosses
through the ground potential. The actual zero-crossing
threshold is the zero-crossing reference voltage,
ZCPINV, which is typically 0.75V above ground.
The connection to the signal to be detected is through
a series current limiting resistor. The module applies a
current source or sink to the ZCD pin to maintain a
constant voltage on the pin, thereby preventing the pin
voltage from forward biasing the ESD protection
diodes. When the applied voltage is greater than the
reference voltage, the module sinks current. When the
applied voltage is less than the reference voltage, the
module sources current. The current source and sink
action keeps the pin voltage constant over the full
range of the applied voltage. The ZCD module is
shown in the simplified block diagram Figure 20-2.
The ZCD module is useful when monitoring an AC
waveform for, but not limited to, the following purposes:
• A/C period measurement
• Accurate long term time measurement
• Dimmer phase delayed drive
• Low EMI cycle switching
20.1 External Resistor Selection
The ZCD module requires a current limiting resistor in
series with the external voltage source. The impedance
and rating of this resistor depends on the external
source peak voltage. Select a resistor value that will
drop all of the peak voltage when the current through
the resistor is nominally 300 A. Refer to
Equation 20-1 and Figure 20-1. Make sure that the
ZCD I/O pin internal weak pull-up is disabled so it does
not interfere with the current source and sink.
EQUATION 20-1: EXTERNAL RESISTOR
FIGURE 20-1: EXTERNAL VOLTAGE
FIGURE 20-2: SI MPL I FI ED ZCD BLOCK DIAGRAM
Rseries
Vpeak
34–
10
------------------=
Vpeak
ZCPINV
maxpeak
minpeak
ZCD pin
+
-
ZCPINV
External current
limiting resistor
External
voltage
source
Interrupt
det
Interrupt
det
INTP
INTN
Sets
ZCDIF flag
OUT
Q1
DQ
LE
POL
ZCDx_output
VDD
Rseries
Rpullup
Vpullup
optional
Rpulldown
optional
PIC16(L)F1777/8/9
DS40001819B-page 266 2015-2016 Microchip Technology Inc.
20.2 ZCD Logic Output
The ZCD module includes a Status bit, which can be
read to determine whether the current source or sink is
active. The OUT bit of the ZCDCON register is set
when the current sink is active, and cleared when the
current source is active. The OUT bit is affected by the
polarity bit.
20.3 ZCD Logic Polarity
The POL bit of the ZCDxCON register inverts the OUT
bit relative to the current source and sink output. When
the POL bit is set, a OUT high indicates that the current
source is active, and a low output indicates that the
current sink is active.
The POL bit affects the ZCD interrupts. See
Section 20.4 “ZCD Interrupts” .
20.4 ZCD Interrupts
An interrupt will be generated upon a change in the
ZCD logic output when the appropriate interrupt
enables are set. A rising edge detector and a falling
edge detector are present in the ZCD for this purpose.
The ZCDIF bit of the PIR3 register will be set when
either edge detector is triggered and its associated
enable bit is set. The INTP enables rising edge inter-
rupts and the INTN bit enables falling edge interrupts.
Both are located in the ZCDxCON register.
To fully enable the interrupt, the following bits must be
set:
• ZCDIE bit of the PIE3 register
• INTP bit of the ZCDxCON register
(for a rising edge detection)
• INTN bit of the ZCDxCON register
(for a falling edge detection)
• PEIE and GIE bits of the INTCON register
Changing the POL bit will cause an interrupt, regard-
less of the level of the EN bit.
The ZCDIF bit of the PIR3 register must be cleared in
software as part of the interrupt service. If another edge
is detected while this flag is being cleared, the flag will
still be set at the end of the sequence.
20.5 Correcting for ZCPINV Offset
The actual voltage at which the ZCD switches is the
reference voltage at the non-inverting input of the ZCD
op amp. For external voltage source waveforms other
than square waves this voltage offset from zero causes
the zero-cross event to occur either too early or too
late.
20.5.1 CORRECTION BY AC COUPLING
When the external voltage source is sinusoidal, the
effects of the ZCPINV offset can be eliminated by
isolating the external voltage source from the ZCD pin
with a capacitor in addition to the voltage reducing
resistor. The capacitor will cause a phase shift resulting
in the ZCD output switch in advance of the actual
zero-crossing event. The phase shift will be the same
for both rising and falling zero crossings, which can be
compensated for by either delaying the CPU response
to the ZCD switch by a timer or other means, or
selecting a capacitor value large enough that the phase
shift is negligible.
To determine the series resistor and capacitor values
for this configuration, start by computing the
impedance, Z, to obtain a peak current of 300 A. Next,
arbitrarily select a suitably large non-polar capacitor
and compute its reactance, XC, at the external voltage
source frequency. Finally, compute the series resistor,
capacitor peak voltage, and phase shift by the formulas
shown in Equation 20-2.
2015-2016 Microchip Technology Inc. DS40001819B-page 267
PIC16(L)F1777/8/9
EQUATION 20-2: R-C CALCULATIONS EQUATION 20-3: R-C CALCULATIONS
EXAMPLE
Vpeak = external voltage source peak voltage
f = external voltage source frequency
C = series capacitor
R = series resistor
VC= Peak capacitor voltage
= Capacitor induced zero crossing phase
advance in radians
T= Time ZC event occurs before actual zero
crossing
Vrms = 120
ZVPEAK
3x10 4–
-----------------=
XC1
2fC
-----------------=
RZ
2XC
–=
VCXC3x10 4–
=
Tan 1– XC
R
------


=
T
2f
-------------=
f= 60 Hz
C= 0.1 f
R = 560 kOhms
Vpeak Vrms 2169.7==
ZVpeak
310
4–
--------------------169.7
310
4–
--------------------565.7 kOhms===
XC1
2fC
----------------- 1
260 1 10 7–

--------------------------------------------- 26.53 kOhms===
ZRR2Xc2
+560.6 kOhm using actual resi stor==
Ipeak Vpeak
ZR
------------- 3 0 2 . 7 10 6–
==
VCXCIpeak
8.0 V==
Tan 1– XC
R
------

 0.047 radians==
T
2f
-------------125.6 s==
PIC16(L)F1777/8/9
DS40001819B-page 268 2015-2016 Microchip Technology Inc.
20.5.2 CORRECTION BY OFFSET
CURRENT
When the waveform is varying relative to Vss then the
zero cross is detected too early as the waveform falls
and too late as the waveform rises. When the
waveform is varying relative to VDD then the zero cross
is detected too late as the waveform rises and too early
as the waveform falls. The actual offset time can be
determined for sinusoidal waveforms with the
corresponding equations shown in Equation 20-4.
EQUATION 20-4: ZCD EVENT OFFSET
This offset time can be compensated for by adding a
pull-up or pull-down biasing resistor to the ZCD pin. A
pull-up resistor is used when the external voltage
source is varying relative to Vss. A pull-down resistor is
used when the voltage is varying relative to VDD.The
resistor adds a bias to the ZCD pin so that the target
external voltage source must go to zero to pull the pin
voltage to the ZCPINV switching voltage. The pull-up or
pull-down value can be determined with the equations
shown in Equation 20-5.
EQUATION 20-5: ZCD PULL-UP/DOWN
The pull-up and pull-down resistor values are
significantly affected by small variations of ZCPINV.
Measuring ZCPINV can be difficult, especially when the
waveform is relative to VDD. However, by combining
Equation 20-4 and Equation 20-5 the resistor value
can be determined from the time difference between
the ZCDOUT high and low periods. Note that the time
difference, ∆T, is 4 *Toffset. The equation for determining
the pull-up and pull-down resistor values from the high
and low ZCDOUT periods is shown in Equation 20-6.
The ZCDOUT signal can be directly observed on a pin
by routing the ZCDOUT signal through one of the
CLCs.
EQUATION 20-6:
20.6 Handling Vpeak variations
If the peak amplitude of the external voltage is
expected to vary then the series resistor must be
selected to keep the ZCD current source and sink
below the design maximum range of ± 600 A for the
maximum expected voltage and high enough to be
detected accurately at the minimum peak voltage. A
general rule of thumb is that the maximum peak voltage
can be no more than six times the minimum peak
voltage. To ensure that the maximum current does not
exceed ± 600 A and the minimum is at least
±100A, compute the series resistance as shown in
Equation 20-7. The compensating pull-up for this
series resistance can be determined with
Equation 20-5 because the pull-up value is
independent from the peak voltage.
EQUATION 20-7: SERIES R FOR V RANGE
Toffset
Zcpinv
Vpeak
-----------------



asin
2Freq
----------------------------------=
When External Voltage Source is relative to Vss:
Toffset
VDD Zcpinv
–
Vpeak
--------------------------------



asin
2Freq
-------------------------------------------------=
When External Voltage Source is relative to VDD:
Rpullup
Rseries Vpullup Zcpinv
–
Zcpinv
---------------------------------------------------------------------=
When External Signal is relative to Vss:
When External Signal is relative to VDD:
Rpulldown
Rseries Zcpinv

VDD Zcpinv
–
------------------------------------------=
RR
series
Vbias
Vpeak Freq T
2
------------


sin


---------------------------------------------------------------- 1–





=
R is pull-up or pull-down resistor
Vbias is Vpullup when R is pull-up or VDD when R is
pull-down
∆T is the ZCDOUT high and low period difference
Rseries
Vmaxpeak Vminpeak
+
74–
10
------------------------------------------------------------=
2015-2016 Microchip Technology Inc. DS40001819B-page 269
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20.7 Operation During Sleep
The ZCD current sources and interrupts are unaffected
by Sleep.
20.8 Effects of a Reset
The ZCD circuit can be configured to default to the active
or inactive state on Power-on-Reset (POR). When the
ZCD Configuration bit is cleared, the ZCD circuit will be
active at POR. When the ZCD Configuration bit is set,
the ZCDEN bit of the ZCDCON register must be set to
enable the ZCD module.
PIC16(L)F1777/8/9
DS40001819B-page 270 2015-2016 Microchip Technology Inc.
20.9 Register Definitions: ZCD Control
Long bit name prefixes for the zero-cross detect periph-
eral is shown in Table 20-1. Refer to 1.1 .2.2 “Long Bit
Names” for more information
TABLE 20-1:
Peripheral Bit Name Prefix
ZCD1 ZCD1
REGISTER 20-1: ZCDxCON: ZERO-CROSS DETECTION CONTROL REGISTER
R/W-0/0 U-0 R-x/x R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
EN —OUTPOL—— INTP INTN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on configuration bits
bit 7 EN: Zero-Cross Detection Enable bit(1)
1 = Zero-cross detect is enabled. ZCD pin is forced to output to source and sink current.
0 = Zero-cross detect is disabled. ZCD pin operates according to PPS and TRIS controls.
bit 6 Unimplemented: Read as ‘0’
bit 5 OUT: Zero-Cross Detection Logic Level bit
POL bit = 0:
1 = ZCD pin is sinking current
0 = ZCD pin is sourcing current
POL bit = 1:
1 = ZCD pin is sourcing current
0 = ZCD pin is sinking current
bit 4 POL: Zero-Cross Detection Logic Output Polarity bit
1 = ZCD logic output is inverted
0 = ZCD logic output is not inverted
bit 3-2 Unimplemented: Read as ‘0’
bit 1 INTP: Zero-Cross Positive Edge Interrupt Enable bit
1 = ZCDIF bit is set on low-to-high OUT transition
0 = ZCDIF bit is unaffected by low-to-high OUT transition
bit 0 INTN: Zero-Cross Negative Edge Interrupt Enable bit
1 = ZCDIF bit is set on high-to-low OUT transition
0 = ZCDIF bit is unaffected by high-to-low OUT transition
Note 1: The EN bit has no effect when the ZCD Configuration bit is cleared.
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TABLE 20-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE ZCD MODULE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on page
PIE3 — — COG2IE ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE 135
PIR3 — — COG2IF ZCDIF CLC4IF CLC3IF CLC2IF CLC1IF 141
ZCD1CON EN —OUTPOL—— INTP INTN 270
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the ZCD module.
TABLE 20-3: SUMMARY OF CONFIGURATION WORD WITH THE ZCD MODULE
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register
on Page
CONFIG2 13:8 — — LVP DEBUG LPBOR BORV STVREN PLLEN 97
7:0 ZCD — — — — PPS1WAY WRT<1:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the ZCD module.
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21.0 TIMER0 MODULE
The Timer0 module is an 8-bit timer/counter with the
following features:
• 8-bit timer/counter register (TMR0)
• 8-bit prescaler (independent of Watchdog Timer)
• Programmable internal or external clock source
• Programmable external clock edge selection
• Interrupt-on-overflow
• TMR0 can be used to gate Timer1
Figure 21-1 is a block diagram of the Timer0 module.
21.1 Timer0 Operation
The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.
21.1.1 8-BIT TIMER MODE
The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-bit Timer mode is
selected by clearing the TMR0CS bit of the
OPTION_REG register.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
21.1.2 8-BIT COUNTER MODE
In 8-Bit Counter mode, the Timer0 module will increment
on every rising or falling edge of the T0CKI pin.
8-Bit Counter mode using the T0CKI pin is selected by
setting the TMR0CS bit in the OPTION_REG register to
‘1’.
The rising or falling transition of the incrementing edge
for either input source is determined by the TMR0SE bit
in the OPTION_REG register.
FIGURE 21-1: BLOCK DIAGRAM OF THE TIMER0
Note: The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
T0CKI
TMR0SE
TMR0
PS<2:0>
Data Bus
Set TMR0IF
TMR0CS
0
1
0
18
8
8-bit
Prescaler
FOSC/4
PSA
Sync
2 TCY Timer0 overflow
T0CKIPPS
PPS
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21.1.3 SOFTWARE PROGRAMMABLE
PRESCALER
A software programmable prescaler is available for
exclusive use with Timer0. The prescaler is enabled by
clearing the PSA bit of the OPTION_REG register.
There are eight prescaler options for the Timer0 mod-
ule ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION_REG
register. In order to have a 1:1 prescaler value for the
Timer0 module, the prescaler must be disabled by
setting the PSA bit of the OPTION_REG register.
The prescaler is not readable or writable. All instructions
writing to the TMR0 register will clear the prescaler.
21.1.4 TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The TMR0IF
interrupt flag bit of the INTCON register is set every
time the TMR0 register overflows, regardless of
whether or not the Timer0 interrupt is enabled. The
TMR0IF bit can only be cleared in software. The Timer0
interrupt enable is the TMR0IE bit of the INTCON
register.
21.1.5 8-BIT COUNTER MODE
SYNCHRONIZATION
When in 8-Bit Counter mode, the incrementing edge on
the T0CKI pin must be synchronized to the instruction
clock. Synchronization can be accomplished by
sampling the prescaler output on the Q2 and Q4 cycles
of the instruction clock. The high and low periods of the
external clocking source must meet the timing
requirements as shown in Table 36-12: Timer0 and
Timer1 External Clock Requirements.
21.1.6 OPERATION DURING SLEEP
Timer0 cannot operate while the processor is in Sleep
mode. The contents of the TMR0 register will remain
unchanged while the processor is in Sleep mode.
Note: The Watchdog Timer (WDT) uses its own
independent prescaler.
Note: The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
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21.2 Register Definitions: Option Register
TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
REGISTER 21-1: OPTION_REG: OPTION REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 WPUEN: Weak Pull-Up Enable bit
1 = All weak pull-ups are disabled (except MCLR, if it is enabled)
0 = Weak pull-ups are enabled by individual WPUx latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 TMR0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4 TMR0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is not assigned to the Timer0 module
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 274
TMR0 Timer0 Module Register 272*
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.
* Page provides register information.
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Bit Value Timer0 Rate
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22.0 TIMER1/3/5 MODULE WITH
GATE CONTROL
The Timer1 module is a 16-bit timer/counter with the
following features:
• 16-bit timer/counter register pair (TMR1H:TMR1L)
• Programmable internal or external clock source
• 2-bit prescaler
• Dedicated 32 kHz oscillator circuit
• Optionally synchronized comparator out
• Multiple Timer1 gate (count enable) sources
• Interrupt-on-overflow
• Wake-up on overflow (external clock,
Asynchronous mode only)
• Time base for the Capture/Compare function
• Auto-conversion Trigger (with CCP)
• Selectable Gate Source Polarity
• Gate Toggle mode
• Gate Single-pulse mode
• Gate Value Status
• Gate Event Interrupt
Figure 22-1 is a block diagram of the Timer1 module.
This device has three instances of Timer1 type
modules. They include:
•Timer1
•Timer3
•Timer5
FIGURE 22-1: TIMER1 BLOCK DIAGRAM
Note: All references to Timer1 and Timer1 Gate
apply to Timer3 and Timer5.
TMR1H TMR1L
T1SYNC
T1CKPS<1:0>
Prescaler
1, 2, 4, 8
0
1
Synchronized
clock input
2
TMR1(2)
TMR1ON
Note 1: ST Buffer is high speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
T1G
SOSC
FOSC/4
Internal
Clock
SOSCO
SOSCI
T1OSCEN
1
0
T1CKI
TMR1CS<1:0>
(1)
Synchronize(3)
det
Sleep input
TMR1GE
0
1
00
01
10
11
T1GPOL
D
Q
CK
Q
0
1
T1GVAL
T1GTM
Single-Pulse
Acq. Control
T1GSPM
T1GGO/DONE
T1GSS<1:0>
EN
OUT
10
11
00
01
FOSC
Internal
Clock
R
D
EN
Q
Q1
RD
T1GCON
Data Bus
det
Interrupt
TMR1GIF
Set
T1CLK
FOSC/2
Internal
Clock
D
EN
Q
t1g_in
TMR1ON
LFINTOSC
Timer0 overflow
sync_C2OUT
sync_C1OUT
To Comparator Module
To Clock Switching Modules
Set flag bit
TMR1IF on
Overflow
To ADC Auto-Conversion
T1GPPS
PPS
T1CKIPPS
PPS
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22.1 Timer1 Operation
The Timer1 module is a 16-bit incrementing counter
which is accessed through the TMR1H:TMR1L register
pair. Writes to TMR1H or TMR1L directly update the
counter.
When used with an internal clock source, the module is
a timer and increments on every instruction cycle.
When used with an external clock source, the module
can be used as either a timer or counter and incre-
ments on every selected edge of the external source.
Timer1 is enabled by configuring the ON and GE bits in
the T1CON and T1GCON registers, respectively.
Table 22-1 displays the Timer1 enable selections.
22.2 Clock Source Selection
The CS<1:0> and OSCEN bits of the T1CON register
are used to select the clock source for Timer1.
Table 22-2 displays the clock source selections.
22.2.1 INTERNAL CLOCK SOURCE
When the internal clock source is selected, the
TMR1H:TMR1L register pair will increment on multiples
of FOSC as determined by the Timer1 prescaler.
When the FOSC internal clock source is selected, the
Timer1 register value will increment by four counts every
instruction clock cycle. Due to this condition, a 2 LSB
error in resolution will occur when reading the Timer1
value. To utilize the full resolution of Timer1, an
asynchronous input signal must be used to gate the
Timer1 clock input.
The following asynchronous sources may be used:
• Asynchronous event on the T1G pin to Timer1
gate
• C1 or C2 comparator input to Timer1 gate
22.2.2 EXTERNAL CLOCK SOURCE
When the external clock source is selected, the Timer1
module may work as a timer or a counter.
When enabled to count, Timer1 is incremented on the
rising edge of the external clock input T1CKI, which can
be synchronized to the microcontroller system clock or
can run asynchronously.
When used as a timer with a clock oscillator, an
external 32.768 kHz crystal can be used in conjunction
with the dedicated internal oscillator circuit.
TABLE 22-1: TIMER1 ENABLE
SELECTIONS
TMR1ON TMR1GE Timer1
Operation
00Off
01Off
10Always On
11Count Enabled
Note: In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
• Timer1 enabled after POR
• Write to TMR1H or TMR1L
• Timer1 is disabled
• Timer1 is disabled (TMR1ON = 0)
when T1CKI is high then Timer1 is
enabled (TMR1ON=1) when T1CKI is
low.
TABLE 22-2: CLOCK SOURCE SELECTIONS
TMR1CS<1:0> T1OSCEN Clock Source
11 x LFINTOSC
10 0 External Clocking on T1CKI Pin
01 x System Clock (FOSC)
00 x Instruction Clock (FOSC/4)
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22.3 Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
22.4 Timer1 (Secondary) Oscillator
A dedicated low-power 32.768 kHz oscillator circuit is
built-in between pins SOSCI (input) and SOSCO
(amplifier output). This internal circuit is to be used in
conjunction with an external 32.768 kHz crystal.
The oscillator circuit is enabled by setting the OSCEN
bit of the T1CON register. The oscillator will continue to
run during Sleep.
22.5 Timer1 Operation in
Asynchronous Counter Mode
If the control bit SYNC of the T1CON register is set, the
external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If the external clock source is selected then the
timer will continue to run during Sleep and can
generate an interrupt-on-overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 22.5.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
22.5.1 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TMR1L register pair.
22.6 Timer1 Gate
Timer1 can be configured to count freely or the count
can be enabled and disabled using Timer1 gate
circuitry. This is also referred to as Timer1 Gate Enable.
Timer1 gate can also be driven by multiple selectable
sources.
22.6.1 TIMER1 GATE ENABLE
The Timer1 Gate Enable mode is enabled by setting
the GE bit of the T1GCON register. The polarity of the
Timer1 Gate Enable mode is configured using the
GPOL bit of the T1GCON register.
When Timer1 Gate Enable mode is enabled, Timer1
will increment on the rising edge of the Timer1 clock
source. When Timer1 Gate Enable mode is disabled,
no incrementing will occur and Timer1 will hold the
current count. See Figure 22-3 for timing details.
Note: The oscillator requires a start-up and
stabilization time before use. Thus,
OSCEN should be set and a suitable
delay observed prior to using Timer1. A
suitable delay similar to the OST delay
can be implemented in software by
clearing the TMR1IF bit then presetting
the TMR1H:TMR1L register pair to
FC00h. The TMR1IF flag will be set when
1024 clock cycles have elapsed, thereby
indicating that the oscillator is running and
reasonably stable.
Note: When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
TABLE 22-3: TIMER1 GATE ENABLE
SELECTIONS
T1CLK T1GPOL T1G Timer1 Operation
11Counts
10Holds Count
01Holds Count
00Counts
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22.6.2 TIMER1 GATE SOURCE
SELECTION
Timer1 gate source selections are shown in Table 22-4.
Source selection is controlled by the T1GSS bits of the
T1GCON register. The polarity for each available source
is also selectable. Polarity selection is controlled by the
T1GPOL bit of the T1GCON register.
TABLE 22-4: TIMER1 GATE SOURCES
22.6.2.1 T1G Pin Gate Operation
The T1G pin is one source for Timer1 gate control. It
can be used to supply an external source to the Timer1
gate circuitry.
22.6.2.2 Timer0 Overflow Gate Operation
When Timer0 increments from FFh to 00h, a
low-to-high pulse will automatically be generated and
internally supplied to the Timer1 gate circuitry.
22.6.2.3 Comparator C1 Gate Operation
The output resulting from a Comparator 1 operation can
be selected as a source for Timer1 gate control. The
Comparator 1 output (sync_C1OUT) can be
synchronized to the Timer1 clock or left asynchronous.
For more information see Section 19.4.1 “Comp ar ator
Output Synchronization”.
22.6.2.4 Comparator C2 Gate Operation
The output resulting from a Comparator 2 operation
can be selected as a source for Timer1 gate control.
The Comparator 2 output (sync_C2OUT) can be
synchronized to the Timer1 clock or left asynchronous.
For more information see Section 19.4.1 “Comparator
Output Synchronization”.
22.6.3 TIMER1 GATE TOGGLE MODE
When Timer1 Gate Toggle mode is enabled, it is possi-
ble to measure the full-cycle length of a Timer1 gate
signal, as opposed to the duration of a single level
pulse.
The Timer1 gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. See Figure 22-4 for timing details.
Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
22.6.4 TIMER1 GATE SINGLE-PULSE
MODE
When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single-pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the
T1GGO/DONE bit in the T1GCON register must be set.
The Timer1 will be fully enabled on the next
incrementing edge. On the next trailing edge of the
pulse, the T1GGO/DONE bit will automatically be
cleared. No other gate events will be allowed to
increment Timer1 until the T1GGO/DONE bit is once
again set in software. See Figure 22-5 for timing details.
If the Single-Pulse Gate mode is disabled by clearing the
T1GSPM bit in the T1GCON register, the T1GGO/DONE
bit should also be cleared.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1 gate
source to be measured. See Figure 22-6 for timing
details.
22.6.5 TIMER1 GATE VALUE STATUS
When Timer1 Gate Value Status is utilized, it is possible
to read the most current level of the gate control value.
The value is stored in the T1GVAL bit in the T1GCON
register. The T1GVAL bit is valid even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
22.6.6 TIMER1 GATE EVENT INTERRUPT
When Timer1 Gate Event Interrupt is enabled, it is
possible to generate an interrupt upon the completion
of a gate event. When the falling edge of T1GVAL
occurs, the TMR1GIF flag bit in the PIR1 register will be
set. If the TMR1GIE bit in the PIE1 register is set, then
an interrupt will be recognized.
The TMR1GIF flag bit operates even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
T1GSS Timer1 Gate Source
11 Comparator 2 Output sync_C2OUT
(optionally Timer1 synchronized output)
10 Comparator 1 Output sync_C1OUT
(optionally Timer1 synchronized output)
01 Overflow of Timer0
(TMR0 increments from FFh to 00h)
00 Timer1 Gate Pin
Note: Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.
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22.7 Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 register is
set. To enable the interrupt-on-rollover, you must set
these bits:
• ON bit of the T1CON register
• TMR1IE bit of the PIE1 register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
22.8 Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
• ON bit of the T1CON register must be set
• TMR1IE bit of the PIE1 register must be set
• PEIE bit of the INTCON register must be set
•S
YNC bit of the T1CON register must be set
• CS bits of the T1CON register must be configured
• OSCEN bit of the T1CON register must be
configured
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine.
Secondary oscillator will continue to operate in Sleep
regardless of the SYNC bit setting.
22.9 CCP Capture/Compare Time Base
The CCP modules use the TMR1H:TMR1L register
pair as the time base when operating in Capture or
Compare mode.
In Capture mode, the value in the TMR1H:TMR1L
register pair is copied into the CCPR1H:CCPR1L
register pair on a configured event.
In Compare mode, an event is triggered when the value
in the CCPR1H:CCPR1L register pair matches the
value in the TMR1H:TMR1L register pair. This event
can be an Auto-conversion Trigger.
For more information, see Section 24.0
“Capture/Compare/PWM Modules”.
22.10 CCP Auto-Conversion Trigger
When any of the CCP’s are configured to trigger an
auto-conversion, the trigger will clear the
TMR1H:TMR1L register pair. This auto-conversion
does not cause a Timer1 interrupt. The CCP module
may still be configured to generate a CCP interrupt.
In this mode of operation, the CCPR1H:CCPR1L
register pair becomes the period register for Timer1.
Timer1 should be synchronized and FOSC/4 should be
selected as the clock source in order to utilize the
Auto-conversion Trigger. Asynchronous operation of
Timer1 can cause an Auto-conversion Trigger to be
missed.
In the event that a write to TMR1H or TMR1L coincides
with an Auto-conversion Trigger from the CCP, the
write will take precedence.
For more information, see Section 24.2.1 “A uto -Con-
version Trigger”.
FIGURE 22-2: TIMER1 INCREMENTING EDGE
Note: The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
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FIGURE 22-3: TI MER1 GATE ENABLE MODE
FIGURE 22-4: TIMER1 GATE TOGGLE MODE
TMR1GE
T1GPOL
t1g_in
T1CKI
T1GVAL
Timer1 N N + 1 N + 2 N + 3 N + 4
TMR1GE
T1GPOL
T1GTM
t1g_in
T1CKI
T1GVAL
Timer1
N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8
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FIGURE 22-5: TIMER1 GATE SINGLE-PULSE MODE
TMR1GE
T1GPOL
t1g_in
T1CKI
T1GVAL
Timer1 N N + 1 N + 2
T1GSPM
T1GGO/
DONE
Set by software
Cleared by hardware on
falling edge of T1GVAL
Set by hardware on
falling edge of T1GVAL
Cleared by software
Cleared by
software
TMR1GIF
Counting enabled on
rising edge of T1G
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FIGURE 22-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
TMR1GE
T1GPOL
t1g_in
T1CKI
T1GVAL
Timer1 NN + 1
N + 2
T1GSPM
T1GGO/
DONE
Set by software
Cleared by hardware on
falling edge of T1GVAL
Set by hardware on
falling edge of T1GVAL
Cleared by software
Cleared by
software
TMR1GIF
T1GTM
Counting enabled on
rising edge of T1G
N + 4
N + 3
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22.11 Register Definitions: Timer1 Control
Long bit name prefixes for the Timer1 peripherals are
shown in Table 22-5. Refer to Section 1.1.2.2 “Long
Bit Names” for more information
TABLE 22-5:
Peripheral Bit Name Prefix
Timer1 T1
Timer3 T3
Timer5 T5
REGISTER 22-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u U-0 R/W-0/u
CS<1:0> CKPS<1:0> OSCEN(1) SYNC —ON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 CS<1:0>: Timer1 Clock Source Select bits
11 =LFINTOSC
10 = Timer1 clock source is pin or oscillator:(1)
If T1OSCEN = 0:
External clock from T1CKI pin (on the rising edge)
If T1OSCEN = 1:
Crystal oscillator on SOSCI/SOSCO pins
01 = Timer1 clock source is system clock (FOSC)
00 = Timer1 clock source is instruction clock (FOSC/4)
bit 5-4 CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 OSCEN: LP Oscillator Enable Control bit(1)
1 = Dedicated secondary oscillator circuit enabled
0 = Dedicated secondary oscillator circuit disabled
bit 2 SYNC: Timer1 Synchronization Control bit
1 = Do not synchronize asynchronous clock input
0 = Synchronize asynchronous clock input with system clock (FOSC)
bit 1 Unimplemented: Read as ‘0’
bit 0 ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1 and clears Timer1 gate flip-flop
Note 1: Timer1 only. Reserved, do not use for Timer3 and Timer5.
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REGISTER 22-2: T1GCON: TIMER1 GATE CONTROL REGISTER
R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x R/W-0/u R/W-0/u
GE GPOL GTM GSPM GGO/
DONE
GVAL GSS<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware
bit 7 GE: Timer1 Gate Enable bit
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1 = Timer1 counting is controlled by the Timer1 gate function
0 = Timer1 counts regardless of Timer1 gate function
bit 6 GPOL: Timer1 Gate Polarity bit
1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 5 GTM: Timer1 Gate Toggle Mode bit
1 = Timer1 Gate Toggle mode is enabled
0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4 GSPM: Timer1 Gate Single-Pulse Mode bit
1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate
0 = Timer1 Gate Single-Pulse mode is disabled
bit 3 GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit
1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge
0 = Timer1 gate single-pulse acquisition has completed or has not been started
bit 2 GVAL: Timer1 Gate Value Status bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L
Unaffected by Timer1 Gate Enable (TMR1GE)
bit 1-0 GSS<1:0>: Timer1 Gate Source Select bits
11 = Comparator 2 optionally synchronized output (sync_C2OUT)
10 = Comparator 1 optionally synchronized output (sync_C1OUT)
01 = Timer0 overflow output
00 = Timer1 gate pin
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TABLE 22-6: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177
CCPxCON EN —OUT FMT MODE<3:0> 319
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139
TMRxH Holding Register for the Most Significant Byte of the 16-bit TMR1/3/5 Register 275*
TMRxL Holding Register for the Least Significant Byte of the 16-bit TMR1/3/5 Register 275*
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176
TxCON CS<1:0> CKPS<1:0> OSCEN SYNC —ON283
TxGCON GE GPOL GTM GSPM GGO/
DONE
GVAL GSS<1:0> 284
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module.
* Page provides register information.
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23.0 T IMER2/ 4/6/8 MO DULE
The Timer2/4/6/8 modules are 8-bit timers that can
operate as free-running period counters or in
conjunction with external signals that control start, run,
freeze, and reset operation in One-Shot and
Monostable modes of operation. Sophisticated
waveform control such as pulse density modulation are
possible by combining the operation of these timers
with other internal peripherals such as the comparators
and CCP modules. Features of the timer include:
• 8-bit timer register
• 8-bit period register
• Selectable external hardware timer Resets
• Programmable prescaler (1:1 to 1:128)
• Programmable postscaler (1:1 to 1:16)
• Selectable synchronous/asynchronous operation
• Alternate clock sources
• Interrupt-on-period
• Three modes of operation:
- Free Running Period
-One-shot
- Monostable
See Figure 23-1 for a block diagram of Timer2. See
Figure 23-2 for the clock source block diagram.
FIGURE 23-1: TIMER2 BLOCK DIAGRAM
Note: Three identical Timer2 modules are
implemented on this device. The timers are
named Timer2, Timer4, Timer6, and
Timer8. All references to Timer2 apply as
well to Timer4, Timer6 and Timer8. All
references to T2PR apply as well to T4PR,
T6PR and T8PR.
Rev . 10 -000 168B
5/29 /201 4
MODE<3>
Clear ON
TMRx
Comparator
PRx
CKSYNC
ON
OUTPS<3:0>
Postscaler
Set flag bi t
TMRxIF
TMRx_postscaled
CKPOL
4
MODE<4:0>
PSYNC
Prescaler
CKPS<2:0>
3
TMRx_clk
RSEL
R
Sync
(2 Clocks)
Edge Detector
Level Detector
Mode Control
(2 clock Sync)
TMRx_ers
0
1
1
0
Note 1: Signal to the CCP to trigger the PWM pulse
2: See Section 22.5 for description of CCP interaction in the different TMR modes
enable
reset
Sync
Fosc/4
DQ
CCP_pset
MODE<4:1>=10 11
MODE<4:3>=01
PPS
TxINPPS
TxIN
External Reset
Sources
(Table 23-4)
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FIGURE 23-2: TIMER2 CLOCK SOURCE
BLOCK DIAGRAM
23.1 Timer2 Operation
Timer2 operates in three major modes:
• Free Running Period
•One-shot
• Monostable
Within each mode there are several options for starting,
stopping, and reset. Table 23-1 lists the options.
In all modes, the TMR2 count register is incremented
on the rising edge of the clock signal from the program-
mable prescaler. When TMR2 equals T2PR, a high
level is output to the postscaler counter. TMR2 is
cleared on the next clock input.
An external signal from hardware can also be config-
ured to gate the timer operation or force a TMR2 count
Reset. In Gate modes the counter stops when the gate
is disabled and resumes when the gate is enabled. In
Reset modes the TMR2 count is reset on either the
level or edge from the external source.
The TMR2 and T2PR registers are both directly read-
able and writable. The TMR2 register is cleared and the
T2PR register initializes to FFh on any device Reset.
Both the prescaler and postscaler counters are cleared
on the following events:
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset
• External Reset Source event that resets the timer.
23.1.1 FREE RUNNING PERIOD MODE
The value of TMR2 is compared to that of the Period
register, T2PR, on each clock cycle. When the two
values match, the comparator resets the value of TMR2
to 00h on the next cycle and increments the output
postscaler counter. When the postscaler count equals
the value in the OUTPS<4:0> bits of the TMRxCON1
register then a one clock period wide pulse occurs on the
TMR2_postscaled output, and the postscaler count is
cleared.
23.1.2 ONE-SHOT MODE
The One-Shot mode is identical to the Free Running
Period mode except that the ON bit is cleared and the
timer is stopped when TMR2 matches T2PR and will
not restart until the T2ON bit is cycled off and on.
Postscaler OUTPS<4:0> values other than 0 are
meaningless in this mode because the timer is stopped
at the first period event and the postscaler is reset
when the timer is restarted.
23.1.3 MONOSTABLE MODE
Monostable modes are similar to One-Shot modes
except that the ON bit is not cleared and the timer can
be restarted by an external Reset event.
23.2 PRx Period Register
The PRx period register is double buffered, software
reads and writes the PRx register. However, the timer
uses a buffered PRx register for operation. Software
does not have direct access to the buffered PRx
register. The contents of the PRx register is transferred
to the buffer by any of the following events:
• A write to the TMRx register
• A write to the TMRxCON register
• When TMRx = PRx buffer and the prescaler rolls
over
• An external Reset event
23.3 Timer2 Output
The Timer2 module’s primary output is TMR2_posts-
caled, which pulses for a single TMR2_clk period when
the postscaler counter matches the value in the
OUTPS bits of the TMR2xCON register. The T2PR
postscaler is incremented each time the TMR2 value
matches the T2PR value. This signal can be selected
as an input to several other input modules:
• The ADC module, as an Auto-conversion Trigger
• COG, as an auto-shutdown source
Note: TMR2 is not cleared when T2CON is
written.
Rev . 10 -000 169B
5/29 /201 4
TMR2_clk
T
X
IN
TxCLKCON
PPS
T
X
INPPS
Timer Clock Sources
(See Table 23-3)
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In addition, the Timer2 is also used by the CCP module
for pulse generation in PWM mode. Both the actual
TMR2 value as well as other internal signals are sent to
the CCP module to properly clock both the period and
pulse width of the PWM signal. See Section 24.6
“CCP/PWM Clock Selection” for more details on
setting up Timer2 for use with the CCP, as well as the
timing diagrams in Section 23.6 “Operation Exam-
ples” for examples of how the varying Timer2 modes
affect CCP PWM output.
23.4 External Reset Sources
In addition to the clock source, the Timer2 also takes in
an external Reset source. This external Reset source
is selected for Timer2, Timer4, Timer6 and Timer8 with
the T2RST, T4RST, T6RST and T8RST registers,
respectively. This source can control starting and
stopping of the timer, as well as resetting the timer,
depending on which mode the timer is in. The mode of
the timer is controlled by the MODE<4:0> bits of the
TMRxHLT register. Edge-Triggered modes require six
Timer clock periods between external triggers.
Level-Triggered modes require the triggering level to
be at least three Timer clock periods long. External
triggers are ignored while in Debug Freeze mode.
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TABLE 23-1: TIMER2 OPERATING MODES
Mode MODE<4:0> Output
Operation Operation Timer Control
<4:3> <2:0> Start Reset Stop
Free
Running
Period
00
000
Period
Pulse
Software gate (Figure 23-4)ON = 1—ON = 0
001 Hardware gate, active-high
(Figure 23-5)
ON = 1 and
TMRx_ers = 1
—ON = 0 or
TMRx_ers = 0
010 Hardware gate, active-low ON = 1 and
TMRx_ers = 0
—ON = 0 or
TMRx_ers = 1
011
Period
Pulse
with
Hardware
Reset
Rising or falling edge Reset
ON = 1
TMRx_ers ↕
ON = 0100 Rising edge Reset (Figure 23-6) TMRx_ers ↑
101 Falling edge Reset TMRx_ers ↓
110 Low level Reset TMRx_ers = 0ON = 0 or
TMRx_ers = 0
111 High level Reset (Figure 23-7)TMRx_ers = 1ON = 0 or
TMRx_ers = 1
One-shot 01
000 One-shot Software start (Figure 23-8)ON = 1—
ON = 0
or
Next clock
after
TMRx = PRx
(Note 2)
001 Edge
triggered
start
(Note 1)
Rising edge start (Figure 23-9)ON = 1 and
TMRx_ers ↑—
010 Falling edge start ON = 1 and
TMRx_ers ↓—
011 Any edge start ON = 1 and
TMRx_ers ↕—
100 Edge
triggered
start
and
hardware
Reset
(Note 1)
Rising edge start and
Rising edge Reset (Figure 23-10)
ON = 1 and
TMRx_ers ↑TMRx_ers ↑
101 Falling edge start and
Falling edge Reset
ON = 1 and
TMRx_ers ↓TMRx_ers ↓
110 Rising edge start and
Low level Reset (Figure 23-11)
ON = 1 and
TMRx_ers ↑TMRx_ers = 0
111 Falling edge start and
High level Reset
ON = 1 and
TMRx_ers ↓TMRx_ers = 1
Mono-stable
10
000 Reserved
001 Edge
triggered
start
(Note 1)
Rising edge start
(Figure 23-12)
ON = 1 and
TMRx_ers ↑—ON = 0
or
Next clock
after
TMRx = PRx
(Note 3)
010 Falling edge start ON = 1 and
TMRx_ers ↓—
011 Any edge start ON = 1 and
TMRx_ers ↕—
Reserved 100 Reserved
Reserved 101 Reserved
One-shot
110 Level
triggered
start
and
hardware
Reset
High level start and
Low level Reset (Figure 23-13)
ON = 1 and
TMRx_ers = 1TMRx_ers = 0
ON = 0 or
Held in Reset
(Note 2)
111 Low level start &
High level Reset
ON = 1 and
TMRx_ers = 0TMRx_ers = 1
Reserved 11 xxx Reserved
Note 1: If ON = 0 then an edge is required to restart the timer after ON = 1.
2: When TMRx = PRx then the next clock clears ON and stops TMRx at 00h.
3: When TMRx = PRx then the next clock stops TMRx at 00h but does not clear ON.
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23.5 Timer2 Interrupt
Timer2 can also generate a device interrupt. The
interrupt is generated when the postscaler counter
matches one of 16 postscale options (from 1:1 through
1:16), which are selected with the postscaler control
bits, OUTPS<3:0> of the T2CON register. The interrupt
is enabled by setting the TMR2IE interrupt enable bit of
the PIE1 register. Interrupt timing is illustrated in
Figure 23-3.
FIGURE 23-3: TIMER2 PRESCALER , POSTSCALER, AND INTERRUPT TIMING DIAGRAM
Rev. 10-000205A
4/7/2016
TMRx_clk
PRx
TMRx
1
0
CKPS 0b010
TMRx_postscaled
OUTPS 0b0001
10 1 0 1 0
TMRxIF (1)
Note 1: Setting the interrupt flag is synchronized with the instruction clock.
Synchronization may take as many as 2 instruction cycles
2: Cleared by software.
(1) (2)
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23.6 Operation Examples
Unless otherwise specified, the following notes apply to
the following timing diagrams:
- Both the prescaler and postscaler are set to
1:1 (both the CKPS and OUTPS bits in the
TxCON register are cleared).
- The diagrams illustrate any clock except
Fosc/4 and show clock-sync delays of at
least two full cycles for both ON and
Timer2_ers. When using Fosc/4, the
clock-sync delay is at least one instruction
period for Timer2_ers; ON applies in the next
instruction period.
- The PWM Duty Cycle and PWM output are
illustrated assuming that the timer is used for
the PWM function of the CCP module as
described in Section 24.6 “CCP/PWM Clock
Selection”. The signals are not a part of the
Timer2 module.
23.6.1 SOFTWARE GATE MODE
This mode corresponds to legacy Timer2 operation.
The timer increments with each clock input when
ON = 1 and does not increment when ON = 0. When
the TMRx count equals the PRx period count the timer
resets on the next clock and continues counting from 0.
Operation with the ON bit software controlled is illus-
trated in Figure 23-4. With PRx = 5, the counter
advances until TMRx = 5, and goes to zero with the
next clock.
FIGURE 23-4: SOFTWARE GATE MODE TIMING DIAGRAM (MODE = 00000)
Rev. 10-000195B
5/30/2014
TMRx_clk
Instruction(1)
ON
PRx
TMRx
TMRx_postscaled
BSF BCF BSF
5
0 12345012 2 345
MODE 0b00000
3 4 5 0 1 0 1
PWM Duty
Cycle 3
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
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23.6.2 HARDWARE GATE MODE
The Hardware Gate modes operate the same as the
Software Gate mode except the TMRx_ers external
signal can also gate the timer. When used with the CCP
the gating extends the PWM period. If the timer is
stopped when the PWM output is high then the duty
cycle is also extended.
When MODE<4:0> = 00001 then the timer is stopped
when the external signal is high. When
MODE<4:0> = 00010 then the timer is stopped when
the external signal is low.
Figure 23-5 illustrates the Hardware Gating mode for
MODE<4:0> = 00001 in which a high input level starts
the counter.
FIGURE 23-5: HARDWARE GATE MODE TIMING DIAGRAM (MODE = 00001)
Rev . 10 -000 196B
5/ 30 /201 4
TMRx_clk
TMRx_ers
PRx
TMRx
TMRx_postscaled
5
MODE 0b00001
0 1234501 2 34501
PWM Duty
Cycle 3
PWM Output
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23.6.3 EDGE-TRIGGERED HARDWARE
LIMIT MODE
In Hardware Limit mode the timer can be reset by the
TMRx_ers external signal before the timer reaches the
period count. Three types of Resets are possible:
• Reset on rising or falling edge
(MODE<4:0>= 00011)
• Reset on rising edge (MODE<4:0> = 00100)
• Reset on falling edge (MODE<4:0> = 00101)
When the timer is used in conjunction with the CCP in
PWM mode then an early Reset shortens the period
and restarts the PWM pulse after a two clock delay.
Refer to Figure 23-6.
FIGURE 23-6: EDGE-TRIGGERE D HARDWA RE LIMIT MODE TIMING DIAGRAM
(MODE = 00100)
Rev . 10 -000 197B
5/30 /201 4
TMRx_clk
ON
PRx
TMRx
BS F BC F BS F
5
0 12 0 123450 450
MODE 0b00100
TMRx_ers
12 3 1
TMRx_postscaled
PWM Duty
Cycle 3
PWM Output
Instruction(1)
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
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23.6.4 LEVEL-TRIGGERED HARDWARE
LIMIT MODE
In the Level-Triggered Hardware Limit Timer modes the
counter is reset by high or low levels of the external
signal TMRx_ers, as shown in Figure 23-7. Selecting
MODE<4:0> = 00110 will cause the timer to reset on a
low level external signal. Selecting
MODE<4:0> = 00111 will cause the timer to reset on a
high level external signal. In the example, the counter
is reset while TMRx_ers = 1. ON is controlled by BSF
and BCF instructions. When ON = 0 the external signal
is ignored.
When the CCP uses the timer as the PWM time base
then the PWM output will be set high when the timer
starts counting and then set low only when the timer
count matches the CCPRx value. The timer is reset
when either the timer count matches the PRx value or
two clock periods after the external Reset signal goes
true and stays true.
The timer starts counting, and the PWM output is set
high, on either the clock following the PRx match or two
clocks after the external Reset signal relinquishes the
Reset. The PWM output will remain high until the timer
counts up to match the CCPRx pulse width value. If the
external Reset signal goes true while the PWM output
is high then the PWM output will remain high until the
Reset signal is released allowing the timer to count up
to match the CCPRx value.
FIGURE 23-7: LEVEL-TRI GGERED HARDWARE LIMIT MODE TIMING DIAGRAM
(MODE = 00111)
Rev. 10-000198B
5/30/2014
TMRx_clk
ON
PRx
TMRx
BSF BCF BSF
5
012 0 12345 123
MODE 0b00111
TMRx_ers
00 4
TMRx_postscaled
50
PWM Duty
Cycle 3
PWM Output
Instruction(1)
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
2015-2016 Microchip Technology Inc. DS40001819B-page 295
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23.6.5 SOFTWARE START ONE-SHOT
MODE
In One-Shot mode the timer resets and the ON bit is
cleared when the timer value matches the PRx period
value. The ON bit must be set by software to start
another timer cycle. Setting MODE<4:0> = 01000
selects One-Shot mode which is illustrated in
Figure 23-8. In the example, ON is controlled by BSF
and BCF instructions. In the first case, a BSF instruction
sets ON and the counter runs to completion and clears
ON. In the second case, a BSF instruction starts the
cycle, BCF/BSF instructions turn the counter off and on
during the cycle, and then it runs to completion.
When One-Shot mode is used in conjunction with the
CCP PWM operation the PWM pulse drive starts con-
current with setting the ON bit. Clearing the ON bit
while the PWM drive is active will extend the PWM
drive. The PWM drive will terminate when the timer
value matches the CCPRx pulse width value. The
PWM drive will remain off until software sets the ON bit
to start another cycle. If software clears the ON bit after
the CCPRx match but before the PRx match then the
PWM drive will be extended by the length of time the
ON bit remains cleared. Another timing cycle can only
be initiated by setting the ON bit after it has been
cleared by a PRx period count match.
FIGURE 23-8: SOFTWARE START ONE-SHOT MODE TIMING DIAGRAM (MODE = 01000)
Rev. 10-000199B
4/7/2016
TMRx_clk
ON
PRx
TMRx
BSF BSF
5
0123450 431
MODE 0b01000
2 5 0
TMRx_postscaled
BCF BSF
PWM Duty
Cycle 3
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions
executed by the CPU to set or clear the ON bit of TxCON. CPU
execution is asynchronous to the timer clock input.
Instruction(1)
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23.6.6 EDGE-TRIGGERED ONE-SHOT
MODE
The Edge-Triggered One-Shot modes start the timer
on an edge from the external signal input, after the ON
bit is set, and clear the ON bit when the timer matches
the PRx period value. The following edges will start the
timer:
• Rising edge (MODE<4:0> = 01001)
• Falling edge (MODE<4:0> = 01010)
• Rising or Falling edge (MODE<4:0> = 01011)
If the timer is halted by clearing the ON bit then another
TMRx_ers edge is required after the ON bit is set to
resume counting. Figure 23-9 illustrates operation in
the rising edge One-Shot mode.
When Edge-Triggered One-Shot mode is used in con-
junction with the CCP then the edge-trigger will activate
the PWM drive and the PWM drive will deactivate when
the timer matches the CCPRx pulse width value and
stay deactivated when the timer halts at the PRx period
count match.
FIGURE 23-9: EDGE-TRIGGERE D ONE-SHOT MODE TIMING DIAGRAM (MODE = 01001)
Rev. 10-000200B
5/19/2016
TMRx_clk
ON
PRx
TMRx
BSF BSF
5
012345 0 1
MODE 0b01001
2
CCP_pset
TMRx_postscaled
BCF
TMRx_ers
PWM Duty
Cycle 3
PWM Output
Instruction(1)
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
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23.6.7 EDGE-TRIGGERED HARDWARE
LIMIT ONE-SHOT MODE
In Edge-Triggered Hardware Limit One-Shot modes
the timer starts on the first external signal edge after
the ON bit is set and resets on all subsequent edges.
Only the first edge after the ON bit is set is needed to
start the timer. The counter will resume counting
automatically two clocks after all subsequent external
Reset edges. Edge triggers are as follows:
• Rising edge start and Reset
(MODE<4:0> = 01100)
• Falling edge start and Reset
(MODE<4:0> = 01101)
The timer resets and clears the ON bit when the timer
value matches the PRx period value. External signal
edges will have no effect until after software sets the
ON bit. Figure 23-10 illustrates the rising edge hard-
ware limit one-shot operation.
When this mode is used in conjunction with the CCP
then the first starting edge trigger, and all subsequent
Reset edges, will activate the PWM drive. The PWM
drive will deactivate when the timer matches the
CCPRx pulse-width value and stay deactivated until
the timer halts at the PRx period match unless an exter-
nal signal edge resets the timer before the match
occurs.
2015-2016 Microchip Technology Inc. DS40001819B-page 298
PIC16(L)F1777/8/9
FIGURE 23-10: EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 01100)
Rev. 10-000201B
4/7/2016
TMRx_clk
ON
PRx
TMRx
BSF BSF
5
0 12345 0 01
MODE 0b01100
2
TMRx_postscaled
TMRx_ers
1 2 3 4 5 0
PWM Duty
Cycle 3
PWM Output
Instruction(1)
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
2015-2016 Microchip Technology Inc. DS40001819B-page 299
PIC16(L)F1777/8/9
23.6.8 LEVEL RESET, EDGE-TRIGGERED
HARDWARE LIMIT ONE-SHOT
MODES
In Level -Triggered One-Shot mode the timer count is
reset on the external signal level and starts counting
on the rising/falling edge of the transition from Reset
level to the active level while the ON bit is set. Reset
levels are selected as follows:
• Low Reset level (MODE<4:0> = 01110)
• High Reset level (MODE<4:0> = 01111)
When the timer count matches the PRx period count,
the timer is reset and the ON bit is cleared. When the
ON bit is cleared by either a PRx match or by software
control a new external signal edge is required after the
ON bit is set to start the counter.
When Level-Triggered Reset One-Shot mode is used
in conjunction with the CCP PWM operation the PWM
drive goes active with the external signal edge that
starts the timer. The PWM drive goes inactive when the
timer count equals the CCPRx pulse width count. The
PWM drive does not go active when the timer count
clears at the PRx period count match.
2015-2016 Microchip Technology Inc. DS40001819B-page 300
PIC16(L)F1777/8/9
FIGURE 23-11: LOW LEVEL RESET, EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 01110)
Rev. 10-000202B
4/7/2016
TMRx_clk
ON
PRx
TMRx
BSF BSF
5
0 12345 0 01
MODE 0b01110
TMRx_postscaled
TMRx_ers
1 2 3 4 0
PWM Duty
Cycle 3
PWM Output
5
Instruction(1)
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
2015-2016 Microchip Technology Inc. DS40001819B-page 301
PIC16(L)F1777/8/9
23.6.9 EDGE-TRIGGERED MONOSTABLE
MODES
The Edge-Triggered Monostable modes start the timer
on an edge from the external Reset signal input, after
the ON bit is set, and stop incrementing the timer when
the timer matches the PRx period value. The following
edges will start the timer:
• Rising edge (MODE<4:0> = 10001)
• Falling edge (MODE<4:0> = 10010)
• Rising or Falling edge (MODE<4:0> = 10011)
When an Edge-Triggered Monostable mode is used in
conjunction with the CCP PWM operation the PWM
drive goes active with the external Reset signal edge
that starts the timer, but will not go active when the
timer matches the PRx value. While the timer is incre-
menting, additional edges on the external Reset signal
will not affect the CCP PWM.
2015-2016 Microchip Technology Inc. DS40001819B-page 302
PIC16(L)F1777/8/9
FIGURE 23-12: RISING EDGE-TRIGGERED MONOSTABLE MODE TIMING DIAGRAM (MODE = 10001)
Rev. 10-000203A
4/7/2016
TMRx_clk
ON
PRx
TMRx
BSF BCF
5
0 12345 0 1
MODE 0b10001
TMRx_postscaled
TMRx_ers
2 3 4 5 0
PWM Duty
Cycle 3
PWM Output
Instruction(1)
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
BSF BCF BSF
1 2 3 4 5 0
2015-2016 Microchip Technology Inc. DS40001819B-page 303
PIC16(L)F1777/8/9
23.6.10 LEVEL-TRIGGERED HARDWARE
LIMIT ONE-SHOT MODES
The Level-Triggered Hardware Limit One-Shot modes
hold the timer in Reset on an external Reset level and
start counting when both the ON bit is set and the exter-
nal signal is not at the Reset level. If one of either the
external signal is not in Reset or the ON bit is set then
the other signal being set/made active will start the
timer. Reset levels are selected as follows:
• Low Reset level (MODE<4:0> = 10110)
• High Reset level (MODE<4:0> = 10111)
When the timer count matches the PRx period count,
the timer is reset and the ON bit is cleared. When the
ON bit is cleared by either a PRx match or by software
control the timer will stay in Reset until both the ON bit
is set and the external signal is not at the Reset level.
When Level-Triggered Hardware Limit One-Shot
modes are used in conjunction with the CCP PWM
operation the PWM drive goes active with either the
external signal edge or the setting of the ON bit,
whichever of the two starts the timer.
2015-2016 Microchip Technology Inc. DS40001819B-page 304
PIC16(L)F1777/8/9
FIGURE 23-13: LEVEL-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 10110)
Rev. 10-000204A
4/7/2016
TMR2_clk
Instruction
(1)
ON
PRx
TMRx
BSF BSF
5
0 12345 0 1
MODE 0b10110
TMR2_postscaled
TMR2_ers
2 1 20
PWM Duty
Cycle ‘D3
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
3 3 4 5 0
BSFBCF
2015-2016 Microchip Technology Inc. DS40001819B-page 305
PIC16(L)F1777/8/9
23.7 PR2 Period Register
The PR2 period register (T2PR) is double-buffered.
Software reads and writes the PR2 register. However,
the timer uses a buffered PR2 register for operation.
Software does not have direct access to the buffered
PR2 register. The contents of the PR2 register are
transferred to the buffer by any of the following events:
• A write to the TMR2 register
• A write to the TMR2CON register
• When TMR2 = PR2 buffer and the prescaler rolls
over
• An external Reset event
23.8 Timer2 Operation During Sleep
When PSYNC = 1, Timer2 cannot be operated while
the processor is in Sleep mode. The contents of the
TMR2 and T2PR registers will remain unchanged while
processor is in Sleep mode.
When PSYNC = 0, Timer2 will operate in Sleep as long
as the clock source selected is also still running.
Selecting the LFINTOSC, MFINTOSC, or HFINTOSC
oscillator as the timer clock source will keep the
selected oscillator running during Sleep.
PIC16(L)F1777/8/9
DS40001819B-page 306 2015-2016 Microchip Technology Inc.
23.9 Regis t er D e finiti o n s : Tim e r2 / 4/6/8 C o n trol
Long bit name prefixes for the Timer2/4/6/8 peripherals
are shown in Table 23-2. Refer to Section 1.1.2.2
“Long Bit Names” for more information
TABLE 23-2:
Peripheral Bit Name Prefix
Timer2 T2
Timer4 T4
Timer6 T6
Timer8 T8
REGISTER 23-1: TxCLKCON: TIMERx CLOCK SELECTION REGISTER
U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — —CS<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 CS<3:0>: Timerx Clock Selection bits
See Table 23-3.
TABLE 23-3: TIMERX CLOCK SOURCES
CS<3:0> Timer2 Timer4 Timer6 Timer8
1100-1111 Reserved Reserved Reserved Reserved
1011 LC4_out LC4_out LC4_out LC4_out
1010 LC3_out LC3_out LC3_out LC3_out
1001 LC2_out LC2_out LC2_out LC2_out
1000 LC1_out LC1_out LC1_out LC1_out
0111 ZCD_out ZCD_out ZCD_out ZCD_out
0110 SOSC SOSC SOSC SOSC
0101 MFINTOSC MFINTOSC MFINTOSC MFINTOSC
0100 LFINTOSC LFINTOSC LFINTOSC LFINTOSC
0011 HFINTOSC HFINTOSC HFINTOSC HFINTOSC
0010 Fosc Fosc Fosc Fosc
0001 Fosc/4 Fosc/4 Fosc/4 Fosc/4
0000 Pin selected by T2INPPS Pin selected by T4INPPS Pin selected by T6INPPS Pin selected by T8INPPS
2015-2016 Microchip Technology Inc. DS40001819B-page 307
PIC16(L)F1777/8/9
REGISTER 23-2: TxCON: TIMERx CONTROL REGISTER
R/W/HC-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ON(1) CKPS<2:0> OUTPS<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware
bit 7 ON: Timerx On bit
1 = Timerx is on
0 = Timerx is off: all counters and state machines are reset
bit 6-4 CKPS<2:0>: Timer2-type Clock Prescale Select bits
111 = 1:128 Prescaler
110 = 1:64 Prescaler
101 = 1:32 Prescaler
100 = 1:16 Prescaler
011 =1:8 Prescaler
010 =1:4 Prescaler
001 =1:2 Prescaler
000 =1:1 Prescaler
bit 3-0 OUTPS<3:0>: Timerx Output Postscaler Select bits
1111 = 1:16 Postscaler
1110 = 1:15 Postscaler
1101 = 1:14 Postscaler
1100 = 1:13 Postscaler
1011 = 1:12 Postscaler
1010 = 1:11 Postscaler
1001 = 1:10 Postscaler
1000 = 1:9 Postscaler
0111 = 1:8 Postscaler
0110 = 1:7 Postscaler
0101 = 1:6 Postscaler
0100 = 1:5 Postscaler
0011 = 1:4 Postscaler
0010 = 1:3 Postscaler
0001 = 1:2 Postscaler
0000 = 1:1 Postscaler
Note 1: In certain modes, the ON bit will be auto-cleared by hardware. See Section 23.6 “Opera tion Exam ples”.
PIC16(L)F1777/8/9
DS40001819B-page 308 2015-2016 Microchip Technology Inc.
REGISTER 23-3: TxHLT: TIMERx HARDWARE LIMIT CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
PSYNC(1, 2) CKPOL(3) CKSYNC(4, 5) MODE<4:0>(6, 7)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 PSYNC: Timerx Prescaler Synchronization Enable bit(1, 2)
1 = TMRx Prescaler Output is synchronized to Fosc/4
0 = TMRx Prescaler Output is not synchronized to Fosc/4
bit 6 CKPOL: Timerx Clock Polarity Selection bit(3)
1 = Falling edge of input clock clocks timer/prescaler
0 = Rising edge of input clock clocks timer/prescaler
bit 5 CKSYNC: Timerx Clock Synchronization Enable bit(4, 5)
1 = ON register bit is synchronized to TMR2_clk input
0 = ON register bit is not synchronized to TMR2_clk input
bit 4-0 MODE<4:0>: Timerx Control Mode Selection bits(6, 7)
See Table 23-1.
Note 1: Setting this bit ensures that reading TMRx will return a valid value.
2: When this bit is ‘1’, Timer2 cannot operate in Sleep mode.
3: CKPOL should not be changed while ON = 1.
4: Setting this bit ensures glitch-free operation when the ON is enabled or disabled.
5: When this bit is set then the timer operation will be delayed by two TMRx input clocks after the ON bit is set.
6: Unless otherwise indicated, all modes start upon ON = 1 and stop upon ON = 0 (stops occur without affect-
ing the value of TMRx).
7: When TMRx = PRx, the next clock clears TMRx, regardless of the operating mode.
2015-2016 Microchip Technology Inc. DS40001819B-page 309
PIC16(L)F1777/8/9
REGISTER 23-4: TXRST: TIMERX EXTERNAL RESET SIGNAL SELECTION REGISTER
U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — RSEL<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 RSEL<4:0>: TimerX External Reset Signal Source Selection bits
See Table 23-4.
TABLE 23-4: EXTERNAL RESET SOURCES
RSEL<4:0> Timer2 Timer4 Timer6 Timer8
11111 Reserved Reserved Reserved Reserved
11110 Reserved Reserved Reserved Reserved
11101 LC4_out LC4_out LC4_out LC4_out
11100 LC3_out LC3_out LC3_out LC3_out
11011 LC2_out LC2_out LC2_out LC2_out
11010 LC1_out LC1_out LC1_out LC1_out
11001 ZCD_out ZCD_out ZCD_out ZCD_out
11000(1) sync_C8OUT sync_C8OUT sync_C8OUT sync_C8OUT
10111(1) sync_C7OUT sync_C7OUT sync_C7OUT sync_C7OUT
10110 sync_C6OUT sync_C6OUT sync_C6OUT sync_C6OUT
10101 sync_C5OUT sync_C5OUT sync_C5OUT sync_C5OUT
10100 sync_C4OUT sync_C4OUT sync_C4OUT sync_C4OUT
10011 sync_C3OUT sync_C3OUT sync_C3OUT sync_C3OUT
10010 sync_C2OUT sync_C2OUT sync_C2OUT sync_C2OUT
10001 sync_C1OUT sync_C1OUT sync_C1OUT sync_C1OUT
10000(1) PWM12_out PWM12_out PWM12_out PWM12_out
01111 PWM11_out PWM11_out PWM11_out PWM11_out
01110 PWM6_out PWM6_out PWM6_out PWM6_out
01101 PWM5_out PWM5_out PWM5_out PWM5_out
01100(1) PWM10_out PWM10_out PWM10_out PWM10_out
01011 PWM9_out PWM9_out PWM9_out PWM9_out
01010 PWM4_out PWM4_out PWM4_out PWM4_out
01001 PWM3_out PWM3_out PWM3_out PWM3_out
01000(1) CCP8_out CCP8_out CCP8_out CCP8_out
00111 CCP7_out CCP7_out CCP7_out CCP7_out
00110 CCP2_out CCP2_out CCP2_out CCP2_out
00101 CCP1_out CCP1_out CCP1_out CCP1_out
00100 TMR8_postscaled TMR8_postscaled TMR8_postscaled Reserved
00011 TMR6_postscaled TMR6_postscaled Reserved TMR6_postscaled
00010 TMR4_postscaled Reserved TMR4_postscaled TMR4_postscaled
00001 Reserved TMR2_postscaled TMR2_postscaled TMR2_postscaled
00000 Pin selected byT2INPPS Pin selected by T4INPPS Pin selected by T6INPPS Pin selected by T6INPPS
Note 1: PIC16LF1777/9 only.
PIC16(L)F1777/8/9
DS40001819B-page 310 2015-2016 Microchip Technology Inc.
TABLE 23-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Pa ge
CCP1CON EN —OUT FMT MODE<3:0> 319
CCP2CON EN — OUT FMT MODE<3:0> 319
CCP7CON EN — OUT FMT MODE<3:0> 319
CCP8CON(1) EN — OUT FMT MODE<3:0> 319
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139
T2PR Timer2 Module Period Register 287*
TMR2 Holding Register for the 8-bit TMR2 Register 287*
T2CON ON CKPS<2:0> OUTPS<3:0> 307
T2CLKCON ———— CS<3:0> 306
T2RST — — — RSEL<4:0> 309
T2HLT PSYNC CKPOL CKSYNC MODE<4:0> 308
T4PR Timer4 Module Period Register 287*
TMR4 Holding Register for the 8-bit TMR4 Register 287*
T4CON ON CKPS<2:0> OUTPS<3:0> 307
T4CLKCON ———— CS<3:0> 306
T4RST — — — RSEL<4:0> 309
T4HLT PSYNC CKPOL CKSYNC MODE<4:0> 308
T6PR Timer6 Module Period Register 287*
TMR6 Holding Register for the 8-bit TMR6 Register 287*
T6CON ON CKPS<2:0> OUTPS<3:0> 307
T6CLKCON ———— CS<3:0> 306
T6RST — — — RSEL<4:0> 309
T6HLT PSYNC CKPOL CKSYNC MODE<4:0> 308
T8PR Timer6 Module Period Register 287*
TMR8 Holding Register for the 8-bit TMR6 Register 287*
T8CON ON CKPS<2:0> OUTPS<3:0> 307
T8CLKCON ———— CS<3:0> 306
T8RST — — — RSEL<4:0> 309
T8HLT PSYNC CKPOL CKSYNC MODE<4:0> 308
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module.
* Page provides register information.
Note 1: PIC16LF1777/9 only.
2015-2016 Microchip Technology Inc. DS40001819B-page 311
PIC16(L)F1777/8/9
24.0 CAPTURE/COMPARE/PWM
MODULES
The Capture/Compare/PWM module is a peripheral
which allows the user to time and control different
events, and to generate Pulse-Width Modulation
(PWM) signals. In Capture mode, the peripheral allows
the timing of the duration of an event. The Compare
mode allows the user to trigger an external event when
a predetermined amount of time has expired. The
PWM mode can generate Pulse-Width Modulated
signals of varying frequency and duty cycle.
24.1 Capture Mode
The Capture mode function described in this section is
available and identical for all CCP modules.
Capture mode makes use of the 16-bit Timer1
resource. When an event occurs on the CCPx input,
the 16-bit CCPRxH:CCPRxL register pair captures and
stores the 16-bit value of the TMR1H:TMR1L register
pair, respectively. An event is defined as one of the
following and is configured by the MODE<3:0> bits of
the CCPxCON register:
• Every edge (rising or falling)
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
The CCPx capture input signal is configured by the
CTS bits of the CCPxCAP register with the following
options:
• CCPx pin
• Comparator 1 output (C1_OUT_sync)
• Comparator 2 output (C2_OUT_sync)
• Comparator 7 output (C7_OUT_sync)
• Comparator 8 output (C8_OUT_sync)
(PIC16(L)F1777/9 only)
• LC2_output
• LC3_output
• Interrupt-on-change interrupt trigger
(IOC_interrupt)
When a capture is made, the Interrupt Request Flag bit
CCPxIF of the PIRx register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPRxH:CCPRxL register pair
is read, the old captured value is overwritten by the new
captured value.
Figure 24-1 shows a simplified diagram of the capture
operation.
24.1.1 CCP PIN CONFIGURATION
In Capture mode, select the interrupt source using the
CTS bits of the CCPxCAP register. If the CCPx pin is
chosen, it should be configured as an input by setting
the associated TRIS control bit.
TABLE 24-1: AVAILABLE CCP MODULES
Device CCP1 CCP2 CCP7 CCP8
PIC16(L)F1778 ●●●
PIC16(L)F1777/9 ●●●●
Note 1: In devices with more than one CCP
module, it is very important to pay close
attention to the register names used. A
number placed after the module acronym
is used to distinguish between separate
modules. For example, the CCP1CON
and CCP2CON control the same
operational aspects of two completely
different CCP modules.
2: Throughout this section, generic
references to a CCP module in any of its
operating modes may be interpreted as
being equally applicable to a CCPx
module. Register names, module signals,
I/O pins, and bit names may use the
generic designator ‘x’ to indicate the use of
a numeral to distinguish a particular
module, when required.
Note: If the CCPx pin is configured as an output,
a write to the port can cause a capture
condition.
PIC16(L)F1777/8/9
DS40001819B-page 312 2015-2016 Microchip Technology Inc.
FIGURE 24-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
24.1.2 TIMER1 MODE RESOURCE
Timer1 must be running in Timer mode or Synchronized
Counter mode for the CCP module to use the capture
feature. In Asynchronous Counter mode, the capture
operation may not work.
See Section 22.0 “Timer1/3/5 Module with Gate
Control” for more information on configuring Timer1.
24.1.3 SOFTWARE INTERRUPT MODE
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit of the PIEx register clear to
avoid false interrupts. Additionally, the user should
clear the CCPxIF interrupt flag bit of the PIRx register
following any change in operating mode.
24.1.4 CCP PRESCALER
There are four prescaler settings specified by the
MODE<3:0> bits of the CCPxCON register. Whenever
the CCP module is turned off, or the CCP module is not
in Capture mode, the prescaler counter is cleared. Any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the EN bit of the CCPxCON register before
changing the prescaler.
24.1.5 CAPTURE DURING SLEEP
Capture mode depends upon the Timer1 module for
proper operation. There are two options for driving the
Timer1 module in Capture mode. It can be driven by the
instruction clock (FOSC/4), or by an external clock source.
When Timer1 is clocked by FOSC/4, Timer1 will not
increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
Capture mode will operate during Sleep when Timer1
is clocked by an external clock source.
24.1.6 ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the PPS controls. See
Section 12.0 “Peripheral Pin Select (PPS) Module”
for more details.
24.1.7 CAPTURE OUTPUT
Whenever a capture occurs, the output of the CCP will
go high for a period equal to one system clock period
(1/FOSC). This output is available as an input signal to
the following peripherals:
• ADC Trigger
•COG
•PRG
•DSM
•CLC
• Op Amp override
• Timer2/4/6/8 Reset
• Any device pins
In addition, the CCP output can be output to any pin
with that pin’s PPS control.
Rev . 10 -000 158E
9/5/ 201 4
CCPRxH CCPRxL
TMR1H TMR1L
16
16
Prescal er
1,4,16
CCPx
TRIS Control
set CCPxIF
CCPx MODE <3:0>
and
Edge Detect
RxyPP S
CTS<2:0> PPS
PPS
CCPxPPS
Note: Capture sources. See Register 24-4.
Note: Clocking Timer1 from the system clock
(FOSC) should not be used in Capture
mode. In order for Capture mode to
recognize the trigger event on the CCPx
pin, Timer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
2015-2016 Microchip Technology Inc. DS40001819B-page 313
PIC16(L)F1777/8/9
24.2 Compare Mode
The Compare mode function described in this section
is available and identical for all CCP modules.
Compare mode makes use of the 16-bit Timer1
resource. The 16-bit value of the CCPRxH:CCPRxL
register pair is constantly compared against the 16-bit
value of the TMR1H:TMR1L register pair. When a
match occurs, one of the following events can occur:
• Toggle the CCPx output
• Set the CCPx output
• Clear the CCPx output
• Pulse the CCPx output
• Generate a Software Interrupt
• Auto-conversion Trigger
The action on the pin is based on the value of the
MODE<3:0> control bits of the CCPxCON register. At
the same time, the interrupt flag CCPxIF bit is set.
All Compare modes can generate an interrupt.
Figure 24-2 shows a simplified diagram of the compare
operation.
24.2.1 AUTO-CONVERSION TRIGGER
When Auto-Conversion Trigger mode is chosen
(CCPxM<3:0> = 1011), the CCPx module does the
following:
• Resets Timer1
• Starts an ADC conversion if ADC is enabled
The CCPx module does not assert control of the CCPx
pin in this mode.
The Auto-conversion Trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPRxH:CCPRxL
register pair. The TMR1H:TMR1L register pair is not
reset until the next rising edge of the Timer1 clock. The
Auto-conversion Trigger output starts an ADC conver-
sion (if the ADC module is enabled). This allows the
CCPRxH:CCPRxL register pair to effectively provide a
16-bit programmable period register for Timer1.
Refer to Section 16.2.5 “Auto-Conversion Trigger”
for more information.
24.2.2 CCPx PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the associated TRIS bit.
The CCPx pin function can be moved to alternate pins
using the PPS controls. See Section 12.0 “Pe ripheral
Pin Select (PPS) Module” for more detail.
FIGURE 24-2: COMPARE MODE OPERATION BLOCK DIAGRAM
Note 1: The Auto-conversion Trigger from the
CCP module does not set interrupt flag
bit TMR1IF of the PIR1 register.
2: Removing the match condition by
changing the contents of the CCPRxH
and CCPRxL register pair, between the
clock edge that generates the
Auto-conversion Trigger and the clock
edge that generates the Timer1 Reset,
will preclude the Reset from occurring.
Note: Clearing the CCPxCON register will force
the CCPx compare output latch to the
default low level. This is not the PORT I/O
data latch.
Rev . 10 -000 159B
9/5/201 4
CCPRxH CCPRxL
TMR1H TMR1L
Comparator
S
R
Q
Output
Logic
set CCPxIF
MODE<3:0>
4
To Peripherals
TRIS Control
CCPx
RxyPP S
PPS
PIC16(L)F1777/8/9
DS40001819B-page 314 2015-2016 Microchip Technology Inc.
24.2.3 TIMER1 MODE RESOURCE
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
See Section 22.0 “Timer1/3/5 Module with Gate
Control” for more information on configuring Timer1.
24.2.4 SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen
(MODE<3:0> = 1010), the CCPx module does not
assert control of the CCPx pin (see the CCPxCON
register).
24.2.5 COMPARE DURING SLEEP
The Compare mode is dependent upon the system
clock (FOSC) for proper operation. Since FOSC is shut
down during Sleep mode, the Compare mode will not
function properly during Sleep.
24.2.6 ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the PPS controls. See
Section 12.0 “Peripheral Pin Select (PPS) Module”
for more detail.
24.2.7 CAPTURE OUTPUT
When in Compare mode, the CCP will provide an
output upon the 16-bit value of the CCPRxH:CCPRxL
register pair, matching the TMR1H:TMR1L register
pair. The compare output depends on which Compare
mode the CCP is configured as. If the MODE bits of
CCPxCON register are equal to ‘1011’ or ‘1010’, the
CCP module will output high, while TMR1 is equal to
the CCPRxH:CCPRxL register pair. This means that
the pulse width is determined by the TMR1 prescaler. If
the MODE bits of CCPxCON are equal to ‘0001’ or
‘0010’, the output will toggle upon a match, going from
‘0’ to ‘1’ or vice-versa. If the MODE bits of CCPxCON
are equal to ‘1001’, the output is cleared on a match,
and if the MODE bits are equal to ‘1000’, the output is
set on a match. This output is available to the following
peripherals:
• ADC Trigger
•COG
•PRG
•DSM
•CLC
• Op Amp override
• Timer2/4/6/8 Reset
• Any device pins
Note: Clocking Timer1 from the system clock
(FOSC) should not be used in Compare
mode. In order for Compare mode to
recognize the trigger event on the CCPx
pin, TImer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
2015-2016 Microchip Technology Inc. DS40001819B-page 315
PIC16(L)F1777/8/9
24.3 PWM Overview
Pulse-Width Modulation (PWM) is a scheme that
provides power to a load by switching quickly between
fully on and fully off states. The PWM signal resembles
a square wave where the high portion of the signal is
considered the on state and the low portion of the signal
is considered the off state. The high portion, also known
as the pulse width, can vary in time and is defined in
steps. A larger number of steps applied, which
lengthens the pulse width, also supplies more power to
the load. Lowering the number of steps applied, which
shortens the pulse width, supplies less power. The
PWM period is defined as the duration of one complete
cycle or the total amount of on and off time combined.
PWM resolution defines the maximum number of steps
that can be present in a single PWM period. A higher
resolution allows for more precise control of the pulse
width time and in turn the power that is applied to the
load.
The term duty cycle describes the proportion of the on
time to the off time and is expressed in percentages,
where 0% is fully off and 100% is fully on. A lower duty
cycle corresponds to less power applied and a higher
duty cycle corresponds to more power applied.
Figure 24-3 shows a typical waveform of the PWM
signal.
FIGURE 24-3: SIMP LIFIED PWM BLOCK DIAGRAM
Rev . 10-000 157 C
9/5/201 4
CCPRxH
Duty cycle registers
10-bit Latch(2)
(Not accessible by user)
Comparator
Comparator
PR2
(1)
TMR2
TMR2 Module
CCPx
CCPx_out To Peripherals
R
TRIS Control
R
S
Q
CCPRxL
set CCPIF
CCPx_pset
ERS logic
Notes: 1. 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to
create 10-bit time-base.
2. The alignment of the 10 bits from the CCPR register is determined by the FMT bit.
PPS
RxyPP S
PIC16(L)F1777/8/9
DS40001819B-page 316 2015-2016 Microchip Technology Inc.
24.3.1 STANDARD PWM OPERATION
The standard PWM function described in this section is
available and identical for all CCP modules.
The standard PWM mode generates a Pulse-Width
Modulation (PWM) signal on the CCPx pin with up to
ten bits of resolution. The period, duty cycle, and
resolution are controlled by the following registers:
• T2PR/T4PR/T6PR/T8PR registers
• T2CON/T4CON/T6CON/T8CON registers
• CCPRxH:CCPRxL register pair
Figure 24-3 shows a simplified block diagram of PWM
operation.
24.3.2 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for standard PWM operation:
1. Disable the CCPx pin output driver by setting the
associated TRIS bit.
2. Select the timer associated with the PWM by
setting the CCPTMRS register.
3. Load the associated T2PR/T4PR/T6PR/T8PR
register with the PWM period value.
4. Configure the CCP module for the PWM mode
by loading the CCPxCON register with the
appropriate values.
5. Load the CCPRxH:CCPRxL register pair with
the PWM duty cycle value.
6. Configure and start the timer selected in step 2:
• Clear the timer interrupt flag bit of the PIRx
register. See Note below.
• Configure the CKPS bits of the TxCON
register with the Timer prescale value.
• Enable the Timer by setting the ON bit of
the TxCON register.
7. Enable PWM output pin:
• Wait until the Timer overflows and the timer
interrupt bit of the PIRx register is set. See
Note below.
• Enable the CCPx pin output driver by
clearing the associated TRIS bit.
Note 1: The corresponding TRIS bit must be
cleared to enable the PWM output on the
CCPx pin.
2: Clearing the CCPxCON register will
relinquish control of the CCPx pin.
Note: In order to send a complete duty cycle and
period on the first PWM output, the above
steps must be included in the setup
sequence. If it is not critical to start with a
complete PWM signal on the first output,
then step 6 may be ignored.
2015-2016 Microchip Technology Inc. DS40001819B-page 317
PIC16(L)F1777/8/9
24.4 CCP/PWM Clock Selection
The PIC16(L)F1777/8/9 allows each individual CCP
and PWM module to select the timer source that con-
trols the module. Each module has an independent
selection.
As there are up to four 8-bit timers with auto-reload
(Timer2/4/6/8). The PWM mode on the CCP and PWM
modules can use any of these timers.
The CCPTMRS register is used to select which timer is
used.
24.4.1 USING THE TMR2/4/6/8 WITH THE
CCP MODULE
This device has a new version of the TMR2 module that
has many new modes, which allow for greater custom-
ization and control of the PWM signals than older parts.
Refer to Section 23.6 “Operation Examples” for
examples of PWM signal generation using the different
modes of Timer2. The CCP operation requires that the
timer used as the PWM time base has the FOSC/4 clock
source selected.
24.4.2 PWM PERIOD
The PWM period is specified by the
T2PR/T4PR/T6PR/T8PR register of Timer2/4/6/8. The
PWM period can be calculated using the formula of
Equation 24-1.
EQUATION 24-1: PWM PERIOD
When TMR2/4/6/8 is equal to its respective
T2PR/T4PR/T6PR/T8PR register, the following three
events occur on the next increment cycle:
• TMR2/4/6/8 is cleared
• The CCPx pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
• The PWM duty cycle is latched from the
CCPRxH:CCPRxL pair into the internal 10-bit
latch.
24.4.3 PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit value
to two registers: the CCPRxH:CCPRxL register pair.
Where the particular bits go is determined by the FMT bit
of the CCPxCON register. If FMT = 0, the two Most
Significant bits of the duty cycle value should be written
to bits <1:0> of the CCPRxH register and the remaining
eight bits to the CCPRxL register. If FMT = 1, the Least
Significant two bits of the duty cycle should be written to
bits <7:6> of the CCPRxL register and the Most
Significant eight bits to the CCPRxH register. This is
illustrated in Figure 24-4. These bits can be written at any
time. The duty cycle value is not latched into the internal
latch until after the period completes (i.e., a match
between T2PR/T4PR/T6PR/T8PR and TMR2/4/6/8
registers occurs).
Equation 24-2 is used to calculate the PWM pulse width.
Equation 24-3 is used to calculate the PWM duty cycle
ratio.
EQUATION 24-2: PULSE WIDTH
EQUATION 24-3: DUTY CYCLE RATIO
The PWM duty cycle registers are double buffered for
glitchless PWM operation.
The 8-bit timer TMR2/4/6/8 register is concatenated with
either the 2-bit internal system clock (FOSC), or two bits
of the prescaler, to create the 10-bit time base. The
system clock is used if the Timer2/4/6/8 prescaler is set
to 1:1.
When the 10-bit time base matches the internal buffer
register, then the CCPx pin is cleared (see Figure 24-3).
FIGURE 24-4: CCPx DUTY CYCLE
ALIGNMENT
Note: The Timer postscaler (see Figure 24-1) is
not used in the determination of the PWM
frequency.
PWM Pe riod PR21+4TOSC =
(TM R2 Prescale Value)
Note 1: TOSC = 1/FOSC
Pulse Width CCPRxH:CCPRx L
TOSC=
(TMR2 Prescale Value)
Duty Cycle Ratio CCPRxH:CCPRxL
4 PRx 1+
--------------------------------------------------=
Rev . 10 -000 160 A
12/9 /201 3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
CCPRxH CCPRxL
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
CCPRxH CCPRxL
FMT = 0
FMT = 1
7 6 5 4 3 2 1 09 8
10-bit Duty Cycle
PIC16(L)F1777/8/9
DS40001819B-page 318 2015-2016 Microchip Technology Inc.
24.4.4 PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolution will result in 256 discrete duty cycles.
The maximum PWM resolution is ten bits when
T2PR/T4PR/T6PR/T8PR is 255. The resolution is a
function of the T2PR/T4PR/T6PR/T8PR register value
as shown by Equation 24-4.
EQUATION 24-4: PWM RESOLUTION
TABLE 24-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
TABLE 24-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
24.4.5 CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 5.0 “Oscillator Module (with Fail-Safe
Clock Monitor)” for additional details.
24.4.6 EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
24.4.7 PWM OUTPUT
The output of the CCP in PWM mode is the PWM signal
generated by the module and described above. This
output is available to the following peripherals:
• ADC Trigger
•COG
•PRG
•DSM
•CLC
• Op Amp override
• Timer2/4/6/8 Reset
• Any device pins
Note: If the pulse-width value is greater than the
period, the assigned PWM pin(s) will
remain unchanged.
Resolution 4PR21+log 2log
------------------------------------------ bits=
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescale 16 4 1 1 1 1
T2PR Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6
PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz
Timer Prescale 16 4 1 1 1 1
T2PR Value 0x65 0x65 0x65 0x19 0x0C 0x09
Maximum Resolution (bits) 8 8 8 6 5 5
2015-2016 Microchip Technology Inc. DS40001819B-page 319
PIC16(L)F1777/8/9
24.5 Regis t er D e finiti o n s : C C P Co n t ro l
REGISTER 24-1: CCPxCON: CCPx CONTROL REGISTER
R/W-0/0 U-0 R-x R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
EN — OUT FMT MODE<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 EN: CCPx Module Enable bit
1 = CCPx is enabled
0 = CCPx is disabled
bit 6 Unimplemented: Read as ‘0’
bit 5 OUT: CCPx Output Data bit (read-only)
bit 4 FMT: CCPW (Pulse-Width) Alignment bit
If MODE = PWM Mode
1 = Left-aligned format, CCPRxH <7> is the MSB of the PWM duty cycle
0 = Right-aligned format, CCPRxL<0> is the LSB of the PWM duty cycle
bit 3-0 MODE<3:0>: CCPx Mode Selection bits
11xx =PWM mode
1011 = Compare mode: Pulse output, clear TMR1
1010 = Compare mode: Pulse output (0 - 1 - 0)
1001 = Compare mode: clear output on compare match. Output is set upon selection of this mode.
1000 = Compare mode: set output on compare match. Output is set upon selection of this mode.
0111 = Capture mode: every 16th rising edge
0110 = Capture mode: every 4th rising edge
0101 = Capture mode: every rising edge
0100 = Capture mode: every falling edge
0011 = Capture mode: every rising or falling edge
0010 = Compare mode: toggle output on match
0001 = Compare mode: Toggle output and clear TMR1 on match
0000 = Capture/Compare/PWM off (resets CCPx module) (reserved for backwards compatibility)
PIC16(L)F1777/8/9
DS40001819B-page 320 2015-2016 Microchip Technology Inc.
REGISTER 24-2: CCPRxL: CCPx LOW BYTE REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
CCPR<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 MODE = Capture Mode
CCPRxL<7:0>: LSB of captured TMR1 value
MODE = Compare Mode
CCPRxL<7:0>: LSB compared to TMR1 value
MODE = PWM Mode && FMT = 0
CCPRxL<7:0>: CCPW<7:0> – Pulse width Least Significant eight bits
MODE = PWM Mode && FMT = 1
CCPRxL<7:6>: CCPW<1:0> – Pulse width Least Significant two bits
CCPRxL<5:0>: Not used
REGISTER 24-3: CCPRxH: CCPx HIGH BYTE REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
CCPR<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 MODE = Capture Mode
CCPRxH<7:0>: MSB of captured TMR1 value
MODE = Compare Mode
CCPRxH<7:0>: MSB compared to TMR1 value
MODE = PWM Mode && FMT = 0
CCPRxH<7:2>: Not used
CCPRxH<1:0>: CCPW<9:8> – Pulse width Most Significant two bits
MODE = PWM Mode && FMT = 1
CCPRxH<7:0>: CCPW<9:2> – Pulse width Most Significant eight bits
2015-2016 Microchip Technology Inc. DS40001819B-page 321
PIC16(L)F1777/8/9
REGISTER 24-4: CCPxCAP: CCPx CAPTURE INPUT SELECTION REGISTER
U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — —CTS<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 CTS<3:0>: Capture Trigger Input Selection bits
1101 = IOC_event
1100 = LC4_output
1011 = LC3_output
1010 = LC2_output
1001 = LC1_output
1000 = C8_sync_out(1)
0111 = C7_sync_out(1)
0110 = C6_sync_out
0101 = C5_sync_out
0100 = C4_sync_out
0011 = C3_sync_out
0010 = C2_sync_out
0001 = C1_sync_out
0000 = Pin selected with the CCPxPPS register
Note 1: PIC16LF1777/9 only.
PIC16(L)F1777/8/9
DS40001819B-page 322 2015-2016 Microchip Technology Inc.
24.6 CCP/PWM Clock Selection
This device allows each individual CCP and PWM
module to select the timer source that controls the
module. Each module has an independent selection.
As there are four 8-bit timers with auto-reload (Timer2,
Timer4, Timer6 and Timer8). The PWM mode on the
CCP and 10-bit PWM modules can use any of these
timers.
The CCPTMRS register is used to select which timer is
used.
24.7 Regis t er D e finiti o n s : C C P /P WM Time rs C o n tr ol
REGISTER 24-5: CCPTMRS1: PWM TIMER SELECTION CONTROL REGISTER 1
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
C8TSEL<1:0>(1) C7TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 C8TSEL<1:0>: CCP8 (PWM8) Timer Selection bits(1)
11 = CCP8 is based off Timer8 in PWM mode
10 = CCP8 is based off Timer6 in PWM mode
01 = CCP8 is based off Timer4 in PWM mode
00 = CCP8 is based off Timer2 in PWM mode
bit 5-4 C7TSEL<1:0>: CCP7 (PWM7) Timer Selection bits
11 = CCP7 is based off Timer8 in PWM mode
10 = CCP7 is based off Timer6 in PWM mode
01 = CCP7 is based off Timer4 in PWM mode
00 = CCP7 is based off Timer2 in PWM mode
bit 3-2 C2TSEL<1:0>: CCP2 (PWM2) Timer Selection bits
11 = CCP2 is based off Timer8 in PWM mode
10 = CCP2 is based off Timer6 in PWM mode
01 = CCP2 is based off Timer4 in PWM mode
00 = CCP2 is based off Timer2 in PWM mode
bit 1-0 C1TSEL<1:0>: CCP1 (PWM1) Timer Selection bits
11 = CCP1 is based off Timer8 in PWM mode
10 = CCP1 is based off Timer6 in PWM mode
01 = CCP1 is based off Timer4 in PWM mode
00 = CCP1 is based off Timer2 in PWM mode
Note 1: PIC16(L)F1777/9 only.
2015-2016 Microchip Technology Inc. DS40001819B-page 323
PIC16(L)F1777/8/9
REGISTER 24-6: CCPTMRS2: PWM TIMER SELECTION CONTROL REGISTER 2
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
P10TSEL<1:0>(1) P9TSEL<1:0> P4TSEL<1:0> P3TSEL<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 P10TSEL<1:0>: PWM10 Timer Selection bits(1)
11 = PWM10 is based off Timer8 in PWM mode
10 = PWM10 is based off Timer6 in PWM mode
01 = PWM10 is based off Timer4 in PWM mode
00 = PWM10 is based off Timer2 in PWM mode
bit 5-4 P9TSEL<1:0>: PWM9 Timer Selection bits
11 = PWM9 is based off Timer8 in PWM mode
10 = PWM9 is based off Timer6 in PWM mode
01 = PWM9 is based off Timer4 in PWM mode
00 = PWM9 is based off Timer2 in PWM mode
bit 3-2 P4TSEL<1:0>: PWM4 Timer Selection bits
11 = PWM4 is based off Timer8 in PWM mode
10 = PWM4 is based off Timer6 in PWM mode
01 = PWM4 is based off Timer4 in PWM mode
00 = PWM4 is based off Timer2 in PWM mode
bit 1-0 P3TSEL<1:0>: PWM3 Timer Selection bits
11 = PWM3 is based off Timer8 in PWM mode
10 = PWM3 is based off Timer6 in PWM mode
01 = PWM3 is based off Timer4 in PWM mode
00 = PWM3 is based off Timer2 in PWM mode
Note 1: PIC16(L)F1777/9 only.
PIC16(L)F1777/8/9
DS40001819B-page 324 2015-2016 Microchip Technology Inc.
TABLE 24-4: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM
Name Bit 7 Bit 6 B it 5 Bit 4 Bit 3 B it 2 Bit 1 Bit 0 Register
on Page
CCPxCAP ————CTS<3:0>321
CCPxCON EN —OUTFMT MODE<3:0> 319
CCPRxL Capture/Compare/PWM Register x (LSB) 320
CCPRxH Capture/Compare/PWM Register x (MSB) 320
CCPTMRS1 C8TSEL<1:0>(1) C7TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 323
CCPTMRS2 P10TSEL<1:0>(1) P9TSEL<1:0> P4TSEL<1:0> P3TSEL<1:0> 323
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133
PIE2 OSFIE C2IE C1IE COG1IE BCL1IE C4IE C3IE CCP2IE 134
PIE5 CCP8IE(1) CCP7IE COG4IE(1) COG3IE C8IE(1) C7IE(1) C6IE C5IE 137
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139
PIR2 OSFIF C2IF C1IF COG1IF BCL1IF C4IF C3IF CCP2IF 140
PIR5 CCP8IF(1) CCP7IF COG4IF(1) COG3IF C8IF(1) C7IF(1) C6IF C5IF 143
T2PR Timer2 Period Register 287*
T2CON ON CKPS<2:0> OUTPS<3:0> 307
TMR2 Timer2 Module Register 287
T4PR Timer4 Period Register 287*
T4CON ON CKPS<2:0> OUTPS<3:0> 307
TMR4 Timer4 Module Register 287
T6PR Timer6 Period Register 287*
T6CON ON CKPS<2:0> OUTPS<3:0> 307
TMR6 Timer6 Module Register 287
T8PR Timer8 Period Register 287*
T8CON ON CKPS<2:0> OUTPS<3:0> 307
TMR8 Timer8 Module Register 287
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.
* Page provides register information.
Note 1: PIC16(L)F1777/9 only.
2015-2016 Microchip Technology Inc. DS40001819B-page 325
PIC16(L)F1777/8/9
25.0 10-BIT PULSE-WIDTH
MODULATION (PWM) MODULE
The 10-bit PWM module generates a Pulse-Width
Modulated signal determined by the duty cycle, period,
and resolution that are configured by the following
registers:
•T2PR
•T2CON
• PWMxDCH
• PWMxDCL
•PWMxCON
Figure 25-1 shows a simplified block diagram of PWM
operation.
Figure 25-2 shows a typical waveform of the PWM
signal.
FIGURE 25-1: SIMPL I FI ED PWM BLOCK DIAGRAM
For a step-by-step procedure on how to set up this
module for PWM operation, refer to Section 25.1.9
“Setup for PWM Operation using PWMx Output
Pins”.
FIGURE 25-2: PWM OUTPUT
TABLE 25-1: AVAILABLE 10-BIT PWM
MODULES
Device PWM3 PWM4 PWM9 PWM10
PIC16(L)F1778 ●●●
PIC16(L)F1777/9 ●●●●
PWMxDCH
Comparator
TMR2
Comparator
T2PR
(1)
RQ
S
Duty Cycle registers PWMxDCL<7:6>
Clear Timer,
PWMx pin and
latch Duty Cycle
PWMx
Note 1: 8-bit timer is concatenated with the two Least Significant bits of 1/FOSC adjusted by the Timer2 prescaler to
create a 10-bit time base.
Latched
(Not visible to user)
Q
Output Polarity (PWMxPOL)
TMR2 Module
0
1
PWMxOUT
to other peripherals: ADC, COG, CLC
TRIS
PPS
RXYPPS
PRG, DSM, Op Amp override
Period
Pulse Width
TMR2 = 0
TMR2 =
TMR2 = T2PR
PWMxDCH<7:0>:PWMxDCL<7:6>
PIC16(L)F1777/8/9
DS40001819B-page 326 2015-2016 Microchip Technology Inc.
25.1 PWM x Pin Configuration
All PWM outputs are multiplexed with the PORT data
latch. The user must configure the pins as outputs by
clearing the associated TRIS bits.
25.1.1 FUNDAMENTAL OPERATION
The PWM module produces a 10-bit resolution output.
Timer2 and T2PR set the period of the PWM. The
PWMxDCL and PWMxDCH registers configure the
duty cycle. The period is common to all PWM modules,
whereas the duty cycle is independently controlled.
All PWM outputs associated with Timer2 are set when
TMR2 is cleared. Each PWMx is cleared when TMR2
is equal to the value specified in the corresponding
PWMxDCH (8 MSb) and PWMxDCL<7:6> (2 LSb)
registers. When the value is greater than or equal to
T2PR, the PWM output is never cleared (100% duty
cycle).
25.1.2 PWM OUTPUT POLARITY
The output polarity is inverted by setting the PWMxPOL
bit of the PWMxCON register.
25.1.3 PWM PERIOD
The PWM period is specified by the T2PR register of
Timer2. The PWM period can be calculated using the
formula of Equation 25-1.
EQUATION 25-1: PWM PERIOD
When TMR2 is equal to T2PR, the following three
events occur on the next increment cycle:
•TMR2 is cleared
• The PWM output is active. (Exception: When the
PWM duty cycle = 0%, the PWM output will
remain inactive.)
• The PWMxDCH and PWMxDCL register values
are latched into the buffers.
25.1.4 PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit value
to the PWMxDCH and PWMxDCL register pair. The
PWMxDCH register contains the eight MSbs and the
PWMxDCL<7:6>, the two LSbs. The PWMxDCH and
PWMxDCL registers can be written to at any time.
Equation 25-2 is used to calculate the PWM pulse
width.
Equation 25-3 is used to calculate the PWM duty cycle
ratio.
EQUATION 25-2: PULSE WIDTH
EQUATION 25-3: DUTY CYCLE RATIO
The 8-bit timer TMR2 register is concatenated with the
two Least Significant bits of 1/FOSC, adjusted by the
Timer2 prescaler to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to 1:1.
Note: The Timer2 postscaler is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than the
PWM output.
Note: The PWMxDCH and PWMxDCL registers
are double buffered. The buffers are updated
when Timer2 matches T2PR. Care should
be taken to update both registers before the
timer match occurs.
PWM Period T2PR 1+4TOSC =
(TM R2 Prescale Value)
Note: TOSC = 1/FOSC
Note: The Timer2 postscaler has no effect on the
PWM operation.
Pulse Width PWMxDCH:PWMxDCL<7:6>
=
TOSC
(TMR2 Prescale Value)
Note: TOSC = 1/FOSC
Duty Cycle Ratio PWMxDCH:PWMxDCL<7:6>
4T2PR 1+
-----------------------------------------------------------------------------------=
2015-2016 Microchip Technology Inc. DS40001819B-page 327
PIC16(L)F1777/8/9
25.1.5 PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolution will result in 256 discrete duty cycles.
The maximum PWM resolution is ten bits when T2PR
is 255. The resolution is a function of the T2PR register
value as shown by Equation 25-4.
EQUATION 25-4: PWM RESOLUTION
25.1.6 OPERATION IN SLEEP MODE
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the
PWMx pin is driving a value, it will continue to drive that
value. When the device wakes up, TMR2 will continue
from its previous state.
25.1.7 CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency (FOSC). Any changes in the system clock
frequency will result in changes to the PWM frequency.
Refer to Section 5.0 “Oscillator Module (with
Fail-Safe Clock Monitor)” for additional details.
25.1.8 EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
PWM registers to their Reset states.
Note: If the pulse-width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
Resolution 4T2PR 1+log 2log
---------------------------------------------- bits=
TABLE 25-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency 0.31 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescale 64 4 1 1 1 1
T2PR Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6.6
TABLE 25-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
PWM Frequency 0.31 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz
Timer Prescale 64 4 1 1 1 1
T2PR Value 0x65 0x65 0x65 0x19 0x0C 0x09
Maximum Resolution (bits) 8 8 8 6 5 5
PIC16(L)F1777/8/9
DS40001819B-page 328 2015-2016 Microchip Technology Inc.
25.1.9 SETUP FOR PWM OPERATION
USING PWMx OUTPUT PINS
The following steps should be taken when configuring
the module for PWM operation using the PWMx output
pins:
1. Disable the PWMx pin output driver(s) by setting
the associated TRIS bit(s).
2. Clear the PWMxCON register.
3. Load the T2PR register with the PWM period
value.
4. Load the PWMxDCH register and bits <7:6> of
the PWMxDCL register with the PWM duty cycle
value.
5. Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the PIR1
register. See Note below.
• Configure the CKPS bits of the T2CON register
with the Timer2 prescale value.
• Enable Timer2 by setting the ON bit of the
T2CON register.
6. Enable PWM output pin and wait until Timer2
overflows, TMR2IF bit of the PIR1 register is set.
See Note below.
7. Enable the PWMx pin output driver(s) by clear-
ing the associated TRIS bit(s) and setting the
desired pin PPS control bits.
8. Configure the PWM module by loading the
PWMxCON register with the appropriate values.
25.1.10 SETUP FOR PWM OPERATION TO
OTHER DEVICE PERIPHERALS
The following steps should be taken when configuring
the module for PWM operation to be used by other
device peripherals:
1. Disable the PWMx pin output driver(s) by setting
the associated TRIS bit(s).
2. Clear the PWMxCON register.
3. Load the T2PR register with the PWM period
value.
4. Load the PWMxDCH register and bits <7:6> of
the PWMxDCL register with the PWM duty cycle
value.
5. Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the PIR1
register. See Note below.
• Configure the CKPS bits of the T2CON register
with the Timer2 prescale value.
• Enable Timer2 by setting the ON bit of the
T2CON register.
6. Enable PWM output pin:
• Wait until Timer2 overflows, TMR2IF bit of the
PIR1 register is set. See Note below.
7. Configure the PWM module by loading the
PWMxCON register with the appropriate values.
Note 1: In order to send a complete duty cycle
and period on the first PWM output, the
above steps must be followed in the order
given. If it is not critical to start with a
complete PWM signal, then move Step 8
to replace Step 4.
2: For operation with other peripherals only,
disable PWMx pin outputs.
Note: In order to send a complete duty cycle and
period on the first PWM output, the above
steps must be included in the setup
sequence. If it is not critical to start with a
complete PWM signal on the first output,
then step 6 may be ignored.
2015-2016 Microchip Technology Inc. DS40001819B-page 329
PIC16(L)F1777/8/9
25.2 Regis t er D e finition s : 10 - B it PWM C o n tr o l
Long bit name prefixes for the DSM peripherals are
shown in Table 25-4. Refer to Section 1.1.2.2 “Long
Bit Names” for more information
TABLE 25-4:
Peripheral Bit Name Prefix
PWM3 PWM3
PWM4 PWM4
PWM9 PWM9
PWM10(1) PWM10
Note 1: PIC16(L)F1777/9 only.
REGISTER 25-1: PWMxCON: PWM CONTROL REGISTER
R/W-0/0 U-0 R-0/0 R/W-0/0 U-0 U-0 U-0 U-0
EN —OUTPOL— — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 EN: PWM Module Enable bit
1 = PWM module is enabled
0 = PWM module is disabled
bit 6 Unimplemented: Read as ‘0’
bit 5 OUT: PWM module output level when bit is read.
bit 4 POL: PWMx Output Polarity Select bit
1 = PWM output is active-low
0 = PWM output is active-high
bit 3-0 Unimplemented: Read as ‘0’
PIC16(L)F1777/8/9
DS40001819B-page 330 2015-2016 Microchip Technology Inc.
REGISTER 25-2: PWMxDCH: PWM DUTY CYCLE HIGH BITS
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
DC<9:2>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 DC<9:2>: PWM Duty Cycle Most Significant bits
These bits are the MSbs of the PWM duty cycle. The two LSbs are found in the PWMxDCL Register.
REGISTER 25-3: PWMxDCL: PWM DUTY CYCLE LOW BITS
R/W-x/u R/W-x/u U-0 U-0 U-0 U-0 U-0 U-0
DC<1:0> — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 DC<1:0>: PWM Duty Cycle Least Significant bits
These bits are the LSbs of the PWM duty cycle. The MSbs are found in the PWMxDCH Register.
bit 5-0 Unimplemented: Read as ‘0’
2015-2016 Microchip Technology Inc. DS40001819B-page 331
PIC16(L)F1777/8/9
TABLE 25-5: SUMMARY OF REGISTERS ASSOCIATED WITH 10-BIT PWM
Name B it 7 Bit 6 B it 5 Bit 4 B it 3 Bit 2 Bit 1 Bit 0 Register
on Page
CCPTMRS2 P10TSEL<1:0>(1) P9TSEL<1:0> P4TSEL<1:0> P3TSEL<1:0> 323
PWM3CON EN —OUTPOL— — — — 329
PWM3DCH DC<9:2> 330
PWM3DCL DC<1:0> — — — — — — 330
PWM4CON EN —OUTPOL— — — — 329
PWM4DCH DC<9:2> 330
PWM4DCL DC<1:0> — — — — — — 330
PWM9CON EN —OUTPOL— — — — 329
PWM9DCH DC<9:2> 330
PWM9DCL DC<1:0> — — — — — — 330
PWM10CON(1) EN —OUTPOL— — — — 329
PWM10DCH(1) DC<9:2> 330
PWM10DCL(1) DC<1:0> — — — — — — 330
RxyPPS —— RxyPPS<5:0> 205
TxCON ON CKPS<2:0> OUTPS<3:0> 307
TxCLKCON — — — — CS<3:0> 306
TxPR TMRx Period Register 287
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186
Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM.
Note 1: PIC16LF1777/9 only.
PIC16(L)F1777/8/9
DS40001819B-page 332 2015-2016 Microchip Technology Inc.
26.0 16-BIT PULSE-WIDTH
MODULATION (PWM) MODULE
The Pulse-Width Modulation (PWM) module generates
a pulse-width modulated signal determined by the
phase, duty cycle, period, and offset event counts that
are contained in the following registers:
• PWMxPH register
• PWMxDC register
• PWMxPR register
• PWMxOF register
Figure 26-1 shows a simplified block diagram of the
PWM operation. Each PWM module has four modes of
operation:
• Standard
• Set On Match
• Toggle On Match
• Center Aligned
For a more detailed description of each PWM mode,
refer to Section 26.2 “PWM Modes”.
Each PWM module has four offset modes:
• Independent Run
• Slave Run with Synchronous Start
• One-Shot Slave with Synchronous Start
• Continuous Run Slave with Synchronous Start
and Timer Reset
Using the offset modes, each PWM module can offset
its waveform relative to any other PWM module in the
same device. For a more detailed description of the off-
set modes refer to Section 26.3 “Offset Modes” .
Every PWM module has a configurable reload operation
to ensure all event count buffers change at the end of a
period, thereby avoiding signal glitches. Figure 26-2
shows a simplified block diagram of the reload operation.
For a more detailed description of the reload operation,
refer to Section Section 26.4 “Reload Operation”.
FIGURE 26-1: 16-BIT PWM BLOCK DIAGRAM
TABLE 26-1: AVAILABLE 16-BIT PWM
MODULES
Device PWM5 PWM6 PWM11 PWM12
PIC16(L)F1778 ●●●
PIC16(L)F1777/9 ●●●●
Rev . 10 -000 152B
4/22 /201 4
PWM Control
Unit
MODE<1:0>
PWMxPR
Comparator
PWMxTMR
PRx_match
PWMxDC
Comparator
16-bt Latch
DCx_match
PWMxOF
Comparator
16-bt Latch
OFx_match
PWMxPH
Comparator
16-bt Latch
PHx_match
16-bt Latch LDx_trigger LDx_trigger LDx_trigger LDx_trigger
PWMxPOL
PWMx
PWMxOUT
To Peripherals
TRIS Control
set PRIF set PHIF set OFIF set DCIF
D
CK
Q
Q4
PWMx_output
Offset
Control
ERU/D
OFM<1:0>
PRx_match
OF6_match(1)
OF5_match(1)
OFS
OF_match
EN
PHx_match
DCx_match
Note 1: A PWM module cannot trigger from its own offset match event.
The input corresponding to a PWM module’s own offset match is reserved.
PWM_clock
PPS
RxyPP S
1
0
2015-2016 Microchip Technology Inc. DS40001819B-page 333
PIC16(L)F1777/8/9
FIGURE 26-2: LOAD TRIGGER BLOCK DIAGRAM
26.1 Fundamental Operation
The PWM module produces a 16-bit resolution
pulse-width modulated output.
Each PWM module has an independent timer driven by
a selection of clock sources determined by the
PWMxCLKCON register (Register 26-4). The timer
value is compared to event count registers to generate
the various events of a the PWM waveform, such as the
period and duty cycle. For a block diagram describing
the clock sources refer to Figure 26-3.
Each PWM module can be enabled individually using
the EN bit of the PWMxCON register, or several PWM
modules can be enabled simultaneously using the
MPWMxEN bits of the PWMEN register.
The current state of the PWM output can be read using
the OUT bit of the PWMxCON register. In some modes
this bit can be set and cleared by software giving
additional software control over the PWM waveform.
This bit is synchronized to FOSC/4 and therefore does
not change in real time with respect to the PWM_clock.
FIGURE 26-3: PWM CLOCK SOURCE
BLOCK DIAGRAM
26.1.1 PWMx PIN CONFIGURATION
This device uses the PPS control circuitry to route
peripherals to any device I/O pin. Select the desired
pin, or pins, for PWM output with the device pin
RxyPPS control registers (Register 12-2).
All PWM outputs are multiplexed with the PORT data
latch, so the pins must also be configured as outputs by
clearing the associated PORT TRIS bits.
The slew rate feature may be configured to optimize
the rate to be used in conjunction with the PWM out-
puts. High-speed output switching is attained by clear-
ing the associated PORT SLRCON bits.
The PWM outputs can be configured to be open-drain
outputs by setting the associated PORT ODCON bits.
26.1.2 PWMx Output Polarity
The output polarity is inverted by setting the POL bit of
the PWMxCON register. The polarity control affects the
PWM output even when the module is not enabled.
Rev . 10 -000 153B
7/9/201 5
LDx_trigger(1)
LDy_trigger
PWMxLDS
PRx_match
1
0
PWMxLDA(2) DQ
PWM_clock
LDx_trigger
PWMxLDT
Note 1. The input corresponding to a PWM module’s own load trigger is reserved.
2. PWMxLDA is cleared by hardware upon LDx_trigger.
Note: If PWM_clock > FOSC/4, the OUT bit may
not accurately represent the output state of
the PWM.
Rev. 10-000156A
1/7/2015
00
11
10
01
HFINTOSC
LFINTOSC
FOSC
Reserved
PWMxCS<1:0>
Prescaler PWMx_clock
PWMxPS<2:0>
PIC16(L)F1777/8/9
DS40001819B-page 334 2015-2016 Microchip Technology Inc.
26.2 PWM Modes
PWM modes are selected with MODE<1:0> bits of the
PWMxCON register (Register 26-1).
In all PWM modes an offset match event can also be
used to synchronize the PWMxTMR in three offset
modes. See Section 26.3 “Offset Modes” for more
information.
26.2.1 STANDARD MODE
The Standard mode (MODE = 00) selects a single
phase PWM output. The PWM output in this mode is
determined by when the period, duty cycle, and phase
counts match the PWMxTMR value. The start of the
duty cycle occurs on the phase match and the end of
the duty cycle occurs on the duty cycle match. The
period match resets the timer. The offset match can
also be used to synchronize the PWMxTMR in the off-
set modes. See Section 26.3 “Offset Modes” for
more information.
Equation 26-1 is used to calculate the PWM period in
Standard mode.
Equation 26-2 is used to calculate the PWM duty cycle
ratio in Standard mode.
EQUATION 26-1: PWM PERIOD IN
STANDARD MODE
EQUATION 26-2: PWM DUTY CYCLE IN
STANDARD MODE
A detailed timing diagram for Standard mode is shown
in Figure 26-4.
26.2.2 SET ON MATCH MODE
The Set On Match mode (MODE = 01) generates an
active output when the phase count matches the
PWMxTMR value. The output stays active until the
OUT bit of the PWMxCON register is cleared or the
PWM module is disabled. The duty cycle count has no
effect in this mode. The period count only determines
the maximum PWMxTMR value above which no phase
matches can occur.
The PWMxOUT bit can be used to set or clear the out-
put of the PWM in this mode. Writes to this bit will take
place on the next rising edge of the PWM_clock after
the bit is written.
A detailed timing diagram for Set On Match is shown in
Figure 26-5.
26.2.3 TOGGLE ON MATCH MODE
The Toggle On Match mode (MODE = 10) generates a
50% duty cycle PWM with a period twice as long as that
computed for the standard PWM mode. Duty cycle
count has no effect in this mode. The phase count
determines how many PWMxTMR periods after a
period event the output will toggle.
Writes to the OUT bit of the PWMxCON register will
have no effect in this mode.
A detailed timing diagram for Toggle On Match is
shown in Figure 26-6.
26.2.4 CENTER ALIGNED MODE
The Center Aligned mode (MODE = 11) generates a
PWM waveform that is centered in the period. In this
mode the period is two times the PWMxPR count. The
PWMxTMR counts up to the period value then counts
back down to 0. The duty cycle count determines both
the start and end of the active PWM output. The start of
the duty cycle occurs at the match event when
PWMxTMR is incrementing and the duty cycle ends at
the match event when PWMxTMR is decrementing.
The incrementing match value is the period count
minus the duty cycle count. The decrementing match
value is the incrementing match value plus 1.
Equation 26-3 is used to calculate the PWM period in
Center Aligned mode.
EQUATION 26-3: PWM PERIOD IN CENTER
ALIGNED MODE
Equation 26-4 is used to calculate the PWM duty cycle
ratio in Center Aligned mode
EQUATION 26-4: PWM DUTY CYCLE IN
CENTER ALIGNED MODE
Writes to PWMxOUT will have no effect in this mode.
A detailed timing diagram for Center Aligned mode is
shown in Figure 26-7.
Period PWMxPR 1+
Prescale
PWM_clock
----------------------------------------------------------------------=
Duty Cycle PWMxDC PWMxPH–
PWMxPR 1+
-----------------------------------------------------------------=
Period PWMxPR 1+
2Prescale

PWM_clock
------------------------------------------------------------------------------=
Duty Cycle PWMxDC 2
PWMxPR 1+2
-------------------------------------------------=
2015-2016 Microchip Technology Inc. DS40001819B-page 335
PIC16(L)F1777/8/9
FIGURE 26-4: STANDARD PWM MODE TIMING DIAGRAM
FIGURE 26-5: SET ON MATCH PWM MODE TIMING DIAGRAM
Rev. 10-000142A
9/5/2013
PWMxCLK
10
4
9
PWMxPR
PWMxPH
PWMxDC
Phase
Duty Cycle
Period
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6PWMxTMR
PWMxOUT
Rev. 10-000143A
9/5/2013
PWMxCLK
10
4
PWMxPR
PWMxPH
Phase
Period
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6PWMxTMR
PWMxOUT
PIC16(L)F1777/8/9
DS40001819B-page 336 2015-2016 Microchip Technology Inc.
FIGURE 26-6: TOGGLE ON MATCH PWM MODE TIMING DIAGRAM
FIGURE 26-7: CEN TER ALI GNED PWM MODE TIMING DIAGRAM
Rev. 10-000144A
9/5/2013
PWMxCLK
10
4
PWMxPR
PWMxPH
Phase
Period
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6PWMxTMR
PWMxOUT
Rev. 10 -000 145A
4/22 /201 4
PWMxCLK
6
4
PWMxPR
PWMxDC
Duty Cycle
Perio d
0 1 2 3 4 5 6 6 5 4 3 2 1 0 0 1 2 3PWMxTMR
PWMxOUT
2015-2016 Microchip Technology Inc. DS40001819B-page 337
PIC16(L)F1777/8/9
26.3 Offset Modes
The offset modes provide the means to adjust the
waveform of a slave PWM module relative to the wave-
form of a master PWM module in the same device.
26.3.1 INDEPENDENT RUN MODE
In Independent Run mode (OFM = 00), the PWM mod-
ule is unaffected by the other PWM modules in the
device. The PWMxTMR associated with the PWM
module in this mode starts counting as soon as the EN
bit associated with this PWM module is set and contin-
ues counting until the EN bit is cleared. Period events
reset the PWMxTMR to zero after which the timer con-
tinues to count.
A detailed timing diagram of this mode used with
Standard PWM mode is shown in Figure 26-8.
26.3.2 SLAVE RUN MODE WITH SYNC
START
In Slave Run mode with Sync Start (OFM = 01), the
slave PWMxTMR waits for the master’s OF_match
event. When this event occurs, if the EN bit is set, the
PWMxTMR begins counting and continues to count
until software clears the EN bit. Slave period events
reset the PWMxTMR to zero after which the timer con-
tinues to count.
A detailed timing diagram of this mode used with
Standard PWM mode is shown in Figure 26-9.
26.3.3 ONE-SHOT SLAVE MODE WITH
SYNC START
In One-Shot Slave mode with Synchronous Start (OFM
= 10), the slave PWMxTMR waits until the master’s
OF_match event. The timer then begins counting, start-
ing from the value that is already in the timer, and con-
tinues to count until the period match event. When the
period event occurs the timer resets to zero and stops
counting. The timer then waits until the next master
OF_match event after which it begins counting again to
repeat the cycle.
A detailed timing diagram of this mode used with
Standard PWM mode is shown in Figure 26-10.
26.3.4 CONTINUOUS RUN SLAVE MODE
WITH SYNC START AND TIMER
RESET
In Continuous Run Slave mode with Synchronous Start
and Timer Reset (OFM = 11) the slave PWMxTMR is
inhibited from counting after the slave PWM enable is
set. The first master OF_match event starts the slave
PWMxTMR. Subsequent master OF_match events
reset the slave PWMxTMR timer value back to 1 after
which the slave PWMxTMR continues to count. The
next master OF_match event resets the slave
PWMxTMR back to 1 to repeat the cycle. Slave period
events that occur before the master’s OF_match event
will reset the slave PWMxTMR to zero after which the
timer will continue to count. Slaves operating in this
mode must have a PWMxPH register pair value equal
to or greater than 1, otherwise the phase match event
will not occur precluding the start of the PWM output
duty cycle.
The offset timing will persist if both the master and
slave PWMxPR values are the same and the Slave
Offset mode is changed to Independent Run mode
while the PWM module is operating.
A detailed timing diagram of this mode used in
Standard PWM mode is shown in Figure 26-11.
26.3.5 OFFSET MATCH IN CENTER
ALIGNED MODE
When a master is operating in Center-Aligned mode
the offset match event depends on which direction the
PWMxTMR is counting. Clearing the OFO bit of the
PWMxOFCON register will cause the OF_match event
to occur when the timer is counting up. Setting the OFO
bit of the PWMxOFCON register will cause the
OF_match event to occur when the timer is counting
down. The OFO bit is ignored in Non-Center-Aligned
modes.
The OFO bit is double buffered and requires setting the
LDA bit to take effect when the PWM module is operat-
ing.
Detailed timing diagrams of Center-Aligned mode
using offset match control in Independent Slave with
Sync Start mode can be seen in Figure 26-12 and
Figure 26-13.
Note: Unexpected results will occur if the slave
PWM_clock is a higher frequency than the
master PWM_clock.
PIC16(L)F1777/8/9
DS40001819B-page 338 2015-2016 Microchip Technology Inc.
FIGURE 26-8: INDEPE NDE NT RUN MODE TIMING DIAGRAM
Rev. 10 -000 146B
7/8/ 201 5
PWMxCLK
10
3
5
2
PWMxPR
PWMxPH
PWMxDC
PWMxOF
Off set
Phase
Duty Cycle
Perio d
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6PWMxTMR
PWMxOUT
OFx_match
PHx_match
DCx_match
PRx_match
0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2PWMyTMR
4
0
1
PWMyPR
PWMyPH
PWMyDC
PWMyOUT
Note: PWMx = Master, PWMy = Slave
2015-2016 Microchip Technology Inc. DS40001819B-page 339
PIC16(L)F1777/8/9
FIGURE 26-9: SLAVE RUN MODE WITH SYNC START TIMING DIAGRAM
Rev. 10 -000 147B
7/8/ 201 5
PWMxCLK
10
3
5
2
PWMxPR
PWMxPH
PWMxDC
PWMxOF
Off set
Phase
Duty Cycle
Perio d
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6PWMxTMR
PWMxOUT
OFx_match
PWMyTMR
4
0
1
PWMyPR
PWMyPH
PWMyDC
PWMyOUT
10 2 3 4 0 1 2 3 4 0 1 2 3 4 0
Note: Master = PWMx, Slave = PWMy
PIC16(L)F1777/8/9
DS40001819B-page 340 2015-2016 Microchip Technology Inc.
FIGURE 26-10: ONE-SHOT SLAVE RUN MODE WITH SYNC START TIMING DIAGRAM
Rev. 10 -000 148B
7/8/ 201 5
PWMxCLK
10
3
5
2
PWMxPR
PWMxPH
PWMxDC
PWMxOF
Off set
Phase
Duty Cycle
Perio d
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6PWMxTMR
PWMxOUT
OFx_match
PWMyTMR
4
0
1
PWMyPR
PWMyPH
PWMyDC
PWMyOUT
10 2 3 4 1 2 3 40
Note: Master = PWMx, Slave = PWMy
2015-2016 Microchip Technology Inc. DS40001819B-page 341
PIC16(L)F1777/8/9
FIGURE 26-11: CONTINUOUS SLAVE RUN MODE WITH IMMEDIATE RESET AND SYNC START TIMING DIAGRAM
Rev. 10 -000 149B
7/8/ 201 5
PWMxCLK
10
3
5
2
PWMxPR
PWMxPH
PWMxDC
PWMxOF
Off set
Phase
Duty Cycle
Perio d
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6PWMxTMR
PWMxOUT
OFx_match
PWMyTMR
4
1
2
PWMyPR
PWMyPH
PWMyDC
PWMyOUT
10 2 3 4 1 2 3 401 2 3 40 1
Note: Maste r= PWMx, Slave=PWMy
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DS40001819B-page 342 2015-2016 Microchip Technology Inc.
FIGURE 26-12: O FFSET MATCH ON INCREMENTING TIMER TIMING DIAGRAM
Rev. 10 -000 150B
7/9/ 201 5
PWMxCLK
6
2
2
PWMxPR
PWMxDC
PWMxOF
Off set
Duty Cycle
Perio d
0 1 2 3 4 5 6 6 5 4 3 2 1 0 0 1 2 3PWMxTMR
PWMxOUT
OFx_match
PHx_match
DCx_match
PRx_match
0 12 3 4 4 3 2 1 0PWMyTMR
4
1
PWMyPR
PWMyDC
PWMyOUT
0100
Note: Master = PWMx, Slave = PWMy
2015-2016 Microchip Technology Inc. DS40001819B-page 343
PIC16(L)F1777/8/9
FIGURE 26-13: OFFSET MATCH ON DECREMENTING TIMER TIMING DIAGRAM
Rev. 10 -000 151B
7/9/ 201 5
PWMxCLK
6
2
2
PWMxPR
PWMxDC
PWMxOF
Off set
Duty Cycle
Perio d
0 1 2 3 4 5 6 6 5 4 3 2 1 0 0 1 2 3PWMxTMR
PWMxOUT
OF5_match
PH5_match
DC5_match
PR5_match
PWMyTMR
4
1
PWMyPR
PWMyDC
PWMyOUT
0 1 2 3 4 4 30
Note: Master = PWMx, Slave = PWMy
PIC16(L)F1777/8/9
DS40001819B-page 344 2015-2016 Microchip Technology Inc.
26.4 Reload Operation
Four of the PWM module control register pairs and one
control bit are double buffered so that all can be
updated simultaneously. These include:
• PWMxPHH:PWMxPHL register pair
• PWMxDCH:PWMxDCL register pair
• PWMxPRH:PWMxPRL register pair
• PWMxOFH:PWMxOFL register pair
•ODO control bit
When written to, these registers do not immediately
affect the operation of the PWM. By default, writes to
these registers will not be loaded into the PWM operat-
ing buffer registers until after the arming conditions are
met. The arming control has two methods of operation:
• Immediate
• Triggered
The LDT bit of the PWMxLDCON register controls the
arming method. Both methods require the LDA bit to be
set. All four buffer pairs will load simultaneously at the
loading event.
26.4.1 IMMEDIATE RELOAD
When the LDT bit is clear then the Immediate mode is
selected and the buffers will be loaded at the first period
event after the LDA bit is set. Immediate reloading is
used when a PWM module is operating stand-alone or
when the PWM module is operating as a master to
other slave PWM modules.
26.4.2 TRIGGERED RELOAD
When the LDT bit is set then the Triggered mode is
selected and a trigger event is required for the LDA bit
to take effect. The trigger source is the buffer load
event of one of the other PWM modules in the device.
The triggering source is selected by the LDS<1:0> bits
of the PWMxLDCON register. The buffers will be
loaded at the first period event following the trigger
event. Triggered reloading is used when a PWM mod-
ule is operating as a slave to another PWM and it is
necessary to synchronize the buffer reloads in both
modules.
26.5 Operation in Sleep M ode
Each PWM module will continue to operate in Sleep
mode when either the HFINTOSC or LFINTOSC is
selected as the clock source by PWMxCLKCON<1:0>.
26.6 Interrupts
Each PWM module has four independent interrupts
based on the phase, duty cycle, period, and offset
match events. The interrupt flag is set on the rising
edge of each of these signals. Refer to Figures 26-8
and 26-12 for detailed timing diagrams of the match
signals.
Note 1: The buffer load operation clears the LDA
bit.
2: If the LDA bit is set at the same time as
PWMxTMR = PWMxPR, the LDA bit is
ignored until the next period event. Such is
the case when triggered reload is selected
and the triggering event occurs
simultaneously with the target’s period
event
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PIC16(L)F1777/8/9
26.7 Regis t er D e finiti o n s : P W M C o n tr o l
Long bit name prefixes for the 16-bit PWM peripherals
are shown in Table 26-2. Refer to Section
1.1 “Register and Bit naming conventions” for more
information
TABLE 26-2:
Peripheral Bit Name Prefix
PWM5 PWM5
PWM6 PWM6
PWM11 PWM11
PWM12(1) PWM12
Note 1: PIC16(L)F1777/9 only.
REGISTER 26-1: PWMxCON: PWM CONTROL REGISTER
R/W-0/0 U-0 R/HS/HC-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0
EN — OUT POL MODE<1:0> — —
bit 7 bit 0
Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 EN: PWM Module Enable bit
1 = Module is enabled
0 = Module is disabled
bit 6 Unimplemented: Read as ‘0’
bit 5 OUT: Output State of the PWM module
bit 4 POL: PWM Output Polarity Control bit
1 = PWM output active state is low
0 = PWM output active state is high
bit 3-2 MODE<1:0>: PWM Mode Control bits
11 = Center Aligned mode
10 = Toggle On Match mode
01 = Set On Match mode
00 = Standard PWM mode
bit 1-0 Unimplemented: Read as ‘0’
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REGISTER 26-2: PWMxINTE: PWM INTERRUPT ENABLE REGISTER
U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
———— OFIE PHIE DCIE PRIE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 Unimplemented: Read as ‘0’
bit 3 OFIE: Offset Interrupt Enable bit
1 = Interrupt CPU on Offset Match
0 = Do not interrupt CPU on Offset Match
bit 2 PHIE: Phase Interrupt Enable bit
1 = Interrupt CPU on Phase Match
0 = Do not Interrupt CPU on Phase Match
bit 1 DCIE: Duty Cycle Interrupt Enable bit
1 = Interrupt CPU on Duty Cycle Match
0 = Do not interrupt CPU on Duty Cycle Match
bit 0 PRIE: Period Interrupt Enable bit
1 = Interrupt CPU on Period Match
0 = Do not interrupt CPU on Period Match
REGISTER 26-3: PWMxINTF: PWM INTERRUPT REQUEST REGISTER
U-0 U-0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
———— OFIF PHIF DCIF PRIF
bit 7 bit 0
Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 Unimplemented: Read as ‘0’
bit 3 OFIF: Offset Interrupt Flag bit(1)
1 = Offset Match Event occurred
0 = Offset Match Event did not occur
bit 2 PHIF: Phase Interrupt Flag bit(1)
1 = Phase Match Event occurred
0 = Phase Match Event did not occur
bit 1 DCIF: Duty Cycle Interrupt Flag bit(1)
1 = Duty Cycle Match Event occurred
0 = Duty Cycle Match Event did not occur
bit 0 PRIF: Period Interrupt Flag bit(1)
1 = Period Match Event occurred
0 = Period Match Event did not occur
Note 1: Bit is forced clear by hardware while module is disabled (EN = 0).
2015-2016 Microchip Technology Inc. DS40001819B-page 347
PIC16(L)F1777/8/9
REGISTER 26-4: PWMxCLKCON: PWM CLOCK CONTROL REGISTER
U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
—PS<2:0>——CS<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 Unimplemented: Read as ‘0’
bit 6-4 PS<2:0>: Clock Source Prescaler Select bits
111 = Divide clock source by 128
110 = Divide clock source by 64
101 = Divide clock source by 32
100 = Divide clock source by 16
011 = Divide clock source by 8
010 = Divide clock source by 4
001 = Divide clock source by 2
000 = No Prescaler
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 CS<1:0>: Clock Source Select bits
11 = Reserved
10 = LFINTOSC (continues to operate during Sleep)
01 = HFINTOSC (continues to operate during Sleep)
00 = FOSC
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DS40001819B-page 348 2015-2016 Microchip Technology Inc.
REGISTER 26-5: PWMxLDCON: PWM RELOAD TRIGGER SOURCE SELECT REGISTER
R/W/HC-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0
LDA(1) LDT ————LDS<1:0>
(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware
bit 7 LDA: Load Buffer Armed bit(1)
If LDT = 1:
1 = Load the ODO bit and OFx, PHx, DCx and PRx buffers at the end of the period in which the selected
trigger occurs
0 = Do not load buffers, load has completed
If LDT = 0:
1 = Load the ODO bit and OFx, PHx, DCx and PRx buffers at the end of the current period
0 = Do not load buffers, load has completed
bit 6 LDT: Load Buffer on Trigger bit
1 = Wait for trigger selected by the LDS<1:0> bits to occur before enabling the LDA bit
0 = Load triggering is disabled. Buffer loads are controlled by the LDA bit alone.
bit 5-2 Unimplemented: Read as ‘0’
bit 1-0 LDS<1:0>: Load Trigger Source Select bits(2)
10 = LD11_trigger
01 = LD6_trigger
00 = LD5_trigger
Note 1: This bit is cleared by the module after a reload operation. It can be cleared in software to clear an existing arming
event.
2: The source corresponding to a PWM module’s own LDx_trigger is reserved.
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PIC16(L)F1777/8/9
REGISTER 26-6: PWMxOFCON: PWM OFFSET TRIGGER SOURCE SELECT REGISTER
U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
— OFM<1:0> OFO(1) ——OFS<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 Unimplemented: Read as ‘0’
bit 6-5 OFM<1:0>: Offset Mode Select bits
11 = Continuous Run Slave mode with offset triggered timer Reset and synchronized start
10 = One-shot Slave mode with offset triggered synchronized start
01 = Slave Run mode with offset triggered synchronized start
00 = Independent Run mode
bit 4 OFO: Offset Match Output Control bit(1)
If MODE<1:0> = 11 (PWM center aligned mode):
1 = OFx_match occurs when the PWMxTMR is counting up
0 = OFx_match occurs when the PWMxTMR is counting down
If MODE<1:0> = 00, 01, or 10 (all other modes):
this bit is ignored
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 OFS<1:0>: Offset Trigger Source Select bit
10 =OF11_match
01 = OF6_match
00 = OF5_match
Note 1: The source corresponding to the PWM module’s own OFx_match is reserved.
PIC16(L)F1777/8/9
DS40001819B-page 350 2015-2016 Microchip Technology Inc.
REGISTER 26-7: PWMxPHH: PWMx PHASE COUNT HIGH REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
PH<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 PH<15:8>: PWM Phase High bits
Upper eight bits of PWM phase count
REGISTER 26-8: PWMxPHL: PWMx PHASE COUNT LOW REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
PH<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 PH<7:0>: PWM Phase Low bits
Lower eight bits of PWM phase count
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PIC16(L)F1777/8/9
REGISTER 26-9: PWMxDCH: PWMx DUTY CYCLE COUNT HIGH REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
DC<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 DC<15:8>: PWM Duty Cycle High bits
Upper eight bits of PWM duty cycle count
REGISTER 26-10: PWMxDCL: PWMx DUTY CYCLE COUNT LOW REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
DC<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 DC<7:0>: PWM Duty Cycle Low bits
Lower eight bits of PWM duty cycle count
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DS40001819B-page 352 2015-2016 Microchip Technology Inc.
REGISTER 26-11: PWMxPRH: PWMx PERIOD COUNT HIGH REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
PR<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 PR<15:8>: PWM Period High bits
Upper eight bits of PWM period count
REGISTER 26-12: PWMxPRL: PWMx PERIOD COUNT LOW REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
PR<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 PR<7:0>: PWM Period Low bits
Lower eight bits of PWM period count
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REGISTER 26-13: PWMxOFH: PWMx OFFSET COUNT HIGH REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
OF<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 OF<15:8>: PWM Offset High bits
Upper eight bits of PWM offset count
REGISTER 26-14: PWMxOFL: PWMx OFFSET COUNT LOW REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
OF<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 OF<7:0>: PWM Offset Low bits
Lower eight bits of PWM offset count
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DS40001819B-page 354 2015-2016 Microchip Technology Inc.
REGISTER 26-15: PWMxTMRH: PWMx TIMER HIGH REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
TMR<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 TMR<15:8>: PWM Timer High bits
Upper eight bits of PWM timer counter
REGISTER 26-16: PWMxTMRL: PWMx TIMER LOW REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
TMR<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 TMR<7:0>: PWM Timer Low bits
Lower eight bits of PWM timer counter
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Note: There are no long and short bit name variants for the following three mirror registers
REGISTER 26-17: PWMEN: PWMEN BIT MIRROR REGISTER
U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
————MPWM12EN
(1) MPWM11EN MPWM6EN MPWM5EN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-3 Unimplemented: Read as ‘0’
bit 2-0 PWMxEN: PWM11/PWM6/PWM5 Enable bits
Mirror copy of each PWM module’s PWMxCON<7> bit
Note 1: PIC16(L)F1777/9 only.
REGISTER 26-18: PWMLD: LDA BIT MIRROR REGISTER
U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
————MPWM12LD
(1) MPWM11LD MPWM6LD MPWM5LD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-3 Unimplemented: Read as ‘0’
bit 2 MPWM11LD: PWM11LD bits
Mirror copy of each PWM module’s PWMxLDCON<7> bit
bit 1 MPWM6LD: PWM6LD bits
Mirror copy of each PWM module’s PWMxLDCON<7> bit
bit 0 MPWM5LD: PWM5LD bits
Mirror copy of each PWM module’s PWMxLDCON<7> bit
Note 1: PIC16(L)F1777/9 only.
REGISTER 26-19: PWMOUT: PWMOUT BIT MIRROR REGISTER
U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
————MPWM12OUT
(1) MPWM11OUT MPWM6OUT MPWM5OUT
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-3 Unimplemented: Read as ‘0’
bit 2 MPWM11OUT: PWM11 OUT bits
Mirror copy of each PWM module’s PWMxCON<5> bit
bit 1 MPWM6OUT: PWM6 OUT bits
Mirror copy of each PWM module’s PWMxCON<5> bit
bit 0 MPWM5OUT: PWM5 OUT bits
Mirror copy of each PWM module’s PWMxCON<5> bit
Note 1: PIC16(L)F1777/9 only.
PIC16(L)F1777/8/9
DS40001819B-page 356 2015-2016 Microchip Technology Inc.
TABLE 26-3: SUMMARY OF REGISTERS ASSOCIATED WITH PWM
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
OSCCON SPLLEN IRCF<3:0> —SCS<1:0>116
PWMEN — — — — MPWM12EN(1) MPWM11EN MPWM6EN MPWM5EN 355
PWMLD — — — — MPWM12LD(1) MPWM11LD MPWM6LD MPWM5LD 355
PWMOUT — — — —MPWM12OUT
(1) MPWM11OUT MPWM6OUT MPWM5OUT 355
PWM5PHL PH<7:0> 350
PWM5PHH PH<15:8> 350
PWM5DCL DC<7:0> 351
PWM5DCH DC<15:8> 351
PWM5PRL PR<7:0> 352
PWM5PRH PR<15:8> 352
PWM5OFL OF<7:0> 353
PWM5OFH OF<15:8> 353
PWM5TMRL TMR<7:0> 354
PWM5TMRH TMR<15:8> 354
PWM5CON EN — OUT POL MODE<1:0> — — 345
PWM5INTE — — — —OFIEPHIE
DCIE PRIE
346
PWM5INTF — — — — OFIF PHIF DCIF PRIF 346
PWM5CLKCON —PS<2:0> —— CS<1:0> 347
PWM5LDCON LDA LDT — — — —LDS<1:0>348
PWM5OFCON — OFM<1:0> OFO ——OFS<1:0>349
PWM6PHL PH<7:0> 350
PWM6PHH PH<15:8> 350
PWM6DCL DC<7:0> 351
PWM6DCH DC<15:8> 351
PWM6PRL PR<7:0> 352
PWM6PRH PR<15:8> 352
PWM6OFL OF<7:0> 353
PWM6OFH OF<15:8> 353
PWM6TMRL TMR<7:0> 354
PWM6TMRH TMR<15:8> 354
PWM6CON EN — OUT POL MODE<1:0> — — 345
PWM6INTE — — — — OFIE PHIE DCIE PRIE 346
PWM6INTF — — — — OFIF PHIF DCIF PRIF 346
PWM6CLKCON —PS<2:0> —— CS<1:0> 347
PWM6LDCON LDA LDT — — — —LDS<1:0>348
PWM6OFCON — OFM<1:0> OFO ——OFS<1:0>349
PWM11PHL PH<7:0> 350
PWM11PHH PH<15:8> 350
PWM11DCL DC<7:0> 351
PWM11DCH DC<15:8> 351
PWM11PRL PR<7:0> 352
PWM11PRH PR<15:8> 352
PWM11OFL OF<7:0> 353
PWM11OFH OF<15:8> 353
PWM11TMRL TMR<7:0> 354
PWM11TMRH TMR<15:8> 354
PWM11CON EN — OUT POL MODE<1:0> — — 345
PWM11INTE — — — — OFIE PHIE DCIE PRIE 346
PWM11INTF — — — — OFIF PHIF DCIF PRIF 346
PWM11CLKCON —PS<2:0> —— CS<1:0> 347
PWM11LDCON LDA LDT — — — —LDS<1:0>348
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PWM.
Note 1: PIC16(L)F1777/9 only.
2015-2016 Microchip Technology Inc. DS40001819B-page 357
PIC16(L)F1777/8/9
TABLE 26-3: SUMMARY OF REGISTERS ASSOCIATED WITH PWM (CONTINUED)
TABLE 26-4: SUMMARY OF CONFIGURATION WORDS WITH CLOCK SOURCES
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
PWM11OFCON —OFM<1:0>OFO——OFS<1:0>349
PWM12PHL(1) PH<7:0> 350
PWM12PHH(1) PH<15:8> 350
PWM12DCL(1) DC<7:0> 351
PWM12DCH(1) DC<15:8> 351
PWM12PRL(1) PR<7:0> 352
PWM12PRH(1) PR<15:8> 352
PWM12OFL(1) OF<7:0> 353
PWM12OFH(1) OF<15:8> 353
PWM12TMRL(1) TMR<7:0> 354
PWM12TMRH(1) TMR<15:8> 354
PWM12CON(1) EN —OUTPOL MODE<1:0> — — 345
PWM12INTE(1) ———— OFIE PHIE DCIE PRIE 346
PWM12INTF(1) ———— OFIF PHIF DCIF PRIF 346
PWM12CLKCON(1) —PS<2:0>—— CS<1:0> 347
PWM12LDCON(1) LDA LDT ————LDS<1:0>348
PWM12OFCON(1) —OFM<1:0>OFO——OFS<1:0>349
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PWM.
Note 1: PIC16(L)F1777/9 only.
Name Bits Bit -/7 B it -/6 Bit 13/5 Bit 12/4 B it 11/3 Bit 10/2 Bit 9/1 Bit 8/0 R egister
on Page
CONFIG1 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> —95
7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
PIC16(L)F1777/8/9
DS40001819B-page 358 2015-2016 Microchip Technology Inc.
NOTES:
2015-2016 Microchip Technology Inc. DS40001819B-page 359
PIC16(L)F1777/8/9
27.0 COMPLEMENTARY OUTPUT
GENERATOR (COG) MODU LES
The primary purpose of the Complementary Output
Generator (COG) is to convert a single-output PWM sig-
nal into a two-output complementary PWM signal. The
COG can also convert two separate input events into a
single or complementary PWM output.
The COG PWM frequency and duty cycle are
determined by a rising event input and a falling event
input. The rising event and falling event may be the
same source. Sources may be synchronous or
asynchronous to the COG_clock.
The rate at which the rising event occurs determines
the PWM frequency. The time from the rising event to
the falling event determines the duty cycle.
A selectable clock input is used to generate the phase
delay, blanking, and dead-band times. Dead-band time
can also be generated with a programmable delay
chain, which is independent from all clock sources.
Simplified block diagrams of the various COG modes
are shown in Figure 27-2 through Figure 27-6.
The COG module has the following features:
• Six modes of operation:
- Steered PWM mode
- Synchronous Steered PWM mode
- Forward Full-Bridge mode
- Reverse Full-Bridge mode
- Half-Bridge mode
- Push-Pull mode
• Selectable COG_clock clock source
• Independently selectable rising event sources
• Independently selectable falling event sources
• Independently selectable edge or level event
sensitivity
• Independent output polarity selection
• Phase delay with independent rising and falling
delay times
• Dead-band control with:
- independent rising and falling event
dead-band times
- Synchronous and asynchronous timing
• Blanking control with independent rising and
falling event blanking times
• Auto-shutdown control with:
- Independently selectable shutdown sources
- Auto-restart enable
- Auto-shutdown pin override control
(high, low, off, and High-Z)
27.1 Output to Pins (all modes)
The COG peripheral has four outputs: COGA, COGB,
COGC, and COGD.
The operating mode, selected with the MD<2:0> bits of
the COGxCON0 register, determine the waveform
available at each output. An individual peripheral
source control for each device pin selects the pin or
pins at which the outputs will appear. Please refer to the
RxyPPS register (Register 12-2) for more information.
27.2 Event-Driven PWM (All Modes)
Besides generating PWM and complementary outputs
from a single PWM input, the COG can also generate
PWM waveforms from a periodic rising event and a
separate falling event. In this case, the falling event is
usually derived from analog feedback within the
external PWM driver circuit. In this configuration,
high-power switching transients may trigger a false
falling event that needs to be blanked out. The COG
can be configured to blank falling (and rising) event
inputs for a period of time immediately following the
rising (and falling) event drive output. This is referred to
as input blanking and is covered in Section 27.8
“Blanking Co ntrol”.
It may be necessary to guard against the possibility of
external circuit faults. In this case, the active drive must
be terminated before the Fault condition causes
damage. This is referred to as auto-shutdown and is
covered in Section 27.10 “Auto-Shutdown Control”.
The COG can be configured to operate in phase
delayed conjunction with another PWM. The active
drive cycle is delayed from the rising event by a phase
delay timer. Phase delay is covered in more detail in
Section 27.9 “Phase Delay”.
A typical operating waveform, with phase delay and
dead band, generated from a single CCP1 input is
shown in Figure 27-10.
TABLE 27-1: AVAILABLE COG MODULES
Device COG1 COG2 COG3 COG4
PIC16(L)F1778 ●●●
PIC16(L)F1777/9 ●●●●
PIC16(L)F1777/8/9
DS40001819B-page 360 2015-2016 Microchip Technology Inc.
27.3 Modes of Operation
27.3.1 STEERED PWM MODES
In Steered PWM mode, the PWM signal derived from
the input event sources is output as a single phase
PWM which can be steered to any combination of the
four COG outputs. Output steering takes effect on the
instruction cycle following the write to the COGxSTR
register.
Synchronous Steered PWM mode is identical to the
Steered PWM mode except that changes to the output
steering take effect on the first rising event after the
COGxSTR register write. Static output data is not
synchronized.
Steering mode configurations are shown in Figure 27-2
and Figure 27-3.
Steered PWM and Synchronous Steered PWM modes
are selected by setting the MD<2:0> bits of the
COGxCON0 register (Register 27-1) to ‘000’ and
‘001’, respectively.
27.3.2 FULL-BRIDGE MODES
In both Forward and Reverse Full-Bridge modes, two of
the four COG outputs are active and the other two are
inactive. Of the two active outputs, one is modulated by
the PWM input signal and the other is on at 100% duty
cycle. When the direction is changed, the dead-band
time is inserted to delay the modulated output. This
gives the unmodulated driver time to shut down,
thereby, preventing shoot-through current in the series
connected power devices.
In Forward Full-Bridge mode, the PWM input
modulates the COGxD output and drives the COGA
output at 100%.
In Reverse Full-Bridge mode, the PWM input
modulates the COGxB output and drives the COGxC
output at 100%.
The full-bridge configuration is shown in Figure 27-4.
Typical full-bridge waveforms are shown in
Figure 27-12 and Figure 27-13.
Full-Bridge Forward and Full-Bridge Reverse modes
are selected by setting the MD<2:0> bits of the
COGxCON0 register to ‘010’ and ‘011’, respectively.
FIGURE 27-1: EXAMP LE OF FULL-BRIDGE APPLICA TION
FET
Driver
FET
Driver
V+
V-
Load
FET
Driver
FET
Driver
QA
QB QD
QC
COGxA
COGxC
COGxB
COGxD
2015-2016 Microchip Technology Inc. DS40001819B-page 361
PIC16(L)F1777/8/9
27.3.3 HALF-BRIDGE MODE
In Half-Bridge mode, the COG generates a two output
complementary PWM waveform from rising and falling
event sources. In the simplest configuration, the rising
and falling event sources are the same signal, which is
a PWM signal with the desired period and duty cycle.
The COG converts this single PWM input into a dual
complementary PWM output. The frequency and duty
cycle of the dual PWM output match those of the single
input PWM signal. The off-to-on transition of each
output can be delayed from the on-to-off transition of
the other output, thereby, creating a time immediately
after the PWM transition where neither output is driven.
This is referred to as dead-band time and is covered in
Section 27.7 “Dead-Band Control”.
The half-bridge configuration is shown in Figure 27-5. A
typical operating waveform, with dead band, generated
from a single CCP1 input is shown in Figure 27-9.
The primary output is available on either, or both, COGxA
and COGxC. The complementary output is available on
either, or both, COGxB and COGxD.
Half-Bridge mode is selected by setting the MD<2:0>
bits of the COGxCON0 register to ‘100’.
27.3.4 PUSH-PULL MODE
In Push-Pull mode, the COG generates a single PWM
output that alternates between the two pairs of the
COG outputs at every PWM period. COGxA has the
same signal as COGxC. COGxB has the same signal
as COGxD. The output drive activates with the rising
input event and terminates with the falling event input.
Each rising event starts a new period and causes the
output to switch to the COG pair not used in the previ-
ous period.
The Push-Pull configuration is shown in Figure 27-6. A
typical Push-Pull waveform generated from a single
CCP1 input is shown in Figure 27-11.
Push-Pull mode is selected by setting the MD<2:0> bits
of the COGxCON0 register to ‘101’.
PIC16(L)F1777/8/9
DS40001819B-page 362 2015-2016 Microchip Technology Inc.
FIGURE 27-2: SIMPLIFIED COG BLOCK DIAGRAM (STEERED PWM MODE, MD = 0)
COG_clock
CS<1:0> ASDBD<1:0>
ASDAC<1:0>
POLA
POLB
ARSEN
SQ
R0
1
0
1
SQ
RDQ
Write ASE Low
ASE
Auto-shutdown source
Set Dominates
Q
Reset Dominates
S
EN
clock
count_en
rising_event
clock
count_en
falling_event
src0
src15
Rising Input Block
Falling Input Block
ASDBD<1:0>
ASDAC<1:0>
POLC
POLD
0
1
0
1
0
1
SDATC
0
1
STRD
SDATD
0
1
STRB
SDATB
0
1
STRA
SDATA
STRC
Fosc/4
Fosc
HFINTOSC
00
01
10
11
Reserved
COGxA
COGxB
COGxC
COGxD
‘1’
‘0’
Hi-Z 01
00
10
11
‘1’
‘0’
Hi-Z 01
00
10
11
‘1’
‘0’
Hi-Z 01
00
10
11
‘1’
‘0’
Hi-Z 01
00
10
11
src0
src15
Rising event sources
See Register 27-3 and
Register 27-4.
Falling event sources
See Register 27-7 and
Register 27-8.
Write ASE High
Source 7
AS7E
Source 0
AS0E
Shutdown sources
See Register 27-12.
2015-2016 Microchip Technology Inc. DS40001819B-page 363
PIC16(L)F1777/8/9
FIGURE 27-3: SI MPLIFI ED COG BLOCK DIAGRAM (SYNCHRONOUS STEERED PWM MODE, MD = 1)
COG_clock
CS<1:0> ASDBD<1:0>
ASDAC<1:0>
POLA
POLB
ARSEN
SQ
R0
1
0
1
SQ
RDQ
Write ASE Low
ASE
Auto-shutdown source
Set Dominates
Q
Reset Dominates
S
EN
clock
count_en
rising_event
clock
count_en
falling_event
Rising Input Block
Falling Input Block
ASDBD<1:0>
ASDAC<1:0>
POLC
POLD
0
1
0
1
0
1
SDATC
0
1
STRD
SDATD
0
1
STRB
SDATB
0
1
STRA
SDATA
STRC
Fosc/4
Fosc
HFINTOSC
00
01
10
11
Reserved
COGxA
COGxB
COGxC
COGxD
‘1’
‘0’
High-Z 01
00
10
11
‘1’
‘0’
High-Z 01
00
10
11
‘1’
‘0’
High-Z 01
00
10
11
‘1’
‘0’
High-Z 01
00
10
11
DQ
DQ
DQ
DQ
src0
src15
src0
src15
Rising event sources
See Register 27-3 and
Register 27-4.
Falling event sources
See Register 27-7 and
Register 27-8.
Write ASE High
Source 7
AS7E
Source 0
AS0E
Shutdown sources
See Register 27-12.
PIC16(L)F1777/8/9
DS40001819B-page 364 2015-2016 Microchip Technology Inc.
FIGURE 27-4: SIMPLIFIED COG BLOCK DIAGRAM (FULL-BRIDGE MODES, FORWARD: MD = 2, REVERSE: MD = 3)
COG_clock
CS<1:0> ASDBD<1:0>
ASDAC<1:0>
POLA
POLB
ARSEN
SQ
R0
1
0
1
SQ
RDQ
Write ASE Low
ASE
Auto-shutdown source
Set Dominates
Q
Reset Dominates
S
EN
clock
count_en
rising_event
clock
count_en
falling_event
Rising Input Block
Falling Input Block
ASDBD<1:0>
ASDAC<1:0>
POLC
POLD
0
1
0
1
Fosc/4
Fosc
HFINTOSC
00
01
10
11
Reserved
COGxA
COGxB
COGxC
COGxD
‘1’
‘0’
High-Z 01
00
10
11
‘1’
‘0’
High-Z 01
00
10
11
‘1’
‘0’
High-Z 01
00
10
11
‘1’
‘0’
High-Z 01
00
10
11
clock
signal_in
signal_out
clock
signal_in
signal_out
Rising Dead-Band Block
Falling Dead-Band Block
DQ
Q
Forward/Reverse
MD0
src0
src15
src0
src15
Rising event sources
See Register 27-3
and Register 27-4.
Falling event sources
See Register 27-7 and
Register 27-8.
Write ASE High
Source 7
AS7E
Source 0
AS0E
Shutdown sources
See Register 27-12.
2015-2016 Microchip Technology Inc. DS40001819B-page 365
PIC16(L)F1777/8/9
FIGURE 27-5: SIMPLIFIED COG BLOCK DIAGRAM (HALF-BRIDGE MODE, MD = 4)
COG_clock
CS<1:0>
ARSEN
SQ
R
SQ
R
Write ASE Low
Auto-shutdown source
Set Dominates
Q
Reset Dominates
EN
clock
count_en
rising_event
clock
count_en
falling_event
Rising Input Block
Falling Input Block
Fosc/4
Fosc
HFINTOSC
00
01
10
11
reserved
clock
signal_in
signal_out
clock
signal_in
signal_out
Rising Dead-Band Block
Falling Dead-Band Block
ASDBD<1:0>
ASDAC<1:0>
POLA
POLB
0
1
0
1
DQ
ASE
S
ASDBD<1:0>
ASDAC<1:0>
POLC
POLD
0
1
0
1
COGxA
COGxB
COGxC
COGxD
‘1’
‘0’
High-Z 01
00
10
11
‘1’
‘0’
High-Z 01
00
10
11
‘1’
‘0’
High-Z 01
00
10
11
‘1’
‘0’
High-Z 01
00
10
11
src0
src15
src0
src15
Rising event sources
See Register 27-3
and Register 27-4.
Falling event sources
See Register 27-7 and
Register 27-8.
Write ASE High
Source 7
AS7E
Source 0
AS0E
Shutdown sources
See Register 27-12.
PIC16(L)F1777/8/9
DS40001819B-page 366 2015-2016 Microchip Technology Inc.
FIGURE 27-6: SIMPLIFIED COG BLOCK DIAGRAM (PUSH-PULL MODE, MD = 5)
COG_clock
CS<1:0>
ARSEN
SQ
R
SQ
R
Write ASE Low
Auto-shutdown source
Set Dominates
Q
Reset Dominates
EN
clock
count_en
rising_event
clock
count_en
falling_event
Rising Input Block
Falling Input Block
Fosc/4
Fosc
HFINTOSC
00
01
10
11
reserved
DQ
Q
Push-Pull
R
ASDBD<1:0>
ASDAC<1:0>
POLA
POLB
0
1
0
1
DQ
ASE
S
ASDBD<1:0>
ASDAC<1:0>
POLC
POLD
0
1
0
1
COGxA
COGxB
COGxC
COGxD
‘1’
‘0’
High-Z 01
00
10
11
‘1’
‘0’
High-Z 01
00
10
11
‘1’
‘0’
High-Z 01
00
10
11
‘1’
‘0’
High-Z 01
00
10
11
src0
src15
src0
src15
Rising event sources
See Register 27-3
and Register 27-4.
Falling event sources
See Register 27-7 and
Register 27-8.
Write ASE High
Source 7
AS7E
Source 0
AS0E
Shutdown sources
See Register 27-12.
2015-2016 Microchip Technology Inc. DS40001819B-page 367
PIC16(L)F1777/8/9
FIGURE 27-7: COG (RISING/FALLING) INPUT BLOCK
FIGURE 27-8: COG (RISING/FALLING) DEAD-BAND BLOCK
Phase
Delay
PH(R/F)<3:0>
Blanking
Cnt/Clr
BLK(F/R)<3:0>
=
0
1
clock
0
1
(R/F)SIM15
(R/F)SIM0
(rising/falling)_event
(R/F)IS0
(R/F)IS15
src15
src0
count_en
LE
DQ
LE
DQ
src1 through src14
(R/F)IS1 through (R/F)IS14
(R/F)SIM1 through (R/F)SIM14
DBR<3:0>
Cnt/Clr =
Asynchronous
Delay Chain
1
0
1
0
clock
signal_in signal_out
Synchronous
Delay
(R/F)DBTS
PIC16(L)F1777/8/9
DS40001819B-page 368 2015-2016 Microchip Technology Inc.
FIGURE 27-9: TYPICAL HALF-BRIDGE MODE COG OPERATION WITH CCP1
FIGURE 27-10: HALF-BRIDGE MODE COG OPERATION WITH CCP1 AND PHASE DELAY
FIGURE 27-11: PUSH-PULL MODE COG OPERATION WITH CCP1
falling event dead band
rising event dead band
falling event dead band
COG_clock
CCP1
COGxA
COGxB
Source
falling event
rising event
Phase Delayfalling event dead band
CCP1
COGxA
COGxB
COG_clock
Source
dead band
dead band
CCP1
COGxA
COGxB
2015-2016 Microchip Technology Inc. DS40001819B-page 369
PIC16(L)F1777/8/9
FIGURE 27-12: F ULL-BRIDGE FORWARD MODE COG OPERATION WITH CCP1
FIGURE 27-13: FULL-BRIDGE MODE COG OPERATION WITH CCP1 AND DIRECTION CHANGE
CCP1
COGxA
COGxB
COGxC
COGxD
CCP1
COGxA
COGxB
COGxC
COGxD
MD0
falling event dead band
PIC16(L)F1777/8/9
DS40001819B-page 370 2015-2016 Microchip Technology Inc.
27.4 Clock Sources
The COG_clock is used as the reference clock to the
various timers in the peripheral. Timers that use the
COG_clock include:
• Rising and falling dead-band time
• Rising and falling blanking time
• Rising and falling event phase delay
Clock sources available for selection include:
• 16 MHz HFINTOSC (active during Sleep)
• Instruction clock (FOSC/4)
• System clock (FOSC)
The clock source is selected with the CS<1:0> bits of
the COGxCON0 register (Register 27-1).
27.5 Selectable Event Sources
The COG uses any combination of independently
selectable event sources to generate the complementary
waveform. Sources fall into two categories:
• Rising event sources
• Falling event sources
The rising event sources are selected by setting bits in
the COGxRIS0 and COGxRIS1 registers (Register 27-3
and Register 27-4). The falling event sources are
selected by setting bits in the COGxFIS0 and COGxF1
registers (Register 27-7 and Register 27-8). All selected
sources are OR’d together to generate the correspond-
ing event signal. Refer to Figure 27-7.
27.5.1 EDGE VS. LEVEL SENSING
Event input detection may be selected as level or edge
sensitive. The detection mode is individually selectable
for every source. Rising source detection modes are
selected with the COGxRSIM0 and COGxRSIM1
registers (Register 27-5 and Register 27-6). Falling
source detection modes are selected with the
COGxFSIM0 and COGxFSIM1 registers (Register 27-9
and Register 27-10). A set bit selects edge detection for
the corresponding event source. A cleared bit selects
level detection.
In general, events that are driven from a periodic
source should be edge detected and events that are
derived from voltage thresholds at the target circuit
should be level sensitive. Consider the following two
examples:
1. The first example is an application in which the
period is determined by a 50% duty cycle clock on the
rising event input and the COG output duty cycle is
determined by a voltage level fed back through a com-
parator on the falling event input. If the clock input is
level sensitive, duty cycles less than 50% will exhibit
erratic operation because the level sensitive clock will
suppress the comparator feedback.
2. The second example is similar to the first except that
the duty cycle is close to 100%. The feedback
comparator high-to-low transition trips the COG drive
off, but almost immediately the period source turns the
drive back on. If the off cycle is short enough, the
comparator input may not reach the low side of the
hysteresis band precluding an output change. The
comparator output stays low and without a high-to-low
transition to trigger the edge sense, the drive of the
COG output will be stuck in a constant drive-on
condition. See Figure 27-14.
FIGURE 2 7-14: EDGE VS. LEVEL SENSE
Rising (CCP1)
Falling (C1OUT)
C1IN-
COGOUT
hyst
Edge Sensitive
Rising (CCP1)
Falling (C1OUT)
C1IN-
COGOUT
hyst
Level Sensitive
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27.5.2 RISING EVENT
The rising event starts the PWM output active duty
cycle period. The rising event is the low-to-high
transition of the rising_event output. When the rising
event phase delay and dead-band time values are zero,
the primary output starts immediately. Otherwise, the
primary output is delayed. The rising event source
causes all the following actions:
• Start rising event phase delay counter (if enabled).
• Clear complementary output after phase delay.
• Start falling event input blanking (if enabled).
• Start dead-band delay (if enabled).
• Set primary output after dead-band delay expires.
27.5.3 FALLING EVENT
The falling event terminates the PWM output active duty
cycle period. The falling event is the high-to-low
transition of the falling_event output. When the falling
event phase delay and dead-band time values are zero,
the complementary output starts immediately. Otherwise,
the complementary output is delayed. The falling event
source causes all the following actions:
• Start falling event phase delay counter (if enabled).
• Clear primary output.
• Start rising event input blanking (if enabled).
• Start falling event dead-band delay (if enabled).
• Set complementary output after dead-band delay
expires.
27.6 Output Control
Upon disabling, or immediately after enabling the COG
module, the primary COG outputs are inactive and
complementary COG outputs are active.
27.6.1 OUTPUT ENABLES
There are no output enable controls in the COG
module. Instead, each device pin has an individual
output selection control called the PPS register. All
four COG outputs are available for selection in the
PPS register of every pin.
When a COG output is enabled by PPS selection, the
output on the pin has several possibilities which
depend on the mode, steering control, EN bit, and
shutdown state as shown in Table 27-2 and Table 27-3.
.
27.6.2 POLARITY CONTROL
The polarity of each COG output can be selected
independently. When the output polarity bit is set, the
corresponding output is active-low. Clearing the output
polarity bit configures the corresponding output as
active-high. However, polarity affects the outputs in
only one of the four shutdown override modes. See
Section 27.10 “Auto-Shutdown Control” for more
details.
Output polarity is selected with the POLA through POLD
bits of the COGxCON1 register (Register 27-2).
27.7 Dead-Band Control
The dead-band control provides for non-overlapping
PWM output signals to prevent shoot-through current
in the external power switches. Dead-band time
affects the output only in the Half-Bridge mode and
when changing direction in the Full-Bridge mode.
The COG contains two dead-band timers. One
dead-band timer is used for rising event dead-band
control. The other is used for falling event dead-band
control. Timer modes are selectable as either:
• Asynchronous delay chain
• Synchronous counter
The Dead-Band Timer mode is selected for the rising
event and falling event dead-band times with the
respective RDBS and FDBS bits of the COGxCON1
register (Register 27-2).
In Half-Bridge mode, the rising event dead-band time
delays all selected primary outputs from going active
for the selected dead-band time after the rising event.
COGxA and COGxC are the primary outputs in
Half-Bridge mode.
In Half-Bridge mode, the falling event dead-band time
delays all selected complementary outputs from going
active for the selected dead-band time after the falling
event. COGxB and COGxD are the complementary
outputs in Half-Bridge mode.
In Full-Bridge mode, the dead-band delay occurs only
during direction changes. The modulated output is
delayed for the falling event dead-band time after a
direction change from forward to reverse. The
modulated output is delayed for the rising event
dead-band time after a direction change from reverse
to forward.
TABLE 27-2: PIN OUTPUT STATES
MD<2:0> = 00x
EN STR bit Shutdown Output
x0Inactive Static steering data
x1Active Shutdown override
01Inactive Inactive state
11Inactive Active PWM signal
TABLE 27-3: PIN OUTPUT STATES
MD<2:0> > 001
EN STR bit Shutdown Output
xxInactive Inactive state
xxActive Shutdown override
1xInactive Active PWM signal
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27.7.1 ASYNCHRONOUS DELAY CHAIN
DEAD-BAND DELAY
Asynchronous dead-band delay is determined by the
time it takes the input to propagate through a series of
delay elements. Each delay element is a nominal five
nanoseconds.
For rising event asynchronous dead-band delay set the
RDBS bit of the COGxCON0 register and set the
COGxDBR register (Register 27-14) value to the
desired number of delay elements in the rising event
dead-band time.
For falling event asynchronous dead-band delay set
the FDBS bit of the COGxCON0 register and set the
COGxDBF register (Register 27-15) value to the
desired number of delay elements in the falling event
dead-band time.
Setting the value to zero disables dead-band delay.
27.7.2 SYNCHRONOUS COUNTER
DEAD-BAND DELAY
Synchronous counter dead band is timed by counting
COG_clock periods from zero up to the value in the
dead-band count register. Use Equation 27-1 to
calculate dead-band times.
For rising event synchronous dead-band delay clear
the RDBS bit of the COGxCON0 register and set the
COGxDBR count register value to the number of
COG_clock periods in the rising event dead-band
time.
For falling event synchronous dead-band delay clear
the FDBS bit of the COGxCON0 register and set the
COGxDBF count register value to the number of
COG_clock periods in the falling event dead-band
time.
When the value is zero, dead-band delay is disabled.
27.7.3 SYNCHRONOUS COUNTER
DEAD-BAND TIME UNCERTAINTY
When the rising and falling events that trigger the
dead-band counters come from asynchronous inputs,
it creates uncertainty in the synchronous counter
dead-band time. The maximum uncertainty is equal to
one COG_clock period. Refer to Example 27-1 for
more detail.
When event input sources are asynchronous with no
phase delay, use the Asynchronous Delay Chain
Dead-Band mode to avoid the dead-band time
uncertainty.
27.7.4 RISING EVENT DEAD BAND
Rising event dead band delays the turn-on of the
primary outputs from when complementary outputs are
turned off. The rising event dead-band time starts
when the rising_ event output goes true.
See Section 27.7.1 “Asynchronous Delay Chain
Dead-Band Delay” and Section 27.7.2
“Synchronous Counter Dead-Band Delay” for more
information on setting the rising edge dead-band time.
27.7.5 FALLING EVENT DEAD BAND
Falling event dead band delays the turn-on of
complementary outputs from when the primary outputs
are turned off. The falling event dead-band time starts
when the falling_event output goes true.
See Section 27.7.1 “Asynchronous Delay Chain
Dead-Band Delay” and Section 27.7.2
“Synchronous Counter Dead-Band Delay” for more
information on setting the rising edge dead-band time.
27.7.6 DEAD-BAND OVERLAP
There are two cases of potential dead-band overlap:
• Rising-to-falling
• Falling-to-rising
27.7.6.1 Rising-to-Falling Overlap
In this case, the falling event occurs while the rising
event dead-band counter is still counting. When this
happens, the primary drives are suppressed and the
dead band extends by the falling event dead-band
time. At the termination of the extended dead-band
time, the complementary drive goes true.
27.7.6.2 Falling-to-Rising Overlap
In this case, the rising event occurs while the falling
event dead-band counter is still counting. When this
happens, the complementary drive is suppressed and
the dead band extends by the rising event dead-band
time. At the termination of the extended dead-band
time, the primary drive goes true.
27.8 Blanking Control
Input blanking is a function whereby the event inputs
can be masked or blanked for a short period of time.
This is to prevent electrical transients caused by the
turn-on/off of power components from generating a
false input event.
The COG contains two blanking counters: one
triggered by the rising event and the other triggered by
the falling_event. The counters are cross coupled with
the events they are blanking. The falling event
blanking counter is used to blank rising input events
and the rising event blanking counter is used to blank
falling input events. Once started, blanking extends for
the time specified by the corresponding blanking
counter.
Blanking is timed by counting COG_clock periods from
zero up to the value in the blanking count register. Use
Equation 27-1 to calculate blanking times.
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27.8.1 FALLING EVENT BLANKING OF
RISING EVENT INPUTS
The falling event blanking counter inhibits rising event
inputs from triggering a rising event. The falling event
blanking time starts when the rising_event output drive
goes false.
The falling event blanking time is set by the value
contained in the COGxBLKF register (Register 27-17).
Blanking times are calculated using the formula shown
in Equation 27-1.
When the COGxBLKF value is zero, falling event
blanking is disabled and the blanking counter output is
true, thereby, allowing the event signal to pass straight
through to the event trigger circuit.
27.8.2 RISING EVENT BLANKING OF
FALLING EVENT INPUTS
The rising event blanking counter inhibits falling event
inputs from triggering a falling event. The rising event
blanking time starts when the falling_event output
drive goes false.
The rising event blanking time is set by the value
contained in the COGxBLKR register (Register 27-16).
When the COGxBLKR value is zero, rising event
blanking is disabled and the blanking counter output is
true, thereby, allowing the event signal to pass straight
through to the event trigger circuit.
27.8.3 BLANKING TIME UNCERTAINTY
When the rising and falling sources that trigger the
blanking counters are asynchronous to the
COG_clock, it creates uncertainty in the blanking time.
The maximum uncertainty is equal to one COG_clock
period. Refer to Equation 27-1 and Example 27-1 for
more detail.
27.9 Phase Delay
It is possible to delay the assertion of either or both the
rising event and falling events. This is accomplished
by placing a non-zero value in COGxPHR or
COGxPHF phase-delay count registers, respectively
(Register 27-18 and Register 27-19). Refer to
Figure 27-10 for COG operation with CCP1 and phase
delay. The delay from the input rising event signal
switching to the actual assertion of the events is
calculated the same as the dead-band and blanking
delays. Refer to Equation 27-1.
When the phase-delay count value is zero, phase
delay is disabled and the phase-delay counter output
is true, thereby, allowing the event signal to pass
straight through to the complementary output driver
flop.
27.9.1 CUMULATIVE UNCERTAINTY
It is not possible to create more than one COG_clock of
uncertainty by successive stages. Consider that the
phase-delay stage comes after the blanking stage, the
dead-band stage comes after either the blanking or
phase-delay stages, and the blanking stage comes
after the dead-band stage. When the preceding stage
is enabled, the output of that stage is necessarily
synchronous with the COG_clock, which removes any
possibility of uncertainty in the succeeding stage.
EQUATION 27-1: PHASE, DEAD-BAND,
AND BLANKING TIME
CALCULATION
Tmin Count
FCOG_clock
---------------------------------=
Tmax Count 1+
FCOG_clock
---------------------------------=
Tuncertainty Tmax Tmin
–=
Tuncertainty 1
FCOG_clock
---------------------------------=
Also:
Where:
T Count
Rising Phase Delay COGxPHR
Falling Phase Delay COGxPHF
Rising dead band COGxDBR
Falling dead band COGxDBF
Rising Event Blanking COGxBLKR
Falling Event Blanking COGxBLKF
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EXAMPLE 27-1: TIMER UNCERTAI NTY
27.10 Auto-Shutdown Control
Auto-shutdown is a method to immediately override
the COG output levels with specific overrides that
allow for safe shutdown of the circuit.
The shutdown state can be either cleared
automatically or held until cleared by software. In
either case, the shutdown overrides remain in effect
until the first rising event after the shutdown is cleared.
27.10.1 SHUTDOWN
The shutdown state can be entered by either of the
following two mechanisms:
• Software generated
• External Input
27.10.1.1 Software Generated Shutdown
Setting the ASE bit of the COGxASD0 register
(Register 27-11) will force the COG into the shutdown
state.
When auto-restart is disabled, the shutdown state will
persist until the first rising event after the ASE bit is
cleared by software.
When auto-restart is enabled, the ASE bit will clear
automatically and resume operation on the first rising
event after the shutdown input clears. See
Figure 27-15 and Section 27.10.3.2 “Auto-Restart”.
27.10.1.2 External Shutdown Source
External shutdown inputs provide the fastest way to
safely suspend COG operation in the event of a Fault
condition. When any of the selected shutdown inputs
go true, the output drive latches are reset and the
COG outputs immediately go to the selected override
levels without software delay.
Any combination of the input sources can be selected
to cause a shutdown condition. Shutdown occurs
when the selected source is low. Shutdown input
sources include:
• Any input pin selected with the COGxINPPS
control
• Comparator 1
• Comparator 2
• Comparator 3
• Comparator 4
• CLC2 output/CLC4 output
• Timer2 output/Timer6 output
• Timer4 output/Timer8 output
Shutdown inputs are selected independently with bits
of the COGxASD1 register (Register 27-12).
27.10.2 PIN OVERRIDE LEVELS
The levels driven to the output pins, while the
shutdown is active, are controlled by the ASDAC<1:0>
and ASDBC<1:0> bits of the COGxASD0 register
(Register 27-11). ASDAC<1:0> controls the COGxA
and COGxC override levels and ASDBC<1:0> controls
the COGxB and COGxD override levels. There are
four override options for each output pair:
•Forced low
• Forced high
• Tri-state
• PWM inactive state (same state as that caused by
a falling event)
Given:
Therefore:
Count Ah 10d==
FCOG_Clock 8MHz=
Tuncertainty 1
FCOG_clock
---------------------------------=
1
8MHz
---------------=125ns=
Proof:
Tmin Count
FCOG_clock
---------------------------------=
125ns 10d=1.25s=
Tmax Count 1+
FCOG_clock
---------------------------------=
125ns 10d1+=
1.375s=
Therefore:
Tuncertainty Tmax Tmin
–=
1.375s1.25s–=
125ns=
Note: Shutdown inputs are level sensitive, not
edge sensitive. The shutdown state
cannot be cleared as long as the
shutdown input level persists, except by
disabling auto-shutdown,
Note: The polarity control does not apply to the
forced low and high override levels but
does apply to the PWM inactive state.
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27.10.3 AUTO-SHUTDOWN RESTART
After an auto-shutdown event has occurred, there are
two ways to resume operation:
• Software controlled
• Auto-restart
The restart method is selected with the ARSEN bit of
the COGxASD0 register. Waveforms of a software con-
trolled automatic restart are shown in Figure 27-15.
27.10.3.1 Software Controlled Restart
When the ARSEN bit of the COGxASD0 register is
cleared, software must clear the ASE bit to restart
COG operation after an auto-shutdown event.
The COG will resume operation on the first rising
event after the ASE bit is cleared. Clearing the
shutdown state requires all selected shutdown inputs
to be false, otherwise, the ASE bit will remain set.
27.10.3.2 Auto-Restart
When the ARSEN bit of the COGxASD0 register is
set, the COG will restart from the auto-shutdown state
automatically.
The ASE bit will clear automatically and the COG will
resume operation on the first rising event after all
selected shutdown inputs go false.
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FIGURE 27-15: AUTO-SHUTDOWN WAVEFORM – CCP1 AS RISING AND FALLING EVENT INPUT SOURCE
1 2 3 4 5
Next rising event
Next rising event
Cleared in software
Cleared in hardware
NORMAL OUTPUT SHUTDOWN NORMAL OUTPUT SHUTDOWN NORMAL OUTPUT
SOFTWARE CONTROLLED RESTART AUTO-RESTART
CCP1
ARSEN
Shutdown input
ASE
ASDAC
ASDBD
COGxA
COGxB
Operating State
2b00
2b00 2b00
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27.11 Buffer Updates
Changes to the phase, dead-band, and blanking count
registers need to occur simultaneously during COG
operation to avoid unintended operation that may
occur as a result of delays between each register
write. This is accomplished with the LD bit of the
COGxCON0 register and double buffering of the
phase, blanking and dead-band count registers.
Before the COG module is enabled, writing the count
registers loads the count buffers without need of the
LD bit. However, when the COG is enabled, the count
buffer updates are suspended after writing the count
registers until after the LD bit is set. When the LD bit is
set, the phase, dead-band and blanking register val-
ues are transferred to the corresponding buffers syn-
chronous with COG operation. The LD bit is cleared by
hardware when the transfer is complete.
27.12 Input and Output Pin Selection
The COG has one selection for an input from a device
pin. That one input can be used as rising and falling
event source or a fault source. The COGxINPPS reg-
ister is used to select the pin. Refer to registers
xxxPPS (Register 12-1) and RxyPPS (Register 12-2).
The pin PPS control registers are used to enable the
COG outputs. Any combination of outputs to pins is
possible including multiple pins for the same output.
See the RxyPPS control register and Section 12.2
“PPS Outputs” for more details.
27.13 Operation During Sleep
The COG continues to operate in Sleep provided that
the COG_clock, rising event, and falling event sources
remain active.
The HFINTSOC remains active during Sleep when the
COG is enabled and the HFINTOSC is selected as the
COG_clock source.
27.14 Configuring the COG
The following steps illustrate how to properly configure
the COG to ensure a synchronous start with the rising
event input:
1. If a pin is to be used for the COG fault or event
input, use the COGxINPPS register to configure
the desired pin.
2. Clear all ANSEL register bits associated with
pins that are used for COG functions.
3. Ensure that the TRIS control bits corresponding
to the COG outputs to be used are set so that all
are configured as inputs. The COG module will
enable the output drivers as needed later.
4. Clear the EN bit, if not already cleared.
5. Set desired dead-band times with the
COGxDBR and COGxDBF registers and select
the source with the RDBS and FDBS bits of the
COGxCON1 register.
6. Set desired blanking times with the COGxBLKR
and COGxBLKF registers.
7. Set desired phase delay with the COGxPHR
and COGxPHF registers.
8. Select the desired shutdown sources with the
COGxASD1 register.
9. Setup the following controls in COGxASD0
auto-shutdown register:
• Select both output override controls to the
desired levels (this is necessary, even if not
using auto-shutdown because start-up will be
from a shutdown state).
• Set the ASE bit and clear the ARSEN bit.
10. Select the desired rising and falling event
sources with the COGxRIS0, COGxRIS1,
COGxFIS0, and COGxFIS1 registers.
11. Select the desired rising and falling event modes
with the COGxRSIM0, COGxRSIMI1,
COGxFSIM0, and COGxFSIM1 registers.
12. Configure the following controls in the
COGxCON1 register:
• Set the polarity for each output
• Select the desired dead-band timing sources
13. Configure the following controls in the
COGxCON0 register:
• Set the desired operating mode
• Select the desired clock source
14. If one of the steering modes is selected then
configure the following controls in the
COGxSTR register:
• Set the steering bits of the outputs to be
used.
• Set the desired static levels.
15. Set the EN bit.
16. Set the pin PPS controls to direct the COG
outputs to the desired pins.
17. If auto-restart is to be used, set the ARSEN bit
and the ASE will be cleared automatically.
Otherwise, clear the ASE bit to start the COG.
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27.15 Register Definitions: COG Control
Long bit name prefixes for the COG peripherals are
shown in Tab le 27-4. Refer to Section 1.1 “Register
and Bit naming conventions” for more information
TABLE 27-4:
Peripheral Bit Name Prefix
COG1 G1
COG2 G2
COG3 G3
COG4(1) G4
Note 1: PIC16(L)F1777/9 only.
REGISTER 27-1: COGxCON0: COG CONTROL REGISTER 0
R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
EN LD —CS<1:0> MD<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7 EN: COGx Enable bit
1 = Module is enabled
0 = Module is disabled
bit 6 LD: COGx Load Buffers bit
1 = Phase, blanking, and dead-band buffers to be loaded with register values on next input events
0 = Register to buffer transfer is complete
bit 5 Unimplemented: Read as ‘0’
bit 4-3 CS<1:0>: COGx Clock Selection bits
11 = Reserved. Do not use.
10 = COG_clock is HFINTOSC (stays active during Sleep)
01 = COG_clock is FOSC
00 = COG_clock is FOSC/4
bit 2-0 MD<2:0>: COGx Mode Selection bits
11x = Reserved. Do not use.
101 = COG outputs operate in Push-Pull mode
100 = COG outputs operate in Half-Bridge mode
011 = COG outputs operate in Reverse Full-Bridge mode
010 = COG outputs operate in Forward Full-Bridge mode
001 = COG outputs operate in synchronous steered PWM mode
000 = COG outputs operate in steered PWM mode
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REGISTER 27-2: COGxCON1: COG CONTROL REGISTER 1
R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
RDBS FDBS —— POLD POLC POLB POLA
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7 RDBS: COGx Rising Event Dead-band Timing Source Select bit
1 = Delay chain and COGxDBR are used for dead-band timing generation
0 = COGx_clock and COGxDBR are used for dead-band timing generation
bit 6 FDBS: COGx Falling Event Dead-band Timing Source select bit
1 = Delay chain and COGxDBF are used for dead-band timing generation
0 = COGx_clock and COGxDBF are used for dead-band timing generation
bit 5-4 Unimplemented: Read as ‘0’
bit 3 POLD: COGxD Output Polarity Control bit
1 = Active level of COGxD output is low
0 = Active level of COGxD output is high
bit 2 POLC: COGxC Output Polarity Control bit
1 = Active level of COGxC output is low
0 = Active level of COGxC output is high
bit 1 POLB: COGxB Output Polarity Control bit
1 = Active level of COGxB output is low
0 = Active level of COGxB output is high
bit 0 POLA: COGxA Output Polarity Control bit
1 = Active level of COGxA output is low
0 = Active level of COGxA output is high
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TABLE 27-5: RISING/FALLING EVENT INPUT SOURCES
REGISTER 27-3: COGxRIS0: COG RISING EVENT INPUT SELECTION REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
RIS7 RIS6 RIS5 RIS4 RIS3 RIS2 RIS1 RIS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-0 RIS<7:0>: Source Rising Event Input <n> Source Enable bits(1). See Tabl e 27-5.
1 = Source <n> output is enabled as a rising event input
0 = Source <n> output has no effect on the rising event
Note 1: Any combination of <n> bits can be selected.
REGISTER 27-4: COGxRIS1: COG RISING EVENT INPUT SELECTION REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
RIS15 RIS14 RIS13 RIS12 RIS11 RIS10 RIS9 RIS8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 15-8 RIS<15:8>: COGx Rising Event Input <n> Source Enable bits(1). See Table 27-5.
1 = Source <n> output is enabled as a rising event input
0 = Source <n> output has no effect on the rising event
Note 1: Any combination of <n> bits can be selected.
Bit <n> COG1 COG2 COG3(1) COG3(2) COG4(1)
15 LC4_out LC4_out LC4_out LC4_out LC4_out
14 LC3_out LC3_out LC3_out LC3_out LC3_out
13 LC2_out LC2_out LC2_out LC2_out LC2_out
12 LC1_out LC1_out LC1_out LC1_out LC1_out
11 MD1_out MD2_out MD3_out MD3_out MD4_out
10 PWM6_output PWM6_output PWM12_output Reserved PWM12_output
9 PWM5_output PWM5_output PWM11_output PWM11_output PWM11_output
8 PWM4_output PWM4_output PWM10_output Reserved PWM10_output
7 PWM3_output PWM3_output PWM9_output PWM9_output PWM9_output
6 CCP2_out CCP2_out CCP8_out CCP7_out CCP8_out
5 CCP1_out CCP1_out CCP7_out CCP1_out CCP7_out
4 sync_CM4_out sync_CM4_out sync_CM8_out sync_CM6_out sync_CM8_out
3 sync_CM3_out sync_CM3_out sync_CM7_out sync_CM5_out sync_CM7_out
2 sync_CM2_out sync_CM2_out sync_CM6_out sync_CM2_out sync_CM6_out
1 sync_CM1_out sync_CM1_out sync_CM5_out sync_CM1_out sync_CM5_out
0 Pin selected with
COG1PPS
Pin selected with
COG2PPS
Pin selected with
COG3PPS
Pin selected with
COG3PPS
Pin selected with
COG4PPS
Note 1: PIC16(L)F1777/9 only.
2: PIC16(L)F1778 only.
2015-2016 Microchip Technology Inc. DS40001819B-page 381
PIC16(L)F1777/8/9
REGISTER 27-5: COGxRSIM0: COG RISING EVENT SOU RCE INPUT MODE REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
RSIM7 RSIM6 RSIM5 RSIM4 RSIM3 RSIM2 RSIM1 RSIM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-0 RSIM<7:0>: Rising Event Input Source <n> Mode bits(1). See Table 27-5.
RIS<n> = 1:
1 = Source <n> output low-to-high transition will cause a rising event after rising event phase delay
0 = Source <n> output high level will cause an immediate rising event
RIS<n> = 0:
Source <n> output has no effect on rising event
Note 1: Any combination of <n> bits can be selected.
REGISTER 27-6: COGxRSIM1: COG RISING EVENT SOU RCE INPUT MODE REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
RSIM15 RSIM14 RSIM13 RSIM12 RSIM11 RSIM10 RSIM9 RSIM8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 15-8 RSIM<15:8>: Rising Event Input Source <n> Mode bits(1). See Table 27-5.
RIS<n> = 1:
1 = Source <n> output low-to-high transition will cause a rising event after rising event phase delay
0 = Source <n> output high level will cause an immediate rising event
RIS<n> = 0:
Source <n> output has no effect on rising event
Note 1: Any combination of <n> bits can be selected.
PIC16(L)F1777/8/9
DS40001819B-page 382 2015-2016 Microchip Technology Inc.
REGISTER 27-7: COGxFIS0: COG FALLING EVENT INPUT SELECTION REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
FIS7 FIS6 FIS5 FIS4 FIS3 FIS2 FIS1 FIS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-0 FIS<7:0>: Falling Event Input Source <n> Enable bits(1). See Table 27-5.
1 = Source <n> output is enabled as a falling event input
0 = Source <n> output has no effect on the falling event
Note 1: Any combination of <n> bits can be selected.
REGISTER 27-8: COGxFIS1: COG FALLING EVENT INPUT SELECTION REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
FIS15 FIS14 FIS13 FIS12 FIS11 FIS10 FIS9 FIS8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 15-8 FIS<15:8>: Falling Event Input Source <n> Enable bits(1). See Tab le 2 7- 5.
1 = Source <n> output is enabled as a falling event input
0 = Source <n> output has no effect on the falling event
Note 1: Any combination of <n> bits can be selected.
2015-2016 Microchip Technology Inc. DS40001819B-page 383
PIC16(L)F1777/8/9
REGISTER 27-9: COGxFSIM0: COG FALLING EVENT SOURCE INPUT MODE REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
FSIM7 FSIM6 FSIM5 FSIM4 FSIM3 FSIM2 FSIM1 FSIM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-0 FSIM<7:0>: Falling Event Input Source <n> Mode bits(1). See Table 27-5.
FIS<n> = 1:
1 = Source <n> output high-to-low transition will cause a falling event after falling event phase delay
0 = Source <n> output low level will cause an immediate falling event
FIS<n> = 0:
Source <n> output has no effect on falling event
Note 1: Any combination of <n> bits can be selected.
REGISTER 27-10: COGxFSIM1: COG FALLING EVENT SOURCE INPUT MODE REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
FSIM15 FSIM14 FSIM13 FSIM12 FSIM11 FSIM10 FSIM9 FSIM8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 15-8 FSIM<15:8>: Falling Event Input Source <n> Mode bits(1). See Table 2 7- 5.
FIS<n> = 1:
1 = Source <n> output high-to-low transition will cause a falling event after falling event phase delay
0 = Source <n> output low level will cause an immediate falling event
FIS<n> = 0:
Source <n> output has no effect on falling event
Note 1: Any combination of <n> bits can be selected.
PIC16(L)F1777/8/9
DS40001819B-page 384 2015-2016 Microchip Technology Inc.
REGISTER 27-11: COGxASD0: COG AUTO-SHUTDOWN CONTROL REGISTER 0
R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 U-0 U-0
ASE ARSEN ASDBD<1:0> ASDAC<1:0> — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7 ASE: Auto-Shutdown Event Status bit
1 = COG is in the shutdown state
0 = COG is either not in the shutdown state or will exit the shutdown state on the next rising event
bit 6 ARSEN: Auto-Restart Enable bit
1 = Auto-restart is enabled
0 = Auto-restart is disabled
bit 5-4 ASDBD<1:0>: COGxB and COGxD Auto-shutdown Override Level Select bits
11 =A logic ‘1’ is placed on COGxB and COGxD when shutdown is active
10 =A logic ‘0’ is placed on COGxB and COGxD when shutdown is active
01 = COGxB and COGxD are tri-stated when shutdown is active
00 = The inactive state of the pin, including polarity, is placed on COGxB and COGxD when shutdown
is active
bit 3-2 ASDAC<1:0>: COGxA and COGxC Auto-shutdown Override Level Select bits
11 =A logic ‘1’ is placed on COGxA and COGxC when shutdown is active
10 =A logic ‘0’ is placed on COGxA and COGxC when shutdown is active
01 = COGxA and COGxC are tri-stated when shutdown is active
00 = The inactive state of the pin, including polarity, is placed on COGxA and COGxC when shutdown
is active
bit 1-0 Unimplemented: Read as ‘0’
2015-2016 Microchip Technology Inc. DS40001819B-page 385
PIC16(L)F1777/8/9
TABLE 27-6: AUTO-SHUTDOWN SOURCES
REGISTER 27-12: COGxASD1: COG AUTO-SHUTDOWN CONTROL REGISTER 1
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
AS7E AS6E AS5E AS4E AS3E AS2E AS1E AS0E
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-0 AS<7:0>E: Auto-shutdown Source <n> Enable bits(1). See Tabl e 27-6.
1 = COGx is shutdown when source <n> output is low
0 = Source <n> has no effect on shutdown
Note 1: Any combination of <n> bits can be selected.
Bit <n > COG1 COG2 COG3(2) COG3(3) COG4(2)
7 TMR4_postscaled(1) TMR4_postscaled(1) TMR8_postscaled(1) TMR8_postscaled(1) TMR8_postscaled(1)
6 TMR2_postscaled(1) TMR2_postscaled(1) TMR6_postscaled(1) TMR6_postscaled(1) TMR6_postscaled(1)
5 LC2_out LC2_out LC4_out LC4_out LC4_out
4 sync_CM4_out sync_CM4_out sync_CM8_out sync_CM6_out sync_CM8_out
3 sync_CM3_out sync_CM3_out sync_CM7_out sync_CM5_out sync_CM7_out
2 sync_CM2_out sync_CM2_out sync_CM6_out sync_CM2_out sync_CM6_out
1 sync_CM1_out sync_CM1_out sync_CM5_out sync_CM1_out sync_CM5_out
0 Pin selected by
COG1PPS
Pin selected by
COG2PPS
Pin selected by
COG3PPS
Pin selected by
COG3PPS
Pin selected by
COG4PPS
Note 1: Shutdown when source is high.
2: PIC16(L)F1777/9 only.
3: PIC16(L)F1778 only.
PIC16(L)F1777/8/9
DS40001819B-page 386 2015-2016 Microchip Technology Inc.
REGISTER 27-13: COGxSTR: COG STEERING CONTROL REGISTER 1(1)
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
SDATD SDATC SDATB SDATA STRD STRC STRB STRA
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7 SDATD: COGxD Static Output Data bit
1 = COGxD static data is high
0 = COGxD static data is low
bit 6 SDATC: COGxC Static Output Data bit
1 = COGxC static data is high
0 = COGxC static data is low
bit 5 SDATB: COGxB Static Output Data bit
1 = COGxB static data is high
0 = COGxB static data is low
bit 4 SDATA: COGxA Static Output Data bit
1 = COGxA static data is high
0 = COGxA static data is low
bit 3 STRD: COGxD Steering Control bit
1 = COGxD output has the COGxD waveform with polarity control from POLD bit
0 = COGxD output is the static data level determined by the SDATD bit
bit 2 STRC: COGxC Steering Control bit
1 = COGxC output has the COGxC waveform with polarity control from POLC bit
0 = COGxC output is the static data level determined by the SDATC bit
bit 1 STRB: COGxB Steering Control bit
1 = COGxB output has the COGxB waveform with polarity control from POLB bit
0 = COGxB output is the static data level determined by the SDATB bit
bit 0 STRA: COGxA Steering Control bit
1 = COGxA output has the COGxA waveform with polarity control from POLA bit
0 = COGxA output is the static data level determined by the SDATA bit
Note 1: Steering is active only when the MD<1:0> bits of the COGxCON0 register = 00x. (See Register 27-1).
2015-2016 Microchip Technology Inc. DS40001819B-page 387
PIC16(L)F1777/8/9
REGISTER 27-14: COGxDBR: COG RISING EVENT DEAD-BAND COUNT REGISTER
U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
DBR<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 DBR<5:0>: Rising Event Dead-Band Count Value bits
RDBS = 1:
= Number of delay chain element periods to delay primary output after rising event
RDBS = 0:
= Number of COGx clock periods to delay primary output after rising event
REGISTER 27-15: COGxDBF: COG FALLING EVENT DEAD-BAND COUNT REGISTER
U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
DBF<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 DBF<5:0>: Falling Event Dead-Band Count Value bits
FDBS = 1:
= Number of delay chain element periods to delay complementary output after falling event input
FDBS = 0:
= Number of COGx clock periods to delay complementary output after falling event input
PIC16(L)F1777/8/9
DS40001819B-page 388 2015-2016 Microchip Technology Inc.
REGISTER 27-16: COGxBLKR: COG RISING EVENT BLANKING COUNT REGISTER
U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
BLKR<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 BLKR<5:0>: Rising Event Blanking Count Value bits
= Number of COGx clock periods to inhibit falling event inputs
REGISTER 27-17: COGxBLKF: COG FALLING EVENT BLANKING COUNT REGISTER
U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
BLKF<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 BLKF<5:0>: Falling Event Blanking Count Value bits
= Number of COGx clock periods to inhibit rising event inputs
2015-2016 Microchip Technology Inc. DS40001819B-page 389
PIC16(L)F1777/8/9
REGISTER 27-18: COGxPHR: COG RISING EVENT PHASE DELAY COUNT REGISTER
U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — PHR<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 PHR<5:0>: Rising Event Phase Delay Count Value bits
= Number of COGx clock periods to delay rising event
REGISTER 27-19: COGxPHF: COG FALLING EVENT PHASE DELAY COUNT REGISTER
U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — PHF<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 PHF<5:0>: Falling Event Phase Delay Count Value bits
= Number of COGx clock periods to delay falling event
PIC16(L)F1777/8/9
DS40001819B-page 390 2015-2016 Microchip Technology Inc.
TABLE 27-7: SUMMARY OF REGISTERS ASSOCIATED WITH COGx(1)
Name B it 7 Bit 6 Bit 5 B it 4 B it 3 B it 2 B it 1 B it 0 Register
on Page
ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177
ANSELB —— ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182
ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 187
COGxASD0 ASE ARSEN ASDBD<1:0> ASDAC<1:0> — — 384
COGxASD1 AS7E AS6E AS5E AS4E AS3E AS2E AS1E AS0E 385
COGxBLKR —— BLKR<5:0> 388
COGxBLKF —— BLKF<5:0> 388
COGxCON0 EN LD — CS<1:0> MD<2:0> 378
COGxCON1 RDBS FDBS —— POLD POLC POLB POLA 379
COGxDBR ——DBR<5:0>387
COGxDBF ——DBF<5:0>387
COGxFIS0 FIS7 FIS6 FIS5 FIS4 FIS3 FIS2 FIS1 FIS0 382
COGxFIS1 FIS15 FIS14 FIS13 FIS12 FIS11 FIS10 FIS9 FIS8 382
COGxFSIM0 FSIM7 FSIM6 FSIM5 FSIM4 FSIM3 FSIM2 FSIM1 FSIM0 383
COGxFSIM1 FSIM15 FSIM14 FSIM13 FSIM12 FSIM11 FSIM10 FSIM9 FSIM8 383
COGxPHR ——PHR<5:0>389
COGxPHF ——PHF<5:0>389
COGxPPS ——COG1PPS<5:0>205, 207
COGxRIS0 RIS7 RIS6 RIS5 RIS4 RIS3 RIS2 RIS1 RIS0 380
COGxRIS1 RIS15 RIS14 RIS13 RIS12 RIS11 RIS10 RIS9 RIS8 380
COGxRSIM0 RSIM7 RSIM6 RSIM5 RSIM4 RSIM3 RSIM2 RSIM1 RSIM0 381
COGxRSIM1 RSIM15 RSIM14 RSIM13 RSIM12 RSIM11 RSIM10 RSIM9 RSIM8 381
COGxSTR SDATD SDATC SDATB SDATA STRD STRC STRB STRA 386
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132
RxyPPS —— RxyPPS<5:0> 205
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by COG.
Note 1: COG4 is available on PIC16(L)F1777/9 only.
2015-2016 Microchip Technology Inc. DS40001819B-page 391
PIC16(L)F1777/8/9
28.0 CONFIGU RABLE LOGIC CELL
(CLC)
The Configurable Logic Cell (CLCx) provides program-
mable logic that operates outside the speed limitations
of software execution. The logic cell takes up to 32
input signals and, through the use of configurable
gates, reduces the 32 inputs to four logic lines that drive
one of eight selectable single-output logic functions.
Input sources are a combination of the following:
• I/O pins
• Internal clocks
• Peripherals
• Register bits
The output can be directed internally to peripherals and
to an output pin.
Refer to Figure 28-1 for a simplified diagram showing
signal flow through the CLCx.
Possible configurations include:
• Combinatorial Logic
-AND
-NAND
- AND-OR
- AND-OR-INVERT
-OR-XOR
-OR-XNOR
• Latches
-S-R
- Clocked D with Set and Reset
- Transparent D with Set and Reset
- Clocked J-K with Reset
FIGURE 28-1: CLCx SIMPLIFIED BLOCK DIAGRAM
Input Data Selection Gates(1)
Logic
Function
(2)
g2
g1
g3
g4
MODE<2:0>
q
EN
POL
det
Interrupt
det
Interrupt
set bit
CLCxIF
INTN
INTP
CLCx
to Peripherals
Q1
LCx_out
LCxOUT
MLCxOUT
DQ
PPS
LCx_in[0]
LCx_in[1]
LCx_in[2]
LCx_in[35]
LCx_in[36]
LCx_in[37]
.
.
.
Rev . 10 -000 025D
6/ 4/ 201 4
CLCxPPS
TRIS
Note 1: See Figure 28-2: Input Data Selection and Gating.
2: See Figure 28-3: Programmable Logic Functions.
See
Table 28-1.
PIC16(L)F1777/8/9
DS40001819B-page 392 2015-2016 Microchip Technology Inc.
28.1 CLCx Setup
Programming the CLCx module is performed by config-
uring the four stages in the logic signal flow. The four
stages are:
•Data selection
• Data gating
• Logic function selection
• Output polarity
Each stage is setup at run time by writing to the corre-
sponding CLCx Special Function Registers. This has
the added advantage of permitting logic reconfiguration
on-the-fly during program execution.
28.1.1 DATA SELECTION
There are 32 signals available as inputs to the configu-
rable logic. Four 32-input multiplexers are used to
select the inputs to pass on to the next stage.
Data selection is through four multiplexers as indicated
on the left side of Figure 28-2. Data inputs in the figure
are identified by a generic numbered input name.
Table 28-1 correlates the generic input name to the
actual signal for each CLC module. The column labeled
dy indicates the MUX selection code for the selected
data input. DxS is an abbreviation for the MUX select
input codes: D1S<4:0> through D4S<4:0>.
Data inputs are selected with the CLCxSEL0 through
CLCxSEL3 registers (Register 28-3 through
Register 28-6).
Note: Data selections are undefined at power-up.
TABLE 28-1: CLCx DAT A INPUT SELECTION
Data Input dy
DxS CLCx
LCx_in[54] 110110 MD1_OUT OR MD2_OUT OR MD3_OUT
LCx_in[53] 110101 FOSC
LCx_in[52] 110100 HFINTOSC
LCx_in[51] 110011 LFINTOSC
LCx_in[50] 110010 FRC (ADC RC clock)
LCx_in[49] 110001 IOCIF set
LCx_in[48] 110000 Timer8_postscaled
LCx_in[47] 101111 Timer6_postscaled
LCx_in[46] 101110 Timer4_postscaled
LCx_in[45] 101101 Timer2_postscaled
LCx_in[44] 101100 Timer5 overflow
LCx_in[43] 101011 Timer3 overflow
LCx_in[42] 101010 Timer1 overflow
LCx_in[41] 101001 Timer0 overflow
LCx_in[40] 101000 EUSART RX
LCx_in[39] 100111 EUSART TX
LCx_in[38] 100110 ZCD1_output
LCx_in[37] 100101 MSSP1 SDO/SDA
LCx_in[36] 100100 MSSP1 SCL/SCK
LCx_in[35] 100011 PWM12_out(1)
LCx_in[34] 100010 PWM11_out
LCx_in[33] 100001 PWM6_out
LCx_in[32] 100000 PWM5_out
LCx_in[31] 011111 PWM10_out(1)
LCx_in[30] 011110 PWM9_out
LCx_in[29] 011101 PWM4_out
LCx_in[28] 011100 PWM3_out
LCx_in[27] 011011 CCP8_out(1)
LCx_in[26] 011010 CCP7_out
LCx_in[25] 011001 CCP2_out
LCx_in[24] 011000 CCP1_out
LCx_in[23] 010111 COG4B(1)
LCx_in[22] 010110 COG4A(1)
LCx_in[21] 010101 COG3B
LCx_in[20] 010100 COG3A
LCx_in[19] 010011 COG2B
LCx_in[18] 010010 COG2A
LCx_in[17] 010001 COG1B
LCx_in[16] 010000 COG1A
LCx_in[15] 001111 sync_C8OUT(1)
LCx_in[14] 001110 sync_C7OUT(1)
LCx_in[13] 001101 sync_C6OUT
LCx_in[12] 001100 sync_C5OUT
LCx_in[11] 001011 sync_C4OUT
LCx_in[10] 001010 sync_C3OUT
LCx_in[9] 001001 sync_C2OUT
LCx_in[8] 001000 sync_C1OUT
LCx_in[7] 000111 LC4_out from the CLC4
LCx_in[6] 000110 LC3_out from the CLC3
LCx_in[5] 000101 LC2_out from the CLC2
LCx_in[4] 000100 LC1_out from the CLC1
LCx_in[3] 000011 CLCIN3 pin input selected in CLCIN3PPS
register
LCx_in[2] 000010 CLCIN2 pin input selected in CLCIN2PPS
register
LCx_in[1] 000001 CLCIN1 pin input selected in CLCIN1PPS
register
LCx_in[0] 000000 CLCIN0 pin input selected in CLCIN0PPS
register
Note 1: PIC16(L)F1777/9 only.
TABLE 28-1: CLCx DAT A INPUT SELECTION
Data Input dy
DxS CLCx
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28.1.2 DATA GATING
Outputs from the input multiplexers are directed to the
desired logic function input through the data gating
stage. Each data gate can direct any combination of the
four selected inputs.
The gate stage is more than just signal direction. The
gate can be configured to direct each input signal as
inverted or non-inverted data. Directed signals are
ANDed together in each gate. The output of each gate
can be inverted before going on to the logic function
stage.
The gating is in essence a 1-to-4 input
AND/NAND/OR/NOR gate. When every input is
inverted and the output is inverted, the gate is an OR of
all enabled data inputs. When the inputs and output are
not inverted, the gate is an AND or all enabled inputs.
Table 28-2 summarizes the basic logic that can be
obtained in gate 1 by using the gate logic select bits.
The table shows the logic of four input variables, but
each gate can be configured to use less than four. If
no inputs are selected, the output will be zero or one,
depending on the gate output polarity bit.
It is possible (but not recommended) to select both the
true and negated values of an input. When this is done,
the gate output is zero, regardless of the other inputs,
but may emit logic glitches (transient-induced pulses).
If the output of the channel must be zero or one, the
recommended method is to set all gate bits to zero and
use the gate polarity bit to set the desired level.
Data gating is configured with the logic gate select
registers as follows:
• Gate 1: CLCxGLS0 (Register 28-7)
• Gate 2: CLCxGLS1 (Register 28-8)
• Gate 3: CLCxGLS2 (Register 28-9)
• Gate 4: CLCxGLS3 (Register 28-10)
Register number suffixes are different than the gate
numbers because other variations of this module have
multiple gate selections in the same register.
Data gating is indicated in the right side of Figure 28-2.
Only one gate is shown in detail. The remaining three
gates are configured identically with the exception that
the data enables correspond to the enables for that
gate.
28.1.3 LOGIC FUNCTION
There are eight available logic functions including:
• AND-OR
•OR-XOR
•AND
• S-R Latch
• D Flip-Flop with Set and Reset
• D Flip-Flop with Reset
• J-K Flip-Flop with Reset
• Transparent Latch with Set and Reset
Logic functions are shown in Figure 28-3. Each logic
function has four inputs and one output. The four inputs
are the four data gate outputs of the previous stage.
The output is fed to the inversion stage and from there
to other peripherals, an output pin, and back to the
CLCx itself.
28.1.4 OUTPUT POLARITY
The last stage in the Configurable Logic Cell is the
output polarity. Setting the POL bit of the CLCxCON
register inverts the output signal from the logic stage.
Changing the polarity while the interrupts are enabled
will cause an interrupt for the resulting output transition.
Note: Data gating is undefined at power-up.
TABLE 28-2: DATA GATING LOGIC
CLCxGLS0 G1POL Gate Logic
0x55 1AND
0x55 0NAND
0xAA 1NOR
0xAA 0OR
0x00 0Logic 0
0x00 1Logic 1
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28.1.5 CLCx SETUP STEPS
The following steps should be followed when setting up
the CLCx:
• Disable CLCx by clearing the EN bit.
• Select desired inputs using CLCxSEL0 through
CLCxSEL3 registers (See Table 28-1).
• Clear any associated ANSEL bits.
• Set all TRIS bits associated with inputs.
• Clear all TRIS bits associated with outputs.
• Enable the chosen inputs through the four gates
using CLCxGLS0, CLCxGLS1, CLCxGLS2, and
CLCxGLS3 registers.
• Select the gate output polarities with the POLy
bits of the CLCxPOL register.
• Select the desired logic function with the
MODE<2:0> bits of the CLCxCON register.
• Select the desired polarity of the logic output with
the POL bit of the CLCxPOL register. (This step
may be combined with the previous gate output
polarity step).
• If driving a device pin, set the desired pin PPS
control register and also clear the TRIS bit
corresponding to that output.
• If interrupts are desired, configure the following
bits:
- Set the INTP bit in the CLCxCON register for
rising event.
- Set the INTN bit in the CLCxCON register for
falling event.
- Set the CLCxIE bit of the associated PIE
registers.
- Set the GIE and PEIE bits of the INTCON
register.
• Enable the CLCx by setting the EN bit of the
CLCxCON register.
28.2 CLCx Interrupts
An interrupt will be generated upon a change in the
output value of the CLCx when the appropriate interrupt
enables are set. A rising edge detector and a falling
edge detector are present in each CLC for this purpose.
The CLCxIF bit of the associated PIR registers will be
set when either edge detector is triggered and its asso-
ciated enable bit is set. The INTP enables rising edge
interrupts and the INTN bit enables falling edge inter-
rupts. Both are located in the CLCxCON register.
To fully enable the interrupt, set the following bits:
• EN bit of the CLCxCON register
• CLCxIE bit of the associated PIE registers
• INTP bit of the CLCxCON register (for a rising
edge detection)
• INTN bit of the CLCxCON register (for a falling
edge detection)
• PEIE and GIE bits of the INTCON register
The CLCxIF bit of the associated PIR registers, must
be cleared in software as part of the interrupt service. If
another edge is detected while this flag is being
cleared, the flag will still be set at the end of the
sequence.
28.3 Output Mirror Copies
Mirror copies of all LCxCON output bits are contained
in the CLCxDATA register. Reading this register reads
the outputs of all CLCs simultaneously. This prevents
any reading skew introduced by testing or reading the
CLCxOUT bits in the individual CLCxCON registers.
28.4 Effects of a Reset
The CLCxCON register is cleared to zero as the result
of a Reset. All other selection and gating values remain
unchanged.
28.5 Operation During Sleep
The CLC module operates independently from the
system clock and will continue to run during Sleep,
provided that the input sources selected remain active.
The HFINTOSC remains active during Sleep when the
CLC module is enabled and the HFINTOSC is
selected as an input source, regardless of the system
clock source selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and as a CLC input
source, when the CLC is enabled, the CPU will go idle
during Sleep, but the CLC will continue to operate and
the HFINTOSC will remain active.
This will have a direct effect on the Sleep mode current.
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FIGURE 28-2: INPUT DATA SELECTION AND GATING
g1
G1POL
Data GATE 1
D1G1T
g2
g3
g4
Data GATE 2
Data GATE 3
Data GATE 4
D1G1N
D2G1T
D2G1N
D3G1T
D3G1N
D4G1T
D4G1N
D1S<4:0>
D2S<4:0>
D3S<4:0>
D4S<4:0>
LCx_in[0]
LCx_in[37]
Data Selection
Note: All controls are undefined at power-up.
d1T
d1N
d2T
d2N
d3T
d3N
d4T
d4N
(Same as Data GATE 1)
(Same as Data GATE 1)
(Same as Data GATE 1)
LCx_in[0]
LCx_in[37]
LCx_in[0]
LCx_in[37]
LCx_in[0]
LCx_in[37]
See Table 28-1.
See Table 28-1.
See Tabl e 28-1 .
See Table 28-1.
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FIGURE 28-3: PROGRAM MABLE LOGIC FUNCTIONS
g1
g2
g3
g4
q
g1
g2
g3
g4
q
g1
g2
g3
g4
q
S
R
Q
g1
g2
g3
g4
q
DQ
g1
g2
g3
g4
q
S
R
JQ
g2
g3
g4
q
R
g1
K
DQ
g1
g2
g3
g4
q
S
R
DQ
g1
g3
q
R
g4
g2
MODE<2:0>= 000
MODE<2:0>= 010
MODE<2:0>= 001
MODE<2:0>= 011
MODE<2:0>= 100
MODE<2:0>= 110
MODE<2:0>= 101
MODE<2:0>= 111
LE
AND – OR OR – XOR
4-Input AND S-R La tch
1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R
1-Input Transparent Latch with S and R
J-K Flip-Flop with R
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28.6 Register Definitions: CLC Control
Long bit name prefixes for the CLC peripherals are
shown in Table 28-3. Refer to Section 1.1 “Register
and Bit naming conventions” for more information
TABLE 28-3:
Peripheral Bit Name Prefix
CLC1 LC1
CLC2 LC2
CLC3 LC3
CLC4 LC4
REGISTER 28-1: CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER
R/W-0/0 U-0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
EN — OUT INTP INTN MODE<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 EN: Configurable Logic Cell Enable bit
1 = Configurable logic cell is enabled and mixing input signals
0 = Configurable logic cell is disabled and has logic zero output
bit 6 Unimplemented: Read as ‘0’
bit 5 OUT: Configurable Logic Cell Data Output bit
Read-only: logic cell output data, after POL; sampled from lcx_out wire.
bit 4 INTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit
1 = CLCxIF will be set when a rising edge occurs on lcx_out
0 = CLCxIF will not be set
bit 3 INTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit
1 = CLCxIF will be set when a falling edge occurs on lcx_out
0 = CLCxIF will not be set
bit 2-0 MODE<2:0>: Configurable Logic Cell Functional Mode bits
111 = Cell is 1-input transparent latch with S and R
110 = Cell is J-K flip-flop with R
101 = Cell is 2-input D flip-flop with R
100 = Cell is 1-input D flip-flop with S and R
011 = Cell is S-R latch
010 = Cell is 4-input AND
001 = Cell is OR-XOR
000 = Cell is AND-OR
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REGISTER 28-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER
R/W-0/0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u
POL — — — G4POL G3POL G2POL G1POL
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 POL: LCOUT Polarity Control bit
1 = The output of the logic cell is inverted
0 = The output of the logic cell is not inverted
bit 6-4 Unimplemented: Read as ‘0’
bit 3 G4POL: Gate 4 Output Polarity Control bit
1 = The output of gate 4 is inverted when applied to the logic cell
0 = The output of gate 4 is not inverted
bit 2 G3POL: Gate 3 Output Polarity Control bit
1 = The output of gate 3 is inverted when applied to the logic cell
0 = The output of gate 3 is not inverted
bit 1 G2POL: Gate 2 Output Polarity Control bit
1 = The output of gate 2 is inverted when applied to the logic cell
0 = The output of gate 2 is not inverted
bit 0 G1POL: Gate 1 Output Polarity Control bit
1 = The output of gate 1 is inverted when applied to the logic cell
0 = The output of gate 1 is not inverted
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REGISTER 28-3: CLCxSEL0: GENERIC CLCx DATA 1 SELECT REGISTER
U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
——D1S<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 D1S<5:0>: CLCx Data1 Input Selection bits
See Table 28-1.
REGISTER 28-4: CLCxSEL1: GENERIC CLCx DATA 2 SELECT REGISTER
U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
——D2S<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 D2S<5:0>: CLCx Data 2 Input Selection bits
See Table 28-1.
REGISTER 28-5: CLCxSEL2: GENERIC CLCx DATA 3 SELECT REGISTER
U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
——D3S<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 D3S<5:0>: CLCx Data 3 Input Selection bits
See Table 28-1.
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REGISTER 28-6: CLCxSEL3: GENERIC CLCx DATA 4 SELECT REGISTER
U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
——D4S<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 D4S<5:0>: CLCx Data 4 Input Selection bits
See Table 28-1.
REGISTER 28-7: CLCxGLS0: GATE 1 LOGIC SELECT REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 G1D4T: Gate 1 Data 4 True (non-inverted) bit
1 = d4T is gated into g1
0 = d4T is not gated into g1
bit 6 G1D4N: Gate 1 Data 4 Negated (inverted) bit
1 = d4N is gated into g1
0 = d4N is not gated into g1
bit 5 G1D3T: Gate 1 Data 3 True (non-inverted) bit
1 = d3T is gated into g1
0 = d3T is not gated into g1
bit 4 G1D3N: Gate 1 Data 3 Negated (inverted) bit
1 = d3N is gated into g1
0 = d3N is not gated into g1
bit 3 G1D2T: Gate 1 Data 2 True (non-inverted) bit
1 = d2T is gated into g1
0 = d2T is not gated into g1
bit 2 G1D2N: Gate 1 Data 2 Negated (inverted) bit
1 = d2N is gated into g1
0 = d2N is not gated into g1
bit 1 G1D1T: Gate 1 Data 1 True (non-inverted) bit
1 = d1T is gated into g1
0 = d1T is not gated into g1
bit 0 G1D1N: Gate 1 Data 1 Negated (inverted) bit
1 = d1N is gated into g1
0 = d1N is not gated into g1
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REGISTER 28-8: CLCxGLS1: GATE 2 LOGIC SELECT REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 G2D4T: Gate 2 Data 4 True (non-inverted) bit
1 = d4T is gated into g2
0 = d4T is not gated into g2
bit 6 G2D4N: Gate 2 Data 4 Negated (inverted) bit
1 = d4N is gated into g2
0 = d4N is not gated into g2
bit 5 G2D3T: Gate 2 Data 3 True (non-inverted) bit
1 = d3T is gated into g2
0 = d3T is not gated into g2
bit 4 G2D3N: Gate 2 Data 3 Negated (inverted) bit
1 = d3N is gated into g2
0 = d3N is not gated into g2
bit 3 G2D2T: Gate 2 Data 2 True (non-inverted) bit
1 = d2T is gated into g2
0 = d2T is not gated into g2
bit 2 G2D2N: Gate 2 Data 2 Negated (inverted) bit
1 = d2N is gated into g2
0 = d2N is not gated into g2
bit 1 G2D1T: Gate 2 Data 1 True (non-inverted) bit
1 = d1T is gated into g2
0 = d1T is not gated into g2
bit 0 G2D1N: Gate 2 Data 1 Negated (inverted) bit
1 = d1N is gated into g2
0 = d1N is not gated into g2
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REGISTER 28-9: CLCxGLS2: GATE 3 LOGIC SELECT REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 G3D4T: Gate 3 Data 4 True (non-inverted) bit
1 = d4T is gated into g3
0 = d4T is not gated into g3
bit 6 G3D4N: Gate 3 Data 4 Negated (inverted) bit
1 = d4N is gated into g3
0 = d4N is not gated into g3
bit 5 G3D3T: Gate 3 Data 3 True (non-inverted) bit
1 = d3T is gated into g3
0 = d3T is not gated into g3
bit 4 G3D3N: Gate 3 Data 3 Negated (inverted) bit
1 = d3N is gated into g3
0 = d3N is not gated into g3
bit 3 G3D2T: Gate 3 Data 2 True (non-inverted) bit
1 = d2T is gated into g3
0 = d2T is not gated into g3
bit 2 G3D2N: Gate 3 Data 2 Negated (inverted) bit
1 = d2N is gated into g3
0 = d2N is not gated into g3
bit 1 G3D1T: Gate 3 Data 1 True (non-inverted) bit
1 = d1T is gated into g3
0 = d1T is not gated into g3
bit 0 G3D1N: Gate 3 Data 1 Negated (inverted) bit
1 = d1N is gated into g3
0 = d1N is not gated into g3
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REGISTER 28-10: CLCxGLS3: GATE 4 LOGIC SELECT REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 G4D4T: Gate 4 Data 4 True (non-inverted) bit
1 = d4T is gated into g4
0 = d4T is not gated into g4
bit 6 G4D4N: Gate 4 Data 4 Negated (inverted) bit
1 = d4N is gated into g4
0 = d4N is not gated into g4
bit 5 G4D3T: Gate 4 Data 3 True (non-inverted) bit
1 = d3T is gated into g4
0 = d3T is not gated into g4
bit 4 G4D3N: Gate 4 Data 3 Negated (inverted) bit
1 = d3N is gated into g4
0 = d3N is not gated into g4
bit 3 G4D2T: Gate 4 Data 2 True (non-inverted) bit
1 = d2T is gated into g4
0 = d2T is not gated into g4
bit 2 G4D2N: Gate 4 Data 2 Negated (inverted) bit
1 = d2N is gated into g4
0 = d2N is not gated into g4
bit 1 G4D1T: Gate 4 Data 1 True (non-inverted) bit
1 = d1T is gated into g4
0 = d1T is not gated into g4
bit 0 G4D1N: Gate 4 Data 1 Negated (inverted) bit
1 = d1N is gated into g4
0 = d1N is not gated into g4
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REGISTER 28-11: CLCDATA: CLC DATA OUTPUT
U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0
— — — — MLC4OUT MLC3OUT MLC2OUT MLC1OUT
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 Unimplemented: Read as ‘0’
bit 3 MLC4OUT: Mirror copy of LC4OUT bit
bit 2 MLC3OUT: Mirror copy of LC3OUT bit
bit 1 MLC2OUT: Mirror copy of LC2OUT bit
bit 0 MLC1OUT: Mirror copy of LC1OUT bit
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TABLE 28-4: SUMMARY OF REGISTERS ASSOCIATED WITH CLCx
Name Bit7 Bit6 Bit5 Bit4 BIt3 Bit2 Bit1 Bit0 Register
on Page
ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177
ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182
ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 187
CLCxCON EN — OUT INTP INTN MODE<2:0> 397
CLCDATA — — — — MLC4OUT MLC3OUT MLC2OUT MLC1OUT 404
CLCxGLS0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N 400
CLCxGLS1 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N 401
CLCxGLS2 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 402
CLCxGLS3 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N 403
CLCxPOL POL — — — G4POL G3POL G2POL G1POL 398
CLCxSEL0 ——D1S<5:0>
399
CLCxSEL1 ——D2S<5:0>
399
CLCxSEL2 ——D3S<5:0>
399
CLCxSEL3 ——D4S<5:0>
400
CLCINxPPS —— CLCINxPPS<5:0> 205, 207
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132
PIE3 — — COG2IE ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE 135
PIR3 — — COG2IF ZCDIF CLC4IF CLC3IF CLC2IF CLC1IF 141
RxyPPS — — RxyPPS<5:0> 205
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186
Legend: — = unimplemented read as ‘0’. Shaded cells are not used for CLC module.
PIC16(L)F1777/8/9
DS40001819B-page 406 2015-2016 Microchip Technology Inc.
29.0 OPERATIONAL AMPLIFIER
(OPA) MODULES
The Operational Amplifier (OPA) is a standard three-
terminal device requiring external feedback to operate.
The OPA module has the following features:
• External connections to I/O ports
• Low leakage inputs
• Factory Calibrated Input Offset Voltage
• Unity gain control
• Programmable positive and negative source
selections
• Override controls
- Forced tri-state output
- Forced unity gain
FIGURE 29-1: OPAx MO DULE BLOCK DIAGRAM
TABLE 29-1: AVAILABLE OP AMP
MODULES
Device OPA1 OP2 OPA3 OPA4
PIC16(L)F1778 ●●●
PIC16(L)F1777/9 ●●●●
OPA
EN
PCH<1:0>
OPAXOUT
OPAxIN0+
0
1
UG
NCH<1:0>
OPAxIN1+
OPAxIN0-
OPAxIN1-
OPAx_out
ORS<1:0>
ORM1
ORM0
Internal override sources
See Register 29-2.
Internal analog sources
See Register 29-4.
Internal analog sources
See Register 29-3.
ORPOL
2015-2016 Microchip Technology Inc. DS40001819B-page 407
PIC16(L)F1777/8/9
29.1 OPA Module Performance
Common AC and DC performance specifications for
the OPA module:
• Common-Mode Voltage Range
• Leakage Current
• Input Offset Voltage
• Open-Loop Gain
• Gain Bandwidth Product
Common-mode voltage range is the specified volt-
age range for the OPA+ and OPA- inputs, for which the
OPA module will perform to within its specifications.
The OPA module is designed to operate with input volt-
ages between VSS and VDD. Behavior for common-
mode voltages greater than VDD, or below VSS, are not
guaranteed.
Leakage current is a measure of the small source or
sink currents on the OPA+ and OPA- inputs. To
minimize the effect of leakage currents, the effective
impedances connected to the OPA+ and OPA- inputs
should be kept as small as possible and equal.
Input offset voltage is a measure of the voltage
difference between the OPA+ and OPA- inputs in a
closed loop circuit with the OPA in its linear region. The
offset voltage will appear as a DC offset in the output
equal to the input offset voltage, multiplied by the gain
of the circuit. The input offset voltage is also affected by
the common-mode voltage. The OPA is factory
calibrated to minimize the input offset voltage of the
module.
Open-loop gain is the ratio of the output voltage to the
differential input voltage, (OPA+) - (OPA-). The gain is
greatest at DC and falls off with frequency.
Gain Bandwidth Product or GBWP is the frequency
at which the open-loop gain falls off to 0 dB.
29.2 OPA Module Control
The OPA module is enabled by setting the OPAxEN bit
of the OPAxCON register (Register 29-1). When
enabled, the OPA forces the output driver of the
OPAxOUT pin into tri-state to prevent contention
between the driver and the OPA output.
29.2.1 UNITY GAIN MODE
The OPAxUG bit of the OPAxCON register
(Register 29-1) selects the Unity Gain mode. When
unity gain is selected, the OPA output is connected to
the inverting input and the OPAxIN pin is relinquished,
releasing the pin for general purpose input and output.
29.2.2 PROGRAMMABLE SOURCE
SELECTIONS
The inverting and non-inverting sources are selected
with the OPAxNCHS (Register 29-3) and OPAxPCHS
(Register 29-4) registers, respectively. Sources
include:
• Internal DACs
• Device pins
• Internal slope compensation ramp generator
• Other op amps in the device
29.3 Override Control
29.3.1 OVERRIDE MODE
The op amp operation can be overridden in two ways:
• Forced tri-state output
• Force unity gain
The Override mode is selected with the ORM<1:0> bits
of the OPxCON register (Register 29-1). The override
is in effect when the mode is selected and the override
source is true.
29.3.2 OVERRIDE SOURCES
The override source is selected with the OPAxORS
register (Register 29-2). Sources are from internal
peripherals including:
• CCP outputs
• PWM outputs
• Comparator outputs
• Zero-cross detect output
• Configurable Logic Cell outputs
• COG outputs
29.3.3 OVERRIDE SOURCE POLARITY
The override source polarity can be inverted so that the
override will occur on either the high or low level of the
selected source. Override polarity is controlled by the
ORPOL bit of the OPAxCON register (Register 29-1).
29.4 Effects of Reset
A device Reset forces all registers to their Reset state.
This disables the OPA module.
29.5 Effects of Sleep
The operational amplifier continues to operate when
the device is put in Sleep mode.
Note: When the OPA module is enabled, the
OPAxOUT pin is driven by the op amp
output, not by the PORT digital driver.
Refer to Table 36-17: Operational Amplifier
(OPA) for the op amp output drive
capability.
PIC16(L)F1777/8/9
DS40001819B-page 408 2015-2016 Microchip Technology Inc.
29.6 Register Definitions: Op Amp Control
Long bit name prefixes for the op amp peripherals are
shown in Tab le 29-2. Refer to Section 1.1 “Register
and Bit naming conventions” for more information
TABLE 29-2:
Peripheral Bit Name Prefix
OPA1 OPA1
OPA2 OPA2
OPA3 OPA3
OPA4(1) OPA4
Note 1: PIC16(L)F1777/9 only.
REGISTER 29-1: OPAxCON: OPE RATIONAL AMPLIFIER (OPAx) CONTROL REGISTER
R/W-0/0 U-0 U-0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
EN — — UG —ORPOL ORM<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7 EN: Op Amp Enable bit
1 = Op amp is enabled
0 = Op amp is disabled and consumes no active power
bit 6-5 Unimplemented: Read as ‘0’
bit 4 UG: Op Amp Unity Gain Select bit
1 = OPA output is connected to inverting input. OPAxIN- pin is available for general purpose I/O.
0 = Inverting input is connected to the OPAxIN- pin
bit 3 Unimplemented: Read as ‘0’
bit 2 ORPOL: Op Amp Override Source Polarity bit
1 = Override source polarity is inverted. Override occurs when source is high.
0 = Override source polarity is not inverted. Override occurs when source is low.
bit 1-0 ORM<1:0>: Op Amp Override Mode Selection bits
11 = Reserved. Do not use.
10 = Op amp is forced to unity gain when override source is true.
01 = Op amp output is tri-stated when override source is true.
00 = Output override function is disabled.
2015-2016 Microchip Technology Inc. DS40001819B-page 409
PIC16(L)F1777/8/9
REGISTER 29-2: OPAxORS: OP AMP OVERRIDE SOURCE SELECTION REGISTER
U-0 U-0 U-0 R/W-0/0 R/W-0/x R/W-0/x R/W-0/0 R/W-0/x
— — — ORS<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 ORS<4:0>: Op Amp Output Override Source Selection bits
See Table 29-3: Override Sources
TABLE 29-3: OVERRIDE SOURCES
ORS<4:0> OPA1 OPA2 OPA3 OPA4(1)
11111 COG2D COG2D COG4D(1) COG4D
11110 COG2C COG2C COG4C(1) COG4C
11101 COG2B COG2B COG4B(1) COG4B
11100 COG2A COG2A COG4A(1) COG4A
11011 COG1D COG1D COG3D COG3D
11010 COG1C COG1C COG3C COG3C
11001 COG1B COG1B COG3B COG3B
11000 COG1A COG1A COG3A COG3A
10111 LC4_out LC4_out LC4_out LC4_out
10110 LC3_out LC3_out LC3_out LC3_out
10101 LC2_out LC2_out LC2_out LC2_out
10100 LC1_out LC1_out LC1_out LC1_out
10011 sync_C8OUT(1) sync_C8OUT(1) sync_C8OUT(1) sync_C8OUT
10010 sync_C7OUT(1) sync_C7OUT(1) sync_C7OUT(1) sync_C7OUT
10001 sync_C6OUT sync_C6OUT sync_C6OUT sync_C6OUT
10000 sync_C5OUT sync_C5OUT sync_C5OUT sync_C5OUT
01111 sync_C4OUT sync_C4OUT sync_C4OUT sync_C4OUT
01110 sync_C3OUT sync_C3OUT sync_C3OUT sync_C3OUT
01101 sync_C2OUT sync_C2OUT sync_C2OUT sync_C2OUT
01100 sync_C1OUT sync_C1OUT sync_C1OUT sync_C1OUT
01011 PWM12_out(1) PWM12_out(1) PWM12_out(1) PWM12_out
01010 PWM11_out PWM11_out PWM11_out PWM11_out
01001 PWM6_out PWM6_out PWM6_out PWM6_out
01000 PWM5_out PWM5_out PWM5_out PWM5_out
00111 PWM10_out(1) PWM10_out(1) PWM10_out(1) PWM10_out
00110 PWM9_out PWM9_out PWM9_out PWM9_out
00101 PWM4_out PWM4_out PWM4_out PWM4_out
00100 PWM3_out PWM3_out PWM3_out PWM3_out
00011 CCP8_out(1) CCP8_out(1) CCP8_out(1) CCP8_out
00010 CCP7_out CCP7_out CCP7_out CCP7_out
00001 CCP2_out CCP2_out CCP2_out CCP2_out
00000 CCP1_out CCP1_out CCP1_out CCP1_out
Note 1: PIC16(L)F1777/9 only.
PIC16(L)F1777/8/9
DS40001819B-page 410 2015-2016 Microchip Technology Inc.
REGISTER 29-3: OPAxNCHS: OP AMP NEGATIVE CHANNEL SOURCE SELECT REGISTER
U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — NCH<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 NCH<3:0>: Op Amp Inverting Input Channel Selection bits
See Table 29-4: Inverting Input Sources
TABLE 29-4: INVERTING INPUT SOURCES
NCH<3:0> OPA1 OPA2 OPA3 OPA4(1)
1111 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use
1110 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use
1101 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use
1100 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use
1011 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use
1010 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use
1001 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use
1000 PRG2_out PRG2_out PRG4_out(1) PRG4_out
0111 PRG1_out PRG1_out PRG3_out PRG3_out
0110 FVR_Buffer1 FVR_Buffer1 FVR_Buffer2 FVR_Buffer2
0101 DAC4_out DAC4_out DAC8_out(1) DAC8_out
0100 DAC3_out DAC3_out DAC7_out DAC7_out
0011 DAC2_out DAC2_out DAC6_out(1) DAC6_out
0010 DAC1_out DAC1_out DAC5_out DAC5_out
0001 OPA1IN1- OPA2IN1- OPA3IN1-(1) OPA4IN1-
0000 OPA1IN0- OPA2IN0- OPA3IN0- OPA3IN0-
Note 1: PIC16(L)F1777/9 only.
2015-2016 Microchip Technology Inc. DS40001819B-page 411
PIC16(L)F1777/8/9
REGISTER 29-4: OPAxPCHS: OP AMP POSITIVE CHANNEL SOURCE SELECT REGISTER
U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — PCH<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 PCH<3:0>: Op Amp Non-Inverting Input Channel Selection bits
See Table 29-5: Non-Inverting Input Sources
TABLE 29-5: NON-INVERTING INPUT SOURCES
NCH<3:0> OPA1 OPA2 OPA3 OPA4(1)
1111 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use
1110 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use
1101 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use
1100 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use
1011 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use
1010 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use
1001 Reserved. Do not use Reserved. Do not use Reserved. Do not use Reserved. Do not use
1000 PRG2_out PRG2_out PRG4_out(1) PRG4_out
0111 PRG1_out PRG1_out PRG3_out PRG3_out
0110 FVR_Buffer1 FVR_Buffer1 FVR_Buffer2 FVR_Buffer2
0101 DAC4_out DAC4_out DAC8_out(1) DAC8_out
0100 DAC3_out DAC3_out DAC7_out DAC7_out
0011 DAC2_out DAC2_out DAC6_out(1) DAC6_out
0010 DAC1_out DAC1_out DAC5_out DAC5_out
0001 OPA1IN1+ OPA2IN1+ OPA3IN1+(1) OPA4IN1+
0000 OPA1IN0+ OPA2IN0+ OPA3IN0+ OPA4IN0+
Note 1: PIC16(L)F1777/9 only.
PIC16(L)F1777/8/9
DS40001819B-page 412 2015-2016 Microchip Technology Inc.
TABLE 29-6: SUMMARY OF REGISTERS ASSOCIATED WITH OP AMPS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ANSELB --- --- ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182
ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 187
DAC1CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 249
DAC2CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 249
DAC5CON0 EN FM OE1 OE2 PSS<1:0> NSS<1:0> 249
DAC3CON0 EN — OE1 OE2 PSS<1:0> NSS<1:0> 244
DAC4CON0 EN — OE1 OE2 PSS<1:0> NSS<1:0> 244
DAC7CON0 EN — OE1 OE2 PSS<1:0> NSS<1:0> 244
DAC3REF --- --- --- REF<4:0> 245
DAC4REF --- --- --- REF<4:0> 245
DAC7REF --- --- --- REF<4:0> 245
DAC1REFH REF<9:x> (x Depends on FM bit) 250
DAC2REFH REF<9:x> (x Depends on FM bit) 250
DAC5REFH REF<9:x> (x Depends on FM bit) 250
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 223
OPAxCON EN ——UG — ORPOL ORM<1:0> 408
OPAxNCHS — — — — NCH<3:0> 410
OPAxPCHS — — — — PCH<3:0> 411
OPAxORS — — —ORS<4:0>409
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by op amps.
2015-2016 Microchip Technology Inc. DS40001819B-page 413
PIC16(L)F1777/8/9
30.0 PROGRAMMABLE RAMP
GENERATOR (PRG) MODULE
The Programmable Ramp Generator (PRG) module is
designed to provide rising and falling linear ramps. Typical
applications include slope compensation for fixed fre-
quency, continuous current, and Current mode switched
power supplies. Slope compensation is a necessary fea-
ture of these power supplies because it prevents fre-
quency instabilities at duty cycles greater than 50%.
The PRG has the following features:
• Linear positive and negative voltage ramp outputs
• Programmable current source/sink
• Internal and external reference voltage selection
• Internal and external timing source selection
A simplified block diagram of the PRG is shown in
Figure 30-1.
30.1 Fundamental Operation
The PRG can be operated in three voltage ramp
generator modes:
• Falling Voltage (slope compensation)
• Rising Voltage
• Alternating Rising and Falling Voltage
In the Rising or Falling mode an internal capacitor is
discharged when the set_falling timing input is true and
charged by an internally generated constant current
when the set_rising timing input is true. The resulting
linear ramp starts at the selected voltage input level
and resets back to that level when the ramp is termi-
nated by the set_falling timing input. The set_falling
input dominates when both timing inputs are true.
To control the operation with a single-ended source,
select the same source for both the set_rising and
set_falling inputs and invert the polarity of one of them
with the corresponding polarity control bit.
In the Alternating mode the capacitor is not discharged
but alternates between being charged in one direction
then the other.
Input selections are identical for all modes. The input
voltage is supplied by any of the following:
• The PRGxIN0 or PRGxIN1 pins
• The buffered output of the internal Fixed Voltage
Reference (FVR),
• Any of the internal DACs.
The timing sources are selected from the following:
• The synchronized output of any comparator
• Any PWM output
•Any I/O pin
The ramp output is available as an input to any of the
comparators or op amps.
30.1.1 SLOPE COMPENSATION
Slope compensation works by quickly discharging an
internal capacitor at the beginning of each PWM period.
One side of the internal capacitor is connected to the
voltage input source and the other side is connected to
the internal current sink. The internal current sink
charges this capacitor at a programmable rate. As the
capacitor charges, the capacitor voltage is subtracted
from the voltage source, producing a linear voltage
decay at the required rate (see Figure 30-2). The ramp
terminates and the capacitor is discharged when the
set_falling timing input goes true. The next ramp starts
when the set_rising timing input goes true.
Enabling the optional one-shot by setting the OS bit of
the PRGxCON0 register ensures that the capacitor is
fully discharged by overriding the set_rising timing input
and holding the shorting switch closed for at least the
one-shot period, typically 50 ns. Edge sensitive timing
inputs that occur during the one-shot period will be
ignored. Level sensitive timing inputs that occur during,
and extend beyond, the one-shot period will be sus-
pended until the end of the one-shot time.
30.1.2 RAMP GENERATION
Ramp generation is similar to slope compensation
except that the slope is either both rising and falling or
just rising.
30.1.2.1 Alternating Rising/Falling Ramps
The alternating rising/falling ramp generation function
works by employing the built-in current source and sink
and relying on the synchronous control of the internal
analog switches and timing sources to ramp the mod-
ule’s output voltage up and then subsequently down.
Once initialized, the output voltage is ramped up linearly
by the current source at a programmable rate until the
set_falling timing source goes true, at which point the
current source is disengaged. At the same time, the
current sink is engaged to linearly ramp down the output
voltage, also at a programmable rate, until the set_rising
timing input goes true, thereby reversing the ramp slope.
The process then repeats to create a saw tooth like
waveform as shown in Figure 30-3 and Figure 30-4.
The set_rising and set_falling timing inputs can be
either edge or level sensitive which is selected with the
respective REDG and FEDG bits of the PRGxCON0
register. Edge sensitive operation is recommended for
periodic signals such as clocks, and level sensitive
operation is recommended for analog limit triggers
such as comparator outputs.
When the one-shot is enabled (OS bit is set) then both
the falling and rising ramps will persist for a minimum of
the one-shot period. Edge sensitive timing inputs that
occur during the one-shot period will be ignored. Level
TABLE 30-1: AVAILABLE PRG MODULES
Device PRG1 PRG2 PRG3 PRG4
PIC16(L)F1778 ●●●
PIC16(L)F1777/9 ●●●●
PIC16(L)F1777/8/9
DS40001819B-page 414 2015-2016 Microchip Technology Inc.
sensitive timing inputs that occur during, and extend
beyond, the one-shot period will be suspended until the
end of the one-shot time.
30.1.2.2 Rising Ramp
The Rising Ramp mode is identical to the Slope
Compensation mode except that the ramps have a ris-
ing slope instead of a falling slope. One side of the inter-
nal capacitor is connected to the voltage input source and
the other side is connected to the internal current source.
The internal current source charges this capacitor at a
programmable rate. As the capacitor charges, the capac-
itor voltage is added to the voltage source, producing a
linear voltage rise at the required rate (see Figure 30-5).
The ramp terminates and the capacitor is discharged
when the set_falling timing input goes true. The next
ramp starts when the set_rising timing input goes true.
Enabling the optional one-shot by setting the OS bit of
the PRGxCON0 register ensures that the capacitor is
fully discharged by overriding the set_rising timing input
and holding the shorting switch closed for at least the
one-shot period, typically 50 ns. Edge sensitive timing
inputs that occur during the one-shot period will be
ignored. Level sensitive timing inputs that occur during,
and extend beyond, the one-shot period will be
suspended until the end of the one-shot time.
30.2 Enable, Ready, Go
The EN bit of the PRGxCON0 register enables the ana-
log circuitry including the current sources. This permits
preparing the PRG module for use and allowing it to
become stable before putting it into operation. When the
EN bit is set then the timing inputs are enabled so that
initial ramp action can be determined before the GO bit
is set. The capacitor shorting switch is closed when the
EN bit is set and remains closed while the GO bit is zero.
The RDY bit of the PRGxCON1 register indicates that
the analog circuits and current sources are stable.
The GO bit of the PRGxCON0 register enables the
switch control circuits, thereby putting the PRG into
operation. The GO transition from cleared to set trig-
gers the one-shot, thereby extending the capacitor
shorting switch closure for the one-shot period.
To ensure predictable operation, set the EN bit first then
wait for the RDY bit to go high before setting the GO bit.
30.3 Independent Set_rising and
Set_fall ing Timing Inp uts
The timing inputs determine when the ramp starts and
stops. In the Alternating Rising/Falling mode the ramp
rises when the set_rising input goes true and falls when
the set_falling input goes true. In the Slope Compensa-
tion and Rising Ramp modes the capacitor is discharged
when the set_falling timing input goes true and the ramp
starts when the set_rising timing input goes true. The
set_falling input dominates the set_rising input.
30.4 Level and Edge Timing Sensitivity
The set_rising and set_falling timing inputs can be
independently configured as either level or edge sensi-
tive.
Level sensitive operation is useful when it is necessary
to detect a timing input true state after an overriding
condition ceases. For example, level sensitivity is use-
ful for capacitor generated timing inputs that may be
suppressed by the overriding action of the one-shot.
With level sensitivity a capacitor output that changes
during the one-shot period will be detected at the end
of the one-shot time. With edge sensitivity the change
would be ignored.
Edge sensitive operation is useful for periodic timing
inputs such as those generated by PWMs and clocks.
The duty cycle of a level sensitive periodic signal may
interfere with the other timing input. Consider an Alter-
nating Ramp mode with a level sensitive 50% PWM as
the set_rising timing source and a level sensitive com-
parator as the set_falling timing source. If the compar-
ator output reverses the ramp while the PWM signal is
still high then the ramp will improperly reverse again
when the comparator signal goes low. That same sce-
nario with the set_rising timing input set for edge sen-
sitivity would properly change the ramp output to rising
only on the rising edge of the PWM signal.
Set_rising and set_falling timing input edge sensitivity
is selected with the respective REDG and FEDG bits of
the PRGxCON1 register.
30.5 One-Shot Minimum T iming
The one-shot timer ensures a minimum capacitor dis-
charge time in the Slope Compensation and Rising
Ramp modes, and a minimum rising or falling ramp
duration in the Alternating Ramp mode. Setting the OS
bit of the PRGxCON0 register enables the one-shot
timer.
30.6 DAC Voltage Sources
When using any of the DACs as the voltage source
expect a voltage offset equal to the current setting
times the DAC equivalent resistance. This will be a
constant offset in the Slope Compensation and Ramp
modes and a positive/negative step offset in the
Alternating mode. To avoid this limitation, feed the DAC
output to the PRG input through one of the op amps set
for unity gain.
30.7 Operation During Sleep
The RG module is unaffected by Sleep.
30.8 Effects of a Reset
The RG module resets to a disabled condition.
2015-2016 Microchip Technology Inc. DS40001819B-page 415
PIC16(L)F1777/8/9
FIGURE 30-1: SIMPLIFIED PRG MODULE BLOCK DIAGRAM
PRGxIN
RTSS<3:0>
FPOL
FTSS<3:0>
ISET<4:0>
RAMPx_out to
peripherals
VDD
Rev . 10 -000 220A
5/29 /201 4
SW1
SW3
SW2
RPOL
Switch
Control
REDG
FEDG
EN
ISET<4:0>
MODE<1:0>
INS<3:0>
PRGxR
PRGxF
GO
Voltage Sources
Set_rising Timing Sources
Set_falling Timing Sources
R
SQ
OS
voltage_ref
PPS
PPS
PRGxRPPS
PRGxFPPS
See Table 30-4
See Table 30-4
(See Table 30-3)
(See Table 30-5)
(See Table 30-5)
PIC16(L)F1777/8/9
DS40001819B-page 416 2015-2016 Microchip Technology Inc.
FIGURE 30-2: SLOPE COMPENSATION (FALLING RAMP) TIMING DIAGRAM (MODE = 00)
Rev. 10 -000 223A
5/2/201 4
EN
RDY
GO
Init Running
set_falling
on e_sho t
sw1_closed
voltage_ref
RAMPx_out
sw2_closed
sw3_closed
Init Running
OS
set_rising
2015-2016 Microchip Technology Inc. DS40001819B-page 417
PIC16(L)F1777/8/9
FIGURE 30-3: ALTERN ATING RISING/FALLING RAMP GENERATION TIMING DIAGRAM (OS = 0, MODE = 01)
Rev. 10 -000 222A
4/29 /201 4
EN
RDY
GO
set_rising
Init Running
set_falling
on e_sho t
sw1_closed
voltage_ref
RAMPx_out
sw2_closed
sw3_closed
Init Running
REDG
FEDG
PIC16(L)F1777/8/9
DS40001819B-page 418 2015-2016 Microchip Technology Inc.
FIGURE 30-4: ALTERN ATING RISING/FALLING RAMP GENERATION TIMING DIAGRAM (OS = 1, MODE = 01)
Rev. 10 -000 226A
5/2/201 4
EN
RDY
GO
set_rising
Init Running
set_falling
on e_sho t
sw1_closed
voltage_ref
RAMPx_out
sw2_closed
sw3_closed
Init Running
REDG
FEDG
2015-2016 Microchip Technology Inc. DS40001819B-page 419
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FIGURE 30-5: RISING RAMP GENERATION TIMING DIAGRAM (MODE = 10)
Rev. 10 -000 224A
5/2/201 4
EN
RDY
GO
Init Running
set_rising
on e_sho t
sw1_closed
voltage_ref
RAMPx_out
sw2_closed
sw3_closed
Init Running
OS
set_falling
PIC16(L)F1777/8/9
DS40001819B-page 420 2015-2016 Microchip Technology Inc.
30.9 Slope Compensation Application
An example slope compensation circuit is shown in
Figure 30-6. The PRG input voltage is PRGxIN which
shares an I/O pin with the op amp output. The op amp
output is designed to operate at the expected peak cur-
rent sense voltage (i.e., VREF). The PRG output voltage
starts at VREF and should fall at a rate less than half the
target circuit current sense voltage rate of rise. There-
fore, the compensator slope expressed as volts per µs
can be computed by Equation 30-1.
EQUATION 30-1:
For example, when the circuit is using a 1 current
sense resistor and the peak current is 1A, then the
peak current expressed as a voltage is 1V. Therefore,
for this example, the op amp output should be designed
to operate at 1V. If the power supply PWM frequency is
1 MHz, then the period is 1 s. Therefore, the desired
slope is 0.5 V/s, which is computed as shown in
Equation 30-2.
EQUATION 30-2:
FIGURE 30-6: EXAMP LE SLOPE COMPENSATION CIRCUIT
V
s
------
VREF
2
-------------
PWM Period (
s
--------------------------------------------
VREF
2
-------------
PWM Per i od (
s
--------------------------------------------
1
2
---
1
s
--------- 0.5V
s==
Note: The setting for 0.5V/s is ISET<4:0> = 6
COG
-
+
PRG
COGxOUTx
CxINx-
RGxIN
VIN
L1
D1
C1
R1
R2
R3
-
+
OPA xOUT OPAxIN-
C3
DAC
R4
R5 C2
Rev . 10 -000 221 A
5/7/ 201 4
2015-2016 Microchip Technology Inc. DS40001819B-page 421
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30.10 Register Definitions: Slope Compensation Control
Long bit name prefixes for the PRG peripherals are
shown in Table 30-2. Refer to Section 1.1 “Register
and Bit naming conventions” for more information
TABLE 30-2:
Peripheral Bit Name Prefix
PRG1 RG1
PRG2 RG2
PRG3 RG3
PRG4(1) RG4
Note 1: PIC16(L)F1777/9 only.
REGISTER 30-1: PRGxCON0: PROGRAMMABLE RAMP GENERATOR CONTROL 0 REGISTER
R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
EN — FEDG REDG MODE<1:0> OS GO
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on configuration bits
bit 7 EN: Programmable Ramp Generator Enable bit
1 = PRG module is enabled
0 = PRG module is disabled
bit 6 Unimplemented: Read as ‘0’
bit 5 FEDG: Set_falling Input Mode Select bit
1 = Set_falling timing input is edge sensitive
0 = Set_falling timing input is level sensitive
bit 4 REDG: Set_rising Input Mode Select bit
1 = Set_rising timing input is edge sensitive
0 = Set_rising timing input is level sensitive
bit 3-2 MODE<1:0>: Programmable Ramp Generator Mode Selection bits
11 = Reserved
10 = Rising Ramp Generator
01 = Alternating Rising/Falling Ramp Generator
00 = Slope Compensation
bit 1 OS: One-Shot Enable bit
1 = One-shot is enabled. Minimum capacitor discharge is internally timed by one-shot.
0 = One-shot is disabled. Capacitor is discharged when timing input is true.
bit 0 GO: Ramp Generation Control Start bit
if EN = 1:
1 = Slope or Ramp function is operating
0 = Slope or Ramp function is not operating. All current source current source switches are open and
capacitor discharge switch is closed.
If EN = 0:
This bit is forced to 0
PIC16(L)F1777/8/9
DS40001819B-page 422 2015-2016 Microchip Technology Inc.
REGISTER 30-2: PRGxCON1: PROGRAMMABLE RAMP GENERATOR CONTROL 1 REGISTER
U-0 U-0 U-0 U-0 U-0 R-0 R/W-0/0 R/W-0/0
— — — — — RDY FPOL RPOL
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on configuration bits
bit 7-3 Unimplemented: Read as ‘0’
bit 2 RDY: Slope Generator Ready Status bit
1 = PRG is ready
0 = PRG is not ready
bit 1 FPOL: Fall Event Polarity Select bit
1 = Set_falling timing input is active-low
0 = Set_falling timing input is active-high
bit 0 RPOL: Rise Event Polarity Select bit
1 = Set_rising timing input is active-low
0 = Set_rising timing input is active-high
REGISTER 30-3: PRGxINS: VOLTAGE INPUT SELECT REGISTER
U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — —INS<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on configuration bits
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 INS<3:0>: Voltage Input Select bits
Selects source of voltage level at which the ramp starts. See Table 30-3.
TABLE 30-3: VOLTAGE INPUT SOURCES
INS<2:0> P RG1 Volt age Source PRG2 Voltage Source PRG3 Voltage Source PRG4 Voltage Source(2)
1010-1111 Reserved Reserved Reserved Reserved
1001(1) Switched PRG1IN1/OPA2OUT Switched PRG1IN1/OPA2OUT Switched
PRG3IN1/OPA4OUT(2) Switched PRG4IN1/OPA3OUT
1000(1) Switched PRG1IN0/OPA1OUT Switched PRG1IN0/OPA1OUT Switched PRG3IN0/OPA3OUT Switched PRG4IN0/OPA4OUT
0111 Reserved Reserved Reserved Reserved
0110 DAC4_output DAC4_output DAC8_output(2) DAC8_output
0101 DAC3_output DAC3_output DAC7_output DAC7_output
0100 DAC2_output DAC2_output DAC6_output(2) DAC6_output
0011 DAC1_output DAC1_output DAC5_output DAC5_output
0010 FVR_buffer1 FVR_buffer1 FVR_buffer2 FVR_buffer2
0001 PRG1IN1/OPA2OUT PRG2IN1/OPA1OUT PRG3IN1/OPA4OUT(2) PRG4IN1/OPA3OUT
0000 PRG1IN0/OPA1OUT PRG2IN0/OPA2OUT PRG3IN0/OPA3OUT PRG4IN0/OPA4OUT
Note 1: Input source is switched off when op amp override is forcing tri-state. See Se ction 29.3 “Overr ide
Control”.
2: PIC16(L)F1777/9 only.
2015-2016 Microchip Technology Inc. DS40001819B-page 423
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REGISTER 30-4: PRGxCON2: PROGRAMMABLE RAMP GENERATOR CONTROL 2 REGISTER
U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — ISET<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on configuration bits
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 ISET<4:0>: PRG Current Source/Sink Set bits
Current source/sink setting and slope rate. See Table 30-4.
TABLE 30-4: PROGRAMMABLE RAMP GENERATOR CURRENT SETTINGS
ISET<4:0> Current Setting
(uA) Slope Rate
(V/us) ISET<4:0> Current Setting
(uA) Slope Rate
(V/us)
0h 2 0.2 10h 10 1.0
1h 2.5 0.25 11h 11 1.1
2h 3 0.3 12h 12 1.2
3h 3.5 0.35 13h 13 1.3
4h 4 0.4 14h 14 1.4
5h 4.5 0.45 15h 15 1.5
6h 5 0.5 16h 16 1.6
7h 5.5 0.55 17h 17 1.7
8h 6 0.6 18h 18 1.8
9h 6.5 0.65 19h 19 1.9
Ah 7 0.7 1Ah 20 2.0
Bh 7.5 0.75 1Bh 21 2.1
Ch 8 0.8 1Ch 22 2.2
Dh 8.5 0.85 1Dh 23 2.3
Eh 9 0.9 1Eh 24 2.4
Fh 9.5 0.95 1Fh 25 2.5
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REGISTER 30-5: PRGxRTSS: SET_RISING TIMING SOURCE SELECT REGISTER
U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — RTSS<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on configuration bits
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 RTSS<3:0>: Set_rising Timing Source Select bits
See Table 30-5.
REGISTER 30-6: PRGxFTSS: SET_FALLING TIMING SOURCE SELECT REGISTER
U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — FTSS<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on configuration bits
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 FTSS<3:0>: Set_falling Timing Source Select bits
See Table 30-5.
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TABLE 30-5: PROGRAMMABLE RAMP GENERATOR TIMING SOURCES
RTSS<3:0>/
FTSS<3:0> PRG1 Timing Source PRG2 Timing Source PRG3 Timing Source PRG4 Timing Source(2)
1111 Reserved Reserved PWM12_output(2) PWM12_output
1110 Reserved Reserved PWM11_output PWM11_output
1101 LC2_out LC2_out PWM6_output PWM6_output
1100 LC1_out LC1_out PWM5_output PWM5_output
1011 PWM10_output(2) PWM10_output(2) Reserved Reserved
1010 PWM9_output PWM9_output Reserved Reserved
1001 PWM4_output PWM4_output LC4_out(2) LC4_out
1000 PWM3_output PWM3_output LC3_out LC3_out
0111 PRGxR/PRGxF Pin(1) PRGxR/PRGxF Pin(1) PRGxR/PRGxF Pin(1) PRGxR/PRGxF Pin(1)
0110 Reserved Reserved sync_C7OUT(2) sync_C7OUT
0101 Reserved Reserved sync_C6OUT sync_C6OUT
0100 Reserved Reserved sync_C5OUT sync_C5OUT
0011 sync_C4OUT sync_C4OUT Reserved Reserved
0010 sync_C3OUT sync_C3OUT Reserved Reserved
0001 sync_C2OUT sync_C2OUT Reserved Reserved
0000 sync_C1OUT sync_C1OUT Reserved Reserved
Note 1: Input pin is selected with the PRGxRPPS or PRGxFPPS register.
2: PIC16(L)F1777/9 only.
PIC16(L)F1777/8/9
DS40001819B-page 426 2015-2016 Microchip Technology Inc.
TABLE 30-6: SUMMARY OF REGISTERS ASSOCIATED WITH THE PRG MODULE(1)
Name Bit 7 Bit 6 Bit 5 Bit 4 B it 3 Bit 2 B it 1 Bit 0 Register
on Page
PRGxCON0 EN — FEDG REDG MODE<1:0> OS GO 421
PRGxCON1 — — — — — RDY FPOL RPOL 422
PRGxCON2 — — — ISET<4:0> 423
PRGxINS — — — — INS<3:0> 422
PRGxRPPS — — PRGxRPPS<5:0> 424
PRGxFPPS — — PRGxFPPS<5:0> 424
PRGxRTSS — — — — RTSS<3:0> 205, 207
PRGxFTSS — — — — FTSS<3:0> 205, 207
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 186
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186
ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 187
WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 188
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the PRG module.
Note 1: PRG4 available on PIC16(L)F1777/9 only.
2015-2016 Microchip Technology Inc. DS40001819B-page 427
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31.0 DATA SIGNAL MODULATOR
(DSM)
The Data Signal Modulator (DSM) is a peripheral that
allows the user to mix a data stream, also known as a
modulator signal, with a carrier signal to produce a mod-
ulated output.
Both the carrier and the modulator signals are supplied
to the DSM module either internally, from the output of
a peripheral, or externally through an input pin.
The modulated output signal is generated by performing
a logical “AND” operation of both the carrier and modu-
lator signals and then provided to the MDxOUT pin.
The carrier signal is comprised of two distinct and sepa-
rate signals. A carrier high (CARH) signal and a carrier
low (CARL) signal. During the time in which the modula-
tor (MOD) signal is in a logic high state, the DSM mixes
the carrier high signal with the modulator signal. When
the modulator signal is in a logic low state, the DSM
mixes the carrier low signal with the modulator signal.
Using this method, the DSM can generate the following
types of Key Modulation schemes:
• Frequency-Shift Keying (FSK)
• Phase-Shift Keying (PSK)
• On-Off Keying (OOK)
Additionally, the following features are provided within
the DSM module:
• Carrier Synchronization
• Carrier Source Polarity Select
• Carrier Source Pin Disable
• Programmable Modulator Data
• Modulator Source Pin Disable
• Modulated Output Polarity Select
• Slew Rate Control
Figure 31-1 shows a Simplified Block Diagram of the
Data Signal Modulator peripheral.
TABLE 31-1: AVAILABLE DSM MODULES
Device DSM1 DSM2 DSM3 DSM4
PIC16(L)F1778 ●●●
PIC16(L)F1777/9 ●●●●
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DS40001819B-page 428 2015-2016 Microchip Technology Inc.
FIGURE 31-1: SI MPLIFI ED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR
D
Q
MDXMODPPS
MDXCHPPS
MDXCLPPS
CH<3:0>
MS<3:0>
CL<3:0>
SYNC
CHPOL
CLPOL
D
Q1
0
SYNC
1
0
CHSYNC
CLSYNC
MDXOUT
OPOL
CARH
CARL
EN
Data Signal
Modulator
MOD
PPS
RXYPPS
Carrier High Sources
See Table 3 1- 6
Modulation Sources
See Table 31-6
Carrier Low Sources
See Table 31-7.
PPS
PPS
PPS
MDX_OUT
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31.1 DSM Operation
The DSM module is enabled by setting the EN bit in the
MDxCON register. Clearing the EN bit in the MDxCON
register disables the DSM module by automatically
switching the carrier high and carrier low signals to the
VSS signal source. The modulator signal source is also
switched to the BIT bit in the MDxCON0 register. This
not only assures that the DSM module is inactive, but
that it is also consuming the least amount of current.
The values used to select the carrier high, carrier low,
and modulator sources held by the Modulation Source,
Modulation High Carrier, and Modulation Low Carrier
control registers are not affected when the EN bit is
cleared and the DSM module is disabled. The values
inside these registers remain unchanged while the
DSM is inactive. The sources for the carrier high, car-
rier low and modulator signals will once again be
selected when the EN bit is set and the DSM module is
enabled and active.
The modulated output signal can be output on any
device I/O pin by selecting the desired DSM module in
the pin’s PPS control register (see Register 12-2). If the
output is not directed to any I/O pin then the DSM mod-
ule will remain active and continue to mix signals, but
the output value will not be sent to any pin.
31.2 Modulator Signal Sources
The modulator signal is selected by configuring the
MS<4:0> bits of the MDxSRC register. Selections are
shown in Tab le 31-6 .
31.3 Carrier Signal Sources
The carrier high signal is selected by configuring the
CH<4:0> bits of the MDxCARH register. Selections are
shown in Tab le 31-6 .
The carrier low signal is selected by configuring the
CL<4:0> bits of the MDxCARL register. Selections are
shown in Tab le 31-7 .
31.4 Carrier Synchronization
During the time when the DSM switches between car-
rier high and carrier low signal sources, the carrier data
in the modulated output signal can become truncated.
To prevent this, the carrier signal can be synchronized
to the modulator signal. When synchronization is
enabled, the carrier pulse that is being mixed at the
time of the transition is allowed to transition low before
the DSM switches over to the next carrier source.
Synchronization is enabled separately for the carrier
high and carrier low signal sources. Synchronization for
the carrier high signal is enabled by setting the
CHSYNC bit of the MDxCON1 register. Synchroniza-
tion for the carrier low signal is enabled by setting the
CLSYNC bit of the MDxCON1 register.
Figure 31-1 through Figure 31-6 show timing diagrams
of using various synchronization methods.
PIC16(L)F1777/8/9
DS40001819B-page 430 2015-2016 Microchip Technology Inc.
FIGURE 31-2: ON OFF KEYING (OOK) SYNCHRONIZATION
FIGURE 31-3: NO SYNCHRONI ZATION (MDCHSYNC = 0, MDCLSYNC = 0)
FIGURE 31-4: CARRIER HIGH SYNCHRONIZATION (MDCHSYNC = 1, MDCLSYNC = 0)
Carrier Low (CARL)
1 X MDx_out
0 X MDx_out
Carrier High (CARH)
Modulator (MOD)
MDCLSYNC
MDCHSYNC
MDx_out
Modulator (MOD)
Carrier High (CARH)
Carrier Low (CARL)
Active Carrier CARH CARL CARL
CARH
State
MDx_out
Modulator (MOD)
Carrier High (CARH)
Carrier Low (CARL)
Active Carrier
CARH CARL CARL
CARH
State
both both
2015-2016 Microchip Technology Inc. DS40001819B-page 431
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FIGURE 31-5: CARRI ER LOW SYNCHRONIZATION (MDCHS YNC = 0, MDCLSYNC = 1)
FIGURE 31-6: FULL SYNCHRONIZATION (MDCHSYNC = 1, MDCLSYNC = 1)
MDx_out
Modulator (MOD)
Carrier High (CARH)
Carrier Low (CARL)
Active Carrier CARH CARL CARL
CARH
State
MDx_out
Modulator (MOD)
Carrier High (CARH)
Carrier Low (CARL)
Active Carrier CARH CARL CARL
CARH
State
Falling edges
used to sync
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31.5 Input and Output Through Pins
The modulation and carrier sources may be selected
to come from any device pin with the PPS control logic.
Selecting a pin requires two settings: The source
selection determines that the PPS will be used and the
PPS control selects the desired pin. Source and PPS
registers are identified in Table 31-2. PPS register pin
selections are shown in Register 12-1 and
Register 12-2.
Any device pin can be selected as the modulation out-
put with the individual pin PPS controls. See
Register 12-2 for the pin output selections.
31.6 Carrier Source Polarity Select
The signal provided from any selected input source for
the carrier high and carrier low signals can be inverted.
Inverting the signal for the carrier high source is
enabled by setting the CHPOL bit of the MDxCON1
register. Inverting the signal for the carrier low source is
enabled by setting the CLPOL bit of the MDxCON1
register.
31.7 Programmable Modulator Data
The BIT bit of the MDxCON0 register can be selected
as the source for the modulator signal. When the BIT
source is selected then software generates the modu-
lation signal by setting and clearing the BIT bit at the
respective desired modulation high and low times.
31.8 Modulated Output Polarity
The modulated output signal provided on the MDxOUT
pin can also be inverted. Inverting the modulated out-
put signal is enabled by setting the OPOL bit of the
MDxCON0 register.
31.9 Operation in Sleep M ode
The DSM module is not affected by Sleep mode. The
DSM will operate during Sleep provided that the Carrier
and Modulator input sources are also active during
Sleep.
31.10 Effects of a Reset
Upon any device Reset, the data signal modulator
module is disabled. The user’s firmware is responsible
for initializing the module before enabling the output.
The registers are reset to their default values.
TABLE 31-2:
Source Source
Register PPS Regis ter
Modulation MDxSRC MDxMODPPS
Carrier High MDxCARH MDxCHPPS
Carrier Low MDxCARL MDxCLPPS
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31.11 Register Definitions: Data Signal Modulator
Long bit name prefixes for the 10-bit DAC peripherals
are shown in Table 31-3. Refer to Section 1.1 “ Reg is-
ter and Bit naming conventions” for more informa-
tion
TABLE 31-3:
Peripheral Bit Name Prefix
DSM1 DSM1
DSM2 DSM2
DSM3 DSM3
DSM4(1) DSM4
Note 1: PIC16(L)F1777/9 only.
REGISTER 31-1: MDxCON0: MODULATION CONTROL REGISTER 0
R/W-0/0 U-0 R-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0
EN — OUT OPOL — — —BIT
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 EN: Modulator Module Enable bit
1 = Modulator module is enabled and mixing input signals
0 = Modulator module is disabled and has no output
bit 6 Unimplemented: Read as ‘0’
bit 5 OUT: Modulator Output bit
Displays the current output value of the modulator module.(1)
bit 4 OPOL: Modulator Output Polarity Select bit
1 = Modulator output signal is inverted. Idle high output.
0 = Modulator output signal is not inverted. Idle low output.
bit 3-1 Unimplemented: Read as ‘0’
bit 0 BIT: Allows direct software control of the modulation source input to module(2)
1 = Modulator uses High Carrier source
0 = Modulator uses Low Carrier source
Note 1: The modulated output frequency can be greater and asynchronous from the clock that updates this
register bit, the bit value may not be valid for higher speed modulator or carrier signals.
2: BIT must be selected as the modulation source in the MDSRC register for this operation.
PIC16(L)F1777/8/9
DS40001819B-page 434 2015-2016 Microchip Technology Inc.
REGISTER 31-2: MDxCON1: MODULATION CONTROL REGISTER 1
U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
—— CHPOL CHSYNC —— CLPOL CLSYNC
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 Unimplemented: Read as ‘0’
bit 5 CHPOL: Modulation High Carrier Polarity Select bit
1 = Selected high carrier source is inverted
0 = Selected high carrier source is not inverted
bit 4 CHSYNC: Modulation High Carrier Synchronization Enable bit
1 = Modulator waits for a low edge on the high carrier before allowing a switch to the low carrier
0 = Modulator output is not synchronized to the high carrier(1)
bit 3-2 Unimplemented: Read as ‘0’
bit 1 CLPOL: Modulation Low Carrier Polarity Select bit
1 = Selected low carrier source is inverted
0 = Selected low carrier source is not inverted
bit 0 CLSYNC: Modulation Low Carrier Synchronization Enable bit
1 = Modulator waits for a low edge on the low carrier before allowing a switch to the high carrier
0 = Modulator output is not synchronized to the low carrier(1)
Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
REGISTER 31-3: MDxSRC: MODULATION SOURCE CONTROL REGISTER
U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — —MS<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 MS<4:0> Modulation Source Selection bits
See Table 31-4 or Table 31-5.
2015-2016 Microchip Technology Inc. DS40001819B-page 435
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TABLE 31-4: MODULATION SOURCE
MS<4:0> Modulation Sour ce
PIC16(L)F1777/9
11111 Reserved
11110 Reserved
11101 Reserved
11100 Reserved
11011 Reserved
11010 sync_C8OUT
11001 sync_C7OUT
11000 sync_C4OUT
10111 sync_C3OUT
10110 sync_C2OUT
10101 sync_C1OUT
10100 LC4_out
10011 LC3_out
10010 LC2_out
10001 LC1_out
10000 PWM12_out
01111 PWM11_out
01110 PWM6_out
01101 PWM5_out
01100 PWM10_out
01011 PWM9_out
01010 PWM4_out
01001 PWM3_out
01000 PWM8_out
00111 CCP7_out
00110 CCP2_out
00101 CCP1_out
00100 SDO_OUT
00011 DT
00010 TX_out
00001 MDxBIT
00000 MDxMODPPS pin selection
TABLE 31-5: MODULATION SOURCE
MS<4:0> Modulation Source
PIC16(L)F1778
11111 Reserved
11110 Reserved
11101 Reserved
11100 Reserved
11011 Reserved
11010 sync_C6OUT
11001 sync_C5OUT
11000 sync_C4OUT
10111 sync_C3OUT
10110 sync_C2OUT
10101 sync_C1OUT
10100 LC4_out
10011 LC3_out
10010 LC2_out
10001 LC1_out
10000 Reserved
01111 PWM11_out
01110 PWM6_out
01101 PWM5_out
01100 Reserved
01011 PWM9_out
01010 PWM4_out
01001 PWM3_out
01000 Reserved
00111 CCP7_out
00110 CCP2_out
00101 CCP1_out
00100 SDO_OUT
00011 DT
00010 TX_out
00001 MDxBIT
00000 MDxMODPPS pin selection
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DS40001819B-page 436 2015-2016 Microchip Technology Inc.
REGISTER 31-4: MDxCARH: MODULATION HIGH CARRIER CONTROL REGISTER
U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — — CH<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 CH<4:0> Modulator Data High Carrier Selection bits(1)
See Table 31-6.
Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
2015-2016 Microchip Technology Inc. DS40001819B-page 437
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TABLE 31-6: HIGH CARRIER SOURCE
CH<4:0> Carrier Source
PIC16(L)F1778 Carrier Source
PIC16(L)F1777/9
11111 Reserved Reserved
11110 Reserved Reserved
11101 Reserved Reserved
11100 Reserved Reserved
11011 Reserved Reserved
11010 Reserved Reserved
11001 Reserved Reserved
11000 Reserved Reserved
10111 Reserved Reserved
10110 Reserved Reserved
10101 Reserved Reserved
10100 Reserved Reserved
10011 Reserved Reserved
10010 LC4_out LC4_out
10001 LC3_out LC3_out
10000 LC2_out LC2_out
01111 LC1_out LC1_out
01110 Reserved PWM12_out
01101 PWM11_out PWM11_out
01100 PWM6_out PWM6_out
01011 PWM5_out PWM5_out
01010 Reserved PWM10_out
01001 PWM9_out PWM9_out
01000 PWM4_out PWM4_out
00111 PWM3_out PWM3_out
00110 Reserved CCP8_out
00101 CCP7_out CCP7_out
00100 CCP2_out CCP2_out
00011 CCP1_out CCP1_out
00010 HFINTOSC HFINTOSC
00001 FOSC FOSC
00000 MDxMODPPS pin selection MDxMODPPS pin selection
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REGISTER 31-5: MDxCARL: MODULATION LOW CARRIER CONTROL REGISTER
U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — — CL<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 CL<4:0> Modulator Data Low Carrier Selection bits(1)
See Table 31-7.
Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
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TABLE 3 1-8 : SUMMARY OF REG IS TER S ASS OCIA TE D WIT H DA TA SIGN AL MOD ULAT OR MODE (1)
TABLE 31-7: LOW CARRIER SOURCE
CH<4:0> Carrier Source
PIC16(L)F1778 Carrier Source
PIC16(L)F1777/9
11111 Reserved Reserved
11110 Reserved Reserved
11101 Reserved Reserved
11100 Reserved Reserved
11011 Reserved Reserved
11010 Reserved Reserved
11001 Reserved Reserved
11000 Reserved Reserved
10111 Reserved Reserved
10110 Reserved Reserved
10101 Reserved Reserved
10100 Reserved Reserved
10011 Reserved Reserved
10010 LC4_out LC4_out
10001 LC3_out LC3_out
10000 LC2_out LC2_out
01111 LC1_out LC1_out
01110 Reserved PWM12_out
01101 PWM11_out PWM11_out
01100 PWM6_out PWM6_out
01011 PWM5_out PWM5_out
01010 Reserved PWM10_out
01001 PWM9_out PWM9_out
01000 PWM4_out PWM4_out
00111 PWM3_out PWM3_out
00110 Reserved CCP8_out
00101 CCP7_out CCP7_out
00100 CCP2_out CCP2_out
00011 CCP1_out CCP1_out
00010 HFINTOSC HFINTOSC
00001 FOSC FOSC
00000 MDxMODPPS pin selection MDxMODPPS pin selection
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
MDxCARH ———
CH<4:0>
436
MDxCARL ———
CL<4:0>
438
MDxSRC ———
MS<4:0>
434
MDxCON0 EN — OUT OPOL ———
BIT
433
MDxCON1 —— CHPOL
CHSYNC
——CLPOL
CLSYNC
433
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in the Data Signal Modulator mode.
Note 1: DSM4 available on PIC16LF1777/9 only.
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32.0 MASTER SYNCHRONOUS
SERIAL PORT (MS SP)
MODULE
32.1 MSSP Module Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
The SPI interface supports the following modes and
features:
•Master mode
• Slave mode
• Clock Parity
• Slave Select Synchronization (Slave mode only)
• Daisy-chain connection of slave devices
Figure 32-1 is a block diagram of the SPI interface
module.
FIGURE 32-1: MSSP BLOCK DIAGRAM (SPI MODE)
( )
Read Write
Data Bus
SSPSR Reg
SSPM<3:0>
bit 0 Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
T2_match
2
Edge
Select
2 (CKP, CKE)
4
TRIS bit
SDO
SSPxBUF Reg
SDI
SS
SCK
TOSC
Prescaler
4, 16, 64
Baud Rate
Generator
(SSPxADD)
PPS
PPS
PPS
PPS
SSPDATPPS
RxyPPS
SSPCLKPPS(2)
PPS
RxyPPS(1)
SSPSSPPS
Note 1: Output selection for master mode
2: Input selection for slave mode
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The I2C interface supports the following modes and
features:
•Master mode
• Slave mode
• Byte NACKing (Slave mode)
• Limited multi-master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
• Clock stretching
• Bus collision detection
• General call address matching
•Address masking
• Address Hold and Data Hold modes
• Selectable SDA hold times
Figure 32-2 is a block diagram of the I2C interface mod-
ule in Master mode. Figure 32-3 is a diagram of the I2C
interface module in Slave mode.
FIGURE 32-2: MSSP BLOCK DIAGRAM (I2C MASTER MODE)
Read Write
SSPSR
Start bit, Stop bit,
Start bit detect,
SSPxBUF
Internal
data bus
Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV
Shift
Clock
MSb LSb
SDA
Acknowledge
Generate (SSPxCON2)
Stop bit detect
Write collision detect
Clock arbitration
State counter for
end of XMIT/RCV
SCL
SCL in
Bus Collision
SDA in
Receive Enable (RCEN)
Clock Cntl
Clock arbitrate/BCOL detect
(Hold off clock source)
[SSPM<3:0>]
Baud Rate
Reset SEN, PEN (SSPxCON2)
Generator
(SSPxADD)
Address Match detect
Set SSP1IF, BCL1IF
PPS
SSPDATPPS(1)
PPS
Note 1: SDA pin selections must be the same for input and output
2: SCL pin selections must be the same for input and output
PPS
RxyPPS(1)
PPS
SSPCLKPPS(2)
RxyPPS(1)
RxyPPS(2)
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FIGURE 32-3: MSSP BLOCK DIAGRAM (I2C SL AV E MODE)
Read Write
SSPSR Reg
Match Detect
SSPxADD Reg
Start and
Stop bit Detect
SSPxBUF Reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPxSTAT Reg)
SCL
Shift
Clock
MSb LSb
SSPxMSK Reg
PPS
PPS
SSPCLKPPS(2)
RxyPPS(2)
Clock
Stretching
SDA
PPS
PPS
SSPDATPPS(1)
RxyPPS(1)
Note 1: SDA pin selections must be the same for input and output
2: SCL pin selections must be the same for input and output
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32.2 SPI Mode Overview
The Serial Peripheral Interface (SPI) bus is a
synchronous serial data communication bus that
operates in Full-Duplex mode. Devices communicate
in a master/slave environment where the master device
initiates the communication. A slave device is
controlled through a Chip Select known as Slave
Select.
The SPI bus specifies four signal connections:
• Serial Clock (SCK)
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Slave Select (SS)
Figure 32-1 shows the block diagram of the MSSP
module when operating in SPI mode.
The SPI bus operates with a single master device and
one or more slave devices. When multiple slave
devices are used, an independent Slave Select
connection is required from the master device to each
slave device.
Figure 32-4 shows a typical connection between a
master device and multiple slave devices.
The master selects only one slave at a time. Most slave
devices have tri-state outputs so their output signal
appears disconnected from the bus when they are not
selected.
Transmissions involve two shift registers, eight bits in
size, one in the master and one in the slave. With either
the master or the slave device, data is always shifted
out one bit at a time, with the Most Significant bit (MSb)
shifted out first. At the same time, a new Least
Significant bit (LSb) is shifted into the same register.
Figure 32-5 shows a typical connection between two
processors configured as master and slave devices.
Data is shifted out of both shift registers on the
programmed clock edge and latched on the opposite
edge of the clock.
The master device transmits information out on its SDO
output pin which is connected to, and received by, the
slave’s SDI input pin. The slave device transmits infor-
mation out on its SDO output pin, which is connected
to, and received by, the master’s SDI input pin.
To begin communication, the master device first sends
out the clock signal. Both the master and the slave
devices should be configured for the same clock polar-
ity.
The master device starts a transmission by sending out
the MSb from its shift register. The slave device reads
this bit from that same line and saves it into the LSb
position of its shift register.
During each SPI clock cycle, a full-duplex data
transmission occurs. This means that while the master
device is sending out the MSb from its shift register (on
its SDO pin) and the slave device is reading this bit and
saving it as the LSb of its shift register, that the slave
device is also sending out the MSb from its shift register
(on its SDO pin) and the master device is reading this
bit and saving it as the LSb of its shift register.
After eight bits have been shifted out, the master and
slave have exchanged register values.
If there is more data to exchange, the shift registers are
loaded with new data and the process repeats itself.
Whether the data is meaningful or not (dummy data),
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends useful data and slave sends dummy
data.
• Master sends useful data and slave sends useful
data.
• Master sends dummy data and slave sends useful
data.
Transmissions may involve any number of clock
cycles. When there is no more data to be transmitted,
the master stops sending the clock signal and it
deselects the slave.
Every slave device connected to the bus that has not
been selected through its slave select line must disre-
gard the clock and transmission signals and must not
transmit out any data of its own.
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FIGURE 32-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION
32.2.1 SPI MODE REGISTERS
The MSSP module has five registers for SPI mode
operation. These are:
• MSSP STATUS register (SSPxSTAT)
• MSSP Control register 1 (SSPxCON1)
• MSSP Control register 3 (SSPxCON3)
• MSSP Data Buffer register (SSPxBUF)
• MSSP Address register (SSPxADD)
• MSSP Shift register (SSPSR)
(Not directly accessible)
SSPxCON1 and SSPxSTAT are the control and
STATUS registers in SPI mode operation. The
SSPxCON1 register is readable and writable. The
lower six bits of the SSPxSTAT are read-only. The
upper two bits of the SSPxSTAT are read/write.
In one SPI Master mode, SSPxADD can be loaded
with a value used in the Baud Rate Generator. More
information on the Baud Rate Generator is available in
Section 32.7 “Baud Rate Generator”.
SSPSR is the shift register used for shifting data in and
out. SSPxBUF provides indirect access to the SSPSR
register. SSPxBUF is the buffer register to which data
bytes are written, and from which data bytes are read.
In receive operations, SSPSR and SSPxBUF together
create a buffered receiver. When SSPSR receives a
complete byte, it is transferred to SSPxBUF and the
SSPxIF interrupt is set.
During transmission, the SSPxBUF is not buffered. A
write to SSPxBUF will write to both SSPxBUF and
SSPSR.
32.2.2 SPI MODE OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
To enable the serial port, SSP Enable bit, SSPEN of the
SSPxCON1 register, must be set. To reset or reconfig-
ure SPI mode, clear the SSPEN bit, re-initialize the
SSPxCONx registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port
function, some must have their data direction bits (in
the TRIS register) appropriately programmed as
follows:
• SDI must have corresponding TRIS bit set
• SDO must have corresponding TRIS bit cleared
• SCK (Master mode) must have corresponding
TRIS bit cleared
• SCK (Slave mode) must have corresponding
TRIS bit set
•SS
must have corresponding TRIS bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
SPI Master SCK
SDO
SDI
General I/O
General I/O
General I/O
SCK
SDI
SDO
SS
SPI Slave
#1
SCK
SDI
SDO
SS
SPI Slave
#2
SCK
SDI
SDO
SS
SPI Slave
#3
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The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPxBUF). The
SSPSR shifts the data in and out of the device, MSb
first. The SSPxBUF holds the data that was written to
the SSPSR until the received data is ready. Once the
eight bits of data have been received, that byte is
moved to the SSPxBUF register. Then, the Buffer Full
Detect bit, BF of the SSPxSTAT register, and the inter-
rupt flag bit, SSPxIF, are set. This double-buffering of
the received data (SSPxBUF) allows the next byte to
start reception before reading the data that was just
received. Any write to the SSPxBUF register during
transmission/reception of data will be ignored and the
Write Collision Detect bit WCOL of the SSPxCON1 reg-
ister, will be set. User software must clear the WCOL bit
to allow the following write(s) to the SSPxBUF register
to complete successfully.
When the application software is expecting to receive
valid data, the SSPxBUF should be read before the
next byte of data to transfer is written to the SSPxBUF.
The Buffer Full bit, BF of the SSPxSTAT register,
indicates when SSPxBUF has been loaded with the
received data (transmission is complete). When the
SSPxBUF is read, the BF bit is cleared. This data may
be irrelevant if the SPI is only a transmitter. Generally,
the MSSP interrupt is used to determine when the
transmission/reception has completed. If the interrupt
method is not going to be used, then software polling
can be done to ensure that a write collision does not
occur.
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPxBUF register.
Additionally, the SSPxSTAT register indicates the
various Status conditions.
FIGURE 32-5: SPI MAST ER/SLAVE CONNECTION
Serial Input Buffer
(BUF)
Shift Register
(SSPSR)
MSb LSb
SDO
SDI
Processor 1
SCK
SPI Master SSPM<3:0> = 00xx
Serial Input Buffer
(SSPxBUF)
Shift Register
(SSPSR)
LSb
MSb
SDI
SDO
Processor 2
SCK
SPI Slave SSPM<3:0> = 010x
Serial Clock
SS
Slave Select
General I/O (optional)
= 1010
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32.2.3 SPI MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK line. The master
determines when the slave (Processor 2, Figure 32-5)
is to broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPxBUF register is written to. If the SPI
is only going to receive, the SDO output could be
disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPxBUF register as
if a normal received byte (interrupts and Status bits
appropriately set).
The clock polarity is selected by appropriately
programming the CKP bit of the SSPxCON1 register
and the CKE bit of the SSPxSTAT register. This then,
would give waveforms for SPI communication as
shown in Figure 32-6, Figure 32-8, Figure 32-9 and
Figure 32-10, where the MSB is transmitted first. In
Master mode, the SPI clock rate (bit rate) is user
programmable to be one of the following:
•F
OSC/4 (or TCY)
•FOSC/16 (or 4 * TCY)
•FOSC/64 (or 16 * TCY)
• Timer2 output/2
•F
OSC/(4 * (SSPxADD + 1))
Figure 32-6 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPxBUF is loaded with the received
data is shown.
Note: In Master mode the clock signal output to
the SCK pin is also the clock signal input
to the peripheral. The pin selected for out-
put with the RxyPPS register must also be
selected as the peripheral input with the
SSPCLKPPS register.
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FIGURE 32-6: SPI MODE WAVEFORM (MASTER MODE)
32.2.4 SPI SLAVE MODE
In Slave mode, the data is transmitted and received as
external clock pulses appear on SCK. When the last
bit is latched, the SSPxIF interrupt flag bit is set.
Before enabling the module in SPI Slave mode, the clock
line must match the proper Idle state. The clock line can
be observed by reading the SCK pin. The Idle state is
determined by the CKP bit of the SSPxCON1 register.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. The shift register is clocked from the SCK pin
input and when a byte is received, the device will
generate an interrupt. If enabled, the device will
wake-up from Sleep.
32.2.4.1 Daisy-Chain Configuration
The SPI bus can sometimes be connected in a
daisy-chain configuration. The first slave output is
connected to the second slave input, the second slave
output is connected to the third slave input, and so on.
The final slave output is connected to the master input.
Each slave sends out, during a second group of clock
pulses, an exact copy of what was received during the
first group of clock pulses. The whole chain acts as
one large communication shift register. The
daisy-chain feature only requires a single Slave Select
line from the master device.
Figure 32-7 shows the block diagram of a typical
daisy-chain connection when operating in SPI mode.
In a daisy-chain configuration, only the most recent
byte on the bus is required by the slave. Setting the
BOEN bit of the SSPxCON3 register will enable writes
to the SSPxBUF register, even if the previous byte has
not been read. This allows the software to ignore data
that may not apply to it.
SCK
(CKP = 0
SCK
(CKP = 1
SCK
(CKP = 0
SCK
(CKP = 1
4 Clock
Modes
Input
Sample
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 7
SDI
SSPxIF
(SMP = 1)
(SMP = 0)
(SMP = 1)
CKE = 1)
CKE = 0)
CKE = 1)
CKE = 0)
(SMP = 0)
Write to
SSPxBUF
SSPSR to
SSPxBUF
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(CKE = 0)
(CKE = 1)
bit 0
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32.2.5 SLAVE SELECT
SYNCHRONIZATION
The Slave Select can also be used to synchronize
communication. The Slave Select line is held high until
the master device is ready to communicate. When the
Slave Select line is pulled low, the slave knows that a
new transmission is starting.
If the slave fails to receive the communication properly,
it will be reset at the end of the transmission, when the
Slave Select line returns to a high state. The slave is
then ready to receive a new transmission when the
Slave Select line is pulled low again. If the Slave Select
line is not used, there is a risk that the slave will
eventually become out of sync with the master. If the
slave misses a bit, it will always be one bit off in future
transmissions. Use of the Slave Select line allows the
slave and master to align themselves at the beginning
of each transmission.
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSPxCON1<3:0> = 0100).
When the SS pin is low, transmission and reception are
enabled and the SDO pin is driven.
When the SS pin goes high, the SDO pin is no longer
driven, even if in the middle of a transmitted byte and
becomes a floating output. External pull-up/pull-down
resistors may be desirable depending on the applica-
tion.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
FIGURE 32-7: SPI DAISY-CHAIN CONNECTION
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPxCON1<3:0> =
0100), the SPI module will reset if the SS
pin is set to VDD.
2: When the SPI is used in Slave mode with
CKE set; the user must enable SS pin
control.
3: While operated in SPI Slave mode the
SMP bit of the SSPxSTAT register must
remain clear.
SPI Master SCK
SDO
SDI
General I/O
SCK
SDI
SDO
SS
SPI Slave
#1
SCK
SDI
SDO
SS
SPI Slave
#2
SCK
SDI
SDO
SS
SPI Slave
#3
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FIGURE 32-8: SL AVE SELECT SYNCHRONOUS WAVEFORM
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7
SDO bit 7 bit 6 bit 7
SSPxIF
Interrupt
CKE = 0)
CKE = 0)
Write to
SSPxBUF
SSPSR to
SSPxBUF
SS
Flag
bit 0
bit 7
bit 0
bit 6
SSPxBUF to
SSPSR
Shift register SSPSR
and bit count are reset
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FIGURE 32-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
FIGURE 32-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPxIF
Interrupt
CKE = 0)
CKE = 0)
Write to
SSPxBUF
SSPSR to
SSPxBUF
SS
Flag
Optional
bit 0
detection active
Write Collision
Valid
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPxIF
Interrupt
CKE = 1)
CKE = 1)
Write to
SSPxBUF
SSPSR to
SSPxBUF
SS
Flag
Not Optional
Write Collision
detection active
Valid
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32.2.6 SPI OPERATION IN SLEEP MODE
In SPI Master mode, module clocks may be operating
at a different speed than when in Full-Power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the MSSP
clock is much faster than the system clock.
In Slave mode, when MSSP interrupts are enabled,
after the master completes sending data, an MSSP
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSP
interrupts should be disabled.
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the
module will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all eight bits have been received, the
MSSP interrupt flag bit will be set and if enabled, will
wake the device.
TABLE 32-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 B it 3 Bit 2 Bit 1 B i t 0 Register
on Page
ANSELA —— ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177
ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 187
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139
RxyPPS — — RxyPPS<5:0> 205
SSPCLKPPS —— SSPCLKPPS<5:0> 205, 207
SSPDATPPS — — SSPDATPPS<5:0> 205, 207
SSPSSPPS —— SSPSSPPS<5:0> 205, 207
SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 444*
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 489
SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 488
SSP1STAT SMP CKE D/A P S R/W UA BF 488
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
* Page provides register information.
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32.3 I2C MODE OVERVIEW
The Inter-Integrated Circuit (I2C) bus is a multi-master
serial data communication bus. Devices communicate
in a master/slave environment where the master
devices initiate the communication. A slave device is
controlled through addressing.
The I2C bus specifies two signal connections:
• Serial Clock (SCL)
• Serial Data (SDA)
Figure 32-11 shows the block diagram of the MSSP
module when operating in I2C mode.
Both the SCL and SDA connections are bidirectional
open-drain lines, each requiring pull-up resistors for the
supply voltage. Pulling the line to ground is considered
a logical zero and letting the line float is considered a
logical one.
Figure 32-11 shows a typical connection between two
processors configured as master and slave devices.
The I2C bus can operate with one or more master
devices and one or more slave devices.
There are four potential modes of operation for a given
device:
• Master Transmit mode
(master is transmitting data to a slave)
• Master Receive mode
(master is receiving data from a slave)
•Slave Transmit mode
(slave is transmitting data to a master)
• Slave Receive mode
(slave is receiving data from the master)
To begin communication, a master device starts out in
Master Transmit mode. The master device sends out a
Start bit followed by the address byte of the slave it
intends to communicate with. This is followed by a
single Read/Write bit, which determines whether the
master intends to transmit to or receive data from the
slave device.
If the requested slave exists on the bus, it will respond
with an Acknowledge bit, otherwise known as an ACK.
The master then continues in either Transmit mode or
Receive mode and the slave continues in the comple-
ment, either in Receive mode or Transmit mode,
respectively.
A Start bit is indicated by a high-to-low transition of the
SDA line while the SCL line is held high. Address and
data bytes are sent out, Most Significant bit (MSb) first.
The Read/Write bit is sent out as a logical one when the
master intends to read data from the slave, and is sent
out as a logical zero when it intends to write data to the
slave.
FIGURE 32-11: I2C MASTER/
SLAVE CONNECTION
The Acknowledge bit (ACK) is an active-low signal,
which holds the SDA line low to indicate to the transmit-
ter that the slave device has received the transmitted
data and is ready to receive more.
The transition of a data bit is always performed while
the SCL line is held low. Transitions that occur while the
SCL line is held high are used to indicate Start and Stop
bits.
If the master intends to write to the slave, then it repeat-
edly sends out a byte of data, with the slave responding
after each byte with an ACK bit. In this example, the
master device is in Master Transmit mode and the
slave is in Slave Receive mode.
If the master intends to read from the slave, then it
repeatedly receives a byte of data from the slave, and
responds after each byte with an ACK bit. In this exam-
ple, the master device is in Master Receive mode and
the slave is Slave Transmit mode.
On the last byte of data communicated, the master
device may end the transmission by sending a Stop bit.
If the master device is in Receive mode, it sends the
Stop bit in place of the last ACK bit. A Stop bit is
indicated by a low-to-high transition of the SDA line
while the SCL line is held high.
In some cases, the master may want to maintain
control of the bus and re-initiate another transmission.
If so, the master device may send another Start bit in
place of the Stop bit or last ACK bit when it is in receive
mode.
The I2C bus specifies three message protocols:
• Single message where a master writes data to a
slave.
• Single message where a master reads data from
a slave.
• Combined message where a master initiates a
minimum of two writes, or two reads, or a
combination of writes and reads, to one or more
slaves.
Master
SCL
SDA
SCL
SDA
Slave
VDD
VDD
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When one device is transmitting a logical one, or letting
the line float, and a second device is transmitting a log-
ical zero, or holding the line low, the first device can
detect that the line is not a logical one. This detection,
when used on the SCL line, is called clock stretching.
Clock stretching gives slave devices a mechanism to
control the flow of data. When this detection is used on
the SDA line, it is called arbitration. Arbitration ensures
that there is only one master device communicating at
any single time.
32.3.1 CLOCK STRETCHING
When a slave device has not completed processing
data, it can delay the transfer of more data through the
process of clock stretching. An addressed slave device
may hold the SCL clock line low after receiving or send-
ing a bit, indicating that it is not yet ready to continue.
The master that is communicating with the slave will
attempt to raise the SCL line in order to transfer the
next bit, but will detect that the clock line has not yet
been released. Because the SCL connection is
open-drain, the slave has the ability to hold that line low
until it is ready to continue communicating.
Clock stretching allows receivers that cannot keep up
with a transmitter to control the flow of incoming data.
32.3.2 ARBITRATION
Each master device must monitor the bus for Start and
Stop bits. If the device detects that the bus is busy, it
cannot begin a new message until the bus returns to an
Idle state.
However, two master devices may try to initiate a trans-
mission on or about the same time. When this occurs,
the process of arbitration begins. Each transmitter
checks the level of the SDA data line and compares it
to the level that it expects to find. The first transmitter to
observe that the two levels do not match, loses arbitra-
tion, and must stop transmitting on the SDA line.
For example, if one transmitter holds the SDA line to a
logical one (lets it float) and a second transmitter holds
it to a logical zero (pulls it low), the result is that the
SDA line will be low. The first transmitter then observes
that the level of the line is different than expected and
concludes that another transmitter is communicating.
The first transmitter to notice this difference is the one
that loses arbitration and must stop driving the SDA
line. If this transmitter is also a master device, it also
must stop driving the SCL line. It then can monitor the
lines for a Stop condition before trying to reissue its
transmission. In the meantime, the other device that
has not noticed any difference between the expected
and actual levels on the SDA line continues with its
original transmission. It can do so without any compli-
cations, because so far, the transmission appears
exactly as expected with no other transmitter disturbing
the message.
Slave Transmit mode can also be arbitrated, when a
master addresses multiple slaves, but this is less
common.
If two master devices are sending a message to two
different slave devices at the address stage, the master
sending the lower slave address always wins arbitra-
tion. When two master devices send messages to the
same slave address, and addresses can sometimes
refer to multiple slaves, the arbitration process must
continue into the data stage.
Arbitration usually occurs very rarely, but it is a
necessary process for proper multi-master support.
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32.4 I2C MODE OPERATION
All MSSP I2C communication is byte oriented and
shifted out MSb first. Six SFR registers and two
interrupt flags interface the module with the PIC®
microcontroller and user software. Two pins, SDA and
SCL, are exercised by the module to communicate
with other external I2C devices.
32.4.1 BYTE FORMAT
All communication in I2C is done in 9-bit segments. A
byte is sent from a master to a slave or vice-versa, fol-
lowed by an Acknowledge bit sent back. After the
eighth falling edge of the SCL line, the device output-
ting data on the SDA changes that pin to an input and
reads in an acknowledge value on the next clock
pulse.
The clock signal, SCL, is provided by the master. Data
is valid to change while the SCL signal is low, and
sampled on the rising edge of the clock. Changes on
the SDA line while the SCL line is high define special
conditions on the bus, explained below.
32.4.2 DEFINITION OF I2C TERMINOLOGY
There is language and terminology in the description
of I2C communication that have definitions specific to
I2C. That word usage is defined below and may be
used in the rest of this document without explanation.
This table was adapted from the Philips I2C
specification.
32.4.3 SDA AND SCL PINS
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain. These
pins should be set by the user to inputs by setting the
appropriate TRIS bits.
32.4.4 SDA HOLD TIME
The hold time of the SDA pin is selected by the SDAHT
bit of the SSPxCON3 register. Hold time is the time
SDA is held valid after the falling edge of SCL. Setting
the SDAHT bit selects a longer 300 ns minimum hold
time and may help on buses with large capacitance.
TABLE 32-2: I2C BUS TERMS
Note 1: Data is tied to output zero when an I2C
mode is enabled.
2: Any device pin can be selected for SDA
and SCL functions with the PPS peripheral.
These functions are bidirectional. The SDA
input is selected with the SSPDATPPS
registers. The SCL input is selected with
the SSPCLKPPS registers. Outputs are
selected with the RxyPPS registers. It is the
user’s responsibility to make the selections
so that both the input and the output for
each function is on the same pin.
TERM Description
Transmitter The device which shifts data out
onto the bus.
Receiver The device which shifts data in
from the bus.
Master The device that initiates a transfer,
generates clock signals and termi-
nates a transfer.
Slave The device addressed by the
master.
Multi-master A bus with more than one device
that can initiate data transfers.
Arbitration Procedure to ensure that only one
master at a time controls the bus.
Winning arbitration ensures that
the message is not corrupted.
Synchronization Procedure to synchronize the
clocks of two or more devices on
the bus.
Idle No master is controlling the bus,
and both SDA and SCL lines are
high.
Active Any time one or more master
devices are controlling the bus.
Addressed
Slave
Slave device that has received a
matching address and is actively
being clocked by a master.
Matching
Address
Address byte that is clocked into a
slave that matches the value
stored in SSPxADD.
Write Request Slave receives a matching
address with R/W bit clear, and is
ready to clock in data.
Read Request Master sends an address byte with
the R/W bit set, indicating that it
wishes to clock data out of the
Slave. This data is the next and all
following bytes until a Restart or
Stop.
Clock Stretching When a device on the bus hold
SCL low to stall communication.
Bus Collision Any time the SDA line is sampled
low by the module while it is out-
putting and expected high state.
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32.4.5 START CONDITION
The I2C specification defines a Start condition as a
transition of SDA from a high to a low state while SCL
line is high. A Start condition is always generated by
the master and signifies the transition of the bus from
an Idle to an Active state. Figure 32-12 shows wave
forms for Start and Stop conditions.
A bus collision can occur on a Start condition if the
module samples the SDA line low before asserting it
low. This does not conform to the I2C Specification that
states no bus collision can occur on a Start.
32.4.6 STOP CONDITION
A Stop condition is a transition of the SDA line from
low-to-high state while the SCL line is high.
32.4.7 RESTART CONDITION
A Restart is valid any time that a Stop would be valid.
A master can issue a Restart if it wishes to hold the
bus after terminating the current transfer. A Restart
has the same effect on the slave that a Start would,
resetting all slave logic and preparing it to clock in an
address. The master may want to address the same or
another slave. Figure 32-13 shows the wave form for a
Restart condition.
In 10-bit Addressing Slave mode a Restart is required
for the master to clock data out of the addressed
slave. Once a slave has been fully addressed, match-
ing both high and low address bytes, the master can
issue a Restart and the high address byte with the
R/W bit set. The slave logic will then hold the clock
and prepare to clock out data.
After a full match with R/W clear in 10-bit mode, a prior
match flag is set and maintained until a Stop condition, a
high address with R/W clear, or high address match fails.
32.4.8 START/STOP CONDITION
INTERRUPT MASKING
The SCIE and PCIE bits of the SSPxCON3 register
can enable the generation of an interrupt in Slave
modes that do not typically support this function. Slave
modes where interrupt on Start and Stop detect are
already enabled, these bits will have no effect.
FIGURE 32-12 : I2C START AND STOP CONDITIONS
FIGURE 32-13 : I2C RESTART CONDITION
Note: At least one SCL low time must appear
before a Stop is valid, therefore, if the SDA
line goes low then high again while the SCL
line stays high, only the Start condition is
detected.
SDA
SCL
P
Stop
Condition
S
Start
Condition
Change of
Data Allowed
Change of
Data Allowed
Restart
Condition
Sr
Change of
Data Allowed
Change of
Data Allowed
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32.4.9 ACKNOWLEDGE SEQUENCE
The ninth SCL pulse for any transferred byte in I2C is
dedicated as an Acknowledge. It allows receiving
devices to respond back to the transmitter by pulling
the SDA line low. The transmitter must release control
of the line during this time to shift in the response. The
Acknowledge (ACK) is an active-low signal, pulling the
SDA line low indicates to the transmitter that the
device has received the transmitted data and is ready
to receive more.
The result of an ACK is placed in the ACKSTAT bit of
the SSPxCON2 register.
Slave software, when the AHEN and DHEN bits are
set, allow the user to set the ACK value sent back to
the transmitter. The ACKDT bit of the SSPxCON2 reg-
ister is set/cleared to determine the response.
Slave hardware will generate an ACK response if the
AHEN and DHEN bits of the SSPxCON3 register are
clear.
There are certain conditions where an ACK will not be
sent by the slave. If the BF bit of the SSPxSTAT regis-
ter or the SSPOV bit of the SSPxCON1 register are
set when a byte is received.
When the module is addressed, after the eighth falling
edge of SCL on the bus, the ACKTIM bit of the
SSPxCON3 register is set. The ACKTIM bit indicates
the acknowledge time of the active bus. The ACKTIM
Status bit is only active when the AHEN bit or DHEN
bit is enabled.
32.5 I2C SLAVE MODE OPERATION
The MSSP Slave mode operates in one of four modes
selected by the SSPM bits of SSPxCON1 register. The
modes can be divided into 7-bit and 10-bit Addressing
mode. 10-bit Addressing modes operate the same as
7-bit with some additional overhead for handling the
larger addresses.
Modes with Start and Stop bit interrupts operate the
same as the other modes with SSPxIF additionally
getting set upon detection of a Start, Restart, or Stop
condition.
32.5.1 SLAVE MODE ADDRESSES
The SSPxADD register (Register 32-6) contains the
Slave mode address. The first byte received after a
Start or Restart condition is compared against the
value stored in this register. If the byte matches, the
value is loaded into the SSPxBUF register and an
interrupt is generated. If the value does not match, the
module goes idle and no indication is given to the
software that anything happened.
The SSP Mask register (Register 32-5) affects the
address matching process. See Section 32.5.8 “SSP
Mask Register” for more information.
32.5.1.1 I2C Slave 7-bit Addressing Mode
In 7-bit Addressing mode, the LSb of the received data
byte is ignored when determining if there is an address
match.
32.5.1.2 I2C Slave 10-bit Addressing Mode
In 10-bit Addressing mode, the first received byte is
compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9
and A8 are the two MSb’s of the 10-bit address and
stored in bits 2 and 1 of the SSPxADD register.
After the acknowledge of the high byte the UA bit is set
and SCL is held low until the user updates SSPxADD
with the low address. The low address byte is clocked
in and all eight bits are compared to the low address
value in SSPxADD. Even if there is not an address
match; SSPxIF and UA are set, and SCL is held low
until SSPxADD is updated to receive a high byte
again. When SSPxADD is updated the UA bit is
cleared. This ensures the module is ready to receive
the high address byte on the next communication.
A high and low address match as a write request is
required at the start of all 10-bit addressing communi-
cation. A transmission can be initiated by issuing a
Restart once the slave is addressed, and clocking in
the high address with the R/W bit set. The slave
hardware will then acknowledge the read request and
prepare to clock out data. This is only valid for a slave
after it has received a complete high and low address
byte match.
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32.5.2 SLAVE RECEPTION
When the R/W bit of a matching received address byte
is clear, the R/W bit of the SSPxSTAT register is
cleared. The received address is loaded into the
SSPxBUF register and acknowledged.
When the overflow condition exists for a received
address, then not Acknowledge is given. An overflow
condition is defined as either bit BF of the SSPxSTAT
register is set, or bit SSPOV of the SSPxCON1 register
is set. The BOEN bit of the SSPxCON3 register modi-
fies this operation. For more information see
Register 32-4.
An MSSP interrupt is generated for each transferred
data byte. Flag bit, SSPxIF, must be cleared by soft-
ware.
When the SEN bit of the SSPxCON2 register is set,
SCL will be held low (clock stretch) following each
received byte. The clock must be released by setting
the CKP bit of the SSPxCON1 register, except
sometimes in 10-bit mode. See Section 32.5.6.2
“10-bit Addressing Mode” for more detail.
32.5.2.1 7-bit Addressing Reception
This section describes a standard sequence of events
for the MSSP module configured as an I2C slave in
7-bit Addressing mode. Figure 32-14 and Figure 32-15
is used as a visual reference for this description.
This is a step by step process of what typically must
be done to accomplish I2C communication.
1. Start bit detected.
2. S bit of SSPxSTAT is set; SSPxIF is set if inter-
rupt on Start detect is enabled.
3. Matching address with R/W bit clear is received.
4. The slave pulls SDA low sending an ACK to the
master, and sets SSPxIF bit.
5. Software clears the SSPxIF bit.
6. Software reads received address from
SSPxBUF clearing the BF flag.
7. If SEN = 1; Slave software sets CKP bit to
release the SCL line.
8. The master clocks out a data byte.
9. Slave drives SDA low sending an ACK to the
master, and sets SSPxIF bit.
10. Software clears SSPxIF.
11. Software reads the received byte from
SSPxBUF clearing BF.
12. Steps 8-12 are repeated for all received bytes
from the master.
13. Master sends Stop condition, setting P bit of
SSPxSTAT, and the bus goes idle.
32.5.2.2 7-bit Reception with AHEN and
DHEN
Slave device reception with AHEN and DHEN set
operate the same as without these options with extra
interrupts and clock stretching added after the eighth
falling edge of SCL. These additional interrupts allow
the slave software to decide whether it wants to ACK
the receive address or data byte, rather than the hard-
ware. This functionality adds support for PMBus™ that
was not present on previous versions of this module.
This list describes the steps that need to be taken by
slave software to use these options for I2C communi-
cation. Figure 32-16 displays a module using both
address and data holding. Figure 32-17 includes the
operation with the SEN bit of the SSPxCON2 register
set.
1. S bit of SSPxSTAT is set; SSPxIF is set if inter-
rupt on Start detect is enabled.
2. Matching address with R/W bit clear is clocked
in. SSPxIF is set and CKP cleared after the
eighth falling edge of SCL.
3. Slave clears the SSPxIF.
4. Slave can look at the ACKTIM bit of the
SSPxCON3 register to determine if the SSPxIF
was after or before the ACK.
5. Slave reads the address value from SSPxBUF,
clearing the BF flag.
6. Slave sets ACK value clocked out to the master
by setting ACKDT.
7. Slave releases the clock by setting CKP.
8. SSPxIF is set after an ACK, not after a NACK.
9. If SEN = 1 the slave hardware will stretch the
clock after the ACK.
10. Slave clears SSPxIF.
11. SSPxIF set and CKP cleared after eighth falling
edge of SCL for a received data byte.
12. Slave looks at ACKTIM bit of SSPxCON3 to
determine the source of the interrupt.
13. Slave reads the received data from SSPxBUF
clearing BF.
14. Steps 7-14 are the same for each received data
byte.
15. Communication is ended by either the slave
sending an ACK =1, or the master sending a
Stop condition. If a Stop is sent and interrupt on
Stop detect is disabled, the slave will only know
by polling the P bit of the SSTSTAT register.
Note: SSPxIF is still set after the ninth falling edge
of SCL even if there is no clock stretching
and BF has been cleared. Only if NACK is
sent to master is SSPxIF not set
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FIGURE 32-14 : I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
Receiving Address
ACK
Receiving Data
ACK
Receiving Data ACK =1
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDA
SCL
SSPxIF
BF
SSPOV
12345678 12345678 12345678
999
ACK is not sent.
SSPOV set because
SSPxBUF is still full.
Cleared by software
First byte
of data is
available
in SSPxBUF
SSPxBUF is read
SSPxIF set on 9th
falling edge of
SCL
Cleared by software
P
Bus Master sends
Stop condition
S
From Slave to Master
2015-2016 Microchip Technology Inc. DS40001819B-page 459
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FIGURE 32-15 : I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
SEN SEN
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDA
SCL 123456789 123456789 123456789 P
SSPxIF set on 9th
SCL is not held
CKP is written to ‘1’ in software,
CKP is written to ‘1’ in software,
ACK
low because
falling edge of SCL
releasing SCL
ACK is not sent.
Bus Master sends
CKP
SSPOV
BF
SSPxIF
SSPOV set because
SSPxBUF is still full.
Cleared by software
First byte
of data is
available
in SSPxBUF
ACK=1
Cleared by software
SSPxBUF is read
Clock is held low until CKP is set to ‘1’
releasing SCL
Stop condition
S
ACK
ACK
Receive Address Receive Data Receive Data
R/W=0
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FIGURE 32-16 : I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
Receiving Address Receiving Data Received Data
P
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDA
SCL
BF
CKP
S
P
12 3 456 7 8 912345 67 8 912345678
Master sends
Stop condition
S
Data is read from SSPxBUF
Cleared by software
SSPxIF is set on
9th falling edge of
SCL, after ACK
CKP set by software,
SCL is released
Slave software
9
ACKTIM cleared by
hardware in 9th
rising edge of SCL
sets ACKDT to
not ACK
When DHEN=1:
CKP is cleared by
hardware on 8th falling
edge of SCL
Slave software
clears ACKDT to
ACK the received
byte
ACKTIM set by hardware
on 8th falling edge of SCL
When AHEN=1:
CKP is cleared by hardware
and SCL is stretched
Address is
read from
SSBUF
ACKTIM set by hardware
on 8th falling edge of SCL
ACK
Master Releases SDA
to slave for ACK sequence
No interrupt
after not ACK
from Slave
ACK=1
ACK
ACKDT
ACKTIM
SSPxIF
If AHEN = 1:
SSPxIF is set
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FIGURE 32-17 : I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)
Receiving Address Receive Data Receive Data
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDA
SCL
SSPxIF
BF
ACKDT
CKP
S
P
ACK
S12
345678 912
34567 8 9 1234 5 67 8 9
ACK
ACK
Cleared by software
ACKTIM is cleared by hardware
SSPxBUF can be
Set by software,
read any time before
next byte is loaded
release SCL
on 9th rising edge of SCL
Received
address is loaded into
SSPxBUF
Slave software clears
ACKDT to ACK
R/W = 0Master releases
SDA to slave for ACK sequence
the received byte
When AHEN = 1;
on the 8th falling edge
of SCL of an address
byte, CKP is cleared
ACKTIM is set by hardware
on 8th falling edge of SCL
When DHEN = 1;
on the 8th falling edge
of SCL of a received
data byte, CKP is cleared
Received data is
available on SSPxBUF
Slave sends
not ACK
CKP is not cleared
if not ACK
P
Master sends
Stop condition
No interrupt after
if not ACK
from Slave
ACKTIM
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32.5.3 SLAVE TRANSMISSION
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPxSTAT register is set. The received address is
loaded into the SSPxBUF register, and an ACK pulse is
sent by the slave on the ninth bit.
Following the ACK, slave hardware clears the CKP bit
and the SCL pin is held low (see Section 32.5.6
“Clock Stretching” for more detail). By stretching the
clock, the master will be unable to assert another clock
pulse until the slave is done preparing the transmit
data.
The transmit data must be loaded into the SSPxBUF
register which also loads the SSPSR register. Then the
SCL pin should be released by setting the CKP bit of
the SSPxCON1 register. The eight data bits are shifted
out on the falling edge of the SCL input. This ensures
that the SDA signal is valid during the SCL high time.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. This ACK
value is copied to the ACKSTAT bit of the SSPxCON2
register. If ACKSTAT is set (not ACK), then the data
transfer is complete. In this case, when the not ACK is
latched by the slave, the slave goes idle and waits for
another occurrence of the Start bit. If the SDA line was
low (ACK), the next transmit data must be loaded into
the SSPxBUF register. Again, the SCL pin must be
released by setting bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPxIF bit must be cleared by software and
the SSPxSTAT register is used to determine the status
of the byte. The SSPxIF bit is set on the falling edge of
the ninth clock pulse.
32.5.3.1 Slave Mode Bus Collision
A slave receives a Read request and begins shifting
data out on the SDA line. If a bus collision is detected
and the SBCDE bit of the SSPxCON3 register is set,
the BCLIF bit of the PIR register is set. Once a bus col-
lision is detected, the slave goes idle and waits to be
addressed again. User software can use the BCLIF bit
to handle a slave bus collision.
32.5.3.2 7-bit Transmission
A master device can transmit a read request to a
slave, and then clock data out of the slave. The list
below outlines what software for a slave will need to
do to accomplish a standard transmission.
Figure 32-18 can be used as a reference to this list.
1. Master sends a Start condition on SDA and
SCL.
2. S bit of SSPxSTAT is set; SSPxIF is set if inter-
rupt on Start detect is enabled.
3. Matching address with R/W bit set is received by
the Slave setting SSPxIF bit.
4. Slave hardware generates an ACK and sets
SSPxIF.
5. SSPxIF bit is cleared by user.
6. Software reads the received address from
SSPxBUF, clearing BF.
7. R/W is set so CKP was automatically cleared
after the ACK.
8. The slave software loads the transmit data into
SSPxBUF.
9. CKP bit is set releasing SCL, allowing the
master to clock the data out of the slave.
10. SSPxIF is set after the ACK response from the
master is loaded into the ACKSTAT register.
11. SSPxIF bit is cleared.
12. The slave software checks the ACKSTAT bit to
see if the master wants to clock out more data.
13. Steps 9-13 are repeated for each transmitted
byte.
14. If the master sends a not ACK; the clock is not
held, but SSPxIF is still set.
15. The master sends a Restart condition or a Stop.
16. The slave is no longer addressed.
Note 1: If the master ACKs the clock will be
stretched.
2: ACKSTAT is the only bit updated on the
rising edge of SCL (9th) rather than the
falling.
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FIGURE 32-18 : I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)
Receiving Address Automatic Transmitting Data Automatic Transmitting Data
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SDA
SCL
SSPxIF
BF
CKP
ACKSTAT
R/W
D/A
S
P
Received address
When R/W is set
R/W is copied from the
Indicates an address
is read from SSPxBUF
SCL is always
held low after 9th SCL
falling edge
matching address byte
has been received
Masters not ACK
is copied to
ACKSTAT
CKP is not
held for not
ACK
BF is automatically
cleared after 8th falling
edge of SCL
Data to transmit is
loaded into SSPxBUF
Set by software
Cleared by software
ACK
ACK
ACK
R/W =1
SP
Master sends
Stop condition
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32.5.3.3 7-bit Transmission with Address
Hold Enabled
Setting the AHEN bit of the SSPxCON3 register
enables additional clock stretching and interrupt
generation after the eighth falling edge of a received
matching address. Once a matching address has
been clocked in, CKP is cleared and the SSPxIF
interrupt is set.
Figure 32-19 displays a standard waveform of a 7-bit
address slave transmission with AHEN enabled.
1. Bus starts Idle.
2. Master sends Start condition; the S bit of
SSPxSTAT is set; SSPxIF is set if interrupt on
Start detect is enabled.
3. Master sends matching address with R/W bit
set. After the eighth falling edge of the SCL line
the CKP bit is cleared and SSPxIF interrupt is
generated.
4. Slave software clears SSPxIF.
5. Slave software reads ACKTIM bit of the
SSPxCON3 register, and R/W and D/A of the
SSPxSTAT register to determine the source of
the interrupt.
6. Slave reads the address value from the
SSPxBUF register clearing the BF bit.
7. Slave software decides from this information if it
wishes to ACK or not ACK and sets the ACKDT
bit of the SSPxCON2 register accordingly.
8. Slave sets the CKP bit releasing SCL.
9. Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit
and sets SSPxIF after the ACK if the R/W bit is
set.
11. Slave software clears SSPxIF.
12. Slave loads value to transmit to the master into
SSPxBUF setting the BF bit.
13. Slave sets the CKP bit releasing the clock.
14. Master clocks out the data from the slave and
sends an ACK value on the ninth SCL pulse.
15. Slave hardware copies the ACK value into the
ACKSTAT bit of the SSPxCON2 register.
16. Steps 10-15 are repeated for each byte transmit-
ted to the master from the slave.
17. If the master sends a not ACK the slave
releases the bus allowing the master to send a
Stop and end the communication.
Note: SSPxBUF cannot be loaded until after the
ACK.
Note: Master must send a not ACK on the last
byte to ensure that the slave releases the
SCL line to receive a Stop.
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FIGURE 32-19 : I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)
Receiving Address Automatic Transmitting Data Automatic Transmitting Data
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SDA
SCL
SSPxIF
BF
ACKDT
ACKSTAT
CKP
R/W
D/A
Received address
is read from SSPxBUF
BF is automatically
cleared after 8th falling
edge of SCL
Data to transmit is
loaded into SSPxBUF
Cleared by software
Slave clears
ACKDT to ACK
address
Master’s ACK
response is copied
to SSPxSTAT
CKP not cleared
after not ACK
Set by software,
releases SCL
ACKTIM is cleared
on 9th rising edge of SCL
ACKTIM is set on 8th falling
edge of SCL
When AHEN = 1;
CKP is cleared by hardware
after receiving matching
address.
When R/W = 1;
CKP is always
cleared after ACK
SP
Master sends
Stop condition
ACK
R/W =1
Master releases SDA
to slave for ACK sequence
ACK ACK
ACKTIM
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32.5.4 SLAVE MODE 10-BIT ADDRESS
RECEPTION
This section describes a standard sequence of events
for the MSSP module configured as an I2C slave in
10-bit Addressing mode.
Figure 32-20 is used as a visual reference for this
description.
This is a step by step process of what must be done by
slave software to accomplish I2C communication.
1. Bus starts Idle.
2. Master sends Start condition; S bit of SSPxSTAT
is set; SSPxIF is set if Interrupt on Start detect is
enabled.
3. Master sends matching high address with R/W
bit clear; UA bit of the SSPxSTAT register is set.
4. Slave sends ACK and SSPxIF is set.
5. Software clears the SSPxIF bit.
6. Software reads received address from
SSPxBUF clearing the BF flag.
7. Slave loads low address into SSPxADD,
releasing SCL.
8. Master sends matching low address byte to the
slave; UA bit is set.
9. Slave sends ACK and SSPxIF is set.
10. Slave clears SSPxIF.
11. Slave reads the received matching address
from SSPxBUF clearing BF.
12. Slave loads high address into SSPxADD.
13. Master clocks a data byte to the slave and
clocks out the slaves ACK on the ninth SCL
pulse; SSPxIF is set.
14. If SEN bit of SSPxCON2 is set, CKP is cleared
by hardware and the clock is stretched.
15. Slave clears SSPxIF.
16. Slave reads the received byte from SSPxBUF
clearing BF.
17. If SEN is set the slave sets CKP to release the
SCL.
18. Steps 13-17 repeat for each received byte.
19. Master sends Stop to end the transmission.
32.5.5 10-BIT ADDRESSING WITH
ADDRESS OR DATA HOLD
Reception using 10-bit addressing with AHEN or
DHEN set is the same as with 7-bit modes. The only
difference is the need to update the SSPxADD register
using the UA bit. All functionality, specifically when the
CKP bit is cleared and SCL line is held low are the
same. Figure 32-21 can be used as a reference of a
slave in 10-bit addressing with AHEN set.
Figure 32-22 shows a standard waveform for a slave
transmitter in 10-bit Addressing mode.
Note: Updates to the SSPxADD register are not
allowed until after the ACK sequence.
Note: If the low address does not match, SSPxIF
and UA are still set so that the slave soft-
ware can set SSPxADD back to the high
address. BF is not set because there is no
match. CKP is unaffected.
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FIGURE 32-20 : I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
SSPxIF
Receive First Address Byte
ACK
Receive Second Address Byte
ACK
Receive Data
ACK
Receive Data
ACK
11110
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDA
SCL
UA
CKP
12345678912345678
9 123456789123456789P
Master sends
Stop condition
Cleared by software
Receive address is
Software updates SSPxADD
Data is read
SCL is held low
Set by software,
while CKP =
0
from SSPxBUF
releasing SCL
When SEN =
1
;
CKP is cleared after
9th falling edge of received byte
read from SSPxBUF
and releases SCL
When UA =
1
;
If address matches
Set by hardware
on 9th falling edge
SSPxADD it is loaded into
SSPxBUF
SCL is held low
S
BF
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FIGURE 32-21 : I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)
Receive First Address Byte
UA
Receive Second Address Byte
UA
Receive Data
ACK
Receive Data
1 1 1 1 0
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5
SDA
SCL
SSPxIF
BF
ACKDT
UA
CKP
ACKTIM
12345678 9
S
ACK
ACK
12345678 9123456 78 91
2
SSPxBUF
is read from
Received data
SSPxBUF can be
read anytime before
the next received byte
Cleared by software
falling edge of SCL
not allowed until 9th
Update to SSPxADD is
Set CKP with software
releases SCL
SCL
clears UA and releases
Update of SSPxADD,
Set by hardware
on 9th falling edge
Slave software clears
ACKDT to
ACK
the received byte
If when AHEN =
1
;
on the 8th falling edge
of SCL of an address
byte, CKP is cleared
ACKTIM is set by hardware
on 8th falling edge of SCL
Cleared by software
R/
W =
0
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FIGURE 32-22 : I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)
Receiving Address
ACK
Receiving Second Address Byte
Sr
Receive First Address Byte
ACK
Transmitting Data Byte
1 1 1 1 0
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 1 0
A9 A8 D7 D6 D5 D4 D3 D2 D1 D0
SDA
SCL
SSPxIF
BF
UA
CKP
R/W
D/A
123456789 123456789 123456789 123456789
ACK = 1
P
Master sends
Stop condition
Master sends
not ACK
Master sends
Restart event
ACK
R/W = 0
S
Cleared by software
After SSPxADD is
updated, UA is cleared
and SCL is released
High address is loaded
Received address is Data to transmit is
Set by software
Indicates an address
When R/W = 1;
R/W is copied from the
Set by hardware
UA indicates SSPxADD
SSPxBUF loaded
with received address
must be updated
has been received
loaded into SSPxBUF
releases SCL
Masters not ACK
is copied
matching address byte
CKP is cleared on
9th falling edge of SCL
read from SSPxBUF
back into SSPxADD
ACKSTAT
Set by hardware
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32.5.6 CLOCK STRETCHING
Clock stretching occurs when a device on the bus
holds the SCL line low, effectively pausing communi-
cation. The slave may stretch the clock to allow more
time to handle data or prepare a response for the
master device. A master device is not concerned with
stretching as anytime it is active on the bus and not
transferring data it is stretching. Any stretching done
by a slave is invisible to the master software and
handled by the hardware that generates SCL.
The CKP bit of the SSPxCON1 register is used to
control stretching in software. Any time the CKP bit is
cleared, the module will wait for the SCL line to go low
and then hold it. Setting CKP will release SCL and
allow more communication.
32.5.6.1 Normal Clock Stretching
Following an ACK if the R/W bit of SSPxSTAT is set, a
read request, the slave hardware will clear CKP. This
allows the slave time to update SSPxBUF with data to
transfer to the master. If the SEN bit of SSPxCON2 is
set, the slave hardware will always stretch the clock
after the ACK sequence. Once the slave is ready; CKP
is set by software and communication resumes.
32.5.6.2 10-bit Addressing Mode
In 10-bit Addressing mode, when the UA bit is set the
clock is always stretched. This is the only time the SCL
is stretched without CKP being cleared. SCL is
released immediately after a write to SSPxADD.
32.5.6.3 Byte NACKing
When AHEN bit of SSPxCON3 is set; CKP is cleared
by hardware after the eighth falling edge of SCL for a
received matching address byte. When DHEN bit of
SSPxCON3 is set; CKP is cleared after the eighth fall-
ing edge of SCL for received data.
Stretching after the eighth falling edge of SCL allows
the slave to look at the received address or data and
decide if it wants to ACK the received data.
32.5.6.4 Clock Synchronization and
the CKP Bit
Any time the CKP bit is cleared, the module will wait
for the SCL line to go low and then hold it. However,
clearing the CKP bit will not assert the SCL output low
until the SCL output is already sampled low. There-
fore, the CKP bit will not assert the SCL line until an
external I2C master device has already asserted the
SCL line. The SCL output will remain low until the CKP
bit is set and all other devices on the I2C bus have
released SCL. This ensures that a write to the CKP bit
will not violate the minimum high time requirement for
SCL (see Figure 32-23).
FIGURE 32-23: CLOCK SYNCHRONIZATION TIMING
Note 1: The BF bit has no effect on if the clock will
be stretched or not. This is different than
previous versions of the module that
would not stretch the clock, clear CKP, if
SSPxBUF was read before the ninth fall-
ing edge of SCL.
2: Previous versions of the module did not
stretch the clock for a transmission if
SSPxBUF was loaded before the ninth
falling edge of SCL. It is now always
cleared for read requests.
Note: Previous versions of the module did not
stretch the clock if the second address byte
did not match.
SDA
SCL
DX ‚ – 1DX
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPxCON1
CKP
Master device
releases clock
Master device
asserts clock
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32.5.7 GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually deter-
mines which device will be the slave addressed by the
master device. The exception is the general call
address which can address all devices. When this
address is used, all devices should, in theory, respond
with an acknowledge.
The general call address is a reserved address in the
I2C protocol, defined as address 0x00. When the
GCEN bit of the SSPxCON2 register is set, the slave
module will automatically ACK the reception of this
address regardless of the value stored in SSPxADD.
After the slave clocks in an address of all zeros with
the R/W bit clear, an interrupt is generated and slave
software can read SSPxBUF and respond.
Figure 32-24 shows a general call reception
sequence.
In 10-bit Address mode, the UA bit will not be set on
the reception of the general call address. The slave
will prepare to receive the second byte as data, just as
it would in 7-bit mode.
If the AHEN bit of the SSPxCON3 register is set, just
as with any other address reception, the slave hard-
ware will stretch the clock after the eighth falling edge
of SCL. The slave must then set its ACKDT value and
release the clock with communication progressing as it
would normally.
32.5.8 SSP MASK REGISTER
An SSP Mask (SSPxMSK) register (Register 32-5) is
available in I2C Slave mode as a mask for the value
held in the SSPSR register during an address
comparison operation. A zero (‘0’) bit in the SSPxMSK
register has the effect of making the corresponding bit
of the received address a “don’t care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
10-bit Address mode: address compare of A<7:0>
only. The SSP mask has no effect during the reception
of the first (high) byte of the address.
FIGURE 32-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
SDA
SCL
S
SSPxIF
BF (SSPxSTAT<0>)
Cleared by software
SSPxBUF is read
R/W = 0
ACK
General Call Address
Address is compared to General Call Address
Receiving Data ACK
123456789123456789
D7 D6 D5 D4 D3 D2 D1 D0
after ACK, set interrupt
GCEN (SSPxCON2<7>)
’1’
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32.6 I2C Master Mode
Master mode is enabled by setting and clearing the
appropriate SSPM bits in the SSPxCON1 register and
by setting the SSPEN bit. In Master mode, the SDA and
SCK pins must be configured as inputs. The MSSP
peripheral hardware will override the output driver TRIS
controls when necessary to drive the pins low.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I2C bus may be taken when the P bit is
set, or the bus is Idle.
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit condition detection. Start and Stop condition
detection is the only active circuitry in this mode. All
other communication is done by the user software
directly manipulating the SDA and SCL lines.
The following events will cause the SSP Interrupt Flag
bit, SSPxIF, to be set (SSP interrupt, if enabled):
• Start condition detected
• Stop condition detected
• Data transfer byte transmitted/received
• Acknowledge transmitted/received
• Repeated Start generated
32.6.1 I2C MASTER MODE OPERATION
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted eight bits at a time. After each byte is
transmitted, an Acknowledge bit is received. Start and
Stop conditions are output to indicate the beginning
and the end of a serial transfer.
In Master Receive mode, the first byte transmitted
contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received eight bits at a time.
After each byte is received, an Acknowledge bit is
transmitted. Start and Stop conditions indicate the
beginning and end of transmission.
A Baud Rate Generator is used to set the clock
frequency output on SCL. See Section 32.7 “Baud
Rate Generator” for more detail.
Note 1: The MSSP module, when configured in
I2C Master mode, does not allow queuing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register
to initiate transmission before the Start
condition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a
write to the SSPxBUF did not occur
2: Master mode suspends Start/Stop
detection when sending the Start/Stop
condition by means of the SEN/PEN
control bits. The SSPxIF bit is set at the
end of the Start/Stop generation when
hardware clears the control bit.
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32.6.2 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
releases the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the Baud Rate
Generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPxADD<7:0> and begins count-
ing. This ensures that the SCL high time will always be
at least one BRG rollover count in the event that the
clock is held low by an external device (Figure 32-25).
FIGURE 32-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
32.6.3 WCOL STATUS FLAG
If the user writes the SSPxBUF when a Start, Restart,
Stop, Receive or Transmit sequence is in progress, the
WCOL bit is set and the contents of the buffer are
unchanged (the write does not occur). Any time the
WCOL bit is set it indicates that an action on SSPxBUF
was attempted while the module was not idle.
SDA
SCL
SCL deasserted but slave holds
DX ‚ – 1DX
BRG
SCL is sampled high, reload takes
place and BRG starts its count
03h 02h 01h 00h (hold off) 03h 02h
Reload
BRG
Value
SCL low (clock arbitration)
SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
Note: Because queuing of events is not allowed,
writing to the lower five bits of SSPxCON2
is disabled until the Start condition is
complete.
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32.6.4 I2C MASTER MODE START
CONDITION TIMING
To initiate a Start condition (Figure 32-26), the user
sets the Start Enable bit, SEN bit of the SSPxCON2
register. If the SDA and SCL pins are sampled high,
the Baud Rate Generator is reloaded with the contents
of SSPxADD<7:0> and starts its count. If SCL and
SDA are both sampled high when the Baud Rate Gen-
erator times out (TBRG), the SDA pin is driven low. The
action of the SDA being driven low while SCL is high is
the Start condition and causes the S bit of the
SSPxSTAT1 register to be set. Following this, the
Baud Rate Generator is reloaded with the contents of
SSPxADD<7:0> and resumes its count. When the
Baud Rate Generator times out (TBRG), the SEN bit of
the SSPxCON2 register will be automatically cleared
by hardware; the Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
FIGURE 32-26: FIRST START BIT TIMING
Note 1: If at the beginning of the Start condition,
the SDA and SCL pins are already
sampled low, or if during the Start condi-
tion, the SCL line is sampled low before
the SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCLIF, is set, the Start condition is
aborted and the I2C module is reset into
its Idle state.
2: The Philips I2C specification states that a
bus collision cannot occur on a Start.
SDA
SCL
S
TBRG
1st bit 2nd bit
TBRG
SDA = 1, At completion of Start bit,
SCL = 1
Write to SSPxBUF occurs here
TBRG
hardware clears SEN bit
TBRG
Write to SEN bit occurs here Set S bit (SSPxSTAT<3>)
and sets SSPxIF bit
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32.6.5 I2C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated Start condition (Figure 32-27) occurs when
the RSEN bit of the SSPxCON2 register is pro-
grammed high and the master state machine is no lon-
ger active. When the RSEN bit is set, the SCL pin is
asserted low. When the SCL pin is sampled low, the
Baud Rate Generator is loaded and begins counting.
The SDA pin is released (brought high) for one Baud
Rate Generator count (TBRG). When the Baud Rate
Generator times out, if SDA is sampled high, the SCL
pin will be deasserted (brought high). When SCL is
sampled high, the Baud Rate Generator is reloaded
and begins counting. SDA and SCL must be sampled
high for one TBRG. This action is then followed by
assertion of the SDA pin (SDA = 0) for one TBRG while
SCL is high. SCL is asserted low. Following this, the
RSEN bit of the SSPxCON2 register will be automati-
cally cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit of the SSPxSTAT register will be set. The
SSPxIF bit will not be set until the Baud Rate Generator
has timed out.
FIGURE 32-27: REPEATED START CO NDITION WAVE FORM
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL
goes from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate
that another master is attempting
to transmit a data ‘1’.
SDA
SCL
Repeated Start
Write to SSPxCON2
Write to SSPxBUF occurs here
At completion of Start bit,
hardware clears RSEN bit
1st bit
S bit set by hardware
TBRG
TBRG
SDA = 1,SDA = 1,
SCL (no change) SCL = 1
occurs here
TBRG TBRG TBRG
and sets SSPxIF
Sr
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32.6.6 I2C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPxBUF register. This action will
set the Buffer Full flag bit, BF, and allow the Baud Rate
Generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted. SCL is held low for one Baud Rate Generator
rollover count (TBRG). Data should be valid before SCL
is released high. When the SCL pin is released high, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred, or if data was received prop-
erly. The status of ACK is written into the ACKSTAT bit
on the rising edge of the ninth clock. If the master
receives an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSPxIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPxBUF, leaving SCL low and SDA
unchanged (Figure 32-28).
After the write to the SSPxBUF, each bit of the address
will be shifted out on the falling edge of SCL until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
release the SDA pin, allowing the slave to respond with
an Acknowledge. On the falling edge of the ninth clock,
the master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT Status bit of the SSPxCON2
register. Following the falling edge of the ninth clock
transmission of the address, the SSPxIF is set, the BF
flag is cleared and the Baud Rate Generator is turned
off until another write to the SSPxBUF takes place,
holding SCL low and allowing SDA to float.
32.6.6.1 BF Status Flag
In Transmit mode, the BF bit of the SSPxSTAT register
is set when the CPU writes to SSPxBUF and is cleared
when all eight bits are shifted out.
32.6.6.2 WCOL Status Flag
If the user writes the SSPxBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).
WCOL must be cleared by software before the next
transmission.
32.6.6.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit of the SSPxCON2
register is cleared when the slave has sent an Acknowl-
edge (ACK =0) and is set when the slave does not
Acknowledge (ACK =1). A slave sends an Acknowl-
edge when it has recognized its address (including a
general call), or when the slave has properly received
its data.
32.6.6.4 Typical Transmit Sequence:
1. The user generates a Start condition by setting
the SEN bit of the SSPxCON2 register.
2. SSPxIF is set by hardware on completion of the
Start.
3. SSPxIF is cleared by software.
4. The MSSP module will wait the required start
time before any other operation takes place.
5. The user loads the SSPxBUF with the slave
address to transmit.
6. Address is shifted out the SDA pin until all eight
bits are transmitted. Transmission begins as
soon as SSPxBUF is written to.
7. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPxCON2 register.
8. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSPxIF bit.
9. The user loads the SSPxBUF with eight bits of
data.
10. Data is shifted out the SDA pin until all eight bits
are transmitted.
11. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPxCON2 register.
12. Steps 8-11 are repeated for all transmitted data
bytes.
13. The user generates a Stop or Restart condition
by setting the PEN or RSEN bits of the
SSPxCON2 register. Interrupt is generated once
the Stop/Restart condition is complete.
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FIGURE 32-28 : I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
SDA
SCL
SSPxIF
BF (SSPxSTAT<0>)
SEN
A7 A6 A5 A4 A3 A2 A1 ACK = 0D7 D6 D5 D4 D3 D2 D1 D0
ACK
Transmitting Data or Second Half
R/W = 0Transmit Address to Slave
123456789 123456789 P
Cleared by software service routine
SSPxBUF is written by software
from SSP interrupt
After Start condition, SEN cleared by hardware
S
SSPxBUF written with 7-bit address and R/W
start transmit
SCL held low
while CPU
responds to SSPxIF
SEN = 0
of 10-bit Address
Write SSPxCON2<0> SEN = 1
Start condition begins From slave, clear ACKSTAT bit SSPxCON2<6>
ACKSTAT in
SSPxCON2 = 1
Cleared by software
SSPxBUF written
PEN
R/W
Cleared by software
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32.6.7 I2C MASTER MODE RECEPTION
Master mode reception (Figure 32-29) is enabled by
programming the Receive Enable bit, RCEN bit of the
SSPxCON2 register.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes
(high-to-low/low-to-high) and data is shifted into the
SSPSR. After the falling edge of the eighth clock, the
receive enable flag is automatically cleared, the
contents of the SSPSR are loaded into the SSPxBUF,
the BF flag bit is set, the SSPxIF flag bit is set and the
Baud Rate Generator is suspended from counting,
holding SCL low. The MSSP is now in Idle state
awaiting the next command. When the buffer is read by
the CPU, the BF flag bit is automatically cleared. The
user can then send an Acknowledge bit at the end of
reception by setting the Acknowledge Sequence
Enable, ACKEN bit of the SSPxCON2 register.
32.6.7.1 BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPxBUF from SSPSR. It is
cleared when the SSPxBUF register is read.
32.6.7.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when eight
bits are received into the SSPSR and the BF flag bit is
already set from a previous reception.
32.6.7.3 WCOL Status Flag
If the user writes the SSPxBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write does not occur).
32.6.7.4 Typical Receive Sequence:
1. The user generates a Start condition by setting
the SEN bit of the SSPxCON2 register.
2. SSPxIF is set by hardware on completion of the
Start.
3. SSPxIF is cleared by software.
4. User writes SSPxBUF with the slave address to
transmit and the R/W bit set.
5. Address is shifted out the SDA pin until all eight
bits are transmitted. Transmission begins as
soon as SSPxBUF is written to.
6. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPxCON2 register.
7. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSPxIF bit.
8. User sets the RCEN bit of the SSPxCON2 regis-
ter and the master clocks in a byte from the slave.
9. After the eighth falling edge of SCL, SSPxIF and
BF are set.
10. Master clears SSPxIF and reads the received
byte from SSPxBUF, clears BF.
11. Master sets ACK value sent to slave in ACKDT
bit of the SSPxCON2 register and initiates the
ACK by setting the ACKEN bit.
12. Master’s ACK is clocked out to the slave and
SSPxIF is set.
13. User clears SSPxIF.
14. Steps 8-13 are repeated for each received byte
from the slave.
15. Master sends a not ACK or Stop to end
communication.
Note: The MSSP module must be in an Idle
state before the RCEN bit is set or the
RCEN bit will be disregarded.
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FIGURE 32-29 : I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
P
9
87
6
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4 A3 A2 A1
SDA
SCL 12345678912345678 9 1234
Bus master
terminates
transfer
ACK
Receiving Data from Slave
Receiving Data from Slave
D0
D1
D2
D3D4
D5
D6D7
ACK
R/
W
Transmit Address to Slave
SSPxIF
BF
ACK
is not sent
Write to SSPxCON2<0>(SEN =
1
),
Write to SSPxBUF occurs here, ACK from Slave
Master configured as a receiver
by programming SSPxCON2<3> (RCEN =
1
)
PEN bit = 1
written here
Data shifted in on falling edge of CLK
Cleared by software
start XMIT
SEN =
0
SSPOV
SDA =
0
, SCL =
1
while CPU
(SSPxSTAT<0>)
ACK
Cleared by software
Cleared by software
Set SSPxIF interrupt
at end of receive
Set P bit
(SSPxSTAT<4>)
and SSPxIF
Cleared in
software
ACK from Master
Set SSPxIF at end
Set SSPxIF interrupt
at end of Acknowledge
sequence
Set SSPxIF interrupt
at end of Acknow-
ledge sequence
of receive
Set ACKEN, start Acknowledge sequence
SSPOV is set because
SSPxBUF is still full
SDA = ACKDT =
1
RCEN cleared
automatically
RCEN =
1
, start
next receive
Write to SSPxCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPxCON2<5>) =
0
RCEN cleared
automatically
responds to SSPxIF
ACKEN
begin Start condition
Cleared by software
SDA = ACKDT =
0
Last bit is shifted into SSPSR and
contents are unloaded into SSPxBUF
RCEN
Master configured as a receiver
by programming SSPxCON2<3> (RCEN =
1
)
RCEN cleared
automatically
ACK from Master
SDA = ACKDT =
0
RCEN cleared
automatically
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32.6.8 ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN bit of the
SSPxCON2 register. When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to
generate an Acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an Acknowledge sequence. The Baud
Rate Generator then counts for one rollover period
(TBRG) and the SCL pin is deasserted (pulled high).
When the SCL pin is sampled high (clock arbitration),
the Baud Rate Generator counts for TBRG. The SCL pin
is then pulled low. Following this, the ACKEN bit is auto-
matically cleared, the Baud Rate Generator is turned off
and the MSSP module then goes into Idle mode
(Figure 32-30).
32.6.8.1 WCOL Status Flag
If the user writes the SSPxBUF when an Acknowledge
sequence is in progress, then the WCOL bit is set and
the contents of the buffer are unchanged (the write
does not occur).
32.6.9 STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN bit of the SSPxCON2 register. At the end of a
receive/transmit, the SCL line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDA line low. When the SDA
line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCL pin will be brought high
and one TBRG (Baud Rate Generator rollover count)
later, the SDA pin will be deasserted. When the SDA
pin is sampled high while SCL is high, the P bit of the
SSPxSTAT register is set. A TBRG later, the PEN bit is
cleared and the SSPxIF bit is set (Figure 32-31).
32.6.9.1 WCOL Status Flag
If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
FIGURE 32-30: ACKNOWLEDGE SEQUEN CE WAVEFORM
FIGURE 32-31: STOP CONDITION RECEIVE OR TRANSMIT MODE
Note: TBRG = one Baud Rate Generator period.
SDA
SCL
SSPxIF set at
Acknowledge sequence starts here,
write to SSPxCON2 ACKEN automatically cleared
Cleared in
TBRG TBRG
the end of receive
8
ACKEN = 1, ACKDT = 0
D0
9
SSPxIF
software SSPxIF set at the end
of Acknowledge sequence
Cleared in
software
ACK
SCL
SDA
SDA asserted low before rising edge of clock
Write to SSPxCON2,
set PEN
Falling edge of
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
9th clock
SCL brought high after TBRG
Note: TBRG = one Baud Rate Generator period.
TBRG TBRG
after SDA sampled high. P bit (SSPxSTAT<4>) is set.
TBRG
to setup Stop condition
ACK
P
TBRG
PEN bit (SSPxCON2<2>) is cleared by
hardware and the SSPxIF bit is set
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32.6.10 SLEEP OPERATION
While in Sleep mode, the I2C slave module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
32.6.11 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
32.6.12 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit of the SSPxSTAT register is
set, or the bus is Idle, with both the S and P bits clear.
When the bus is busy, enabling the SSP interrupt will
generate the interrupt when the Stop condition occurs.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed by
hardware with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
• A Repeated Start Condition
• An Acknowledge Condition
32.6.13 MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA, by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its Idle state (Figure 32-32).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPxBUF can be written to. When the user services
the bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge condi-
tion was in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are deas-
serted and the respective control bits in the SSPxCON2
register are cleared. When the user services the bus
collision Interrupt Service Routine and if the I2C bus is
free, the user can resume communication by asserting a
Start condition.
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPxIF bit will be set.
A write to the SSPxBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the deter-
mination of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPxSTAT
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 32-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
SDA
SCL
BCLIF
SDA released
SDA line pulled low
by another source
Sample SDA. While SCL is high,
data does not match what is driven
Bus collision has occurred.
Set bus collision
interrupt (BCLIF)
by the master.
by master
Data changes
while SCL = 0
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32.6.13.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the Start condition (Figure 32-33).
b) SCL is sampled low before SDA is asserted low
(Figure 32-34).
During a Start condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCLIF flag is set and
• the MSSP module is reset to its Idle state
(Figure 32-33).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded and counts down. If the
SCL pin is sampled low while SDA is high, a bus
collision occurs because it is assumed that another
master is attempting to drive a data ‘1’ during the Start
condition.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 32-35). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to zero; if the SCL pin is sampled as ‘0’
during this time, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
FIGURE 32-33: BUS COLLISION DURING START CONDITION (SDA ONLY)
Note: The reason that bus collision is not a
factor during a Start condition is that no
two bus masters can assert a Start condi-
tion at the exact same time. Therefore,
one master will always assert SDA before
the other. This condition does not cause a
bus collision because the two masters
must be allowed to arbitrate the first
address following the Start condition. If the
address is the same, arbitration must be
allowed to continue into the data portion,
Repeated Start or Stop conditions.
SDA
SCL
SEN
SDA sampled low before
SDA goes low before the SEN bit is set.
S bit and SSPxIF set because
SSP module reset into Idle state.
SEN cleared automatically because of bus collision.
S bit and SSPxIF set because
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SDA = 0, SCL = 1.
BCLIF
S
SSPxIF
SDA = 0, SCL = 1.
SSPxIF and BCLIF are
cleared by software
SSPxIF and BCLIF are
cleared by software
Set BCLIF,
Start condition. Set BCLIF.
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FIGURE 32-34: BUS COLLISION DURING START CONDITION (SCL = 0)
FIGURE 32-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA
SCL
SEN bus collision occurs. Set BCLIF.
SCL = 0 before SDA = 0,
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPxIF
Interrupt cleared
by software
bus collision occurs. Set BCLIF.
SCL = 0 before BRG time-out,
’0’’0’
’0’’0’
SDA
SCL
SEN
Set S
Less than TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPxIF
S
Interrupts cleared
by software
set SSPxIF
SDA = 0, SCL = 1,
SCL pulled low after BRG
time-out
Set SSPxIF
’0’
SDA pulled low by other master.
Reset BRG and assert SDA.
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
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32.6.13.2 Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level (Case 1).
b) SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’ (Case 2).
When the user releases SDA and the pin is allowed to
float high, the BRG is loaded with SSPxADD and
counts down to zero. The SCL pin is then deasserted
and when sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 32-36).
If SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition,
see Figure 32-37.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
FIGURE 32-36: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
FIGURE 32-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SDA
SCL
RSEN
BCLIF
S
SSPxIF
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
Cleared by software
’0’
’0’
SDA
SCL
BCLIF
RSEN
S
SSPxIF
Interrupt cleared
by software
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
TBRG TBRG
’0’
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32.6.13.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out (Case 1).
b) After the SCL pin is deasserted, SCL is sampled
low before SDA goes high (Case 2).
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPxADD and
counts down to zero. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 32-38). If the SCL pin is sampled
low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 32-39).
FIGURE 32-38: BUS COLLISION DURING A STOP CONDITION (CASE 1)
FIGURE 32-39: BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA
SCL
BCLIF
PEN
P
SSPxIF
TBRG TBRG TBRG
SDA asserted low
SDA sampled
low after TBRG,
set BCLIF
’0’
’0’
SDA
SCL
BCLIF
PEN
P
SSPxIF
TBRG TBRG TBRG
Assert SDA SCL goes low before SDA goes high,
set BCLIF
’0’
’0’
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DS40001819B-page 486 2015-2016 Microchip Technology Inc.
TABLE 32-3: SUMMARY OF REGISTERS ASSOCIATED WITH I2C OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values on
Page:
ANSELA —— ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177
ANSELB —— ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182
ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 187
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133
PIE2 OSFIE C2IE C1IE COG1IE BCL1IE C4IE C3IE CCP2IE 134
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139
PIR2 OSFIF C2IF C1IF COG1IF BCL1IF C4IF C3IF CCP2IF 140
RxyPPS —— RxyPPS<5:0> 205
SSPCLKPPS — — SSPCLKPPS<5:0> 205, 207
SSPDATPPS — — SSPDATPPS<5:0> 205, 207
SSPSSPPS — — SSPSSPPS<5:0> 205, 207
SSP1ADD ADD<7:0> 492
SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 444*
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 489
SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 490
SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 491
SSP1MSK MSK<7:0> 492
SSP1STAT SMP CKE D/A P S R/W UA BF 488
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I2C mode.
* Page provides register information.
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32.7 BAUD RATE GENERATOR
The MSSP module has a Baud Rate Generator avail-
able for clock generation in both I2C and SPI Master
modes. The Baud Rate Generator (BRG) reload value
is placed in the SSPxADD register (Register 32-6).
When a write occurs to SSPxBUF, the Baud Rate
Generator will automatically begin counting down.
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
An internal signal “Reload” in Figure 32-40 triggers the
value from SSPxADD to be loaded into the BRG
counter. This occurs twice for each oscillation of the
module clock line. The logic dictating when the reload
signal is asserted depends on the mode the MSSP is
being operated in.
Table 32-4 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD.
EQUATION 32-1:
FIGURE 32-40: BAUD RATE GENERATOR BLOCK DIAGRAM
TABLE 32-4: MSSP CLOCK RATE W/BRG
FCLOCK FOSC
SSPxADD 1+4
-------------------------------------------------=
Note: Values of 0x00, 0x01 and 0x02 are not valid
for SSPxADD when used as a Baud Rate
Generator for I2C. This is an implementation
limitation.
FOSC FCY BRG Value FCLOCK
(2 Rollovers of BRG)
32 MHz 8 MHz 13h 400 kHz
32 MHz 8 MHz 19h 308 kHz
32 MHz 8 MHz 4Fh 100 kHz
16 MHz 4 MHz 09h 400 kHz
16 MHz 4 MHz 0Ch 308 kHz
16 MHz 4 MHz 27h 100 kHz
4 MHz 1 MHz 09h 100 kHz
Note: Refer to the I/O port electrical specifications in Table 36-10 and Figure 32-7 to ensure the system is
designed to support I/O requirements.
SSPM<3:0>
BRG Down Counter
SSPCLK FOSC/2
SSPxADD<7:0>
SSPM<3:0>
SCL
Reload
Control
Reload
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32.8 Register Definitions: MSSP Control
REGISTER 32-1: SSP1STAT: SSP STATUS REGISTER
R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0
SMP CKE D/A PSR/WUA BF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 SMP: SPI Data Input Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I2 C Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
bit 6 CKE: SPI Clock Edge Select bit (SPI mode only)
In SPI Master or Slave mode:
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
In I2 C mode only:
1 = Enable input logic so that thresholds are compliant with SMBus specification
0 = Disable SMBus specific inputs
bit 5 D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0 = Stop bit was not detected last
bit 3 S: Start bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
bit 2 R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the
next Start bit, Stop bit, or not ACK bit.
In I2 C Slave mode:
1 =Read
0 = Write
In I2 C Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode.
bit 1 UA: Update Address bit (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSP1ADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
Receive (SPI and I2 C modes):
1 = Receive complete, SSP1BUF is full
0 = Receive not complete, SSP1BUF is empty
Transmit (I2 C mode only):
1 = Data transmit in progress (does not include the ACK and Stop bits), SSP1BUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSP1BUF is empty
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REGISTER 32-2: SSP1CON1: SSP CONTROL REGISTER 1
R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
WCOL SSPOV(1) SSPEN CKP SSPM<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared
bit 7 WCOL: Write Collision Detect bit
Master mode:
1 = A write to the SSP1BUF register was attempted while the I2C conditions were not valid for a transmission to be started
0 = No collision
Slave mode:
1 = The SSP1BUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit(1)
In SPI mode:
1 = A new byte is received while the SSP1BUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost.
Overflow can only occur in Slave mode. In Slave mode, the user must read the SSP1BUF, even if only transmitting data, to avoid
setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the
SSP1BUF register (must be cleared in software).
0 = No overflow
In I2 C mode:
1 = A byte is received while the SSP1BUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode
(must be cleared in software).
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2)
0 = Disables serial port and configures these pins as I/O port pins
In I2 C mode:
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3)
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2 C Slave mode:
SCL release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2 C Master mode:
Unused in this mode
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1101 = Reserved
1100 = Reserved
1011 = I2C firmware controlled Master mode (slave idle)
1010 = SPI Master mode, clock = FOSC/(4 * (SSP1ADD+1))(5)
1001 = Reserved
1000 = I2C Master mode, clock = FOSC / (4 * (SSP1ADD+1))(4)
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0011 = SPI Master mode, clock = T2_match/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF register.
2: When enabled, these pins must be properly configured as input or output. Use SSPSSPPS, SSPCLKPPS, SSPDATPPS, and RxyPPS
to select the pins.
3: When enabled, the SDA and SCL pins must be configured as inputs. Use SSPCLKPPS, SSPDATPPS, and RxyPPS to select the pins.
4: SSP1ADD values of 0, 1 or 2 are not supported for I2C mode.
5: SSP1ADD value of ‘0’ is not supported. Use SSPM = 0000 instead.
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REGISTER 32-3: SSP1CON2: SSP CONTROL REGISTER 2(1)
R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set
bit 7 GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only)
1 = Acknowledge was not received
0 = Acknowledge was received
bit 5 ACKDT: Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3 RCEN: Receive Enable bit (in I2C Master mode only)
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only)
SCKMSSP Release Control:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enable bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSP1BUF may not be written (or writes to the SSP1BUF are disabled).
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REGISTER 32-4: SSP1CON3: SSP CONTROL REGISTER 3
R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ACKTIM(3) PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3)
1 = Indicates the I2C bus is in an Acknowledge sequence, set on eighth falling edge of SCL clock
0 = Not an Acknowledge sequence, cleared on ninth rising edge of SCL clock
bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C slave mode only)
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled(2)
bit 5 SCIE: Start Condition Interrupt Enable bit (I2C slave mode only)
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled(2)
bit 4 BOEN: Buffer Overwrite Enable bit
In SPI Slave mode:(1)
1 = SSP1BUF updates every time that a new data byte is shifted in ignoring the BF bit
0 = If new byte is received with BF bit of the SSP1STAT register already set, SSPOV bit of the
SSP1CON1 register is set, and the buffer is not updated
In I2C Master mode and SPI Master mode:
This bit is ignored.
In I2C Slave mode:
1 = SSP1BUF is updated and ACK is generated for a received address/data byte, ignoring the
state of the SSPOV bit only if the BF bit = 0.
0 = SSP1BUF is only updated when SSPOV is clear
bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only)
1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL
0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL
bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If, on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the
BCL1IF bit of the PIR2 register is set, and bus goes idle
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only)
1 = Following the eighth falling edge of SCL for a matching received address byte; CKP bit of the
SSP1CON1 register will be cleared and the SCL will be held low.
0 = Address holding is disabled
bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only)
1 = Following the eighth falling edge of SCL for a received data byte; slave hardware clears the CKP
bit of the SSP1CON1 register and SCL is held low.
0 = Data holding is disabled
Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSP1BUF.
2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
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REGISTER 32-5: SSP1MSK: SSP MASK REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
MSK<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-1 MSK<7:1>: Mask bits
1 = The received address bit n is compared to SSP1ADD<n> to detect I2C address match
0 = The received address bit n is not used to detect I2C address match
bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address
I2C Slave mode, 10-bit address (SSPM<3:0> = 0111 or 1111):
1 = The received address bit 0 is compared to SSP1ADD<0> to detect I2C address match
0 = The received address bit 0 is not used to detect I2C address match
I2C Slave mode, 7-bit address, the bit is ignored
REGISTER 32-6: SSP1ADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ADD<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Master mode:
bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits
SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC
10-Bit Slave mode – Most Significant Address Byte:
bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care”. Bit
pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits
are compared by hardware and are not affected by the value in this register.
bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address
bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.
10-Bit Slave mode – Least Significant Address Byte:
bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address
7-Bi t Slave mode:
bit 7-1 ADD<7:1>: 7-bit address
bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.
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33.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer
independent of device program execution. The
EUSART, also known as a Serial Communications
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous
system. Full-Duplex mode is useful for
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
The EUSART module includes the following capabilities:
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
• One-character output buffer
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
• Input buffer overrun error detection
• Received character framing error detection
• Half-duplex synchronous master
• Half-duplex synchronous slave
• Programmable clock polarity in synchronous
modes
• Sleep operation
The EUSART module implements the following
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
• Automatic detection and calibration of the baud rate
• Wake-up on Break reception
• 13-bit Break character transmit
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 33-1 and Figure 33-2.
The EUSART transmit output (TX_out) is available to
the TX/CK pin and internally to the following peripherals:
• Configurable Logic Cell (CLC)
• Data signal modulator (DSM)
FIGURE 33-1: EUSART TRANS MIT BLOCK DIAGRAM
TXIF
TXIE
Interrupt
TXEN
TX9D
MSb LSb
Data Bus
TXxREG Register
Transmit Shift Register (TSR)
(8) 0
TX9
TRMT
RX/DT pin
Pin Buffer
and Control
8
SPxBRGL
SPxBRGH
BRG16
FOSC ÷ n
n
+ 1 Multiplier x4 x16 x64
SYNC 1X00 0
BRGH X110 0
BRG16 X101 0
Baud Rate Generator
•••
TX_out
PPS
RxyPPS(1)
CK pin
PPS
CKPPS
1
0
SYNC
CSRC
TX/CK pin
PPS
0
1
SYNC
CSRC
RxyPPS
SYNC
Note 1: In Synchronous mode the DT output and RX input PPS
selections should enable the same pin.
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FIGURE 33-2: EUSART RECEIVE BLOCK DIAGRAM
The operation of the EUSART module is controlled
through three registers:
• Transmit Status and Control (TXxSTA)
• Receive Status and Control (RCxSTA)
• Baud Rate Control (BAUDxCON)
These registers are detailed in Register 33-1,
Register 33-2 and Register 33-3, respectively.
The RX and CK input pins are selected with the RXPPS
and CKPPS registers, respectively. TX, CK, and DT
output pins are selected with each pin’s RxyPPS register.
Since the RX input is coupled with the DT output in
Synchronous mode, it is the user’s responsibility to select
the same pin for both of these functions when operating
in Synchronous mode. The EUSART control logic will
control the data direction drivers automatically.
RX/DT pin
Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR
FERR
RSR Register
MSb LSb
RX9D RCxREG Register FIFO
Interrupt
RCIF
RCIE
Data Bus
8
Stop Start
(8) 7 1 0
RX9
• • •
SPxBRGLSPxBRGH
BRG16
RCIDL
FOSC ÷ n
n
+ 1 Multiplier x4 x16 x64
SYNC 1X00 0
BRGH X110 0
BRG16 X101 0
Baud Rate Generator
PPS
RXPPS(1)
Note 1: In Synchronous mode the DT output and RX input PPS
selections should enable the same pin.
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33.1 EUSART Asynchronous Mode
The EUSART transmits and receives data using the
standard non-return-to-zero (NRZ) format. NRZ is
implemented with two levels: a VOH Mark state which
represents a ‘1’ data bit, and a VOL Space state which
represents a ‘0’ data bit. NRZ refers to the fact that
consecutively transmitted data bits of the same value
stay at the output level of that bit without returning to a
neutral level between each bit transmission. An NRZ
transmission port idles in the Mark state. Each character
transmission consists of one Start bit followed by eight
or nine data bits and is always terminated by one or
more Stop bits. The Start bit is always a space and the
Stop bits are always marks. The most common data
format is eight bits. Each transmitted bit persists for a
period of 1/(baud rate). An on-chip dedicated 8-bit/16-bit
Baud Rate Generator is used to derive standard baud
rate frequencies from the system oscillator. See
Table 33-5 for examples of baud rate configurations.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent, but share the same data format and baud
rate. Parity is not supported by the hardware, but can
be implemented in software and stored as the ninth
data bit.
33.1.1 EUSART ASYNCHRONOUS
TRANSMITTER
The EUSART transmitter block diagram is shown in
Figure 33-1. The heart of the transmitter is the serial
Transmit Shift Register (TSR), which is not directly
accessible by software. The TSR obtains its data from
the transmit buffer, which is the TXxREG register.
33.1.1.1 Enabling the Transmitter
The EUSART transmitter is enabled for asynchronous
operations by configuring the following three control
bits:
•TXEN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the TXEN bit of the TXxSTA register enables the
transmitter circuitry of the EUSART. Clearing the SYNC
bit of the TXxSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCxSTA register enables the EUSART and
automatically configures the TX/CK I/O pin as an output.
If the TX/CK pin is shared with an analog peripheral, the
analog I/O function must be disabled by clearing the
corresponding ANSEL bit.
33.1.1.2 Transmitting Data
A transmission is initiated by writing a character to the
TXxREG register. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXxREG is immediately
transferred to the TSR register. If the TSR still contains
all or part of a previous character, the new character
data is held in the TXxREG until the Stop bit of the
previous character has been transmitted. The pending
character in the TXxREG is then transferred to the TSR
in one TCY immediately following the Stop bit
transmission. The transmission of the Start bit, data bits
and Stop bit sequence commences immediately
following the transfer of the data to the TSR from the
TXxREG.
33.1.1.3 Transmit Data Polarity
The polarity of the transmit data can be controlled with
the SCKP bit of the BAUDxCON register. The default
state of this bit is ‘0’, which selects high true transmit idle
and data bits. Setting the SCKP bit to ‘1’ will invert the
transmit data resulting in low true idle and data bits. The
SCKP bit controls transmit data polarity in
Asynchronous mode only. In Synchronous mode, the
SCKP bit has a different function. See Section 33.5.1.2
“Clock Polarity”.
33.1.1.4 Transmit Interrupt Flag
The TXIF interrupt flag bit of the PIR1 register is set
whenever the EUSART transmitter is enabled and no
character is being held for transmission in the TXxREG.
In other words, the TXIF bit is only clear when the TSR
is busy with a character and a new character has been
queued for transmission in the TXxREG. The TXIF flag
bit is not cleared immediately upon writing TXxREG.
TXIF becomes valid in the second instruction cycle
following the write execution. Polling TXIF immediately
following the TXxREG write will return invalid results.
The TXIF bit is read-only, it cannot be set or cleared by
software.
The TXIF interrupt can be enabled by setting the TXIE
interrupt enable bit of the PIE1 register. However, the
TXIF flag bit will be set whenever the TXxREG is
empty, regardless of the state of the TXIE enable bit.
To use interrupts when transmitting data, set the TXIE
bit only when there is more data to send. Clear the
TXIE interrupt enable bit upon writing the last character
of the transmission to the TXxREG.
Note: The TXIF Transmitter Interrupt flag is set
when the TXEN enable bit is set.
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33.1.1.5 TSR Status
The TRMT bit of the TXxSTA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXxREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user has to
poll this bit to determine the TSR status.
33.1.1.6 Transmitting 9-Bit Characters
The EUSART supports 9-bit character transmissions.
When the TX9 bit of the TXxSTA register is set, the
EUSART will shift nine bits out for each character trans-
mitted. The TX9D bit of the TXxSTA register is the
ninth, and Most Significant data bit. When transmitting
9-bit data, the TX9D data bit must be written before
writing the eight Least Significant bits into the TXxREG.
All nine bits of data will be transferred to the TSR shift
register immediately after the TXxREG is written.
A special 9-bit Address mode is available for use with
multiple receivers. See Section 33.1.2.7 “Address
Detection” for more information on the Address mode.
33.1.1.7 Asynchronous Transmission Set-up:
1. Initialize the SPxBRGH:SPxBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 33.4 “EUSART
Baud Rate Generator (BRG)”).
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If 9-bit transmission is desired, set the TX9
control bit. A set ninth data bit will indicate that
the eight Least Significant data bits are an
address when the receiver is set for address
detection.
4. Set the SCKP bit if inverted transmit is desired.
5. Enable the transmission by setting the TXEN
control bit. This will cause the TXIF interrupt bit
to be set.
6. If interrupts are desired, set the TXIE interrupt
enable bit of the PIE1 register. An interrupt will
occur immediately provided that the GIE and
PEIE bits of the INTCON register are also set.
7. If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
8. Load 8-bit data into the TXxREG register. This
will start the transmission.
FIGURE 33-3: ASYNCHRONOUS TRANSMISSION
Note: The TSR register is not mapped in data
memory, so it is not available to the user.
Word 1
Stop bit
Word 1
Transmit Shift Reg.
Start bit bit 0 bit 1 bit 7/8
Write to TXxREG
Word 1
BRG Output
(Shift Clock)
TX/CK
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
1 TCY
pin
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FIGURE 33-4: ASYNCHRONOUS TRANSM ISSION (BACK-TO-BACK)
TABLE 33-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on
Page
ANSELA —— ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177
ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182
ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 187
BAUD1CON ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 505
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139
RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 504
RxyPPS — — RxyPPS<5:0> 205, 207
SP1BRGL SP1BRG<7:0> 506*
SP1BRGH SP1BRG<15:8> 506*
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186
TX1REG EUSART Transmit Data Register 495*
TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 503
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous transmission.
* Page provides register information.
Transmit Shift Reg.
Write to TXxREG
BRG Output
(Shift Clock)
TX/CK
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1 Word 2
Word 1 Word 2
Start bit Stop bit Start bit
Transmit Shift Reg.
Word 1 Word 2
bit 0 bit 1 bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
pin
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
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33.1.2 EUSART ASYNCHRONOUS
RECEIVER
The Asynchronous mode is typically used in RS-232
systems. The receiver block diagram is shown in
Figure 33-2. The data is received on the RX/DT pin and
drives the data recovery block. The data recovery block
is actually a high-speed shifter operating at 16 times
the baud rate, whereas the serial Receive Shift
Register (RSR) operates at the bit rate. When all eight
or nine bits of the character have been shifted in, they
are immediately transferred to a two character
First-In-First-Out (FIFO) memory. The FIFO buffering
allows reception of two complete characters and the
start of a third character before software must start
servicing the EUSART receiver. The FIFO and RSR
registers are not directly accessible by software.
Access to the received data is via the RCxREG
register.
33.1.2.1 Enabling the Receiver
The EUSART receiver is enabled for asynchronous
operation by configuring the following three control bits:
• CREN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the CREN bit of the RCxSTA register enables
the receiver circuitry of the EUSART. Clearing the SYNC
bit of the TXxSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCxSTA register enables the EUSART. The
programmer must set the corresponding TRIS bit to
configure the RX/DT I/O pin as an input.
33.1.2.2 Receiving Data
The receiver data recovery circuit initiates character
reception on the falling edge of the first bit. The first bit,
also known as the Start bit, is always a zero. The data
recovery circuit counts one-half bit time to the center of
the Start bit and verifies that the bit is still a zero. If it is
not a zero then the data recovery circuit aborts
character reception, without generating an error, and
resumes looking for the falling edge of the Start bit. If
the Start bit zero verification succeeds then the data
recovery circuit counts a full bit time to the center of the
next bit. The bit is then sampled by a majority detect
circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.
This repeats until all data bits have been sampled and
shifted into the RSR. One final bit time is measured and
the level sampled. This is the Stop bit, which is always
a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this
character, otherwise the framing error is cleared for this
character. See Section 33.1.2.4 “Receive Framing
Error” for more information on framing errors.
Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
to the EUSART receive FIFO and the RCIF interrupt
flag bit of the PIR1 register is set. The top character in
the FIFO is transferred out of the FIFO by reading the
RCxREG register.
33.1.2.3 Receive Interrupts
The RCIF interrupt flag bit of the PIR1 register is set
whenever the EUSART receiver is enabled and there is
an unread character in the receive FIFO. The RCIF
interrupt flag bit is read-only, it cannot be set or cleared
by software.
RCIF interrupts are enabled by setting all of the
following bits:
• RCIE, Interrupt Enable bit of the PIE1 register
• PEIE, Peripheral Interrupt Enable bit of the
INTCON register
• GIE, Global Interrupt Enable bit of the INTCON
register
The RCIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.
Note: If the RX/DT function is on an analog pin,
the corresponding ANSEL bit must be
cleared for the receiver to function.
Note: If the receive FIFO is overrun, no additional
characters will be received until the overrun
condition is cleared. See Section 33.1.2.5
“Receive Overrun Error” for more
information on overrun errors.
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33.1.2.4 Receive Framing Error
Each character in the receive FIFO buffer has a
corresponding framing error Status bit. A framing error
indicates that a Stop bit was not seen at the expected
time. The framing error status is accessed via the
FERR bit of the RCxSTA register. The FERR bit
represents the status of the top unread character in the
receive FIFO. Therefore, the FERR bit must be read
before reading the RCxREG.
The FERR bit is read-only and only applies to the top
unread character in the receive FIFO. A framing error
(FERR = 1) does not preclude reception of additional
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
The FERR bit can be forced clear by clearing the SPEN
bit of the RCxSTA register which resets the EUSART.
Clearing the CREN bit of the RCxSTA register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
33.1.2.5 Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCxSTA register is
set. The characters already in the FIFO buffer can be
read but no additional characters will be received until
the error is cleared. The error must be cleared by either
clearing the CREN bit of the RCxSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCxSTA register.
33.1.2.6 Receiving 9-Bit Characters
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCxSTA register is set the EUSART
will shift nine bits into the RSR for each character
received. The RX9D bit of the RCxSTA register is the
ninth and Most Significant data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
from the RCxREG.
33.1.2.7 Address Detection
A special Address Detection mode is available for use
when multiple receivers share the same transmission
line, such as in RS-485 systems. Address detection is
enabled by setting the ADDEN bit of the RCxSTA
register.
Address detection requires 9-bit character reception.
When address detection is enabled, only characters
with the ninth data bit set will be transferred to the
receive FIFO buffer, thereby setting the RCIF interrupt
bit. All other characters will be ignored.
Upon receiving an address character, user software
determines if the address matches its own. Upon
address match, user software must disable address
detection by clearing the ADDEN bit before the next
Stop bit occurs. When user software detects the end of
the message, determined by the message protocol
used, software places the receiver back into the
Address Detection mode by setting the ADDEN bit.
Note: If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCxREG will not clear the FERR bit.
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33.1.2.8 Asynchronous Reception Set-up
1. Initialize the SPxBRGH:SPxBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 33.4 “EUSART
Baud Rate Generator (BRG)”).
2. Clear the ANSEL bit for the RX pin (if applicable).
3. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
4. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
5. If 9-bit reception is desired, set the RX9 bit.
6. Enable reception by setting the CREN bit.
7. The RCIF interrupt flag bit will be set when a
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if
the RCIE interrupt enable bit was also set.
8. Read the RCxSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
9. Get the received eight Least Significant data bits
from the receive buffer by reading the RCxREG
register.
10. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
33.1.2.9 9-bit Address Detection Mode Set-up
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPxBRGH:SPxBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 33.4 “EUSART
Baud Rate Generator (BRG)”).
2. Clear the ANSEL bit for the RX pin (if applicable).
3. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
4. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
5. Enable 9-bit reception by setting the RX9 bit.
6. Enable address detection by setting the ADDEN
bit.
7. Enable reception by setting the CREN bit.
8. The RCIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
from the RSR to the receive buffer. An interrupt
will be generated if the RCIE interrupt enable bit
was also set.
9. Read the RCxSTA register to get the error flags.
The ninth data bit will always be set.
10. Get the received eight Least Significant data bits
from the receive buffer by reading the RCxREG
register. Software determines if this is the
device’s address.
11. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
FIGURE 33-5: ASYNCHRONOUS RECEPTION
Start
bit bit 7/8
bit 1bit 0 bit 7/8 bit 0Stop
bit
Start
bit
Start
bit
bit 7/8 Stop
bit
RX/DT pin
Reg
Rcv Buffer Reg.
Rcv Shift
Read Rcv
Buffer Reg.
RCxREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCxREG
Word 2
RCxREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCxREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
RCIDL
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TABLE 33-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ANSELA —— ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177
ANSELB —— ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182
ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 187
BAUD1CON ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 505
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139
RC1REG EUSART Receive Data Register 498*
RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 504
RxyPPS — — RxyPPS<5:0> 205
SP1BRGL SP1BRG<7:0> 506
SP1BRGH SP1BRG<15:8> 506
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186
TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 503
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous reception.
* Page provides register information.
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33.2 Clock Accuracy with
Asynchronous Operation
The factory calibrates the internal oscillator block
output (INTOSC). However, the INTOSC frequency
may drift as VDD or temperature changes, and this
directly affects the asynchronous baud rate. Two
methods may be used to adjust the baud rate clock, but
both require a reference clock source of some kind.
The first (preferred) method uses the OSCTUNE
register to adjust the INTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
changes to the system clock source. See
Section 5.2.2.3 “Internal Oscillator Frequency
Adjustment” for more information.
The other method adjusts the value in the Baud Rate
Generator. This can be done automatically with the
Auto-Baud Detect feature (see Section 33.4.1
“Auto-Baud Detect”). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
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33.3 Regis t er D e fi nitio n s : E U S A R T C ontrol
REGISTER 33-1: TX1STA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0
CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.
PIC16(L)F1777/8/9
DS40001819B-page 504 2015-2016 Microchip Technology Inc.
REGISTER 33-2: RC1STA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 SPEN: Serial Port Enable bit
1 = Serial port enabled
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-Bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Don’t care
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCxREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
2015-2016 Microchip Technology Inc. DS40001819B-page 505
PIC16(L)F1777/8/9
REGISTER 33-3: BAUD1CON: BAUD RATE CONTROL REGISTER
R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 ABDOVF: Auto-Baud Detect Overflow bit
Asynchronous mode:
1 = Auto-baud timer overflowed
0 = Auto-baud timer did not overflow
Synchronous mode:
Don’t care
bit 6 RCIDL: Receive Idle Flag bit
Asynchronous mode:
1 = Receiver is Idle
0 = Start bit has been received and the receiver is receiving
Synchronous mode:
Don’t care
bit 5 Unimplemented: Read as ‘0’
bit 4 SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
1 = Transmit inverted data to the TX/CK pin
0 = Transmit non-inverted data to the TX/CK pin
Synchronous mode:
1 = Data is clocked on rising edge of the clock
0 = Data is clocked on falling edge of the clock
bit 3 BRG16: 16-bit Baud Rate Generator bit
1 = 16-bit Baud Rate Generator is used
0 = 8-bit Baud Rate Generator is used
bit 2 Unimplemented: Read as ‘0’
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE
will automatically clear after RCIF is set.
0 = Receiver is operating normally
Synchronous mode:
Don’t care
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
0 = Auto-Baud Detect mode is disabled
Synchronous mode:
Don’t care
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DS40001819B-page 506 2015-2016 Microchip Technology Inc.
33.4 EUSART Baud Rate Generator
(BRG)
The Baud Rate Generator (BRG) is an 8-bit or 16-bit
timer that is dedicated to the support of both the
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the
BRG16 bit of the BAUDxCON register selects 16-bit
mode.
The SPxBRGH:SPxBRGL register pair determines the
period of the free running baud rate timer. In
Asynchronous mode the multiplier of the baud rate
period is determined by both the BRGH bit of the
TXxSTA register and the BRG16 bit of the BAUDxCON
register. In Synchronous mode, the BRGH bit is ignored.
Table 33-3 contains the formulas for determining the
baud rate. Example 33-1 provides a sample calculation
for determining the baud rate and baud rate error.
Typical baud rates and error values for various
Asynchronous modes have been computed for your
convenience and are shown in Table 33-5. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
Writing a new value to the SPxBRGH:SPxBRGL regis-
ter pair causes the BRG timer to be reset (or cleared).
This ensures that the BRG does not wait for a timer
overflow before outputting the new baud rate.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is idle before
changing the system clock.
EXAMPLE 33-1: CALCULATING BAUD
RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate
of 9600, Asynchronous mode, 8-bit BRG:
Solving for SPxBRGH:SPxBRGL:
X
FOSC
Desired Ba ud R at e
---------------------------------------------
64
--------------------------------------------- 1–=
Desired Baud Rate FOSC
64 [SPBRGH:SPBRGL] 1+
------------------------------------------------------------------------=
16000000
9600
------------------------
64
------------------------1–=
25.04225==
Calculated Baud Rate 16000000
64 25 1+
---------------------------=
9615=
Error Calc. Bau d Rate D e sire d B aud Rate –
Desired Baud Rate
--------------------------------------------------------------------------------------------=
9615 9600–
9600
---------------------------------- 0.1 6%==
2015-2016 Microchip Technology Inc. DS40001819B-page 507
PIC16(L)F1777/8/9
TABLE 33-3: BAUD RATE FORMULAS
TABLE 33-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Configuration Bits BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH
000 8-bit/Asynchronous FOSC/[64 (n+1)]
001 8-bit/Asynchronous FOSC/[16 (n+1)]
010 16-bit/Asynchronous
011 16-bit/Asynchronous
FOSC/[4 (n+1)]10x 8-bit/Synchronous
11x 16-bit/Synchronous
Legend: x = Don’t care, n = value of SPxBRGH:SPxBRGL register pair.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
BAUD1CON ABDOVF RCIDL —SCKP BRG16 —WUE ABDEN 505
RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 504
SP1BRGL SP1BRG<7:0> 506
SP1BRGH SP1BRG<15:8> 506
TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 503
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the Baud Rate Generator.
* Page provides register information.
PIC16(L)F1777/8/9
DS40001819B-page 508 2015-2016 Microchip Technology Inc.
TABLE 33-5: BAUD RATES FOR ASYNCHRONOUS MODES
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
300—— — —— — —— — —— —
1200 — — — 1221 1.73 255 1200 0.00 239 1200 0.00 143
2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71
9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17
10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16
19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8
57.6k 55.55k -3.55 3 — — — 57.60k 0.00 7 57.60k 0.00 2
115.2k — — — — — — — — — — — —
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
300 — — — 300 0.16 207 300 0.00 191 300 0.16 51
1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12
2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — —
9600 9615 0.16 12 — — — 9600 0.00 5 — — —
10417 10417 0.00 11 10417 0.00 5 — — — — — —
19.2k — — — — — — 19.20k 0.00 2 — — —
57.6k — — — — — — 57.60k 0.00 0 — — —
115.2k — — — — — — — — — — — —
BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
300 —— — —— — —— — —— —
1200 — — — — — — — — — — — —
2400 — — — — — — — — — —— —
9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71
10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65
19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35
57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11
115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5
2015-2016 Microchip Technology Inc. DS40001819B-page 509
PIC16(L)F1777/8/9
BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 8.000 MHz FOSC = 4.000 MHz F OSC = 3.6864 MHz FOSC = 1.000 MHz
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
300 —— — — — — — — — 300 0.16 207
1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303
1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575
2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287
9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71
10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65
19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35
57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11
115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 8.000 MHz FOSC = 4.000 MHz F OSC = 3.6864 MHz FOSC = 1.000 MHz
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207
1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
TABLE 33-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
PIC16(L)F1777/8/9
DS40001819B-page 510 2015-2016 Microchip Technology Inc.
BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
300 300.0 0.00 26666 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215
1200 1200 0.00 6666 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303
2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151
9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287
10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264
19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143
57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47
115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23
BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 8.000 MHz FOSC = 4.000 MHz F OSC = 3.6864 MHz FOSC = 1.000 MHz
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
Actual
Rate %
Error
SPxBRG
value
(decimal)
300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832
1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207
2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103
9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25
10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23
19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12
57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — —
115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —
TABLE 33-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
2015-2016 Microchip Technology Inc. DS40001819B-page 511
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33.4.1 AUTO-BAUD DETECT
The EUSART module supports automatic detection
and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
Setting the ABDEN bit of the BAUDxCON register
starts the auto-baud calibration sequence. While the
ABD sequence takes place, the EUSART state
machine is held in Idle. On the first rising edge of the
receive line, after the Start bit, the SPxBRG begins
counting up using the BRG counter clock as shown in
Figure 33-6. The fifth rising edge will occur on the RX
pin at the end of the eighth bit period. At that time, an
accumulated value totaling the proper BRG period is
left in the SPxBRGH:SPxBRGL register pair, the
ABDEN bit is automatically cleared and the RCIF
interrupt flag is set. The value in the RCxREG needs to
be read to clear the RCIF interrupt. RCxREG content
should be discarded. When calibrating for modes that
do not use the SPxBRGH register the user can verify
that the SPxBRGL register did not overflow by
checking for 00h in the SPxBRGH register.
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in Table 3 3- 6. During ABD,
both the SPxBRGH and SPxBRGL registers are used
as a 16-bit counter, independent of the BRG16 bit set-
ting. While calibrating the baud rate period, the
SPxBRGH and SPxBRGL registers are clocked at
1/8th the BRG base clock rate. The resulting byte mea-
surement is the average bit time when clocked at full
speed.
TABLE 33-6: BRG COUNTER CLOCK RATES
FIGURE 33-6: AUTOMATIC BAUD RATE CALIBRATION(1)
Note 1: If the WUE bit is set with the ABDEN bit,
auto-baud detection will occur on the byte
following the Break character (see
Section 33.4.3 “Auto-Wake-up on
Break”).
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
3: During the auto-baud process, the
auto-baud counter starts counting at one.
Upon completion of the auto-baud
sequence, to achieve maximum accuracy,
subtract 1 from the SPxBRGH:SPxBRGL
register pair.
BRG16 BRGH BRG Base
Clock BRG ABD
Clock
00FOSC/64 FOSC/512
01FOSC/16 FOSC/128
10FOSC/16 FOSC/128
11 FOSC/4 FOSC/32
Note: During the ABD sequence, SPxBRGL and
SPxBRGH registers are both used as a
16-bit counter, independent of the BRG16
setting.
BRG Value
RX pin
ABDEN bit
RCIF bit
bit 0 bit 1
(Interrupt)
Read
RCxREG
BRG Clock
Start
Auto Cleared
Set by User
XXXXh 0000h
Edge #1
bit 2 bit 3
Edge #2
bit 4 bit 5
Edge #3
bit 6 bit 7
Edge #4
Stop bit
Edge #5
001Ch
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
SPxBRGL XXh 1Ch
SPxBRGH XXh 00h
RCIDL
PIC16(L)F1777/8/9
DS40001819B-page 512 2015-2016 Microchip Technology Inc.
33.4.2 AUTO-BAUD OVERFLOW
During the course of automatic baud detection, the
ABDOVF bit of the BAUDxCON register will be set if
the baud rate counter overflows before the fifth rising
edge is detected on the RX pin. The ABDOVF bit indi-
cates that the counter has exceeded the maximum
count that can fit in the 16 bits of the
SPxBRGH:SPxBRGL register pair. The overflow condi-
tion will set the RCIF flag. The counter continues to
count until the fifth rising edge is detected on the RX
pin. The RCIDL bit will remain false (‘0’) until the fifth
rising edge at which time the RCIDL bit will be set. If the
RCREG is read after the overflow occurs but before the
fifth rising edge then the fifth rising edge will set the
RCIF again.
Terminating the auto-baud process early to clear an
overflow condition will prevent proper detection of the
sync character fifth rising edge. If any falling edges of
the sync character have not yet occurred when the
ABDEN bit is cleared then those will be falsely detected
as Start bits. The following steps are recommended to
clear the overflow condition:
1. Read RCREG to clear RCIF.
2. If RCIDL is zero then wait for RCIF and repeat
step 1.
3. Clear the ABDOVF bit.
33.4.3 AUTO-WAKE-UP ON BREAK
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper character reception cannot be
performed. The Auto-Wake-up feature allows the
controller to wake-up due to activity on the RX/DT line.
This feature is available only in Asynchronous mode.
The Auto-Wake-up feature is enabled by setting the
WUE bit of the BAUDxCON register. Once set, the
normal receive sequence on RX/DT is disabled, and the
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on the
RX/DT line. (This coincides with the start of a Sync Break
or a wake-up signal character for the LIN protocol.)
The EUSART module generates an RCIF interrupt
coincident with the wake-up event. The interrupt is
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 33-7), and asynchronously if
the device is in Sleep mode (Figure 33-8). The interrupt
condition is cleared by reading the RCxREG register.
The WUE bit is automatically cleared by the low-to-high
transition on the RX line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in Idle mode waiting to
receive the next character.
33.4.3.1 Special Considerations
Break Character
To avoid character errors or character fragments during
a wake-up event, the wake-up character must be all
zeros.
When the wake-up is enabled the function works
independent of the low time on the data stream. If the
WUE bit is set and a valid non-zero character is
received, the low time from the Start bit to the first rising
edge will be interpreted as the wake-up event. The
remaining bits in the character will be received as a
fragmented character and subsequent characters can
result in framing or overrun errors.
Therefore, the initial character in the transmission must
be all ‘0’s. This must be ten or more bit times, 13-bit
times recommended for LIN bus, or any number of bit
times for standard RS-232 devices.
Oscillator Start-up Time
Oscillator start-up time must be considered, especially
in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS/PLL mode). The Sync
Break (or wake-up signal) character must be of
sufficient length, and be followed by a sufficient
interval, to allow enough time for the selected oscillator
to start and provide proper initialization of the EUSART.
WUE Bit
The wake-up event causes a receive interrupt by
setting the RCIF bit. The WUE bit is cleared in
hardware by a rising edge on RX/DT. The interrupt
condition is then cleared in software by reading the
RCxREG register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
2015-2016 Microchip Technology Inc. DS40001819B-page 513
PIC16(L)F1777/8/9
FIGURE 33-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
FIGURE 33-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit(1)
RX/DT Line
RCIF
Bit set by user Auto Cleared
Cleared due to User Read of RCxREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
Q1Q2Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit(2)
RX/DT Line
RCIF
Bit Set by User Auto Cleared
Cleared due to User Read of RCxREG
Sleep Command Executed
Note 1
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
Sleep Ends
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33.4.4 BREAK CHARACTER SEQUENCE
The EUSART module has the capability of sending the
special Break character sequences that are required by
the LIN bus standard. A Break character consists of a
Start bit, followed by 12 ‘0’ bits and a Stop bit.
To send a Break character, set the SENDB and TXEN
bits of the TXxSTA register. The Break character trans-
mission is then initiated by a write to the TXxREG. The
value of data written to TXxREG will be ignored and all
‘0’s will be transmitted.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
The TRMT bit of the TXxSTA register indicates when the
transmit operation is active or idle, just as it does during
normal transmission. See Figure 33-9 for the timing of
the Break character sequence.
33.4.4.1 Break and Sync Transmit Sequence
The following sequence will start a message frame
header made up of a Break, followed by an auto-baud
Sync byte. This sequence is typical of a LIN bus
master.
1. Configure the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to enable the
Break sequence.
3. Load the TXxREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXxREG to load the Sync charac-
ter into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
When the TXxREG becomes empty, as indicated by
the TXIF, the next data byte can be written to TXxREG.
33.4.5 RECEIVING A BREAK CHARACTER
The Enhanced EUSART module can receive a Break
character in two ways.
The first method to detect a Break character uses the
FERR bit of the RCxSTA register and the received data
as indicated by RCxREG. The Baud Rate Generator is
assumed to have been initialized to the expected baud
rate.
A Break character has been received when:
• RCIF bit is set
• FERR bit is set
• RCxREG = 00h
The second method uses the Auto-Wake-up feature
described in Section 33.4.3 “Auto-Wake-up on
Break”. By enabling this feature, the EUSART will
sample the next two transitions on RX/DT, cause an
RCIF interrupt, and receive the next data byte followed
by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Detect feature.
For both methods, the user can set the ABDEN bit of
the BAUDxCON register before placing the EUSART in
Sleep mode.
FIGURE 33-9: SEND BREAK CHARACTER SEQUENCE
Write to TXxREG Dummy Write
BRG Output
(Shift Clock)
Start bit bit 0 bit 1 bit 11 Stop bit
Break
TXIF bit
(Transmit
Interrupt Flag)
TX (pin)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB
(send Break
control bit)
SENDB Sampled Here Auto Cleared
2015-2016 Microchip Technology Inc. DS40001819B-page 515
PIC16(L)F1777/8/9
33.5 EUSART Synchronous Mode
Synchronous serial communications are typically used
in systems with a single master and one or more
slaves. The master device contains the necessary
circuitry for baud rate generation and supplies the clock
for all devices in the system. Slave devices can take
advantage of the master clock by eliminating the
internal clock generation circuitry.
There are two signal lines in Synchronous mode: a
bidirectional data line and a clock line. Slaves use the
external clock supplied by the master to shift the serial
data into and out of their respective receive and trans-
mit shift registers. Since the data line is bidirectional,
synchronous operation is half-duplex only. Half-duplex
refers to the fact that master and slave devices can
receive and transmit data but not both simultaneously.
The EUSART can operate as either a master or slave
device.
Start and Stop bits are not used in synchronous
transmissions.
33.5.1 SYNCHRONOUS MASTER MODE
The following bits are used to configure the EUSART
for synchronous master operation:
• SYNC = 1
• CSRC = 1
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXxSTA register configures
the device for synchronous operation. Setting the CSRC
bit of the TXxSTA register configures the device as a
master. Clearing the SREN and CREN bits of the
RCxSTA register ensures that the device is in the
Transmit mode, otherwise the device will be configured
to receive. Setting the SPEN bit of the RCxSTA register
enables the EUSART.
33.5.1.1 Master Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device config-
ured as a master transmits the clock on the TX/CK line.
The TX/CK pin output driver is automatically enabled
when the EUSART is configured for synchronous
transmit or receive operation. Serial data bits change
on the leading edge to ensure they are valid at the
trailing edge of each clock. One clock cycle is gener-
ated for each data bit. Only as many clock cycles are
generated as there are data bits.
33.5.1.2 Clock Polarity
A clock polarity option is provided for Microwire
compatibility. Clock polarity is selected with the SCKP
bit of the BAUDxCON register. Setting the SCKP bit
sets the clock Idle state as high. When the SCKP bit is
set, the data changes on the falling edge of each clock.
Clearing the SCKP bit sets the Idle state as low. When
the SCKP bit is cleared, the data changes on the rising
edge of each clock.
33.5.1.3 Synchronous Master Transmission
Data is transferred out of the device on the RX/DT pin.
The RX/DT and TX/CK pin output drivers are automat-
ically enabled when the EUSART is configured for
synchronous master transmit operation.
A transmission is initiated by writing a character to the
TXxREG register. If the TSR still contains all or part of
a previous character the new character data is held in
the TXxREG until the last bit of the previous character
has been transmitted. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXxREG is immediately trans-
ferred to the TSR. The transmission of the character
commences immediately following the transfer of the
data to the TSR from the TXxREG.
Each data bit changes on the leading edge of the
master clock and remains valid until the subsequent
leading clock edge.
33.5.1.4 Synchronous Master Transmission
Set-up:
1. Initialize the SPxBRGH:SPxBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 33.4 “EUSART
Baud Rate Generator (BRG)”).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Disable Receive mode by clearing bits SREN
and CREN.
4. Enable Transmit mode by setting the TXEN bit.
5. If 9-bit transmission is desired, set the TX9 bit.
6. If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in the TX9D bit.
8. Start transmission by loading data to the
TXxREG register.
Note: The TSR register is not mapped in data
memory, so it is not available to the user.
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FIGURE 33-10: SY NCHRONOUS TRANSMISSION
FIGURE 33-11: SYNCHRONOUS TRANSM ISSION (THROUGH TXEN)
bit 0 bit 1 bit 7
Word 1
bit 2 bit 0 bit 1 bit 7
RX/DT
Write to
TXxREG Reg
TXIF bit
(Interrupt Flag)
TXEN bit ‘1’ ‘1’
Word 2
TRMT bit
Write Word 1 Write Word 2
Note: Sync Master mode, SPxBRGL = 0, continuous transmission of two 8-bit words.
pin
TX/CK pin
TX/CK pin
(SCKP = 0)
(SCKP = 1)
RX/DT pin
TX/CK pin
Write to
TXxREG reg
TXIF bit
TRMT bit
bit 0 bit 1 bit 2 bit 6 bit 7
TXEN bit
2015-2016 Microchip Technology Inc. DS40001819B-page 517
PIC16(L)F1777/8/9
TABLE 33-7: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ANSELA —— ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177
ANSELB —— ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182
ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 187
BAUD1CON ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 505
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139
RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 504
RxyPPS — — RxyPPS<5:0> 205
SP1BRGL SP1BRG<7:0> 506
SP1BRGH SP1BRG<15:8> 506
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186
TX1REG EUSART Transmit Data Register 495*
TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 503
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master transmission.
* Page provides register information.
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DS40001819B-page 518 2015-2016 Microchip Technology Inc.
33.5.1.5 Synchronous Master Reception
Data is received at the RX/DT pin. The RX/DT pin
output driver is automatically disabled when the
EUSART is configured for synchronous master receive
operation.
In Synchronous mode, reception is enabled by setting
either the Single Receive Enable bit (SREN of the
RCxSTA register) or the Continuous Receive Enable
bit (CREN of the RCxSTA register).
When SREN is set and CREN is clear, only as many
clock cycles are generated as there are data bits in a
single character. The SREN bit is automatically cleared
at the completion of one character. When CREN is set,
clocks are continuously generated until CREN is
cleared. If CREN is cleared in the middle of a character
the CK clock stops immediately and the partial charac-
ter is discarded. If SREN and CREN are both set, then
SREN is cleared at the completion of the first character
and CREN takes precedence.
To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
TX/CK clock pin and is shifted into the Receive Shift
Register (RSR). When a complete character is
received into the RSR, the RCIF bit is set and the char-
acter is automatically transferred to the two character
receive FIFO. The Least Significant eight bits of the top
character in the receive FIFO are available in RCxREG.
The RCIF bit remains set as long as there are unread
characters in the receive FIFO.
33.5.1.6 Slave Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured
as a slave receives the clock on the TX/CK line. The
TX/CK pin output driver is automatically disabled when
the device is configured for synchronous slave transmit
or receive operation. Serial data bits change on the
leading edge to ensure they are valid at the trailing edge
of each clock. One data bit is transferred for each clock
cycle. Only as many clock cycles should be received as
there are data bits.
33.5.1.7 Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before RCxREG is read to access
the FIFO. When this happens the OERR bit of the
RCxSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RCxREG. If the overrun occurred when the CREN bit is
set then the error condition is cleared by either clearing
the CREN bit of the RCxSTA register or by clearing the
SPEN bit which resets the EUSART.
33.5.1.8 Receiving 9-bit Characters
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCxSTA register is set, the EUSART
will shift nine bits into the RSR for each character
received. The RX9D bit of the RCxSTA register is the
ninth, and Most Significant, data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
from the RCxREG.
33.5.1.9 Synchronous Master Reception
Set-up:
1. Initialize the SPxBRGH:SPxBRGL register pair
for the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
2. Clear the ANSEL bit for the RX pin (if applicable).
3. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
4. Ensure bits CREN and SREN are clear.
5. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
6. If 9-bit reception is desired, set bit RX9.
7. Start reception by setting the SREN bit or for
continuous reception, set the CREN bit.
8. Interrupt flag bit RCIF will be set when reception
of a character is complete. An interrupt will be
generated if the enable bit RCIE was set.
9. Read the RCxSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
10. Read the 8-bit received data by reading the
RCxREG register.
11. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCxSTA
register or by clearing the SPEN bit which resets
the EUSART.
Note: If the RX/DT function is on an analog pin,
the corresponding ANSEL bit must be
cleared for the receiver to function.
Note: If the device is configured as a slave and
the TX/CK function is on an analog pin, the
corresponding ANSEL bit must be cleared.
2015-2016 Microchip Technology Inc. DS40001819B-page 519
PIC16(L)F1777/8/9
FIGURE 33-12: SY NCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 33-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ANSELA —— ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177
ANSELB —— ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182
ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 187
BAUD1CON ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 505
CKPPS — — CKPPS<5:0> 205, 207
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139
RC1REG EUSART Receive Data Register 498*
RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 504
RXPPS — — RXPPS<5:0> 205, 207
RxyPPS — — RxyPPS<5:0> 205
SP1BRGL SP1BRG<7:0> 506*
SP1BRGH SP1BRG<15:8> 506*
TRISA TRISA5 TRISA4 TRISA5 TRISA4 TRISA5 TRISA2 TRISA1 TRISA0 176
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186
TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 503
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master reception.
* Page provides register information.
CREN bit
RX/DT
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RCxREG
‘0’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘0’
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TX/CK pin
TX/CK pin
pin
(SCKP = 0)
(SCKP = 1)
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33.5.2 SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART
for synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXxSTA register configures
the device for synchronous operation. Clearing the
CSRC bit of the TXxSTA register configures the device as
a slave. Clearing the SREN and CREN bits of the
RCxSTA register ensures that the device is in the
Transmit mode, otherwise the device will be configured to
receive. Setting the SPEN bit of the RCxSTA register
enables the EUSART.
33.5.2.1 EUSART Synchronous Slave
Transmit
The operation of the Synchronous Master and Slave
modes are identical (see Section 33.5.1.3
“Synchronous Master Transmission”), except in the
case of the Sleep mode.
If two words are written to the TXxREG and then the
SLEEP instruction is executed, the following will occur:
1. The first character will immediately transfer to
the TSR register and transmit.
2. The second word will remain in the TXxREG
register.
3. The TXIF bit will not be set.
4. After the first character has been shifted out of
TSR, the TXxREG register will transfer the
second character to the TSR and the TXIF bit will
now be set.
5. If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
33.5.2.2 Synchronous Slave Transmission
Set-up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
2. Clear the ANSEL bit for the CK pin (if applicable).
3. Clear the CREN and SREN bits.
4. If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
5. If 9-bit transmission is desired, set the TX9 bit.
6. Enable transmission by setting the TXEN bit.
7. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
8. Start transmission by writing the Least
Significant eight bits to the TXxREG register.
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TABLE 33-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ANSELA —— ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177
ANSELB —— ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182
ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 187
BAUD1CON ABDOVF RCIDL —SCKPBRG16 —WUE ABDEN 505
CKPPS — — CKPPS<5:0> 205, 207
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139
RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 504
RXPPS — — RXPPS<5:0> 205, 207
RxyPPS — — RxyPPS<5:0> 205
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186
TX1REG EUSART Transmit Data Register 495*
TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 503
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
* Page provides register information.
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33.5.2.3 EUSART Synchronous Slave
Reception
The operation of the Synchronous Master and Slave
modes is identical (Section 33.5.1.5 “Synchronous
Master Reception” ), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
never idle
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCxREG register. If the RCIE enable bit is set,
the interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
33.5.2.4 Synchronous Slave Reception
Set-up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
2. Clear the ANSEL bit for both the CK and DT pins
(if applicable).
3. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
4. If 9-bit reception is desired, set the RX9 bit.
5. Set the CREN bit to enable reception.
6. The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
7. If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCxSTA
register.
8. Retrieve the eight Least Significant bits from the
receive FIFO by reading the RCxREG register.
9. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCxSTA
register or by clearing the SPEN bit which resets
the EUSART.
TABLE 33-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ANSELA —— ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 177
ANSELB —— ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 182
ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 187
BAUD1CON ABDOVF RCIDL —SCKPBRG16 —WUE ABDEN 505
CKPPS — — CKPPS<5:0> 205, 207
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 132
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 133
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 139
RC1REG EUSART Receive Data Register 498*
RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 504
RXPPS —— RXPPS<5:0> 205, 207
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 176
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 181
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 186
TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 503
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave reception.
* Page provides register information.
2015-2016 Microchip Technology Inc. DS40001819B-page 523
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33.6 EUSART Operation During Sleep
The EUSART will remain active during Sleep only in the
Synchronous Slave mode. All other modes require the
system clock and therefore cannot generate the neces-
sary signals to run the Transmit or Receive Shift
registers during Sleep.
Synchronous Slave mode uses an externally generated
clock to run the Transmit and Receive Shift registers.
33.6.1 SYNCHRONOUS RECEIVE DURING
SLEEP
To receive during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCxSTA and TXxSTA Control registers must be
configured for Synchronous Slave Reception (see
Section 33.5.2.4 “Synchronous Slave
Reception Set-up:”).
• If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
• The RCIF interrupt flag must be cleared by read-
ing RCxREG to unload any pending characters in
the receive buffer.
Upon entering Sleep mode, the device will be ready to
accept data and clocks on the RX/DT and TX/CK pins,
respectively. When the data word has been completely
clocked in by the external device, the RCIF interrupt
flag bit of the PIR1 register will be set. Thereby, waking
the processor from Sleep.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the Global
Interrupt Enable (GIE) bit of the INTCON register is
also set, then the Interrupt Service Routine at address
004h will be called.
33.6.2 SYNCHRONOUS TRANSMIT
DURING SLEEP
To transmit during Sleep, all the following conditions
must be met before entering Sleep mode:
• The RCxSTA and TXxSTA Control registers must
be configured for synchronous slave transmission
(see Section 33.5.2.2 “Synchronous Slave
Transmission Set-up:”).
• The TXIF interrupt flag must be cleared by writing
the output data to the TXxREG, thereby filling the
TSR and transmit buffer.
• If interrupts are desired, set the TXIE bit of the
PIE1 register and the PEIE bit of the INTCON
register.
• Interrupt enable bits TXIE of the PIE1 register and
PEIE of the INTCON register must set.
Upon entering Sleep mode, the device will be ready to
accept clocks on TX/CK pin and transmit data on the
RX/DT pin. When the data word in the TSR has been
completely clocked out by the external device, the
pending byte in the TXxREG will transfer to the TSR
and the TXIF flag will be set. Thereby, waking the pro-
cessor from Sleep. At this point, the TXxREG is avail-
able to accept another character for transmission,
which will clear the TXIF flag.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the Global
Interrupt Enable (GIE) bit is also set then the Interrupt
Service Routine at address 0004h will be called.
PIC16(L)F1777/8/9
DS40001819B-page 524 2015-2016 Microchip Technology Inc.
34.0 IN-CIRCUIT SERIAL
PROGRAMMING™ (ICSP™)
ICSP™ programming allows customers to manufacture
circuit boards with unprogrammed devices. Programming
can be done after the assembly process, allowing the
device to be programmed with the most recent firmware
or a custom firmware. Five pins are needed for ICSP™
programming:
• ICSPCLK
• ICSPDAT
•MCLR
/VPP
•VDD
•VSS
In Program/Verify mode the program memory, User IDs
and the Configuration Words are programmed through
serial communications. The ICSPDAT pin is a
bidirectional I/O used for transferring the serial data
and the ICSPCLK pin is the clock input. For more
information on ICSP™ refer to the “PIC16(L)F177X
Memory Programming Specification” (DS40001792).
34.1 High-Voltage Programming Entry
Mode
The device is placed into High-Voltage Programming
Entry mode by holding the ICSPCLK and ICSPDAT
pins low then raising the voltage on MCLR/VPP to VIHH.
34.2 Low-Voltage Programming Entry
Mode
The Low-Voltage Programming Entry mode allows the
PIC® Flash MCUs to be programmed using VDD only,
without high voltage. When the LVP bit of Configuration
Words is set to ‘1’, the low-voltage ICSP programming
entry is enabled. To disable the Low-Voltage ICSP
mode, the LVP bit must be programmed to ‘0’.
Entry into the Low-Voltage Programming Entry mode
requires the following steps:
1. MCLR is brought to VIL.
2. A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
If low-voltage programming is enabled (LVP = 1), the
MCLR Reset function is automatically enabled and
cannot be disabled. See Sec tion 6.5 “MCLR” for more
information.
The LVP bit can only be reprogrammed to ‘0’ by using
the High-Voltage Programming mode.
34.3 Common Programming Interfaces
Connection to a target device is typically done through
an ICSP™ header. A commonly found connector on
development tools is the RJ-11 in the 6P6C (6-pin,
6-connector) configuration. See Figure 34-1.
FIGURE 34-1: ICD RJ-11 STYLE
CONNECTOR INTERFACE
Another connector often found in use with the PICkit™
programmers is a standard 6-pin header with 0.1 inch
spacing. Refer to Figure 34-2.
For additional interface recommendations, refer to your
specific device programmer manual prior to PCB
design.
It is recommended that isolation devices be used to
separate the programming pins from other circuitry.
The type of isolation is highly dependent on the specific
application and may include devices such as resistors,
diodes, or even jumpers. See Figure 34-3 for more
information.
1
2
3
4
5
6
Target
Bottom Side
PC Board
VPP/MCLR VSS
ICSPCLK
VDD
ICSPDAT
NC
Pin Description*
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
2015-2016 Microchip Technology Inc. DS40001819B-page 525
PIC16(L)F1777/8/9
FIGURE 34-2: PI Ckit™ PROGRAMME R STYLE CONNECTOR INTERFACE
FIGURE 34-3: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
1
2
3
4
5
6
* The 6-pin header (0.100" spacing) accepts 0.025" square pins.
Pin Description*
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
Pin 1 Indicator
VDD
VPP
VSS
External
Device to be
Data
Clock
VDD
MCLR/VPP
VSS
ICSPDAT
ICSPCLK
**
*
To Normal Connections
*Isolation devices (as required).
Programming
Signals Programmed
VDD
PIC16(L)F1777/8/9
DS40001819B-page 526 2015-2016 Microchip Technology Inc.
35.0 INSTRUCTION SET SUMMARY
Each instruction is a 14-bit word containing the opera-
tion code (opcode) and all required operands. The
opcodes are broken into three broad categories.
• Byte Oriented
• Bit Oriented
• Literal and Control
The literal and control category contains the most
varied instruction word format.
Table 35-3 lists the instructions recognized by the
MPASMTM assembler.
All instructions are executed within a single instruction
cycle, with the following exceptions, which may take
two or three cycles:
• Subroutine takes two cycles (CALL, CALLW)
• Returns from interrupts or subroutines take two
cycles (RETURN, RETLW, RETFIE)
• Program branching takes two cycles (GOTO, BRA,
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)
• One additional instruction cycle will be used when
any instruction references an indirect file register
and the file select register is pointing to program
memory.
One instruction cycle consists of four oscillator cycles;
for an oscillator frequency of 4 MHz, this gives a
nominal instruction execution rate of 1 MHz.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
35.1 Read-Modify-Write Operations
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
TABLE 35-1: OPCODE FIELD
DESCRIPTIONS
TABLE 35-2: ABBREVIATION
DESCRIPTIONS
Field Description
fRegister file address (0x00 to 0x7F)
WWorking register (accumulator)
bBit address within an 8-bit file register
kLiteral field, constant data or label
xDon’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
dDestination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
nFSR or INDF number. (0-1)
mm Pre-post increment-decrement mode
selection
Field Description
PC Program Counter
TO Time-Out bit
CCarry bit
DC Digit Carry bit
ZZero bit
PD Power-Down bit
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PIC16(L)F1777/8/9
FIGURE 35-1: GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operati ons
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 7-bit file register address
Bit-oriente d file register operations
13 10 9 7 6 0
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
13 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value
General
CALL and GOTO instructions only
MOVLP instruction only
13 5 4 0
OPCODE k (literal)
k = 5-bit immediate value
MOVLB instruction only
13 9 8 0
OPCODE k (literal)
k = 9-bit immediate value
BRA instruction only
FSR Offset instructions
13 7 6 5 0
OPCODE n k (literal)
n = appropriate FSR
FSR Increment instructions
13 7 6 0
OPCODE k (literal)
k = 7-bit immediate value
13 3 2 1 0
OPCODE n m (mode)
n = appropriate FSR
m = 2-bit mode value
k = 6-bit immediate value
13 0
OPCODE
OPCODE only
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TABLE 35-3: INSTRUCTION SET
Mnemonic,
Operands Description Cycles 14-Bit Opcode Status
Affected Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC
ANDWF
ASRF
LSLF
LSRF
CLRF
CLRW
COMF
DECF
INCF
IORWF
MOVF
MOVWF
RLF
RRF
SUBWF
SUBWFB
SWAPF
XORWF
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
Add W and f
Add with Carry W and f
AND W with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
Clear W
Complement f
Decrement f
Increment f
Inclusive OR W with f
Move f
Move W to f
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract with Borrow W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
00
11
00
11
11
11
00
00
00
00
00
00
00
00
00
00
00
11
00
00
0111
1101
0101
0111
0101
0110
0001
0001
1001
0011
1010
0100
1000
0000
1101
1100
0010
1011
1110
0110
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
1fff
dfff
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
00xx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
C, DC, Z
C, DC, Z
Z
C, Z
C, Z
C, Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
C, DC, Z
Z
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BYTE ORIENTED SKIP OPERATIONS
DECFSZ
INCFSZ
f, d
f, d
Decrement f, Skip if 0
Increment f, Skip if 0
1(2)
1(2)
00
00 1011
1111 dfff
dfff ffff
ffff
1, 2
1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
f, b
f, b
Bit Clear f
Bit Set f
1
1
01
01 00bb
01bb bfff
bfff ffff
ffff
2
2
BIT-ORIENTED SKIP OPERATIONS
BTFSC
BTFSS
f, b
f, b
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1 (2)
1 (2)
01
01 10bb
11bb bfff
bfff ffff
ffff
1, 2
1, 2
LITERAL OPE RATIONS
ADDLW
ANDLW
IORLW
MOVLB
MOVLP
MOVLW
SUBLW
XORLW
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Inclusive OR literal with W
Move literal to BSR
Move literal to PCLATH
Move literal to W
Subtract W from literal
Exclusive OR literal with W
1
1
1
1
1
1
1
1
11
11
11
00
11
11
11
11
1110
1001
1000
0000
0001
0000
1100
1010
kkkk
kkkk
kkkk
001k
1kkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z
Z
Z
C, DC, Z
Z
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
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TABLE 35-3: INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands Description Cycles 14-Bit Opcode Status
Affected Notes
MSb LSb
CONTROL OPERATIONS
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
k
–
k
–
k
k
k
–
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
2
2
2
2
2
2
2
2
11
00
10
00
10
00
11
00
001k
0000
0kkk
0000
1kkk
0000
0100
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
1011
kkkk
1010
kkkk
1001
kkkk
1000
INHERENT OPERATIONS
CLRWDT
NOP
OPTION
RESET
SLEEP
TRIS
–
–
–
–
–
f
Clear Watchdog Timer
No Operation
Load OPTION_REG register with W
Software device Reset
Go into Standby mode
Load TRIS register with W
1
1
1
1
1
1
00
00
00
00
00
00
0000
0000
0000
0000
0000
0000
0110
0000
0110
0000
0110
0110
0100
0000
0010
0001
0011
0fff
TO, PD
TO, PD
C-COMPILER OPTIMIZED
ADDFSR
MOVIW
MOVWI
n, k
n mm
k[n]
n mm
k[n]
Add Literal k to FSRn
Move Indirect FSRn to W with pre/post inc/dec
modifier, mm
Move INDFn to W, Indexed Indirect.
Move W to Indirect FSRn with pre/post inc/dec
modifier, mm
Move W to INDFn, Indexed Indirect.
1
1
1
1
1
11
00
11
00
11
0001
0000
1111
0000
1111
0nkk
0001
0nkk
0001
1nkk
kkkk
0nmm
kkkk
1nmm
kkkk
Z
Z
2, 3
2
2, 3
2
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Table in the MOVIW and MOVWI instruction descriptions.
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35.2 Instruction Descripti ons
ADDFSR Add Literal to FSRn
Syntax: [ label ] ADDFSR FSRn, k
Operands: -32 k 31
n [ 0, 1]
Operation: FSR(n) + k FSR(n)
Status Affected: None
Description: The signed 6-bit literal ‘k’ is added to
the contents of the FSRnH:FSRnL
register pair.
FSRn is limited to the range
0000h-FFFFh. Moving beyond these
bounds will cause the FSR to
wrap-around.
ADDLW Add literal and W
Syntax: [ label ] ADDLW k
Operands: 0 k 255
Operation: (W) + k (W)
Status Affected: C, DC, Z
Description: The contents of the W register are
added to the 8-bit literal ‘k’ and the
result is placed in the W register.
ADDWF Add W and f
Syntax: [ label ] ADDWF f,d
Operands: 0 f 127
d 0,1
Operation: (W) + (f) (destination)
Status Affected: C, DC, Z
Description: Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the result is
stored in the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
ADDWFC ADD W and CARRY bit to f
Syntax: [ label ] ADDWFC f {,d}
Operands: 0 f 127
d [0,1]
Operation: (W) + (f) + (C) dest
Status Affected: C, DC, Z
Description: Add W, the Carry flag and data mem-
ory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
ANDLW AND literal with W
Syntax: [ label ] ANDLW k
Operands: 0 k 255
Operation: (W) .AND. (k) (W)
Status Affected: Z
Description: The contents of W register are
AND’ed with the 8-bit literal ‘k’. The
result is placed in the W register.
ANDWF AND W with f
Syntax: [ label ] ANDWF f,d
Operands: 0 f 127
d 0,1
Operation: (W) .AND. (f) (destination)
Status Affected: Z
Description: AND the W register with register ‘f’. If
‘d’ is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
ASRF Arithmetic Right Shift
Syntax: [ label ] ASRF f {,d}
Operands: 0 f 127
d [0,1]
Operation: (f<7>) dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected: C, Z
Description: The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.
register f C
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BCF Bit Clear f
Syntax: [ label ] BCF f,b
Operands: 0 f 127
0 b 7
Operation: 0 (f<b>)
Status Affected: None
Description: Bit ‘b’ in register ‘f’ is cleared.
BRA Relative Branch
Syntax: [ label ] BRA label
[ label ] BRA $+k
Operands: -256 label - PC + 1 255
-256 k 255
Operation: (PC) + 1 + k PC
Status Affected: None
Description: Add the signed 9-bit literal ‘k’ to the
PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 1 + k. This instruction is a
2-cycle instruction. This branch has a
limited range.
BRW Relative Branch with W
Syntax: [ label ] BRW
Operands: None
Operation: (PC) + (W) PC
Status Affected: None
Description: Add the contents of W (unsigned) to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 1 + (W). This instruction is a
2-cycle instruction.
BSF Bit Set f
Syntax: [ label ] BSF f,b
Operands: 0 f 127
0 b 7
Operation: 1 (f<b>)
Status Affected: None
Description: Bit ‘b’ in register ‘f’ is set.
BTFSC Bit Test f, Skip if Clear
Syntax: [ label ] BTFSC f,b
Operands: 0 f 127
0 b 7
Operation: skip if (f<b>) = 0
Status Affected: None
Description: If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOP is
executed instead, making this a
2-cycle instruction.
BTFSS Bit Test f, Skip if Set
Syntax: [ label ] BTFSS f,b
Operands: 0 f 127
0 b < 7
Operation: skip if (f<b>) = 1
Status Affected: None
Description: If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next instruction
is discarded and a NOP is executed
instead, making this a 2-cycle
instruction.
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CALL Call Subroutine
Syntax: [ label ] CALL k
Operands: 0 k 2047
Operation: (PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<6:3>) PC<14:11>
Status Affected: None
Description: Call Subroutine. First, return address
(PC + 1) is pushed onto the stack.
The 11-bit immediate address is
loaded into PC bits <10:0>. The upper
bits of the PC are loaded from
PCLATH. CALL is a 2-cycle
instruction.
CALLW Subroutine Call With W
Syntax: [ label ] CALLW
Operands: None
Operation: (PC) +1 TOS,
(W) PC<7:0>,
(PCLATH<6:0>) PC<14:8>
Status Affected: None
Description: Subroutine call with W. First, the
return address (PC + 1) is pushed
onto the return stack. Then, the
contents of W is loaded into PC<7:0>,
and the contents of PCLATH into
PC<14:8>. CALLW is a 2-cycle
instruction.
CLRF Clear f
Syntax: [ label ] CLRF f
Operands: 0 f 127
Operation: 00h (f)
1 Z
Status Affected: Z
Description: The contents of register ‘f’ are cleared
and the Z bit is set.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h (W)
1 Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z) is
set.
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h WDT
0 WDT prescaler,
1 TO
1 PD
Status Affected: TO, PD
Description: CLRWDT instruction resets the Watch-
dog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD
are set.
COMF Complement f
Syntax: [ label ] COMF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (destination)
Status Affected: Z
Description: The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
DECF Decrement f
Syntax: [ label ] DECF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - 1 (destination)
Status Affected: Z
Description: Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.
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DECFSZ Decrement f, Skip if 0
Syntax: [ label ] DECFSZ f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - 1 (destination);
skip if result = 0
Status Affected: None
Description: The contents of register ‘f’ are decre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, then a
NOP is executed instead, making it a
2-cycle instruction.
GOTO Unconditional Branch
Syntax: [ label ] GOTO k
Operands: 0 k 2047
Operation: k PC<10:0>
PCLATH<6:3> PC<14:11>
Status Affected: None
Description: GOTO is an unconditional branch. The
11-bit immediate value is loaded into
PC bits <10:0>. The upper bits of PC
are loaded from PCLATH<4:3>. GOTO
is a 2-cycle instruction.
INCF Increment f
Syntax: [ label ] INCF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) + 1 (destination)
Status Affected: Z
Description: The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
INCFSZ Increment f, Skip if 0
Syntax: [ label ] INCFSZ f,d
Operands: 0 f 127
d [0,1]
Operation: (f) + 1 (destination),
skip if result = 0
Status Affected: None
Description: The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, a NOP is
executed instead, making it a 2-cycle
instruction.
IORLW Inclusive OR literal with W
Syntax: [ label ] IORLW k
Operands: 0 k 255
Operation: (W) .OR. k (W)
Status Affected: Z
Description: The contents of the W register are
OR’ed with the 8-bit literal ‘k’. The
result is placed in the W register.
IORWF Inclusive OR W with f
Syntax: [ label ] IORWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .OR. (f) (destination)
Status Affected: Z
Description: Inclusive OR the W register with regis-
ter ‘f’. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
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LSLF Logical Left Shift
Syntax: [ label ] LSLF f {,d}
Operands: 0 f 127
d [0,1]
Operation: (f<7>) C
(f<6:0>) dest<7:1>
0 dest<0>
Status Affected: C, Z
Description: The contents of register ‘f’ are shifted
one bit to the left through the Carry flag.
A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’,
the result is placed in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
LSRF Logical Right Shift
Syntax: [ label ] LSRF f {,d}
Operands: 0 f 127
d [0,1]
Operation: 0 dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected: C, Z
Description: The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. A ‘0’ is shifted into the MSb. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
register f 0
C
register f C0
MOVF Move f
Syntax: [ label ] MOVF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (dest)
Status Affected: Z
Description: The contents of register f is moved to
a destination dependent upon the
status of d. If d = 0, destination is W
register. If d = 1, the destination is file
register f itself. d = 1 is useful to test a
file register since status flag Z is
affected.
Words: 1
Cycles: 1
Example: MOVF FSR, 0
After Instruction
W = value in FSR register
Z= 1
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PIC16(L)F1777/8/9
MOVIW Move INDFn to W
Syntax: [ label ] MOVIW ++FSRn
[ label ] MOVIW --FSRn
[ label ] MOVIW FSRn++
[ label ] MOVIW FSRn--
[ label ] MOVIW k[FSRn]
Operands: n [0,1]
mm [00,01, 10, 11]
-32 k 31
Operation: INDFn W
Effective address is determined by
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
• FSR + 1 (all increments)
• FSR - 1 (all decrements)
• Unchanged
Status Affected: Z
Mode Syntax mm
Preincrement ++FSRn 00
Predecrement --FSRn 01
Postincrement FSRn++ 10
Postdecrement FSRn-- 11
Description: This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
FSRn is limited to the range 0000h -
FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to
wrap-around.
MOVLB Move literal to BSR
Syntax: [ label ] MOVLB k
Operands: 0 k 31
Operation: k BSR
Status Affected: None
Description: The 5-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).
MOVLP Move literal to PCLATH
Syntax: [ label ] MOVLP k
Operands: 0 k 127
Operation: k PCLATH
Status Affected: None
Description: The 7-bit literal ‘k’ is loaded into the
PCLATH register.
MOVLW Move literal t o W
Syntax: [ label ] MOVLW k
Operands: 0 k 255
Operation: k (W)
Status Affected: None
Description: The 8-bit literal ‘k’ is loaded into W reg-
ister. The “don’t cares” will assemble as
‘0’s.
Words: 1
Cycles: 1
Example: MOVLW 0x5A
After Instruction
W = 0x5A
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Operands: 0 f 127
Operation: (W) (f)
Status Affected: None
Description: Move data from W register to register
‘f’.
Words: 1
Cycles: 1
Example: MOVWF OPTION_REG
Before Instruction
OPTION_REG = 0xFF
W = 0x4F
After Instruction
OPTION_REG = 0x4F
W = 0x4F
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MOVWI Move W to INDFn
Syntax: [ label ] MOVWI ++FSRn
[ label ] MOVWI --FSRn
[ label ] MOVWI FSRn++
[ label ] MOVWI FSRn--
[ label ] MOVWI k[FSRn]
Operands: n [0,1]
mm [00,01, 10, 11]
-32 k 31
Operation: W INDFn
Effective address is determined by
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
• FSR + 1 (all increments)
• FSR - 1 (all decrements)
Unchanged
Status Affected: None
Mode Syntax mm
Preincrement ++FSRn 00
Predecrement --FSRn 01
Postincrement FSRn++ 10
Postdecrement FSRn-- 11
Description: This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
FSRn is limited to the range
0000h-FFFFh.
Incrementing/decrementing it beyond
these bounds will cause it to
wrap-around.
The increment/decrement operation on
FSRn WILL NOT affect any Status bits.
NOP No Operation
Syntax: [ label ] NOP
Operands: None
Operation: No operation
Status Affected: None
Description: No operation.
Words: 1
Cycles: 1
Example: NOP
OPTION Load OPTION_REG Register
with W
Syntax: [ label ] OPTION
Operands: None
Operation: (W) OPTION_REG
Status Affected: None
Description: Move data from W register to
OPTION_REG register.
Words: 1
Cycles: 1
Example: OPTION
Before Instruction
OPTION_REG = 0xFF
W = 0x4F
After Instruction
OPTION_REG = 0x4F
W = 0x4F
RESET Software Reset
Syntax: [ label ] RESET
Operands: None
Operation: Execute a device Reset. Resets the
RI flag of the PCON register.
Status Affected: None
Description: This instruction provides a way to
execute a hardware Reset by
software.
2015-2016 Microchip Technology Inc. DS40001819B-page 537
PIC16(L)F1777/8/9
RETFIE Return from Interrupt
Syntax: [ label ] RETFIE k
Operands: None
Operation: TOS PC,
1 GIE
Status Affected: None
Description: Return from Interrupt. Stack is POPed
and Top-of-Stack (TOS) is loaded in
the PC. Interrupts are enabled by
setting Global Interrupt Enable bit,
GIE (INTCON<7>). This is a 2-cycle
instruction.
Words: 1
Cycles: 2
Example: RETFIE
After Interrupt
PC = TOS
GIE = 1
RETLW Return with literal in W
Syntax: [ label ] RETLW k
Operands: 0 k 255
Operation: k (W);
TOS PC
Status Affected: None
Description: The W register is loaded with the 8-bit
literal ‘k’. The program counter is
loaded from the top of the stack (the
return address). This is a 2-cycle
instruction.
Words: 1
Cycles: 2
Example:
TABLE
CALL TABLE;W contains table
;offset value
• ;W now has table value
•
•
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
•
•
•
RETLW kn ; End of table
Before Instruction
W = 0x07
After Instruction
W = value of k8
RETURN Return from Subroutine
Syntax: [ label ] RETURN
Operands: None
Operation: TOS PC
Status Affected: None
Description: Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a 2-cycle instruction.
RLF Rotate Left f through Carry
Syntax: [ label ] RLF f,d
Operands: 0 f 127
d [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ‘f’ are rotated
one bit to the left through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Words: 1
Cycles: 1
Example: RLF REG1,0
Before Instruction
REG1 = 1110 0110
C=0
After Instruction
REG1 = 1110 0110
W = 1100 1100
C=1
Register fC
PIC16(L)F1777/8/9
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RRF Rotate Right f through Carry
Syntax: [ label ] RRF f,d
Operands: 0 f 127
d [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
SLEEP Enter Sleep mode
Syntax: [ label ]SLEEP
Operands: None
Operation: 00h WDT,
0 WDT prescaler,
1 TO,
0 PD
Status Affected: TO, PD
Description: The power-down Status bit, PD is
cleared. Time-out Status bit, TO is
set. Watchdog Timer and its
prescaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
Register fC
SUBLW Subtract W from literal
Syntax: [ label ]SUBLW k
Operands: 0 k 255
Operation: k - (W) W)
Status Affected: C, DC, Z
Description: The W register is subtracted (2’s
complement method) from the 8-bit
literal ‘k’. The result is placed in the W
register.
SUBWF Subtract W from f
Syntax: [ label ] SUBWF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - (W) destination)
Status Affected: C, DC, Z
Description: Subtract (2’s complement method) W
register from register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If ‘d’ is
‘1’, the result is stored back in register
‘f.
SUBWFB Subtract W from f with Borrow
Syntax: SUBWFB f {,d}
Operands: 0 f 127
d [0,1]
Operation: (f) – (W) – (B) dest
Status Affected: C, DC, Z
Description: Subtract W and the BORROW flag
(CARRY) from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
C = 0W k
C = 1W k
DC = 0W<3:0> k<3:0>
DC = 1W<3:0> k<3:0>
C = 0W f
C = 1W f
DC = 0W<3:0> f<3:0>
DC = 1W<3:0> f<3:0>
2015-2016 Microchip Technology Inc. DS40001819B-page 539
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SWAPF Swap Nibbles in f
Syntax: [ label ] SWAPF f,d
Operands: 0 f 127
d [0,1]
Operation: (f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Status Affected: None
Description: The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is ‘0’,
the result is placed in the W register. If
‘d’ is ‘1’, the result is placed in register
‘f’.
TRIS Load TRIS Register with W
Syntax: [ label ] TRIS f
Operands: 5 f 7
Operation: (W) TRIS register ‘f’
Status Affected: None
Description: Move data from W register to TRIS
register.
When ‘f’ = 5, TRISA is loaded.
When ‘f’ = 6, TRISB is loaded.
When ‘f’ = 7, TRISC is loaded.
XORLW Exclusive OR literal with W
Syntax: [ label ]XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k W)
Status Affected: Z
Description: The contents of the W register are
XOR’ed with the 8-bit literal ‘k’. The
result is placed in the W register.
XORWF Exclusive OR W with f
Syntax: [ label ] XORWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .XOR. (f) destination)
Status Affected: Z
Description: Exclusive OR the contents of the W
register with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.
PIC16(L)F1777/8/9
DS40001819B-page 540 2015-2016 Microchip Technology Inc.
36.0 ELECTRICAL SPECIFICATIONS
36.1 Absolute Maximum Ratings(†)
Ambient temperature under bias...................................................................................................... -40°C to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on pins with respect to VSS
on VDD pin
PIC16F1777/8/9 ........................................................................................................ -0.3V to +6.5V
PIC16LF1777/8/9 ...................................................................................................... -0.3V to +4.0V
on MCLR pin ........................................................................................................................... -0.3V to +9.0V
on all other pins ............................................................................................................ -0.3V to (VDD + 0.3V)
Maximum current
on VSS pin(1)
-40°C TA +85°C .............................................................................................................. 350 mA
-40°C TA +125°C ............................................................................................................ 120 mA
on VDD pin(1) PIC16(L)F1778 only
-40°C TA +85°C .............................................................................................................. 250 mA
-40°C TA +125°C .............................................................................................................. 85 mA
on VDD pin(1) PIC16(L)F1777/9 only
-40°C TA +85°C .............................................................................................................. 350 mA
-40°C TA +125°C ............................................................................................................ 120 mA
Sunk by any standard I/O pin ............................................................................................................... 50 mA
Sourced by any standard I/O pin .......................................................................................................... 50 mA
Sunk by any High Current I/O pin ....................................................................................................... 100 mA
Sourced by any High Current I/O pin .................................................................................................. 100 mA
Sourced by any Op Amp output pin .................................................................................................... 100 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA
Total power dissipation(2) ...............................................................................................................................800 mW
Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be
limited by the device package power dissipation characterizations, see Table 36-6: Thermal
Characteristics to calculate device specifications.
2: Power dissipation is calculated as follows:
Pdis = VDD* {Idd- ΣIoh} + Σ{VDD-Voh)*Ioh} + Σ(Vol*IoI).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
2015-2016 Microchip Technology Inc. DS40001819B-page 541
PIC16(L)F1777/8/9
36.2 Standard Oper ating Conditions
The standard operating conditions for any device are defined as:
Operating Voltage: VDDMIN VDD VDDMAX
Operating Temperature: TA_MIN TA TA_MAX
VDD — Operating Supply Voltage(1)
PIC16LF1777/8/9
VDDMIN (Fosc 16 MHz) ......................................................................................................... +1.8V
VDDMIN (Fosc 16 MHz) ......................................................................................................... +2.5V
VDDMAX .................................................................................................................................... +3.6V
PIC16F1777/8/9
VDDMIN (Fosc 16 MHz) ......................................................................................................... +2.3V
VDDMIN (Fosc 16 MHz).......................................................................................................... +2.5V
VDDMAX .................................................................................................................................... +5.5V
TA — Operating Ambient Temperature Range
Industrial Temperature
TA_MIN ...................................................................................................................................... -40°C
TA_MAX .................................................................................................................................... +85°C
Extended Temperature
TA_MIN ...................................................................................................................................... -40°C
TA_MAX .................................................................................................................................. +125°C
Note 1: See Parameter D001, DS Characteristics: Supply Voltage.
PIC16(L)F1777/8/9
DS40001819B-page 542 2015-2016 Microchip Technology Inc.
FIGURE 36-1: VOLT AGE FREQUENCY GRAPH, -40°C
TA

+125°C, PIC16F1777/8/9 ONLY
FIGURE 36-2: VOLT AGE FREQUENCY GRAPH, -40°C
TA

+125°C, PIC16LF1777/8/9 ONLY
0
2.5
Frequency (MHz)
VDD (V)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 36-7 for each Oscillator mode’s supported frequencies.
432
10 16
5.5
2.3
1.8
0
2.5
Frequency (MHz )
VDD (V)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 36-7 for each Oscillator mode’s supported frequencies.
43210 16
3.6
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PIC16(L)F1777/8/9
36.3 DC Characteristics
TABLE 36-1: SUPPLY VOLTAGE
PIC16LF1777/8/9 Standa rd Operating Conditions (unless otherwise stated)
PIC16F1777/8/9
Param.
No. Sym. Characteristic Min. Typ† Max. Units Conditions
D001 VDD Supply Voltage
VDDMIN
1.8
2.5
—
—
VDDMAX
3.6
3.6
V
V
FOSC 16 MHz
FOSC 32 MHz
D001 PIC16F1777/8/9 2.3
2.5
—
—
5.5
5.5
V
V
FOSC 16 MHz
FOSC 32 MHz
D002* VDR RAM Data Retention Voltage(1)
1.5 — — V Device in Sleep mode
D002* 1.7 — — V Device in Sleep mode
D002A* VPOR Power-on Reset Release Voltage
—1.6 — V
D002A* —1.6 — V
D002B* VPORR*Power-on Reset Rearm Voltage(2)
—0.8 — V
D002B* —1.5 — V
D003 VFVR Fixed Voltag e Reference Voltage(3) -4
-4
-7
—
—
—
+4
+4
+7
%
%
%
1x gain, 1.024, VDD 2.5V, -40°C to +85°C
2x gain, 2.048, VDD 2.5V, -40°C to +85°C
4x gain, 4.096, VDD 4.5V, -40°C to +85°C
D004* SVDD VDD Rise Rate 0.05 — — V/ms Ensures that the Power-on Reset
signal is released properly.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: See Figure 36-3: POR and POR Rearm with Slow Rising VDD.
3: Industrial temperature range only.
PIC16(L)F1777/8/9
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FIGURE 36-3: POR AND POR REARM WITH SLOW RISING VDD
VDD
VPOR
VPORR
VSS
VSS
NPOR(1)
TPOR(3)
POR REARM
Note 1: When NPOR is low, the device is held in Reset.
2: TVLOW 1 s typical.
3: TPOR 2.7 s typical.
TVLOW(2)
SVDD
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PIC16(L)F1777/8/9
TABLE 36-2: SUPPLY CURRENT (IDD)(1,2)
PIC16LF1777/8/9 Standard Operating Conditions (unless otherwise stated)
PIC16F1777/8/9
Param
No. Device
Characteristics Min. Typ† Max. Units Conditions
VDD Note
D009 LDO Regulator —75 — A—
High-Power mode, normal operation
—15 — A—
Sleep, VREGCON<1> = 0
—0.3 — A—
Sleep, VREGCON<1> = 1
D010 —8 25
A1.8
FOSC = 32 kHz,
LP Oscillator mode (Note 4),
-40°C TA +85°C
—12 30A3.0
D010 —21 30 A2.3 FOSC = 32 kHz,
LP Oscillator mode (Note 4,5)
-40°C TA +85°C
—25 34 A3.0
—26 35 A5.0
D012 — 210 440 A1.8FOSC = 4 MHz,
XT Oscillator mode
— 390 620 A3.0
D012 —320 530 A2.3 FOSC = 4 MHz,
XT Oscillator mode (No te 5)
—430 680 A3.0
—530 790 A5.0
D014 — 170 380 A1.8FOSC = 4 MHz,
External Clock (ECM),
Medium Power mode
— 320 550 A3.0
D014 —250 513 A2.3 FOSC = 4 MHz,
External Clock (ECM),
Medium Power mode
—360 645 A3.0
—430 735 A5.0
D015 — 2.5 3.8 mA 3.0 FOSC = 32 MHz,
External Clock (ECH),
High-Power mode (Note 5)
—3.14.0mA 3.6
D015 —2.5 4.3 mA 3.0 FOSC = 32 MHz,
External Clock (ECH),
High-Power mode (Note 5)
—2.7 4.6 mA 5.0
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For EXTRC oscillator configurations, current through REXT is not included. The current through the resistor can be
extended by the formula IR = VDD/2REXT (mA) with REXT in k
4: FVR and BOR are disabled.
5: 8 MHz crystal/oscillator with 4x PLL enabled.
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DS40001819B-page 546 2015-2016 Microchip Technology Inc.
D017 — 115 190 A1.8FOSC = 500 kHz,
MFINTOSC mode
— 145 320 A3.0
D017 —160 215 A2.3 FOSC = 500 kHz,
MFINTOSC mode
—180 340 A3.0
—230 420 A5.0
D019 — 0.9 1.5 mA 1.8 FOSC = 16 MHz,
HFINTOSC mode
—1.52.3mA 3.0
D019 —1.2 2.0 mA 2.3 FOSC = 16 MHz,
HFINTOSC mode
—1.5 2.5 mA 3.0
—1.7 2.6 mA 5.0
D020 — 2.9 4.2 mA 3.0 FOSC = 32 MHz,
HFINTOSC mode (Note 5)
—3.54.3mA 3.6
D020 —2.9 4.2 mA 3.0 FOSC = 32 MHz,
HFINTOSC mode (Note 5)
—3.0 5.0 mA 5.0
D022 — 2.8 4 mA 3.0 FOSC = 32 MHz,
HS Oscillator mode (Note 5)
—3.44.7mA 3.6
D022 —2.9 4mA 3.0 FOSC = 32 MHz
HS Oscillator mode (Note 5)
—3.1 4.5 mA 5.0
TABLE 36-2: SUPPLY CURRENT (IDD)(1,2) (CONTINUED)
PIC16LF1777/8/9 Standard Operating Conditions (unless otherwise stated)
PIC16F1777/8/9
Param
No. Device
Characteristics Min. Typ† Max. Units Conditions
VDD Note
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For EXTRC oscillator configurations, current through REXT is not included. The current through the resistor can be
extended by the formula IR = VDD/2REXT (mA) with REXT in k
4: FVR and BOR are disabled.
5: 8 MHz crystal/oscillator with 4x PLL enabled.
2015-2016 Microchip Technology Inc. DS40001819B-page 547
PIC16(L)F1777/8/9
TABLE 36-3: POWER-DOWN CURRENTS (IPD)(1,2)
PIC16LF1777/8/9 Operating Conditions: (u nless otherwise stated)
Low-Power Sleep Mode
PIC16F1777/8/9 Low -P ow e r Sl eep Mode, VREG PM = 1
Param
No. Device Characteristics Min. Typ† Max.
+85°C Max.
+125°C Units Conditions
VDD Note
D023 Base IPD — 0.05 1.0 8.0 A 1.8 WDT, BOR, FVR, and SOSC
disabled, all Peripherals Inactive
— 0.08 2.0 9.0 A3.0
D023 Base IPD —0.3 2.4 10 A2.3 WDT, BOR, FVR, and SOSC
disabled, all Peripherals Inactive,
Low-Power Sleep mode
—0.4 412 A3.0
—0.5 615 A5.0
D023A Base IPD —9.8 17 28 A2.3 WDT, BOR, FVR and SOSC
disabled, all Peripherals inactive,
Normal Power Sleep mode
VREGPM = 0
—10.3 20 40 A3.0
—11.5 22 44 A5.0
D024 — 0.5 6 14 A 1.8 WDT Current
—0.8 7 17 A3.0
D024 —0.8 615 A2.3 WDT Current
—0.9 720 A3.0
—1.0 822 A5.0
D025 — 15 28 30 A 1.8 FVR Current (ADC)
—24 35 38 A3.0
D025 —18 33 35 A2.3 FVR Current (ADC)
—24 35 40 A3.0
—26 37 44 A5.0
D025A — 25 50 55 A 1.8 FVR Current (DAC)
—30 65 70 A3.0
D025A —30 55 66 A2.3 FVR Current (DAC)
—32 68 82 A3.0
—35 77 90 A5.0
D026 — 7.5 25 28 A 3.0 BOR Current
D026 —10 25 28 A3.0 BOR Current
—12 28 31 A5.0
D027 — 0.5 4 10 A 3.0 LPBOR Current
D027 —0.8 615 A3.0 LPBOR Current
— 1 8 17 A5.0
D028 — 0.5 5 9 A 1.8 SOSC Current
—0.88.5 12 A3.0
D028 —1.1 610 A2.3 SOSC Current
—1.3 8.5 20 A3.0
—1.4 10 25 A5.0
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IPD and the additional current consumed when this peripheral is enabled.
The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should
be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS.
3: ADC clock source is FRC.
PIC16(L)F1777/8/9
DS40001819B-page 548 2015-2016 Microchip Technology Inc.
D029 — 0.05 2 9 A 1.8 ADC Current (Note 3),
no conversion in progress
—0.08 3 10 A3.0
D029 —0.3 412 A2.3 ADC Current (Note 3),
no conversion in progress
—0.4 513 A3.0
—0.5 716 A5.0
D030 — 250 — — A 1.8 ADC Current (Note 3),
conversion in progress
—250 — — A3.0
D030 —280 — — A2.3 ADC Current (Note 3),
conversion in progress
—280 — — A3.0
—280 — — A5.0
D031 — 250 650 — A 3.0 Op Amp (High power)
D031 —250 650 —A3.0 Op Amp (High power)
—350 850 —A5.0
D032 — 250 600 — A 1.8 Comparator, CxSP = 0
— 300 650 — A3.0
D032 —280 600 —A2.3 Comparator, CxSP = 0
VREGPM = 0
—300 650 —A3.0
—310 650 —A5.0
TABLE 36-3: POWER-DOWN CURRENTS (IPD)(1,2) (CONTINUED )
PIC16LF1777/8/9 Operating Conditions: (u nless otherwise stated)
Low-Power Sleep Mode
PIC16F1777/8/9 Low-Power Sleep Mode, VREGPM = 1
Param
No. Device Characteristics Min. Typ† Max.
+85°C Max.
+125°C Units Conditions
VDD Note
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IPD and the additional current consumed when this peripheral is enabled.
The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should
be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS.
3: ADC clock source is FRC.
2015-2016 Microchip Technology Inc. DS40001819B-page 549
PIC16(L)F1777/8/9
TABLE 36-4: I/O PORTS
Standard Operating Conditions (unless otherwise stated)
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
VIL Input L ow Voltage
I/O PORT:
D034 with TTL buffer — — 0.8 V 4.5V VDD 5.5V
D034A — — 0.15 VDD V1.8V VDD 4.5V
D035 with Schmitt Trigger buffer — — 0.2 VDD V2.0V VDD 5.5V
with I2C levels — — 0.3 VDD V
with SMBus levels — — 0.8 V 2.7V VDD 5.5V
D036 MCLR, OSC1 (EXTRC mode) — — 0.2 VDD V(Note 1)
D036A OSC1 (HS mode) — — 0.3 VDD V
VIH Input Hi gh Voltage
I/O ports:
D040 with TTL buffer 2.0 — — V 4.5V VDD 5.5V
D040A 0.25 VDD +
0.8
——V1.8V VDD 4.5V
D041 with Schmitt Trigger buffer 0.8 VDD ——V2.0V VDD 5.5V
with I2C levels 0.7 VDD ——V
with SMBus levels 2.1 — — V 2.7V VDD 5.5V
D042 MCLR 0.8 VDD ——V
D043A OSC1 (HS mode) 0.7 VDD ——V
D043B OSC1 (EXTRC oscillator) 0.9 VDD ——VVDD 2.0V (Note 1)
IIL Input Leakage Current(2)
D060 I/O Ports — ± 5 ± 125 nA VSS VPIN VDD,
Pin at high-impedance, 85°C
— ± 5 ± 1000 nA VSS VPIN VDD,
Pin at high-impedance, 125°C
D061 MCLR(3) —± 5± 200nAVSS VPIN VDD,
Pin at high-impedance, 85°C
IPUR Weak Pu l l-up Current
D070* 25 100 200 AVDD = 3.3V, VPIN = VSS
VOL Output Low Voltage(4)
D080 Standard I/O ports
——0.6V
IOL = 8mA, VDD = 5V
IOL = 6mA, VDD = 3.3V
IOL = 1.8mA, VDD = 1.8V
D080A High Drive I/O ports —
—
—
—
0.6
0.6
0.6
—
—
V
V
V
IOH = 10mA, VDD = 2.3V, HIDCX = 1
IOH = 32mA, VDD = 3.0V, HIDCX = 1
IOH = 51mA, VDD = 5.0V, HIDCX = 1
VOH Output H igh Voltage(4)
D090 Standard I/O ports
VDD - 0.7 — — V
IOH = 3.5mA, VDD = 5V
IOH = 3mA, VDD = 3.3V
IOH = 1mA, VDD = 1.8V
D090A High Drive I/O ports VDD - 0.7
—
—
—
VDD - 0.7
VDD - 0.7
—
—
—
V
V
V
IOH = 10mA, VDD = 2.3V, HIDCX = 1
IOH = 37mA, VDD = 3.0V, HIDCX = 1
IOH = 54mA, VDD = 5.0V, HIDCX = 1
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an
external clock in EXTRC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: Including OSC2 in CLKOUT mode.
PIC16(L)F1777/8/9
DS40001819B-page 550 2015-2016 Microchip Technology Inc.
Capacitive Loading Specs on Output Pins
D101* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when
external clock is used to drive
OSC1
D101A* CIO All I/O pins — — 50 pF
TABLE 36-4: I/O PORTS (CONTINUED) (CONTINUED)
Standard Operating Conditions (unless otherwise stated)
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an
external clock in EXTRC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: Including OSC2 in CLKOUT mode.
2015-2016 Microchip Technology Inc. DS40001819B-page 551
PIC16(L)F1777/8/9
TABLE 36-5: MEMORY PROGRAMMING SPECIFICATIONS
Standard Operating Conditions (unle ss othe rwis e stated)
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
Program Memory
Programming S pe cific ation s
D110 VIHH Voltage on MCLR/VPP pin 8.0 — 9.0 V (Note 2, Note 3)
D111 IDDP Supply Current during
Programming
——10mA
D112 VBE VDD for Bulk Erase 2.7 — VDDMAX V
D113 VPEW VDD for Write or Row Erase VDDMIN —VDDMAX V
D114 IPPPGM Current on MCLR/VPP during
Erase/Write
—1.0—mA
D115 IDDPGM Current on VDD during
Erase/Write
—5.0 —mA
Program Flash Memo ry
D121 EPCell Endurance 10K — — E/W -40C TA +85C
(Note 1)
D122 VPRW VDD for Read/Write VDDMIN —VDDMAX V
D123 TIW Self-timed Write Cycle Time — 2 2.5 ms
D124 TRETD Characteristic Retention — 40 — Year Provided no other
specifications are violated
D125 EHEFC High-Endurance Flash Cell 100K — — E/W -0C TA +60°C, Lower
byte last 128 addresses
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Self-write and Block Erase.
2: Required only if single-supply programming is disabled.
3: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the ICD 2 VPP voltage must be
placed between the ICD 2 and target system when programming or debugging with the ICD 2.
PIC16(L)F1777/8/9
DS40001819B-page 552 2015-2016 Microchip Technology Inc.
TABLE 36-6: THERMAL CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Param
No. Sym. Characteristic Typ. Units Conditions
TH01 JA Thermal Resistance Junction to Ambient 60.0 C/W 28-pin SPDIP package
80.0 C/W 28-pin SOIC package
90.0 C/W 28-pin SSOP package
48 C/W 28-pin UQFN 4x4mm package
47.2 C/W 40-pin PDIP package
46.0 C/W 44-pin TQFP package
41.0 C/W 40-pin UQFN 5x5mm package
TH02 JC Thermal Resistance Junction to Case 31.4 C/W 28-pin SPDIP package
24 C/W 28-pin SOIC package
24 C/W 28-pin SSOP package
12 C/W 28-pin UQFN 4x4mm package
24.70 C/W 40-pin PDIP package
14.5 C/W 44-pin TQFP package
5.5 C/W 40-pin UQFN 5x5mm package
TH03 TJMAX Maximum Junction Temperature 150 C
TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1)
TH06 PI/OI/O Power Dissipation — W PI/O = (IOL * VOL) + (IOH * (VDD - VOH))
TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2)
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature, TJ = Junction Temperature
2015-2016 Microchip Technology Inc. DS40001819B-page 553
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36.4 AC Characteristics
Timing Parameter Symbology has been created with one of the following formats:
FIGURE 36-4: LOAD CONDITIONS
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O PORT t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
FFall PPeriod
HHigh RRise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
Load Condition
Legend: CL=50 pF for all pins
Pin
CL
VSS
Rev. 10-000133A
8/1/2013
PIC16(L)F1777/8/9
DS40001819B-page 554 2015-2016 Microchip Technology Inc.
FIGURE 36-5: CLOCK TIMING
TABLE 36-7: CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
OS01 FOSC External CLKIN Frequency(1) DC — 0.5 MHz External Clock (ECL)
DC — 4 MHz External Clock (ECM)
DC — 32 MHz External Clock (ECH)
Oscillator Frequency(1) — 32.768 — kHz LP Oscillator
0.1 — 4 MHz XT Oscillator
1 — 4 MHz HS Oscillator
1 — 20 MHz HS Oscillator, VDD > 2.7V
DC — 4 MHz EXTRC, VDD > 2.0V
OS02 TOSC External CLKIN Period(1) 27 — s LP Oscillator
250 — ns XT Oscillator
50 — ns HS Oscillator
50 — ns External Clock (EC)
Oscillator Period(1) —30.5— s LP Oscillator
250 — 10,000 ns XT Oscillator
50 — 1,000 ns HS Oscillator
31.25 — — ns EXTRC
OS03 T
CY Instruction Cycle Time(1) 125 TCY DC ns TCY = 4/FOSC
OS04* TosH,
TosL
External CLKIN High,
External CLKIN Low
2——s LP Oscillator
100 — — ns XT Oscillator
20 — — ns HS Oscillator
OS05* TosR,
TosF
External CLKIN Rise,
External CLKIN Fall
0—ns LP Oscillator
0—ns XT Oscillator
0—ns HS Oscillator
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min” values with an external
clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock)
for all devices.
CLKIN
CLKOUT
Q4 Q1 Q2 Q3 Q4 Q1
OS02
OS03
(CLKOUT Mode)
Note 1: See Table 36-10.
OS11
OS12
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TABLE 36-8: OSCILLATOR PARAMETERS
FIGURE 36-6: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
Standard Operating Conditions (unless otherwise stated)
Param
No. Sym. Characteristic Freq.
Tolerance Min. Typ† Max. Units Conditions
OS08 HFOSC Internal Calibrated HFINTOSC
Frequency(1) ±2% — 16.0 — MHz VDD = 3.0V, TA = 25°C,
(Note 2)
OS08A MFOSC Internal Calibrated MFINTOSC
Frequency(1) ±2% — 500 — kHz VDD = 3.0V, TA = 25°C,
(Note 2)
OS09 LFOSC Internal LFINTOSC Frequency — — 31 — kHz -40°C TA +125°C
OS10* TWARM HFINTOSC
Wake-up from Sleep Start-up Time
MFINTOSC
Wake-up from Sleep Start-up Time
——3.28s
— — 24 35 s
TLFOSC ST LFINTOSC
Wake-up from Sleep Start-up Time
——0.5—ms
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the
device as possible. 0.1 F and 0.01 F values in parallel are recommended.
2: See Figure 36-6: HFINTOSC Frequency Accuracy Over Device VDD and Temperature,
Figure 37-75: Wake From Sleep, VREGPM = 0., and
Figure 36-6: HFINTOSC Frequency Accuracy Over Device VDD and Temperature.
3: See Figure 37-58: LFINTOSC Frequency, PIC16LF1777/8/9 Only., and
Figure 37-59: LFINTOSC Frequency, PIC16F1777/8/9 Only..
125
25
2.0
0
60
85
VDD (V)
4.0 5.04.5
Temperature (°C)
2.5 3.0 3.5 5.5
1.8
-40
-20
± 5%
± 2%
± 5%
± 3%
PIC16(L)F1777/8/9
DS40001819B-page 556 2015-2016 Microchip Technology Inc.
TABLE 36-9: PLL CLOCK TIMING SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
F10 FOSC Oscillator Frequency Range 4 — 8 MHz
F11 FSYS On-Chip VCO System Frequency 16 — 32 MHz
F12 TRC PLL Start-up Time (Lock Time) — — 2 ms
F13* CLK CLKOUT Stability (Jitter) -0.25% — +0.25% %
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
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FIGURE 36-7: CLKOUT AND I/O TIMING
TABLE 36-10: CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
OS11 TosH2ckL FOSC to CLKOUT (1) — — 70 ns 3.3V VDD 5.0V
OS12 TosH2ckH FOSC to CLKOUT (1) — — 72 ns 3.3V VDD 5.0V
OS13 TckL2ioV CLKOUT to Port out valid(1) — — 20 ns
OS14 TioV2ckH Port input valid before CLKOUT(1) TOSC + 200 ns — — ns
OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid — 50 70* ns 3.3V VDD 5.0V
OS16 TosH2ioI Fosc (Q2 cycle) to Port input invalid
(I/O in hold time)
50 — — ns 3.3V VDD 5.0V
OS17 TioV2osH Port input valid to Fosc(Q2 cycle)
(I/O in setup time)
20 — — ns
OS18* TioR Port output rise time(2) —
—
40
15
72
32
ns VDD = 1.8V
3.3V VDD 5.0V
OS19* TioF Port output fall time(2) —
—
28
15
55
30
ns VDD = 1.8V
3.3V VDD 5.0V
OS20* Tinp INT pin input high or low time 25 — — ns
OS21* Tioc Interrupt-on-change new input level time 25 — — ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in EXTRC mode where CLKOUT output is 4 x TOSC.
2: Slew rate limited.
FOSC
CLKOUT
I/O pin
(Input)
I/O pin
(Output)
Q4 Q1 Q2 Q3
OS11
OS19
OS13
OS15
OS18, OS19
OS20
OS21
OS17
OS16
OS14
OS12
OS18
Old Value New Value
Write Fetch Read ExecuteCycle
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DS40001819B-page 558 2015-2016 Microchip Technology Inc.
FIGURE 36-8: RESE T, WATC HDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMI NG
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Start-up Time
Internal Reset(1)
Watchdog Timer
33
32
30
31
34
I/O pins
34
Note 1: Asserted low.
Reset(1)
2015-2016 Microchip Technology Inc. DS40001819B-page 559
PIC16(L)F1777/8/9
TABLE 36-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
30 TMCLMCLR Pulse Width (low) 2 — — s
31 TWDTLP Low-Power Watchdog Timer
Time-out Period
10 16 27 ms VDD = 3.3V-5V
1:512 Prescaler used
32 TOST Oscillator Start-up Timer Period(1) — 1024 — Tosc
33* TPWRT Power-up Timer Period, PWRTE =040 65 140 ms
34* TIOZ I/O high-impedance from MCLR Low
or Watchdog Timer Reset
——2.0s
35 VBOR Brown-out Reset Voltage(2) 2.55
2.30
1.80
2.70
2.45
1.90
2.85
2.60
2.10
V
V
V
BORV = 0
BORV = 1 (PIC16F1777/8/9)
BORV = 1 (PIC16LF1777/8/9)
35A VLPBOR Low-Power Brown-out 1.8 2.1 2.5 V LPBOR = 1
36* VHYST Brown-out Reset Hysteresis 0 25 75 mV -40°C TA +85°C
37* TBORDC Brown-out Reset DC Response
Time
1335sVDD VBOR
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency.
2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
PIC16(L)F1777/8/9
DS40001819B-page 560 2015-2016 Microchip Technology Inc.
FIGURE 36-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
FIGURE 36-10: BROW N-OUT RESET TIMING AND CHARACTERISTICS
T0CKI
T1CKI
40 41
42
45 46
47 49
TMR0 or
TMR1
VBOR
VDD
(Device in Brown-out Reset) (Device not in Brown-out Reset)
33(1)
Reset
(due to BOR)
VBOR and VHYST
37
Note 1: The delay, (TPWRT) releasing Reset, only occurs when the Power-up Timer is enabled, (PWRTE =0).
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TABLE 36-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
42* TT0P T0CKI Period Greater of:
20 or TCY + 40
N
— — ns N = prescale value
45* TT1H T1CKI High
Time
Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Synchronous, with Prescaler 15 — — ns
Asynchronous 30 — — ns
46* TT1L T1CKI Low
Time
Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Synchronous, with Prescaler 15 — — ns
Asynchronous 30 — — ns
47* TT1P T1CKI Input
Period
Synchronous Greater of:
30 or
(TCY + 40)*N
— — ns N = prescale value
Asynchronous 60 — — ns
48 FT1 Secondary Oscillator Input Frequency Range
(oscillator enabled by setting bit T1OSCEN)
32.4 32.768 33.1 kHz
49* TCKEZTMR1 Delay from External Clock Edge to Timer
Increment
2 TOSC —7 TOSC — Timers in Sync
mode
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
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FIGURE 36-11: CAPTURE/ COMPARE/PWM TIMINGS (CCP)
TABLE 36-13: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)
Standard Operating Conditions (unless otherwise stated)
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
CC01* TccL CCPx Input Low Time No Prescaler 0.5TCY + 20 — — ns
With Prescaler 20 — — ns
CC02* TccH CCPx Input High Time No Prescaler 0.5TCY + 20 — — ns
With Prescaler 20 — — ns
CC03* TccP CCPx Input Period (3TCY + 40)*N — — ns N = prescale value
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 36-4 for load conditions.
(Capture mode)
CC01 CC02
CC03
CCPx
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FIGURE 36-12 : CLC PROPAGATION TIMING
TABLE 36-14: CONFIGURATION LOGIC CELL (CLC) CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Param.
No. Sym. Characteristic Min. Typ† Max. Units Conditions
CLC01* TCLCIN CLC input time — 7 OS17 ns (No te 1)
CLC02* TCLC CLC module input to output progagation time —
—
24
12
—
—
ns
ns
VDD = 1.8V
VDD > 3.6V
CLC03* T
CLCOUT CLC output time Rise Time — OS18 — ns (Note 1)
Fall Time — OS19 — ns (Note 1)
CLC04* FCLCMAX CLC maximum switching frequency — 45 — MHz
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: See Table 36-10 for OS17, OS18 and OS19 rise and fall times.
LCx_in[n](1)
CLC
Output time
CLC
Input time LCx_out(1) CLCx
CLCxINn CLC
Module
CLC01 CLC02 CLC03
LCx_in[n](1) CLC
Output time
CLC
Input time LCx_out(1) CLCx
CLCxINn CLC
Module
Note 1: See Figure 28-1 to identify specific CLC signals.
PIC16(L)F1777/8/9
DS40001819B-page 564 2015-2016 Microchip Technology Inc.
TABLE 36-1 5: ANALOG-TO -D IGITAL CONVER TER ( ADC) CHAR ACTE RIST ICS(1,2,3,4):
TABLE 36-16: ADC CONVERSION REQUIREMENTS
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C, Single-ended, 2 s TAD, VREF+ = 3V, VREF- = VSS
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
AD01 NRResolution — — 10 bit
AD02 EIL Integral Error — — ±1.7 LSb VREF = 3.0V
AD03 EDL Differential Error — — ±1 LSb No missing codes, VREF = 3.0V
AD04 EOFF Offset Error — — ±2.5 LSb VREF = 3.0V
AD05 EGN Gain Error — — ±2.0 LSb VREF = 3.0V
AD06 VREF Reference Voltage 1.8 — VDD VVREF = (VREF+ minus VREF-)
AD07 VAIN Full-Scale Range VSS —VREF V
AD08 ZAIN Recommended Impedance of
Analog Voltage Source
—— 10kCan go higher if external 0.01F capacitor is
present on input pin.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The ADC conversion result never decreases with an increase in the input voltage and has no missing codes.
3: ADC VREF is from external VREF+ pin, VDD pin or FVR, whichever is selected as reference input.
4: See Section 31.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.
Standard Operating Conditions (unless otherwise stated)
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
AD130* TAD ADC Clock Period (TADC) 1.0 — 9.0 sFOSC-based
ADC Internal FRC Oscillator Period
(TFRC)
1.0 2.5 6.0 s ADCS<1:0> = 11 (ADC FRC mode)
AD131 TCNV Conversion Time (not including
Acquisition Time)(1) —13—TAD Set GO/DONE bit to conversion
complete
AD132* TACQ Acquisition Time — 5.0 — s
AD133* THCD Holding Capacitor Disconnect Time — 1/2 TAD — ADCS<2:0> x11 (FOSC-based)
—1/2 T
AD + 1TCY — ADCS<2:0> = x11 (FRC-based)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The ADRES register may be read on the following TCY cycle.
2015-2016 Microchip Technology Inc. DS40001819B-page 565
PIC16(L)F1777/8/9
FIGURE 36-13: ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED)
FIGURE 36-14: ADC CONVERSION TIMING (ADC CLOCK FROM FRC)
AD131
AD130
BSF ADCON0, GO
Q4
ADC_clk
ADC Data
ADRES
ADIF
GO
Sample
OLD_DATA
Sampling Stopped
DONE
NEW_DATA
987 3210
1 TCY
6
AD133
1 TCY
AD132
AD132
AD131
AD130
BSF ADCON0, GO
Q4
ADC_clk
ADC Data
ADRES
ADIF
GO
Sample
OLD_DATA
Sampling Stopped
DONE
NEW_DATA
9 7 3210
Note 1: If the ADC clock source is selected as FRC, a time of TCY is added before the ADC clock starts. This allows the
SLEEP instruction to be executed.
AD133(1)
6
8
1 TCY
1 TCY
PIC16(L)F1777/8/9
DS40001819B-page 566 2015-2016 Microchip Technology Inc.
TABLE 36-17: OPERATIONAL AMPLIFIER (OPA)
TABLE 36-18: PROGRAMMABLE RAMP GENERATOR (PRG) SPECIFICATIONS
TABLE 36-19: COMPARATOR SPECIFICATIONS
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C, OPAxSP = 1 (High GBWP mode)
Param
No. Symbol Parameters Min. Typ. Max. Units Conditions
OPA01* GBWP Gain Bandwidth Product — 3.5 — MHz
OPA02* TON Turn-on Time — 10 — s
OPA03* PMPhase Margin — 40 — degrees
OPA04* SRSlew Rate — 3 — V/s
OPA05 OFF Offset — ±3 ±9 mV
OPA06 CMRR Common-Mode Rejection Ratio 52 70 — dB
OPA07* AOL Open Loop Gain — 90 — dB
OPA08 VICM Input Common-Mode Voltage 0 — VDD VVDD > 2.5V
OPA09* PSRR Power Supply Rejection Ratio — 80 — dB
OPA10* HZ High-Impedance On/Off Time — 50 — ns
* These parameters are characterized but not tested.
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C (unless otherwise stated)
Param
No. Sym. Characteristics Min. Typ. Max. Units Comments
PRG01 RRR Rising Ramp Rate(1) —1—V/s PRGxCON2 = 10h
PRG02 FRR Falling Ramp Rate(1) —1—V/s PRGxCON2 = 10h
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to
VDD.
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C
See Section 31.0 “DC an d AC Chara cteristics Graphs and Charts” for operating characterization.
Param
No. Sym. Characteristics Min. Typ. Max. Units Comments
CM01 VIOFF Input Offset Voltage — ±2.5 ±5 mV VICM = VDD/2
CM02 VICM Input Common-Mode Voltage 0 — VDD V
CM03 CMRR Common-Mode Rejection Ratio 40 50 — dB
CM04A
Tresp(1)
Response Time Rising Edge — 60 125 ns CxSP = 1
CM04B Response Time Falling Edge — 60 110 ns CxSP = 1
CM04C Response Time Rising Edge — 85 — ns CxSP = 0
CM04D Response Time Falling Edge — 85 — ns CxSP = 0
CM05 TMC2OV Comparator Mode Change to
Output Valid*
——10s
CM06 CHYSTER Comparator Hysteresis 20 45 75 mV CxHYS = 1
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to
VDD.
2015-2016 Microchip Technology Inc. DS40001819B-page 567
PIC16(L)F1777/8/9
TABLE 36-20: 10-BIT DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS
TABLE 36-21: 5-BIT DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS
TABLE 36-22: ZERO CROSS PIN SPECIFICATIONS
Operating Conditions (unless otherwise st ate d)
VDD = 3.0V, TA = 25°C
See Section 31.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.
Param
No. Sym. Characteristics Min. Typ. Max. Units Comments
DAC01* CLSB Step Size — VDD/1024 — V
DAC02 CINL Integral Error(2) —— 2.0 LSb For codes 0x004 to 0x3FB
DAC03 CDNL Differential Error(2) —— 1LSb
DAC04 COFF Offset Error(2) —— 3LSb
DAC05 CGN Gain Error(2) —— 3LSb
DAC06* CRUnit Resistor Value (R) — 300 —
DAC07* CST Settling Time(1) ——10s
* These parameters are characterized but not tested.
Note 1: Settling time measured while DACR<9:0> transitions from ‘0x000’ to ‘0x3FF’.
2: Buffered by op amp in unity gain.
Operating Conditions (unless otherwise st ate d)
VDD = 3.0V, TA = 25°C
See Section 31.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.
Param
No. Sym. Characteristics Min. Typ. Max. Units Comments
DAC10* CLSB Step Size — VDD/32 — V
DAC11 CACC Absolute Accuracy(2) —— 0.5 LSb
DAC12* CRUnit Resistor Value (R) — 6000 —
DAC13* CST Settling Time(1) ——10s
* These parameters are characterized but not tested.
Note 1: Settling time measured while DACR<4:0> transitions from ‘0x00’ to ‘0x1F’.
2: Buffered by op amp in unity gain.
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C
Param.
No. Sym. Characteristics Min. Typ. Max. Units Comments
ZC01 ZCPINV Voltage on Zero Cross Pin — 0.75 — V
ZC02 ZCDRV Maximum source or sink current — — 600 A
ZC04 ZCISW Response Time Rising Edge — 1 — s
Response Time Falling Edge — 1 — s
ZC05 ZCOUT Response Time Rising Edge — 1 — s
Response Time Falling Edge — 1 — s
* These parameters are characterized but not tested.
PIC16(L)F1777/8/9
DS40001819B-page 568 2015-2016 Microchip Technology Inc.
FIGURE 36-15: E US ART SYNCHRONO US TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 36-23: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 36-16: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 36-24: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No. Symbol Characteristic Min. Max. Units Conditions
US120 TCKH2DTV SYNC XMIT (Master and Slave)
Clock high to data-out valid
—80ns3.0V VDD 5.5V
— 100 ns 1.8V VDD 5.5V
US121 TCKRF Clock out rise time and fall time
(Master mode)
—45ns3.0V VDD 5.5V
—50ns1.8V VDD 5.5V
US122 TDTRF Data-out rise time and fall time — 45 ns 3.0V VDD 5.5V
—50ns1.8V VDD 5.5V
Standard Operating Conditions (unless otherwise stated)
Param.
No. Symbol Characteristic Min. Max. Units Conditions
US125 TDTV2CKL SYNC RCV (Master and Slave)
Data-setup before CK (DT hold time) 10 — ns
US126 T
CKL2DTL Data-hold after CK (DT hold time) 15 — ns
Note: Refer to Figure 36-4 for load conditions.
US121 US121
US120 US122
CK
DT
Note: Refer to Figure 36-4 for load conditions.
US125
US126
CK
DT
2015-2016 Microchip Technology Inc. DS40001819B-page 569
PIC16(L)F1777/8/9
FIGURE 36-17 : SP I MASTE R MODE TIMING (CKE = 0, SMP = 0)
FIGURE 36-18 : SPI MAST E R MODE TIMING (CKE = 1, SMP = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
SP81
SP71 SP72
SP73
SP74
SP75, SP76
SP78
SP79
SP80
SP79
SP78
MSb LSb
bit 6 - - - - - -1
MSb In LSb In
bit 6 - - - -1
Note: Refer to Figure 36-4 for load conditions.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
SP81
SP71 SP72
SP74
SP75, SP76
SP78
SP80
MSb
SP79
SP73
MSb In
bit 6 - - - - - -1
LSb In
bit 6 - - - -1
LSb
Note: Refer to Figure 36-4 for load conditions.
PIC16(L)F1777/8/9
DS40001819B-page 570 2015-2016 Microchip Technology Inc.
FIGURE 36-19 : SPI SLAVE MODE TIMING (CKE = 0)
FIGURE 36-20 : SPI SLAVE MODE TIMING (CKE = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
SP70
SP71 SP72
SP73
SP74
SP75, SP76 SP77
SP78
SP79
SP80
SP79
SP78
MSb LSb
bit 6 - - - - - -1
MSb In bit 6 - - - -1 LSb In
SP83
Note: Refer to Figure 36-4 for load conditions.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
SP70
SP71 SP72
SP82
SP74
SP75, SP76
MSb bit 6 - - - - - -1 LSb
SP77
MSb In bit 6 - - - -1 LSb In
SP80
SP83
Note: Refer to Figure 36-4 for load conditions.
2015-2016 Microchip Technology Inc. DS40001819B-page 571
PIC16(L)F1777/8/9
TABLE 36-25: SPI MODE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param
No. Symbol Characteristic Min. Typ† Max. Units Conditions
SP70* TSSL2SCH,
TSSL2SCL
SS to SCK or SCK input 2.25 TCY ——ns
SP71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns
SP72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns
SP73* TDIV2SCH,
TDIV2SCL
Setup time of SDI data input to SCK
edge
100 — — ns
SP74* TSCH2DIL,
TSCL2DIL
Hold time of SDI data input to SCK
edge
100 — — ns
SP75* TDOR SDO data output rise time — 10 25 ns 3.0V VDD 5.5V
—2550ns1.8V VDD 5.5V
SP76* TDOF SDO data output fall time — 10 25 ns
SP77* TSSH2DOZSS to SDO output high-impedance 10 — 50 ns
SP78* TSCR SCK output rise time
(Master mode)
—1025ns3.0V VDD 5.5V
—2550ns1.8V VDD 5.5V
SP79* TSCF SCK output fall time (Master mode) — 10 25 ns
SP80* TSCH2DOV,
TSCL2DOV
SDO data output valid after SCK
edge
— — 50 ns 3.0V VDD 5.5V
——145ns1.8V VDD 5.5V
SP81* TDOV2SCH,
TDOV2SCL
SDO data output setup to SCK edge 1 Tcy — — ns
SP82* TSSL2DOV SDO data output valid after SS
edge
——50ns
SP83* TSCH2SSH,
TSCL2SSH
SS after SCK edge 1.5 TCY + 40 — — ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
PIC16(L)F1777/8/9
DS40001819B-page 572 2015-2016 Microchip Technology Inc.
FIGURE 36-21 : I2C BUS START/STOP BITS TIMING
TABLE 36-26: I2C BUS START/STOP BITS REQUIREMENTS
FIGURE 36-22 : I2C BUS DATA TIMING
Standard Operating Conditions (unless otherwise stated)
Param
No. Symbol Characteristic Min. Typ. Max. Units Conditions
SP90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated
Start condition
Setup time 400 kHz mode 600 — —
SP91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first
clock pulse is generated
Hold time 400 kHz mode 600 — —
SP92* TSU:STO Stop condition 100 kHz mode 4700 — — ns
Setup time 400 kHz mode 600 — —
SP93 THD:STO Stop condition 100 kHz mode 4000 — — ns
Hold time 400 kHz mode 600 — —
* These parameters are characterized but not tested.
Note: Refer to Figure 36-4 for load conditions.
SP91
SP92
SP93
SCL
SDA
Start
Condition
Stop
Condition
SP90
Note: Refer to Figure 36-4 for load conditions.
SP90
SP91 SP92
SP100
SP101
SP103
SP106 SP107
SP109 SP109
SP110
SP102
SCL
SDA
In
SDA
Out
2015-2016 Microchip Technology Inc. DS40001819B-page 573
PIC16(L)F1777/8/9
TABLE 36-27: I2C BUS DAT A REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No. Symbol Characteristic Min. Max. Units Conditions
SP100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — s Device must operate at a
minimum of 10 MHz
SSP module 1.5TCY —
SP101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — s Device must operate at a
minimum of 10 MHz
SSP module 1.5TCY —
SP102* TRSDA and SCL rise
time
100 kHz mode — 1000 ns
400 kHz mode 20 + 0.1CB300 ns CB is specified to be from
10-400 pF
SP103* TFSDA and SCL fall
time
100 kHz mode — 250 ns
400 kHz mode 20 + 0.1CB250 ns CB is specified to be from
10-400 pF
SP106* THD:DAT Data input hold time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
SP107* TSU:DAT Data input setup
time
100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
SP109* TAA Output valid from
clock
100 kHz mode — 3500 ns (Note 1)
400 kHz mode — — ns
SP110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free
before a new transmission
can start
400 kHz mode 1.3 — s
SP111 CBBus capacitive loading — 400 pF
* These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the
requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not
stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it
must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the
Standard mode I2C bus specification), before the SCL line is released.
PIC16(L)F1777/8/9
DS40001819B-page 574 2015-2016 Microchip Technology Inc.
NOTES:
2015-2016 Microchip Technology Inc. DS40001819B-page 575
PIC16(L)F1777/8/9
37.0 DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Unless otherwise noted, all graphs apply to both the L and LF devices.
“Typical” represents the mean of the distribution at 25C. “Maximum”, “Max.”, “Minimum” or “Min.”
represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over each
temperature range.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC16(L)F1777/8/9
DS40001819B-page 576 2015-2016 Microchip Technology Inc.
Note: Unless otherwise noted, VIN =5V, FOSC = 300 kHz, CIN = 0.1 µF, TA=25°C.
FIGURE 37-1: IDD, LP Oscillator Mode,
Fosc = 32 kHz, PIC16LF1777/8/9 Only. FIGURE 37-2: IDD, LP Oscillat or Mode,
Fosc = 32 kHz, PIC16F1777/8/9 Only.
Typical
Max.
2
4
6
8
10
12
14
16
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
I
DD
(µA)
V
DD
(V)
Max: 85°C + 3ı
Typical: 25°C
Typical
Max.
10
15
20
25
30
35
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (µA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
FIGURE 37-3: IDD Typical, XT and EXTRC
Oscilla tor, PIC1 6LF 1 777/ 8/9 On ly. FIGURE 37-4: IDD Maximum, XT and
EXTRC Oscillator, PIC16LF1777/8/9 Only.
4 MHz XT
1 MHz XT
0
50
100
150
200
250
300
350
400
450
500
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (µA)
VDD (V)
Typical: 25°C
4 MHz XT
1 MHz XT
0
100
200
300
400
500
600
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (µA)
VDD (V)
Max: 85°C + 3ı
FIGURE 37-5: IDD Typical, XT and EXTRC
Oscillator, PIC16F1777/8 / 9 Only. FIGURE 37-6: IDD Maximum, XT and
EXTRC Oscillator, PIC16F1777/8/9 Only.
4 MHz XT
1 MHz XT
0
100
200
300
400
500
600
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (µA)
VDD (V)
Typical: 25°C
4 MHz XT
1 MHz XT
0
100
200
300
400
500
600
700
800
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (µA)
VDD (V)
Max: 85°C + 3ı
Microchip Technology Inc. DS40001819B-page 577
PIC16(L)F1777/8/9
Note: Unless otherwise noted, VIN =5V, FOSC = 300 kHz, CIN = 0.1 µF, TA=25°C.
FIGURE 37-7: IDD, EC Oscillator LP Mode,
Fosc = 32 kHz, PIC16LF1777/8/9 Only. FIGURE 37-8: IDD, EC Oscillator LP Mode,
Fosc = 32 kHz, PIC16F1777/8/9 Only.
Typical
Max.
0
2
4
6
8
10
12
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (µA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
Typical
Max.
10
12
14
16
18
20
22
24
26
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
I
DD
(µA)
V
DD
(V)
Max: 85°C + 3ı
Typical: 25°C
FIGURE 37-9: IDD, EC Oscillator LP Mode,
Fosc = 500 kHz, PIC16LF1777/8/9 Only. FIGURE 37-10: IDD, EC Oscillator LP Mode,
Fosc = 500 kHz, PIC16F1777/8/9 Only.
Max.
Typical
10
15
20
25
30
35
40
45
50
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (µA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
Typical
Max.
40
45
50
55
60
65
70
75
80
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
I
DD
(µA)
V
DD
(V)
Max: 85°C + 3ı
Typical: 25°C
FIGURE 37-11: IDD Typical, EC Oscillator
MP Mode, PIC16LF1777/8/9 Only. FIGURE 37-12: IDD Maximum, EC Oscillator
MP Mode, PIC16LF 1 777/ 8/9 On ly.
4 MHz
1 MHz
0
50
100
150
200
250
300
350
400
450
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (µA)
VDD (V)
Typical: 25°C
4 MHz
1 MHz
0
50
100
150
200
250
300
350
400
450
500
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (µA)
VDD (V)
Max: 85°C + 3ı
PIC16(L)F1777/8/9
DS40001819B-page 578 2015-2016 Microchip Technology Inc.
Note: Unless otherwise noted, VIN =5V, FOSC = 300 kHz, CIN = 0.1 µF, TA=25°C.
FIGURE 37-13 : IDD Typical, EC Oscillator
MP Mode, PIC16F1777/8/9 Only. FIGURE 37-14: IDD Maximum, EC Oscillator
MP Mode, PIC16F1777/8/9 Only.
4 MHz
1 MHz
0
100
200
300
400
500
600
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
I
DD
(µA)
V
DD
(V)
Typical: 25°C
4 MHz
1 MHz
0
100
200
300
400
500
600
700
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (µA)
VDD (V)
Max: 85°C + 3ı
FIGURE 37-15 : IDD Typical, EC Oscillator
HP Mode, PIC16LF1777/8/9 On ly. FIGURE 37-16: IDD Maximum, EC Oscillator
HP Mode, PIC16LF1777/8/9 Only.
32 MHz
16 MHz
8 MHz
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (mA)
VDD (V)
Typical: 25°C
32 MHz
16 MHz
8 MHz
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (mA)
VDD (V)
Max: 85°C + 3ı
FIGURE 37-17 : IDD Typical, EC Oscillator
HP Mode, PIC16F1777/8/9 Only. FIGURE 37-18: IDD Maximum, EC Oscillator
HP Mode, PIC16F1777/8/9 Only.
32 MHz
16 MHz
8 MHz
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
I
DD
(mA)
V
DD
(V)
Typical: 25°C
32 MHz
16 MHz
8 MHz
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
I
DD
(mA)
V
DD
(V)
Max: 85°C + 3ı
Microchip Technology Inc. DS40001819B-page 579
PIC16(L)F1777/8/9
Note: Unless otherwise noted, VIN =5V, FOSC = 300 kHz, CIN = 0.1 µF, TA=25°C.
FIGURE 37-19 : IDD, LFINTOSC Mode,
Fosc = 31 kHz, PIC16LF1777/8/9 Only. FIGURE 37-20: IDD, LFINTOSC Mode,
Fosc = 31 kHz, PIC16F1777/8/9 Only.
Typical
Max.
0
1
2
3
4
5
6
7
8
9
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (µA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
Typical
Max.
10
12
14
16
18
20
22
24
26
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
I
DD
(µA)
V
DD
(V)
Max: 85°C + 3ı
Typical: 25°C
FIGURE 37-21 : IDD, MFINTOSC Mode,
Fosc = 500 kHz, PIC16LF1777/8/9 Only. FIGURE 37-22: IDD, MFINTOSC Mode,
Fosc = 500 kHz, PIC16F1777/8/9 Only.
Typical
Max.
100
120
140
160
180
200
220
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (µA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
Typical
Max.
140
160
180
200
220
240
260
280
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
I
DD
(µA)
V
DD
(V)
Max: 85°C + 3ı
Typical: 25°C
FIGURE 37-23 : IDD Typical, HFINTOSC
Mode, PIC1 6LF 17 77/8 /9 Only. FIGURE 37-24: IDD Maximum , HFINTOSC
Mode, PIC1 6LF 17 77/ 8/9 Only.
32 MHz PLL
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
0.2
0.7
1.2
1.7
2.2
2.7
3.2
3.7
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
I
DD
(mA)
V
DD
(V)
Typical: 25°C
32 MHz PLL
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
0.2
0.7
1.2
1.7
2.2
2.7
3.2
3.7
4.2
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (mA)
VDD (V)
Max: 85°C + 3ı
PIC16(L)F1777/8/9
DS40001819B-page 580 2015-2016 Microchip Technology Inc.
Note: Unless otherwise noted, VIN =5V, FOSC = 300 kHz, CIN = 0.1 µF, TA=25°C.
FIGURE 37-25 : IDD Typical, HFINTOSC
Mode, PIC1 6F 177 7/8/ 9 Only. FIGURE 37-26: IDD Maximum, HFINTOSC
Mode, PIC1 6F 177 7/8 /9 Only.
32 MHz PLL
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
0.2
0.7
1.2
1.7
2.2
2.7
3.2
3.7
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (mA)
VDD (V)
Typical: 25°C
32 MHz PLL
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
0.2
0.7
1.2
1.7
2.2
2.7
3.2
3.7
4.2
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (mA)
VDD (V)
Max: 85°C + 3ı
FIGURE 37-27 : IDD Typical, HS Oscillator,
25°C, PIC16LF1777/8/9 Only. FIGURE 37-28: IDD Maximum, HS Oscillator,
PIC16LF1777/8/9 Only.
4 MHz
8 MHz
16 MHz
20 MHz
0.0
0.5
1.0
1.5
2.0
2.5
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (mA)
VDD (V)
Typical: 25°C
4 MHz
8 MHz
16 MHz
20 MHz
0.0
0.5
1.0
1.5
2.0
2.5
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (mA)
VDD (V)
Max: 85°C + 3ı
FIGURE 37-29 : IDD Typical, HS Oscillator,
25°C, PIC16F1777/8/9 Only. FIGURE 37-30: IDD, HS Oscillator (8 MHz +
4x PLL), PIC16LF1777/8/9 Only.
4 MHz
8 MHz
16 MHz
20 MHz
0.0
0.5
1.0
1.5
2.0
2.5
3.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (mA)
VDD (V)
Typical: 25°C
Typical
Max.
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (mA)
VDD (V)
Typical: 25°C
Max: 85°C + 3ı
Microchip Technology Inc. DS40001819B-page 581
PIC16(L)F1777/8/9
Note: Unless otherwise noted, VIN =5V, FOSC = 300 kHz, CIN = 0.1 µF, TA=25°C.
FIGURE 37-31 : IDD, HS Oscillator, 32 MHz
(8 MHz + 4x PLL), PIC16F1777/8/9 Only. FIGURE 37-32: IPD Base, LP Sleep Mode,
PIC16LF1777/8/9 Only.
Typical
Max.
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
I
DD
(mA)
V
DD
(V)
Typical: 25°C
Max: 85°C + 3ı
Max.
Typical
0
50
100
150
200
250
300
350
400
450
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (nA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
FIGURE 37-33 : IPD Base, LP Sleep Mode
(VREGPM = 1), PIC16F1777/8/9 Only. FIGURE 37-34: IPD, Watchdog Timer (WDT),
PIC16LF1777/8/9 Only.
Max.
Typical
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IPD (µA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
Max.
Typical
0.0
0.5
1.0
1.5
2.0
2.5
3.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IPD (µA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
FIGURE 37-35: IPD, Watchdog Timer (WDT),
PIC16F1777/8/9 Only. FIGURE 37-36: IPD, Fixed Voltage Reference
(FVR), ADC, PIC16LF1777/8/9 Only.
Max.
Typical
0.0
0.5
1.0
1.5
2.0
2.5
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IPD (µA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
Max.
Typical
5
10
15
20
25
30
35
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
IDD (nA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
PIC16(L)F1777/8/9
DS40001819B-page 582 2015-2016 Microchip Technology Inc.
Note: Unless otherwise noted, VIN =5V, FOSC = 300 kHz, CIN = 0.1 µF, TA=25°C.
FIGURE 37-3 7: IPD, Fixed Voltage Reference
(FVR), ADC, PIC16F1777/8/9 Only. FIGURE 37-38: IPD, Fixed Voltage Reference
(FVR), DAC/ Com p a rator, PIC16LF1777/8/9 Only.
Max.
Typical
10
15
20
25
30
35
40
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (nA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
Max.
Typical
5
10
15
20
25
30
35
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
IDD (nA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
FIGURE 37-39 : IPD, Fixed Voltage Reference
(FVR), DAC/Comparator, PIC16F1777/8/9 Only. FIGURE 37-40: IPD, Brown-Out Reset
(BOR), BORV = 1, PIC16LF1777/8/9 Only.
Max.
Typical
10
15
20
25
30
35
40
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (nA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
Max.
Typical
4
5
6
7
8
9
10
11
2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
IDD (nA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
FIGURE 37-41 : IPD, Brown-Out Reset
(BOR), BORV = 1, PIC16F1777/8/9 Only. FIGURE 37-42: IPD, LP Brown-Out Reset
(LPBOR = 0), PIC16LF1777/8/9 Only.
Max.
Typical
4
5
6
7
8
9
10
11
12
13
2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
IDD (nA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
Max.
Typical
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
IDD (nA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
Microchip Technology Inc. DS40001819B-page 583
PIC16(L)F1777/8/9
Note: Unless otherwise noted, VIN =5V, FOSC = 300 kHz, CIN = 0.1 µF, TA=25°C.
FIGURE 37-43 : IPD, LP Brown-Out Reset
(LPBOR = 0), PIC16F1777/8/9 Only. FIGURE 37-44: IPD, Timer1 Oscillator,
FOSC = 32 kHz, PIC1 6LF1 777 /8/9 Only.
Max.
Typical
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
IDD (µA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
Max.
Typical
0
1
2
3
4
5
6
7
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
I
DD
(µA)
V
DD
(V)
Max: 85°C + 3ı
Typical: 25°C
FIGURE 37-45 : IPD, Timer1 Oscillator,
FOSC = 32 kHz, PIC16F1777/8/9 Only. FIGURE 37-46: IPD, Op Amp, NP Mode
(VREFPM = 0), PIC16LF1777 /8/9 On ly.
Max.
Typical
0
2
4
6
8
10
12
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (µA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
Max.
Typical
0
100
200
300
400
500
600
700
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (µA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
FIGURE 37-47 : IPD, Op Amp, NP Mode
(VREFPM = 0), PIC16F1777/8 /9 Only. FIGURE 37-48: IPD, ADC Non-Converting,
PIC16LF1777/8/9 Only.
Typical
Max.
0
100
200
300
400
500
600
700
800
900
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (µA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
Max.
Typical
0
50
100
150
200
250
300
350
400
450
500
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
I
DD
(nA)
V
DD
(V)
Max: 85°C + 3ı
Typical: 25°C
PIC16(L)F1777/8/9
DS40001819B-page 584 2015-2016 Microchip Technology Inc.
Note: Unless otherwise noted, VIN =5V, FOSC = 300 kHz, CIN = 0.1 µF, TA=25°C.
FIGURE 37-49 : IPD, ADC Non-Conver tin g,
PIC16F1777/8/9 Only. FIGURE 37-50: IPD, Comparator, NP Mode
(VREGPM = 0), PIC16LF1777/ 8/9 On ly.
Max.
Typical
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (µA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
Max.
Typical
200
220
240
260
280
300
320
340
360
380
400
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (µA)
VDD (V)
Max: -40°C + 3ı
Typical: 25°C
FIGURE 37-51 : IPD, Comparator, NP Mode
(VREGPM = 0), PIC16F1777/8/9 Only. FIGURE 37-52: VOL vs. IOL Over
Temperature, VDD = 5.0V, PIC16F1777/8/9 Only.
Max.
Typical
200
250
300
350
400
450
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (µA)
VDD (V)
Max: -40°C + 3ı
Typical: 25°C
-40°C
Typical
125°C
0
1
2
3
4
5
6
-30 -25 -20 -15 -10 -5 0
VOH (V)
IOH (mA)
Graph represents 3ıLimits
FIGURE 37-53 : VOH vs. IOH Over
Temperature, VDD = 5.0V, PIC16F1777/8/9 Only. FIGURE 37-54: VOL vs. IOL Over
Temperature, VDD = 3.0V.
-40°C
Typical
125°C
0
1
2
3
4
5
0 1020304050607080
VOL (V)
IOL (mA)
Graph represents 3ıLimits
-40°C
Typical
125°C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-14-12-10-8-6-4-2 0
VOH (V)
IOH (mA)
Graph represents 3ıLimits
Microchip Technology Inc. DS40001819B-page 585
PIC16(L)F1777/8/9
Note: Unless otherwise noted, VIN =5V, FOSC = 300 kHz, CIN = 0.1 µF, TA=25°C.
FIGURE 37-55 : VOH vs. IOH Over
Temperature, VDD = 3.0V. FIGURE 37-56: VOL vs. IOL Over
Temperature, VDD = 1.8V, PIC16LF1777/8/9
Only.
-40°C
125°C
Typical
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0 5 10 15 20 25 30
VOL (V)
IOL (mA)
Graph represents 3ıLimits
-40°C
Typical
125°C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
VOH (V)
IOH (mA)
Graph represents 3ıLimits
FIGURE 37-57 : VOL vs. IOL Over
Temperature, VDD = 1.8V, PIC16LF1777/8/9
Only.
FIGURE 37-58: LFINTOSC Frequency,
PIC16LF1777/8/9 Only.
-40°C
Typical
125°C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
012345678910
VOL (V)
IOL (mA)
Graph represents 3ıLimits
Typical
Max.
Min.
20,000
22,000
24,000
26,000
28,000
30,000
32,000
34,000
36,000
38,000
40,000
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Frequency (Hz)
VDD (V)
Max: Typical + 3ı(-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3ı(-40°C to +125°C)
FIGURE 37-59 : LFINTOSC Frequency,
PIC16F1777/8/9 Only. FIGURE 37-60: WDT Time-Out Period,
PIC16F1 777/8/9 On ly.
q
y
Typical
Max.
Min.
20,000
22,000
24,000
26,000
28,000
30,000
32,000
34,000
36,000
38,000
40,000
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Frequency (Hz)
VDD (V)
Max: Typical + 3ı(-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3ı(-40°C to +125°C)
Typical
Max.
Min.
10
12
14
16
18
20
22
24
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Time (ms)
VDD (V)
Max: Typical + 3ı(-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3ı(-40°C to +125°C)
PIC16(L)F1777/8/9
DS40001819B-page 586 2015-2016 Microchip Technology Inc.
Note: Unless otherwise noted, VIN =5V, FOSC = 300 kHz, CIN = 0.1 µF, TA=25°C.
FIGURE 37-61: WDT Time - Ou t Per io d ,
PIC16LF1777/8/9 On ly. FIGURE 37-62: Brown-Out Reset Voltage,
Low Trip Point (BORV = 1), PIC16LF1777/8/9
Only.
Typical
Max.
Min.
10
12
14
16
18
20
22
24
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Time (ms)
VDD (V)
Max: Typical + 3ı(-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3ı(-40°C to +125°C)
Max.
Min.
Typical
1.80
1.85
1.90
1.95
2.00
-60 -40 -20 0 20 40 60 80 100 120 140
Voltage (V)
Temperature (°C)
Max: Typical + 3ı
Typical: statistical mean
Min: Typical - 3ı
FIGURE 37-63: Brown-Out Reset Hysteresis,
Low Trip Point (BORV = 1), PIC16LF1777/8/9
Only.
FIGURE 37-64: Brown-Out Reset Voltage,
Low Trip Point (BORV = 1), PIC16F 1773 / 6 Only.
Typical
Max.
Min.
0
10
20
30
40
50
60
70
-60 -40 -20 0 20 40 60 80 100 120 140
Voltage (mV)
Temperature (°C)
Max: Typical + 3ı
Typical: statistical mean
Min: Typical - 3ı
Max.
Min.
Typical
2.30
2.35
2.40
2.45
2.50
2.55
2.60
-60 -40 -20 0 20 40 60 80 100 120 140
Voltage (V)
Temperature (°C)
Max: Typical + 3ı
Typical: statistical mean
Min: Typical - 3ı
FIGURE 37-65 : Brown-Out Reset Hysteresis,
Low Trip Point (BORV = 1), PIC16F1773/6 Only. FIGURE 37-66: Brown-Out Reset Voltage,
High Trip Point (BORV = 0).
Typical
Max.
Min.
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
-60 -40 -20 0 20 40 60 80 100 120 140
Voltage (mV)
Temperature (°C)
Max: Typical + 3ı
Typical: statistical mean
Min: Typical - 3ı
Max.
Min.
Typical
2.60
2.65
2.70
2.75
2.80
2.85
-60 -40 -20 0 20 40 60 80 100 120 140
Voltage (V)
Temperature (°C)
Max: Typical + 3ı
Typical: statistical mean
Min: Typical - 3ı
Microchip Technology Inc. DS40001819B-page 587
PIC16(L)F1777/8/9
Note: Unless otherwise noted, VIN =5V, FOSC = 300 kHz, CIN = 0.1 µF, TA=25°C.
FIGURE 37-67 : Brown-Out Reset Hysteresis,
High Trip Point (BORV = 0). FIGURE 37-68: LPBOR Reset Voltage.
Typical
Max.
Min.
0
10
20
30
40
50
60
70
80
-60 -40 -20 0 20 40 60 80 100 120 140
Voltage (mV)
Temperature (°C)
Max: Typical + 3ı
Typical: statistical mean
Min: Typical - 3ı
Max.
Min.
Typical
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
-60 -40 -20 0 20 40 60 80 100 120 140
Voltage (V)
Temperature (°C)
Max: Typical + 3ı
Typical: statistical mean
Min: Typical - 3ı
FIGURE 37-69 : LPBOR Reset Hysteresis. FIGURE 37-70: PWRT Period,
PIC16F1 777/8/9 On ly.
Typical
Max.
0
5
10
15
20
25
30
35
40
45
50
-60 -40 -20 0 20 40 60 80 100 120 140
Voltage (mV)
Temperature (°C)
Max: Typical + 3ı
Typical: statistical mean
Typical
Max.
Min.
40
50
60
70
80
90
100
22.533.544.555.56
Time (ms)
VDD (V)
Max: Typical + 3ı(-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3ı(-40°C to +125°C)
FIGURE 37-71 : PWRT Period,
PIC16LF1773/6 Only. FIGURE 37-72: POR Rele as e Voltage.
Typical
Max.
Min.
40
50
60
70
80
90
100
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8
Time (ms)
VDD (V)
Max: Typical + 3ı(-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3ı(-40°C to +125°C)
Typical
Max.
Min.
1.50
1.52
1.54
1.56
1.58
1.60
1.62
1.64
1.66
1.68
1.70
-50-250 255075100125150
Voltage (V)
Temperature (°C)
Max: Typical + 3ı
Typical: statistical mean
Min: Typical - 3ı
PIC16(L)F1777/8/9
DS40001819B-page 588 2015-2016 Microchip Technology Inc.
Note: Unless otherwise noted, VIN =5V, FOSC = 300 kHz, CIN = 0.1 µF, TA=25°C.
FIGURE 37-73 : POR Rearm Voltage,
NP Mode (VREGPM1 = 0), PIC16F1773/6 Only. FIGURE 37-74: PO R Rearm Voltage,
NP Mode, PIC16LF1777/8/9 Only.
1.46
1.48
1.5
1.52
1.54
1.56
1.58
-40-200 20406080100120
Voltage (V)
Temperature (°C)
Max: Typical + 3ı
Typical: 25°C
Min: Typical - 3ı
Typical
Max.
Min.
1.44
1.46
1.48
1.50
1.52
1.54
1.56
1.58
-50-250 255075100125150
Voltage (V)
Temperature (°C)
Max: Typical + 3ı
Typical: statistical mean
Min: Typical - 3ı
Typical
Max.
Min.
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
-50-250 255075100125150
Voltage (V)
Temperature (°C)
Max: Typical + 3ı
Typical: statistical mean
Min: Typical - 3ı
FIGURE 37-75 : Wake From Sleep,
VREGPM = 0.FIGURE 37-76: Wake From Sleep,
VREGPM = 1.
Typical
Max.
0
2
4
6
8
10
12
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Time (µs)
VDD (V)
Max: Typical + 3ı(-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3ı(-40°C to +125°C)
Typical
Max.
0
5
10
15
20
25
30
35
40
45
50
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Time (µs)
VDD (V)
Max: Typical + 3ı(-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3ı(-40°C to +125°C)
FIGURE 37-77: FVR Stabilization Period,
PIC16LF1777/8/9 Only. FIGURE 37-78: ADC 10-bit Mode,
Single-Ended DNL, VDD = 3.0V , TAD = 1
S, 25° C.
Typical
Max.
10
15
20
25
30
35
40
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Time (µs)
VDD (mV)
Max: Typical + 3ı
Typical: statistical mean @ 25°C
Note:
The FVR Stabiliztion Period applies when coming out of RESET
or exiting sleep mode.
-1.0
-0.5
0.0
0.5
1.0
0 128 256 384 512 640 768 896 1024
DNL (LSb)
Output Code
Microchip Technology Inc. DS40001819B-page 589
PIC16(L)F1777/8/9
Note: Unless otherwise noted, VIN =5V, FOSC = 300 kHz, CIN = 0.1 µF, TA=25°C.
FIGURE 37-79: ADC 10 - bi t Mo de ,
Single-Ended DNL, VDD = 3.0V, TAD = 4
S, 25° C. FIGURE 37-80: ADC 1 0-bit Mode,
Single-Ended INL, VDD = 3.0V, TAD = 1
S, 25°C .
-1.0
-0.5
0.0
0.5
1.0
0 128 256 384 512 640 768 896 1024
DNL (LSb)
Output Code
-1.0
-0.5
0.0
0.5
1.0
0 128 256 384 512 640 768 896 1024
INL (LSb)
Output Code
FIGURE 37-81: ADC 10 - bi t Mo de ,
Single-Ended INL, VDD = 3.0V, TAD = 4
S, 25°C . FIGURE 37-82: ADC 10-bit Mode,
Single-Ended DNL, VDD = 3.0V, VREF = 3.0V.
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
0 512 1024 1536 2048 2560 3072 3584 4096
DNL (LSb)
Output Code
-1.0
-0.5
0.0
0.5
1.0
0 128 256 384 512 640 768 896 1024
INL (LSb)
Output Code
Min. 25°C
Min. 25°C
Min. 125°C
Min. -40°C
Min. -40°C
Min. 125°C
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
5.0E-07 1.0E-06 2.0E-06 4.0E-06 8.0E-06
DNL (LSB)
TADs
FIGURE 37-83: ADC 10 - bi t Mo de ,
Single-Ended INL, VDD = 3.0V, VREF = 3.0V. FIGURE 37-84: ADC 10-bit Mode ,
Single-Ended DNL, VDD = 3.0V, TAD = 1
S.
,,,,
Max. 25°C
Min. 25°C
Max. -40°C
Min. 125°C
Min. -40°C
Max. 125°C
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
5.0E-07 1.0E-06 2.0E-06 4.0E-06 8.0E-06
INL (LSB)
TADs
Max. 25°C
Min. 25°C
Max. -40°C
Min. -40°C
Max. 125°C
Min. 125°C
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
1.8 2.3 3.0
DNL (LSB)
VREF
PIC16(L)F1777/8/9
DS40001819B-page 590 2015-2016 Microchip Technology Inc.
Note: Unless otherwise noted, VIN =5V, FOSC = 300 kHz, CIN = 0.1 µF, TA=25°C.
FIGURE 37-85: ADC 10 - bi t Mo de ,
Single-Ended INL, VDD = 3.0V, TAD = 1
S. FIGURE 37-86: Temperature Indicator Initial
Offset, High Range, Temp. = 20°C,
PIC16 F17 77 / 8/9 on ly.
Max. 25°C
Min. 25°C
Max. -40°C
Min. -40°C
Max. 125°C
Min. 125°C
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
1.8 2.3 3.0
INL (LSB)
VREF
Typical
Max.
Min.
0
100
200
300
400
500
600
700
800
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
ADC Output Codes
V
DD
(V)
ADC VREF+ SET TO VDD
ADC VREF-SET TO GND
Max: Typical + 3ı
Typical; statistical mean
Min: Typical - 3ı
FIGURE 37-87: Temperature Indicator Initial
Offset, Low Range, Temp. = 20°C,
PIC16F1777/8/9 only.
FIGURE 37-88: Temperature Indicator Initial
Offset, Low Range, Temp. = 20°C,
PIC16LF1773/6 only.
Typical
Max.
Min.
300
400
500
600
700
800
900
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
ADC Output Codes
VDD (V)
ADC VREF+ SET TO VDD
ADC VREF-SET TO GND
Max: Typical + 3ı
Typical; statistical mean
Min: Typical - 3ı
Typical
Max.
Min.
100
200
300
400
500
600
700
800
1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 3.9
ADC Output Codes
VDD (V)
ADC VREF+ SET TO VDD
ADC VREF-SET TO GND
Max: Typical + 3ı
Typical; statistical mean
Min: Typical - 3ı
FIGURE 37-89: Temperature Indicator Slope
Normalized to 20°C, PIC16F1777/8/9 only. FIGURE 37-90: Temperature Indicator Slope
Norm al ize d t o 20 °C, Hi gh Ra ng e, VDD = 3.6V,
PIC16 F17 77 / 8/9 on ly.
Typical
Max.
Min.
-75
-50
-25
0
25
50
75
100
125
150
-50 -25 0 25 50 75 100 125 150
ADC Output Codes
Temperature (°C)
ADC VREF+ SET TO VDD
ADC VREF-SET TO GND
Max: Typical + 3ı
Typical; statistical mean
Min: Typical - 3ı
Typical
Max.
Min.
-150
-100
-50
0
50
100
150
200
250
-50-250 255075100125150
ADC Output Codes
Temperature (°C)
ADC VREF+ SET TO VDD
ADC VREF-SET TO GND
Max: Typical + 3ı
Typical; statistical mean
Min: Typical - 3ı
Microchip Technology Inc. DS40001819B-page 591
PIC16(L)F1777/8/9
Note: Unless otherwise noted, VIN =5V, FOSC = 300 kHz, CIN = 0.1 µF, TA=25°C.
FIGURE 37-91: Temperature Indicator Slope
Normalized to 20°C, Low Range, VDD = 3.0V,
PIC16F1777/8/9 only.
FIGURE 37-92: Temp. Indicat or Slope
Norma lized to 20° C, Low Ra nge, VDD = 1.8V,
PIC16 LF1 77 3/ 6 O n ly.
Typical
Max.
Min.
-75
-50
-25
0
25
50
75
100
125
150
-50 -25 0 25 50 75 100 125 150
ADC Output Codes
Temperature (°C)
ADC VREF+ SET TO VDD
ADC VREF-SET TO GND
Max: Typical + 3ı
Typical; statistical mean
Min: Typical - 3ı
Typical
Max.
Min.
-150
-100
-50
0
50
100
150
200
250
-50-25 0 255075100125150
ADC Output Codes
Temperature (°C)
ADC VREF+ SET TO VDD
ADC VREF-SET TO GND
Max: Typical + 3ı
Typical; statistical mean
Min: Typical - 3ı
FIGURE 37-93: Temp. Indicat or Slope
Norma lized to 20° C, L ow Rang e, VDD = 3.0V,
PIC16 LF 1 77 3/ 6 Only.
FIGURE 37-94: Temp. Indicat or Slope
Norma lized to 20° C, H igh R ang e, VDD = 3.6V,
PIC16 LF1 77 3/ 6 O n ly.
Typical
Max.
Min.
-100
-50
0
50
100
150
-50 -25 0 25 50 75 100 125 150
ADC Output Codes
Temperature (°C)
ADC VREF+ SET TO VDD
ADC VREF-SET TO GND
Max: Typical + 3ı
Typical; statistical mean
Min: Typical - 3ı
Typical
Max.
Min.
-150
-100
-50
0
50
100
150
200
250
-50 -25 0 25 50 75 100 125 150
ADC Output Codes
Temperature (°C)
Max: Typical + 3ı
Typical; statistical mean
Min: Typical - 3ı
ADC VREF+ SET TO VDD
ADC VREF-SET TO GND
FIGURE 37-95: Op Amp, Common Mode
Rejection Ratio (CMRR), VDD = 3.0V. FIGURE 37-96: Op Amp, Offset Voltage
Histogram, VDD = 3.0V, VCM = VDD/2.
Min.
Typical
Max.
40
45
50
55
60
65
70
75
80
-50 -25 0 25 50 75 100 125 150
CMRR (dB)
Temperature (°C)
Max: Typical + 3ı
Typical; statistical mean
Min: Typical - 3ı
0%
5%
10%
15%
20%
25%
30%
35%
-7-5-4-3-2-101234567
Percent of Units
Offset Voltage (mV)
-40°C
25°C
85°C
125°C
Sample Size = 3,200
PIC16(L)F1777/8/9
DS40001819B-page 592 2015-2016 Microchip Technology Inc.
Note: Unless otherwise noted, VIN =5V, FOSC = 300 kHz, CIN = 0.1 µF, TA=25°C.
FIGURE 37-97: Op Amp, Offset over
Common Mode Voltage, VDD = 3.0V,
Temp. = 25°C
FIGURE 37-98: Op Amp, Offset over
Common Mode Voltage, VDD = 5.0V,
Temp. = 25°C, PIC16F1777/8/9 Only.
Min.
Typical
Max.
-8
-6
-4
-2
0
2
4
6
8
-0.3 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
Offset Voltage (V)
Common Mode Voltage (V)
Max: Typical + 3ı
Typical; statistical mean
Min: Typical - 3ı
Min.
Typical
Max.
-8
-6
-4
-2
0
2
4
6
8
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Offset Voltage (V)
Common Mode Voltage (V)
Max: Typical + 3ı
Typical; statistical mean
Min: Typical - 3ı
FIGURE 37-99 : Op Amp, Output Slew Rate,
Rising Edge, PIC16F1777/8/9 Only. FIGURE 37-100: Op Amp, Output Slew Rate,
Falling Edge, PIC16F1777/8/9 Only.
VDD = 2.3V
VDD = 3V
VDD = 3.6V
VDD = 5.5V
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
-60 -40 -20 0 20 40 60 80 100 120 140
Slew Rate (V/µs)
Temperature (°C)
VDD = 2.3V
VDD = 3V
VDD = 3.6V
VDD = 5.5V
3.6
3.8
4.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4
-60 -40 -20 0 20 40 60 80 100 120 140
Slew Rate (V/µs)
Temperature (°C)
FIGURE 37 - 101 : Op Amp, Output Drive
Strength, VDD = 5.0V, Temp. = 25°C,
PIC16F1777/8/9 Only.
FIGURE 37- 102: Comparator Hysteresis,
NP Mode (CxSP = 1), VDD = 3.0V, Typical
Measured Values.
VIN = 2.3V
VIN = 3V
VIN = 5V
0.0
1.0
2.0
3.0
4.0
5.0
6.0
0 20406080100120
Output Voltage (V)
Drive Current (mA)
-40°C
25°C
125°C
85°C
25
27
29
31
33
35
37
39
41
43
45
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Hysteresis (mV)
Common Mode Voltage (V)
Microchip Technology Inc. DS40001819B-page 593
PIC16(L)F1777/8/9
Note: Unless otherwise noted, VIN =5V, FOSC = 300 kHz, CIN = 0.1 µF, TA=25°C.
FIGURE 37 - 103 : Comparator Offset,
NP Mode (CxSP = 1), VDD = 3.0V, Typical
Measured Values at 25°C.
FIGURE 37- 104: Comparator Offset,
NP Mode (CxSP = 1), VDD = 3.0V, Typical
Measured Values from -40°C to 125°C.
Max.
Min.
-20
-15
-10
-5
0
5
10
15
20
25
30
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Offset Voltage (mV)
Common Mode Voltage (V)
Max.
Min.
-20
-15
-10
-5
0
5
10
15
20
25
30
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Offset Voltage (mV)
Common Mode Voltage (V)
FIGURE 37 - 105 : Comparator Hysteresis,
NP Mode (CxSP = 1), VDD = 5.5V, Typical
Measured Values, PIC16F177 7/8/9 only.
FIGURE 37- 106: Comparator Offset,
NP Mode (CxSP = 1), VDD = 5.0V, Typical
Measured Values at 25° C, PIC16F1777/8/9 only.
-40°C
25°C
125°C
85°C
20
25
30
35
40
45
50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Hysteresis (mV)
Common Mode Voltage (V)
Max.
Min.
-20
-15
-10
-5
0
5
10
15
20
25
30
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Hysteresis (mV)
Common Mode Voltage (V)
FIGURE 37 - 107 : Comparator Offset,
NP Mode (CxSP = 1), VDD = 5.5V, Typical
Measured Values from -40°C to 125°C,
PIC16F1777/8/9 only.
FIGURE 37-108: Comparator Response Time
Over Volt age, NP Mod e (CxSP = 1), Typical
Measured Values.
Max.
Min.
-20
-10
0
10
20
30
40
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Offset Voltage (mV)
Common Mode Voltage (V)
Min.
Typical
Max.
0
20
40
60
80
100
120
140
1.5 2.0 2.5 3.0 3.5 4.0
Time (ns)
VDD (V)
Max: Typical + 3ı(-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3ı(-40°C to +125°C)
PIC16(L)F1777/8/9
DS40001819B-page 594 2015-2016 Microchip Technology Inc.
Note: Unless otherwise noted, VIN =5V, FOSC = 300 kHz, CIN = 0.1 µF, TA=25°C.
FIGURE 37-10 9: Comparator Response Time
Over Volt age, NP Mod e (CxSP = 1), Typical
Meas ured Values, PIC16F1777/8/9 Only.
FIGURE 37-110: Com parator Ou tput Filter
Delay Time Over Temp., NP Mode (CxSP = 1),
Typical Measured Values, PIC16LF1777/8/9
Only.
Min.
Typical
Max.
0
10
20
30
40
50
60
70
80
90
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Time (ns)
VDD (V)
Max: Typical + 3ı(-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3ı(-40°C to +125°C)
Min.
Typical
Max.
0
200
400
600
800
1,000
1,200
1,400
1.5 2.0 2.5 3.0 3.5 4.0
Time (ns)
V
DD
(V)
Max: Typical + 3ı(-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3ı(-40°C to +125°C)
FIGURE 37-111 : Comparator Output Filter
Delay Time Over Temp., NP Mode (CxSP = 1),
Typical Measured Values, PIC16F1777/8/9 Only.
FIGURE 37-112: Typical DAC DNL Error,
VDD = 3.0V, VREF = External 3V.
()
Min.
Typical
Max.
0
100
200
300
400
500
600
700
800
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Time (ns)
VDD (V)
Max: Typical + 3ı(-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3ı(-40°C to +125°C)
-0.020
-0.015
-0.010
-0.005
0.000
0.005
0.010
0.015
0.020
0.025
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
DNL (LSb)
Output Code
-40°C
25°C
85°C
125°C
FIGURE 37-113: Typi cal DAC INL Error,
VDD = 3.0V, VREF = External 3V. FIGURE 37-114: Typical DAC DNL Error,
VDD = 5.0V, VREF = External 5V,
PIC16F1 777/8/9 On ly.
-0.45
-0.40
-0.35
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
INL (LSb)
Output Code
-40°C
25°C
85°C
125°C
-0.015
-0.010
-0.005
0.000
0.005
0.010
0.015
0.020
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
DNL (LSb)
Output Code
-40°C
25°C
85°C
125°C
Microchip Technology Inc. DS40001819B-page 595
PIC16(L)F1777/8/9
Note: Unless otherwise noted, VIN =5V, FOSC = 300 kHz, CIN = 0.1 µF, TA=25°C.
FIGURE 37-115: Typi cal DAC INL Error,
VDD = 5.0V, VREF = External 5V,
PIC16F1777/8/9 Only.
FIGURE 37-116: DAC INL Error,
VDD = 3.0V, PIC16LF1773/6 Only.
-0.45
-0.40
-0.35
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
INL (LSb)
Output Code
-40°C
25°C
85°C
125°C
,
Typical
Max.
Min.
10
12
14
16
18
20
22
24
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8
DNL (LSb)
Output Code
Max: Typical + 3ı(-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3ı(-40°C to +125°C)
FIGURE 37-117: Absolute V alue of DAC DNL
Error, VDD = 3.0V, VREF = VDD.FIGURE 37-118: Absolute Value of DAC INL
Error, VDD = 3.0V, VREF = VDD.
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
-50 0 50 100 150
Absolute DNL (LSb)
Temperature (°C)
Vref = Int. Vdd
Vref = Ext. 1.8V
Vref = Ext. 2.0V
Vref = Ext. 3.0V
0.0
0.1
0.2
0.3
0.4
-60 -40 -20 0 20 40 60 80 100 120 140
Absolute DNL (LSb)
Temperature (°C)
VREF = INT. VDD
VREF = EXT. 1.8V
VREF = EXT. 2.0V
VREF = EXT. 3.0V
-3.5
-3.3
-3.1
-2.9
-2.7
-2.5
-2.3
-2.1
0.0 1.0 2.0 3.0 4.0 5.0
Absolute INL (LSb)
Temperature (°C)
-40
25
85
125
0.78
0.80
0.82
0.84
0.86
0.88
0.90
-60 -40 -20 0 20 40 60 80 100 120 140
Absolute INL (LSb)
Temperature (°C)
V
REF
= I
NT
. V
DD
V
REF
= E
XT
. 1.8V
V
REF
= E
XT
. 2.0V
V
REF
= E
XT
. 3.0V
FIGURE 37-119: Absolute V alue of DAC DNL
Error, VDD = 5.0V, VREF = VDD, PIC1 6F 17 77/8 /9
Only.
FIGURE 37-120: Absolute Value of DAC INL
Error, VDD = 5.0V, VREF = VDD, PIC16F1777/8/9
Only.
0
0.05
0.1
0.15
0.2
0.25
0.3
0.0 1.0 2.0 3.0 4.0 5.0 6.0
Absolute DNL (LSb)
Temperature (°C)
-40
25
85
125
0.10
0.14
0.18
0.22
0.26
0.30
-60 -40 -20 0 20 40 60 80 100 120 140
Absolute DNL (LSb)
Temperature (°C)
V
REF
= I
NT
. V
DD
V
REF
= E
XT
. 1.8V
V
REF
= E
XT
. 2.0V
V
REF
= E
XT
. 3.0V
V
REF
= E
XT
. 5.0V
-3.5
-3.3
-3.1
-2.9
-2.7
-2.5
-2.3
-2.1
0.0 1.0 2.0 3.0 4.0 5.0 6.0
Absolute INL (LSb)
Temperature (°C)
-40
25
85
125
0.78
0.80
0.82
0.84
0.86
0.88
0.90
-60 -40 -20 0 20 40 60 80 100 120 140
Absolute INL (LSb)
Temperature (°C)
V
REF
= I
NT
. V
DD
V
REF
= E
XT
. 1.8V
V
REF
= E
XT
. 2.0V
V
REF
= E
XT
. 3.0V
V
REF
= E
XT
. 5.0V
PIC16(L)F1777/8/9
DS40001819B-page 596 2015-2016 Microchip Technology Inc.
Note: Unless otherwise noted, VIN =5V, FOSC = 300 kHz, CIN = 0.1 µF, TA=25°C.
FIGURE 37-121: DAC DNL Error, VDD = 3.0 V,
VREF = External 3V. FIGURE 37-122: DAC INL Error , VDD = 3.0V,
VREF = External 3V.
-0.20
-0.10
0.00
0.10
0.20
0.30
0.40
0.50
0 128 256 384 512 640 768 896
DNL (LSb)
Output Code
Typical: 25°C
Max: 85°C + 3ı
-0.50
0.00
0.50
1.00
1.50
2.00
2.50
0 128 256 384 512 640 768 896
INL (LSb)
Output Code
Typical: 25°C
Max: 85°C + 3ı
FIGURE 37-123: DAC DNL Error, VDD = 5.0 V,
VREF = External 5V, PIC16F1777/8/9 Only. FIGURE 37-124: Typical DAC INL Error, VDD
= 5.0V, VREF = External 5V, PIC16F1777/8/9
Only.
-0.20
-0.10
0.00
0.10
0.20
0.30
0.40
0 128 256 384 512 640 768 896
DNL (LSb)
Output Code
Typical: 25°C
Max: 85°C + 3ı
-0.50
0.00
0.50
1.00
1.50
2.00
2.50
0 128 256 384 512 640 768 896
INL (LSb)
Output Code
Typical: 25°C
Max: 85°C + 3ı
FIGURE 37-12 5: Absolute V alue of DAC DNL
Error, VDD = 3.0V, VREF = VDD.FIGURE 37-126: Absolute Value of DAC INL
Error, VDD = 3.0V, VREF = VDD.
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
-50 0 50 100 150
Absolute DNL (LSb)
Temperature (°C)
Vref = Int. Vdd
Vref = Ext. 1.8V
Vref = Ext. 2.0V
Vref = Ext. 3.0V
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
-60 -40 -20 0 20 40 60 80 100 120 140
Absolute DNL (LSb)
Temperature (°C)
VREF = INT. VDD
VREF = EXT. 1.8V
VREF = EXT. 2.0V
VREF = EXT. 3.0V
-3.5
-3.3
-3.1
-2.9
-2.7
-2.5
-2.3
-2.1
0.0 1.0 2.0 3.0 4.0 5.0
Absolute INL (LSb)
Temperature (°C)
-40
25
85
125
0.30
0.80
1.30
1.80
2.30
2.80
-60 -40 -20 0 20 40 60 80 100 120 140
Absolute INL (LSb)
Temperature (°C)
V
REF
= I
NT
. V
DD
V
REF
= E
XT
. 1.8V
V
REF
= E
XT
. 2.0V
V
REF
= E
XT
. 3.0V
Microchip Technology Inc. DS40001819B-page 597
PIC16(L)F1777/8/9
Note: Unless otherwise noted, VIN =5V, FOSC = 300 kHz, CIN = 0.1 µF, TA=25°C.
FIGURE 37-12 7: Absolute V alue of DAC DNL
Error, VDD = 5.0V, VREF = VDD, PIC1 6F 17 77/8 /9
Only.
FIGURE 37-128: Absolute Value of DAC INL
Error, VDD = 5.0V, VREF = VDD, PIC16F1777/8/9
Only.
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0.0 1.0 2.0 3.0 4.0 5.0 6.0
Absolute DNL (LSb)
Temperature (°C)
-40
25
85
125
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
-60 -40 -20 0 20 40 60 80 100 120 140
Absolute DNL (LSb)
Temperature (°C)
V
REF
= I
NT
. V
DD
V
REF
= E
XT
. 1.8V
V
REF
= E
XT
. 2.0V
V
REF
= E
XT
. 3.0V
V
REF
= E
XT
. 5.0V
,,
-3.5
-3.3
-3.1
-2.9
-2.7
-2.5
-2.3
-2.1
0.0 1.0 2.0 3.0 4.0 5.0 6.0
Absolute INL (LSb)
Temperature (°C)
-40
25
85
125
0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
-60 -40 -20 0 20 40 60 80 100 120 140
Absolute INL (LSb)
Temperature (°C)
VREF = INT. VDD
VREF = EXT. 1.8V
VREF = EXT. 2.0V
VREF = EXT. 3.0V
VREF = EXT. 5.0V
FIGURE 37-12 9: ZCD Pin Voltage, Typical
Measured Values. FIGURE 37-130: ZCD Response Time over
Voltage, Typical Measured Values.
-40°C
25°C
125°C
85°C
0.60
0.65
0.70
0.75
0.80
0.85
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
ZCD Pin Voltage (V)
VDD (V)
Fall-2.3V
Fall-3.0V
Fall-5.5V
Rise-2.3V
Rise-3.0V
Rise-5.5V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
-50 -25 0 25 50 75 100 125 150
Time (µs)
Temperature (°C)
FIGURE 37-13 1: ZCD Pin Current over ZCD
Pin Voltage, Typical Measured Values from
-40°C to 125°C.
FIGURE 37-132: ZCD Pin Response Time
over Current, Typical Measured Values from
-40°C to 125°C.
1.8V
2.3V
3.0V
5.5V
-4.0
-2.0
0.0
2.0
4.0
6.0
8.0
-0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20
ZCD Source/Sink Current (mA)
ZCD Pin Voltage (V)
Title TYPICAL MEASURED VALUES FROM 40 C to 125 C
1.8V
2.3V
3.0V
5.5V
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
0 100 200 300 400 500
Time (µs)
ZCD Source/Sink Current (uA)
PIC16(L)F1777/8/9
DS40001819B-page 598 2015-2016 Microchip Technology Inc.
Note: Unless otherwise noted, VIN =5V, FOSC = 300 kHz, CIN = 0.1 µF, TA=25°C.
FIGURE 37-13 3: COG Dead-Band Delay,
DBR/DBF = 32, Typical Measured Values. FIGURE 37-134: COG Dead-Band Delay,
DBR/DBF Delay per Step, Typical Measured
Values.
-40°C
25°C
125°C
85°C
0.14
0.16
0.18
0.20
0.22
0.24
0.26
0.28
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Time (µs)
VDD (V)
Title TYPICAL MEASURED VALUES
-40°C
25°C
85°C
125°C
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Time (ns)
VDD (V)
FIGURE 37-13 5: COG Dead-Band Delay per
Step, Typical Measured Values. FIGURE 37-136: COG Dead-Band Delay per
Step, Zoomed to First 10 Codes, Typical
Measured Values.
Title TYPICAL MEASURED VALUES
Typical
Max.
Min.
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0 10203040506070
Time (µs)
DBR/DBF Value
Max: Typical + 3ı
Typical; statistical mean
Min: Typical - 3ı
Typical
Max.
Min.
0.00
0.01
0.02
0.03
0.04
0.05
0.06
0.07
01234567891011
Time (µs)
DBR/DBF Value
Max: Typical + 3ı
Typical; statistical mean
Min: Typical - 3ı
2015-2016 Microchip Technology Inc. DS40001819B-page 599
PIC16(L)F1777/8/9
38.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
•Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
38.1 MPLAB X Integrated Developme nt
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for high-
performance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as you type
• Automatic code formatting based on user-defined
rules
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
PIC16(L)F1777/8/9
DS40001819B-page 600 2015-2016 Microchip Technology Inc.
38.2 MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16, and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other relo-
catable object files and archives to create an execut-
able file. MPLAB XC Compiler uses the assembler to
produce its object file. Notable features of the assem-
bler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
• Rich directive set
• Flexible macro language
• MPLAB X IDE compatibility
38.3 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
38.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
38.5 MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
• Rich directive set
• Flexible macro language
• MPLAB X IDE compatibility
2015-2016 Microchip Technology Inc. DS40001819B-page 601
PIC16(L)F1777/8/9
38.6 MPLAB X SIM Sof tware Simul ator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
38.7 MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgradeable through future firm-
ware downloads in MPLAB X IDE. MPLAB REAL ICE
offers significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
38.8 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a high-
speed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
38.9 PICkit 3 In-Circuit De bugger/
Programmer
The MPLAB PICkit 3 allows debugging and program-
ming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a full-
speed USB interface and can be connected to the tar-
get via a Microchip debug (RJ-11) connector (compati-
ble with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
38.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a mod-
ular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
PIC16(L)F1777/8/9
DS40001819B-page 602 2015-2016 Microchip Technology Inc.
38.11 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide applica-
tion firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstra-
tion software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
38.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
2015-2016 Microchip Technology Inc. DS40001819B-page 603
PIC16(L)F1777/8/9
39.0 PACKAGING INFORMATION
39.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC® designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
28-Lead SOIC (7.50 mm) Example
YYWWNNN
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
28-Lead SPDIP (.300”) Example
PIC16F1778-SO
3
e
1548017
PIC16F1778-SP
1548017
3
e
28-Lead SSOP (5.30 mm) Example
PIC16F1778
-SS
3
e
1548017
PIC16(L)F1777/8/9
DS40001819B-page 604 2015-2016 Microchip Technology Inc.
Package Marking Information (Continued)
28-Lead UQFN (6x6 mm) Example
XXXXXXXX
XXXXXXXX
YYWWNNN
PIN 1 PIN 1
16F1778
/ML
1548017
3
e
40-Lead PDIP (600 mil) Example
XXXXXXXXXXXXXXXXXX
YYWWNNN
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
PIC16F1777
/P
3
e
1526017
40-Lead UQFN (5x5x0.5 mm) Example
PIN 1 PIN 1
PIC16
/MV
1526017
3
e
F1779
44-Lead QFN (8x8x0.9 mm) Example
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
XXXXXXXXXXX
PIN 1 PIN 1
2015-2016 Microchip Technology Inc. DS40001819B-page 605
PIC16(L)F1777/8/9
Package Marking Information (Continue d)
44-Lead TQFP (10x10x1 mm) Example
XXXXXXXXXX
YYWWNNN
XXXXXXXXXX
XXXXXXXXXX
16F1779
/PT
1526017
3
e
PIC16(L)F1777/8/9
DS40001819B-page 606 2015-2016 Microchip Technology Inc.
39.2 Package Details
The following sections give the technical details of the packages.
!
"#
 
 
 
 
 
"# 

 
   
 
 
 
    
  
   
    
   
   
   
    
   
  
NOTE 1
N
12
D
E1
eB
c
E
L
A2
eb
b1
A1
A
3
   
2015-2016 Microchip Technology Inc. DS40001819B-page 607
PIC16(L)F1777/8/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC16(L)F1777/8/9
DS40001819B-page 608 2015-2016 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2015-2016 Microchip Technology Inc. DS40001819B-page 609
PIC16(L)F1777/8/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC16(L)F1777/8/9
DS40001819B-page 610 2015-2016 Microchip Technology Inc.
$%&'(&!
"#
 
 
 
 
 
"# 

 
   
 
 
 
    
  
   
    
   
   
  
  
   
  
L
L1
c
A2
A1
A
E
E1
D
N
12
NOTE 1 b
e
φ
   
2015-2016 Microchip Technology Inc. DS40001819B-page 611
PIC16(L)F1777/8/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC16(L)F1777/8/9
DS40001819B-page 612 2015-2016 Microchip Technology Inc.
B
A
0.15 C
2X
0.15 C
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-0209 Rev C Sheet 1 of 2
C
Note:
2X
0.08 C
0.10 C A B
0.05 C
SEATING
PLANE
N
N
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTE 1
NOTE 4
(DATUM A)
(DATUM B)
D
E
(A3) A1
A
D2
E2
L
K
b
0.10 C
0.10 C A B
2
1
2
1
NOTE 4
28-Lead Plastic Quad Flat, No Lead Package (MX) - 6x6x0.5mm Body [UQFN]
Ultra-Thin with 0.40 x 0.60 mm Terminal Width/Length and Corner Anchors
4x b1
4x b2 0.10 C A B
4x b1
e
4x b2
2015-2016 Microchip Technology Inc. DS40001819B-page 613
PIC16(L)F1777/8/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Number of Pins
Overall Width
Overall Length
Overall Height
Terminal Length
Exposed Pad Width
Exposed Pad Length
Standoff
Pitch
D2
L
D
Units
Dimension Limits
A1
E2
E
A
e
N
0.55 0.60
6.00 BSC
4.00
MILLIMETERS
0.65 BSC
0.00
0.40
MIN
6.00 BSC
0.50
0.02
4.00
NOM
28
0.65
0.60
0.05
MAX
K-0.20 -
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
3.
Notes:
Terminal Thickness (A3) 0.127 REF
Terminal-to-Exposed Pad
Corner Pad, Metal Free Zone b2 0.15 0.20 0.25
Terminal Width b0.35 0.40 0.45
Pin 1 visual index feature may vary, but must be located within the hatched area.
Package is saw singulated
Dimensioning and tolerancing per ASME Y14.5M
4. Outermost portions of corner structures may vary slightly.
Corner Pad b1 0.55 0.60 0.65
Microchip Technology Drawing C04-0209 Rev C Sheet 2 of 2
PIC16(L)F1777/8/9
DS40001819B-page 614 2015-2016 Microchip Technology Inc.
RECOMMENDED LAND PATTERN
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
T2
SILK SCREEN
X1
C1
W1
E
G
Y1
C2
X2
Y2
Dimension Limits
Units
C1
Optional Center Pad Width
Contact Pad Spacing
Contact Pad Spacing
Optional Center Pad Length
Contact Pitch
C2
T2
W1
4.05
4.05
MILLIMETERS
0.65 BSC
MIN
E
MAX
5.70
5.70
Contact Pad Length (X28)
Contact Pad Width (X28)
Y1
X1
1.00
0.45
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
Microchip Technology Drawing No. C04-2209B
GDistance Between Pads 0.20
NOM
Corner Pad Length (X4)
Corner Pad Width (X4)
Y2
X2
0.90
0.90
28-Lead Plastic Quad Flat, No Lead Package (MX) - 6x6 mm Body [UQFN]
With 0.60mm Contact Length And Corner Anchors
2015-2016 Microchip Technology Inc. DS40001819B-page 615
PIC16(L)F1777/8/9
)*!
"#
 
 
 
 
 
"# 

 
   
 
 
 
   
 
  
  
  
  
  
   
  
  
N
NOTE 1
E1
D
123
A
A1 b1
be
c
eB
E
L
A2
   
PIC16(L)F1777/8/9
DS40001819B-page 616 2015-2016 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2015-2016 Microchip Technology Inc. DS40001819B-page 617
PIC16(L)F1777/8/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC16(L)F1777/8/9
DS40001819B-page 618 2015-2016 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2015-2016 Microchip Technology Inc. DS40001819B-page 619
PIC16(L)F1777/8/9
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Microchip Technology Drawing C04-103D Sheet 1 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN]
B
A
0.20 C
0.20 C
0.07 C A B
0.05 C
(DATUM B)
(DATUM A)
C
SEATING
PLANE
NOTE 1
1
2
N
2X
NOTE 1
1
2
N
0.10 C A B
0.10 C A B
0.10 C
0.08 C
2X
44X
D
E
A3
A
A1
D2
E2
L
44X b
K
e
PIC16(L)F1777/8/9
DS40001819B-page 620 2015-2016 Microchip Technology Inc.
Microchip Technology Drawing C04-103D Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Number of Pins
Overall Height
Terminal Width
Overall Width
Overall Length
Terminal Length
Exposed Pad Width
Exposed Pad Length
Terminal Thickness
Pitch
Standoff
Units
Dimension Limits
A1
A
b
D
E2
D2
A3
e
L
E
N
0.65 BSC
0.20 REF
6.25
6.25
0.30
0.20
0.80
0.00
0.30
8.00 BSC
0.40
6.45
6.45
0.90
0.02
8.00 BSC
MILLIMETERS
MIN NOM
44
6.60
6.60
0.50
0.35
1.00
0.05
MAX
K-0.20 -
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
3.
Notes:
Pin 1 visual index feature may vary, but must be located within the hatched area.
Package is saw singulated
Dimensioning and tolerancing per ASME Y14.5M
Terminal-to-Exposed-Pad
44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN]
2015-2016 Microchip Technology Inc. DS40001819B-page 621
PIC16(L)F1777/8/9
RECOMMENDED LAND PATTERN
Dimension Limits
Units
C2
Optional Center Pad Width
Contact Pad Spacing
Optional Center Pad Length
Contact Pitch
Y2
X2
6.60
6.60
MILLIMETERS
0.65 BSC
MIN
E
MAX
8.00
Contact Pad Length (X44)
Contact Pad Width (X44)
Y1
X1
0.85
0.35
Microchip Technology Drawing No. C04-2103C
NOM
44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN]
SILK SCREEN
1
2
44
C1Contact Pad Spacing 8.00
Contact Pad to Contact Pad (X40) G1 0.30
Thermal Via Diameter V
Thermal Via Pitch EV
0.33
1.20
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M
For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
1.
2.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
C1
C2
EV
EV
X2
Y2
E
X1
Y1
Contact Pad to Center Pad (X44) G2 0.28
G2
ØV
G1
PIC16(L)F1777/8/9
DS40001819B-page 622 2015-2016 Microchip Technology Inc.
B
A
0.20 H A B
0.20 H A B
44 X b
0.20 C A B
(DATUM B)
(DATUM A)
C
SEATING PLANE
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Microchip Technology Drawing C04-076C Sheet 1 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
e
NOTE 1
12
N
D
D1
EE1
2X
A2
A1
A
0.10 C
3
N
AA
0.20 C A B
4X 11 TIPS
123
44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP]
NOTE 1
NOTE 2
2015-2016 Microchip Technology Inc. DS40001819B-page 623
PIC16(L)F1777/8/9
Microchip Technology Drawing C04-076C Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
L
(L1)
c
θ
SECTION A-A
H
Number of Leads
Overall Height
Lead Width
Overall Width
Overall Length
Lead Length
Molded Package Width
Molded Package Length
Molded Package Thickness
Lead Pitch
Standoff
Units
Dimension Limits
A1
A
b
D
E1
D1
A2
e
L
E
N
0.80 BSC
0.45
0.30
-
0.05
0.37
12.00 BSC
0.60
10.00 BSC
10.00 BSC
-
-
12.00 BSC
MILLIMETERS
MIN NOM
44
0.75
0.45
1.20
0.15
MAX
0.95 1.00 1.05
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
3.
Notes:
Pin 1 visual index feature may vary, but must be located within the hatched area.
Exact shape of each corner is optional.
Dimensioning and tolerancing per ASME Y14.5M
Footprint L1 1.00 REF
θ3.5°0° 7°Foot Angle
Lead Thickness c0.09 - 0.20
44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP]
PIC16(L)F1777/8/9
DS40001819B-page 624 2015-2016 Microchip Technology Inc.
RECOMMENDED LAND PATTERN
44-Lead Plastic Thin Quad Flatpack (PT) - 10X10X1 mm Body, 2.00 mm Footprint [TQFP]
SILK SCREEN
1
2
44
C1
E
G
Y1
X1
C2
Contact Pad Width (X44)
0.25
Contact Pad Length (X44)
Distance Between Pads
X1
Y1
G
1.50
Contact Pad Spacing
Contact Pitch
C1
E
Units
Dimension Limits
11.40
0.55
0.80 BSC
MILLIMETERS
MAXMIN NOM
11.40C2Contact Pad Spacing
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1. Dimensioning and tolerancing per ASME Y14.5M
Notes:
Microchip Technology Drawing No. C04-2076B
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
2015-2016 Microchip Technology Inc. DS40001819B-page 625
PIC16(L)F1777/8/9
APPENDIX A: DATA SHEET
REVISION HISTORY
Revision A (11/2015)
Initial release of this document.
Revision B (10/2016)
Updated Figures 14-1, 23-3, 23-8, 23-9, and 23-10;
Registers 7-5, 7-11, 18-1, 19-1, 24-6, 27-11, 31-3, 31-4,
31-5, 31-6, 31-7, and 32-4; Section 32.6; Tables 3, 4,
3-4, 3-6, 3-7, 3-14, 3-15, 3-18, 12-1, 12-2, 12-3, 24-4,
25-5, 27-5, 27-6, 28-1, 32-4, 36-1, 36-2, 36-7 and 36-8.
Updated the Cover page.
Section 20.5 rewritten. Added Characterization Data.
PIC16(L)F1777/8/9
DS40001819B-page 626 2015-2016 Microchip Technology Inc.
THE MICROCHIP WEBSITE
Microchip provides online support via our website at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the website contains the following information:
•Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
CUSTOMER SUPP ORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the website
at: http://www.microchip.com/support
2015-2016 Microchip Technology Inc. DS40001819B-page 627
PIC16(L)F1777/8/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device: PIC16F1777, PIC16LF1777,
PIC16F1778, PIC16LF1778,
PIC16F1779, PIC16F1779
Tape and Reel
Option: Blank = Standard packaging (tube or tray)
T = Tape and Reel(1)
Temperature
Range: I= -40C to +85C(Industrial)
E= -40
C to +125C (Extended)
Package:(2) MV = UQFN, 40-pin 5x5x0.5 mm
MX = UQFN, 28-pin 6x6x0.5 mm
P=PDIP, 40-pin
PT = TQFN, 44-pin 10x10 mm
ML = QFN, 44-pin 8x8 mm
SO = SOIC, 28-pin
SP = SPDIP, 28-pin
SS = SSOP, 28-pin
Pattern: QTP, SQTP, Code or Special Requirements
(blank otherwise)
Examples:
a) PIC16LF1777-I/P
Industrial temperature
PDIP package
b) PIC16F1779-E/SS
Extended temperature
SSOP package
Note 1: Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package.
Check with your Microchip Sales Office
for package availability with the Tape and
Reel option.
2: Small form-factor packaging options may
be available. Please check
www.microchip.com/packaging for
small-form factor package availability, or
contact your local Sales Office.
[X](1)
Tape and Reel
Option
-
PIC16(L)F1777/8/9
DS40001819B-page 628 2015-2016 Microchip Technology Inc.
NOTES:
2015-2016 Microchip Technology Inc. DS40001819B-page 629
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
KEELOQ logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2015-2016, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-1016-4
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microch ip rece ived IS O/T S-16 94 9:20 09 certificat ion for i ts worldwid e
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPI C® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS40001819B-page 630 2015-2016 Microchip Technology Inc.
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
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Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
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Tel: 512-257-3370
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Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los A n ge les
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
ASIA/PACIFIC
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
China - Dongguan
Tel: 86-769-8702-9880
China - Guangzhou
Tel: 86-20-8755-8029
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
China - Hong K ong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
ASIA/PACIFIC
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Taiwan - Kaohsiung
Tel: 886-7-213-7828
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangko k
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Cop e nha gen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Dusseldorf
Tel: 49-2129-3766400
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Venice
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Worldwide Sales and Service
06/23/16