Single/Dual Battery, 0.9–3.6 V, 16–8 kB, SmaRTClock, 12/10-Bit ADC MCU
C8051F91x-C8051F90x
Rev. 1.1 5/11 Copyright © 2011 by Silicon Laboratories C8051F91x-C8051 F90x
Ultra-Low Power
-160 uA/MHz in active mode (24.5 MHz clock)
-2 us wake-up time (two-cell mode)
-10 nA sleep mode with memory retention;
-50 nA sleep mode with brownout detector
-300 nA sleep mode with LFO (‘F912/02 only)
-600 nA sleep mode with external crystal
Supply Voltage 0.9 to 3.6 V
-One-cell mode supports 0.9 to 1.8 V operation
(‘F911/01). ‘F912 and ‘F902 devices can operate
from 0.9 to 3.6 V continuously
-Two-cell mode supports 1.8 to 3.6 V operation
-Built-in dc-dc converter with 1.8 to 3.3 V output for
use in one-cell mode
-Built-in LDO regulator allows a high analog supply
voltage and low digital core voltage
-2 built in supply monitors (brownout detectors)
12-Bit or 10-Bit Analog to Digital Converter
-±1 LSB INL (10-bit mode); ±1.5 LSB INL (12-bit
mode, ‘F912/02 only) no missing codes
-Programmable throughput up to 300 ksps (10-Bit
Mode) or 75 ksps (12-bit mode, ‘F912/02 only)
-Up to 15 external inputs
-On-chip voltage reference
-On-Chip PGA allows measuring volt ages up to twice
the reference voltage
-16-bit auto-averaging accumulator with burst mode
provides increased ADC resolution
-Data dependent windowed interrupt generator
-Built-in temp erature sensor
Two Comparators
-Programmable hysteresis and response time
-Configurable as wake-up or reset source
-Up to 15 Capacitive Touch Sense Inputs
6-Bit Programmable Current Reference
-Up to ±500 µA. Can be used as a bias or for
generating a custom reference voltage
-PWM enhanced mode on ‘F912/02 devices
High-S peed 8051 µC Core
-Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
-Up to 25 MIPS throughput with 25 MHz clock
-Expanded interrupt handler
Memory
-768 bytes RAM
-16 kB (‘F912/1), or 8 kB (‘F902/1) Flash; In-system
programmable
Digital Peripherals
-16 port I/O; All 5 V tolerant with high sink
current and programmable drive strength
-Hardware SMBus™ (I2C™ Compatible), 2 x SPI™,
and UART serial ports available concurrently
-Four general purpose 16-bit counter/timers
-Programmable 16-bit counter/timer array with six
capture/compare modules and watchdog timer
Clock Sources
-Internal oscillators: 24.5 MHz, 2% accuracy
supports UART operation; 20 MHz low power
oscillator requires very little bias current.
-External oscillator: Crystal, RC, C, or CMOS clock
-SmaRTClock oscillator: 32 kHz crystal or internal
low frequency oscillator (‘F912/02) or self-oscillate
mode
-Can switch between clock sources on-the-fly; useful
in implementing various power saving modes
On-Chip Debug
-On-chip debug circuitry facilitates full-speed, non-
intrusive in-system debug (no emulator required)
-Provides 4 breakpoints, single stepping
-Inspect/modify memory and registers
-Complete development kit
Packages
-24-pin QFN (4 x 4 mm)
-24-pin QSOP (easy to hand-solder)
-Tested die available
Temperature Range: –40 to +85 °C
ANALOG
PERIPHERALS
12/10-bit
75/300 ksps
ADC
16/8 kB
ISP FLASH 768 B SRAM
POR
DEBUG
CIRCUITRY
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
TEMP
SENSOR
DIGITAL I/O
24 .5 MHz P RECISION
INTERNAL OSCILLATOR
HIGH-SPEED CONTROLLER CO RE
A
M
U
X
CROSSBAR
VOLTAGE
COMPARATORS
+
–
WDT
UART
SMBus
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Port 0
2 x SPI
IREF Port 1
Port 2
+
–
VREG
20 MHz LOW POWER
INTERNAL OSCILLATOR
VREF
CRC
HARDWARE SmaRTClockExternal Oscillator
C8051F91x-C8051F90x
2 Rev. 1.1
Rev. 1.1 3
C8051F91x-C8051F90x
Table of Contents
1. System Overview.................................................................................................... 17
1.1. CIP-51™ Microcontroller Core.......................................................................... 20
1.1.1. Fully 8051 Compatible.............................................................................. 20
1.1.2. Improved Throughput............................................................................... 20
1.1.3. Additional Features .................................................................................. 20
1.2. Port Input/Output............................................................................................... 21
1.3. Serial Ports ....................................................................................................... 22
1.4. Programmable Counter Array........................................................................... 22
1.5. SAR ADC with 16-bit Auto-Averaging Accumulator and
Autonomous Low Power Burst Mode ............................................................... 23
1.6. Programmable Current Reference (IREF0)...................................................... 24
1.7. Comparators..................................................................................................... 24
2. Ordering Information.............................................................................................. 26
3. Pinout and Package Definitions............................................................................ 27
4. Electrical Characteristics....................................................................................... 36
4.1. Absolute Maximum Specifications.................................................................... 36
4.2. Electrical Characteristics................................................................................... 37
5. SAR ADC with 16-bit Auto-Averaging Accumulator and
Autonomous Low Power Burst Mode................................................................... 61
5.1. Output Code Formatting ................................................................................... 62
5.2. Modes of Operation .......................................................................................... 63
5.2.1. Starting a Conversion............................................................................... 63
5.2.2. Tracking Modes........................................................................................ 64
5.2.3. Burst Mode............................................................................................... 65
5.2.4. Settling Time Requirements..................................................................... 66
5.2.5. Gain Setting.............................................................................................. 67
5.3. 8-Bit Mode......................................................................................................... 67
5.4. 12-Bit Mode (C8051F912/02 Only)................................................................... 67
5.5. Low Power Mode (C8051F912/902 only) ......................................................... 67
5.6. Programmable Window Detector...................................................................... 75
5.6.1. Window Detector In Single-Ended Mode ................................................. 77
5.6.2. ADC0 Specifications................................................................................. 77
5.7. ADC0 Analog Multiplexer.................................................................................. 78
5.8. Temperature Sensor......................................................................................... 80
5.8.1. Calibration................................................................................................ 81
5.9. Voltage and Ground Reference Options........................................................... 83
5.10.External Voltage References............................................................................ 84
5.11.Internal Voltage References............................................................................. 84
5.12.Analog Ground Reference................................................................................ 84
5.13.Temperature Sensor Enable ............................................................................ 84
5.14.Voltage Reference Electrical Specifications..................................................... 85
6. Programmable Current Reference (IREF0) .......................................................... 86
6.1. PWM Enhanced Mode...................................................................................... 86
C8051F91x-C8051F90x
4 Rev. 1.1
6.2. IREF0 Specifications......................................................................................... 87
7. Comparators........................................................................................................... 88
7.1. Comparator Inputs............................................................................................ 88
7.2. Comparator Outputs ......................................................................................... 89
7.3. Comparator Response Time............................................................................. 90
7.4. Comparator Hysteresis..................................................................................... 90
7.5. Comparator Register Descriptions.................................................................... 91
7.6. Comparator0 and Comparator1 Analog Multiplexers........................................ 95
8. CIP-51 Microcontroller........................................................................................... 98
8.1. Performance ..................................................................................................... 98
8.2. Programming and Debugging Support ............................................................. 99
8.3. Instruction Set................................................................................................... 99
8.3.1. Instruction and CPU Timing ..................................................................... 99
8.4. CIP-51 Register Descriptions.......................................................................... 104
9. Memory Organization........................................................................................... 107
9.1. Program Memory............................................................................................ 108
9.1.1. MOVX Instruction and Program Memory ............................................... 108
9.2. Data Memory .................................................................................................. 108
9.2.1. Internal RAM .......................................................................................... 108
9.2.2. External RAM......................................................................................... 110
10.On-Chip XRAM...................................................................................................... 111
10.1.Accessing XRAM............................................................................................ 111
10.1.1.16-Bit MOVX Example........................................................................... 111
10.1.2.8-Bit MOVX Example............................................................................. 111
10.2.Special Function Registers............................................................................. 112
11.Special Function Registers ................................................................................. 113
11.1.SFR Paging.................................................................................................... 114
12.Interrupt Handler ............ ...................................................................................... 120
12.1.Enabling Interrupt Sources............................................................................. 120
12.2.MCU Interrupt Sources and Vectors............................................................... 120
12.3.Interrupt Priorities........................................................................................... 121
12.4.Interrupt Latency............................................................................................. 121
12.5.Interrupt Register Descriptions....................................................................... 123
12.6.External Interrupts INT0 and INT1.................................................................. 130
13.Flash Memory ....................................................................................................... 132
13.1.Programming The Flash Memory................................................................... 132
13.1.1.Flash Lock and Key Functions............................................................... 132
13.1.2.Flash Erase Procedure .......................................................................... 133
13.1.3.Flash Write Procedure ........................................................................... 133
13.2.Non-volatile Data Storage .............................................................................. 133
13.3.Security Options............................................................................................. 134
13.4.Determining the Device Part Number at Run Time........................................ 136
13.5.Flash Write and Erase Guidelines.................................................................. 137
13.5.1.VDD Maintenance and the VDD Monitor ............................................... 137
13.5.2.PSWE Maintenance............................................................................... 138
Rev. 1.1 5
C8051F91x-C8051F90x
13.5.3.System Clock......................................................................................... 138
13.6.Minimizing Flash Read Current...................................................................... 139
14.Power Management.............................................................................................. 143
14.1.Normal Mode.................................................................................................. 144
14.2.Idle Mode........................................................................................................ 145
14.3.Stop Mode...................................................................................................... 145
14.4.Suspend Mode ............................................................................................... 146
14.5.Sleep Mode .................................................................................................... 146
14.6.Configuring Wakeup Sources......................................................................... 147
14.7.Determining the Event that Caused the Last Wakeup.................................... 148
14.8.Power Management Specifications................................................................ 151
15.Cyclic Redundancy Check Unit (CRC0) ............................................................. 152
15.1.CRC Algorithm................................................................................................ 152
15.2.Preparing for a CRC Calculation.................................................................... 154
15.3.Performing a CRC Calculation ....................................................................... 154
15.4.Accessing the CRC0 Result........................................................................... 154
15.5.CRC0 Bit Reverse Feature............................................................................. 159
16.On-Chip DC-DC Converter (DC0)........................................................................ 160
16.1.Startup Behavior............................................................................................. 161
16.2.High Power Applications............................................................................. 162
16.3.Pulse Skipping Mode...................................................................................... 162
16.4.Enabling the DC-DC Converter...................................................................... 163
16.5.Minimizing Power Supply Noise..................................................................... 164
16.6.Selecting the Optimum Switch Size................................................................ 164
16.7.DC-DC Converter Clocking Options............................................................... 164
16.8.DC-DC Converter Behavior in Sleep Mode.................................................... 164
16.9.Bypass Mode (C8051F912/02 only)............................................................... 165
16.10.Low Power Mode (C8051F912/02 only)....................................................... 165
16.11.Passive Diode Mode (C8051F912/02 only).................................................. 166
16.12.DC-DC Converter Register Descriptions...................................................... 167
16.13.DC-DC Converter Specifications.................................................................. 169
17.Voltage Regulator (VREG0)................................................................................. 170
17.1.Voltage Regulator Electrical Specifications.................................................... 170
18.Reset Sources....................................................................................................... 171
18.1.Power-On (VBAT Supply Monitor) Reset....................................................... 172
18.2.Power-Fail (VDD/DC+ Supply M o nitor ) Reset................................................ 173
18.3.External Reset................................................................................................ 176
18.4.Missing Clock Detector Reset ........................................................................ 176
18.5.Comparator0 Reset........................................................................................ 176
18.6.PCA Watchdog Timer Reset .......................................................................... 176
18.7.Flash Error Reset ........................................................................................... 177
18.8.SmaRTClock (Real Time Clock) Reset.......................................................... 177
18.9.Software Reset............................................................................................... 177
19.Clocking Sources................................................................................................. 179
19.1.Programmable Precision Internal Oscillator................................................... 180
C8051F91x-C8051F90x
6 Rev. 1.1
19.2.Low Power Internal Oscillator......................................................................... 180
19.3.External Oscillator Drive Circuit...................................................................... 180
19.3.1.External Crystal Mode............................................................................ 180
19.3.2.External RC Mode.................................................................................. 182
19.3.3.External Capacitor Mode........................................................................ 183
19.3.4.External CMOS Clock Mode.................................................................. 184
19.4.Special Function Registers for Selecting and Configuring the System Clock 185
20.SmaRTClock (Real Time Clock).......................................................................... 188
20.1.SmaRTClock Interface ................................................................................... 189
20.1.1.SmaRTClock Lock and Key Functions................................................... 189
20.1.2.Using RTC0ADR and RTC0DAT to Access SmaRTClock
Internal Registers................................................................................... 190
20.1.3.RTC0ADR Short Strobe Feature............................................................ 190
20.1.4.SmaRTClock Interface Autoread Feature.............................................. 190
20.1.5.RTC0ADR Autoincrement Feature......................................................... 191
20.2.SmaRTClock Clocking Sources ..................................................................... 194
20.2.1.Using the SmaRTClock Oscillator with a Crystal or
External CMOS Clock ............................................................................ 194
20.2.2.Using the SmaRTClock Oscillator in Self-Oscillate Mode...................... 195
20.2.3.Using the Low Frequency Oscillator (LFO)............................................ 195
20.2.4.Programmable Load Capacitance.......................................................... 196
20.2.5.Automatic Gain Control (Crystal Mode Only) and
SmaRTClock Bias Doubling................................................................... 197
20.2.6.Missing SmaRTClock Detector.............................................................. 199
20.2.7.SmaRTClock Oscillator Crystal Valid Detector...................................... 199
20.3.SmaRTClock Timer and Alarm Function........................................................ 199
20.3.1.Setting and Reading the SmaRTClock Timer Value.............................. 199
20.3.2.Setting a SmaRTClock Alarm ................................................................ 200
20.3.3.Software Considerations for using the SmaRTClock Timer and Alarm . 200
21.Port Input/Output.................................................................................................. 205
21.1.Port I/O Modes of Operation........................................................................... 206
21.1.1.Port Pins Configured for Analog I/O....................................................... 206
21.1.2.Port Pins Configured For Digital I/O...... ................................................. 206
21.1.3.Interfacing Port I/O to 5 V and 3.3 V Logic............................................. 207
21.1.4.Increasing Port I/O Drive Strength......................................................... 207
21.2.Assigning Port I/O Pins to Analog and Digital Functions................................ 207
21.2.1.Assigning Port I/O Pins to Analog Functions ......................................... 207
21.2.2.Assigning Port I/O Pins to Digital Functions........................................... 208
21.2.3.Assigning Port I/O Pins to External Digital Event Capture Functions .... 208
21.3.Priority Crossbar Decoder.............................................................................. 209
21.4.Port Match...................................................................................................... 215
21.5.Special Function Registers for Accessing and Configuring Port I/O .............. 217
22.SMBus ................................................................................................................... 225
22.1.Supporting Documents................................................................................... 226
22.2.SMBus Configuration...................................................................................... 226
Rev. 1.1 7
C8051F91x-C8051F90x
22.3.SMBus Operation........................................................................................... 227
22.3.1.Transmitter Vs. Receiver........................................................................ 227
22.3.2.Arbitration............................................................................................... 227
22.3.3.Clock Low Extension.............................................................................. 228
22.3.4.SCL Low Timeout................................................................................... 228
22.3.5.SCL High (SMBus Free) Timeout .......................................................... 228
22.4.Using the SMBus............................................................................................ 229
22.4.1.SMBus Configuration Register............................................................... 230
22.4.2.SMB0CN Control Register..................................................................... 233
22.4.3.Hardware Slave Address Recognition ................................................... 236
22.4.4.Data Register......................................................................................... 238
22.5.SMBus Transfer Modes.................................................................................. 239
22.5.1.Write Sequence (Master)....................................................................... 239
22.5.2.Read Sequence (Master)....................................................................... 240
22.5.3.Write Sequence (Slave)......................................................................... 241
22.5.4.Read Sequence (Slave)......................................................................... 242
22.6.SMBus Status Decoding................................................................................. 242
23.UART0.................................................................................................................... 247
23.1.Enhanced Baud Rate Generation................................................................... 248
23.2.Operational Modes......................................................................................... 249
23.2.1.8-Bit UART............................................................................................. 249
23.2.2.9-Bit UART............................................................................................. 250
23.3.Multiprocessor Communications .................................................................... 250
24.Enhanced Serial Peripheral Interface (SPI0 and SPI1)...................................... 255
24.1.Signal Descriptions......................................................................................... 256
24.1.1.Master Out, Slave In (MOSI).................................................................. 256
24.1.2.Master In, Slave Out (MISO).................................................................. 256
24.1.3.Serial Clock (SCK)................................................................................. 256
24.1.4.Slave Select (NSS) ................................................................................ 256
24.2.SPI Master Mode Operation........................................................................... 257
24.3.SPI Slave Mode Operation............................................................................. 259
24.4.SPI Interrupt Sources..................................................................................... 259
24.5.Serial Clock Phase and Polarity..................................................................... 260
24.6.SPI Special Function Registers...................................................................... 262
25.Timers.................................................................................................................... 270
25.1.Timer 0 and Timer 1....................................................................................... 272
25.1.1.Mode 0: 13-bit Counter/Timer................................................................ 272
25.1.2.Mode 1: 16-bit Counter/Timer................................................................ 273
25.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 274
25.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 275
25.2.Timer 2 .......................................................................................................... 280
25.2.1.16-bit Timer with Auto-Reload................................................................ 280
25.2.2.8-bit Timers with Auto-Reload................................................................ 281
25.2.3.Comparator 0/SmaRTClock Capture Mode........................................... 282
25.3.Timer 3 .......................................................................................................... 286
C8051F91x-C8051F90x
8 Rev. 1.1
25.3.1.16-bit Timer with Auto-Reload................................................................ 286
25.3.2.8-bit Timers with Auto-Reload................................................................ 287
25.3.3.Comparator 1/External Oscillator Capture Mode................................... 288
26.Programmable Counter Array............................................................................. 292
26.1.PCA Counter/Timer........................................................................................ 293
26.2.PCA0 Interrupt Sources.................................................................................. 294
26.3.Capture/Compare Modules ............................................................................ 296
26.3.1.Edge-triggered Capture Mode................................................................ 297
26.3.2.Software Timer (Compare) Mode........................................................... 298
26.3.3.High-Speed Output Mode ...................................................................... 299
26.3.4.Frequency Output Mode ........................................................................ 300
26.3.5. 8-Bit, 9-Bit, 10-Bit and 11-Bit Pulse Width Modulator Modes............... 301
26.3.6. 16-Bit Pulse Width Modulator Mode..................................................... 303
26.4.Watchdog Timer Mode................................................................................... 304
26.4.1.Watchdog Timer Operation.................................................................... 304
26.4.2.Watchdog Timer Usage ......................................................................... 305
26.5.Register Descriptions for PCA0...................................................................... 306
27.C2 Interface........................................................................................................... 312
27.1.C2 Interface Registers.................................................................................... 312
27.2.C2 Pin Sharing ............................................................................................... 315
Document Change List............................................................................................. 316
Contact Information.................................................................................................. 318
Rev. 1.1 9
C8051F91x-C8051F90x
List of Figures
Figure 1.1. C8051F912 Block Diagram.................................................................... 18
Figure 1.2. C8051F911 Block Diagram.................................................................... 18
Figure 1.3. C8051F902 Block Diagram.................................................................... 19
Figure 1.4. C8051F901 Block Diagram.................................................................... 19
Figure 1.5. Port I/O Functional Block Diagram......................................................... 21
Figure 1.6. PCA Block Diagram................................................................................ 22
Figure 1.7. ADC0 Functional Block Diagram............................................................ 23
Figure 1.8. ADC0 Multiplexer Block Diagram........................................................... 24
Figure 1.9. Comparator 0 Functional Block Diagram ............................................... 25
Figure 1.10. Comparator 1 Functional Block Diagram ............................................. 25
Figure 3.1. QFN-24 Pinout Diagram (Top View) ...................................................... 30
Figure 3.2. QSOP-24 Pinout Diagram F912 (Top View) .......................................... 31
Figure 3.3. QFN-24 Package Drawing ..................................................................... 32
Figure 3.4. Typical QFN-24 Landing Diagram.......................................................... 33
Figure 3.5. QSOP-24 Package Diagram.................................................................. 34
Figure 3.6. QSOP-24 Landing Diagram ................................................................... 35
Figure 4.1. Active Mode Current (External CMOS Clock)........................................ 41
Figure 4.2. Idle Mode Current (External CMOS Clock)............................................ 42
Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 2 V)... 43
Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 3 V)... 44
Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC+ = 2 V).... 45
Figure 4.6. Typical One-Cell Suspend Mode Current............................................... 46
Figure 4.7. Typical VOH Curves, 1.8–3.6 V ............................................................. 48
Figure 4.8. Typical VOH Curves, 0.9–1.8 V ............................................................. 49
Figure 4.9. Typical VOL Curves, 1.8–3.6 V.............................................................. 50
Figure 4.10. Typical VOL Curves, 0.9–1.8 V............................................................ 51
Figure 5.1. ADC0 Functional Block Diagram............................................................ 61
Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0).... 64
Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4................... 65
Figure 5.4. ADC0 Equivalent Input Circuits.............................................................. 66
Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended Data... 77
Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data ...... 77
Figure 5.7. ADC0 Multiplexer Block Diagram........................................................... 78
Figure 5.8. Temperature Sensor Transfer Function................................................. 80
Figure 5.9. Temperature Sensor Error with 1-Point Calibration (VREF = 1.68 V) ..... 81
Figure 5.10. Voltage Reference Functional Block Diagram...................................... 83
Figure 7.1. Comparator 0 Functional Block Diagram ............................................... 88
Figure 7.2. Comparator 1 Functional Block Diagram ............................................... 89
Figure 7.3. Comparator Hysteresis Plot ................................................................... 90
Figure 7.4. CPn Multiplexer Block Diagram.............................................................. 95
Figure 8.1. CIP-51 Block Diagram............................................................................ 98
Figure 9.1. C8051F91x-C8051F90x Memory Map................................................. 107
Figure 9.2. Flash Program Memory Map................................................................ 108
C8051F91x-C8051F90x
10 Rev. 1.1
Figure 13.1. Flash Program Memory Map (16 kB and 8 kB devices)..................... 134
Figure 14.1. C8051F91x-C8051F90x Power Distribution....................................... 144
Figure 15.1. CRC0 Block Diagram......................................................................... 152
Figure 15.2. Bit Reverse Register .......................................................................... 159
Figure 16.1. DC-DC Converter Block Diagram....................................................... 160
Figure 16.2. DC-DC Converter Configuration Options........................................... 163
Figure 18.1. Reset Sources. ................................................................................... 171
Figure 18.2. Power-Fail Reset Timing Diagram ..................................................... 172
Figure 18.3. Power-Fail Reset Timing Diagram ..................................................... 173
Figure 19.1. Clocking Sources Block Diagram....................................................... 179
Figure 19.2. 25 MHz External Crystal Example...................................................... 181
Figure 20.1. SmaRTClock Block Diagram.............................................................. 188
Figure 20.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results.......... 197
Figure 21.1. Port I/O Functional Block Diagram..................................................... 205
Figure 21.2. Port I/O Cell Block Diagram ............................................................... 206
Figure 21.3. Crossbar Priority Decoder with No Pins Skipped............................... 210
Figure 21.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 211
Figure 22.1. SMBus Block Diagram ....................................................................... 225
Figure 22.2. Typical SMBus Configuration............................................................. 226
Figure 22.3. SMBus Transaction............................................................................ 227
Figure 22.4. Typical SMBus SCL Generation......................................................... 230
Figure 22.5. Typical Master Write Sequence ......................................................... 239
Figure 22.6. Typical Master Read Sequence......................................................... 240
Figure 22.7. Typical Slave Write Sequence ........................................................... 241
Figure 22.8. Typical Slave Read Sequence........................................................... 242
Figure 23.1. UART0 Block Diagram....................................................................... 247
Figure 23.2. UART0 Baud Rate Logic.................................................................... 248
Figure 23.3. UART Interconnect Diagram.............................................................. 249
Figure 23.4. 8-Bit UART Timing Diagram............................................................... 249
Figure 23.5. 9-Bit UART Timing Diagram............................................................... 250
Figure 23.6. UART Multi-Processor Mode Interconnect Diagram.......................... 251
Figure 24.1. SPI Block Diagram............................................................................. 255
Figure 24.2. Multiple-Master Mode Connection Diagram....................................... 258
Figure 24.3. 3-Wire Single Master and 3-Wire Single Slave Mode
Connection Diagram........................................................................... 258
Figure 24.4. 4-Wire Single Master Mode and 4-Wire Slave Mode
Connection Diagram........................................................................... 258
Figure 24.5. Master Mode Data/Clock Timing........................................................ 260
Figure 24.6. Slave Mode Data/Clock Timing (CKPHA = 0).................................... 261
Figure 24.7. Slave Mode Data/Clock Timing (CKPHA = 1).................................... 261
Figure 24.8. SPI Master Timing (CKPHA = 0)........................................................ 267
Figure 24.9. SPI Master Timing (CKPHA = 1)........................................................ 267
Figure 24.10. SPI Slave Timing (CKPHA = 0)........................................................ 268
Figure 24.11. SPI Slave Timing (CKPHA = 1)........................................................ 268
Figure 25.1. T0 Mode 0 Block Diagram.................................................................. 273
Rev. 1.1 11
C8051F91x-C8051F90x
Figure 25.2. T0 Mode 2 Block Diagram.................................................................. 274
Figure 25.3. T0 Mode 3 Block Diagram.................................................................. 275
Figure 25.4. Timer 2 16-Bit Mode Block Diagram .................................................. 280
Figure 25.5. Timer 2 8-Bit Mode Block Diagram .................................................... 281
Figure 25.6. Timer 2 Capture Mode Block Diagram............................................... 282
Figure 25.7. Timer 3 16-Bit Mode Block Diagram .................................................. 286
Figure 25.8. Timer 3 8-Bit Mode Block Diagram. ................................................... 287
Figure 25.9. Timer 3 Capture Mode Block Diagram............................................... 288
Figure 26.1. PCA Block Diagram............................................................................ 292
Figure 26.2. PCA Counter/Timer Block Diagram.................................................... 294
Figure 26.3. PCA Interrupt Block Diagram............................................................. 295
Figure 26.4. PCA Capture Mode Diagram.............................................................. 297
Figure 26.5. PCA Software Timer Mode Diagram.................................................. 298
Figure 26.6. PCA High-Speed Output Mode Diagram............................................ 299
Figure 26.7. PCA Frequency Output Mode............................................................ 300
Figure 26.8. PCA 8-Bit PWM Mode Diagram......................................................... 301
Figure 26.9. PCA 9, 10 and 11-Bit PWM Mode Diagram....................................... 302
Figure 26.10. PCA 16-Bit PWM Mode.................................................................... 303
Figure 26.11. PCA Module 5 with Watchdog Timer Enabled................................. 304
Figure 27.1. Typical C2 Pin Sharing....................................................................... 315
C8051F91x-C8051F90x
12 Rev. 1.1
List of Tables
2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 2.1. Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 3.1. Pin Definitions for the C8051F91x-C8051F90x . . . . . . . . . . . . . . . . . . . 27
Table 3.2. QFN-24 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 3.3. PCB Land Pattern ................................................................................... 33
Table 3.4. QSOP-24 Package Dimensions ............................................................. 34
Table 3.5. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 4.1. Absolute Maximum Ratings .................................................................... 36
Table 4.2. Global Electrical Characteristics ............................................................. 37
Table 4.3. Port I/O DC Electrical Characteristics ..................................................... 47
Table 4.4. Reset Electrical Characteristics .............................................................. 52
Table 4.5. Power Management Electrical Specifications ......................................... 53
Table 4.6. Flash Electrical Characteristics .............................................................. 53
Table 4.7. Internal Precision Oscillator Electrical Characteristics ........................... 53
Table 4.8. Internal Low-Power Oscillator Electrical Characteristics ........................ 53
Table 4.9. SmaRTClock Characteristics .................................................................. 54
Table 4.10. ADC0 Electrical Characteristics ............................................................ 54
Table 4.11. Temperature Sensor Electrical Characteristics .................................... 55
Table 4.12. Voltage Reference Electrical Characteristics ....................................... 56
Table 4.13. IREF0 Electrical Characteristics ........................................................... 57
Table 4.14. Comparator Electrical Characteristics .................................................. 58
Table 4.15. VREG0 Electrical Characteristics ......................................................... 59
Table 4.16. DC-DC Converter (DC0) Electrical Characteristics .............................. 60
Table 5.1. Representative Conversion Times and Energy Consumption for the SAR
ADC with 1.65 V High-Speed VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 8.1. CIP-51 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 11.1. Special Function Register (SFR) Memory Map (Page 0x0) . . . . . . . . 113
Table 11.2. Special Function Register (SFR) Memory Map (Page 0xF) . . . . . . . . 114
Table 11.3. Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 12.1. Interrupt Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 13.1. Flash Security Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 14.1. Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 15.1. Example 16-bit CRC Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 16.1. IPeak Inductor Current Limit Settings . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 19.1. Recommended XFCN Settings for Crystal Mode . . . . . . . . . . . . . . . . 181
Table 19.2. Recommended XFCN Settings for RC and C modes . . . . . . . . . . . . . 182
Table 20.1. SmaRTClock Internal Registers ......................................................... 189
Table 20.2. SmaRTClock Load Capacitance Settings . . . . . . . . . . . . . . . . . . . . . 196
Table 20.3. SmaRTClock Bias Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 21.1. Port I/O Assignment for Analog Functions . . . . . . . . . . . . . . . . . . . . . 207
Table 21.2. Port I/O Assignment for Digital Functions . . . . . . . . . . . . . . . . . . . . . . 208
Table 21.3. Port I/O Assignment for External Digital Event Capture Functions . . 208
Table 22.1. SMBus Clock Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Rev. 1.1 13
C8051F91x-C8051F90x
Table 22.2. Minimum SDA Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 22.3. Sources for Hardware Changes to SMB0CN . . . . . . . . . . . . . . . . . . . 235
Table 22.4. Hardware Address Recognition Examples (EHACK = 1) . . . . . . . . . . 236
Table 22.5. SMBus Status Decoding With Hardware ACK Generation Disabled
(EHACK = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 22.6. SMBus Status Decoding With Hardware ACK Generation Enabled
(EHACK = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Table 23.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . 254
Table 23.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator . . . . . . . . . . . . . . . . . . . . . 254
Table 24.1. SPI Slave Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Table 25.1. Timer 0 Running Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Table 26.1. PCA Timebase Input Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Table 26.2. PCA0CPM and PCA0PWM Bit Settings for PCA
Capture/Compare Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Table 26.3. Watchdog Timer Timeout Intervals . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
C8051F91x-C8051F90x
14 Rev. 1.1
List of Registers
SFR Definition 5.1. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SFR Definition 5.2. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration . . . . . . . . . . . . . . . . . 71
SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time . . . . . . . . . . . . . . 72
SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time . . . . . . . . . . . . . . . . . . . . 73
SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte . . . . . . . . . . . . . . . . . . . . . . 74
SFR Definition 5.7. ADC0L: ADC0 Data Word Low Byte . . . . . . . . . . . . . . . . . . . . . . . 74
SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte . . . . . . . . . . . . . . . . . . 75
SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte . . . . . . . . . . . . . . . . . . 75
SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte . . . . . . . . . . . . . . . . . . . 76
SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte . . . . . . . . . . . . . . . . . . . . 76
SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select . . . . . . . . . . . . . . . . . . . . 79
SFR Definition 5.13. TOFFH: ADC0 Data Word High Byte . . . . . . . . . . . . . . . . . . . . . 82
SFR Definition 5.14. TOFFL: ADC0 Data Word Low Byte . . . . . . . . . . . . . . . . . . . . . . 82
SFR Definition 5.15. REF0CN: Voltage Reference Control . . . . . . . . . . . . . . . . . . . . . 85
SFR Definition 6.1. IREF0CN: Current Reference Control . . . . . . . . . . . . . . . . . . . . . . 86
SFR Definition 6.2. IREF0CF: Current Reference Configuration . . . . . . . . . . . . . . . . . 87
SFR Definition 7.1. CPT0CN: Comparator 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 91
SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection . . . . . . . . . . . . . . . . . . . 92
SFR Definition 7.3. CPT1CN: Comparator 1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 93
SFR Definition 7.4. CPT1MD: Comparator 1 Mode Selection . . . . . . . . . . . . . . . . . . . 94
SFR Definition 7.5. CPT0MX: Comparator0 Input Channel Select . . . . . . . . . . . . . . . . 96
SFR Definition 7.6. CPT1MX: Comparator1 Input Channel Select . . . . . . . . . . . . . . . . 97
SFR Definition 8.1. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
SFR Definition 8.2. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
SFR Definition 8.3. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SFR Definition 8.4. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SFR Definition 8.5. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SFR Definition 8.6. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
SFR Definition 10.1. EMI0CN: External Memory Interface Control . . . . . . . . . . . . . . 112
SFR Definition 11.1. SFR Page: SFR Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
SFR Definition 12.1. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
SFR Definition 12.2. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SFR Definition 12.3. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . 126
SFR Definition 12.4. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . 127
SFR Definition 12.5. EIE2: Extended Interrupt Enable 2 . . . . . . . . . . . . . . . . . . . . . . 128
SFR Definition 12.6. EIP2: Extended Interrupt Priority 2 . . . . . . . . . . . . . . . . . . . . . . 129
SFR Definition 12.7. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . 131
SFR Definition 13.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . 140
SFR Definition 13.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
SFR Definition 13.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SFR Definition 13.4. FLWR: Flash Write Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SFR Definition 14.1. PMU0CF: Power Management Unit Configuration1,2 . . . . . . . . 149
Rev. 1.1 15
C8051F91x-C8051F90x
SFR Definition 14.2. PMU0MD: Power Management Unit Mode . . . . . . . . . . . . . . . . 150
SFR Definition 14.3. PCON: Power Management Control Register . . . . . . . . . . . . . . 151
SFR Definition 15.1. CRC0CN: CRC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
SFR Definition 15.2. CRC0IN: CRC0 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
SFR Definition 15.3. CRC0DAT: CRC0 Data Output . . . . . . . . . . . . . . . . . . . . . . . . . 156
SFR Definition 15.4. CRC0AUTO: CRC0 Automatic Control . . . . . . . . . . . . . . . . . . . 157
SFR Definition 15.5. CRC0CNT: CRC0 Automatic Flash Sector Count . . . . . . . . . . . 158
SFR Definition 15.6. CRC0FLIP: CRC0 Bit Flip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
SFR Definition 16.1. DC0CN: DC-DC Converter Control . . . . . . . . . . . . . . . . . . . . . . 167
SFR Definition 16.2. DC0CF: DC-DC Converter Configuration . . . . . . . . . . . . . . . . . 168
SFR Definition 16.3. DC0MD: DC-DC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
SFR Definition 17.1. REG0CN: Voltage Regulator Control . . . . . . . . . . . . . . . . . . . . 170
SFR Definition 18.1. VDM0CN: VDD/DC+ Supply Monitor Control . . . . . . . . . . . . . . 175
SFR Definition 18.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
SFR Definition 19.1. CLKSEL: Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
SFR Definition 19.2. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . 186
SFR Definition 19.3. OSCICL: Internal Oscillator Calibration . . . . . . . . . . . . . . . . . . . 186
SFR Definition 19.4. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 187
SFR Definition 20.1. RTC0KEY: SmaRTClock Lock and Key . . . . . . . . . . . . . . . . . . 192
SFR Definition 20.2. RTC0ADR: SmaRTClock Address . . . . . . . . . . . . . . . . . . . . . . 193
SFR Definition 20.3. RTC0DAT: SmaRTClock Data . . . . . . . . . . . . . . . . . . . . . . . . . 193
Internal Register Definition 20.4. RTC0CN: SmaRTClock Control . . . . . . . . . . . . . . . 201
Internal Register Definition 20.5. RTC0XCN: SmaRTClock Oscillator Control . . . . . . 202
Internal Register Definition 20.6. RTC0XCF: SmaRTClock Oscillator Configuration . 203
Internal Register Definition 20.7. RTC0PIN: SmaRTClock Pin Configuration . . . . . . 203
Internal Register Definition 20.8. CAPTUREn: SmaRTClock Timer Capture . . . . . . . 204
Internal Register Definition 20.9. ALARMn: SmaRTClock Alarm Programmed Value 204
SFR Definition 21.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 212
SFR Definition 21.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 213
SFR Definition 21.3. XBR2: Port I/O Crossbar Register 2 . . . . . . . . . . . . . . . . . . . . . 214
SFR Definition 21.4. P0MASK: Port0 Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . 215
SFR Definition 21.5. P0MAT: Port0 Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . 215
SFR Definition 21.6. P1MASK: Port1 Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . 216
SFR Definition 21.7. P1MAT: Port1 Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . 216
SFR Definition 21.8. P0: Port0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
SFR Definition 21.9. P0SKIP: Port0 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
SFR Definition 21.10. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
SFR Definition 21.11. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 219
SFR Definition 21.12. P0DRV: Port0 Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . 220
SFR Definition 21.13. P1: Port1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
SFR Definition 21.14. P1SKIP: Port1 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
SFR Definition 21.15. P1MDIN: Port1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
SFR Definition 21.16. P1MDOUT: Port1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 222
SFR Definition 21.17. P1DRV: Port1 Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . 223
SFR Definition 21.18. P2: Port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
C8051F91x-C8051F90x
16 Rev. 1.1
SFR Definition 21.19. P2MDOUT: Port2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 224
SFR Definition 21.20. P2DRV: Port2 Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . 224
SFR Definition 22.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 232
SFR Definition 22.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
SFR Definition 22.3. SMB0ADR: SMBus Slave Address . . . . . . . . . . . . . . . . . . . . . . 237
SFR Definition 22.4. SMB0ADM: SMBus Slave Address Mask . . . . . . . . . . . . . . . . . 237
SFR Definition 22.5. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
SFR Definition 23.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 252
SFR Definition 23.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 253
SFR Definition 24.1. SPInCFG: SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
SFR Definition 24.2. SPInCN: SPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
SFR Definition 24.3. SPInCKR: SPI Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
SFR Definition 24.4. SPInDAT: SPI Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
SFR Definition 25.1. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
SFR Definition 25.2. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
SFR Definition 25.3. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
SFR Definition 25.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
SFR Definition 25.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
SFR Definition 25.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
SFR Definition 25.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
SFR Definition 25.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
SFR Definition 25.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 284
SFR Definition 25.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 284
SFR Definition 25.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
SFR Definition 25.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
SFR Definition 25.13. TMR3CN: Timer 3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
SFR Definition 25.14. TMR3RLL: Timer 3 Reload Register Low Byte . . . . . . . . . . . . 290
SFR Definition 25.15. TMR3RLH: Timer 3 Reload Register High Byte . . . . . . . . . . . 290
SFR Definition 25.16. TMR3L: Timer 3 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
SFR Definition 25.17. TMR3H Timer 3 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
SFR Definition 26.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
SFR Definition 26.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
SFR Definition 26.3. PCA0PWM: PCA PWM Configuration . . . . . . . . . . . . . . . . . . . . 308
SFR Definition 26.4. PCA0CPMn: PCA Capture/Compare Mode . . . . . . . . . . . . . . . 309
SFR Definition 26.5. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 310
SFR Definition 26.6. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . . 310
SFR Definition 26.7. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 311
SFR Definition 26.8. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 311
C2 Register Definition 27.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
C2 Register Definition 27.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 313
C2 Register Definition 27.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 313
C2 Register Definition 27.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 314
C2 Register Definition 27.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 314
Rev. 1.1 17
C8051F91x-C8051F90x
1. System Overview
C8051F91x-C8051F90x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted
features are listed below. Refer to Table 2.1 for specific product feature selection and part ordering
numbers.
• Single/Dual Battery operation with on-chip dc-dc boost converter.
• High-speed pipelined 8051-compatib le microcontroller core (up to 25 MIPS)
• In-system, full-speed, non-intrusive debug interface (on-chip)
• 10-bit 300 ksps or 12-bit 75 ksps single-ended ADC with analog multiplexer
• 6-Bit Programmable Current Reference. Resolution can be increased with PWM.
• Precision programmable 24.5 MHz internal oscillator with spread spectrum technology.
•16 kB or 8 kB of on-chip Flash memory
• 768 bytes of on-chip RAM
•SMBus/I
2C, Enhanced UART, and two Enhanced SPI serial interfaces implemented in hardware
• Four gener al- pu rp o s e 16 - bit tim er s
• Programmable Counter/Timer Array (PCA) with six capture/comp are modules and Watchdog Timer
function
• On-chip Power-On Reset, VDD Monitor, and Temperature Sensor
• Two On-chip Voltage Comparators with 15 Capacitive Touch Sense inputs.
• 16 Port I/O (5 V tolerant)
With on-chip Power-On Reset, VDD monitor, Watchdog Timer, and clock oscillator, the C8051F91x-
C8051F90x devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can be
reprogrammed even in-circuit, providing non-volatile data stor age, and also allowin g field upgrades of the
8051 firmware. User software has complete control of all peripherals, and may individually shut down any
or all peripherals for power savings.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging
without occupying package pins.
Each device is specified for 0.9 to 1.8 V, 0.9 to 3.6 V or 1.8 to 3.6 V operation over the industrial
temperature range (–40 to +85 °C). The Port I/O an d RST pins are tolerant of input signals up to 5 V. The
C8051F91x-C8051F90x devices are available in 24-pin QFN or QSOP packages. Both package options
are lead-free and RoHS compliant. See Table 2.1 for ordering information. Block diagrams are included in
Figure 1.1 through Figure 1.4.
C8051F91x-C8051F90x
18 Rev. 1.1
Figure 1.1. C8051F912 Block Diagram
Figure 1.2. C8051F911 Block Diagram
Port 0
Drivers
Digital Peripherals
UART
Timers 0,
1, 2, 3
PCA/
WDT
SMBus
Priority
Crossbar
Decoder
P0.0/VREF
P0.1/AGND
P0.2/XTAL1/RTCOUT
P0.3/XTAL2/WAKEOUT
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
Crossbar Control
Port I/O Configuration
CIP-51 8051
Controller Core
16k Byte ISP Flash
Program Memory
256 Byte SRAM
SFR
Bus
512 Byte XRAM
Port 1
Drivers
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
Port 2
Drivers
SPI 0,1
Analog Peripherals
Comparators
+
-
Power Net
VDD/DC+
GND/DC-
XTAL1
SYSCLK
System Clock
Configuration
External
Oscillator
Circuit
Precision
24.5 MHz
Oscillator
Debug /
Programming
Hardware
Power On
Reset/PMU
Reset
C2D
C2CK/RST
Wake
12/10-bit
75/300ksps
ADC
A
M
U
X
Temp
Sensor
External
VREF
Internal
VREF VDD
XTAL2
Low Power
20 MHz
Oscillator
6-bit
IREF
VREF
GND
P1.6
IREF0
CP0, CP0A
P2.7/C2D
+
-
CP1, CP1A
SmaRTClock
Oscillator
XTAL3
XTAL4
DC/DC
Converter
GND
VREG Digital
Power
Analog
Power
CRC
Engine
VBAT
DCEN
Port 0
Drivers
Digital Peripherals
UART
Timers 0,
1, 2, 3
PCA/
WDT
SMBus
Priority
Crossbar
Decoder
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
Crossbar Control
Port I/O Configuration
CIP-51 8051
Controller Core
16k Byte ISP F lash
Program Memory
256 Byte SRAM
SFR
Bus
512 Byte XRAM
Port 1
Drivers
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
Port 2
Drivers
SPI 0,1
Analog Peripherals
Comparators
+
-
Power Net
VDD/DC+
GND/DC-
XTAL1
SYSCLK
System Clock
Configuration
External
Oscillator
Circuit
Precision
24.5 MHz
Oscillator
Debug /
Programming
Hardware
Power On
Reset/PMU
Reset
C2D
C2CK/RST
Wake
10-bit
300ksps
ADC
A
M
U
X
Temp
Sensor
External
VREF
Internal
VREF VDD
XTAL2
Low Power
20 MHz
Oscillator
6-bit
IREF
VREF
GND
P1.6
IREF0
CP0, CP0A
P2.7/C2D
+
-
CP1, CP1A
SmaRTClock
Oscillator
XTAL3
XTAL4
DC/DC
Converter
GND
VREG Digital
Power
Analog
Power
CRC
Engine
VBAT
DCEN
Rev. 1.1 19
C8051F91x-C8051F90x
Figure 1.3. C8051F902 Block Diagram
Figure 1.4. C8051F901 Block Diagram
Port 0
Drivers
Digital Peripherals
UART
Timers 0,
1, 2, 3
PCA/
WDT
SMBus
Priority
Crossbar
Decoder
P0.0/VREF
P0.1/AGND
P0.2/XTAL1/RTCOUT
P0.3/XTAL2/WAKEOUT
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
Crossbar Control
Port I/O Configuration
CIP-51 8051
Contro ller Core
8k Byte ISP Flash
Program Memory
256 Byte SRAM
SFR
Bus
512 Byte XRAM
Port 1
Drivers
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
Port 2
Drivers
SPI 0,1
Analog Peripherals
Comparators
+
-
Power Net
VDD/DC+
GND/DC-
XTAL1
SYSCLK
System Clock
Configuration
External
Oscillator
Circuit
Precision
24.5 MHz
Oscillator
Debug /
Programming
Hardware
Power On
Reset/PMU
Reset
C2D
C2CK/RST
Wake
12/10-bit
75/300ksps
ADC
A
M
U
X
Temp
Sensor
External
VREF
Internal
VREF VDD
XTAL2
Low Power
20 MHz
Oscillator
6-bit
IREF
VREF
GND
P1.6
IREF0
CP0, CP0A
P2.7/C2D
+
-
CP1, CP1A
SmaRTClock
Oscillator
XTAL3
XTAL4
DC/DC
Converter
GND
VREG Digital
Power
Analog
Power
CRC
Engine
VBAT
DCEN
Port 0
Drivers
Digital Peripherals
UART
Timers 0,
1, 2, 3
PCA/
WDT
SMBus
Priority
Crossbar
Decoder
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
Crossbar Control
Port I/O Configuration
CIP-51 8051
Controller Core
8k Byte ISP F lash
Program Memory
256 Byte SRAM
SFR
Bus
512 Byte XRAM
Port 1
Drivers
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
Port 2
Drivers
SPI 0,1
Analog Peripherals
Comparators
+
-
Power Net
VDD/DC+
GND/DC-
XTAL1
SYSCLK
System Clock
Configuration
External
Oscillator
Circuit
Precision
24.5 MHz
Oscillator
Debug /
Programming
Hardware
Power On
Reset/PMU
Reset
C2D
C2CK/RST
Wake
10-bit
300ksps
ADC
A
M
U
X
Temp
Sensor
External
VREF
Internal
VREF VDD
XTAL2
Low Power
20 MHz
Oscillator
6-bit
IREF
VREF
GND
P1.6
IREF0
CP0, CP0A
P2.7/C2D
+
-
CP1, CP1A
SmaRTClock
Oscillator
XTAL3
XTAL4
DC/DC
Converter
GND
VREG Digital
Power
Analog
Power
CRC
Engine
VBAT
DCEN
C8051F91x-C8051F90x
20 Rev. 1.1
1.1. CIP-51™ Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F91x-C8051F90x family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-
51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers
can be used to develop sof tware. The CIP-5 1 core offers all the peripherals included with a st andar d 8052.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the
standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24
system clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking
more than four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS.
1.1.3. Additional Features
The C8051F91x-C8051F90x SoC family includes several key enhancements to the CIP-51 core and
peripherals to improve performance and ease of use in end applications.
The extended interrupt handler provides multiple interrupt sources into the CIP-51 allowing numerous
analog and digital peripherals to interrupt the controller. An interrupt driven system requires less
intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful
when building multi-tasking, real-time systems.
Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset
when power supply voltage drops below safe levels), a Watchdog Timer, a Missing Clock Detector,
SmaRTClock oscillator fail or alarm, a voltage level detection from Comparator0, a forced software reset,
an external reset pin, and an illegal Flash access protection circuit. Each reset source except for the POR,
Reset Input Pin, or Flash error may be disabled by the user in software. The WDT may be permanently
disabled in software after a power-on reset during MC U initialization.
The internal oscillator factory calibrated to 24.5 MHz and is accurate to ±2% over the full temperature and
supply range. The internal oscillator period can also be adjusted by user firmware. An additional 20 MHz
low power oscillator is also available which facilitates low-power operation. An external oscillator drive
circuit is included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to
generate the system clock. If desired, the system clock source may be switched on-the-fly between both
internal and external oscillator circuits. An external oscillator can also be extremely useful in low power
applications, allowing the MCU to run from a slow (power saving) source, while periodically switching to
the fast (up to 25 MHz) internal oscillator as needed.
Clocks to Execute 1 2 2/3 33/4 44/5 5 8
Number of Instructions 26 50 514 73121
Rev. 1.1 21
C8051F91x-C8051F90x
1.2. Port Input/Output
Digital and analog resource s are av ailable thr oug h 16 I/O pins. Port pins are organized as three byte-wide
ports. Port pins P0. 0–P1.6 c an be defined as digital or analog I/O. Digital I/O pins can be assigned to one
of the internal digital resources or used as general purpose I/O (GPIO). Analog I/O pins are used by the
internal analog resources. P2.7 can be used as GPIO and is shared with the C2 Interface Data signal
(C2D). See Section “27. C2 Interface” on page 312 for more details.
The designer has complete control over which digital and analog functions are assigned to individual Port
pins, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a Priority Crossbar Decoder. See Section “21.3. Priority Crossbar Decoder” on
page 209 for more information on the Crossbar.
All Port I/Os are 5 V tolerant when used as digital inputs or open-drain outputs . For Port I/Os configure d as
push-pull outputs, current is sourced from the VDD/DC+ supply. Port I/Os used for analog functions can
operate up to the VDD/DC+ supply voltage. See Section “21.1. Port I/O Modes of Operation” on page 206
for more information on Port I/O operating modes and the electrical specifications chapter for detailed
electrical specifications.
Figure 1.5. Port I/O Functional Block Diagram
XBR0, XBR1,
XBR2, PnSKIP
Registers
Digital
Crossbar
Priority
Decoder
2
P0
I/O
Cells
P0.0
P0.7
8
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
UART
(Internal Digital Signals)
Highest
Priority
Lowest
Priority
SYSCLK
2
SMBus
T0, T1 2
7
PCA
4
CP0
CP1
Outputs
SPI0
SPI1 4
P1
I/O
Cells
P1.0
P1.6
7
(Port La t c he s )
P0 (P0.0-P0.7)
(P1.0-P1.6)
8
7
P1
P2
I/O
Cell
P2 (P2.7)
1
1
PnMDOUT,
PnMDIN Registers
P2.7
To Analog Peripherals
(ADC0, CP0, and CP1 inputs,
VREF, IREF0, AGND)
External Interrupts
EX0 and EX1
C8051F91x-C8051F90x
22 Rev. 1.1
1.3. Serial Ports
The C8051F91x-C8051F90x Family includes an SMBus/I2C interface, a full-duplex UART with enhanced
baud rate configuration, and two Enhanced SPI interfaces. Each of the serial buses is fully implemented in
hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.
1.4. Programmable Counter Array
An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general
purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with six
programmable capture/compare modules. The PCA clock is derived from one of six sources: the system
clock divided by 12, the system clock divided by 4, Timer 0 ov erflows, an External Clock In put (ECI), the
system clock, or the external oscilla tor clock source divided by 8. ‘F912 and ‘F902 devices also support a
SmaRTClock divided by 8 clock source.
Each capture/compare module can be configured to operate in a variety of modes: edge- triggere d ca pture,
software timer, high-speed output, pulse width modulator (8, 9, 10, 11, or 16-bit), or frequency output.
Additionally, Capture/Compare Module 5 offers watchdog timer (WDT) capabilities. Following a system
reset, Module 5 is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and
External Clock Input may be routed to Port I/O via the Digital Crossbar.
Figure 1.6. PCA Block Diagram
Capture/C ompare
Module 1
Capture/Com pare
Modu le 0 Capture/Com pare
Module 2
CEX1
ECI
Crossbar
CEX2
CEX0
P o r t I/O
16-Bit Counter/Timer
PCA
CLOCK
MUX
SYSCLK/12
SYSCLK/4
Tim er 0 Overflow
E CI
SYSCLK
External Clock/8
Capture/Com pare
Module 4
Capture/C ompare
Module 3 Capture/Com pare
Module 5 / W D T
CEX4
CEX5
CEX3
SmaRTClock/8*
*Only available on ‘F912 and ‘F902 devices.
Rev. 1.1 23
C8051F91x-C8051F90x
1.5. SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low
Power Burst Mode
C8051F91x-C8051F90x devices have a 300 ksps, 10-bit or 75 ksps 12-bit successive-approximation-
register (SAR) ADC with integrated track- and- hold and programmable window detector. ADC0 also has an
autonomous low power Burst Mode which can automatically enable ADC0, capture and accumulate
samples, then place ADC0 in a low power shutdown mode without CPU intervention. It also has a 16-bit
accumulato r that can automatically av erage the ADC results, providing an effective 11, 12, or 13 bit ADC
result without any additional CPU intervention.
The ADC can sample the voltage at any of the GPIO pins (with the exception of P2.7) and has an on-chip
attenuator that allows it to measure voltages up to twice the voltage reference. Additional ADC inputs
include an on-chip temperature sensor, the VDD/DC+ supply voltage, the VBAT supply voltage, and the
internal digital supply voltage.
Figure 1.7. ADC0 Functional Block Diagram
ADC0CF
AMP0GN
AD0TM
AD08BE
AD0SC0
AD0SC1
AD0SC2
AD0SC3
AD0SC4
10/12-Bit
SAR
ADC
REF
SYSCLK
ADC0H
32
ADC0CN
AD0CM0
AD0CM1
AD0CM2
AD0WINT
AD0BUSY
AD0INT
BURSTEN
AD0EN
Timer 0 O verflow
Timer 2 O verflow
Timer 3 O verflow
Start
Conversion
000 AD 0BU SY (W)
VDD
ADC0LTH
AD0WINT
001
010
011
100 CNVSTR Input
W ind ow
Compare
Logic
ADC0LTL
ADC0GTH ADC0GTL
ADC0L
AIN+
From
AMUX0
Burst M ode Logic
ADC0TK
ADC0PWR
16-Bit Accumulator
C8051F91x-C8051F90x
24 Rev. 1.1
Figure 1.8. ADC0 Multiplexer Block Diagram
1.6. Programmable Current Reference (IREF0)
C8051F91x-C8051F90x devices include an on -chip programmable current reference (source or sink) with
two output current settings: low power mode and high current mode. The maximum current output in low
power mode is 63 µA (1 µA steps) and the maximum current output in high current mode is 504 µA (8 µA
steps).
1.7. Comparators
C8051F91x-C8051F90x devices include two on-chip programmable voltage comparators: Comparator 0
(CPT0) which is shown in Figure 1.9; Comparator 1 (CPT1) which is shown in Figure 1.10. The two
comparators operate identically but may differ in their ability to be used as reset or wake-up sources. See
Section “18. Reset Sources” on page 171 and the Section “14. Power Management” on page 143 for
details on reset sources and low power mode wake-up sources, respec tively.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous CP0A signal is available even when the
system clock is not active. This allows the Comparator to operate and generate an output when the device
is in some low power modes.
The compara tor inputs ma y be connected to Por t I/O pins or to other interna l signals. Port pins may also be
used to directly sense capacitive touch switches.
ADC0
Temp
Sensor
AMUX
VBAT
ADC0MX
AD0MX4
AD0MX3
AD0MX2
AD0MX1
AM0MX0
AIN+
P0.0
P1.6
Digit a l Supply
VDD/DC+
Programmable
Attenuator
Gain = 0.5 or 1
Rev. 1.1 25
C8051F91x-C8051F90x
Figure 1.9. Comparator 0 Functional Block Diagram
Figure 1.10. Comparator 1 Functional Block Diagram
VDD
CPT0CN
Reset
Decision
Tree
+
- Crossbar
Interrupt
Logic
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CP0 +
Px.x
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0 CPT0MD
CP0RIE
CP0FIE
CP0MD1
CP0MD0
CP0
CP0A
CP0
Rising-edge CP0
Falling-edge
CP0
Interrupt
Px.x
Px.x
Px.x
CP0 - (ASYNCHRONOUS)
Analog Inp ut Multiplexer
VDD
CPT0CN
Reset
Decision
Tree
+
- Crossbar
Interrupt
Logic
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CP1 +
Px.x
CP1EN
CP1OUT
CP1RIF
CP1FIF
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0 CPT0MD
CP1RIE
CP1FIE
CP1MD1
CP1MD0
CP1
CP1A
CP1
Rising-edge CP1
Falling-edge
CP1
Interrupt
Px.x
Px.x
Px.x
CP1 - (ASYNCHRONOUS)
Analog Input Multiplexer
C8051F91x-C8051F90x
26 Rev. 1.1
2. Ordering Information
*The 'F9xx Plus features are a set of enhancements that allow greater power efficiency and increased
functionality. They include 12-bit ADC mode, PWM Enhanced IREF, ultra-low power SmaRTClock LFO,
VBAT input voltage from 0.9 to 3.6 V, and VBAT battery low indicator. The 'F9xx Plus features are
described in detail in "AN431: F93x-F90x Software Porting Guide ."
Table 2.1. Product Selection Guide
Ordering Part Number
MIPS (Peak)
Flash Memory (kB)
RAM (bytes)
SmaRTClock Real Time Clock
SMBus/I2C
UART
Enhanced SPI
Timers (16-bit)
Programmable Counter Array
Digital Port I/Os
10-bit 300ksp s ADC
Programmabl e Current Reference
Internal Voltag e Re fe re nc e
Temperat ur e Sensor
Analog Comparators
Lead-free (RoHS Compliant)
C8051F9xx Plus Features*
Package
C8051F912-GM 25 16 768
1124
16
2
QFN-24
C8051F912-GU 25 16 768
1124
16
2
QSOP-24
C8051F912-GD 25 16 768
1124
16
2
Tested Die
C8051F911-GM 25 16 768
1124
16
2
QFN-24
C8051F911-GU 25 16 768
1124
16
2
QSOP-24
C8051F911-GD 25 16 768
1124
16
2
Tested Die
C8051F902-GM 25 8 768
1124
16
2
QFN-24
C8051F902-GU 25 8 768
1124
16
2
QSOP-24
C8051F902-GD 25 8 768
1124
16
2
Tested Die
C8051F901-GM 25 8 768
1124
16
2
QFN-24
C8051F901-GU 25 8 768
1124
16
2
QSOP-24
C8051F901-GD 25 8 768
1124
16
2
Tested Die
Rev. 1.1 27
C8051F91x-C8051F90x
3. Pinout and Package Definitions
Table 3.1. Pin Definitions for the C8051F91x-C8051F90x
Name
Pin Numbers
Type Description
‘F912-GM
‘F902-GM
‘F911-GM
‘F901-GM
‘F912-GU
‘F902-GU
‘F911-GU
‘F901-GU
VBAT 5 8 P In Battery Supply Voltage.
C8051F911/01 devices:
Must be 0.9 to 1.8 V in single-cell battery mode and 1.8 to 3.6 V in
dual-cell battery mode.
C8051F912/02 devices:
Must be 0.9 to 3.6 V in single-cell battery mode and 1.8 to 3.6 V in
dual-cell battery mode.
VDD /
DC+
3 6 P In
P Out
Power Supply V oltage. Must be 1.8 to 3.6 V. This supply volt age is
not required in low power sleep mode. This voltage must always
be > VBAT.
Positive output of the dc -dc converter. In single-cell battery mode,
a 1uF ceramic capacitor is required between DC+ and DC–. This
pin can supply power to external devices when operating in single-
cell battery mode.
DC– /
GND
1 4 P In
G
DC-DC converter return current path. In single-cell battery mode,
this pin is typically not connected to ground.
In dual-cell battery mode, this pin must be connected directly to
ground.
GND 2 5 G Required Ground.
DCEN 4 7 P In
G
DC-DC Enable Pin. In single-cell battery mode, this pin must be
connected to VBAT through a 0.68 µH inductor.
In dual-cell battery mode, this pin must be connected directly to
ground.
RST/
C2CK
6 9 D I/O
D I/O
Device Reset. Open-drain out put of internal POR or VDD monitor.
An external source can initiate a system reset by driving this pin
low for at least 15 µs. A 1 k to 5 k pullup to VDD is recom-
mended. See Section “18. Reset Sources” on page 171 Section
for a complete description.
Clock signal for the C2 Debug Interface.
P2.7/
C2D
710 D I/O
D I/O
Port 2.7. This pin can only be used as GPIO. The Crossbar cannot
route signals to this pin and it cannot be configured as an analog
input. See Port I/O Section for a complete description.
Bi-directional data signal for the C2 Debug Interface.
*Note: Available only on the C8051F912/02.
C8051F91x-C8051F90x
28 Rev. 1.1
XTAL3 912 A In SmaRTClock Oscillator Crystal Input.
See Section 20 for a complete description.
XTAL4 811 A Out SmaRTClock Oscillator Crystal Output.
See Section 20 for a complete description.
P0.0
VREF
24 3D I/O or
A In
A In
A Out
Port 0.0. See Port I/O Section for a complete description.
External VREF Input.
Internal VREF Output. External VREF decoupling capacitors are
recommended. See Section “5.9. Voltage and Ground Reference
Options” on page 83.
P0.1
AGND
23 2D I/O or
A In
G
Port 0.1. See Port I/O Section for a complete description.
Optional Analog Ground. See Section “5.9. Voltage and Ground
Reference Options” on page 83.
P0.2
XTAL1
RTCOUT*
22 1D I/O or
A In
A In
Port 0.2. See Port I/O Section for a complete description.
External Clock Input. This pin is the external oscillator return for a
crystal or resonator. See Section “19. Clocking Sources” on
page 179.
Buffered SmaRT Clock oscillator output.
P0.3
XTAL2
WAKEOUT*
21 24 D I/O or
A In
A Out
D In
A In
Port 0.3. See Section “21. Port Input/Output” on page 205 for a
complete description.
External Clock Output. This pin is the excit ation driver for an exter-
nal crystal or resonator.
External Clock Input. This pin is the external clock input in external
CMOS clock mode.
External Clock Input. This pin is the external clock input in capaci-
tor or RC oscillator configurations.
See Section “19. Clocking Sources” on page 179 for complete
details.
Wake-up request signal to wake up external devices (e.g. an
external DC-DC converter).
P0.4
TX
20 23 D I/O or
A In
D Out
Port 0.4. See Section “21. Port Input/Output” on page 205 for a
complete description.
UART TX Pin. See Section “21. Port Input/Output” on page 205.
P0.5
RX
19 22 D I/O or
A In
D In
Port 0.5. See Section “21. Port Input/Output” on page 205 for a
complete description.
UART RX Pin. See Section “21. Port Input/Output” on page 205.
Table 3.1. Pin Definitions for the C8051F91x-C8051F90x (Continued)
Name
Pin Numbers
Type Description
‘F912-GM
‘F902-GM
‘F911-GM
‘F901-GM
‘F912-GU
‘F902-GU
‘F911-GU
‘F901-GU
*Note: Available only on the C8051F912/02.
Rev. 1.1 29
C8051F91x-C8051F90x
P0.6
CNVSTR
18 21 D I/O or
A In
D In
Port 0.6. See Section “21. Port Input/Output” on page 205 for a
complete description.
External Convert Start Input for ADC0. See Section “5.7. ADC0
Analog Multiplexer” on page 78 for a complete description.
P0.7
IREF0
17 20 D I/O or
A In
A Out
Port 0.7. See Section “21. Port Input/Output” on page 205 for a
complete description.
IREF0 Output. See IREF Section for co mplete description.
P1.0 16 19 D I/O or
A In Port 1.0. See Section “21. Port Input/Output” on page 205 for a
complete description. May also be used as SCK for SPI1.
P1.1 15 18 D I/O or
A In Port 1.1. See Section “21. Port Input/Output” on page 205 for a
complete description.
May also be used as MISO for SPI1.
P1.2 14 17 D I/O or
A In Port 1.2. See Section “21. Port Input/Output” on page 205 for a
complete description.
May also be used as MOSI for SPI1.
P1.3 13 16 D I/O or
A In Port 1.3. See Section “21. Port Input/Output” on page 205 for a
complete description.
May also be used as NSS for SPI1.
P1.4 12 15 D I/O or
A In Port 1.4. See Section “21. Port Input/Output” on page 205 for a
complete description.
P1.5 11 14 D I/O or
A In Port 1.5. See Section “21. Port Input/Output” on page 205 for a
complete description.
P1.6 10 13 D I/O or
A In Port 1.6. See Section “21. Port Input/Output” on page 205 for a
complete description.
Table 3.1. Pin Definitions for the C8051F91x-C8051F90x (Continued)
Name
Pin Numbers
Type Description
‘F912-GM
‘F902-GM
‘F911-GM
‘F901-GM
‘F912-GU
‘F902-GU
‘F911-GU
‘F901-GU
*Note: Available only on the C8051F912/02.
C8051F91x-C8051F90x
30 Rev. 1.1
Figure 3.1. QFN-24 Pinout Diagram (Top View)
P2.7/C2D
XTAL4
XTAL3
P1.6
P1.5
P1.4
10
11
12
8
7
9
GND/DC–
GND
VDD/DC+
DCEN
VBAT
RST/C2CK
4
5
6
2
1
3
P0.5/RX
P0.4/TX
P0.3/XTAL2/WAKEOUT*
P0.2/XTAL1/RTCOUT*
P0.1/AGND
P0.0/VREF
22
23
24
20
19
21
C8051F912/02-GM
C8051F911/01-GM
Top View
G ND (Optional Connection)
P1.3
P1.2
P1.1
P1.0
P0.7/IREF0
P0.6/CNVSTR
15
14
13
17
18
16
*Note: Signal only available on 'F9 12 and 'F902 devices.
Rev. 1.1 31
C8051F91x-C8051F90x
Figure 3.2. QSOP-24 Pinout Diagram F912 (Top View)
P0.2/XTAL1/RTCOUT* P0.3/XTAL2/WAKEOUT*
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
P1.0
P1.1
P1.2
P1.3
C8051F912/02 – GU
C8051F911/01 – GU
P0.1/AGND
P0.0/VREF
GND
VDD/DC+
DCEN
VBAT
P2.7/C2D P1.4
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
XTAL4
XTAL3
11
12
P1.5
P1.6
14
13
GND/DC-
RST/C2CK
*N ote: Signal only available on 'F 912 and 'F 902 devices.
C8051F91x-C8051F90x
32 Rev. 1.1
Figure 3.3. QFN-24 Package Drawing
Table 3.2. QFN-24 Package Dimensions
Dimension Min Typ Max Dimension Min Typ Max
A0.70 0.75 0.80 L0.30 0.40 0.50
A1 0.00 0.02 0.05 L1 0.00 —0.15
b0.18 0.25 0.30 aaa — — 0.15
D4.00 BSC bbb — — 0.10
D2 2.55 2.70 2.80 ddd — — 0.05
e0.50 BSC eee — — 0.08
E4.00 BSC Z — 0.24 —
E2 2.55 2.70 2.80 Y — 0.18 —
Notes:
1. All dimensions shown are in millimeters (mm) unless oth erwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, variati on WGGD except
for custom features D2, E2, Z, Y, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
Rev. 1.1 33
C8051F91x-C8051F90x
Figure 3.4. Typical QFN-24 Landing Diagram
Table 3.3. PCB Land Pattern
Dimension Min Max Dimension Min Max
C1 3.90 4.00 X1 0.20 0.30
C2 3.90 4.00 X2 2.70 2.80
E0.50 BSC Y1 0.65 0.75
Y2.70 2.80
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is base d on the IPC-7351 guidelines.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perime ter pads.
4. A 2 x 2 array of 1.0 x 1.0 mm square openings on 1.30 mm pitch should be used for the
center ground pad.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JED EC/IPC J-STD-020 specification for
Small Body Components.
C8051F91x-C8051F90x
34 Rev. 1.1
Figure 3.5. QSOP-24 Package Diagram
Table 3.4. QSOP-24 Package Dimensions
Dimension Min Nom Max Dimension Min Nom Max
A — — 1.75 e 0.635 BSC
A1 0.10 — 0.25 L 0.40 — 1.27
b 0.20 — 0.30 0º — 8º
c 0.10 — 0.25 aaa 0.20
D 8.65 BSC bbb 0.18
E 6 .00 BSC ccc 0.10
E1 3.90 BSC ddd 0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-137, variation AE.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.1 35
C8051F91x-C8051F90x
Figure 3.6. QSOP-24 Landing Diagram
Table 3.5. PCB Land Pattern
Dimension MIN MAX
C5.205.30
E 0.635 BSC
X0.300.40
Y1.501.60
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern is based on the IPC-7351 guidelines.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NMSD). Clearance between the solder mask and
the metal pad is to be 60 m minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to
assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimete r pads.
Card Assembly
1. A No-Clean, Type 3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
C8051F91x-C8051F90x
36 Rev. 1.1
4. Electrical Characteristics
Throughout the Electrical Characteristics chapter, “VDD ” refers to the VDD/DC+ Supply Voltage.
Blue indicates a feature only available on ‘F912 and ‘F902 devices.
4.1. Absolute Maximum Specifications
Table 4.1. Absolute Maximum Ratings
Parameter Conditions Min Typ Max Units
Ambient temperature under bias –55 — 125 °C
Storage Temperature –65 — 150 °C
Voltage on any Port I/O Pin or
RST with respect to GND VDD > 2.2 V
VDD < 2.2 V –0.3
–0.3 —
—5.8
VDD + 3.6 V
Voltage on VBAT with respect to
GND One-Cell Mode (F912/02
One-Cell Mode (F911/01)
Two-Cell Mode
–0.3
–0.3
–0.3
—
—
—
4.0
2.0
4.0
V
V oltage on VDD/DC+ with respect
to GND –0.3 — 4.0 V
Maximum total current through
VBAT, DCEN, VDD/DC+ or GND ——500mA
Maximum current through RST or
any Port pin ——100mA
Maximum tot al current through all
Port pins ——200mA
DC-DC Converter Output Power — — 110 mW
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Rev. 1.1 37
C8051F91x-C8051F90x
4.2. Electrical Characteristics
Table 4.2. Global Electrical Characteristics
–40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the
‘F9xx" for details on how to achieve the supply current specifications listed in this table.
Parameter Conditions Min Typ Max Units
Battery Supply Voltage (VBAT) One-Cell Mode (F912/02)
One-Cell Mode (F911/01)
Two-Cell Mode
0.9
0.9
1.8
1.2
1.2
2.4
3.6
1.8
3.6
V
Supply Voltage (VDD/DC+) One-Cell Mode
Two-Cell Mode 1.8
1.8 1.9
2.4 3.6
3.6 V
Minimum RAM Data
Retention Voltage1VDD (not in Sleep Mode)
VBAT (in Sleep Mode) —
—1.4
0.3 —
0.5 V
SYSCLK (System Clock)20—25MHz
TSYSH (SYSCLK High T ime) 18 — — ns
TSYSL (SYSCLK Low T ime) 18 — — ns
Specified Operating
Temperature Range –40 — +85 °C
C8051F91x-C8051F90x
38 Rev. 1.1
Digital Supply Current—CPU Active (Normal Mo de, fetching instructions from Flash)
IDD 3, 4, 5, 6 VDD = 1.8–3.6 V, F = 24.5 MHz
(includes precision oscillator current) —4.05.0 mA
VDD = 1.8–3.6 V, F = 20 MHz
(includes low power oscillator current) —3.4— mA
VDD = 1.8 V, F = 1 MHz
VDD = 3.6 V, F = 1 MHz
(includes external oscillator/GPIO current)
—
—265
305 —
—µA
µA
VDD = 1.8–3.6 V, F = 32.768 kHz
(includes SmaRTClock oscillator current) —84— µA
IDD Frequency Sensitivity3, 5, 6 VDD = 1.8–3.6 V, T = 25 °C, F < 14 MHz
(Flash oneshot active, see Section 13.6) —191—µA/MHz
VDD = 1.8–3.6 V, T = 25 °C, F > 14 MHz
(Flash oneshot bypassed, see Section 13.6) —102—µA/MHz
Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash)
IDD4, 6, 7 VDD = 1.8–3.6 V, F = 24.5 MHz
(includes precision oscillator current) —2.13.0 mA
VDD = 1.8–3.6 V, F = 20 MHz
(includes low power oscillator current) —1.6— mA
VDD = 1.8 V, F = 1 MHz
VDD = 3.6 V, F = 1 MHz
(includes external oscillator/GPIO current)
—
—160
185 —
—µA
µA
VDD = 1.8–3.6 V, F = 32.768 kHz (includes
SmaRTClock oscillator current) —82— µA
IDD Frequency Sensitivity1,6,7 VDD = 1.8–3.6 V, T = 25 °C — 79 — µA/MHz
Table 4.2. Global Electrical Characteristics (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Op timizing Low Power Operation of the
‘F9xx" for details on how to achieve the supply current specifications listed in this table.
Parameter Conditions Min Typ Max Units
Rev. 1.1 39
C8051F91x-C8051F90x
Digital Supply Current—Suspend and Sleep Mode
Digital Supply Current6
(Suspend Mode) VDD = 1.8–3.6 V, two-cell mode — 77 — µA
Digital Supply Current
(Sleep Mode, SmaRTClock run-
ning, 32.768 kHz crystal)
1.8 V, T = 25 °C
3.0 V, T = 25 °C
3.6 V, T = 25 °C
1.8 V, T = 85 °C
3.0 V, T = 85 °C
3.6 V, T = 85 °C
(includes SmaRTClock oscillator and VBAT
Supply Monitor)
—
—
—
—
—
—
0.60
0.75
0.85
1.30
1.60
1.90
—
—
—
—
—
—
µA
Digital Supply Current8
(Sleep Mode, SmaRTClock run-
ning, internal LFO)
1.8 V, T = 25 °C
(includes SmaRTClock oscillator and VBAT
Supply Monitor)
—0.3— µA
Digital Supply Current
(Sleep Mode) 1.8 V, T = 25 °C
3.0 V, T = 25 °C
3.6 V, T = 25 °C
1.8 V, T = 85 °C
3.0 V, T = 85 °C
3.6 V, T = 85 °C
(includes VBAT supply monitor)
—
—
—
—
—
—
0.05
0.08
0.12
0.75
0.90
1.20
—
—
—
—
—
—
µA
Digital Supply Current (Sleep
Mode, VBAT Supply Monitor
Disabled)9
1.8 V, T = 25 °C — 0.01 — µA
Table 4.2. Global Electrical Characteristics (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Op timizing Low Power Operation of the
‘F9xx" for details on how to achieve the supply current specifications listed in this table.
Parameter Conditions Min Typ Max Units
C8051F91x-C8051F90x
40 Rev. 1.1
Notes:
1. Based on device characterization data; Not production tested.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Digital Supply Current depends upon the p articular code being executed. The values in this table are obtained
with the CPU executing an “sjmp $” loop, which is the compiled form of a while(1) loop in C. One iteration
requires 3 CPU clock cycles, and the Flash memory is read on each cycle. The supply current will vary slightly
based on the physical location of the sjmp instructi on and the number of Flash address lines that toggle as a
result. In the worst case, current can increase by up to 30% if the sjmp loop straddles a 64-byte Flash address
boundary (e.g., 0x007F to 0x0080). Real-world code with larger loops and longer line ar sequences will have
few transitions across the 64-byte address boundaries.
4. Includes oscillator and regulator supply current.
5. IDD can be estimated for frequencies <14 MHz by simply multiplying the frequency of interest by the
frequency sensitivity number for that range, then adding an offset of 90 µA. When using these numbers to
estimate IDD for >14 MHz, the estimate should be the current at 25 MHz minus the difference in current
indicated by the frequency sensitivity number. For example: VDD = 3.0 V; F = 20 MHz, IDD = 4 mA –
(25 MHz – 20 MHz) x 0.102 mA/MHz = 3.5 mA assuming the same oscillator setting.
6. The supply current specifications in Tabl e 4.2 ar e for two cell mode. The VBAT current in one-cell mode can
be estimated using the following equation:
The VBAT Voltage is the voltage at the VBAT pin, typically 0.9 to 1.8 V.
The Supply Current (two-cell mode) is the data sheet specification for supply current.
The Supply Voltage is the volt age at the VDD/DC+ pin, typically 1.8 to 3.3 V (default = 1.9 V).
The DC-DC Converter Efficiency can be estimated using Figure 4.3–Figure 4.5.
7. Idle IDD can be estimated by taking the current at 25 MHz minus the difference in current indicated by the
frequency sensitivity number . For example: VDD = 3.0 V; F = 5 MHz, Idle IDD = 2.1 mA – (25 MHz –
5 MHz) x 0.079 mA/MHz = 0.52 mA.
8. Internal LFO on ly available on ‘F912 and ‘F902 devices.
9. Ability to disable VBAT supply monitor only available on ‘F912 and ‘F902 devices .
Table 4.2. Global Electrical Characteristics (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Op timizing Low Power Operation of the
‘F9xx" for details on how to achieve the supply current specifications listed in this table.
Parameter Conditions Min Typ Max Units
VBAT Current (one-cell mode) Supply Voltage Supply Current (two-cell mode)
DC-DC Converter Efficiency VBAT Voltage
-----------------------------------------------------------------------------------------------------------------------------------
=
Rev. 1.1 41
C8051F91x-C8051F90x
Figure 4.1. Active Mode Current (External CMOS Clock)
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
3100
3200
3300
3400
3500
3600
3700
3800
3900
4000
4100
4200
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Frequency (MHz)
Supply Current (uA)
F < 14 MHz
Oneshot Enabled
F > 14 MHz
Oneshot Bypassed
< 160 uA/MHz
185 uA/MHz
215 uA/MHz
300 uA/MHz
200 uA/MHz
C8051F91x-C8051F90x
42 Rev. 1.1
Figure 4.2. Idle Mode Current (External CMOS Clock)
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
3100
3200
3300
3400
3500
3600
3700
3800
3900
4000
4100
4200
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Frequency (MHz)
Supply Current (uA)
Rev. 1.1 43
C8051F91x-C8051F90x
Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 2 V)
Load Current (mA)
Efficiency (%)
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
6:6(/ 6:6(/
X+,QGXFWRUSDFNDJH(65 2KPV
9'''& 90LQLPXP3XOVH:LGWK QV3XOVH6NLSSLQJ'LVDEOHG
1RWH(IILFLHQF\DWKLJKFXUUHQWVPD\EHLPSURYHGE\FKRRVLQJDQ
LQGXFWRUZLWKDORZHU(65
C8051F91x-C8051F90x
44 Rev. 1.1
Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 3 V)
Load current (mA)
Efficiency (%)
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
6:6(/ 6:6(/
X+,QGXFWRUSDFNDJH(65 2KPV
9'''& 90LQLPXP3XOVH:LGWK QV
3XOVH6NLSSLQJ'LVDEOHG
1RWH(IILFLHQF\DWKLJKFXUUHQWVPD\EHLPSURYHGE\
FKRRVLQJDQLQGXFWRUZLWKDORZHU(65
Rev. 1.1 45
C8051F91x-C8051F90x
Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC+ = 2 V)
Load current (mA)
Efficiency (%)
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
X+,QGXFWRUSDFNDJH(65 2KPV
6:6(/ 9'''& 90LQLPXP3XOVH:LGWK QV
C8051F91x-C8051F90x
46 Rev. 1.1
Figure 4.6. Typical One-Cell Suspend Mode Current
9%$79
9%$7&XUUHQWX$
0LQ3XOVH:LGWKQV
0LQ3XOVH:LGWKQV
0LQ3XOVH:LGWKQV
0LQ3XOVH:LGWKQV
X+,QGXFWRUSDFNDJH(65 2KPV
6:6(/ 9'''& 9/RDG&XUUHQW X$
Rev. 1.1 47
C8051F91x-C8051F90x
Table 4.3. Port I/O DC Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameters Conditions Min Typ Max Units
Output High Voltage High Drive Strength, PnDRV.n = 1
IOH = –3 mA, Port I/O push-pull
IOH = –10 µA, Port I/O push-pull
IOH = –10 mA, Port I/O push-pull
Low Drive Strength, PnDRV.n = 0
IOH = –1 mA, Port I/O push-pull
IOH = –10 µA, Port I/O push-pull
IOH = –3 mA, Port I/O push-pull
VDD – 0.7
VDD – 0.1
VDD – 0.7
VDD – 0.1
—
—
—
See Chart
—
—
See Chart
—
—
—
—
—
V
Output Low Voltage High Drive Strength, PnDRV.n = 1
IOL = 8.5 mA
IOL = 10 µA
IOL = 25 mA
Low Drive Strength, PnDRV.n = 0
IOL = 1.4 mA
IOL = 10 µA
IOL = 4 mA
—
—
—
—
—
—
—
—
See Chart
—
—
See Chart
0.6
0.1
—
0.6
0.1
—
V
Input High Vo ltage VDD = 2.0 to 3.6 V VDD – 0.6 ——V
VDD = 0.9 to 2.0 V 0.7 x VDD — — V
Input Low Vo ltage VDD = 2.0 to 3.6 V — — 0.6 V
VDD = 0.9 to 2.0 V — — 0.3 x VDD V
Input Leakage
Current
Weak Pullup Off
Weak Pullup On, VIN = 0 V, VDD = 1.8 V
Weak Pullup On, Vin = 0 V, VDD = 3.6 V
—
—
—
—
4
20
±1
—
35 µA
C8051F91x-C8051F90x
48 Rev. 1.1
Figure 4.7. Typical VOH Curves, 1.8–3.6 V
T ypical VOH ( H igh Dr iv e M ode)
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
3.3
3.6
0 5 10 15 20 25 30 35 40 45 50
Load Cu rr ent ( mA)
Voltage
VDD = 3. 6V
VDD = 3. 0V
VDD = 2. 4V
VDD = 1. 8V
T ypic al VO H (Low Driv e Mode)
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
3.3
3.6
0123456789101112131415
Load Cu rr ent ( mA)
Voltage
VDD = 3.6V
VDD = 3.0V
VDD = 2.4V
VDD = 1.8V
Rev. 1.1 49
C8051F91x-C8051F90x
Figure 4.8. Typical VOH Curves, 0.9–1.8 V
Ty p ic a l VO H ( High Drive Mode )
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
0123456789101112
Load Curr ent (m A)
Voltage
VDD = 1. 8V
VDD = 1. 5V
VDD = 1. 2V
VDD = 0. 9V
T ypical VO H (Low Driv e M ode)
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
0123
Load Cu r r ent ( m A)
Voltage
VDD = 1. 8V
VDD = 1. 5V
VDD = 1. 2V
VDD = 0. 9V
C8051F91x-C8051F90x
50 Rev. 1.1
Figure 4.9. Typical VOL Curves, 1.8–3.6 V
T ypical VO L ( High Drive Mode)
0
0.3
0.6
0.9
1.2
1.5
1.8
-80 -70 -60 -50 -40 -30 -20 -10 0
Load Cu r r ent ( m A)
Voltage
VDD = 3.6V
VDD = 3.0V
VDD = 2.4V
VDD = 1.8V
T ypic al VOL (Low Dr ive Mode)
0
0.3
0.6
0.9
1.2
1.5
1.8
-10-9-8-7-6-5-4-3-2-10
Load Cu r r ent ( m A)
Voltage
VDD = 3. 6V
VDD = 3. 0V
VDD = 2. 4V
VDD = 1. 8V
Rev. 1.1 51
C8051F91x-C8051F90x
Figure 4.10. Typical VOL Curves, 0.9–1.8 V
T ypic al VO L ( High Drive Mode)
0
0.1
0.2
0.3
0.4
0.5
-5 -4 -3 -2 -1 0
Load Cu r r ent ( m A)
Voltage
VDD = 1. 8V
VDD = 1. 5V
VDD = 1. 2V
VDD = 0. 9V
T ypical VO L ( Low Driv e M ode)
0
0.1
0.2
0.3
0.4
0.5
-3 -2 -1 0
Load Cu r r ent ( m A)
Voltage
VDD = 1. 8V
VDD = 1. 5V
VDD = 1. 2V
VDD = 0. 9V
C8051F91x-C8051F90x
52 Rev. 1.1
Table 4.4. Reset Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
RST Output Low Voltage IOL = 1.4 mA, ——0.6V
RST Input High Voltage VDD = 2.0 to 3.6 V VDD – 0.6 —— V
VDD = 0.9 to 2.0 V 0.7 x VDD —— V
RST Input Low Voltage VDD = 2.0 to 3.6 V ——0.6V
VDD = 0.9 to 2.0 V ——
0.3 x VDD V
RST Input Pullup Current RST = 0.0 V, VDD = 1.8 V
RST = 0.0 V, VDD = 3.6 V —
—4
20 —
35 µA
VDD/DC+ Monitor
Threshold (VRST)
Early Warning
Reset Trigger
(all power modes ex ce pt Slee p )
1.8
1.7 1.85
1.75 1.9
1.8 V
VBAT Ramp Time for
Power On VBAT Ramp from 0–0.9 V —— 3 ms
VBAT Monitor Threshold
(VPOR)
Initial Power-On (VBAT Rising)
Early Warning
Brownout Condition (VBAT Falling)
Recovery from Brownout (VBAT Rising)
—
0.9
0.7
—
0.75
1.0
0.8
0.95
—
1.1
0.9
—
V
Missing Clock Detector
Timeout T ime from last system clock rising edge
to reset initiation 100 525 1000 µs
Minimum System Clock w/
Missing Clock Detector
Enabled
System clock frequency which triggers
a missing clock detector timeout — 2 10 kHz
Reset Time Delay Delay between release of any reset
source and code
execution at location 0x0000 —10—µs
Minimum RST Low T ime to
Generate a System Reset 15 — — µs
VDD Monitor Turn-on Time — 300 — ns
VDD Monitor Supply
Current —10—µA
*Note: Blue indicates a feature only available on ‘F912 and ‘F902 devices.
Rev. 1.1 53
C8051F91x-C8051F90x
Table 4.5. Power Management Electrical Specifications
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Idle Mode Wake-up Time 2 — 3 SYSCLKs
Suspend Mode Wake-up Time Low power oscillator —400 — ns
Precision oscillator —400 —ns
Sleep Mode Wake-up Time Two-cell mode — 2 — µs
One-cell mode —10 —µs
Table 4.6. Flash Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Flash Size C8051F912/1 16384* — — bytes
C8051F902/1 8192 — — bytes
Scratchpad Size 512 — 512 bytes
Endurance 1 k 90 k — Erase/Write
Cycles
Erase Cycle Time 28 32 36 ms
Write Cycle Time 57 64 71 µs
*Note: On 16 kB devices, 1024 bytes at addresses 0x3C00 to 0x3FFF are reserved.
Table 4.7. Internal Precision Oscillator Electrical Characteristics
VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter Conditions Min Typ Max Units
Oscillator Frequency –40 to +85 °C,
VDD = 1.8–3.6 V 24 24.5 25 MHz
Oscillator Supply Current
(from VDD)25 °C; includes bias current
of 90–100 µA —300*— µA
*Note: Does not include clock divider or clock tree supply current.
Table 4.8. Internal Low-Power Oscillator Electrical Characteristics
VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter Conditions Min Typ Max Units
Oscillator Frequency –40 to +85 °C,
VDD = 1.8–3.6 V 18 20 22 MHz
Oscillator Supply Current
(from VDD)
25 °C
No separate bias current
required. —100*— µA
*Note: Does not include clock divider or clock tree supply current.
C8051F91x-C8051F90x
54 Rev. 1.1
Table 4.9. SmaRTClock Characteristics
VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter Conditions Min Typ Max Units
Oscillator Fre q ue n cy (L FO ) 13.1 16.4 19.7 kHz
Note: Blue indicates a feature only available on ‘F912 and ‘F902 devices.
Table 4.10. ADC0 Electrical Characteristics
VDD = 1.8 to 3.6V V, VREF = 1.65 V (REFSL[1:0] = 11), –40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
DC Accuracy
Resolution 12-bit mode
10-bit mode 12
10 bits
Integral Nonlinearity 12-bit mode 2
10-bit mode —
—±1
±0.5 ±1.5
±1 LSB
Differential Nonlinearity
(Guaranteed Monotonic) 12-bit mode2
10-bit mode —
—±0.8
±0.5 ±1
±1 LSB
Offset Error 12-bit mode
10-bit mode —
—±<1
±<1 ±2
±2 LSB
Full Scale Error 12-bit mode3
10-bit mode —
—±1
±1 ±4
±2.5 LSB
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale,
maximum sampling rate)
Signal-to-Noise Plus Distortion412-bit mode
10-bit mode 62
54 65
58 —
—dB
Signal-to-Distortion4 12-bit mode
10-bit mode —
—76
73 —
—dB
Spurious-Free Dynamic Range412-bit mode
10-bit mode —
—82
75 —
—dB
Conversion Rate
SAR Conversion Clock Normal Mode
Low Power Mode —
——
—8.33
4.4 MHz
Conversion Time in SAR Clocks 10-bit Mode
8-bit Mode 13
11 —
——
—clocks
Track/Hold Acquisition Time Initial Acquisition
Subsequent Acquisitions (DC
input, burst mode)
1.5
1.1 — — us
Throughput Rate 12-bit mode
10-bit mode —
——
—75
300 ksps
Notes:
1. Blue indicates a feature only available on ‘F912 and ‘F902 devices.
2. INL and DNL specifications for 12-bit mode do not include the first or last four ADC codes.
3. The maximum code in 12-bit mode is 0xFFFC. Th e Full Scale Error is referenced from the maximum code.
4. Performance in 8-bit mode is similar to 10-bit mode.
Rev. 1.1 55
C8051F91x-C8051F90x
Analog Inputs
ADC Input Voltage Range Single Ended (AIN+ – GND) 0 — VREF V
Absolute Pin Voltage with respect
to GND Single Ended 0 — VDD V
Sampling Capacitance
(C8051F912/11/02/01) 1x Gain
0.5x Gain —28
26 —pF
Input Multiplexer Impedance — 5 — k
Power Specifications
Power Supply Current
(VDD supplied to ADC0) Conversion Mode (300 ksps)
Tracki ng Mode (0 ksps) —
—720
680 —
—µA
Power Supply Rejection Internal High Speed VREF
External VREF —
—67
74 —
—dB
Table 4.11. Temperature Sensor Electrical Characteristics
VDD = 1.8 to 3.6V V, –40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Linearity —±1 —°C
Slope —3.40 — mV/°C
Slope Error1—40 —µV/°C
Offset Temp = 25 °C —1025 —mV
Offset Error1Temp = 25 °C —18 —mV
Temperature Sensor Settling
Time2Initial Voltage=0 V
Initial Voltage=3.6 V — — 3.0
6.5 µs
Supply Current —35 —µA
Notes:
1. Represents one standard deviation from the mean.
2. The temperature sensor settling time, resulting from an ADC mux change or enabling of the temperature
sensor, varies with the voltage of the previously sampled channel and can be up to 6 µs if the previously
sampled channel voltage was greater than 3 V. To mini mize the temperature sensor settling time, the ADC
mux can be momentarily set to ground before being set to the temperature sensor output. This ensures th at
the temperature sensor output will settle in 3 µs or less.
Table 4.10. ADC0 Electrical Characteristics (Continued)
VDD = 1.8 to 3.6V V, VREF = 1.65 V (REFSL[1:0] = 11), –40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Notes:
1. Blue indicates a feature only available on ‘F912 and ‘F902 devices.
2. INL and DNL specifications for 12-bit mode do not include the first or last four ADC codes.
3. The maximum code in 12-bit mode is 0xFFFC. Th e Full Scale Error is referenced from the maximum code.
4. Performance in 8-bit mode is similar to 10-bit mode.
C8051F91x-C8051F90x
56 Rev. 1.1
Table 4.12. Voltage Reference Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Internal High Speed Reference (REFSL[1:0] = 11)
Output Voltage –40 to +85 °C,
VDD = 1.8–3.6 V 1.60 1.65 1.70 V
VREF Turn-on Time — — 1.5 µs
Supply Current Normal Power Mode
Low Power Mode —
—260
140 —
—µA
Internal Precision Reference (REFSL[1:0] = 00, REFOE = 1)
Output Voltage –40 to +85 °C,
VDD = 1.8–3.6 V 1.645 1.680 1.715 V
VREF Short-Circuit Current —10 —mA
Load Regulation Load = 0 to 200 µA to AGND —400 —µV/µA
VREF Turn-on Time 1 4.7 µF tantalum, 0.1 µF ceramic
bypass, settling to 0.5 LSB —15 —ms
VREF Turn-on Time 2 0.1 µF ceramic byp ass, settling to
0.5 LSB —300 —µs
VREF Turn-on Time 3 no bypass cap, settling to 0.5 LSB —25 —µs
Supply Current —15 —µA
External Referenc e (REFSL[1:0] = 00, REFOE = 0)
Input Voltage Range 0 — VDD V
Input Current Sample Rate = 300 ksps; VREF =
3.0 V —5.25 —µA
Note: Blue indicates a feature only available on ‘F912 and ‘F902 devices.
Rev. 1.1 57
C8051F91x-C8051F90x
Table 4.13. IREF0 Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C, unless otherwise specified.
Parameter Conditions Min Typ Max Units
Static Performance
Resolution16bits
Output Compliance Range
Low Power Mode, Source
High Current Mode, Source
Low Power Mode, Sink
High Current Mode, Sink
0
0
0.3
0.8
—
—
—
—
VDD – 0.4
VDD – 0.8
VDD
VDD
V
Integral Nonlinearity —<±0.2 ±1.0 LSB
Differential Nonlinearity —<±0.2 ±1.0 LSB
Offset Error —<±0.1 ±0.5 LSB
Full Scale Error2
Low Power Mode, Source — — ±5 %
High Current Mode, Source — — ±6 %
Low Power Mode, Sink — — ±8 %
High Current Mode, Sink — — ±8 %
Absolute Current Error Low Power Mode
Sourcing 20 µA —<±1 ±3 %
Dynamic Performance
Output Settling Time to 1/2 LSB —300 —ns
Startup Time — 1 — µs
Power Consumption
Net Power Supply Current
(VDD supplied to IREF0 minus any
output source current)
Low Power Mode, Source
IREF0DAT = 000 001 —10 —µA
IREF0DAT = 111111 —10 —µA
High Current Mode, Source
IREF0DAT = 000 001 —10 —µA
IREF0DAT = 111111 —10 —µA
Low Power Mode, Sink
IREF0DAT = 000 001 — 1 — µA
IREF0DAT = 111111 —11 —µA
High Current Mode, Sink
IREF0DAT = 000 001 —12 —µA
IREF0DAT = 111111 —81 —µA
Notes:
1. Refer to “PWM Enhanced Mode” on page 86 for information on how to improve IREF0 resolution .
2. Full scale is 63 µA in Low Power Mode and 504 µA in High Power Mode.
C8051F91x-C8051F90x
58 Rev. 1.1
Table 4.14. Comparator Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise noted.
Parameter Conditions Min Typ Max Units
Response Time:
Mode 0, VDD = 2.4 V, VCM* = 1.2 V CP0+ – CP0– = 100 mV —130 —ns
CP0+ – CP0– = –100 mV —200 —ns
Response Time:
Mode 1, VDD = 2.4 V, VCM* = 1.2 V CP0+ – CP0– = 100 mV —210 —ns
CP0+ – CP0– = –100 mV —410 —ns
Response Time:
Mode 2, VDD = 2.4 V, VCM* = 1.2 V CP0+ – CP0– = 100 mV —420 —ns
CP0+ – CP0– = –100 mV —1200 —ns
Response Time:
Mode 3, VDD = 2.4 V, VCM* = 1.2 V CP0+ – CP0– = 100 mV —1750 —ns
CP0+ – CP0– = –100 mV —6200 —ns
Common-Mode Rejection Ratio —1.5 4mV/V
Inverting or Non-Inverting Input
Voltage Range –0.25 — VDD + 0.25 V
Input Capacitance —12 —pF
Input Bias Current — 1 — nA
Input Offset Voltage –7 —+7 mV
Power Supply
Power Supply Rejection —0.1 —mV/V
Power-up Time
VDD = 3.6 V — 0.6 —µs
VDD = 3.0 V — 1.0 —µs
VDD = 2.4 V — 1.8 —µs
VDD = 1.8 V — 10 —µs
Supply Current at DC
Mode 0 —23 —µA
Mode 1 —8.8 —µA
Mode 2 —2.6 —µA
Mode 3 —0.4 —µA
*Note: Vcm is the common-mode voltage on CP0+ and CP0–.
Rev. 1.1 59
C8051F91x-C8051F90x
Hysteresis
Mode 0
Hysteresis 1 (CPnHYP/N1–0 = 00) — 0 — mV
Hysteresis 2 (CPnHYP/N1–0 = 01) —8.5 —mV
Hysteresis 3 (CPnHYP/N1–0 = 10) —17 —mV
Hysteresis 4 (CPnHYP/N1–0 = 11) —34 —mV
Mode 1
Hysteresis 1 (CPnHYP/N1–0 = 00) — 0 — mV
Hysteresis 2 (CPnHYP/N1–0 = 01) —6.5 —mV
Hysteresis 3 (CPnHYP/N1–0 = 10) —13 —mV
Hysteresis 4 (CPnHYP/N1–0 = 11) —26 —mV
Mode 2
Hysteresis 1 (CPnHYP/N1–0 = 00) — 0 1 mV
Hysteresis 2 (CPnHYP/N1–0 = 01) 2 5 10 mV
Hysteresis 3 (CPnHYP/N1–0 = 10) 510 20 mV
Hysteresis 4 (CPnHYP/N1–0 = 11) 12 20 30 mV
Mode 3
Hysteresis 1 (CPnHYP/N1–0 = 00) — 0 — mV
Hysteresis 2 (CPnHYP/N1–0 = 01) —4.5 —mV
Hysteresis 3 (CPnHYP/N1–0 = 10) — 9 — mV
Hysteresis 4 (CPnHYP/N1–0 = 11) —17 —mV
Table 4.15. VREG0 Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Input Voltage Range 1.8 — 3.6 V
Bias Current Normal, idle, suspend, or stop mode —20 —µA
Table 4.14. Comparator Electrical Characteristics (Continued)
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise noted.
Parameter Conditions Min Typ Max Units
*Note: Vcm is the common-mode voltage on CP0+ and CP0–.
C8051F91x-C8051F90x
60 Rev. 1.1
Table 4.16. DC-DC Converter (DC0) Electrical Characteristics
VBAT = 0.9 to 1.8 V, –40 to +85 °C unless otherw ise sp ec ified .
Parameter Conditions Min Typ Max Units
Input Voltage Range C8051F912/02
C8051F911/01 0.9
0.9 —
—3.6
1.8 V
Input Inductor Value 500 680 900 nH
Input Inductor Current Rat-
ing 250 — — mA
Inductor DC Resistance — — 0.5
Input Capacitor Value Source Impedance < 2 —
—4.7
1.0 —
—µF
Output Voltage Range Target Output = 1.8 V
Target Output = 1.9 V
Target Output = 2.0 V
Target Output = 2.1 V
Target Output = 2.4 V
Target Output = 2.7 V
Target Output = 3.0 V
Target Output = 3.3 V
1.73
1.83
1.93
2.03
2.30
2.60
2.90
3.18
1.80
1.90
2.00
2.10
2.40
2.70
3.00
3.30
1.87
1.97
2.07
2.17
2.50
2.80
3.10
3.42
V
Output Load Regulation Target Output = 2.0 V, 1 to 30 mA
Target Output = 3.0 V, 1 to 20 mA —
—±0.3
±1 —
—%
Output Current
(based on output power
spec)
Target Output = 1.8 V
Target Output = 1.9 V
Target Output = 2.0 V
Target Output = 2.1 V
Target Output = 2.4 V
Target Output = 2.7 V
Target Output = 3.0 V
Target Output = 3.3 V
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
36
34
32
30
27
24
21
19
mA
Output Power — — 65 mW
Bias Current
(Normal Current Mode) from VBAT supply
from VDD/DC+ supply —
—80
100 —
—µA
Bias Current
(Low Power Mode) from VBAT supply
from VDD/DC+ supply —
—70
85 —
—
Clocking Frequency 1.6 2.4 3.2 MHz
Maximum DC Load Current
During Startup — — 1 mA
Capacitance Connected to
Output 0.8 1.0 2.0 µF
Rev. 1.1 61
C8051F91x-C8051F90x
5. SAR ADC with 16-bit Auto-Averaging Accumulator and
Autonomous Low Power Burst Mode
The ADC0 on C8051F91x-C8051F90x devices is a 300 ksps, 10-bit or 75 ksps, 12-bit (‘F912/02 only)
successive-approximation-register (SAR) ADC with integrated track-and-hold and programmable window
detector. ADC0 also has an autonomous low power Burst Mode which can automatically enable ADC0,
capture and accumulate samples, then place ADC0 in a low power shutdown mode without CPU
intervention. It also has a 16-bit accumulator that can automatically oversample and average the ADC
results. See Section 5.4 for more details on using the ADC in 12-bit mode.
The ADC is fully configurable under sof tware control via Special Function Registers. The ADC0 operates i n
Single-ended mode and may be configured to measure various different signals using the analog
multiplexer described in “5.7. ADC0 Analog Mult iplexer” on page 78. T he voltage refere nce for the ADC is
selected as described in “5.9. Voltage and Ground Reference Optio ns” on page 83.
Figure 5.1. ADC0 Functional Block Diagram
ADC0CF
AMP0GN
AD0TM
AD08BE
AD0SC0
AD0SC1
AD0SC2
AD0SC3
AD0SC4
10/12-Bit
SAR
ADC
REF
SYSCLK
ADC0H
32
ADC0CN
AD0CM0
AD0CM1
AD0CM2
AD0WINT
AD0BUSY
AD0INT
BURSTEN
AD0EN
Timer 0 Overflow
Timer 2 Overflow
Timer 3 Overflow
Start
Conversion
000 AD0B U SY (W )
VDD
ADC0LTH
AD0WINT
001
010
011
100 CN VS TR Input
W indow
Com pare
Logic
ADC0LTL
ADC0GTH ADC0GTL
ADC0L
AIN+
From
AMUX0
Burst M ode Logic
ADC0TK
ADC0PWR
16-B it Acc u mu la tor
C8051F91x-C8051F90x
62 Rev. 1.1
5.1. Output Code Formatting
The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the
ADC at the completion of each conversion. Data can be right-justified or left-justified, depending on the
setting of the AD0SJST[2:0]. When the repeat count is set to 1, conversion codes are represented as 10-
bit unsigned inte gers. Inputs are measured from 0 to VREF x 1023/10 24. Example c odes are shown below
for both right-justified and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to 0.
When the repeat count is grea ter than 1, th e output conversio n code repr esen ts the accumulat ed result of
the conversions performed and is updated after the last conversion in the series is finished. Sets of 4, 8,
16, 32, or 64 consecutive samples can be accumulated and represented in unsigned integer format. The
repeat count can be selected using the AD0RPT bits in the ADC0AC register. When a repeat count higher
than 1, the ADC output must be right-justified (AD0SJST = 0xx); unused bits in the ADC0H and ADC0L
registers are set to 0. The example below shows the right-justified result for various input voltages and
repeat counts. Notice that accumulating 2n samples is equivalent to left-shifting by n bit positions when all
samples returned from the ADC have the same value.
The AD0SJST bits can be used to format the contents of the 16-bit accumulator. The accumulated result
can be shifted right by 1, 2, or 3 bit positions. Based on the pr inciples of oversampling and averaging, the
effective ADC resolution increa ses by 1 bit each time the oversamp ling rate is increased by a factor of 4.
The example below shows how to increase the effective ADC resolution by 1, 2, and 3 bits to obtain an
effective ADC resolution of 11-bit, 12-bit, or 13-bit re sp ectively without CPU intervention.
Input Voltage Right-Justified ADC0H:ADC0L
(AD0SJST = 000) Left-Justified ADC0H:ADC0L
(AD0SJST = 100)
VREF x 1023/1024 0x03FF 0xFFC0
VREF x 512/1024 0x0200 0x8000
VREF x 256/1024 0x0100 0x4000
0 0x0000 0x0000
Input Voltage Repeat Count = 4 Repeat Count = 16 Repeat Count = 64
VREF x 1023/1024 0x0FFC 0x3FF0 0xFFC0
VREF x 512/1024 0x0800 0x2000 0x8000
VREF x 511/1024 0x07FC 0x1FF0 0x7FC0
0 0x0000 0x0000 0x0000
Input Voltage Repeat Count = 4
Shift Right = 1
11-Bit Result
Repeat Count = 16
Shift Right = 2
12-Bit Result
Repeat Count = 64
Shift Right = 3
13-Bit Result
VREF x 1023/1024 0x07F7 0x0FFC 0x1FF8
VREF x 512/1024 0x0400 0x0800 0x1000
VREF x 511/1024 0x03FE 0x04FC 0x0FF8
0 0x0000 0x0000 0x0000
Rev. 1.1 63
C8051F91x-C8051F90x
5.2. Modes of Operation
ADC0 has a maximum conversion speed of 300 ksps in 10-bit mode. The ADC0 conversion clock
(SARCLK) is a divided version of the system clock when Burst Mode is disabled (BURSTEN = 0), or a
divided version of the low power oscillator when Burst Mode is enabled (BURSEN = 1). The clock divide
value is determined by the AD0SC bits in the ADC0CF register.
5.2.1. Starting a Conversion
A conversion ca n be in itiated in one of five way s, dep ending on the programmed states of the ADC0 Start
of Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of the
following:
1. Writing a 1 to the AD0BUSY bit of register ADC0CN
2. A Timer 0 overflow (i.e., timed continuous conversions)
3. A Timer 2 overflow
4. A Timer 3 overflow
5. A rising edge on the CNVSTR input signal (pin P0.6)
Writing a 1 to AD0BUSY provides software control of ADC0 whereby conversions are performed "on-
demand". During conversion, the AD0BUSY bit is set to logic 1 and reset to log ic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT) should be
used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT is logic 1.
When Timer 2 or Timer 3 overflows are used as the conversion source, Low Byte overflows are used if
Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit mode. See “25. Timers” on
page 270 for timer configuration.
Import ant Note Ab out Using CNVSTR: Th e CNVSTR input pin also functions as Port p in P0 .6. When th e
CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital
Crossbar. To configure the Crossbar to skip P0.6, set to 1 Bit 6 in register P0SKIP. See “21. Port
Input/Output” on page 205 for details on Port I/O configuration.
Important Note: When operating the device in one-cell mode, there is an option available to automatically
synchronize the start of conversion with the quietest portion of the dc-dc converter switching cycle.
Activating this option may help to reduce interference from internal or external power supply noise
generated by the dc-dc converter. Asserting this bit will hold off the start of an ADC conversion initiated by
any of the methods described above until the ADC receives a synchronizing signal from the dc-dc
converter. The delay in initiation of the conversion can be as much as one cycle of the dc-dc converter
clock, which is 625 ns at the minimum dc-dc clock frequency of 1.6 MHz. The synchronization feature also
causes the dc-dc converter clock to be used as the ADC0 conversion clock. The maximum conversion rate
will be limited to approximately 170 ksps at the maximum dc-dc converter clock rate of 3.2 MHz. In this
mode, the ADC0 SAR Conversion Clock Divider must be set to 1 by setting AD0SC[4:0] = 00000b in SFR
register ADC0CF. To provide additional flexibility in minimizing noise, the ADC0 conversion clock provided
by the dc-dc c onverter can b e inverted by setting the AD0CKINV bit in the DC0CF register. For additional
information on the synchronization feature, see the description of the SYNC bit in “SFR
Definition 16.1. DC0CN: DC-DC Converter Control” on page 167 and the description of the AD0CKINV bit
in “SFR Definition 16.2. DC0CF: DC-DC Converter Configuration” on page 168. This bit must be set to 0
in two-cell mode for the ADC to operate.
C8051F91x-C8051F90x
64 Rev. 1.1
5.2.2. Tracking Modes
Each ADC0 conversion must be preceded by a minimum tracking time in order for the converted result to
be accurate. The minimum tracking time is given in Table 4.10. The AD0TM bit in register ADC0CN
controls the ADC0 track-and-hold mode. In its default state when Burst Mode is disabled, the ADC0 input
is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0
operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking
period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initiate
conversions in low-power tracking mode, ADC0 tracks only when CNVSTR is low; conversion begins on
the rising edge of CNVSTR (see Figure 5.2). Tracking can also be disabled (shutdown) when the device is
in low power standby or sleep modes. Low-po we r tr ack- an d-hold mod e is also useful whe n AMUX settings
are frequently changed, due to the settling time requirements described in “5.2.4. Settling Time
Requirements” on p age 66.
Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0)
Write '1' to AD0BUSY,
Timer 0, Timer 2,
Timer 1, Timer 3 Overflow
(AD0CM[2:0]=000, 001,010
011, 101)
AD0TM=1 Track Convert Low Power Mode
AD0TM=0 Track or
Convert Convert Track
Low Power
or Convert
SAR
Clocks
SAR
Clocks
B. ADC0 Timing for Internal Trigger Source
123456789
CNVSTR
(AD0CM[2:0]=100)
AD0TM=1
A. ADC0 Timing for External Trigger Source
SAR Clocks
Track or Convert Convert TrackAD0TM=0
Track Convert Low Power
Mode
Low Power
or Convert
10 11 12 13 14
123456789
10 11 12 13 14
123456789
10 11 12 13 14 15 16 17
Rev. 1.1 65
C8051F91x-C8051F90x
5.2.3. Burst Mode
Burst Mode is a power saving feature that allows ADC0 to remain in a low power state between
conversions . When Burst Mode is ena bled, ADC 0 wakes from a low power state, accumulates 1, 4, 8, 16,
32, or 64 using an internal Burst Mode clock (approximately 20 MHz), then re-enters a low power state.
Since the Burst Mode clock is independent of the system clock, ADC0 can perform multiple conversions
then enter a low power state within a single system clock cycle, even if the system clock is slow (e.g.
32.768 kHz), or suspended.
Burst Mode is enabled by setting BURSTEN to logic 1. When in Burst Mode, AD0EN controls the ADC0
idle power stat e (i.e. the state ADC0 enters when not tracking or performing conversions). If AD0EN is set
to logic 0, ADC0 is powered d own after each burst. If AD0EN is set to logic 1, ADC0 remains enabled after
each burst. On each conver t start signal, ADC0 is awakened from its Idle Power State. If ADC0 is powere d
down, it will automatically power up and wait the programmable Power-Up Time controlled by the
AD0PWR bits. Otherwise, ADC0 will start tracking and converting immediately. Figure 5.3 shows an
example of Burst Mode Operation with a slow system clock and a repeat count of 4.
When Burst Mode is enabled, a single convert start will initiate a number of conversions equal to the repeat
count. When Burst Mode is disabled, a convert start is required to initiate each conversion. In both modes,
the ADC0 End of Conversion Interrupt Flag (AD0INT) will be set after “repeat count” conversions have
been accumulated. Similarly, the Window Comparator will not compare the result to the greater-than and
less-than registers until “repeat count” conversions have been accumulated.
In Burst Mode, tracking is determined by the settings in AD0PWR and AD0TK. The default settings for
these registers will work in most applications without modification; however, settling time requirements may
need adjustment in some applications. Refer to “5.2.4. Settling Time Requirements” on page 66 for more
details.
Notes:
• Setting AD0TM to 1 will insert an additional 3 SAR clocks of tracking before each conversion, regard-
less of the settings of AD0PWR and AD0TK.
• When using Burst Mode, care must be taken to issue a convert start signal no faster than once every
four SYSCLK periods. This includes external convert start signals.
Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4
C onvert S tart
AD0TM = 1
AD0EN = 0 Powered
Down Powered
Down
System C lock
T
3C
Power-Up
and Track T C T C T C Power-Up
and Track TC..
AD0TM = 0
AD0EN = 0 Powered
Down Powered
Down
C
Power-Up
and Track T C T C T C Power-Up
and Track TC..
AD0PWR
T = T racking set by A D 0TK
T 3 = Tra c k in g s e t b y AD 0 TM (3 SA R clo c k s )
C = C onverting
AD0TK
T
3
T
3
T
3
C8051F91x-C8051F90x
66 Rev. 1.1
5.2.4. Settling Time Requirements
A minimum amount of tracking time is required before each conversion can be performed, to allow the
sampling capacitor voltage to settle. This tracking time is determined by the AMUX0 resistance, the ADC0
sampling capacitance, any external source resistance, and the accuracy required for the conversion. Note
that in low-power tracking mode, three SAR clocks are used for tracking at the start of every conversion.
For many applications, these three SAR clocks will meet the minimum tracking time requirements, and
higher values for the external source impedance will increase the required tracking time.
Figure 5.4 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation 5.1. When measuring the Temperature Sensor output or
VDD with respect to GND, RTOTAL reduces to RMUX. See Table 4.10 for ADC0 minimum settling time
requirements as well as the mux impedance and sampling capacitor values.
Equation 5.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
RTOTAL is the sum of the AMUX0 resistance and any external source resistance.
n is the ADC resolution in bits (10).
Figure 5.4. ADC0 Equivalent Input Circuits
t2n
SA
-------
RTOTALCSAMPLE
ln=
RMUX
CSAMPLE
RCInput= RMUX * CSAMPLE
MUX Select
P0.x
Note: The value of CSAMPLE depends on the PGA Gain. See Table 4.10 for details.
Rev. 1.1 67
C8051F91x-C8051F90x
5.2.5. Gain Setting
The ADC has gain settings of 1x and 0.5x. In 1x mode, the full scale reading of the ADC is determined
directly by VREF. In 0.5x mode, the full-scale reading of the ADC occurs when the input volt age is VREF x 2.
The 0.5x gain setting can be useful to obtain a higher input Voltage range when using a small VREF
voltage, or to measure input voltages that are between VREF and VDD. Gain settings for the ADC are
controlled by the AMP0GN bit in register ADC0CF.
5.3. 8-Bit Mode
Setting the ADC08BE bit in register ADC0CF to 1 will put the ADC in 8-bit mode.In 8-bit mode, only the
8 MSBs of data are converted, allowing the conversion to be completed in two fewer SAR clock cycles
than a 10-bit conversion. This can result in an overall lower power consumption since the system can
spend more time in a low po wer mode. The two LSBs of a conversion are always 00 in this mode, and the
ADC0L register will always read back 0x00.
5.4. 12-Bit Mode (C8051F912/02 Only)
C8051F912/02 devices have an enhanced SAR converter that provides 12-bit resolution while retaining
the 10- and 8-bit operating modes of the other devices in the family. When configured for 12-bit
conversions, the ADC performs four 10-bit conversions using four different reference voltages and
combines the results into a single 12-bit value. Unlike simple averaging techniques, this method provides
true 12-bit resolution of AC or DC input signals without depending on noise to provide dithering. The
converter also employs a hardware Dynamic Element Matching algorithm that reconfigures the largest
elements of the internal DAC for each of the four 10-bit conversions to cancel the any matching errors,
enabling the converter to achieve 12-bit linearity performance to go along with its 12-bit resolution. For
best performance, the Low Power Oscillator should be selected as the system clock source while taking
12-bit ADC measurements.
The 12-bit mode is enabled b y setting the AD01 2BE bit ( ADC0AC.7) to logi c 1 and configu rin g Burst Mod e
for four conversions as described in Section 5.2.3. The conversion can be initiated using any of the
methods described in Section 5.2.1, and the 12-bit result will appear in the ADC0H and ADC0L registers.
Since the 12-bit result is formed from a combination of four 10-bit results, the maximum output value is
4 x (1023) = 4092, ra ther than the max value of (2^12 – 1) = 4095 that is produced by a traditional 12-bit
converter. To further increase resolution, the burst mode repeat value may be configured to any multiple of
four conversions. For example, if a repeat value of 16 is selected, the ADC0 output will be a 14-bit number
(sum of four 12-bit numbers) with 13 effective bits of resolution.
5.5. Low Power Mode (C8051F912/902 only)
The C8051F912/02 SAR converter provides a low power mode that allows a significant reduction in
operating curren t when oper ating at low SAR clock fre quencies. Low powe r mode is enab led by setting the
AD0LPM bit (ADC0PWR.7) to 1. In general, low power mode is r ecommended when operating with SAR
conversion clock frequency at 4 MHz or less. See the Electrical Characteristics chapter for details on
power consumption and the maximum clock frequencies allowed in each mode. Setting the Low Power
Mode bit reduces the bias currents in both the SAR converter and in the High-Speed Voltage Reference.
describes the various modes of the ADC.
C8051F91x-C8051F90x
68 Rev. 1.1
Table 5.1. Represent ative Conversion Times and Energy Consumption for the SAR
ADC with 1.65 V High-Speed VREF
Normal Power Mode Low Power Mode
8 bit 10 bit 12 bit 8 bit 10 bit 12 bit
Highest nominal SAR clock
frequency
8.17
MHz
(24.5 / 3)
8.17
MHz
(24.5 /
3) 6.67 MHz
(20.0 / 3)
4.08
MHz
(24.5 / 6)
4.08
MHz
(24.5 / 6) 4.00 MHz
(20.0 / 5)
Total number of
conversion clocks required 11 13 52
(13*4) 11 13 52
(13*4)
Total tracking time (min) 1.5 us 1.5 us 4.8 us
(1.5+3*1.1) 1.5 us 1.5 us 4.8 us
(1.5+3*1.1)
Total time for one
conversion 2.85 us 3.09 us 12.6 us 4.19 us 4.68 us 17.8 us
ADC Throughput 351 ksps 323
ksps 79 ksps 238 ksps 214 ksps 56 ksps
Energy per conversion 8.2 nJ 8.9 nJ 36.5 nJ 6.5 nJ 7.3 nJ 27.7 nJ
Note: This table assumes that the 24.5 MHz precision oscillator is used for 8- and 10-bit modes, and the 20 MHz low
power oscillator is used for 12-bit mode. The values in the ta ble assume that the oscillators run at their
nominal frequencies. The maximum SAR clock values given in Table 4.10 allow for maximum oscillation
frequencies of 25.0 MHz and 22 MHz for the precision and low-power oscillators, respectively, when using the
given SAR clock divider values. Ener gy calculations are for the ADC subsystem only and do not include CPU
current. Modes in BLUE are only available on 'F91 2 and 'F902 devices.
Rev. 1.1 69
C8051F91x-C8051F90x
SFR Page = 0x0; SFR Address = 0xE8; bit-addressable
;
SFR Definition 5.1. ADC0CN: ADC0 Control
Bit76543210
Name AD0EN BURSTEN AD0INT AD0BUSY AD0WINT ADC0CM
Type R/W R/W R/W W R/W R/W
Reset 00000000
Bit Name Function
7AD0EN ADC0 Enable.
0: ADC0 Disabled (low-power shutdown).
1: ADC0 Enabled (active and ready for data conversions).
6BURSTEN ADC0 Burst Mode Enable.
0: ADC0 Burst Mode Disabled.
1: ADC0 Burst Mode Enabled.
5AD0INT ADC0 Conversion Complete Interrupt Flag.
Set by hardware upon completion of a data conversion (BURSTEN=0), or a burst
of conversions (BURSTEN=1). Can trigger an interrupt. Must be cleared by soft-
ware.
4AD0BUSY ADC0 Busy.
Writing 1 to this bit initiates an ADC conversion when ADC0CM[2:0] = 000.
3AD0WINT ADC0 Window Compare Interrupt Flag.
Set by hardware when the contents of ADC0H:ADC0L fall within the window speci-
fied by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL. Can trigger an interrupt.
Must be cleared by software.
2:0 ADC0CM[2:0] ADC0 Start of Conversion Mod e Select.
Specifies the ADC0 start of conversion source.
000: ADC0 conversion initiated on write of 1 to AD0BUSY.
001: ADC0 conversion initiated on overflow of Timer 0.
010: ADC0 conversion initiated on overflow of Timer 2.
011: ADC0 conversion initiated on overflow of Timer 3.
1xx: ADC0 conversion initiated on rising edge of CNVSTR.
Note:
C8051F91x-C8051F90x
70 Rev. 1.1
SFR Page = 0x0; SFR Address = 0xBC
SFR Definition 5.2. ADC0CF: ADC0 Configuration
Bit76543210
Name AD0SC[4:0] AD08BE AD0TM AMP0GN
Type R/W R/W R/W R/W
Reset 11111000
Bit Name Function
7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Divider.
SAR Conversion clock is derived from FCLK by the following equation, where
AD0SC refers to the 5-bit valu e hel d in bits AD0SC[4:0 ]. SAR Conv er sion cloc k
requirements are given in Table 4.10.
BURSTEN = 0: FCLK is the current system clock.
BURSTEN = 1: FCLK is the 20 MHz low power oscillator, independent of the system
clock.
2AD08BE ADC0 8-Bit Mode Enable.
0: ADC0 operates in 10-bit mode (normal operation).
1: ADC0 operates in 8-bit mode.
1AD0TM ADC0 Track Mode.
Selects be tween Normal or Delayed Tracking Modes.
0: Normal Track Mode: When ADC0 is enabled, conversion begins immediately fol-
lowing the start-of-conversion signal.
1: Delayed Track Mode: When ADC0 is enabled, conversion begins 3 SAR clock
cycles following the start-of-conversion signal. The ADC is allowed to track during
this time.
0AMP0GN ADC0 Gain Control.
0: The on-chip PGA gain is 0.5.
1: The on-chip PGA gain is 1.
*
*Round the result up.
or
AD0SC FCLK
CLKSAR
-------------------- 1–=
CLKSAR FCLK
AD0SC 1+
----------------------------
=
Rev. 1.1 71
C8051F91x-C8051F90x
SFR Page = 0x0; SFR Address = 0xBA
SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration
Bit76543210
Name AD012BE AD0AE AD0SJST AD0RPT
Type R/W W R/W R/W
Reset 00000000
Bit Name Function
7AD012BE ADC0 12-Bit Mode Enab l e.
Enables 12-bit Mode. Only available on ‘F912 and ‘F902 devices.
0: 12-bit Mode Disabled.
1: 12-bit Mode Enabled.
6AD0AE ADC0 Accumulate Enable.
Enables multiple conver sions to be accumulated when burst mode is disabled.
0: ADC0H:ADC0L cont ain the result of the latest conver sion when Burst Mode is
disabled.
1: ADC0H:ADC0L cont ain the accumulated conversion results when Burst Mode
is disabled. Software must write 0x0000 to ADC0H:ADC0L to clear the accumu-
lated result.
This bit is write-only. Always reads 0b.
5:3 AD0SJST[2:0] ADC0 Accumulator Shift and Justify.
Specifies the format of data rea d from ADC0H:ADC0L.
000: Right justified. No shifting applied.
001: Right justified. Shifted right by 1 bit.
010: Right justified. Shifted right by 2 bits.
011: Right justified. Shifted right by 3 bits.
100: Left justified. No shifting applied.
All remaining bit combinations are reserved.
2:0 AD0RPT[2:0] ADC0 Repeat Count.
Selects the number of conversions to perform and accumulate in Burst Mode.
This bit field must be set to 000 if Burst Mode is disabled.
000: Perform and Accumulate 1 conversion.
001: Perform and Accumulate 4 conversions.
010: Perform and Accumulate 8 conversions.
011: Perform and Accumulate 16 conversions.
100: Perform and Accumulate 32 conversions.
101: Perform and Accumulate 64 conversions.
All remaining bit combinations are reserved.
C8051F91x-C8051F90x
72 Rev. 1.1
SFR Page = 0xF; SFR Address = 0xBA
SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time
Bit76543210
Name AD0LPM AD0PWR[3:0]
Type R/W RRR R/W
Reset 00001111
Bit Name Function
7AD0LPM ADC0 Low Power Mode Enable.
Enables Low Power Mode Operation. Only available on ‘F912 and ‘F902 devices.
0: Low Power Mode disabled.
1: Low Power Mode enabled.
6:4 Unused Unused.
Read = 0000b; Write = Don’t Care.
3:0 AD0PWR[3:0] ADC0 Burst Mode Power-Up Time.
Sets the time delay required for ADC0 to power up from a low power state.
For BURSTEN = 0:
ADC0 power state controlled by AD0EN.
For BURSTEN = 1 and AD0EN = 1:
ADC0 remains enabled and does no t enter a low power state af ter
all conversions are co mp le te .
Conversions can beg i n imme dia te ly follo win g th e start-of -co nv er sion sig na l.
For BURSTEN = 1 and AD0EN = 0:
ADC0 enters a low powe r state af ter all conversions are complete.
Conversions can begin a progr ammed delay after the start-of-conversion signal.
The ADC0 Burst Mode Power-Up time is programmed according to the following
equation:
Note: Setting AD0PWR to 0x04 provides a typi cal tracki ng time of 2 us for th e fir s t
sample taken after the start of conversion.
or
AD0PWR Tstartup
400ns
---------------------- 1–=
Tstartup AD0PWR 1+400ns=
Rev. 1.1 73
C8051F91x-C8051F90x
SFR Page = 0xF; SFR Address = 0xBD
SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time
Bit 7 6 5 4 3 2 1 0
Name Reserved AD0TK[5:0]
Type R R R/W
Reset 0 0011110
Bit Name Function
7:6 Reserved Reserved.
Read = 0b; Write = Must Write 0b.
6Unused Unused.
Read = 0b; Write = Don’t Care.
5:0 AD0TK[5:0] ADC0 Burst Mode Track Time.
Sets the time delay between consecutive conversions performed in Burst Mode.
The ADC0 Burst Mode Track time is programmed according to the following equa-
tion:
Notes:
1. If AD0TM is set to 1, an additional 3 SAR clock cycles of Track time will be inserted prior to starting the
conversion.
2. The Burst Mode Track delay is not inserted prior to the first conversion. The required tracking time for the first
conversion should be met by the Burst Mode Power-Up Time.
or
AD0TK 63 Ttrack
50ns
-----------------1–
–=
Ttrack 64 AD0TK–50ns=
C8051F91x-C8051F90x
74 Rev. 1.1
SFR Page = 0x0; SFR Address = 0xBE
SFR Page = 0x0; SFR Address = 0xBD;
SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte
Bit76543210
Name ADC0[15:8]
Type R/W
Reset 00000000
Bit Name Description Read Write
7:0 ADC0[15:8] ADC0 Data Word High
Byte. Most Significant Byte of the
16-bit ADC0 Accumulator
formatted according to the
settings in AD0SJST[2:0].
Set the most significant
byte of the 16-bit ADC0
Accumulator to the value
written.
Note: If Accumulator shifting is enabled, the most significant bits of the value read will be zeros. This register
should not be written when the SYNC bit is set to 1.
SFR Definition 5.7. ADC0L: ADC0 Data Word Low Byte
Bit76543210
Name ADC0[7:0]
Type R/W
Reset 00000000
Bit Name Description Read Write
7:0 ADC0[7:0] ADC0 Data Word Low
Byte. Least Significant Byte of the
16-bit ADC0 Accumulator
formatted according to the
settings in AD0SJST[2:0].
Set the least significant
byte of the 16-bit ADC0
Accumulator to the value
written.
Note: If Accumulator shifting is enabled, the most significant bits of the value read will be the least significant bits of
the accumulator high byte. This register should not be written when the SYNC bit is set to 1.
Rev. 1.1 75
C8051F91x-C8051F90x
5.6. Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-
programmed limits, and notifies the system when a desired condition is detected. This is especially
effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster
system response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be
used in polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH,
ADC0LTL) registers hold the comp ariso n values. Th e window detector fla g can be prog ramme d to ind ica te
when measured data is inside or outside of the user-programmed limits, depending on the contents of the
ADC0 Less-Than and ADC0 Greater-Than registers.
SFR Page = 0x0; SFR Address = 0xC4
SFR Page = 0x0; SFR Address = 0xC3
SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte
Bit76543210
Name AD0GT[15:8]
Type R/W
Reset 11111111
Bit Name Function
7:0 AD0GT[15:8] ADC0 Greater-Than High Byte.
Most Significant Byte of the 16-bit Greater-Than window compare register.
SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte
Bit76543210
Name AD0GT[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 AD0GT[7:0] ADC0 Greater-Than Low Byte.
Least Significant Byte of the 16-bit Greater-Than window compare register.
Note: In 8-bit mode, this regi st er sh ou l d be set to 0x0 0 .
C8051F91x-C8051F90x
76 Rev. 1.1
SFR Page = 0x0; SFR Address = 0xC6
SFR Page = 0x0; SFR Address = 0xC5
SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte
Bit76543210
Name AD0LT[15:8]
Type R/W
Reset 00000000
Bit Name Function
7:0 AD0LT[15:8] ADC0 Less-Than High Byte.
Most Significant Byte of th e 16 -bit Le ss- T ha n window com pare regist er.
SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte
Bit76543210
Name AD0LT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 AD0LT[7:0] ADC0 Less-Than Low Byte.
Least Significant Byte of the 16-bit Less-Than window compare r egister.
Note: In 8-bit mode, this regi st er sh ou l d be set to 0x0 0 .
Rev. 1.1 77
C8051F91x-C8051F90x
5.6.1. Window Detector In Single-Ended Mode
Figure 5.5 shows two example window comparisons for right-justified data, with
ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can
range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer
value. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word
(ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL
(if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt will be generated if
the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers
(if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 5.6 shows an example using left-
justified data with the same comparison values.
Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended Data
Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data
5.6.2. ADC0 Specifications
See “4. Electrical Characteristics” on page 36 for a detailed listing of ADC0 specifications.
0x03FF
0x0081
0x0080
0x007F
0x0041
0x0040
0x003F
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
VREF x (128/ 1 024)
VREF x (64/1024)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
0x03FF
0x0081
0x0080
0x007F
0x0041
0x0040
0x003F
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT
not affe c ted
AD0WINT=1
AD0WINT=1
ADC0H:ADC0L ADC0H:ADC0L
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0xFFC0
0x2040
0x2000
0x1FC0
0x1040
0x1000
0x0FC0
0x0000
0
Input Voltage
(Px.x - G N D)
VREF x (1023/1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
0xFFC0
0x2040
0x2000
0x1FC0
0x1040
0x1000
0x0FC0
0x0000
0
Input Voltage
(Px.x - GN D)
VREF x (1023/1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT
not affected
AD0WINT=1
AD0WINT=1
ADC0H:ADC0L ADC0H:ADC0L
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
C8051F91x-C8051F90x
78 Rev. 1.1
5.7. ADC0 Analog Multiplexer
ADC0 on C8051F91x-C8051F90x has an analog multiplexer, referred to as AMUX0.
AMUX0 selects the positive inputs to the single-ended ADC0. Any of the following may be selected as the
positive input: Port I/O pins, the on-chip temperature sensor, the VBAT Power Supply, Regulated Digital
Supply Voltage (Output of VREG0), VDD/DC+ Su pply, or the positive input may be connected to GND. The
ADC0 input channels are selected in the ADC0MX register described in SFR Definition 5.12.
Figure 5.7. ADC0 Multiplexer Block Diagram
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be
configured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for
analog inp ut , s et to 0 th e co rr esponding bit in register PnMDIN and disable the digital driver (PnMDOUT =
0 and Port Latch = 1). To force the Crossbar to skip a Port pin, set to 1 the corresponding bit in register
PnSKIP. See Section “21. Port Input/Output” on page 205 for more Port I/O co nfig u ra tio n de tails.
ADC0
Temp
Sensor
AMUX
VBAT
ADC0MX
AD0MX4
AD0MX3
AD0MX2
AD0MX1
AM0MX0
AIN+
P0.0
P1.6*
D ig ital S u p ply
VDD/DC+
Programmable
Attenuator
G ain = 0.5 or 1
ADC0
Temp
Sensor
AMUX
VBAT
ADC0MX
AD0MX4
AD0MX3
AD0MX2
AD0MX1
AM0MX0
AIN+
P0.0
P1.6*
D ig ital S u p ply
VDD/DC+
Programmable
Attenuator
G ain = 0.5 or 1
Rev. 1.1 79
C8051F91x-C8051F90x
SFR Page = 0x0; SFR Address = 0xBB
SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select
Bit76543210
Name AD0MX
Type R R R R/W R/W R/W R/W R/W
Reset 00011111
Bit Name Function
7:5 Unused Unused.
Read = 000b; Write = Don’t Care.
4:0 AD0MX AMUX0 Positive Input Selection.
Selects the positive input channel for ADC0.
00000: P0.0 10000: Reserved.
00001: P0.1 10001: Reserved.
00010: P0.2 10010: Reserved.
00011: P0.3 10011: Reserved.
00100: P0.4 10100: Reserved.
00101: P0.5 10101: Reserved.
00110: P0.6 10110: Reserved.
00111: P0.7 10111: Reserved.
01000: P1.0 11000: Reserved.
01001: P1.1 11001: Reserved.
01010: P1.2 11010: Reserved.
01011: P1.3 11011: Temperat ur e Sen so r
01100: P1.4 11100: VBAT Supply Voltage
(0.9–1.8 V) or (1.8–3.6 V)
01101: P1.5
01110: P1.6 11101: Digital Supply Voltage
(VREG0 Output, 1.7 V Typical)
01111: Reserved, 11110: VDD/DC+ Supply Voltage
(1.8–3.6 V)
11111: Ground
C8051F91x-C8051F90x
80 Rev. 1.1
5.8. Temperature Sensor
An on-chip temperature sensor is included on the C8051F91x-C8051F90x which can be directly accessed
via the ADC multiplexer in single-ended configuration. To use the ADC to measure the temperature sensor,
the ADC mux channel should select the temperature sensor. The temperature sensor transfer function is
shown in Figure 5.8. The output voltage (VTEMP) is the positive ADC input when the ADC multiplexer is set
correctly. The TEMPE bit in register REF0CN enables/disables the temperature sensor, as described in
SFR Definition 5.15. While disabled, the temperature sensor defaults to a high impedance state and any
ADC measurements performed on the sensor will result in meaningless data. Refer to Table 4.11 for the
slope and offset parameters of the temperature sensor.
Figure 5.8. Temperature Sensor Transfer Function
Temperature
Voltage
VTEMP = Slope x (TempC
Offset ( V at 25 Celsius)
Slope (V / deg C)
TempC = 25 + (
- 25) + Offset
VTEMP - Offset) / Slope
Rev. 1.1 81
C8051F91x-C8051F90x
5.8.1. Calibration
The uncalibrated temperat ure sensor output is extremely linear and suitable for relative temperature mea-
surements (see Table 4.11 for linearity specifications). For absolute temperature measurements, offset
and/or gain calibr ation is recomme nded. Typically a 1-point (off set) ca libration inclu des the following ste ps:
1. Control/measure the ambient temperature (this temperature must be known).
2. Power the device, and delay for a few seconds to allow for self-heating.
3. Perform an ADC conversion with the temperature sensor selected as the positive input and
GND selected as the negative input.
4. Calculate the offset characteristics, and store this value in non-volatile memory for use with
subsequent temperature sensor measurements.
Figure 5.9 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C. Parame-
ters that affect ADC measurement, in particular the voltage reference value, will also affect temper-
ature measurement.
A single-point offset measurement of the temperature sensor is performed on each device during produc-
tion test. The measurement is pe rformed at 25 °C ±5 °C, using the ADC with the internal high speed refer-
ence buffer selected as the Voltage Reference. The direct ADC result of the measurement is stored in the
SFR registers TOFFH and TOFFL, shown in SFR Definition 5.13 and SFR Definition 5.14.
Figure 5.9. Temperature Sensor Error with 1-Point Calibration (VREF = 1.68 V)
-40.00 -20.00 0.00 20.00 40.00 60.00 80.00
Temperature (degrees C)
Error (degrees C)
-5.00
-4.00
-3.00
-2.00
-1.00
0.00
1.00
2.00
3.00
4.00
5.00
-5.00
-4.00
-3.00
-2.00
-1.00
0.00
1.00
2.00
3.00
4.00
5.00
C8051F91x-C8051F90x
82 Rev. 1.1
SFR Page = 0xF; SFR Address = 0x86
SFR Page = 0xF; SFR Address = 0x85
SFR Definition 5.13. TOFFH: ADC0 Data Word High Byte
Bit76543210
Name TOFF[9:2]
Type RRRRRRRR
Reset Varies Varies Varies Varies Varies Varies Varies Varies
Bit Name Function
7:0 TOFF[9:2] Temperature Sensor Offset High Bits.
Most Significant Bits o f the 10-bit temperature sensor offset measurement.
SFR Definition 5.14. TOFFL: ADC0 Data Word Low Byte
Bit76543210
Name TOFF[1:0]
Type RR
Reset VariesVaries000000
Bit Name Function
7:6 TOFF[1:0] Temperature Sensor Offset Low Bits.
Least Significant Bits of the 10-bit temp erature sensor offset measurement.
5:0 Unused Unused.
Read = 0; Write = Don't Care.
Rev. 1.1 83
C8051F91x-C8051F90x
5.9. Voltage and Ground Reference Options
The voltage reference MUX is configurable to use an externally connected voltage reference, one of two
internal voltage references, or one of two power supply voltages (see Figure 5.10). The gr ound refere nce
MUX allows the ground reference for ADC0 to be selected between the ground pin (GND) or a port pin
dedicated to analog ground (P0.1/AGND).
The voltage and ground reference options are configured using the REF0CN SFR described on page 85.
Electrical specifications are can be found in the Electrical Specifications Chapter.
Important Note About the VREF and AGND Inputs: Port pins are used as the external VREF and AGND
inputs. When u sing an external volt age r eference or the internal precision reference, P0.0/VREF should be
configured as an analog input and skipped by the Digital Crossbar. When using AGND as the ground
reference to ADC0, P0.1/AGND should be configured as an analog input and skipped by the Digital
Crossbar. Refer to Section “21. Port Input/Output” on page 205 for complete Port I/O configuration details.
The external reference voltage must be within the range 0 VREF VDD/DC+ and the external ground
reference must be at the same DC voltage potential as GND.
Figure 5.10. Voltage Reference Functional Block Diagram
VREF
(to A D C )
ADC
Input
Mux
P0.0/VREF
R1
VDD External
Voltage
Reference
Circuit
GND
Tem p S ensor
EN
00
01
10
11
REF0CN
REFSL0
TEMPE
REFOE
REFSL1
REFGND
Internal 1.68V
Reference
Recom mended
Bypass Capacitors
+
4.7F0.1F
Internal 1.8V
Regulated D igital Supply
EN
VDD/DC+
Internal 1.65V
High Speed R eference
GND
P0.1/AGND 0
1 G round
(to A D C )
REFOE
REFGND
C8051F91x-C8051F90x
84 Rev. 1.1
5.10. External Voltage References
To use an external voltage reference, REFSL[1 :0] should be set to 00 and the inter nal 1.68 V pr ecision ref-
erence should be disabled by setting REFOE to 0. Bypass capacitors should be added as recommended
by the manufacturer of the external voltage reference.
5.11. Internal Voltage References
For applications requiring the maximum number of port I/O pins, or very short VREF turn-on time, the
1.65 V high-speed reference will be the best internal reference option to choose. The high speed internal
reference is selected by setting REFSL[1:0] to 11. When selected, the high speed internal reference will be
automatically enabled/disabled on an as-needed basis by ADC0.
For applications requiring the highest absolute accuracy, the 1.68 V precision voltage reference will be the
best internal reference option to choose. The 1.68 V precision reference may be enabled and selected by
setting REFOE to 1 and REFSL[1:0] to 00. An external capacitor of at least 0.1 µF is recommended when
using the precision voltage reference.
In applications that leave the precision internal oscillator always running, there is no additional power
required to use the precision voltage reference. In all other applications, using the high speed reference
will result in lower overall power consumption due to its minimal startup time and the fact that it remains in
a low power state when an ADC conversion is not taking place.
Note: When using the pr ec is io n internal oscillator as the system clock source, the precision voltage
reference should not be enabled from a disabled state. To use the precision oscillator and the precision
voltage reference simultan eously, the precision voltage reference should be en abled first and allowed
to settle to its final value (charging the external capacitor) before the precision oscillator is started and
selected as the system clo ck.
For applications with a non-varying power supply voltage, using the power supply as the voltage reference
can provide ADC0 with added dynamic range at the cost of reduced power supply noise rejection. To use
the 1.8 to 3.6 V power supply voltage (VDD/DC+) or the 1.8 V regulated digital supply voltage as the
reference so ur ce , RE FS L[1 :0 ] shou ld be se t to 01 or 10, respectively.
5.12. Analog Ground Reference
To prevent ground noise generated by switching digital logic from affecting sensitive analog
measurements, a separate analog ground reference option is available. When enabled, the ground
reference for ADC0 during both the tracking/sampling and the conversion periods is taken from the
P0.1/AGND pin. Any exter nal sensor s sampled by ADC0 should be re ferenced to the P0.1/AGND pin. This
pin should be connected to the ground terminal of any external sensors sampled by ADC0. If an external
voltage r eference is used, the P0.1/AGND pi n should be co nnecte d to th e ground of the ex ternal refe renc e
and its associate d decoupling cap acitor. If the 1.68 V precision internal reference is used, then P0.1/AGND
should be connected to the ground terminal of its external decoupling capacitor. The separate analog
ground reference option is enabled by setting REFGND to 1. Note that when sampling the internal
temperature sensor, the internal chip ground is always used for the sampling operation, regardless of the
setting of the REFGND bit. Similarly, whenever the internal 1.65 V high-speed reference is selected, the
internal chip groun d is a lwa ys use d dur ing th e conversion pe riod, re gar dless o f the settin g of th e REFGND
bit.
5.13. Temperature Sensor Enable
The TEMPE bit in register REF0CN enables/disables the temperature sensor. While disabled, the
temperature sensor defaults to a high impedance state and any ADC0 measurements performed on the
sensor result in meaningless data. See Section “5.8. Temperature Sensor” on page 80 for details on
temperature sensor ch aracteristics when it is enabled.
Rev. 1.1 85
C8051F91x-C8051F90x
SFR Page = 0x0; SFR Address = 0xD1
5.14. Voltage Reference Electrical Specifications
See Table 4.12 on page 56 for detailed Voltage Reference Electrical Specifications.
SFR Definition 5.15. REF0CN: Voltage Reference Control
Bit76543210
Name REFGND REFSL TEMPE REFOE
Type R R R/W R/W R/W R/W R R/W
Reset 00011000
Bit Name Function
7:6 Unused Unused.
Read = 00b; Write = Don’t Care.
5REFGND Analog Ground Reference.
Selects the ADC0 ground reference.
0: The ADC0 ground reference is the GND pi n.
1: The ADC0 ground refer ence is the P0.1/AGND pin.
4:3 REFSL Voltage Reference Select.
Selects the ADC0 voltage reference.
00: The ADC0 voltage reference is the P0.0/VREF pin.
01: The ADC0 voltage reference is the VDD/DC+ pin.
10: The ADC0 voltage refere nc e is the inte rn al 1. 8 V digital supply voltage.
11: The ADC0 voltage reference is the internal 1.65 V high speed voltage reference.
2TEMPE Temperature Sensor Enable.
Enables/Disables the internal temperature sensor.
0: Temperature Sensor Disabled.
1: Temperature Sensor Enabled.
1Unused Unused.
Read = 0b; Write = Don’t Care.
0REFOE Internal Voltage Reference Output Enable.
Connects/Disconnects the internal voltage reference to the P0.0/VREF pin.
0: Internal 1.68 V Precision Voltage Reference disabled and not connected to
P0.0/VREF.
1: Internal 1.68 V Precision Voltage Referenc e en ab le d an d co nn e cte d to
P0.0/VREF.
C8051F91x-C8051F90x
86 Rev. 1.1
6. Programmable Current Reference (IREF0)
C8051F91x-C8051F90x devices include an on -chip programmable current reference (source or sink) with
two output current settings: Lo w Power Mode and High Current Mode. The maximum current output in Low
Power Mode is 63 µA (1 µA steps) and the maximum current output in High Current Mode is 504 µA (8 µA
steps).
The current source/sink is controlled though the IREF0CN special function register. It is enabled by setting
the desired output current to a non-zero value. It is disabled by writing 0x 00 to IREF0CN. Th e port I/O pin
associated with ISRC0 should be configured as an analog input and skipped in the Crossbar. See Section
“21. Port Input/Output” on page 205 for more details.
SFR Page = 0x0; SFR Address = 0xB9
6.1. PWM Enhanced Mode
On ‘F912 and ‘F902 devices, the precision of the current reference can be increased by fine tuning the
IREF0 output using a PWM signal generated by the PCA. This mode allows the IREF0DAT bits to perform
a course adjustment on the IREF0 output. Any available PCA channel can perform a fine adjustment on
the IREF0 output. When enabled (PWMEN = 1), the CEX signal selected using the PWMSS bit field is
internally routed to IREF0 to control the on time of a current source having the weight of 2 LSBs. With the
two least significant bits of IREF0DAT set to 00b, applying a 100% duty cycle on the CEX signal will be
equivalent to setting the two LSBs of IREF0DAT to 10b. PWM enhanced mode is enabled and setup using
the IREF0CF register.
SFR Definition 6.1. IREF0CN: Current Reference Control
Bit76543210
Name SINK MODE IREF0DAT
Type R/W R/W R/W
Reset 00000000
Bit Name Function
7SINK IREF0 Current Sink Enable.
Selects if IREF0 is a current source or a current sink.
0: IREF0 is a current source.
1: IREF0 is a current sink.
6MDSEL IREF0 Output Mode Select.
Selects Low Power or High Current Mode.
0: Low Power Mode is selected (step size = 1 µA).
1: High Current Mode is selected (step size = 8 µA).
5:0 IREF0DAT[5:0] IREF0 Data Word.
Specifies the number of steps required to achieve the desired output current.
Output current = direction x step size x IREF0 DAT.
IREF0 is in a low power state when IREF0DAT is set to 0x00.
Rev. 1.1 87
C8051F91x-C8051F90x
SFR Page = 0xF; SFR Address = 0xB9
6.2. IREF0 Specifications
See Table 4.13 on page 57 for a detailed listing of IREF0 specifications.
SFR Definition 6.2. IREF0CF: Current Reference Configuration
Bit76543210
Name PWMEN PWMSS[2:0]
Type R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7PWMEN PWM Enhanced Mode Enable.
Enables the PWM Enhanced Mode. Only available on ‘F912 and ‘F902 devices.
0: PWM Enhanced Mode disabled.
1: PWM Enhanced Mode enabled.
6:3 Unused Unused.
Read = 00b, Write = don’t care.
2:0 PWMSS[2:0] PWM Source Select.
Selects the PCA channel to use for the fine-tuning control signal. Only available
on ‘F912 and ‘F902 devices.
000: CEX0 selected as fine-tuning control signal.
001: CEX1 selected as fine-tuning control signal.
010: CEX2 selected as fine-tuning control signal.
011: CEX3 selected as fine-tuning control signal.
100: CEX4 selected as fine-tuning control signal.
101: CEX5 selected as fine tuning control signal.
All Other Values: Reserved.
C8051F91x-C8051F90x
88 Rev. 1.1
7. Comparators
C8051F91x-C8051F90x devices include two on-chip programmable voltage comparators: Comparator 0
(CPT0) is shown in Figure 7.1; Compar ator 1 (CPT1) is shown in Figure 7.2. The two comparators operate
identically, but may differ in their ability to be used as reset or wake-up sources. See the Reset Sources
chapter and the Power Management chapter for details on reset sources and low power mode wake-up
sources, respectively.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are op tiona lly ava ilable at the Port pins: a digital synchronous “latched” output (CP0, CP1), or
a digit al as ynchronou s “ra w” outp ut (CP0A, CP1A). T he asynchronous CP0A signal is available even when
the system clock is not active. This allows the Comparator to operate and generate an output when the
device is in some low power modes.
7.1. Comparator Inputs
Each Comparator performs an analog comparison of the voltage levels at its positive (CP0+ or CP1+) and
negative (CP0- or CP1-) input. Both comparators support multiple port pin inputs multiplexed to their
positive and negative comp arato r input s using ana log input mu ltiplexer s. The an alog input m ultiplexers are
completely under sof tware control and configured using SFR registers. See Section “7.6. Comp arator0 and
Comparator1 Analog Multiplexers” on page 95 for details on how to select and configure Comparator
inputs.
Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be
configured as analog input s and skipped by the Crossbar. See the Port I/O chapter for more det ails on how
to configure Port I/O pins as Analog Inputs. The Comparator may also be used to compare the logic level
of digital signals, however, Port I/O pins configured as digital inputs must be driven to a valid logic state
(HIGH or LOW) to avoid increased power consumption.
Figure 7.1. Comparator 0 Functional Block Diagram
VDD
CPT0CN
Reset
Decision
Tree
+
- Crossbar
Interrupt
Logic
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CP0 +
Px.x
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0 CPT0MD
CP0RIE
CP0FIE
CP0MD1
CP0MD0
CP0
CP0A
CP0
Rising-edge CP0
Falling-edge
CP0
Interrupt
Px.x
Px.x
Px.x
CP0 - (ASYNCHRONOUS)
Analog Input Multiplexer
Rev. 1.1 89
C8051F91x-C8051F90x
7.2. Comparator Outputs
When a comparator is enabled, its output is a logic 1 if the voltage at the positive input is higher than the
voltage at the negative input. When disabled, the comparator ou tpu t is a lo gic 0. The comparator output is
synchronized with the system clock as shown in Figure 7.2. The synchronous “latched” output (CP0, CP1)
can be polled in sof tware (CPnOUT bit), used as an interrupt source, or routed to a Port pin (configured for
digital I/O) through the Crossbar.
The asynchronous “raw” comparator output (CP0A, CP1A) is used b y the low power mode wake-up logic
and reset decision logic. See the Power Options chapter and the Reset Sources chapter for more details
on how the asynchronous comparator outputs are used to make wake-up and reset decisions. The
asynchronous comparator output can also be routed directly to a Port pin through the Crossbar, and is
available for use outside the device even if the system clock is stopped.
When using a Comparator as an interrupt source, Comparator interrupts can be generated on rising-edge
and/or falling-edge comparator output transitions. Two independent interrupt flags (CPnRIF and CPnFIF)
allow sof tware to d eter mine wh ich ed ge cau sed the Comparator interrupt. The comparator rising-edge and
falling-edge interrupt flags are set by hardware when a corresponding edge is detected regardless of the
interrupt enable state. Once set, these bits remain set until cleared by software.
The rising-edge and falling-edge interrupts can be individually enabled using the CPnRIE and CPnFIE
interrupt enable bits in the CPTnMD register. In order for the CPnRIF and/or CPnFIF interrupt flags to
generate an interrupt request to the CPU, the Comparator must be enabled as an interrupt source and
global interrupts must be enabled. See the Interrupt Handler chapter for additional information.
Figure 7.2. Comparator 1 Functional Block Diagram
VDD
CPT0CN
Reset
Decision
Tree
+
- Crossbar
Interrupt
Logic
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CP1 +
Px.x
CP1EN
CP1OUT
CP1RIF
CP1FIF
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0 CPT0MD
CP1RIE
CP1FIE
CP1MD1
CP1MD0
CP1
CP1A
CP1
Rising-edge CP1
Falling-edge
CP1
Interrupt
Px.x
Px.x
Px.x
CP1 - (ASYNCHRONOUS)
Analog Input Multiplexer
C8051F91x-C8051F90x
90 Rev. 1.1
7.3. Comparator Response Time
Comparator response time may be configured in software via the CPTnMD registers described on
“CPT0MD: Comparator 0 Mode Selection” on page 92 and “CPT1MD: Comparator 1 Mode Selection” on
page 94. Four response time settings are available: Mode 0 (Fastest Response Time), Mode 1, Mode 2,
and Mode 3 (Lowest Power). Selecting a longer response time reduces the Comparator active supply
current. The Comparators also have low power shutdown state, which is entered any time the comparator
is disabled. Comparator rising edge and falling edge response times are typically not equal. See
Table 4.14 on page 58 for complete comparator timing and supply current specifications.
7.4. Comparator Hysteresis
The Comparators feature software-programmable hysteresis that can be used to stabilize the comparator
output while a transition is occurring on the input. Using the CPTnCN registers, the user can program both
the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going
symmetry of this hysteresis around the threshold voltage (i.e., the comparator negative input).
Figure 7.3 shows that when positive hysteresis is enabled, the comparator output does not transition from
logic 0 to logic 1 until the comparator positive input voltage has exceeded the threshold voltage by an
amount equal to the programmed hysteresis. It also shows that when negative hys teresis is enabled, the
comparator output does not transition from logic 1 to logic 0 until the comparator positive input voltage has
fallen below the threshold voltage by an amount equal to the programmed hysteresis.
The amount of positive hysteresis is determined by the settings of the CPnHYP bits in the CPTnCN
register and th e a mou nt of neg ative h ysteresis voltage is determined by the settin gs o f th e CPnHYN bits in
the same register. Settings of 20, 10, 5, or 0 mV can be programmed for both positive and negative
hysteresis. See Section “Table 4.14. Comparator Electrical Characteristics” on page 58 for complete
comparator hysteresis specifications.
Figure 7.3. Comparator Hysteresis Plot
Positive Hysteresis Voltage
(Programm ed with CP0HYP Bits)
Negative Hysteresis Voltage
(Program med by CP0HY N Bits)
VIN-
VIN+
INPUTS
CIRCUIT CONFIGURATION
+
_
CPn+
CPn- CPn
VIN+
VIN- OUT
VOH
Positive Hysteresis
Disabled Maximum
Positive Hysteresis
Negative Hysteresis
Disabled Maximum
Negative Hysteresis
OUTPUT
VOL
Rev. 1.1 91
C8051F91x-C8051F90x
7.5. Comparator Register Descriptions
The SFRs used to enable and configure the comparators are described in the following register
descriptions. A Comparator must be enabled by setting the CPnEN bit to logic 1 before it can be used.
From an enabled state, a comparator can be disabled and placed in a low power state by clearing the
CPnEN bit to logic 0.
Important Note About Comparator Settings: False rising and falling edges can be detected by the
Comparator while powering on or if changes are made to the hysteresis or response time control bits.
Therefore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a
short time af ter the co mp arator is ena bled or its mode bits have been change d. The Comparator Power Up
Time is specified in Section “Table 4.14. Comparator Electrical Char acteristics” on page 58.
SFR Page= 0x0; SFR Address = 0x9B
SFR Definition 7.1. CPT0CN: Comparator 0 Control
Bit76543210
Name CP0EN CP0OUT CP0RIF CP0FIF CP0HYP[1:0] CP0HYN[1:0]
Type R/W RR/W R/W R/W R/W
Reset 00000000
Bit Name Function
7CP0EN Comparator0 Enable Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.
6CP0OUT Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
5CP0RIF Comparator0 Rising-Edge Flag. Must be cleared by software.
0: No Comparator0 Rising Edge has occurred since this flag was last cleared.
1: Comparator0 Rising Edge has occurred.
4CP0FIF Comparator0 Falling-Edge Flag. Must be cleared by software.
0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge has occurred.
3-2 CP0HYP[1:0] Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = Hysteresis 1.
10: Positive Hysteresis = Hysteresis 2.
11: Positive Hysteresis = Hysteresis 3 (Maximum).
1:0 CP0HYN[1:0] Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = Hysteresis 1.
10: Negative Hysteresis = Hysteresis 2.
11: Negative Hysteresis = Hysteresis 3 (Maximum).
C8051F91x-C8051F90x
92 Rev. 1.1
SFR Page = All Pages; SFR Address = 0x9D
SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection
Bit76543210
Name CP0RIE CP0FIE CP0MD[1:0]
Type R/W RR/W R/W R R R/W
Reset 10000010
Bit Name Function
7Reserved Reserved.
Read = 1b, Must W rite 1b.
6Unused Unused.
Read = 0b, Write = don’t care.
5CP0RIE Comparator0 Rising-Edge Interrupt En able.
0: Comparator0 Rising-edge interrupt disabled.
1: Comparator0 Rising-edge interrupt enabled.
4CP0FIE Comparator0 Falling-Edge Interrupt Enable.
0: Comparator0 Falling-edge interrupt disabled.
1: Comparator0 Falling-edge interrupt enabled.
3:2 Unused Unused.
Read = 00b, Write = don’t care.
1:0 CP0MD[1:0] Comparator0 Mode Select
These bits affect the response time and power consumption for Comparato r0.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
Rev. 1.1 93
C8051F91x-C8051F90x
SFR Page= 0x0; SFR Address = 0x9A
SFR Definition 7.3. CPT1CN: Comparator 1 Control
Bit76543210
Name CP1EN CP1OUT CP1RIF CP1FIF CP1HYP[1:0] CP1HYN[1:0]
Type R/W RR/W R/W R/W R/W
Reset 00000000
Bit Name Function
7CP1EN Comparator1 Enable Bit.
0: Comparator1 Disabled.
1: Comparator1 Enabled.
6CP1OUT Comparator1 Output State Flag.
0: Voltage on CP1+ < CP1–.
1: Voltage on CP1+ > CP1–.
5CP1RIF Comparator1 Rising-Edge Flag. Must be cleared by software.
0: No Comparator1 Rising Edge has occurred since this flag was last cleared.
1: Comparator1 Rising Edge has occurred.
4CP1FIF Comparator1 Falling-Edge Flag. Must be cleared by software.
0: No Comparator1 Falling-Edge has occurred since this flag was last cleared.
1: Comparator1 Falling-Edge has occurred.
3:2 CP1HYP[1:0] Comparator1 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = Hysteresis 1.
10: Positive Hysteresis = Hysteresis 2.
11: Positive Hysteresis = Hysteresis 3 (Maximum).
1:0 CP1HYN[1:0] Comparator1 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = Hysteresis 1.
10: Negative Hysteresis = Hysteresis 2.
11: Negative Hysteresis = Hysteresis 3 (Maximum).
C8051F91x-C8051F90x
94 Rev. 1.1
SFR Page = 0x0; SFR Address = 0x9C
SFR Definition 7.4. CPT1MD: Comparator 1 Mode Selection
Bit76543210
Name CP1RIE CP1FIE CP1MD[1:0]
Type R/W RR/W R/W R R R/W
Reset 10000010
Bit Name Function
7Reserved Reserved.
Read = 1b, Must W rite 1b.
6Unused Unused.
Read = 00b, Write = don’t care.
5CP1RIE Comparator1 Rising-Edge Interrupt En able.
0: Comparator1 Rising-edge interrupt disabled.
1: Comparator1 Rising-edge interrupt enabled.
4CP1FIE Comparator1 Falling-Edge Interrupt Enable.
0: Comparator1 Falling-edge interrupt disabled.
1: Comparator1 Falling-edge interrupt enabled.
3:2 Unused Unused.
Read = 00b, Write = don’t care.
1:0 CP1MD[1:0] Comparator1 Mode Select
These bits affect the response time and power consumption for Comparato r1.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
Rev. 1.1 95
C8051F91x-C8051F90x
7.6. Comparator0 and Comparator1 Analog Multiplexers
Comparator0 and Comparator1 on C8051F91x-C8051F90x devices have analog input multiplexers to
connect Port I/O pins and internal signals the comparator inputs; CP0+/CP0- are the positive and negative
input multiplexers for Comparator0 and CP1+/CP1- are the positive and negative input multiplexers for
Comparator1.
The comparator inp ut multiplexers directly support capacitive touch switches. When the Capacitive Touch
Sense Compare input is selected on the positive or negative multiplexer, any Port I/O pin connected to the
other multiplexer can be directly connected to a capacitive touch switch with no additional external
components. The Capacitive Touch Sense Compare provides the appropriate reference level for detecting
when the capacitive touch switches have charged or discharged through the on-chip Rsense resistor. The
Comparator outputs can be routed to Timer2 or Timer3 for capturing sense capacitor’s charge and
discharge time. See Section “25. Timers” on page 270 for details.
Any of the following may be selected as comparator inputs: Port I/O pins, Capacitive Touch Sense
Compare, VDD/DC+ Supply Voltage, Regulated Digital Supply Voltage (Output of VREG0), the VBAT
Supply voltage or groun d. The Comparator’s supply voltage divided by 2 is also available as an input; the
resistors used to divide the voltage only draw curre nt when this setting is select ed. The Comparator input
multiplexers are config ured usin g th e CPT0MX and CPT1 MX register s described in SFR Definition 7.5 and
SFR Definition 7.6.
Figure 7.4. CPn Multiplexer Block Diagram
Import ant Not e About Co mp ar ator Input Configurat ion: Por t pins selected as compar ator input s should
be configured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for
analog inp ut , s et to 0 th e co rr esponding bit in register PnMDIN and disable the digital driver (PnMDOUT =
0 and Port Latch = 1). To force the Crossbar to skip a Port pin, set to 1 the corresponding bit in register
PnSKIP. See Section “21. Port Input/Output” on page 205 for more Port I/O co nfig u ra tio n de tails.
CPn-
Input
MUX
Digital Supply
P0.1
VDD/DC+
+
-
GND
VDD/DC+
P0.3
P0.5
P0.7
P1.1
P1.3
P1.5
VDD/DC+
R
R
VDD/DC+
R
R
CPnOUT
R
½ x VDD/DC+
(1/3 or 2/3) x VDD/DC+
Capacitive
Touch
Sense
Compare
CPn+
Input
MUX
VBAT
CPTnMX
CMXnN3
CMXnN2
CMXnN1
CMXnN0
CMXnP3
CMXnP2
CMXnP1
CMXnP0
P0.0
P0.2
P0.4
P0.6
P1.0
P1.2
P1.4
P1.6
VDD/DC+
R
R
VDD/DC+
R
R
CPnOUT
R
½ x VDD/DC+
(1/3 or 2/3) x VD D /DC+
CPnOUT
Rsense
Only enabled when
Capacitive Touch
Sense Com pare is
selected o n CP n+
Inpu t MUX .
CPnOUT
Rsense
GND
Capacitive
Touch
Sense
Compare
Only enabled when
Capacitive Touch
Sense Com pare is
selected on C Pn-
Inp ut MUX .
C8051F91x-C8051F90x
96 Rev. 1.1
SFR Page = 0x0; SFR Address = 0x9F
SFR Definition 7.5. CPT0MX: Comparator0 Input Channel Select
Bit76543210
Name CMX0N[3:0] CMX0P[3:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 11111111
Bit Name Function
7:4 CMX0N Comparator0 Negative Input Selection.
Selects the negative input channel for Comparator0.
0000: P0.1 1000: Reserved
0001: P0.3 1001: Reserved
0010: P0.5 1010: Reserved
0011: P0.7 1011: Reserved
0100: P1.1 1100: Capacitive Touch Sense
Compare
0101: P1.3 1101: VDD/DC+ divided by 2
0110: P1.5 1110: Digital Supply Voltage
0111: Reserved 1111: Ground
3:0 CMX0P Comparator0 Positive Input Selection.
Selects the positive input channel for Comparator0.
0000: P0.0 1000: Reserved
0001: P0.2 1001: Reserved
0010: P0.4 1010: Reserved
0011: P0.6 1011: Reserved
0100: P1.0 1100: Capacitive Touch Sense
Compare
0101: P1.2 1101: VDD/DC+ divided by 2
0110: P1.4 1110: VBAT Supply Voltage
0111: P1.6 1111: VDD/DC+ Supply Voltage
Rev. 1.1 97
C8051F91x-C8051F90x
SFR Page = 0x0; SFR Address = 0x9E
SFR Definition 7.6. CPT1MX: Comparator1 Input Channel Select
Bit76543210
Name CMX1N[3:0] CMX1P[3:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 11111111
Bit Name Function
7:4 CMX1N Comparator1 Negative Input Selection.
Selects the negative input channel for Comparator1.
0000: P0.1 1000: Reserved
0001: P0.3 1001: Reserved
0010: P0.5 1010: Reserved
0011: P0.7 1011: Reserved
0100: P1.1 1100: Capacitive Touch Sense
Compare
0101: P1.3 1101: VDD/DC+ divided by 2
0110: P1.5 1110: Digital Supply Voltage
0111: Reserved 1111: Ground
3:0 CMX1P Comparator1 Positive Input Selection.
Selects the positive input channel for Comparator1.
0000: P0.0 1000: Reserved
0001: P0.2 1001: Reserved
0010: P0.4 1010: Reserved
0011: P0.6 1011: Reserved
0100: P1.0 1100: Capacitive Touch Sense
Compare
0101: P1.2 1101: VDD/DC+ divided by 2
0110: P1.4 1110: VBAT Supply Voltage
0111: P1.6 1111: VDD/DC+ Supply Voltage
C8051F91x-C8051F90x
98 Rev. 1.1
8. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop
software. The MCU family has a su pe rs et of all the peripherals included with a standard 8051. The CIP-51
also includes on-chip debug hardware (see description in Section 27), and interfaces directly with the
analog and d igital subsystems pro viding a comple te data acquisition or control-system solution in a single
integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 8.1 for a block diagram).
The CIP-51 includes the following features:
8.1. Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the
standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24
system clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the
CIP-51 core executes 70% of its instructions in one or two system clock cycles, w ith no instructions taking
more than eight system clock cycles.
Figure 8.1. CIP-51 Block Diagram
- Fully Compatible with MCS-51 Instruction
Set
- 25 MIPS Peak Throughput with 25 MHz
Clock
- 0 to 25 MHz Clock Frequency
- Extended Interrupt Handler
- Reset Input
- Power Management Modes
- On-chip Debug Logic
- Program and Data Memory Security
DATA BUS
TMP1 TMP2
PRGM. ADDRESS REG.
PC INCREMENTER
ALU
PSW
DATA BUS
DATA BUS
MEMORY
INTERFACE
MEM_ADDRESS
D8
PIPELINE
BUFFER
DATA POINTER
INTERRUPT
INTERFACE
SYSTEM_IRQs
EMULATION_IRQ
MEM_CONTROL
CONTROL
LOGIC
A16
PROGRAM COUNTER (PC)
STOP
CLOCK
RESET
IDLE POWER CONTROL
REGISTER
DATA BUS
SFR
BUS
INTERFACE
SFR_ADDRESS
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
D8
D8
B REGISTER
D8
D8
ACCUMULATOR
D8
D8
D8
D8
D8
D8
D8
D8
MEM_WRITE_DATA
MEM_READ_DATA
D8
SRAM
ADDRESS
REGISTER SRAM
D8
STACK POINTER
D8
Rev. 1.1 99
C8051F91x-C8051F90x
With the CIP-51's maximum system clock at 25 MHz, it has a pea k throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each
execution time.
8.2. Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2).
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and
memory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers,
or other on-chip resources. C2 details can be found in Section “27. C2 Interface” on page 312.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs
provides an integrated development environment (IDE) including editor, debugger and programmer. The
IDE's debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient
in-system device programming and debugging. Third party macro assemblers and C compilers are also
available.
8.3. Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™
instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-
51 instructions are the binary an d functional eq uivalent of their MCS-51™ cou nterpa rts, includ ing opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the
standard 8051.
8.3.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to com plete when the branch is not taken a s opposed to wh en the branch is taken. Table 8.1 is the
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
Clocks to Execute 1 2 2/3 33/4 44/5 5 8
Number of Instructions 26 50 514 73121
C8051F91x-C8051F90x
100 Rev. 1.1
Table 8.1. CIP-51 Instruction Set Summary
Mnemonic Description Bytes Clock
Cycles
Arithmetic Operations
ADD A, Rn Add register to A 1 1
ADD A, direct Add direct byte to A 2 2
ADD A, @Ri Add indirect RAM to A 1 2
ADD A, #data Add immediate to A 2 2
ADDC A, Rn Add register to A with carry 1 1
ADDC A, direct Add direct byte to A with carry 2 2
ADDC A, @Ri Add indirect RAM to A with carry 1 2
ADDC A, #data Add immediate to A with carry 2 2
SUBB A, Rn Subtract register from A with borrow 1 1
SUBB A, direct Subtract direct byte from A with borrow 2 2
SUBB A, @Ri Subtract indi rect RAM fro m A with bo rr ow 1 2
SUBB A, #data Subtract immediate from A with bo rr ow 2 2
INC A Increment A 1 1
INC Rn Increment register 1 1
INC direct Increment direct byte 2 2
INC @Ri Increment indirect RAM 1 2
DEC A Decrement A 1 1
DEC Rn Decrem e nt re gis te r 1 1
DEC direct Decrement direct byt e 2 2
DEC @Ri Decrement indirect RAM 1 2
INC DPTR Increment Data Pointer 1 1
MUL AB Multiply A and B 1 4
DIV AB Divide A by B 1 8
DA A Decimal adjust A 1 1
Logical Operations
ANL A, Rn AND Register to A 1 1
ANL A, direct AND direct byte to A 2 2
ANL A, @Ri AND indirect RAM to A 1 2
ANL A, #data AND immediate to A 2 2
ANL direct, A AND A to direct byte 2 2
ANL direct, #data AND immediate to direct byte 3 3
ORL A, Rn OR Register to A 1 1
ORL A, direct OR direct byte to A 2 2
ORL A, @Ri OR indirect RAM to A 1 2
ORL A, #data OR immediate to A 2 2
ORL direct, A OR A to direct byte 2 2
ORL direct, #d ata OR immediate to direct byte 3 3
XRL A, Rn Exclusive-OR Register to A 1 1
XRL A, direct Exclusive-OR direct byte to A 2 2
XRL A, @Ri Exclusive-OR indirect RAM to A 1 2
XRL A, #data Exclusive-OR immediate to A 2 2
XRL direct, A Exclusive-OR A to direct byte 2 2
XRL direct, #data Exclusive-OR immediate to direct byte 3 3
Rev. 1.1 101
C8051F91x-C8051F90x
CLR A Clear A 1 1
CPL A Complement A 1 1
RL A Rotate A left 1 1
RLC A Rotate A left through Carry 1 1
RR A Rotate A right 1 1
RRC A Rotate A right through Carry 1 1
SWAP A Swap nibbles of A 1 1
Data Transfer
MOV A, Rn Move Register to A 1 1
MOV A, direct Move direct byte to A 2 2
MOV A, @Ri Move indirect RAM to A 1 2
MOV A, #data Move immediate to A 2 2
MOV Rn, A Move A to Register 1 1
MOV Rn, direct Move direct byte to Register 2 2
MOV Rn, #data Move immediate to Register 2 2
MOV direct, A Move A to direct byte 2 2
MOV direct, Rn Move Register to direct byte 2 2
MOV direct, direct Move direct byte to direct byte 3 3
MOV direct, @Ri Move indirect RAM to direct byte 2 2
MOV direct, #data Move immediate to direct byte 3 3
MOV @Ri, A Move A to indirect RAM 1 2
MOV @Ri, direct Move direct byte to indirect RAM 2 2
MOV @Ri, #data Move immediate to indirect RAM 2 2
MOV DPTR, #data16 Load DPTR with 16-bit constant 3 3
MOVC A, @A+DPTR Move code byte relative DPTR to A 1 3
MOVC A, @A+PC Move code byte relative PC to A 1 3
MOVX A, @Ri Move external data (8-bit address) to A 1 3
MOVX @Ri, A Move A to external da ta (8-bit address) 1 3
MOVX A, @DPTR Move external data (16-bit address) to A 1 3
MOVX @DPTR, A Move A to external data (16-bit address) 1 3
PUSH direct Push direct byte onto stack 2 2
POP direct Pop direct byte from stack 2 2
XCH A, Rn Exchange Register with A 1 1
XCH A, direct Exchange direct byte with A 2 2
XCH A, @Ri Exchange indirect RAM with A 1 2
XCHD A, @Ri Exchange low nibble of indirect RAM with A 1 2
Boolean Manipulation
CLR C Clear Carry 1 1
CLR bit Clear direct bit 2 2
SETB C Set Carry 1 1
SETB bit Set direct bit 2 2
CPL C Complement Carry 1 1
CPL bit Complement direct bit 2 2
ANL C, bit AND direct bit to Carry 2 2
Table 8.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
C8051F91x-C8051F90x
102 Rev. 1.1
ANL C, /bit AND complement of dire ct bit to Carry 2 2
ORL C, bit OR direct bit to carry 2 2
ORL C, /bit OR complement of direct bit to Carry 2 2
MOV C, bit Move direct bit to Carry 2 2
MOV bit, C Move Carry to dir ect bit 2 2
JC rel Jump if Carry is set 22/3
JNC rel Jump if Carry is not set 22/3
JB bit, rel Jump if direct bit is set 33/4
JNB bit, rel Jump if direct bit is not set 33/4
JBC bit, rel Jump if direct bit is set and clear bit 33/4
Program Branch ing
ACALL addr11 Absolute subroutine call 2 3
LCALL addr16 Long subroutine call 3 4
RET Return from subroutine 1 5
RETI Return from interrupt 1 5
AJMP addr11 Absolute jump 2 3
LJMP addr16 Long jump 3 4
SJMP rel Short jump (relative address) 2 3
JMP @A+DPTR Jump indirect relative to DPTR 1 3
JZ rel Jump if A equals zero 22/3
JNZ rel Jump if A does not equal zero 22/3
CJNE A, direct, rel Compare direct byte to A and jump if not equal 33/4
CJNE A, #data, rel Compare immediate to A and jump if not equal 33/4
CJNE Rn, #data, rel Compare immediate to Register and jump if not
equal 33/4
CJNE @Ri, #data, rel Compare immediate to indirect a nd jump if not
equal 34/5
DJNZ Rn, rel Decrement Register and jump if not zero 22/3
DJNZ direct, rel Decrement direct byt e and jum p if not zer o 33/4
NOP No operation 1 1
Table 8.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
Rev. 1.1 103
C8051F91x-C8051F90x
Notes on Registers, Oper ands and Addressing Modes:
Rn—Register R0–R7 of the currently selected register bank.
@Ri—Data RAM location addressed indirectly through R0 or R1.
rel—8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct—8-bit internal data location’s address. This co uld be a dir ec t-access Data RAM location
(0x00–0x7F) or an SFR (0x80–0xFF).
#data—8-bit constant
#data16—16-bit constant
bit—Direct-accessed bit in Data RAM or SFR
addr11—11-bit destination address used by ACALL and AJMP. The destination must be within the
same 2 kB page of program mem ory as the first byte of the following instruction.
addr16—16-bit destin ation address used by LCALL a nd LJMP. The destination may be anywhere within
the 8 kB program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
C8051F91x-C8051F90x
104 Rev. 1.1
8.4. CIP-51 Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP- 51 System Controller. Reserved bits
should not be set to logic l. Future product version s may use these bits to implement new feature s in which
case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of
the remaining SFRs are included in the sections of the data sheet associated with their corresponding
system function.
SFR Page = All Pages; SFR Address = 0x82
SFR Page = All Pages; SFR Address = 0x83
SFR Definition 8.1. DPL: Data Pointer Low Byte
Bit76543210
Name DPL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 DPL[7:0] Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indi-
rectly addressed Flash memory or XRAM.
SFR Definition 8.2. DPH: Data Pointer High Byte
Bit76543210
Name DPH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 DPH[7:0] Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indi-
rectly addressed Flash memory or XRAM.
Rev. 1.1 105
C8051F91x-C8051F90x
SFR Page = All Pages; SFR Address = 0x81
SFR Page = All Pages; SFR Address = 0xE0; Bit-Addressable
SFR Page = All Pages; SFR Addr es s = 0x F0 ; Bit- Addre ssable
SFR Definition 8.3. SP: Stack Pointer
Bit76543210
Name SP[7:0]
Type R/W
Reset 00000111
Bit Name Function
7:0 SP[7:0] Stack Pointer.
The S t ack Pointer holds the location of the top of the st ack. The stack pointer is incre-
mented before every PUSH operation. The SP register defaults to 0x07 after reset.
SFR Definition 8.4. ACC: Accumulator
Bit76543210
Name ACC[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 ACC[7:0] Accumulator.
This register is the accumulator for arithmetic operations.
SFR Definition 8.5. B: B Register
Bit76543210
Name B[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 B[7:0] B Register.
This register serves as a second accumulator for certain arithmetic operations.
C8051F91x-C8051F90x
106 Rev. 1.1
SFR Page = All Pages; SFR Address = 0xD0; Bit-Addressable
SFR Definition 8.6. PSW: Program Status Word
Bit76543210
Name CY AC F0 RS[1:0] OV F1 PARITY
Type R/W R/W R/W R/W R/W R/W R
Reset 00000000
Bit Name Function
7CY Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a bor-
row (subtraction). It is cleared to logic 0 by all other arithmetic operations.
6AC Auxiliary Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a
borrow from (subtraction) th e high order nibble. It is cleared to logic 0 by all other arith-
metic opera tion s.
5F0 User Flag 0.
This is a bit-addres sable, general purpose flag for use under software control.
4:3 RS[1:0] Register Bank Select.
These bits select which register bank is used during register accesses.
00: Bank 0, Addresses 0x00-0x07
01: Bank 1, Addresses 0x08-0x0F
10: Bank 2, Addresses 0x10-0x17
11: Bank 3, Addresses 0x18-0x1F
2OV Overflow Flag.
This bit is set to 1 under the following circumstances:
• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
• A MUL instruction results in an overflow (result is greater than 255).
• A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all
other cases.
1F1 User Flag 1.
This is a bit-addres sable, general purpose flag for use under software control.
0PARITY Parity Flag.
This bit is set to logic 1 if the sum of the eigh t bits in the accumulator is odd and cleared
if the sum is even.
Rev. 1.1 107
C8051F91x-C8051F90x
9. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization of the
C8051F91x-C8051F90x device family is shown in Figure 9.1
Figure 9.1. C8051F91x-C8051F90x Memory Map
PROGRAM/DAT A MEMORY
(FLASH)
(Direct and Indirec t
Addressing)
Upper 128 RAM
(Indirect Addressing Only)
Special Function
Registers
(Direct Addressing Only)
DATA MEMORY
(RAM)
General Purpose
Registers
Bit Addressable Lower 128 RAM
(Direct and Indirect
Addressing)
INTERNAL DATA ADDRESS SPACE
EXTERNAL DATA ADDRESS SPACE
F
0
0x0000
0x3FFF RESERVED
0x3C00
0x3BFF
Scrachpad Memory
(DATA only)
0x01FF
0x0000
C8051F912/11
8KB FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
0x1FFF
Scrachpad Memory
(DATA only)
0x01FF
0x0000
C8051F902/1
XRAM - 512 Bytes
(accessable using MO VX
instruction)
0x0000
0x01FF
Unpopulated Address Space
0x0200
0x1FFF C8051F912/11/02/01
16KB FLASH
(In-System
Programmable in 512
Byte Sectors)
Note: Code compatible devic es with up to 64 kB Flash and 4 kB RAM are available as the C8051F93x-92x fami ly.
C8051F91x-C8051F90x
108 Rev. 1.1
9.1. Program Memory
The CIP-51 core has a 64 kB program memory space. The C8051F91x-C8051F90x devices implement
16 kB (C8051F912/1) or 8 kB (C8051F902/1) of this program memory space as in-system, re-
programmable Flash memory, organized in a contiguous block from addresses 0x0000 to 0x3BFF
(C8051F912/1) or 0x1FFF (C8051F902/1). The last byte of this contiguous block of addresses serves as
the security lock byte for the device. Any addresses above the lock byte are reserved.
Figure 9.2. Flash Program Memory Map
9.1.1. MOVX Instruction and Program Memory
The MOVX instruction in an 8051 device is typically used to access external data memory. On the
C8051F91x-C8051F90x devices, the MOVX instruction is normally used to read and write on-chip XRAM,
but can be re-configured to write and erase on-chip Flash memory space. MOVC instructions are always
used to read Fla sh memory, while M OVX write instructions are used to erase and writ e Flash. This Flash
access feature provides a mechanism for the C8051F91x-C8051F90x to update program code and use
the program memory space for non-volatile data storage. Refer to Section “13. Flash Memory” on
page 132 for further details.
9.2. Data Memory
The C8051F91x-C8051F90x device family include 768 bytes of RAM data memory. 256 bytes of this
memory is mapped into the internal RAM space of the 8051. The remainder of this memory is on-chip
“external” memory. The data memory map is shown in Figure 9.1 for reference.
9.2.1. Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The
lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either
direct or indirect addressing may be used to access the lower 128 bytes of data memory. Loca tions 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or
as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory ar e acce ssible on ly by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
Lock Byte
0x0000
FLASH memory organized in
512-byte pages
Flash Memory Space
Lock Byte Page
Lock Byte
Flash Memory Space
Lock Byte Page
Reserved Area
0x0000
0x3BFE
0x3C00
0x3A00
0xFFFF
0x3BFF
0x1FFF
0x1FFE
0x1E00
0x1BFF
0x39FF
Scratchpad
(Data Only)
Unpopulated
Address Space
(Reserved)
0xFFFF
0x8000
0x0000
0x01FF
C8051F912/1
(SFLE=0) C8051F902/1
(SFLE=0)
C8051F912/1
C8051F902/1
(SFLE=1)
Rev. 1.1 109
C8051F91x-C8051F90x
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F acce ss the
upper 128 bytes of data memory. Figure 9.1 illustrates the data memory organization of the C8051F91x-
C8051F90x.
9.2.1.1. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of
general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7.
Only one of these banks may be enabled at a time. Two bits in th e progr am st atus word , RS0 (PSW.3) and
RS1 (PSW.4), select the active register bank (see description of the PSW in SFR Definition 8.6). This
allows fast context switching when entering subroutines and interrupt service routines. Indirect addressing
modes use registers R0 an d R1 as index registers.
9.2.1.2. Bit Addressable Locations
In addition to direct access to d ata memory organized as bytes, the sixtee n data memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 o f the byte at 0x2 0 has bit addre ss 0x00 while bit 7 of the byte at 0x 20 has bit addr ess
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished fro m a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or
destination).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
C8051F91x-C8051F90x
110 Rev. 1.1
9.2.1.3. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is
designated using the Stack Pointer (SP) SFR. The SP will point to the last location used. The next value
pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to
location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the
first regist er (R0) of re gister bank 1. Thus, if more than one register bank is to be used, the SP should be
initialized to a location in the data memory not being used for dat a storage . Th e stack depth can extend up
to 256 bytes.
9.2.2. External RAM
There are 512 bytes of on-chip RAM mapped into the external data memory space. All of these address
locations may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or
using MOVX indirect addressing mode (such as @R1) in combination with the EMI0CN register.
Rev. 1.1 111
C8051F91x-C8051F90x
10. On-Chip XRAM
The C8051F91x-C8051F90x MCUs include on-chip RAM mapped into the external data memory space
(XRAM). The external memory space may be accessed using the external mo ve instruction (MOVX) with
the target address specified in either the data pointer (DPTR), or with the target address low byte in R0 or
R1 and the t arget addre ss high byte in the Extern al Memo ry Interface Contr ol Re gister (EMI0CN, shown in
SFR Definition 10.1).
When using the MOVX instruction to access on-chip RAM, no additional initialization is required and the
MOVX instruction execution time is as specified in the CIP-51 chapter.
Important Note: MOVX write ope ratio ns can be conf igured to t arget Flas h memory, instead of XRAM. See
Section “13. Flash Memory” on page 132 for more details. The MOVX instruction accesses XRAM by
default.
10.1. Accessing XRAM
The XRAM memory space is accessed using the MOVX instruction. The MOVX instruction has two forms,
both of which use an indirect addressing method. The first method uses the Data Pointer, DPTR, a 16-bit
register which contains the effective address of the XRAM location to be read from or written to. The
second method uses R0 or R1 in combination with the EMI0CN register to generate the effective XRAM
address. Examples of both of these methods are given below.
10.1.1. 16-Bit MOVX Example
The 16-bit form of the MOVX instruction accesses the memory location pointed to by the contents of the
DPTR register. The following series of instructions reads the value of the byte at address 0x1234 into the
accumulator A:
MOV DPTR, #1234h ; load DPTR with 16-bit address to read (0x1234)
MOVX A, @DPTR ; load contents of 0x1234 into accumulator A
The above example uses the 16-bit immediate MOV instruction to set the contents of DPTR. Alternately,
the DPTR can be accessed thro ugh th e SFR regi ster s DPH, which contains the upper 8-bits of DPTR, and
DPL, which contains the lower 8-bits of DPTR.
10.1.2. 8-Bit MOVX Example
The 8-bit form of the MOVX instruction uses the content s of the EMI0CN SF R to dete rmine the upp er 8-bit s
of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of the
effective address to be accessed. The following series of instructions read the contents of the byte at
address 0x1234 into the accumulator A.
MOV EMI0CN, #12h ; load high byte of address into EMI0CN
MOV R0, #34h ; load low byte of address into R0 (or R1)
MOVX a, @R0 ; load contents of 0x1234 into accumulator A
C8051F91x-C8051F90x
112 Rev. 1.1
10.2. Special Function Registers
The special function register used for configuring XRAM access is EMI0CN.
SFR Page = 0x0; SFR Address = 0xAA
SFR Definition 10.1. EMI0CN: External Memory Interface Control
Bit76543210
Name PGSEL
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:1 Unused Unused.
Read = 0000000b; Write = Don’t Care
0PGSEL XRAM Page Select.
The EMI0CN register provides the high byte of the 16-bit external data memory
address when using an 8-bit MOVX command, effectively selecting a 256-byte page
of RAM. Since the upper (unused) bits of the register are always zero, the PGSEL
determines which page of XRAM is accessed.
For Example:
If EMI0CN = 0x01, addresses 0x0100 through 0x01FF will be accessed.
If EMI0CN = 0x00, addresses 0x0000 through 0x00FF will be accessed.
Rev. 1.1 113
C8051F91x-C8051F90x
11. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the C8051F91x-C8051F90x's resources and
peripherals. The CIP- 51 controller core duplicates the SFRs found in a typical 8051 impl ement ation as well
as implementing additional SFRs used to configure and access the sub-systems unique to the
C8051F91x-C8051F90x. This allows the addition of new functionality while retaining compatibility with the
MCS-51™ instruction set. Table 11.1 and Table 11.2 list the SFRs implemented in the C8051F91x-
C8051F90x device family.
The SFR regist ers are access ed anytime the direct a ddressing mode is used to access me mory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g., P0, TCON, SCON 0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 11.3, for a detailed descr iption of each register.
Table 11.1. Special Function Register (SFR) Memory Map (Page 0x0)
F8 SPI0CN PCA0L PCA0H PCA0CPL0 PCA0CPH0 PCA0CPL4 PCA0CPH4 VDM0CN
F0 BP0MDIN P1MDIN SMB0ADR SMB0ADM EIP1 EIP2
E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3 RSTSRC
E0 ACC XBR0 XBR1 XBR2 IT01CF FLWR EIE1 EIE2
D8 PCA0CN PCA0MD PCA0CPM0PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4 PCA0PWM
D0 PSW REF0CN PCA0CPL5 PCA0CPH5 P0SKIP P1SKIP P0MAT
C8 TMR2CN REG0CN TMR2RLL TMR2RLH TMR2L TMR2H PCA0CPM5 P1MAT
C0 SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH ADC0LTL ADC0LTH P0MASK
B8 IP IREF0CN ADC0AC ADC0MX ADC0CF ADC0L ADC0H P1MASK
B0 SPI1CN OSCXCN OSCICN OSCICL PMU0CF FLSCL FLKEY
A8 IE CLKSEL EMI0CN RTC0ADR RTC0DAT RTC0KEY
A0 P2 SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT P2MDOUT SFRPAGE
98 SCON0 SBUF0 CPT1CN CPT0CN CPT1MD CPT0MD CPT1MX CPT0MX
90 P1 TMR3CN TMR3RLL TMR3RLH TMR3L TMR3H DC0CF DC0CN
88 TCON TMOD TL0 TL1 TH0 TH1 CKCON PSCTL
80 P0 SP DPL DPH SPI1CFG SPI1CKR SPI1DAT PCON
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
(bit addressable)
C8051F91x-C8051F90x
114 Rev. 1.1
11.1. SFR Paging
To accommodate more than 128 SFRs in the 0x80 to 0xFF address space, SFR paging has been
implemented. By default, all SFR accesses target SFR Page 0x0 to allow access to the registers listed in
Table 11.1. During device initialization, some SFRs located on SFR Page 0xF may need to be accessed.
Table 11.2 lists the SFRs accessible from SFR Page 0x0F. Some SFRs are accessible from both pages,
including the SFRPAGE register. SFRs only accessible from Page 0xF are in bold. SFRs only available on
the ‘F912 and ‘F90 2 de vice s ar e in blue.
The following procedure should be used when accessing SFRs on Page 0xF:
1. Save the current interrupt state (EA_save = EA).
2. Disable Interrupts (EA = 0).
3. Set SFRPAGE = 0xF.
4. Access the SFRs located on SFR Page 0xF.
5. Set SFRPAGE = 0x0.
6. Restore interrupt state (EA = EA_s ave ) .
Table 11.2. Special Function Register (SFR) Memory Map (Page 0xF)
F8
F0 BEIP1 EIP2
E8
E0 ACC FLWR EIE1 EIE2
D8
D0 PSW
C8
C0
B8 IREF0CF ADC0PWR ADC0TK
B0 PMU0MD
A8 IE CLKSEL
A0 P2 P0DRV P1DRV P2DRV SFRPAGE
98
90 P1 CRC0DAT CRC0CN CRC0IN DC0MD CRC0FLIP CRC0AUTO CRC0CNT
88
80 P0 SP DPL DPH TOFFL TOFFH PCON
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
(bit addressable)
Rev. 1.1 115
C8051F91x-C8051F90x
SFR Page = All Pages; SFR Address = 0xA7
SFR Definition 11.1. SFR Page: SFR Page
Bit76543210
Name SFRPAGE[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 SFRPAGE[7:0] SFR Page.
Specifies the SFR Page used when reading, writing, or modifying special function
registers.
Table 11.3. Special Function Registers
SFRs are listed in alphabetical o rder . All undefined SFR loca tions are reserved. SFRs highlighted
in blue are only available on ‘F912 and ‘F902 devices.
Register Address SFR Page Description Page
ACC 0xE0 All Accumulator 105
ADC0AC 0xBA 0x0 ADC0 Accumulator Configuration 71
ADC0CF 0xBC 0x0 ADC0 Configuration 70
ADC0CN 0xE8 0x0 ADC0 Control 69
ADC0GTH 0xC4 0x0 ADC0 Greater-Than Compare High 75
ADC0GTL 0xC3 0x0 ADC0 Greater-Than Compare Low 75
ADC0H 0xBE 0x0 ADC0 High 74
ADC0L 0xBD 0x0 ADC0 Low 74
ADC0LTH 0xC6 0x0 ADC0 Less-Than Compare Word High 76
ADC0LTL 0xC5 0x0 ADC0 Less-Than Compare Word Low 76
ADC0MX 0xBB 0x0 AMUX0 Channel Select 79
ADC0PWR 0xBA 0xF ADC0 Burst Mode Power-Up Time 72
ADC0TK 0xBD 0xF AD C0 Tracking Control 73
B 0xF0 All B Register 105
CKCON 0x8E 0x0 Clock Control 271
CLKSEL 0xA9 All Clock Select 185
CPT0CN 0x9B 0x0 Comparator0 Control 92
CPT0MD 0x9D 0x0 Comparator0 Mode Selection 92
CPT0MX 0x9F 0x0 Comparator0 Mux Selection 96
CPT1CN 0x9A 0x0 Comparator1 Control 93
C8051F91x-C8051F90x
116 Rev. 1.1
CPT1MD 0x9C 0x0 Comparator1 Mode Selection 94
CPT1MX 0x9E 0x0 Comparator1 Mux Selection 97
CRC0AUTO 0x96 0xF CRC0 Automatic Control 157
CRC0CN 0x92 0xF CRC0 Control 155
CRC0CNT 0x97 0xF CRC0 Automatic Flash Sector Count 158
CRC0DAT 0x91 0xF CRC0 Data 156
CRC0FLIP 0x95 0xF CRC0 Flip 159
CRC0IN 0x93 0xF CRC0 Input 156
DC0CF 0x96 0x0 DC 0 (DC-DC Converter) Configuration 168
DC0CN 0x97 0x0 DC0 (DC-DC Converter) Control 167
DC0MD 0x94 0xF DC0 (DC-DC Converte r) Mode 169
DPH 0x83 All Data Pointer High 104
DPL 0x82 All Data Pointer Low 104
EIE1 0xE6 All Extended Interrupt Enable 1 126
EIE2 0xE7 All Extended Interrupt Enable 2 128
EIP1 0xF6 0x0 Extended Interrupt Priority 1 127
EIP2 0xF7 0x0 Extended Interrupt Priority 2 129
EMI0CN 0xAA 0x0 EMIF Control 112
FLKEY 0xB7 0x0 Flash Lock And Key 141
FLSCL 0xB6 0x0 Flash Scale 141
IE 0xA8 All Interrupt Enable 124
IP 0xB8 0x0 Interrupt Priority 125
IREF0CN 0xB9 0x0 Current Reference IREF Control 86
IREF0CF 0xB9 0xF Current Reference IREF Configuration 87
IT01CF 0xE4 0x0 INT0/INT1 Configuration 131
OSCICL 0xB3 0x0 Internal Oscillator Calibration 186
OSCICN 0xB2 0x0 Internal Oscillator Control 186
OSCXCN 0xB1 0x0 External Oscillator Control 187
P0 0x80 All Port 0 Latch 218
P0DRV 0xA4 0xF Port 0 Drive Strength 220
P0MASK 0xC7 0x0 Port 0 Mask 215
P0MAT 0xD7 0x0 Port 0 Match 215
P0MDIN 0xF1 0x0 Port 0 Input Mode Configuration 219
Table 11.3. Special Function Registers (Continued)
SFRs are listed in alphabetical o rder . All undefined SFR loca tions are reserved. SFRs highlighted
in blue are only available on ‘F912 and ‘F902 devices.
Register Address SFR Page Description Page
Rev. 1.1 117
C8051F91x-C8051F90x
P0MDOUT 0xA4 0x0 Port 0 Output Mode Configuration 219
P0SKIP 0xD4 0x0 Port 0 Skip 218
P1 0x90 All Port 1 Latch 221
P1DRV 0xA5 0xF Port 1 Drive Strength 223
P1MASK 0xBF 0x0 Port 1 Mask 216
P1MAT 0xCF 0x0 Port 1 Match 216
P1MDIN 0xF2 0x0 Port 1 Input Mode Configuration 222
P1MDOUT 0xA5 0x0 Port 1 Output Mode Configuration 222
P1SKIP 0xD5 0x0 Port 1 Skip 221
P2 0xA0 All Port 2 Latch 223
P2DRV 0xA6 0xF Port 2 Drive Strength 224
P2MDOUT 0xA6 0x0 Port 2 Output Mode Configuration 224
PCA0CN 0xD8 0x0 PCA0 Control 306
PCA0CPH0 0xFC 0x0 PCA0 Capture 0 High 311
PCA0CPH1 0xEA 0x0 PCA0 Capture 1 High 311
PCA0CPH2 0xEC 0x0 PCA0 Capture 2 High 311
PCA0CPH3 0xEE 0x0 PCA0 Capture 3 High 311
PCA0CPH4 0xFE 0x0 PCA0 Capture 4 High 311
PCA0CPH5 0xD3 0x0 PCA0 Capture 5 High 311
PCA0CPL0 0xFB 0x0 PCA0 Capture 0 Low 311
PCA0CPL1 0xE9 0x0 PCA0 Capture 1 Low 311
PCA0CPL2 0xEB 0x0 PCA0 Capture 2 Low 311
PCA0CPL3 0xED 0x0 PCA0 Capture 3 Low 311
PCA0CPL4 0xFD 0x0 PCA0 Capture 4 Low 311
PCA0CPL5 0xD2 0x0 PCA0 Capture 5 Low 311
PCA0CPM0 0xDA 0x0 PCA0 Module 0 Mode Register 309
PCA0CPM1 0xDB 0x0 PCA0 Module 1 Mode Register 309
PCA0CPM2 0xDC 0x0 PCA0 Module 2 Mode Register 309
PCA0CPM3 0xDD 0x0 PCA0 Module 3 Mode Register 309
PCA0CPM4 0xDE 0x0 PCA0 Module 4 Mode Register 309
PCA0CPM5 0xCE 0x0 PCA0 Module 5 Mode Register 309
PCA0H 0xFA 0x0 PCA0 Counter High 310
PCA0L 0xF9 0x0 PCA0 Counter Low 310
Table 11.3. Special Function Registers (Continued)
SFRs are listed in alphabetical o rder . All undefined SFR loca tions are reserved. SFRs highlighted
in blue are only available on ‘F912 and ‘F902 devices.
Register Address SFR Page Description Page
C8051F91x-C8051F90x
118 Rev. 1.1
PCA0MD 0xD9 0x0 PCA0 Mode 307
PCA0PWM 0xDF 0x0 PCA0 PWM Configuration 308
PCON 0x87 0x0 Power Control 151
PMU0CF 0xB5 0x0 PMU0 Configuration 149
PMU0MD 0xB5 0xF PMU0 Mode 150
PSCTL 0x8F 0x0 Program Stor e R/W Co nt ro l 140
PSW 0xD0 All Program Status Word 106
REF0CN 0xD1 0x0 Voltage Reference Control 85
REG0CN 0xC9 0x0 Voltage Regulator (VREG0) Control 170
RSTSRC 0xEF 0x0 Reset Source Co nfig ura tio n/ Status 178
RTC0ADR 0xAC 0x0 RTC0 Address 193
RTC0DAT 0xAD 0x0 RTC0 Data 193
RTC0KEY 0xAE 0x0 RTC0 Key 192
SBUF0 0x99 0x0 UA RT0 Data Buffer 253
SCON0 0x98 0x0 UA RT0 Control 252
SFRPAGE 0xA7 All SFR Page 115
SMB0ADM 0xF5 0x0 SMBus Slave Address Mask 237
SMB0ADR 0xF4 0x0 SMBus Slave Address 237
SMB0CF 0xC1 0x0 SMBus Configuration 232
SMB0CN 0xC0 0x0 SMBus Control 234
SMB0DAT 0xC2 0x0 SMBus Data 238
SP 0x81 All Stack Pointer 105
SPI0CFG 0xA1 0x0 SPI0 Configuration 263
SPI0CKR 0xA2 0x0 SPI0 Clock Rate Control 265
SPI0CN 0xF8 0x0 SPI0 Control 264
SPI0DAT 0xA3 0x0 SPI0 Data 266
SPI1CFG 0x84 0x0 SPI1 Configuration 263
SPI1CKR 0x85 0x0 SPI1 Cloc k Rate Control 265
SPI1CN 0xB0 0x0 SPI1 Control 264
SPI1DAT 0x86 0x0 SPI1 Data 266
TCON 0x88 0x0 Timer/Counter Control 276
TH0 0x8C 0x0 Timer/Counter 0 High 279
TH1 0x8D 0x0 Timer/Counter 1 High 279
Table 11.3. Special Function Registers (Continued)
SFRs are listed in alphabetical o rder . All undefined SFR loca tions are reserved. SFRs highlighted
in blue are only available on ‘F912 and ‘F902 devices.
Register Address SFR Page Description Page
Rev. 1.1 119
C8051F91x-C8051F90x
TL0 0x8A 0x0 Timer/Counte r 0 Lo w 278
TL1 0x8B 0x0 Timer/Counte r 1 Lo w 278
TMOD 0x89 0x0 Timer/Counter Mode 277
TMR2CN 0xC8 0x0 Timer/Counter 2 Co nt ro l 283
TMR2H 0xCD 0x0 Timer/Counter 2 High 285
TMR2L 0xCC 0x0 Timer/Counter 2 Lo w 285
TMR2RLH 0xCB 0x0 Timer/Counter 2 Reload High 284
TMR2RLL 0xCA 0x0 Timer/Counter 2 Reload Low 284
TMR3CN 0x91 0x0 Timer/Counter 3 Control 289
TMR3H 0x95 0x0 Timer/Counter 3 High 291
TMR3L 0x94 0x0 Timer/Counter 3 Low 291
TMR3RLH 0x93 0x0 Timer/Counter 3 Reload High 290
TMR3RLL 0x92 0x0 Timer/Counter 3 Reload Low 290
TOFFH 0x86 0xF Temperature Offset High 82
TOFFL 0x85 0xF Temperature Offset Low 82
VDM0CN 0xFF 0x0 VDD Monitor Control 175
XBR0 0xE1 0x0 Port I/O Crossbar Control 0 212
XBR1 0xE2 0x0 Port I/O Crossbar Control 1 213
XBR2 0xE3 0x0 Port I/O Crossbar Control 2 214
Table 11.3. Special Function Registers (Continued)
SFRs are listed in alphabetical o rder . All undefined SFR loca tions are reserved. SFRs highlighted
in blue are only available on ‘F912 and ‘F902 devices.
Register Address SFR Page Description Page
C8051F91x-C8051F90x
120 Rev. 1.1
12. Interrupt Handler
The C8051F91x-C8051F90x microcontroller family includes an extended interrupt system supporting
multiple interrupt sources and two priority levels. The allocation of interrupt sources between on-chip
peripherals and external input pins varies according to the specific version of the device. Refer to
Table 12.1, “Interrupt Summary,” on page 122 for a detailed listing of all interrupt sources supported by the
device. Refer to the data sheet section associated with a particular on-chip peripheral for information
regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR or an
indirect register. When a peripheral or external source meets a valid interrupt condition, the associated
interrupt-pending flag is set to logic 1. If both global interrupts and the sp ecific interrupt source is enabled,
a CPU interrupt request is gen erated when the interrupt-pending flag is set.
As soon as execution of the current instruction is complete, the CPU generates an LCALL to a
predetermined addr ess to begin execution of an interr upt service routine (ISR). Each ISR must end with an
RETI instruction, which returns program execution to the next instruction that would have been executed if
the interrupt request had not occurred. If in terrupt s are no t enabled , the interrup t-pending flag is igno red by
the hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1
regardless of the interrupt's enable/disable state.)
Some interrupt-pending flags are automatically cleared by hardware when the CPU vectors to the ISR.
However, m ost are not clear ed by the hardware and must be clear ed by sof tware be fore retur ning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
12.1. Enabling Interrupt Sources
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in the Interrupt Enable and Extended Interrupt Enable SFRs. However, interrupts must first be
globally enabled by setting the EA bit (IE.7) to logic 1 before the individual interrupt enables are
recognized. Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt-
enable settings. Note that interrupts which occur when the EA bit is set to logic 0 will be held in a pending
state, and will not be serviced until the EA bit is set back to logic 1.
12.2. MCU Interrupt Sources and Vectors
The CPU services interrupts by generating an LCALL to a predetermined address (the interrupt vector
address) to begin execution of an interrupt service routine (ISR). The interrupt vector addresses
associated with each interrupt source are listed in Table 12.1 on page 122. Software should ensure that
the interrupt vector for each enabled interrupt source contains a valid interrupt service routine.
Software can simulate an interrupt by setting any interrupt-pe nding flag to logic 1. If interrupts are enabled
for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated
with the interrupt-pending flag.
Rev. 1.1 121
C8051F91x-C8051F90x
12.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low
priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt
cannot be preempted. If a high priority interrupt preempts a low priority interrupt, the low priority interrupt
will finish execution after the high priority interrupt completes. Each interrupt has an associated interrupt
priority bit in in the Interrupt Priority and Extended Interrupt Priority registers used to configure its priority
level. Low priority is the default.
If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. If both
interrupts have the same priority level, a fixed priority order is used to arbitrate. See Table 12.1 on
page 122 to determine the fixed priority order used to arbitrate between simultaneously recognized
interrupts.
12.4. Interrupt Latency
Interrupt response time depen ds on the state of the CPU when the interrupt occurs. Pending inter rupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 7
system clock cycles: 1 clock cycle to detect the interrupt, 1 clock cycle to execute a single instruction, and
5 clock cycles to complete the LCALL to the ISR. If an interrupt is pending when a RETI is executed, a
single instruction is executed before an LCALL is made to service the pending interrupt. Therefore, the
maximum response time for an interrupt (when no other interrupt is currently being serviced or the new
interrupt is of gre ater pr ior ity) o ccurs when the CPU is performi ng an RE TI instruction followed by a DIV as
the next instruction. In this case, the response time is 19 system clock cycles: 1 clock cycle to detect the
interrupt, 5 clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 5 clock
cycles to execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or hig her
priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and
following instruction.
C8051F91x-C8051F90x
122 Rev. 1.1
Table 12.1. Interrupt Summary
Interrupt Source Interrupt
Vector Priority
Order Pending Flag
Bit
addressable?
Cleared
by HW?
Enable Flag Priority
Control
Reset 0x0000 Top None N/A N/A Always
Enabled Always
Highest
External Interrupt 0 (INT0)0x0003 0IE 0 (TC ON.1) Y Y EX0 (IE.0) PX0 (IP.0)
Timer 0 Overflow 0x000B 1TF0 (TCON.5) Y Y ET0 (IE.1) PT0 (IP.1)
External Interrupt 1 (INT1)0x0013 2IE 1 (TC ON.3) Y Y EX1 (IE.2) PX1 (IP.2)
Timer 1 Overflow 0x001B 3TF1 (TCON.7) Y Y ET1 (IE.3) PT1 (IP.3)
UART0 0x0023 4RI0 (SCON0.0)
TI0 (SCON0.1) Y N ES0 (IE.4) PS0 (IP.4)
Timer 2 Overflow 0x002B 5TF2H (TMR2CN.7)
TF2L (TMR2CN.6) Y N ET2 (IE.5) PT2 (IP.5)
SPI0 0x0033 6
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
Y N ESPI0 (IE.6) PSPI0 (IP.6)
SMB0 0x003B 7SI (SMB0CN.0) Y N ESMB0
(EIE1.0) PSMB0
(EIP1.0)
SmaRTClock Alarm 0x0043 8ALRM (RTC0CN.2)2N N EARTC0
(EIE1.1) PARTC0
(EIP1.1)
ADC0 Window Comparator 0x004B 9AD0WINT (ADC0CN.3) Y N EWADC0
(EIE1.2) PWADC0
(EIP1.2)
ADC0 End of Conversi on 0x0053 10 AD0INT (ADC0STA.5) Y N EADC0
(EIE1.3) PADC0
(EIP1.3)
Programmable Counter
Array 0x005B 11 CF (PCA0CN.7)
CCFn (PCA0CN.n) Y N EPCA0
(EIE1.4) PPCA0
(EIP1.4)
Comparator0 0x0063 12 CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5) N N ECP0
(EIE1.5) PCP0
(EIP1.5)
Comparator1 0x006B 13 CP1FIF (CPT1CN.4)
CP1RIF (CPT1CN.5) N N ECP1
(EIE1.6) PCP1
(EIP1.6)
Timer 3 Overflow 0x0073 14 TF3H (TMR3CN.7)
TF3L (TMR3CN.6) N N ET3
(EIE1.7) PT3
(EIP1.7)
Supply Monitor Early
Warning 0x007B 15 VDDOK (VDM0CN.5)1
VBATOK (VDM0CN.4)1, 3 EWARN
(EIE2.0) PWARN
(EIP2.0)
Port Match 0x0083 16 None EMAT
(EIE2.1) PMAT
(EIP2.1)
SmaRTClock Oscillator Fail 0x008B 17 OSCFAIL (RTC0CN.5)2N N ERTC0F
(EIE2.2) PFRTC0F
(EIP2.2)
SPI1 0x0093 18
SPIF (SPI1CN.7)
WCOL (SPI1CN.6)
MODF (SPI1CN.5)
RXOVRN (SPI1CN.4)
N N ESPI1
(EIE2.3) PSPI1
(EIP2.3)
Notes:
1. Indicates a read-only inte rrupt pending flag. The interrupt enable may be used to preven t software from
vectoring to the associated interrupt service routine.
2. Indicates a register located in an indirect memory space.
3. 8Blue text Indicat es a bit only available on ‘F912 and ‘F902 devices.
Rev. 1.1 123
C8051F91x-C8051F90x
12.5. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described in the following
register descriptions. Refer to the data sheet section associated with a particular on-chip peripheral for
information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending
flag(s).
C8051F91x-C8051F90x
124 Rev. 1.1
SFR Page = All Pages; SFR Address = 0xA8; Bit-Addressable
SFR Definition 12.1. IE: Interrupt Enable
Bit76543210
Name EA ESPI0 ET2 ES0 ET1 EX1 ET0 EX0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7EA Enable All Interrupts.
Globally enables/disables all interrupts. It overrides individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
6ESPI0 Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit set s the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
5ET2 Enable Timer 2 Interrupt.
This bit set s the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
4ES0 Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UAR T0 interrupt.
3ET1 Enable Timer 1 Interrupt.
This bit set s the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
2EX1 Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the INT1 input.
1ET0 Enable Timer 0 Interrupt.
This bit set s the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
0EX0 Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the INT0 input.
Rev. 1.1 125
C8051F91x-C8051F90x
SFR Page = 0x0; SFR Address = 0xB8; Bit-Addressable
SFR Definition 12.2. IP: Interrupt Priority
Bit76543210
Name PSPI0 PT2 PS0 PT1 PX1 PT0 PX0
Type RR/W R/W R/W R/W R/W R/W R/W
Reset 10000000
Bit Name Function
7Unused Unused.
Read = 1b, Write = don't care.
6PSPI0 Serial Peripheral Interface (SPI0) Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
5PT2 Timer 2 Interrupt Priority Control.
This bit sets the priority of th e Timer 2 interrupt.
0: Timer 2 interrupt set to low priority level.
1: Timer 2 interrupt set to high priority level.
4PS0 UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupt set to low priority level.
1: UART0 interrupt se t to high priority level.
3PT1 Timer 1 Interrupt Priority Control.
This bit sets the priority of th e Timer 1 interrupt.
0: Timer 1 interrupt set to low priority level.
1: Timer 1 interrupt set to high priority level.
2PX1 External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
1PT0 Timer 0 Interrupt Priority Control.
This bit sets the priority of th e Timer 0 interrupt.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
0PX0 External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
C8051F91x-C8051F90x
126 Rev. 1.1
SFR Page = All Pages; SFR Address = 0xE6
SFR Definition 12.3. EIE1: Extended Interrupt Enable 1
Bit76543210
Name ET3 ECP1 ECP0 EPCA0 EADC0 EWADC0 ERTC0A ESMB0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7ET3 Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
6ECP1 Enable Comparator1 (CP1) Interrupt.
This bit sets the masking of the CP1 interrupt.
0: Disable CP1 interrupts.
1: Enable interrupt requests generated by the CP1RIF or CP1FIF flags.
5ECP0 Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags.
4EPCA0 Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts .
1: Enable interrupt requests ge nerated by PCA0.
3EADC0 Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
2EWADC0 Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
1ERTC0A Enable SmaRTClock Alarm Interrupts.
This bit sets the masking of the SmaRTClock Alarm interrupt.
0: Disable SmaRTClock Alarm interrupts.
1: Enable interrupt requests g enerated by a SmaRTClock Alarm .
0ESMB0 Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests ge nerated by SMB0.
Rev. 1.1 127
C8051F91x-C8051F90x
SFR Page = All Pages; SFR Address = 0xF6
SFR Definition 12.4. EIP1: Extended Interrupt Priority 1
Bit76543210
Name PT3 PCP1 PCP0 PPCA0 PADC0 PWADC0 PRTC0A PSMB0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7PT3 Timer 3 Interrupt Priority Control.
This bit sets the priority of the Timer 3 interrupt.
0: Timer 3 interrupts set to low priority level.
1: Timer 3 interrupts set to high priority level.
6PCP1 Comparator1 (CP1) Interrupt Priority Control.
This bit sets the priority of the CP1 interrupt.
0: CP1 interrupt set to low priority level.
1: CP1 interrupt set to high priority level.
5PCP0 Comparator0 (CP0) Interrupt Priority Control.
This bit sets the priority of the CP0 interrupt.
0: CP0 interrupt set to low priority level.
1: CP0 interrupt set to high priority level.
4PPCA0 Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
3PADC0 ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
2PWADC0 ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
1PRTC0A SmaRTClock Alarm Interrupt Priority Control.
This bit sets the priority of the SmaRTClock Alarm interrupt.
0: SmaRTClock Alarm interrupt set to low priority level.
1: SmaRTClock Alarm inter rupt set to high priority level.
0PSMB0 SMBus (SMB0) Interrupt Priority Control.
This bit sets the priority of the SMB0 inter rupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.
C8051F91x-C8051F90x
128 Rev. 1.1
SFR Page = All Pages;SFR Address = 0xE7
SFR Definition 12.5. EIE2: Extended Interrupt Enable 2
Bit76543210
Name ESPI1 ERTC0F EMAT EWARN
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:4 Unused Unused.
Read = 0000b. Write = Don’t care.
3ESPI1 Enable Serial Peripheral Interface (SPI1) Interrupt.
This bit sets the masking of the SPI1 interrupts.
0: Disable all SPI1 interrupts.
1: Enable interrupt requests generated by SPI1.
2ERTC0F Enable SmaRTClock Oscillator Fail Interrupt.
This bit sets the masking of the SmaRTClock Alarm interrupt.
0: Disable SmaRTClock Alarm interrupts.
1: Enable interrupt requests generated by SmaRTClock Alarm.
1 EMAT Enable Port Match Inter r upts.
This bit sets the masking of the Port Match Event interrupt.
0: Disable all Port Match interrupts.
1: Enable interrupt requests generated by a Port Match.
0EWARN Enable Supply Monitor Early Warning Interrupt.
This bit sets the masking of the Supply Monitor Early Warning interrupt.
0: Disable the Supply Monitor Early Warning interrupt.
1: Enable interrupt requests generated by the Supply Monitor(s). ‘F912 and ‘F902
devices can provide an early warning for both VBAT and the VDD/DC+ supply. All
other devices only provide an early warning for the VDD/DC+ supply.
Rev. 1.1 129
C8051F91x-C8051F90x
SFR Page = All Pages; SFR Address = 0xF7
SFR Definition 12.6. EIP2: Extended Interrupt Priority 2
Bit76543210
Name PSPI1 PRTC0F PMAT PWARN
Type RRRRR/WR/WR/WR/W
Reset 00000000
Bit Name Function
7:4 Unused Unused.
Read = 0000b. Write = Don’t care.
3PSPI1 Serial Peripheral Interface (SPI1) Interrupt Priority Control.
This bit set s the priority of the SPI1 interrupt.
0: SP1 interrupt set to low priority level.
1: SPI1 interrupt set to high priority level.
2PRTC0F SmaRTClock Oscillator Fail Interrupt Priority Control.
This bit sets the priority of the SmaRTClock Alarm interrupt.
0: SmaRTClock Alarm interrupt set to low priority level.
1: SmaRTClock Alarm interrupt set to high priority level.
1 PMAT Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match Event interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
0PWARN Supply Monitor Early Warning Interrupt Priority Control.
This bit sets the priority of the VDD/DC+ Supply Monitor Early Warning interrupt.
0: Supply Monitor Early Warning interrupt set to low priority level.
1: Supply Monitor Early Warning interrupt set to high priority level.
C8051F91x-C8051F90x
130 Rev. 1.1
12.6. External Interrupts INT0 and INT1
The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level
sensitive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active
high or active low; the IT0 and IT1 bits in TCON (Section “25.1. Timer 0 and Timer 1” on page 272) select
level or edge sensitive. The table below lists the possible configurations.
INT0 and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 12.7). Note
that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1
will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar. To assign a Port pin only to INT0 and/or INT1, configure the Crossbar to skip the selecte d pin(s).
This is accomplished by setting the associated bit in register XBR0 (see Section “21.3. Priority Crossbar
Decoder” on page 209 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the INT0 and INT1 external
interrupts, respectively. If an INT0 or INT1 external interrupt is configured as edge-sensitive, the
corresponding interrupt-pending flag is automatically cleared by the hardware when the CPU vector s to the
ISR. When configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active
as defined by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is
inactive. The external inte rr upt source m ust hold the inpu t active until the interrupt request is recognized. It
must then deactivate the interrupt request before execution of the ISR completes or another interrupt
request will be generated.
IT0 IN0PL INT0 Interrupt IT1 IN 1PL INT1 Interrupt
10
Active low, edge sensitive 10Active low, edge sensitive
11Active high, edge sensitive 11Active high, edge sensitive
00Active low, level sensitive 00Active low, level sensitive
01Active high, level sensitive 01Active high, level sensitive
Rev. 1.1 131
C8051F91x-C8051F90x
SFR Page = 0x0; SFR Address = 0xE4
SFR Definition 12.7. IT01CF: INT0/INT1 Configuration
Bit76543210
Name IN1PL IN1SL[2:0] IN0PL IN0SL[2:0]
Type R/W R/W R/W R/W
Reset 00000001
Bit Name Function
7IN1PL INT1 Polarity.
0: INT1 input is active low.
1: INT1 input is active high.
6:4 IN1SL[2:0] INT1 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT1. Note that this pin assignment is
independent of the Crossbar; INT1 will monitor the assigned Port pin without disturb-
ing the periph eral that has b een assigned the Port pi n via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
3IN0PL INT0 Polarity.
0: INT0 input is active low.
1: INT0 input is active high.
2:0 IN0SL[2:0] INT0 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT0. Note that this pin assignment is
independent of the Crossbar; INT0 will monitor the assigned Port pin without disturb-
ing the periph eral that has b een assigned the Port pi n via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
C8051F91x-C8051F90x
132 Rev. 1.1
13. Flash Memory
On-chip, re-programmable Flash memory is included for program code and non-vo latile data storag e. The
Flash memory can be programmed in-system through the C2 interface or by software using the MOVX
write instruction. Once cleared to logic 0, a Flash bit must be erased t o set it back to logic 1. Flash bytes
would typically be erased (set to 0xFF) before being reprogrammed. The write and erase operations are
automatically timed by hardware for proper execution; data polling to determine the end of the write/erase
operations is not required. Code execution is stalled during Flash write/erase operations. Refer to
Table 4.6 for complete Flash memory electrical characteristics.
13.1. Programming The Flash Memory
The simplest means of programming the Flash memory is through the C2 interface using programming
tools provided by Silicon Laboratories or a third party vendor. This is the only means for programming a
non-initialized device. For details on the C2 commands to program Flash memory, see Section “27. C2
Interface” on page 312.
The Flash memory can be programmed by software using the MOVX write instruction with the address and
data byte to be programmed provided as normal operands. Before programming Flash memory using
MOVX, Flash programming operations must be enabled by: (1) setting the PSWE Program Store Write
Enable bit (PSCTL.0) to logic 1 (this directs the MOVX writes to target Flash memory); and (2) Writing the
Flash key codes in sequence to the Flash Lock regist er (FLKEY). The PSWE bit remains set until cleared
by software.
For detailed guidelines on programming Flash from firmware, please see Section “13.5. Flash
Write and Erase Guidelines” on page 137.
To ensure the integrity of the Flash contents, the on-chip VDD Monitor must be enabled and enabled as a
reset source in any system that includes code that writes and/or erases Flash memory from software.
Furthermore, there should be no delay between enabling the VDD Monitor and enabling the VDD Monitor as
a reset source. Any attempt to write or erase Flash memory while the VDD Monitor is disabled, or not
enabled as a reset source, will cause a Flash Error device reset.
13.1.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function. The Flash Lock and
Key Register (FLKEY) must be written with the correct key codes, in sequence, before Flash operations
may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be
written in order. If the key codes are written out of order, or the wrong codes are written, Flash writes and
erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a Flash
write or erase is attempted before the key codes have been written properly. The Flash lock resets after
each write or erase; the key codes must be written again before a following Flash operation can be
performed. The FLKEY register is detailed in SFR Definition 13.2.
Rev. 1.1 133
C8051F91x-C8051F90x
13.1.2. Flash Erase Procedure
The Flash memory is organized in 512-byte pages. The erase operation applies to an entire page (setting
all bytes in the page to 0xFF). To erase an entire Flash page, perform the following step s:
1. Save current interrupt state and disable interrupts.
2. Set the PSEE bit (register PSCTL).
3. Set the PSWE bit (register PSCTL).
4. Write the first key code to FLKEY: 0xA5.
5. Write the second key code to FLKEY: 0xF1.
6. Using the MOVX instruction, write a data byte to any location within the page to be erased.
7. Clear the PSWE and PSEE bits.
8. Restore previous interrupt state.
Steps 4–6 must be repeated for each 512-byte page to be erased.
Notes:
1. To maintain code compatibility with the ‘F93x-’F92x product family, the erase procedure should be performed
on two consecutive 512-byte sections of memory at a time. This allows the same software to run on devices
with 1024-byte or 512-byte Flash pages. Using this techniqu e, devices with 1024-byte Flash pages will have
each Flash page erased twice.
2. Flash security settings may prevent erasure of some Flash pages, such as the reserved area and the page
containing the lock bytes. For a summary of Flash security settings and restrictions affecting Flash erase
operations, please see Section “13.3. Security Options” on page 134.
3. 8-bit MOVX instructions cannot be used to erase or write to Flash memory at addresses higher than 0x00F F.
13.1.3. Flash Write Procedure
A write to Flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits
to logic 1 in Flash. A byte loc ation to be prog rammed should be erased befo re a new value is written.
The recommended procedure for writing a single byte in Flash is as follows:
1. Save current interrupt state and disable interrupts.
2. Ensure that the Flash byte has been erased (has a value of 0xFF).
3. Set the PSWE bit (register PSCTL).
4. Clear the PSEE bit (register PSCTL).
5. Write the first key code to FLKEY: 0xA5.
6. Write the second key code to FLKEY: 0xF1.
7. Using the MOVX instruction, write a single data byte to the desired location within the 1024-
byte sector.
8. Clear the PSWE bit.
9. Restore previous interrupt state.
Steps 5–7 must be repeated for each byte to be written.
Notes:
1. Flash security settings may prevent writes to some areas of Flash, such as the reserved area . For a summary
of Flash security settings and restriction s affecting Flash write operations, please see Section “13.3. Security
Options” on page 134.
2. 8-bit MOVX instructions cannot be used to erase or write to Flash memory at addresses higher than 0x00F F.
13.2. Non-volatile Data Storage
The Flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
write instruction and read using the MOVC instruction. MOVX read instructions always target XRAM.
An additional 512-byte scratchpad is available for non-volatile data storage. It is accessible at addresses
0x0000 to 0x01FF when SFLE is set to 1. The scratchpad area cannot be used for code execution.
C8051F91x-C8051F90x
134 Rev. 1.1
13.3. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by
software as well as to prevent th e viewing of proprietary program code and constants. The Program Store
Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register
PSCTL) bits protect the Flash memory from accidental modification by software. PSWE must be explicitly
set to 1 before software can modify the Flash memory; both PSWE and PSEE must be set to 1 before
software can erase Flash memory. Additional security features prevent proprietary program code and data
constants from being read or altered across the C2 interface.
A Security Lock Byte located at the last byte of Flash user space offers protection of the Flash program
memory from access (re ads, writes, or er ases) by unprotected code or the C2 inter face. The Flash security
mechanism allows the user to lock n 512-byte Flash pages, starting at page 0 (addresses 0x0000 to
0x01FF), where n is the 1s complement number represented by the Security Lock Byte. Note that the
page containing the Flash Security Lock Byte is unlocked when no other Flash pages are locked
(all bits of the Lock Byte are 1) and locked when any other Flash pages are locked (any bit of the
Lock Byte is 0).
Figure 13.1. Flash Program Memory Map (16 kB and 8 kB devices)
The level of Flash security depends on the Flash access method. The three Flash access methods that
can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on
unlocked pages, and user firmware executin g on locked pages. Table 13.1 summarizes the Flash security
features of the C8051F91x-C8051F90x devi ces.
Security Lock Byte: 1111 1011b
ones Complement: 0000 0100b
Flash pages locked: 5 (First four Flash pages + Lock Byte Page)
Addresses locked: 0x0000 to 0x07FF (first four Flash pages) and
0x3A00 to 0x3BFF (Lock Byte Page)
Lock Byte Page
Access limit
set according
to the Flash
security lock
byte 0x0000
0x1FFF
Lock Byte
0x1FFE
0x2000 Flash
memory
organized in
512-byte
pages
0x1E00
Unlocked Flash Pages
Locked when
any other
Flash pages
are locked
Lock Byte Page
0x0000
0x3BFF Lock Byte
Reserved
0x3BFE
0x3C00
0x3A00
Unlocked Flash Pages
16KB Flash Device
(SFLE = 0) 8KB Flash Device
(SFLE = 0)
0x0000
Scratchpad Area
(Data Only)
0x01FF
16/8 KB Flash Device
(SFLE = 1)
0xFFFF
Reserved
0xFFFF
Rev. 1.1 135
C8051F91x-C8051F90x
Table 13.1. Flash Security Summary
Action C2 Debug
Interface User Firmware executing from:
an unlocked page a locked page
Read, Write or Erase unlocked pages
(except page with Lock Byte) Permitted Permitted Permitted
Read, Write or Erase locked pages
(except page with Lock Byte) Not Permitted FEDR Permitted
Read or Write page containing Lock Byte
(if no pages are locked) Permitted Permitted Permitted
Read or Write page containing Lock Byte
(if any page is locked) Not Permitted FEDR Permitted
Read contents of Lock Byte
(if no pages are locked) Permitted Permitted Permitted
Read contents of Lock Byte
(if any page is locked) Not Permitted FEDR Permitted
Erase page containing Lock Byte
(if no pages are locked) Permitted FEDR FEDR
Erase page containing Lock Byte - Unlock all pages
(if any page is locked) Only by C2DE FEDR FEDR
Lock additional pages
(change 1s to 0s in the Lock Byte) Not Permitted FEDR FEDR
Unlock individual pages
(change 0s to 1s in the Lock Byte) Not Permitted FEDR FEDR
Read, Write or Erase Reserved Area Not Permitted FEDR FEDR
C2DE—C2 Device Erase (Erases all Flash pages including the page containing the Lock Byte)
FEDR—Not permitted; Causes Flash Erro r Device Reset (FERROR bit in RSTSRC is 1 after reset)
• All prohibited operations that are performed via the C2 interface are ignored (do not cause device
reset).
• Locking any Flash page also locks the page containing the Lock Byte.
• Once written to, the Lock Byte cannot be modified except by performing a C2 Device Erase.
• If user code writes to the Lock Byte, the Lock does not take effect until the next device reset.
• The scratchpad is locked when all other Flash pages are locked.
• The scratchpad is erased when a Flash Device Erase command is performed.
C8051F91x-C8051F90x
136 Rev. 1.1
13.4. Determining the Device Part Number at Run Time
In many applications, user software may need to determine the MCU part number at run time in order to
determine the hardware capabilities. The part number can be determined by reading the value of the Flash
byte at address 0x3FFE.
The value of the Flash byte at address 0x3FFE can be decoded as follows:
0xD0—C8051F901
0xD1—C8051F902
0xD2—C8051F911
0xD3—C8051F912
Rev. 1.1 137
C8051F91x-C8051F90x
13.5. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of VDD, system clock frequency, or temperature. This accidental execution of Flash
modifying code can result in alteration of Flash memory contents causing a system failure that is only
recoverable by re-Flashing the code in the device.
To help prevent the accidental modification of Flash by firmware, the VDD Monitor must be enabled and
enabled as a re se t s ou rc e o n C8 05 1 F91 x-C8051F90x devices fo r t he F lash to be successfully m o dif ied . If
either the VDD Monitor or the VDD Monitor reset source is not enabled, a Flash Error Devi ce Reset
will be generated when the firmware attempts to modify the Flash.
The following guidelines are recommended for any system that contains routines which write or erase
Flash from code.
13.5.1. VDD Maintenance and the VDD Monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient
protection devices to the p ower supply to ensure that the supply voltages listed in the Absolute
Maximum Ratings table are not exceeded.
2. Make certain that the m inimum VDD rise time specification of 1 ms is met. If the system can-
not meet this rise time specification, then add an external VDD brownout circuit to the RST pin
of the device that holds the device in reset until VDD reaches the minimum device operating
voltage and re-asserts RST if VDD drops below the minimum device operating voltage.
3. Keep the on-chip VDD Monitor enabled and enable the VDD Monitor as a reset source as
early in code as possible. This should be the first set of instructions executed after the Reset
Vector. For C-based systems, this will involve modifying the st artup code added by the C com-
piler. See your compiler documentation for more details. Make certain that there are no delays
in software between enabling the VDD Monitor and enabling the VDD Monitor as a reset
source. Code examples showing this can be found in “AN201: Writing to Flash from Firm-
ware," available from the Silicon Laboratories website.
Note: On C8051F91x-C8051F90x devices, both the VDD Monitor and the VDD Monitor reset
source must be enabled to write or erase Flash without generating a Flash Error Device Reset.
Note: On C8051F91x-C8051F90x devices, both the VDD Monitor and the VDD Monitor reset
source are en ab le d by ha r dwa re after a powe r- on res et .
4. As an added pr ecaution, explic itly enable the VDD Monit or and enable the V DD Monitor as a
reset source inside the functions th at write and er ase Fla sh memory. The VDD Monitor enable
instructions should be p laced just af ter th e inst ruction to set PSWE to a 1, but befo re th e Flash
write or erase operation instruction.
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment
operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For exam-
ple, "RSTSRC = 0x02" is correct, but "RSTSRC |= 0x02" is incorrect.
6. Make certain that all writes to the RSTSRC regist er explicitly set t he PORSF bit to a 1. Areas
to check are initialization code which enables other reset sources, such as the Missing Clock
Detector or Comparator, for example, and instructions which force a Software Reset. A global
search on "RSTSRC" can quickly verify this.
C8051F91x-C8051F90x
138 Rev. 1.1
13.5.2. PSWE Maintenance
7. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a 1. There
should be exactly one routine in code that sets PSWE to a 1 to write Flash bytes and one rou-
tine in code that sets both PSWE and PSEE both to a 1 to erase Flash pages.
8. Minimize the number of variable accesses while PSWE is set to a 1. Handle pointer address
updates and loop maintenance outside the "PSWE = 1;... PSWE = 0;" area. Code examples
showing this can be found in AN201, "Writing to Flash from Firmware", available from the Sili-
con Laborator ies web site.
9. Disable interrup ts prior to setting PSWE to a 1 and leave them disabled until after PSWE has
been reset to 0. Any interrupts posted during the Flash write or erase operation will be ser-
viced in priority order after the Flash operation has been completed and interrupts have been
re-enabled by software.
10. Make certain that the Flash write and erase pointer variables are not located in XRAM. See
your compiler documentation for instructions regarding how to explicitly locate variables in dif-
ferent memory areas.
11. Add address bounds checking to the routines that write or erase Flash memory to ensure that
a routine called with an illegal address does not result in modification of the Flash.
13.5.3. System Clock
12. If operating from an external crystal, be advised that crystal performance is susceptible to
electrical interferen ce and is sensitive to layou t and to cha nges in tem perature. If the syste m is
operating in an electrically noisy environment, use the internal oscillator or use an external
CMOS clock.
13. If operating from the external oscillator, switch to the internal oscillator during Flash write or
erase operations. The external oscillator can continue to run, and the CPU can switch back to
the external oscillator after the Flash operation has completed.
Additional Flash recommendations and example code can be found in “AN201: Writing to Flash from
Firmware", available from the Silicon Laboratories web site.
Rev. 1.1 139
C8051F91x-C8051F90x
13.6. Minimizing Flash Read Current
The Flash memory in the C8051F91x-C8051F90x devices is responsible for a substantial portion of the
total digital supply current when the device is executing code. Below are suggestions to minimize Flash
read current.
1. Use idle, suspend, or sleep modes while waiting for an interrupt, rather than polling the inter-
rupt flag. Idle Mode is particularly well-suited for use in implementing short pauses, since the
wake-up time is no more than three system clock cycles. See the Power Management chapter
for details on the various low-power operating modes.
2. C8051F91x-C8051F90x devices have a one-shot timer that saves power when operating at
system clock frequencies of 14 MHz or less. The one-shot timer generates a minimum-dura-
tion enable signal for the Flash sense amps on each clock cycle in which the Flash memory is
accessed. This allows the Flash to remain in a low power state for the remainder of the long
clock cycle.
At clock frequencies above 14 MHz, the system clock cycle becomes short enough that the
one-shot timer no longer provides a power benefit. Disabling the one-shot timer at higher fre-
quencies reduces power consumption. The one-shot is enabled by default, and it can be dis-
abled (bypassed ) by setting the B YPASS bit (F LSCL.6) to logic 1. To r e-enable the one-shot,
clear the BYPASS bit to logic 0.
3. Flash read current depends on the number of address lines that toggle between sequential
Flash read operations. In most cases, the difference in power is relatively small (on the order
of 5%).
The Flash memory is organized in rows of 64 bytes. A substantial current increase can be
detected when the read address jumps from one row in the Flash memory to another. Con-
sider a 3-cycle loop (e.g., SJMP $, or while(1);) which straddles a Flash row boundary. The
Flash address jumps from one row to another on two of every three clock cycles. This can
result in a current increase of up 30% when compared to the same 3-cycle loop contained
entirely within a single row.
To minimize the power consumption of small loop s, it is best to locate them with in a single row,
if possible. To che ck if a loop is contained within a Flash row, divide the star ting a ddress of the
first instruction in the loop by 64. If the remainder (result of modulo operation) plus the length
of the loop is less than 63, then the loop fits inside a single Flash row. Otherwise, the loop will
be straddling two adjacent F lash rows. If a loop execut es in 20 or more clock cycles, th en the
transitions from one row to another will occur on relatively few clock cycles, and any resulting
increase in operating current will be negligible.
To write software that is compatible with all devices in the ‘F93x-’F92x and ‘F91x-’F90x
product families, the Flash row size should be considered 64 bytes.
C8051F91x-C8051F90x
140 Rev. 1.1
SFR Page =0x0; SFR Address = 0x8F
SFR Definition 13.1. PSCTL: Program Store R/W Control
Bit76543210
Name SFLE PSEE PSWE
Type RRRRRR/W R/W R/W
Reset 00000000
Bit Name Function
7:3 Unused Unused.
Read = 00000b, Write = don’t care.
2SFLE Scratchpad Flash Memory Access Enable.
When this bit is set, Flash MOVC reads and MOVX writes from use r so ftware are
directed to the Scratchpad Flash sector. Flash accesses outside the address range
0x0000-0x01FF shou ld not be attempted and may yield undefined results when SFLE
is set to 1.
0: Flash access from user software directed to the Program/Dat a Flash sector.
1: Flash access from user software directed to the Scratchpad Sector.
1PSEE Program Store Erase Enable.
Setting this bit (in combination with PSWE) allows an entire page of Flash program
memory to be erased. If this bit is logic 1 and Flash writes are enabled (PSWE is logic
1), a write to Flash memory using the MOVX instruction will erase th e en tir e page that
conta ins the location addressed by the MOVX instruction. The value of the da ta byte
written does not matter.
0: Flash program memory erasure disabled.
1: Flash prog ra m me m ory erasure enabled.
0PSWE Program Store Write Enable.
Setting this bit allows writing a byte of data to the Flash program memory using the
MOVX write instruction. The Flash location should be erased before writing data.
0: Writes to Flash program memory disabled.
1: Writes to Flash program memory enabled; the MOVX write instruction targets Flash
memory.
Rev. 1.1 141
C8051F91x-C8051F90x
SFR Page = 0x0; SFR Address = 0xB6
SFR Definition 13.2. FLKEY: Flash Lock and Key
Bit76543210
Name FLKEY[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 FLKEY[7:0] Flash Lock and Key Re gister.
Write:
This register provides a lock and key function for Flash erasures and writes. Flash
writes and erases are enabled by writing 0xA5 followed by 0xF1 to the FLKEY regis-
ter. Flash writes and erases are automatically disabled after the next write or er ase is
complete. If any writes to FLKEY are performed incorrectly, or if a Flash write or erase
operation is attempted while these operations are disabled, the Flash will be perma-
nently locked from writes or erasures until the next device reset. If an applicat ion
never writes to Flash, it can intentionally lock the Flash by writing a non-0xA5 value to
FLKEY from software.
Read:
When read, bits 1–0 indicate the current Flash lock state.
00: Flash is write/erase locked.
01: The first key code has been written (0xA5).
10: Flash is unlocked (writes/erases allowed).
11: Flash writ es /e ra se s disa ble d until th e ne xt re se t.
C8051F91x-C8051F90x
142 Rev. 1.1
SFR Page = 0x0; SFR Address = 0xB6
SFR Page = 0x0; SFR Address = 0xE5
SFR Definition 13.3. FLSCL: Flash Scale
Bit 7 6 5 4 3 2 1 0
Name BYPASS
Type RR/W RRRRRR
Reset 0 0 0 0 0 0 0 0
Bit Name Function
7Reserved Reserved. Always Write to 0.
6BYPASS Flash Read Timing One-Shot Bypass.
0: The one-shot determin es the Flash read time. This setting should be used for oper-
ating frequencies less than 10 MHz.
1: The system clock determines the Flash read time. This setting should be used for
frequencies grea ter than 10 MHz.
5:0 Reserved Reserved. Always Write to 000000.
Note: Operations which clear the BYPASS bit do not need to be immediately followed by a benign 3-byte instruction
on C8051F912/11/02/01 devices. For code compatibility with C8051F930/31/20/21 devices, a benign 3-byte
instruction whose third byte is a don't care should follow the clear operation. See the C8051F93x-C8051F92x
data sheet for more details.
SFR Definition 13.4. FLWR: Flash Write Only
Bit 7 6 5 4 3 2 1 0
Name FLWR[7:0]
Type W
Reset 0 0 0 0 0 0 0 0
Bit Name Function
7:0 FLWR[7:0] Flash Write Only.
All writes to this register have no ef fect on system operation.
Rev. 1.1 143
C8051F91x-C8051F90x
14. Power Management
C8051F91x-C8051F90x devices support 5 power modes: Normal, Idle, Stop, Suspend, and Sleep. The
power management unit (PMU0) allows the device to enter and wake-up from the available power modes.
A brief description of each power mode is provided in Table 14.1. Detailed descriptions of each mode can
be found in the following sections.
In battery powered systems, the system shou ld sp end as much time as po ssible in slee p m ode in o rde r to
preserve batt ery life. When a task with a fixed num ber of clock cycles needs to be performed, the device
should switch to no rmal mode , finish the task as quickly as possible, and return to slee p mode. Idle mode
and suspend modes provide a very fast wake-up time; however, the power savings in these modes will not
be as much as in sleep mode. Stop mode is included for legacy reasons; the system will be more power
efficient an d easier to wake up when idle, suspend, or sleep mode are used.
Although switching power modes is an integral part of power management, enabling/disabling individual
peripherals as needed will help lower power consumption in all power modes. Each analog peripheral can
be disabled when not in use or placed in a low power mode. Digital peripherals such as timers or serial
busses draw little power whenever they are not in use. Digital peripherals draw no power in Sleep Mode.
Table 14.1. Power Modes
Power Mode Description Wake-Up
Sources Power Savings
Normal Device fully functional N/A Excellent MIPS/mW
Idle All peripherals fully functional.
Very easy to wake up. Any Interrupt. Good
No Code Execution
Stop Legacy 8051 low power mode.
A reset is required to wake up. Any Reset. Good
No Code Execution
Precision Oscillator Disabled
Suspend Similar to S top Mode, but very fast
wake-up time and co de res um e s
execution at the next instruction.
SmaRTClock,
Port Match,
Comparator0,
RST pin.
Very Good
No Code Execution
All Internal Oscillators Disabled
System Clock Gated
Sleep Ultra Low Power and flexible
wake-up sources. Code resumes
execution at the next instruction.
Comparator0 only fun ct i on a l in
two-cell mode.
SmaRTClock,
Port Match,
Comparator0,
RST pin.
Excellent
Power Supply Gated
All Oscillators except SmaRT-
Clock Disabled
C8051F91x-C8051F90x
144 Rev. 1.1
14.1. Normal Mode
The MCU is fully functional in normal mode. Figure 14.1 shows the on-chip power distribution to various
peripherals. There are three supply voltages powering various sections of the chip: VBAT, VDD/DC+ , and
the 1.8 V internal core supply. VREG0, PMU0 and the SmaRTClock are a lways powere d directly fro m the
VBAT pin. All analog peripherals are directly powered from the VDD/DC+ pin, which is an output in one-cell
mode and an input in two-ce ll mode. All digit al peripher als and the CIP-51 core are powered from the 1.8 V
internal core supply. The RAM is also powered from the core supply in Normal mode.
Figure 14.1. C8051F91x-C8051F90x Power Distribution
RAM
VREG0
PMU0
Sleep Active/Idle/
Stop/Suspend
VBAT VDD/DC+
One-cell: 0.9 to 1.8 V
Two-cell: 1.8 to 3.6 V One-cell or Two-cell: 1.8 to 3.6 V
Analog Peripherals
10-bit
300 ksps
ADC
TEMP
SENSOR
A
M
U
X
VOLTAGE
COMPARATORS
+
-
IREF0
+
-
VREF
Digital Peripherals
Flash
CIP-51
Core
UART
SPI
SMBusTimers
GPIO
1.8 V
DC0
SmaRTClock
One-Cell Active/
Idle/Stop/Suspend
One-Cell Sleep
1.9 V
typical Note: VDD/DC+ must be > VBAT
One-cell: 0.9 to 3.6 V (F912/02 devices only)
Rev. 1.1 145
C8051F91x-C8051F90x
14.2. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon
as the instruction that sets the bit completes execution. All internal registers and memory maintain their
original dat a. All analog and digital peripherals can remain active during Idle mode.
Note: To ensure the MCU enters a low power state upon entry into Idle Mode, the one-shot circuit should be
enabled by clearing the BYPASS bit (FLSCL.6).
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby termi-
nate the Idle mode. This featur e protect s the system from an unintended per manen t shut down in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the idle mode if the WDT was initially configured to allow this operation. This pro-
vides the opportunity for additional power savings, allowing the system to remain in the idle mode indefi-
nitely, waiting for an external stimulus to wake up the system. Refer to Se ction “18.6. PCA W a tchdog T imer
Reset” on page 176 for more information on the use and config uration of the WDT.
14.3. S t op Mode
Setting the St op Mode Select bit (PCON.1) causes the CIP-51 to enter stop mode as soon as the instruc-
tion that sets the bit completes execution. In stop mode the precision internal oscillator and CPU are
stopped; the state of the low power oscillator and the external oscillator circuit is not affected. Each analog
peripheral (including the external oscillator circuit) may be shut down individually prior to entering stop
mode. Stop mode can only be terminated by an internal or external reset. On reset, the CIP-51 performs
the normal reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Dete ctor sho uld be d isabled if the CPU is to be put to in STOP mode for longer tha n the
MCD timeout.
Stop mode is a legacy 8051 power mode; it will not result in optimal power savings. Sleep or suspend
mode will provide more power savings if the MCU needs to be inactive for a long period of time.
Note: To ensure the MCU enters a low power state upon entry into Stop Mode, the one-shot circuit should be
enabled by clearing the BYPA SS b it (FL S CL.6).
C8051F91x-C8051F90x
146 Rev. 1.1
14.4. Suspend Mode
Setting the Suspend Mode Select bit (PMU0CF.6) causes the system clock to be gated off and all internal
oscillators disabled. The system clock source must be set to the low power internal oscillator or the preci-
sion oscillator prior to entering suspend mode. All digital logic (timers, communication peripherals, inter-
rupts, CPU, etc.) stops func tioning until one of the enabled wake-up sources occurs.
The following wake-up sources can be configured to wake the device from suspend mode:
SmaRTClock Oscillator Fail
SmaRTClock Alarm
Port Match Event
Comparator0 Rising Edge
Note: Upon wake-up from suspend mode, PMU0 requires two system clocks in order to update the PMU0CF wake-
up flags. All flags will read back a value of '0' during the first two system clocks following a wake-up from
suspend mode.
In addition, a noise glitch on RST that is not long enough to reset the device will cause the device to exit
suspend. In order for the MCU to respond to the pin reset event, software must not place the device back
into suspend mode for a period of 15 µs. The PMU0CF regis ter m a y b e ch e cke d to d et erm ine if th e wa ke -
up was due to a falling edge on the /RST pin. If the wake-up source is not due to a falling edge on RST,
there is no time restriction on how soon software may place the device back into suspend mode. A 4.7 kW
pullup resistor to VDD/DC+ is recommend for RST to prevent noise glitches from waking the device.
14.5. Sleep Mode
Setting the Sleep Mode Select bit (PMU0CF.6) turns off the internal 1.8 V regulator (VREG0) and switches
the power supply of all on-chip RAM to the VBAT pin (see Figure 14.1). Power to most digital logic on the
chip is disconnected; only PMU0 and the SmaRTClock remain powered. Analog peripherals remain pow-
ered in two-cell mode and lose their supply in one-cell mode because the dc-dc converter is disabled. In
two-cell mode, only the Comparators remain functional when the device enters sleep mode. All other ana-
log peripherals (ADC0, IREF0, External Oscillator, etc.) should be disabled prior to entering sleep mode.
The system clock source must be set to the low power internal oscillator or the pr ecision oscillator prior to
entering sleep mode.
Note: When exiting sleep mode, 4 NOP instructions should be located immediately after the write to PMU0CF
that placed the device in sleep mode.
Note: If the average active time (between successive entries into Sleep Mode) is less than 1 ms, peripherals
that may cause a wake-up from Sleep Mode (SmaRTCloc k, Port Ma tch, and Comparator0) or are
enabled or configured in a way which may cau se the wake-up flag to be set should be sele cted as
wake-up sources. If these per ipherals are not selected as wake-up sources, then it is recommended to
bypass the Flash on e-shot (FLSCL.6=1) before entering into Sleep Mode.
GPIO pins configured as digital outputs will retain their output state during sleep mode. In two-cell mode,
they will maintain the same current drive capability in sleep mode as they have in normal mode. In one-cell
mode, the VDD/DC+ supply will drop to the level of VBAT, which will reduce the output high-voltage level
and the source and sink current drive capability.
GPIO pins configu red as digital inputs can be used during sleep mode as wakeup sources using the port
match feature. In two-cell mode, they will maintain the same input level s pecs in sleep mode as they have
in normal mode. In one-cell mode, the VDD supply will drop to the level of VBAT, which will lower the
switching threshold and increase the propagation delay.
C8051F912 and C8051F902 devices support a wakeup request for external devices. Upon exit from sleep
mode, the wake-up request signal is driven high, allowing other devices in the system to wake up from
their low power m odes. An exam ple of a system that may b enefi t from th is fu nction is one that u ses a hi gh-
power dc-dc converter (>65 mW of output power). The dc-dc conver ter may be disabled when the system
is asleep, and can be awoken by the wake-up request signal from the MCU. The wakeup request signal is
high when the MCU is awake and low when the MCU is asleep.
Rev. 1.1 147
C8051F91x-C8051F90x
Note: By default, the VDD/DC+ supply is connected to VBAT upon entry into Sleep Mode (one-cell mode). If the
VDDSLP bit (DC0CF.1) is set to logic 1, the VDD/D C+ supply will float in Sleep Mode. This allows the
decoupling capacitance on the VDD/DC+ supply to maintain the supply rail until the cap acitors are discharged.
For relatively short sleep intervals, this can result in substantial power savings because the decoupling
capacitance is not continuously charged and discharged.
RAM and SFR register contents are preserved in sleep mode as long as the voltage on VBAT does not fall
below VPOR. The PC counter and all other volatile state information is preserved allowing the device to
resume code execution upon waking up from Sleep mode. The following wake-up sources can be config-
ured to wake the devi ce from sleep mode:
SmaRTClock Oscillator Fail
SmaRTClock Alarm
Port Match Event
Comparator0 Rising Edge .
The Comparator0 Rising Edge wakeup is only valid in two-cell mode. The comparator requires a supply
voltage of at least 1.8 V to operate pr ope rly. On ‘F912 and ‘F902 devices, the VBAT supply monitor can be
disabled to save power by writing 1 to the MONDIS (PMU0MD.5) bit. When the VBAT supply monitor is
disabled, all reset sources will trigger a full POR and will re-enable the VBAT supply monitor.
In addition, any falling edge on RST (due to a pin reset or a noise glitch) will cause the device to exit sleep
mode. In order for the MCU to re sp on d to the p i n reset event, software must not place the device back into
sleep mode for a period of 15 µs. The PMU0CF register may be checked to determine if th e wake -up was
due to a falling edge on the RST pin. If the wake-up source is not due to a falling edge on RST, there is no
time restriction on how soon software may place the device back into sleep mode. A 4.7 k pullup resistor
to VDD/DC+ is recommend for RST to prevent noise glitches from waking the device.
14.6. Configuring Wakeup Sources
Before placing the device in a low power mode, one or more wakeup sources should be enabled so that
the device does not remain in the low power mode indefinitely. For Idle Mode, this includes enabling any
interrupt. For Stop Mode, this includes enabling any reset source or relying on the RST pin to reset the
device.
Wake-up sources for suspend and sleep modes are configured through the PMU0CF register. Wake-up
sources are enabled by writing 1 to the corresponding wake-up source enable bit. Wake-up sources must
be re-enabled each time the device is placed in suspend or sleep mode, in the same write that places the
device in the low power mode.
The reset pin is always enabled as a wake-up source. On the falling edge of RST, the device will be
awaken from sleep mode. The device must remain awake for more than 15 µs in order for the reset to take
place.
C8051F91x-C8051F90x
148 Rev. 1.1
14.7. Determining the Event that Caused the Last Wakeup
When waking from idle mode, the CPU will vector to the interrupt which caused it to wake up. When wak-
ing from stop mode, the RSTSRC register may be read to determine the cause of the last reset.
Upon exit from suspend or sleep mode, the wake-up flags in the PMU0CF register can be read to deter-
mine the event which caused the device to wake up. After waking up, the wake-up flags will continue to be
updated if any of the wake-up events occur. Wake-up flags are always updated, even if they are not
enabled as wake-up sources.
All wake-up flags enabled as wake-up sources in PMU0CF must be cleared before the device can enter
suspend or sleep mode. After clearing the wake-up flags, each of the enabled wake-up events should be
checked in the individual peripherals to ensure that a wake-up event did not occur while the wake-up flags
were being cleared.
Rev. 1.1 149
C8051F91x-C8051F90x
SFR Page = 0x0; SFR Address = 0xB5
SFR Definition 14.1. PMU0CF: Power Management Unit Configuration1,2
Bit 7 6 5 4 3 2 1 0
Name SLEEP SUSPEND CLEAR RSTWK RTCFWK RTCAWK PMATWK CPT0WK
Type W W W R R/W R/W R/W R/W
Reset 0 0 0 Varies Varies Varies Varies Varies
Bit Name Description Write Read
7SLEEP Sleep Mode Select Writing 1 places the
device in Sleep Mode. N/A
6SUSPEND Suspend Mode Select Writing 1 places the
device in Suspend Mode. N/A
5CLEAR Wake-up Flag Clear Writing 1 clears all wake-
up flags. N/A
4RSTWK Reset Pin Wake-up Flag N/A Set to 1 if a falling edge
has been dete cte d on
RST.
3RTCFWK SmaRTClock Oscillator
Fail Wake-up Source
Enable and Flag
0: Disable wake-up on
SmaRTClock Osc. Fail.
1: Enable wake-up on
SmaRTClock Osc. Fail.
Set to 1 if the SmaRT-
Clock Oscillator has failed.
2RTCAWK SmaRTClock Alarm
Wake-up Source Enable
and Flag
0: Disable wake-up on
SmaRTClock Alarm.
1: Enable wake-up on
SmaRTClock Alarm.
Set to 1 if a SmaRTClock
Alarm has occurred.
1PMATWK Port Match Wake-up
Source Enable and Flag 0: Disable wake-up on
Port Match Event.
1: Enable wake-up on
Port Match Event.
Set to 1 if a Port Match
Event has occurred.
0CPT0WK Comparator0 Wake-up
Source Enable and Flag 0: Disable wake-up on
Comparator0 rising edge.
1: Enable wake-up on
Comparator0 rising edge.
Set to 1 if Comparator0
rising edge has occurred.
Notes:
1. Read-modify-write operati ons (ORL, ANL, etc.) should not be used on this register. Wake-up sources must
be re-enabled each time the SLEEP or SUSPEND bits are written to 1.
2. The Low Power Internal Oscillator cannot be disabled and the MCU cannot be placed in Suspend or Sleep
Mode if any wake-up flags ar e set to 1. Software should clear all wake-up sources af ter each reset and after
each wake-up from Suspend or Sleep Modes.
3. PMU0 requires two system clocks to update the wake-up source flags after waking from Suspend mode. The
wake-up source flags will read ‘0’ during the first two system clocks following the wake from Suspend mode.
C8051F91x-C8051F90x
150 Rev. 1.1
SFR Page = 0xF; SFR Address = 0xB5
SFR Definition 14.2. PMU0MD: Power Management Unit Mode
Bit 7 6 5 4 3 2 1 0
Name RTCOE WAKEOE MONDIS
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00 000000
Bit Name Function
7RTCOE Buffered SmaRTClock Output Enable.
Enables the buffered SmaRTClock oscillator output on P0.2. Only available on
‘F912 and ‘F902 devices.
0: Buff ered SmaRTClock output is not enabled.
1: Buffered SmaRTClock output is enabled.
6WAKEOE Wakeup Request Output Enable.
Enables the Sleep Mode wake-up request signal on P0.3. Only available on ‘F912
and ‘F902 devices.
0: Wake-up request signal is not enabled.
1: Wa ke -u p re qu e st sign a l is enab le d.
5MONDIS VBAT Supply Monitor Disable.
Writing a 1 to this bit disables the VBAT supply monitor. Writing a 0 to this bit when
the VBAT supply monitor is disabled will trigger a power-on reset. Only available on
‘F912 and ‘F902 devices.
4:0 Unused Unused.
Read = 00000b. Write = Don’t Care.
Rev. 1.1 151
C8051F91x-C8051F90x
SFR Page = All Pages; SFR Address = 0x87
14.8. Power Management Specifications
See Table 4 .5 on page 53 for detailed Power Management Specifications.
SFR Definition 14.3. PCON: Power Management Control Register
Bit 7 6 5 4 3 2 1 0
Name GF[5:0] STOP IDLE
Type R/W W W
Reset 00 000000
Bit Name Description Write Read
7:2 GF[5:0] General Purpose Flags Sets the logic value. Returns the logic value.
1STOP Stop Mode Select Writing 1 places the
device in Stop Mode. N/A
0IDLE Idle Mode Select Writing 1 places the
device in Idle Mode. N/A
C8051F91x-C8051F90x
152 Rev. 1.1
15. Cyclic Redundancy Check Unit (CRC0)
C8051F91x-C8051F90x devices include a cyclic redundancy check unit (CRC0) that can perform a CRC
using a 16-bit or 32-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register.
CRC0 posts the 16- bit or 32-bit re sult to an intern al register. Th e internal resu lt register ma y be accessed
indirectly using the CRC0PNT bits and CRC0DAT register, as shown in Figure 15.1. CRC0 also has a bit
reverse register for quick data manipulation.
Figure 15.1. CRC0 Block Diagram
15.1. CRC Algorithm
The C8051F91x-C8051F90x CRC unit generates a CRC re sult equivalent to the following algorithm:
1. XOR the input with the most-significant bits of the current CRC result. If this is the first iteration
of the CRC unit, the current CRC result will be the set initial value
(0x00000000 or 0xFFFFFFFF).
2a. If the MSB of the CRC result is set, shift the CRC result and XOR the result with the selected
polynomial.
2b. If the MSB of the CRC result is not set, shift the CRC result.
Repeat Steps 2a/2b for the number of input bits (8). The algorithm is also described in the following
example.
The 16-bit C8051F91x-C8051F90x CRC algorithm can be described by the following code:
unsigned short UpdateCRC (unsigned short CRC_acc, unsigned char CRC_input)
{
unsigned char i; // loop counter
#define POLY 0x1021
// Create the CRC "dividend" for polynomial arithmetic (binary arithmetic
CRC0IN 8
CRC0DAT
CRC0CN
CRC0SEL
CRC0INIT
CRC0VAL
CRC0PNT1
CRC0PNT0
CRC Engine
4 to 1 MUX
RESULT
32
8 8 8 8
8
CRC0AUTO
CRC0CNT
Automat ic CRC
Controller Flash
Memory
8
CRC0FLIP
Write
CRC0FLIP
Read
Rev. 1.1 153
C8051F91x-C8051F90x
// with no carries)
CRC_acc = CRC_acc ^ (CRC_input << 8);
// "Divide" the poly into the dividend using CRC XOR subtraction
// CRC_acc holds the "remainder" of each divide
//
// Only complete this division for 8 bits since input is 1 byte
for (i = 0; i < 8; i++)
{
// Check if the MSB is set (if MSB is 1, then the POLY can "divide"
// into the "dividend")
if ((CRC_acc & 0x8000) == 0x8000)
{
// if so, shift the CRC value, and XOR "subtract" the poly
CRC_acc = CRC_acc << 1;
CRC_acc ^= POLY;
}
else
{
// if not, just shift the CRC value
CRC_acc = CRC_acc << 1;
}
}
// Return the final remainder (CRC value)
return CRC_acc;
}
Table 15.1 lists several input values and the associated outputs using the 16-bit C8051F91x-C8051F90x
CRC algorithm:
Table 15.1. Example 16-bit CRC Outputs
Input Output
0x63 0xBD35
0x8C 0xB1F4
0x7D 0x4ECA
0xAA, 0xBB, 0xCC 0x6CF6
0x00, 0x00, 0xAA, 0xBB, 0xCC 0xB166
C8051F91x-C8051F90x
154 Rev. 1.1
15.2. Preparing for a CRC Calculation
To prepare CRC0 for a CRC calculation, software should select the desired polynomial and set the initial
value of the result. Two polynomials are available: 0x1021 (16-bit) and 0x04C11DB7 (32-bit). The CRC0
result may be initialized to one of two values: 0x00000000 or 0xFFFFFFFF. The following steps can be
used to initialize CRC0.
1. Select a polynomial (Set CRC0SEL to 0 for 32-bit or 1 for 16-bit).
2. Select the initial result value (Set CRC0VAL to 0 for 0x00000000 or 1 for 0xFFFFFFFF).
3. Set the result to its initial value (Write 1 to CRC0INIT).
15.3. Performing a CRC Calculation
Once CRC0 is initialized, the input data stream is sequentially written to CRC0IN, one byte at a time. The
CRC0 result is automatically updated af ter each byte is written . The CRC engine may also be configur ed to
automatically perform a CRC on one or more Flash sectors. The following steps can be used to
automatically perform a CRC on Flash memory.
1. Prepare CRC0 for a CRC calculation as shown above.
2. Write the index of the starting page to CRC0AUTO.
3. Set the AUTO EN bit in CRC0AUTO.
4. Write the number of Flash sectors to perform in the CRC calculation to CRC0CNT.
Note: Each Flash sector is 512 bytes on ‘F91x and ‘F90x devices.
5. Write any value to CRC0CN (or OR its contents with 0x00) to initiate the CRC calculation. The
CPU will not execute code any additional code until the CRC operation completes. See the
note in SFR Definition 15.1. CRC0CN: CRC0 Control for more information on how to
properly initiate a CRC calculation.
6. Clear the AUTOEN bit in CRC0AUTO.
7. Read the CRC result using the procedure below.
15.4. Accessing the CRC0 Result
The internal CRC0 result is 32-bits (CRC0SEL = 0b) or 16-bits (CRC0SEL = 1b). The CRC0PNT bits
select the byte that is t argeted by re ad and write opera tions on CRC0DAT and increment after each r ead or
write. The calculation result will remain in the internal CR0 result register until it is set, overwritten, or
additional data is written to CRC0IN.
Rev. 1.1 155
C8051F91x-C8051F90x
SFR Page = 0xF; SFR Address = 0x92
SFR Definition 15.1. CRC0CN: CRC0 Control
Bit76543210
Name CRC0SEL CRC0INIT CRC0VAL CRC0PNT[1:0]
Type R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:5 Unused Unused.
Read = 000b; Write = Don’t Care.
4CRC0SEL CRC0 Polynomial Select Bit.
This bit selects the CRC0 polynomial and result length (32-bit or 16-bit).
0: CRC0 uses the 32-bit polynomial 0x04C11DB7 for calculating the CRC result.
1: CRC0 uses the 16-bit polynomial 0x1021 for calculating the CRC result.
3CRC0INIT CRC0 Result Initialization Bit.
Writing a 1 to this bit initializes the entire CRC result based on CRC0VAL.
2CRC0VAL CRC0 Set Value Initialization Bit.
This bit selects the set value of the CRC result.
0: CRC result is set to 0x00000 000 on write of 1 to CRC0INIT.
1: CRC result is set to 0xFFFFFFFF on write of 1 to CRC0INIT.
1:0 CRC0PNT[1:0] CRC0 Result Pointer.
Specifies the byte of the CRC result to be read/w ritt en on th e ne xt ac ce ss to
CRC0DAT. The value of these bits will auto-increment upon each read or write.
For CRC0SEL = 0:
00: CRC0DAT accesses bits 7–0 of the 32-bit CRC resu lt.
01: CRC0DAT accesses bits 15–8 of the 32-bit CRC result.
10: CRC0DAT accesses bits 23–16 of the 32-bit CRC result.
11: CRC0DAT accesses bits 31–24 of the 32-bit CRC result.
For CRC0SEL = 1:
00: CRC0DAT accesses bits 7–0 of the 16-bit CRC resu lt.
01: CRC0DAT accesses bits 15–8 of the 16-bit CRC result.
10: CRC0DAT accesses bits 7–0 of the 16-bit CRC result.
11: CRC0DAT accesses bits 15–8 of the 16-bit CRC result.
Note: Upon initiation of a n auto ma tic CR C calcu l at io n , the th ird op co d e byte fetched from program memory is
indeterminate. Therefore, writes to CRC0CN that initiate a CRC operation must be immediately followed by a
benign 3-byte instruction whose third byte is a don’t care. An example of such an instruction is a 3-byte MOV
that targets the CRC0FLIP register. When programming in ‘C’, the dummy value written to CRC0FLIP should
be a non-zero value to prevent the compiler from generating a 2-byte MOV instruction.
C8051F91x-C8051F90x
156 Rev. 1.1
SFR Page = 0xF; SFR Address = 0x93
SFR Page = 0xF; SFR Address = 0x91
SFR Definition 15.2. CRC0IN: CRC0 Data Input
Bit76543210
Name CRC0IN[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 CRC0IN[7:0] CRC0 Data Input.
Each write to CRC0IN results in the written data being computed into the existing
CRC result according to the CRC algorithm described in Section 15 .1
SFR Definition 15.3. CRC0DAT: CRC0 Data Output
Bit76543210
Name CRC0DAT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 CRC0DAT[7:0] CRC0 Data Output.
Each read or write performed on CRC0DAT targets the CRC result bits pointed to
by the CRC0 Result Pointer (CRC0PNT bits in CRC0CN).
Rev. 1.1 157
C8051F91x-C8051F90x
SFR Page = 0xF; SFR Address = 0x96
SFR Definition 15.4. CRC0AUTO: CRC0 Automatic Control
Bit 7 6 5 4 3 2 1 0
Name AUTOEN CRCDONE CRC0ST[5:0]
Type R/W R/W
Reset 0 1 0 0 0 0 0 0
Bit Name Function
7AUTOEN Automatic CRC Calculation Enable.
When AUTOEN is set to 1, any write to CRC0CN will initiate an automatic CRC
starting at Flash sector CRC0ST and continuing for CRC0CNT sectors.
6CRCDONE CRCDONE Automatic CRC Calculation Complete.
Set to 0 when a CRC calculation is in progress. Code executio n is stopped during
a CRC calculation; therefore, reads from firmware will always return 1.
5:0 CRC0ST[5:0] Automatic CRC Calculation Starting Flash Sector.
These bits specify the Flash sector to start the automatic CRC calculation. The
starting ad dress of the first Flash sector inclu ded in the automatic CRC calculation
is CRC0ST x Page Size.
Note: ‘F91x and ‘F90x devices have a page size of 512 bytes.
C8051F91x-C8051F90x
158 Rev. 1.1
SFR Page = 0xF; SFR Address = 0x97
SFR Definition 15.5. CRC0CNT: CRC0 Automatic Flash Sector Count
Bit76543210
Name CRC0CNT[5:0]
Type R/W R/W
Reset 00000000
Bit Name Function
7:6 Unused Unused.
Read = 00b; Write = Don’t Care.
5:0 CRC0CNT[5:0] Automatic CRC Calculation Flash Sector Count.
These bits specify the number of Flash sectors to include in an automatic CRC
calculation. The st arting addr ess of the last Flash sector included in the automatic
CRC calculation is (CRC0ST+CRC0CNT) x Page Size.
Note: ‘F91x and ‘F90x devices have a page size of 512 bytes.
Rev. 1.1 159
C8051F91x-C8051F90x
15.5. CRC0 Bit Reverse Feature
CRC0 includes hardware to reverse the bit order of each bit in a byte as shown in Figure 15.2. Each byte
of data written to CRC0FLIP is read back bit reversed. For example, if 0xC0 is written to CRC0FLIP, the
data read back is 0x03. Bit reversal is a useful mathematical function used in algorithms such as the FFT.
Figure 15.2. Bit Reverse Register
SFR Page = 0xF; SFR Address = 0x95
SFR Definition 15.6. CRC0FLIP: CRC0 Bit Flip
Bit76543210
Name CRC0FLIP[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 CRC0FLIP[7:0] CRC0 Bit Flip.
Any byte written to CRC0FLIP is read back in a bit-reversed order , i.e. the written
LSB becomes the MSB. For example:
If 0xC0 is written to CRC0FLIP, the data read back will be 0x03.
If 0x05 is written to CRC0FLIP, the data read back will be 0xA0.
CRC0FLIP
Write
CRC0FLIP
Read
C8051F91x-C8051F90x
160 Rev. 1.1
16. On-Chip DC-DC Converter ( DC0)
C8051F91x-C8051F90x devices include an on-chip dc-dc converter to allow operation from a single cell
battery with a supply voltage as low as 0.9 V. The dc-dc converter is a switching boost converter with an
input voltage range of 0.9 to 1.8 V (C8051F911/01) or 3.6 V (C8051F912/11) and a programmable output
voltage range of 1.8 to 3.3 V. The default output voltage is 1.9 V when the input is less than 1.9 V. Since
the dc-dc converter uses a boost architecture , the output voltage wil l always be greater than or equal to the
input voltage. The dc-dc converter can supply the system with up to 65 mW of regulated power (or up to
100 mW in some applications) and ca n be used for powe ring other devices in the system. This allows the
most flexibility when interfacing to sensors and other analog signals which typically require a higher supply
voltage than a single-cell battery can provide.
Figure 16.1 shows a block diagram of the dc-dc converter. During normal operation in the first half of the
switching cycle, the Duty Cycle Control switch is closed and the Diode Bypass switch is open. Since the
output voltage is higher than the voltage at the DCEN pin, no current flows through the diode and the load
is powered from the output capacitor. During this stage, the DCEN pin is connected to ground through the
Duty Cycle Control switch, generating a positive voltage across the inductor and forcing it s cur rent to ramp
up.
In the second half of the switching cycle, the Duty Cycle control switch is opened and the Diode Bypass
switch is closed. This connects DCEN directly to VDD/DC+ and forces the inductor current to charge the
output capacitor. Once the inductor transfers its stored energy to the output capacitor , the Duty Cycle Con-
trol switch is closed, the Diode Bypass switch is opened, and the cycle repeats.
The dc-dc converter has a built in voltage reference and oscillator, and will automatically limit or turn off the
switching activity in case the peak inductor current rises beyond a safe limit or the output voltage rises
above the programmed target value. This allows the dc-dc converter output to be safely overdriven by a
secondary power source (when available) in order to preserve battery life. The dc-dc converter ’s settings
can be modified using SFR registers which provide the ability to change the target output voltage, oscillator
frequency or source, Diode Bypass switch resistance, peak inductor current, and minimum duty cycle.
Figure 16.1. DC-DC Converter Block Diagram
VBAT
VDD/DC+
DCEN
GND/DC-GND
1uF Cload
Iload
Control Logic
Duty
Cycle
Control
Diode
Bypass
0.68 uH
DC/DC Converter
DC0CF
DC0CN
DC/DC
Oscillator
Voltage
Reference
Lparasitic
4.7 uF
Lparasitic
DC0MD
Rev. 1.1 161
C8051F91x-C8051F90x
16.1. Startup Behavior
On initial power-on, the dc-dc converter outputs a constant 50% duty cycle until there is sufficient voltage
on the output cap acito r to main tain regulation. The size of the output capacitor and the amount of load cur-
rent present during startup will determine the length of time it takes to charge the output capacitor.
During initial power-on reset, the maximum peak inductor cur re n t th re sh old , wh ich trig ge rs the ov er cu rr en t
protection circuit, is set to approximately 125 mA. This generates a “soft-start” to limit the output voltage
slew rate and prevent excessive in-rush current at the output capacitor. In order to ensure reliable startup
of the dc-dc converter, the following restrictions have been impo sed:
• The maximum dc load current allowed during startup is given in Table 4.16 on page 60. If the dc-dc
converter is powering external sensors or devices through the VDD/DC+ pin or through GPIO pins,
then the current supplied to these sensors or devices is counted towards this limit. The in-rush current
into capacitors does not count towards this limit.
• The maximum total output capacitance is given in Table 4.16 on page 60. This value includes the
required 1 µF ceramic output capacitor and any additional capacitance connected to the VDD/DC+ pin.
Once initial power-on is complete , the peak inductor current limit ca n be incr eased by sof tware as shown in
Table 16.1. Limiting the peak inductor current can allow the device to start up near the battery’s end of life.
.
The peak inductor current is dependent on several factors including the dc load current and can be esti-
mated using following equation:
efficiency = 0.80
inductan ce = 0.68 µH
frequency = 2.4 MHz
Table 16.1. IPeak Inductor Current Limit Settings
SWSEL ILIMIT Peak Current (mA)
Normal Power Mode Peak Current (mA)
Low Power Mode
1 0 100 75
1 1 125 100
0 0 250 125
0 1 500 250
IPK 2 ILOAD VDD/DC+ VBAT–
efficiency inductancefrequency
-------------------------------------------------------------------------------------------=
C8051F91x-C8051F90x
162 Rev. 1.1
16.2. High Power Applications
The dc-dc converter is designed to provide the system with 65 mW of output power, however, it can safely
provide up to 100 mW of output power without any risk of damage to the device. For high power applica-
tions, the system should be carefully designed to prevent unwanted VBAT and VDD/DC+ Supply Monitor
resets, which are more likely to oc cur when the dc-dc converter output power exceeds 65mW. In addition,
output powe r abov e 65 mW causes the dc-dc converter to have relaxed output regulation, high output rip-
ple and more analog noise. At high output power, an inductor with low DC resistance shou ld be chosen in
order to minimize power loss and maximize efficiency.
The combination of high output power and low input voltage will result in very high peak and average
inductor currents. If the power supply has a high internal resistance, the transient voltage on the VBAT ter-
minal could drop below 0.9 V and trigger a VBAT Supply Monitor Reset, even if the open-circuit voltage is
well above the 0.9 V threshold. While this problem is most often associated with operation from very small
batteries or batteries that are near the end of their useful life, it can also occur when using bench power
supplies that have a slow transie nt resp onse; th e supply’s display may indicate a voltage above 0.9 V, but
the minimum volta ge on the VBAT pin may be lower. A similar problem can occur at the outp ut of the dc-dc
converter: using the default low current limit setting (125 mA) ca n trigger VDD Supply Monitor reset s if there
is a high transient load current, particularly if the programmed output voltage is at or near 1.8 V.
16.3. Pulse Skipping Mode
The dc-dc converter allows the user to set the minimum pulse width such that if the duty cycle needs to
decrease below a certain width in order to maintain regulation, an entire "clock pulse" will be skipped.
Pulse skipping can provide substantial power savings, particularly at low values of load current. The con-
verter will continue to maintain a minimum output voltage at its programmed value when pulse skipping is
employed, though the o utput volt age ripple can be higher. Another cons ideration is that the dc-d c will ope r-
ate with pulse-frequency modulation rather than pulse-width modulation, which makes the switching fre-
quency spectrum less predictable; this could be an issue if the dc-dc converter is used to power a radio.
Figure 4.5 and Figure 4.6 on page 45 and 46 show the effect of pulse skipping on power con sum p tio n.
Rev. 1.1 163
C8051F91x-C8051F90x
16.4. Enabling the DC-DC Converter
On power-on reset, the state of the DCEN pin is sampled to determine if the device will power up in one-
cell or two-cell mode. In two-cell mode, the dc-dc converter always remains disabled. In one-cell mode, the
dc-dc converter remains disabled in Sleep Mode, and enabled in all other power modes. See Section
“14. Power Management” on page 143 for complete details on available power modes.
The dc-dc converter is enabled (one-cell mode ) in hardware by placing a 0.68 µH inductor between DCEN
and VBAT. The dc-dc converter is disabled (two-cell mode) by shorting DCEN directly to GND. The DCEN
pin should never be left floating. The device can only switch between one-cell and two-cell mode during a
power-on reset. See Section “18. Reset Sources” on p age 171 for more information re garding reset behav-
ior.
Figure 16.2 shows the two dc-dc converter configuration options.
Figure 16.2. DC-DC Converter Configuration Options
When the dc-dc converter “Enabled” configuration (one-cell mode) is chosen, the following guidelines
apply:
• In most cases, the GND/DC– pin should not be externally connected to GND.
• The 0.68 µH inductor should be placed as close as possible to the DCEN pin for maximum efficiency.
•The 4.7 µF capacitor should be placed as close as possible to the inductor.
• The current loop including GND, the 4.7 µF capacitor, the 0.68 µH inductor and the DCEN pin should
be made as short as possible.
• The PCB traces connecting VDD/DC+ to the output capacitor and the output capacitor to GND/DC–
should be as short and as thick as possible in order to minimize parasitic inductance.
VBAT VDD/DC+
DCEN GND/DC-
1uF
0
.
68 uH
GND
4.7 uF
VBAT VDD/DC+
DCEN GND/DC-
GND
DC-DC Converter
Enabled
0.9 to 3.6 V (‘F912/ 02 )
0.9 to 1.8 V (‘F911/01)
Supply Voltage
(one-cell mode)
DC-DC Converter
Disabled
1.8 to 3.6 V
Supply Voltage
(two-cell mode)
C8051F91x-C8051F90x
164 Rev. 1.1
16.5. Minimizing Power Supply Noise
To minimize noise on the power supply lines, the GND and GND/DC- pins should be kept separate, as
shown in Figure 16.2; one or the other should be conn ected to the pc board gr ound plane. Fo r applica tions
in which the dc-dc converter is used only to power internal circuits, the GND pin is normally connected to
the board ground.
The large decoupling capacitors in the input and output circuits ensure that each supply is relatively quiet
with respect to its own ground. However, connecting a circuit element "diagonally" (e.g. connecting an
external chip between VDD/DC+ and GND, or between VBAT and GND/DC-) can result in high supply
noise across that circuit element. For applications in which the dc-dc converter is used to power extern al
analog circuitry, it is recommended to connect the GND/DC– pin to the board ground and connect the bat-
tery’s negative terminal to the GND pin only, which is not connected to board ground.
To accommodate situations in which ADC0 is sampling a signal that is referenced to one of the external
grounds, we recommend using the Analog Ground Reference (P0.1/AGND) option described in Section
5.12. This option prevents any voltage differences between the internal chip ground and the external
grounds from modulating the ADC input signal. If this option is enabled, the P0.1 pin should be tied to the
ground reference of the external analog input signal. When using the ADC with the dc-dc converter, we
also recommend enabling the SYNC bit in the DC0CN register to minimi ze interference.
These general guidelines provide the best performance in most applications, though some situations may
benefit from experimentation to eliminate any residual noise issues. Examples might include tying the
grounds to gether, using additional low-in ductan ce decoupling cap s in parallel with the recommended ones,
investigating the effects of different dc-dc converter settings, etc.
16.6. Selecting the Optimum Switch Size
The dc-dc converter has two built-in switches (the diode bypass switch and duty cycle control switch). To
maximize efficiency, one of two switch sizes may be selected. The large switches are ideal for carrying
high currents and the small switches are ideal for low current applications. The ideal switchover point to
switch from the small switches to the large switches varies with the programmed output voltage. At an out-
put voltage of 2 V, the ideal switchover point is at approximately 4 mA total output current. At an output
voltage of 3 V, the ideal switchover point is at approximately 8 mA total output current.
16.7. DC-DC Converter Clocking Options
The dc-dc converter may be clocked from its internal oscillator, or from any system clock source, select-
able by the CLKSEL bit (DC0CF.0). The dc-dc converter internal oscillator frequency is approximately
2.4 MHz. For a more accurate clock source, the system clock, or a divided version of th e system clock may
be used as the dc-dc clock source. The dc-dc converter has a built in clock divider (configured using
DC0CF[6:5]) which allows any system clock frequency over 1.6 MHz to generate a valid clock in the range
of 1.6 to 3.2 MHz.
When the precision internal oscillator is selected as the system clock source, the OSCICL register may be
used to fine tune the oscillator frequency and the dc-dc converter clock. The oscillator frequency should
only be decreased since it is factory calibrated at its maximum frequency. The minimum frequency which
can be reached by the oscillator after taking into account process variations is approximately 16 MHz. The
system clock routed to the dc-dc converter clock divider also may be inverted by setting the CLKINV bit
(DC0CF.3) to logic 1. These options can be used to minimize interference in noise sensitive applications.
16.8. DC-DC Converter Behavior in Sleep Mode
When the C8051F91x-C8051F90x devices a re placed in Sleep mode, the dc-dc converter is disabled, an d
the VDD/DC+ output is internally connected to VBAT by default. This behavior ensures that the GPIO pins
are powered from a low-impedance source during sleep mode. If the GPIO pins are not used as inputs or
Rev. 1.1 165
C8051F91x-C8051F90x
outputs during sleep mode, then the VDD/DC+ output can be made to float during Sleep mode by setting
the VDDSLP bit in the DC0CF register to 1.
Setting this bit can provide power savings in two ways. First, if the sleep interval is relatively short and the
VDD/DC+ load current (include leakage currents) is negligible, then the capacitor on VDD/DC+ will main-
tain the output volt age near the programmed value, which means that the VDD/DC+ cap acitor will not need
to be recharged upon every wake up ev ent. The second po wer advantage is that intern al or external low-
power circuits that require more than 1.8 V can continue to function during Sleep mode without operating
the dc-dc converter, powered by the energy stored in the 1 µF output decoupling capacitor. For example,
the C8051F91x-C8051F90 x comp ar ators require a bout 0.4 µA when operating in their lowest power mode.
If the dc-dc conve rter output were incr eased to 3.3 V just before putting the device into Sleep mode, then
the comparator could be powered for more than 3 seconds before the output voltage dropped to 1.8 V. In
this example, the overall energy consum ption would be much lower than if the dc-dc converter were kept
running to power the comparator.
If the load current on VDD/DC+ is high enough to discharge the VDD/DC+ capacitance to a voltage lower
than VBAT during the sleep interval, an internal diode will prevent VDD/DC+ from dropping more than a
few hundred millivolts below VBAT. There may be some additional leakage current from VBAT to ground
when the VDD/DC+ level falls below VBAT, but this leakage current should be small compared to the cur-
rent from VDD/DC+.
The amount of time that it takes for a device configured in one-cell mode to wake up from Sleep mode
depends on a number of factors, including the dc-dc converter clock speed, the settings of the SWSEL,
ILIMIT, and LPEN bits, the battery internal resistance, the load current, and the difference between the
VBAT voltage level and the prog rammed output volt a ge. The wake up time can be as shor t as 2 µs, though
it is more commonly in the range of 5 to 10 µs, and it can exce ed 50 µs under extreme conditions.
See Section “14. Power Management” on page 143 for more information about sleep mode.
16.9. Bypass Mode (C8051F912/02 only)
During normal operation, if the dc-dc converter input voltage exceeds the programmed output voltage, the
converter will stop switching and the Diode Bypass switch will remain in the “on” state. The output voltage
will be equal to the input voltage minus any resistive loss in the switch and all of the converter’ s analog cir-
cuits will remain biased. The bypass feature automatically shuts off the dc-dc converter when the input
voltage is gre ater than the programme d output voltage by 150 mV. In bypass, the Diode Bypass switch and
dc-dc conver ter bias curren ts are disabled except for the voltage comparison circuitry (~ 3 µA, depending
on the configuration settings in the DC0MD register). If the input voltage drops within 50 mV of the pro-
grammed output value, th en the dc-dc converter automatically st art s operating in th e normal st ate. There is
100 mV voltage hysteresis built in the bypass comparator to enhance stability.
The bypass mode increases system operating time in systems which have a minimum operating voltage
higher than the batter y end of life vo ltage. For instance, if an exte rnal ch ip re qu ires a min imum supply volt -
age of 2.7 V and a lithium coin cell battery is used as power source (end-of-life voltage is approximately
2 V), then the C8051F912/902’s dc-dc converter could be configured for an output voltage of 2.7 V with
bypass mode enabled. The dc-dc converter would be bypassed when the battery was fresh, bu t as soon
as the battery voltage dropped below 2.75 V, the dc-dc converter would turn on to en su re th a t th e ext er n al
chip was provided with a minimum of 2.7 V for the remainder of the ba tt er y life.
16.10. Low Power Mode (C8051F912/02 only)
Setting the LPEN bit in the DC0CF register will enable a Low Power Mode for the dc-dc converter. In Low
Power Mode, th e bias curren ts are subst antially redu ced, which can lead to an ef ficiency improvement with
light load currents (generally less than a few mA). The drawback to this mode is that the response time of
the converter ’s analog blocks is increased; larger delay in the circuits controlling the Diode Bypass switch
can lead to loss of efficiency at medium and high load currents due to reverse leakage in the switch. The
Low power mode also reduces the peak inductor current limit as shown in Table 16.1.
C8051F91x-C8051F90x
166 Rev. 1.1
16.11. Passive Diode Mode (C8051F912/02 only)
Setting the EXTDEN bit in DC0MD enables the Passive Diode Mode. In this mode, the control circuits for
the Diode Bypass switch are disabled, which reduces the converter’s quiescent operating current. An
external Schottky diode may be connected between the DCEN (anode) and VDD/DC+ (cathode) pins.
Under light load conditions, an external diode is typically not required. There are two situations in which
this mode can prove beneficial. First is with very light load currents, where the efficiency is dominated by
the converter ’s quiescent current. The converter will use an internal p-n junction diode to transfer current
from the inductor to the output capacitor; although there is a larger voltage drop (and power loss) across a
passive diode, the overall efficiency may be improved due to the reduction in quiescent current. The sec-
ond situation is when output power is very high. In that case, efficiency can suffer because some reverse
current can flow in the Diode Bypass switch before the control circuitry turns the switch off. Putting the
device in Passive Diode Mode and optionally connecting an external Schottky diode between the DCEN
and VDD/DC+ pins (parallel to the internal diode) may provide higher efficiency in some applications than
using the internal Diode Bypass switch.
Rev. 1.1 167
C8051F91x-C8051F90x
16.12. DC-DC Converter Register Descriptions
The SFRs used to configure the dc-dc converter are described in the following register descriptions. The
reset values fo r these registers can be us ed as-is in most systems; ther efore, no software interventio n or
initialization is required.
SFR Page = 0x0; SFR Address = 0x97
SFR Definition 16.1. DC0CN: DC-DC Converter Control
Bit76543210
Name MINPW SWSEL Reserved SYNC VSEL
Type R/W R/W R/W R/W R/W
Reset 00100001
Bit Name Function
7:6 MINPW[1:0] DC-DC Converter Minimum Pulse Width.
Specifies the minimum pulse width.
00: No minimum du ty cycle.
01: Minimum pulse width is 20 ns.
10: Minimum pulse width is 40 ns.
11: Minimum pulse width is 80 ns.
5SWSEL DC-DC Converter Switch Select.
Selects on e of two possible converter switch sizes to maximize efficiency.
0: The large switches are selected (best efficiency for high output current s).
1: The small switches are selected (best efficiency for low output currents).
4Reserved Reserved. Always Write to 0.
3SYNC ADC0 Synchronization Enable.
When synchronization is enabled, the ADC0SC[4:0] bits in the ADC0CF register
must be set to 00000b.
0: The ADC is not synchronized to the dc-dc converter.
1: The ADC is synchronized to the dc-dc converter. ADC0 tracking is performed
during the long est quiet time of the dc-dc converter switching cycle and ADC0 SAR
clock is also synchronized to the dc-dc converter switching cycle.
2:0 VSEL[2:0] DC-DC Converter Output Voltage Select.
Specifies the target output voltag e.
000: Target output voltage is 1.8 V.
001: Target output voltage is 1.9 V.
010: Target output voltage is 2.0 V.
011: Target output voltage is 2.1 V.
100: Target output voltage is 2.4 V.
101: Target output voltage is 2.7 V.
110: Target output voltage is 3.0 V.
111: Target output voltage is 3.3 V.
C8051F91x-C8051F90x
168 Rev. 1.1
SFR Page = 0x0; SFR Address = 0x96
SFR Definition 16.2. DC0CF: DC-DC Converter Configuration
Bit 7 6 5 4 3 2 1 0
Name LPEN CLKDIV[1:0] AD0CKINV CLKINV ILIMIT VDDSLP CLKSEL
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit Name Function
7LPEN Low Power Mode Enable.
Enables the dc-dc low power mode which reduces bias currents, reduces peak
inductor current, and increases efficiency for low load currents. Only available on
‘F912 and ‘F902 devices.
0: Low Power Mode Disabled .
1: Low Power Mode Enabled.
6:5 CLKDIV[1:0] DC-DC Clock Divider.
Divides the dc-dc converter clock when the system clock is selected as the clock
source for dc-dc converter. These bits are ignored when the dc-dc co nverter is
clocked from its local oscillator.
00: The dc-dc converter clock is system clock divided by 1.
01: The dc-dc converter clock is system clock divided by 2.
10: The dc-dc converter clock is system clock divided by 4.
11: The dc-dc converter clock is system clock divided by 8.
4AD0CKINV ADC0 Clock Inve rsi on (Cl o ck Invert During Sync).
Inverts the ADC0 SAR clock derived fr om the dc-dc converte r clock when the SYNC
bit (DC0CN.3) is enabled. This bit is ignored when the SYNC bit is set to zero.
0: ADC0 SAR clock is inverted.
1: ADC0 SAR clock is not inverted.
3CLKINV DC-DC Converter Clock Invert.
Inverts the system clock used as the input to the dc-dc clock divider.
0: The dc-dc converter clock is not inverted.
1: The dc-dc converter clock is inverted.
2ILIMIT Peak Current Limit Threshold.
Sets the threshold for the maximum allowed peak inductor current according to
Table 16.1.
1VDDSLP VDD-DC+ Sleep Mode Connection.
S pe cifies the power sour ce for VDD/DC+ in Sleep Mode when the dc-dc converter is
enabled.
0: VDD-DC+ connected to VBAT in Sleep Mode.
1: VDD-DC+ is floating in Sleep Mode.
0CLKSEL DC-DC Converter Clock Source Select.
Specifies the dc-dc converter clock source.
0: The dc-dc converter is clocked from its local oscillator.
1: The dc-dc converter is clocked from the system clock.
Rev. 1.1 169
C8051F91x-C8051F90x
SFR Page = 0xF; SFR Address = 0x94
16.13. DC-DC Converter Specifications
See Table 4.16 on page 60 for a detailed listing of dc-dc conve rter specifications.
SFR Definition 16.3. DC0MD: DC-DC Mode
Bit 7 6 5 4 3 2 1 0
Name BYPFLG BYPSEL[1:0] PASDEN
Type R/W R/W R/W R/W R R/W R/W
Reset 0 0 0 0 Varies 0 0 0
Bit Name Function
7:4 Unused Unused.
Read = 0000b, W rite = don’t care.
3BYPFLG Bypass Indicator.
Indicates when the dc-dc converter is operating in bypass mode. Only available on
‘F912 and ‘F902 devices.
0: DC0 is not operating in bypass mode.
1: DC0 is operating in bypass mode.
2:1 BYPSEL[1:0] Bypass Mode Select.
Selects the bypass settings. Only available on ‘F912 and ‘F902 devices.
00: Bypass mode disabled (highest supply current when the input voltage exceeds
the programmed output voltage).
01: Bypass enabled (auto switch), dc-dc oscillator enabled (fast response time)
10: Bypass enabled (auto switch), dc-dc oscillator disabled (reduced supply current)
11: The dc-dc converter is forced into bypass mod e (lowest supply current wh en the
input voltage exceeds the programmed output voltage).
0PASDEN Passive Diode Mode Enable.
Passive external diode mode. Only available on ‘F912 and ‘F902 devices.
0: Passive diode mode disabled.
1: Passive diode mode enabled.
C8051F91x-C8051F90x
170 Rev. 1.1
17. Voltage Regulator (VREG0)
C8051F91x-C8051F90x devices include an internal voltage regulator (VREG0) to regulate the internal
core supply to 1.8 V from a VDD/DC+ supply of 1.8 to 3.6 V. Electrical characteristics for the on-chip
regulator are specifie d in the Electrical Specifications chapter.
The REG0CN register allows the Precision Oscillator Bias to be disabled, reducing supply current in all
non-Sleep power modes. This bias should only be disabled when the precision oscillator is not being used.
The internal regulator (VREG0) is disabled when the device enters Sleep Mode and remains enabled
when the devi ce enters Suspend Mo de. See Section “14. Power Management” on page 143 for complete
details about low power mod es.
SFR Page = 0x0; SFR Address = 0xC9
17.1. Voltage Regulator Electrical Specifications
See Table 4.15 on page 59 for detailed Voltage Regulator Electrical Specifications.
SFR Definition 17.1. REG0CN: Voltage Regulator Control
Bit76543210
Name Reserved Reserved OSCBIAS Reserved
Type R R/W R/W R/W R R R R/W
Reset 00010000
Bit Name Function
7Unused Unused.
Read = 0b. Write = Don’t care.
6Reserved Reserved.
Read = 0b. Must W rite 0b.
5Reserved Reserved.
Read = 0b. Must W rite 0b.
4OSCBIAS Precision Oscillator Bias.
When set to 1, the bias used by the precision oscillator is forced on. If the precision
oscillator is not being used, this bit may be cleared to 0 to save approximately 80 µA
of supply current in all non-Sleep power modes. If disabled then re-enabled, the pre-
cision oscillator bias requires 4 µs of settling time.
3:1 Unused Unused.
Read = 000b. Write = Don’t care.
0Reserved Reserved.
Read = 0b. Must W rite 0b.
Rev. 1.1 171
C8051F91x-C8051F90x
18. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
• CIP-51 halts program execution
• Special Function Registers (SFRs) are initial ized to their defined reset values
• External Port pins are forced to a known state
• Interrupts and timers are disabled
All SFRs are reset to the predefined values noted in the SFR descriptions. The contents of RAM are
unaffected during a reset; any previously stored data is preserved as long as power is not lost. Since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled
during and after the reset. For VDD Monitor and power-on resets, the RST pin is driven low until the device
exits the re set state.
On exit from the reset st ate, the program counter (PC) is reset, and the system clock defaults to an internal
oscillator. Refer to Section “19. Clocking Sources” on page 179 for information on selecting and
configuring the system clock source. The Watchdog Timer is enabled with the system clock divided by 12
as its clock source (Section “26.4. Watchdog Timer Mode” on page 304 details the use of the Watchdog
Timer). Program execution begins at location 0x0000.
Figure 18.1. Reset Sources
PCA
WDT
Missing
Clock
Detector
(one-
shot) (Software Reset)
System Re set
Reset
Funnel
Px.x
Px.x
EN SWRSF
System
Clock CIP-51
Microcontroller
Core
Extended Interrupt
Handler
EN
WDT
Enable
MCD
Enable
Illegal Flash
Operation
RST
(wired-OR)
'0'
+
-
Comparator 0
VDD/DC+
+
-
Supply
Monitor
Enable
SmaRTClock RTC0RE
C0RSEF
Power-On Reset
Power Management
Block (PMU0)
System Reset
VBAT
Power On
Reset
Reset
C8051F91x-C8051F90x
172 Rev. 1.1
18.1. Power-On (VBAT Supply Monitor) Reset
During power-up, the device is held in a reset state and the RST pin is driven low until VBAT settles above
VPOR. An additional delay occurs before the device is released from reset; the delay decreases as the
VBAT ramp time increases (VBAT ramp time is defined as how fast VBAT ramps from 0 V to VPOR).
Figure 18.3 plots the power-on and VDD monitor reset timing. For valid ramp times (less than 3 ms), the
power-on reset delay (TPORDelay) is typically 3 ms (VBAT = 0.9 V), 7 ms (VBAT = 1.8 V), or 15 ms (VBAT =
3.6 V).
Note: The maximum VDD ramp time is 3 ms; slower ramp times may cause the device to be released from reset
before VBAT reaches the VPOR level.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000), software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be un defined after a power-on reset.
On ‘F912 and ‘F902 devices, the VBAT supply monitor can be disabled to save power by writing ‘1’ to the
MONDIS (PMU0MD.5) bit. When the VBAT supply monitor is disabled, all reset sources will trigger a full
POR and will re-enable the VBAT supply monitor.
Figure 18.2. Power-Fail Reset Timing Diagram
Power-On
Reset Power-On
Reset
RST
t
volts
~0.5
0.6
Logic HIGH
Logic LO W TPORDelay
VBAT
~0.8 VPOR
VBAT
See specificati on
table for min/max
voltages.
TPORDelay
Rev. 1.1 173
C8051F91x-C8051F90x
18.2. Power-Fail (VDD/DC+ Supply Monitor) Reset
C8051F91x-C 8051 F90x device s have a VDD /DC+ Su pply Monitor that is enabled and selected as a reset
source after each power-on or power-fail reset. When enabled and selected as a reset source, any power
down transit ion or power irregularity that causes VDD/DC+ to drop below VRST will cause the RST pin to
be driven low and the CIP-51 will be held in a reset state (see Figure 18.3). When VDD/DC+ returns to a
level above VRST, the CIP-51 will be released from the reset state.
After a power-fail reset, the PORSF flag reads 1, the contents of RAM invalid, and the VDD/DC+ supply
monitor is enabled and selected as a reset source. The enable state of the VDD/DC+ supply monitor and
its selection as a reset source is only altered by power-on and power-fail resets. For example, if the
VDD/DC+ supply monitor is de-selected as a reset source and disabled by software, then a software reset
is performed, the VDD/DC+ supply monitor will remain disabled and de-selected af ter the reset.
In battery-operated systems, the contents of RAM can be preserved near the end of the battery’s usable
life if the device is placed in Sleep Mode prior to a power-fail reset occurring. When the device is in Sleep
Mode, the power-fail reset is automatically d isabled and the contents of RAM are preserved as long as the
VBAT supply does not fall below VPOR. A large capacitor can be used to hold the power supply voltage
above VPOR while the user is replacing the battery. Upon waking from Sleep mode, the enable and reset
source select state of the VDD/DC+ su pp ly mon itor are restored to the value last set by the user.
To allow software early notification that a power failure is about to occur, the VDDOK bit is cleared when
the VDD/DC+ supply falls below the VWARN threshold. The VDDOK bit can be configured to generate an
interrupt. See Section “12. Interrupt Handler” on page 120 for mo re details.
Important Note: To protect the integrity of Flash contents, the VDD/DC+ supply monitor must be
enabled and selected as a reset source if software contains routines which erase or write Flash
memory. If the VDD/DC+ supply monitor is not enabled, any erase or write performed on Flash memory
will cause a Flash Error device reset.
Figure 18.3. Power-Fail Reset Timing Diagram
t
volts
VRST
VDD/DC+
VPOR
VDDWARN
VBAT
Note: Wake up signal
required after new
battery insertion
VDDOK
SLEEP
RST
Active Mode
P o we r -F ail R eset Sleep Mode
RAM Retained - No Reset
VBATWARN
C8051F91x-C8051F90x
174 Rev. 1.1
Important Notes:
• The Power-on Reset (POR) delay is not incurred after a VDD/DC+ supply monitor reset. See Section
“4. Electrical Characteristics” on page 36 for complete electrical characteristics of the VDD/DC+ moni-
tor.
• Software should take care not to inadvertently disable the VDD Monitor as a reset so ur ce when wr itin g
to RSTSRC to enable other reset sources or to trigger a software reset. All writes to RSTSRC should
explicitly set PORSF to 1 to keep the VDD Monitor enabled as a rese t source.
• The VDD/DC+ supply monitor must be enabled before selecting it as a reset source. Selecting the
VDD/DC+ supply monitor as a reset source before it has stabilized may generate a system reset. In
systems where this reset would be undesirable, a delay should be introduced between enabling the
VDD/DC+ supply monitor and selecting it a s a reset source. See Section “4. Electrical Characte ristics”
on page 36 for minimum VDD/DC+ Supply Monitor turn-on time. No delay should be intro duced in
systems where software contains routines that erase or write Flash memory. The pr ocedure for
enabling the VDD/DC+ supply monitor and selecting it as a reset source is shown below:
1. Enable the VDD/DC+ Supply Monitor (VDMEN bit in VDM0CN = 1).
2. Wait for the VDD/DC+ Supply Monitor to stabilize (optional).
3. Select the VDD/DC+ Supply Monitor as a reset source (PORSF bit in RSTSRC = 1).
Rev. 1.1 175
C8051F91x-C8051F90x
SFR Page = 0x0; SFR Address = 0xFF
SFR Definition 18.1. VDM0CN: VDD/DC+ Supply Monitor Control
Bit 7 6 5 4 3 2 1 0
Name VDMEN VDDSTAT VDDOK VBATOK VDDOKIE VBATOKIE
Type R/W R R R R/W R/W R/W R/W
Reset 1 Varies Varies Varies 1 0 0 0
Bit Name Function
7VDMEN VDD/DC+ Supply Monitor Enable.
This bit turns the VDD/DC+ supply monitor circuit on/off. The VDD/DC+ Supply
Monitor cannot gene ra te syste m re sets until it is also selected as a reset source in
register RSTSRC (SFR Definition 18.2).
0: VDD/DC+ Supply Monitor Disabled.
1: VDD/DC+ Supply Monitor Enabled.
6VDDSTAT VDD/DC+ Supply Status.
This bit indicates the current power supp ly status.
0: VDD/DC+ is at or below the VRST threshold.
1: VDD/DC+ is above the VRST threshold.
5VDDOK VDD/DC+ Supply Status (Early Warning).
This bit indicates the current VDD/DC+ power supply status.
0: VDD/DC+ is at or below the VDDWARN threshold.
1: VDD/DC+ is above the VDDWARN threshold.
4VBATOK VBAT Supply Status (Early Warning).
This bit indicates the curr ent VBAT power supply status. This bit is only p resent on
‘F912 and ‘F902 devices.
0: VBAT is at or below the VBATWARN threshold.
1: VBAT is above the VBATWARN threshold.
3VDDOKIE VDD/DC+ Early Warning Interrupt Enable.
Enables the VDD/DC+ Early W arning Interrupt. This bit only has an effect on ‘F912
and ‘F902 devices. All other devices behave as if this bit is set to 1.
0: VDD/DC+ Early Warning Interrupt is disabled.
1: VDD/DC+ Early Warning Interrupt is enabled.
2VBATOKIE VBAT Early Warning Interrupt Enable.
Enables the VBAT Early W arning Inter rupt. This bit only ha s an ef fect on ‘F912 and
‘F902 devices. All other devices behave as if this bit is set to 0.
0: VBAT Early Warning Interrupt is disabled.
1: VBAT Early Warning Interrupt is enabled.
1:0 Unused Unused.
Read = 00b. Write = Don’t Care.
C8051F91x-C8051F90x
176 Rev. 1.1
18.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state.
Asserting an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of
the RST pin may be necessary to avoid erroneous noise-induced resets. See Table 4.4 fo r complete RST
pin specifications. The exte rnal rese t remains functional even when the device is in the low power su spend
and sleep modes. The PINRSF flag (RSTSRC.0 ) is set on exit from an external reset.
18.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is t riggered by the s yst em clock . If the syst em
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; otherwise,
this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it.
The missing clock detector reset is automatically disabled when the device is in the low power suspend or
sleep mode. Upon exit from either low power state, the enabled/disabled state of this reset source is
restored to its previous valu e. The state of the RST pin is unaffected by this reset.
18.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparat or0 reset is activ e-low: if t he non -
inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0–), the device is put into
the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying
Comparator0 as the reset source; otherwise, this bit reads 0. The Comparator0 reset source remains
functional even when the device is in the low power suspend and sleep states as long as Comparator0 is
also enabled as a wake -u p so ur ce . Th e state of the RST pin is un affected by th is res et .
18.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “26.4. Watchdog Timer Mode” on
page 304; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to 1. The PCA Watchdog Timer reset source is automatically disabled when the device is in the low
power suspend or sleep mode. Upon exit from either low power state, the enabled/disabled state of this
reset source is restored to its previous value.The state of the RST pin is unaffected by this reset.
Rev. 1.1 177
C8051F91x-C8051F90x
18.7. Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
• A Flash write or e ra se is attemp te d abo ve user cod e space. This occurs when PSWE is set to 1 and a
MOVX write operation targets an address above the Lock Byte address.
• A Flash read is attempted ab ove user code space. This occurs when a MOVC operation targets an
address above the Lock Byte address.
• A Program read is attempte d above user code sp ac e. This occurs wh en user code attemp t s to branch
to an address above the Lock Byte address.
• A Flash read, write or erase attempt is restricted due to a Flash security setting (see Section
“13.3. Security Options” on page 134).
• A Flash write or erase is attempted while the VDD Monitor is disabled.
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The st ate of the RST p in is unaf fected by
this reset.
18.8. SmaRTClock (Real Time Clock) Reset
The SmaRTClock can generate a system reset on two events: SmaRTClock Oscillator Fail or
SmaRTClock Alarm. The SmaRTClock Oscillator Fail event oc curs when the SmaRTClock Missing Clock
Detector is enabled and the SmaRTClock clock is below approximately 20 kHz. A SmaRTClock alarm
event occurs when the SmaRTClock Alarm is enabled and the SmaRTClock timer value matches the
ALARMn registers. The SmaRTClock can be configured as a reset source b y writing a 1 to the RTC0RE
flag (RSTSRC.7). The SmaRTClock reset remains functional even when the device is in the low power
Suspend or Sleep mode. The state of the RST pin is unaffected by this reset.
18.9. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1
following a software forced reset. The state of the RST pin is unaffected by this reset.
C8051F91x-C8051F90x
178 Rev. 1.1
SFR Page = 0x0; SFR Address = 0xEF.
SFR Definition 18.2. RSTSRC: Reset Source
Bit76543210
Name RTC0RE FERROR C0RSEF SWRSF WDTRSF MCDRSF PORSF PINRSF
Type R/W R R/W R/W R R/W R/W R
Reset Varies Varies Varies Varies Varies Varies Varies Varies
Bit Name Description Write Read
7RTC0RE SmaRTClock Reset Enable
and Flag 0: Disable SmaRTClock
as a reset source.
1: Enable SmaRTClock as
a reset source.
Set to 1 if SmaRTClock
alarm or oscillator fail
caused the last reset.
6FERROR Flash Error Reset Flag. N/A Set to 1 if Flash
read/write/erase error
caused the last reset.
5C0RSEF Comparator0 Reset Enable
and Flag. 0: Disable Comparator0 as
a reset source.
1: Enable Comp arator0 as
a reset source.
Set to 1 if Comparator0
caused the last reset.
4SWRSF Software Reset Force and
Flag. Writing a 1 forces a sys-
tem reset. Set to 1 if last reset was
caused by a write to
SWRSF.
3WDTRSF Watchdog Timer Reset Flag. N/A Set to 1 if W atchdog T imer
overflow caused the last
reset.
2MCDRSF Missing Clock Detector
(MCD) Enable and Flag. 0: Disable the MCD.
1: Enable the MCD.
The MCD triggers a reset
if a missing clock condition
is detected.
Set to 1 if Missing Clock
Detector timeout caused
the last reset.
1PORSF Power-On / Power-Fail
Reset Flag, and Power-Fail
Reset Enable.
0: Disable the VDD/DC+
Supply Monitor as a reset
source.
1: Enable the VDD/DC+
Supply Monitor as a reset
source.3
Set to 1 anytime a power-
on or VDD monitor reset
occurs.2
0PINRSF HW Pin Reset Fl ag . N/A Set to 1 if RST pin caused
the last reset.
Notes:
1. It is safe to use read-modify-write operations (ORL, ANL, etc.) to enable or disable specific interrupt sources.
2. If PORSF read back 1, the value read from all othe r bits in this register are indeterminate.
3. Writing a 1 to PORSF before the VDD/DC+ Supply Monitor is stabilized may generate a system reset.
Rev. 1.1 179
C8051F91x-C8051F90x
19. Clocking Sources
C8051F91x-C8051F90x devices include a programmable precision internal oscillator, an external oscillator
drive circuit, a low power internal oscillator, and a SmaRTClock real time clock oscillator. The precision
internal oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as
shown in Figure 19.1. The external oscillator can be configured using the OSCXCN register. The low
power internal oscillator is automatically enabled and disabled when selected and deselected as a clock
source. SmaRTClock operation is described in the SmaRTClock oscillator chapter.
The system clock (SYSCLK) can be derived from the precision internal oscillator, external oscillator, low
power internal oscillator, or SmaRTClock oscillator. The global c lock divider can generate a system clock
that is 1, 2, 4, 8, 16, 32, 64, or 128 times slower that the selected input clock source. Os cillator electrical
specifications can be found in the Electrical Specifications Chapter.
Figure 19.1. Clocking Sources Block Diagram
The proper way of changing the system clock when both the clock source and the clock divide value are
being changed is as follows:
If switching from a fast “undivided” clock to a slower “undivided” cloc k:
a. Change the clock divide value.
b. Poll for CLKRDY > 1.
c. Change the clock source.
If switching from a slow “undivided” clock to a faster “undivided” clock:
a. Change the cloc k source.
b. Change the clock divide value.
c. Poll for CLKRDY > 1.
External
Oscillator
Drive Circuit
XTAL1
XTAL2
Option 2
VDD
XTAL2
Option 1
10M
Option 4
XTAL2
OSCXCN
XTLVLD
XOSCMD2
XOSCMD1
XOSCMD0
XFCN2
XFCN1
XFCN0
Precision
Internal Oscillator
EN
OSCICL OSCICN
IOSCEN
IFRDY
SYSCLK
CLKSEL
CLKDIV2
CLKDIV1
CLKDIV0
CLKRDY
CLKSL1
CLKSL0
Sm aRTC lock
Oscillator
Clock Divider
n
Low Pow er
Internal Oscillator
Low Power Internal O scillator
Sm aR T C lock Oscillator
Ex te rn a l O s c illato r
Precision Internal Oscillator CLKRDY
Option 3
XTAL2
C8051F91x-C8051F90x
180 Rev. 1.1
19.1. Programmable Precision Internal Oscillator
All C8051F91x-C8051F90x devices include a programmable precision internal oscillator that may be
selected as the system clock. OSCICL is factory calibrated to obtain a 24.5 MHz frequency. See Section
“4. Electrical Characteristics” on page 36 for complete oscillator specifications.
The precision oscillator supports a spread spectrum mode which modulates the output frequency in order
to reduce the EMI generated by the system. When enabled (SSE = 1), the oscillator output frequency is
modulated by a stepped triangle wave whose frequency is equal to the oscillator frequency divided by 384
(63.8 kHz using the factory calibration). The deviation from the nominal oscillator frequen cy is +0%, –1.6%,
and the step size is typically 0.26% of the nominal frequency. When using this mode, the typical average
oscillator frequency is lowered from 24.5 MHz to 24.3 MHz.
19.2. Low Power Internal Oscillator
All C8051F91x-C8051F90x devices include a low power internal oscillator that defaults as the system
clock after a system reset. The low power internal oscillator frequency is 20 MHz ± 10% and is automati-
cally enabled when selected as the system clock and disabled when not in use. See Section “4. Electrical
Characteristics” on page 36 for complete oscillator specifications.
19.3. External Oscillator Drive Circuit
All C8051F91x-C8051F90x devices include an external oscillator circuit that may drive an ex ternal crystal,
ceramic resonator, capacitor, or RC network. A CMOS clock may also provide a clock input. Figure 19.1
shows a block diagram of the four external oscillator options. The external oscillator is enabled and config-
ured using the OSCXCN register.
The external oscillator output may be selected as the system clock or used to clock some of the digital
peripherals (e.g. Timers, PCA, etc.). See the dat a sheet chapters for each digital periph eral for det ails. See
Section “4. Electrical Characteristics” on page 36 for complete oscillator specifications.
19.3.1. External Crystal Mode
If a crystal or ceramic resonator is used as the external oscillator, the crystal/resonator and a 10 Mresis-
tor must be wired across the XTAL1 and XTAL2 pins as shown in Figure 19.1, Option 1. Appropriate load-
ing capacitors should be added to XTAL1 and XTAL2, and both pins should be configured for analog I/O
with the digital output drivers disabled.
Figure 19.2 shows the external oscillator circuit for a 20 MHz quartz crystal with a manufacturer recom-
mended load capacitance of 12.5 pF. Loading capacitors are "in series" as seen by the crystal and "in par-
allel" with the stray capacitance of the XTAL1 and XTAL2 pins. The total value of the each loading
capacitor and th e stray cap acit ance of each XTAL pin should equal 12.5pF x 2 = 25 pF. With a stray capac-
itance of 10 pF per pin, the 15 pF capacitors yield an equivalent serie s capacitance of 12.5 pF across the
crystal.
Note: The recommended load cap acitance depends upon the crystal and the manufacturer. Please refer to the crystal
data sheet when completing these calculations.
Rev. 1.1 181
C8051F91x-C8051F90x
Figure 19.2. 25 MHz External Crystal Example
Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The
crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as
short as possible and shielded with ground plane from any other traces which could introduce noise or
interference.
When using an external crystal, the external oscillator drive circuit must be configured by sof tware for Crys-
tal Oscillator Mode or Cryst al Oscillator Mode with divide by 2 stage. T he divide by 2 st age ensures that the
clock derived from the external oscillator has a duty cycle of 50%. The External Oscillator Frequency Con-
trol value (XFCN) must also be specified based on the crystal frequency. The selection should be based on
Table 19.1. For example, a 25 MHz crystal requires an XFCN setting of 111b.
When the crystal oscillator is first enabled, the external oscillator valid detector allows software to deter-
mine when the external system clock has stabilized. Switching to the external oscillator before the crys tal
oscillator has stabilized can result in unpredictable behav ior. The recommended procedure for starting the
crystal is as follows:
1. Configure XTAL1 and XTAL2 for analo g I/O an d dis ab le th e dig i tal output drive r s.
2. Configure and enable the external oscillator.
3. Poll for XTLVLD => 1.
4. Switch the system clock to the external oscillator.
Table 19.1. Recommended XFCN Settings for Crystal Mode
XFCN Crystal Frequency Bias Current Typical Supply Current
(VDD = 2.4 V)
000 f 20 kHz 0.5 µA 3.0 µA, f = 32.768 kHz
001 20 kHz f 58 kHz 1.5 µA 4.8 µA, f = 32.768 kHz
010 58 kHz f 155 kHz 4.8 µA 9.6 µA, f = 32.768 kHz
011 155 kHz f 415 kHz 14 µA 28 µA, f = 400 kHz
100 415 kHz f 1.1 MHz 40 µA 71 µA, f = 400 kHz
101 1.1 MHz f 3.1 MHz 120 µA 193 µA, f = 400 kHz
110 3.1 MHz f 8.2 MHz 550 µA 940 µA, f = 8 MHz
111 8.2 MHz f 25 MHz 2.6 mA 3.9 mA, f = 25 MHz
15 pF
15 pF
25 MHz
XTAL1
XTAL2
10 Mohm
C8051F91x-C8051F90x
182 Rev. 1.1
19.3.2. External RC Mode
If an RC network is used as the external oscillator, the circuit should be configured as shown in
Figure 19.1, Option 2. The RC network should be added to XTAL2, and XTAL2 should be configured for
analog I/O with the digital output drivers disabled. XTAL1 is not affected in RC mode.
The capacitor should be no greater than 100 pF; however for ve ry small capacitors, the total capacitance
may be dominated by parasitic capacitance in the PCB layout. The resistor should be no smaller than
10 k. The oscillation frequency can be determined by the following equation:
where
f = frequency of clock in MHzR = pull-up resistor value in k
VDD = power supply voltage in VoltsC = capacitor value on the XTAL2 pin in pF
To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Regis ter,
first select the RC network value to produce the desired frequency of oscillation. For example, if the fre-
quency desired is 100 kHz, let R = 246 k and C = 50 pF:
where
f = frequency of clock in MHz R = pull-up resistor value in k
VDD = power supply voltage in Volts C = capacitor value on the XTAL2 pin in pF
Referencing Table 19.2, the recommended XFCN setting is 010.
Table 19.2. Recommended XFCN Settings for RC and C modes
XFCN Approximate
Frequency Range (RC
and C Mode)
K Factor (C Mode) Typical Supply Current/ Actual
Measured Frequency
(C Mode, VDD = 2.4 V)
000 f 25 kHz K Factor = 0.87 3.0 µA, f = 11 kHz, C = 33 pF
001 25 kHz f 50 kHz K Factor = 2.6 5.5 µA, f = 33 kHz, C = 33 pF
010 50 kHz f 100 kHz K Factor = 7.7 13 µA, f = 98 kHz, C = 33 pF
011 100 kHz f 200 kHz K Factor = 22 32 µA, f = 270 kHz , C = 33 pF
100 200 kHz f 400 kHz K Factor = 65 82 µA, f = 310 kHz, C = 46 pF
101 400 kHz f 800 kHz K Factor = 180 242 µA, f = 890 kHz, C = 46 pF
110 800 kHz f 1.6 MHz K Factor = 664 1.0 mA, f = 2.0 MHz, C = 46 pF
111 1.6 MHz f 3.2 MHz K Factor = 1590 4.6 mA, f = 6.8 MHz, C = 46 pF
f1.23 103
RC
-------------------------
=
f1.23 103
RC
-------------------------1.23 103
246 50
-------------------------100 kHz===
Rev. 1.1 183
C8051F91x-C8051F90x
When the RC oscillator is first enabled , the external oscillator valid detector allows software to determine
when oscillation has stabilized. The recommended procedure for starting the RC oscillator is as follows:
1. Configure XTAL2 for analog I/O and disable the digital output drivers.
2. Configure and enable the external oscillator.
3. Poll for XTLVLD => 1.
4. Switch the system clock to the external oscillator.
19.3.3. External Capacitor Mode
If a capacitor is used as the external oscillator, the circuit should be configured as shown in Figure 19.1,
Option 3. The capacitor should be added to XTAL2, and XTAL2 should be configured for analog I/O with
the digital output drivers disabled. XTAL1 is not affected in RC mode.
The capacitor should be no greater than 100 pF; however, for very small capacitors, the t otal capa citance
may be dominated by parasitic capacitance in the PCB layout. The oscillation frequency and the required
External Oscillator Frequency Control value (XFCN) in the OSCXCN Register can be determined by the
following equation:
where
f = frequency of clock in MHzR = pull-up resistor value in k
VDD = power supply voltage in VoltsC = capacitor value on the XTAL2 pin in pF
Below is an example of selecting the capacitor and finding the frequency of oscillation Assume VDD = 3.0 V
and f = 150 kHz:
Since a frequency of roughly 150 kHz is desired, select the K Factor from Table 19.2 as KF = 22:
Therefore, the XFCN value to use in this example is 011 and C is approximately 50 pF.
The recommended startup procedure for C mode is the same as RC mode.
fKF
CV
DD
---------------------
=
fKF
CV
DD
---------------------
=
0.150 MHz KF
C3.0
-----------------
=
0.150 MHz 22
C 3.0 V
-----------------------
=
C22
0.150 MHz 3.0 V
-----------------------------------------------
=
C 48.8 pF=
C8051F91x-C8051F90x
184 Rev. 1.1
19.3.4. External CMOS Clock Mode
If an external CMOS clock is used as the external oscillator, the clock should be directly routed into XTAL2.
The XTAL2 pin should be configured as a digital input. XTAL1 is not used in external CMOS clock mode.
The external oscillator valid detector will always return zero when the external oscillator is configured to
External CMOS Clock mode.
Rev. 1.1 185
C8051F91x-C8051F90x
19.4. Special Function Registers for Selecting and Configuring the System Clock
The clocking sources on C8051F91x-C8051F90x devices are enabled and configured using the OSCICN,
OSCICL, OSCXCN and the SmaRTClock internal registers. See Section “20. SmaRTClock (Real Time
Clock)” on page 188 for SmaRTClock register descriptions. The system clock source for the MCU can be
selected using the CLKSEL register. To minimize active mode current, the oneshot timer which sets Flash
read time should by bypassed when the system clock is greater than 10 MHz. See the FLSCL register
description for details.
The clock selected as the system clock can be divided by 1, 2, 4, 8, 16, 32, 64, or 128. When switching
between two clock divide values, the transition may take up to 128 cycles of the undivided clock source.
The CLKRDY flag can be polled to deter mine when the new clock divide value h as been applied. The clock
divider must be set to "divide by 1" when entering Suspend or Sleep Mode.
The system clock source may also be switched on-the-fly. The switchover takes effect after one clock
period of the slower oscillator.
SFR Page = All Pages; SFR Address = 0xA9
SFR Definition 19.1. CLKSEL: Clock Select
Bit76543210
Name CLKRDY CLKDIV[2:0] CLKSEL[2:0]
Type R R/W R/W R/W R/W R/W R/W R/W
Reset 00110100
Bit Name Function
7CLKRDY System Clock Div id e r Clo c k Rea d y F lag .
0: The selected clock di vide setting has not been applied to the system clock.
1: The selected clock divide setting has been applied to the system clock.
6:4 CLKDIV[2:0] System Clock Div id e r Bits.
Selects the clock division to be applied to the undivided system clock source.
000: System clock is divided by 1.
001: System clock is divided by 2.
010: System clock is divided by 4.
011: System clock is divided by 8.
100: System clock is divided by 16.
101: System clock is divided by 32.
110: System clock is divided by 64.
111: Syst em clock is divided by 128.
3Unused Unused.
Read = 0b. Must W rite 0b.
2:0 CLKSEL[2:0] System Clock Select.
Selects the oscillator to be used as the undivided system clock source.
000: Precision Internal Oscillator.
001: External Oscillator.
011: SmaRTClock Oscillator.
100: Low Power Oscillator.
All other values reserved.
C8051F91x-C8051F90x
186 Rev. 1.1
SFR Page = 0x0; SFR Address = 0xB2
Note: Read-modify-write operations such as ORL and ANL must be used to set or clear the enable bit of this register.
SFR Page = 0x0; SFR Address = 0xB3
SFR Definition 19.2. OSCICN: Internal Oscillator Control
Bit76543210
Name IOSCEN IFRDY Reserved[5:0]
Type R/W R R/W R/W R/W R/W R/W R/W
Reset 0 0 Varies Varies Varies Varies Varies Varies
Bit Name Function
7IOSCEN Internal Oscillat o r Enab le .
0: Internal oscillator disabled.
1: Internal oscillator enabled.
6IFRDY Internal Oscillator Frequency Ready Flag.
0: Internal oscillator is not running at its programmed frequency.
1: Internal oscillator is running at its programmed frequency.
5:0 Reserved Reserved.
Must perform read- modify-write.
SFR Definition 19.3. OSCICL: Internal Oscillator Calibration
Bit76543210
Name SSE OSCICL[6:0]
Type R/W R R/W R/W R/W R/W R/W R/W
Reset 0 Varies Varies Varies Varies Varies Varies Varies
Bit Name Function
7SSE Spread Spectrum Enable.
0: Spread Spectrum clock dithering disabled.
1: Spread Spectrum clock dithering enabled.
6:0 OSCICL Internal Oscillator Calibration.
Factory calibrated to obtain a frequency of 24.5 MHz. Incrementing this register
decreases the oscillator frequency and decrementing this register increases the
oscillator frequency. The step size is approximately 1% of the calibrated frequency.
The recommende d calibration frequency range is betwee n 16 and 24.5 MHz.
Rev. 1.1 187
C8051F91x-C8051F90x
SFR Page = 0x0; SFR Address = 0xB1
SFR Definition 19.4. OSCXCN: External Oscillator Control
Bit76543210
Name XCLKVLD XOSCMD[2:0] Reserved XFCN[2:0]
Type R R R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7XCLKVLD External Oscillator Valid Flag.
Provides External Oscillator status and is valid at all times for all modes of operation
except External CMOS Clock Mode and External CMOS Clock Mode with divide by
2. In these modes, XCLKVLD always returns 0.
0: External Oscillator is unused or not yet stable.
1: External Oscillator is running and stable.
6:4 XOSCMD External Oscillator Mode Bits .
Configures the external oscillator circuit to the selected mode.
00x: External Oscillator circuit disabled.
010: External CMOS Clock Mode.
011: External CMOS Clock Mode with divide by 2 stage.
100: RC Oscillator Mode.
101: Capacitor Oscillator Mode.
110: Crystal Oscillator Mode.
111: Crystal Oscillator Mode with divide by 2 stage.
3Reserved Reserved.
Read = 0b. Must W rite 0b.
2:0 XFCN External Oscillator Frequency Control Bits.
Controls the external oscillator bias current.
000-11 1 : See Table 19.1 on p age 181 (Crystal Mode) or Table 19.2 on page 182 (RC
or C Mode) for r ecommended settings.
C8051F91x-C8051F90x
188 Rev. 1.1
20. SmaRTClock (Real Time Clock)
C8051F91x-C8051F90x devices include an ultra low power 32-bit SmaRTClock Peripheral (Real Time
Clock) with alar m. The SmaRTCloc k has a ded icated 32 kHz oscillator that can be configured for us e with
or without a crystal. No external resistor or loading capacitors are required. The on-chip loading capacitors
are programmable to 16 discrete levels allowing compatibility with a wide range of crystals. The
SmaRTClo ck can operate directly from a 0.9–3.6 V battery voltage an d remains operationa l even when the
device goes into its lowest power down mode. On ‘F912 an d ‘F902 devices, th e SmaRTClock output can
be buffered and routed to a GPIO pin to provide an accurate, low frequency clock to other devices while
the MCU is in its lowest power down mo de (see “PMU0MD: Power Management Unit Mode” on page 150
for more details) . ‘F912 and ‘F902 devices also supp ort an ultr a low power inter nal LFO that reduce s sleep
mode current.
The SmaRTClock allows a maximum of 36 hour 32-bit independent time-keeping when used with a
32.768 kHz Watch Crystal. The SmaRTClock provides an Alarm and Missing SmaRTClock events, which
could be used as reset or wakeup sources. See Section “18. Reset Sources” on page 171 and Section
“14. Power Mana ge men t” o n page 143 for details on reset sources and low power mode wake-up sources,
respectively.
Figure 20.1. SmaRTClock Block Diagram
SmaRTClock Oscillator
SmaRTClock
CIP-51 CPU
XTAL4 XTAL3
RTC0CN
CAPTUREn
RTC0XCF
RTC0XCN
ALARMn
RTC0KEY
RTC0ADR
RTC0DAT
Interface
Registers
Internal
Registers
SmaRTClock State Machine
Wake-Up
32-Bit
SmaRTClock
Timer
Programmable Load Capacitors Power/
Clock
Mgmt
Interrupt
RTC0PIN
RTCOUT
Buffered clock output and LFO only
available on ‘F912 and ‘F902 devices.
LFO
Rev. 1.1 189
C8051F91x-C8051F90x
20.1. SmaRTClock Interface
The SmaRTClock Interface consists of three registers: RTC0KEY, RTC0ADR, and RTC0DAT. These
interface registers are located on the CIP-51’s SFR map and provide access to the SmaRTClock internal
registers listed in Table 20.1. The SmaRTClock internal registers can only be accessed indirectly through
the SmaRTClock Interfac e.
20.1.1. SmaRTClock Lock and Key Functions
The SmaRTClock Interface is protected with a lock and key function. The SmaRTClock Lock and Key
Register (RTC0KEY) must be written with the correct key codes, in sequence, before writes and reads to
RTC0ADR and RTC0DAT may be performed. The key codes are: 0xA5, 0xF1. There are no timing
restrictions, bu t the ke y code s must be w ritten in or der. If the key code s are writ ten ou t of ord er, the wro ng
codes are written, or an indirect register read or write is attempted while the interface is locked, the
SmaRTClock interface will be disabled, and the RTC0ADR and RTC0DAT registers will become
inaccessible until the next system reset. Once the SmaRTClock interface is unlocked, software may
perform any number of accesses to the SmaRTClock registers until the interface is re-locked or the device
is reset. Any write to RTC0KEY while the SmaRTClock interface is unlocked will re-lock the interface.
Reading the RTC0KEY register at any time will provide the SmaRTClock Interface status and will not
interfere with the sequence that is being written. The RTC0KEY register description in SFR Definition 20.1
lists the definition of each status code.
Table 20.1. SmaRTClock Internal Registers
SmaRTClock
Address SmaRTClock
Register Register Name Description
0x00–0x03 CAPTUREn SmaRTClock Capture
Registers Four Registers used for setting the 32-bit
SmaRTClock timer or reading its current value.
0x04 RTC0CN SmaRTClock Control
Register Co ntrols the operation of the SmaRTClock S t ate
Machine.
0x05 RTC0XCN SmaRTClock Oscillator
Control Register Controls the operation of the SmaRTClock
Oscillator.
Note: Some bits in this register are only available on
‘F912 and ‘F902 devices.
0x06 RTC0XCF SmaRTClock Oscillator
Configuration Register Controls the value of the progammable
oscillator load capacitance and
enables/disables AutoStep.
0x07 RTC0PIN SmaRTClock Pin
Configuration Register Forces XTAL3 and XTAL4 to be internally
shorted.
Note: This register also co n tains other reserved bits
which should not be modified.
0x08–0x0B ALARMn S maRTClock Alarm
Registers Four registers used for setting or reading the
32-bit SmaRTClock al arm value.
C8051F91x-C8051F90x
190 Rev. 1.1
20.1.2. Using RTC0ADR and RTC0DAT to Access SmaRTClock Internal Registers
The SmaRTClock internal registers can be read and written using RTC0ADR and RTC0DAT. The
RTC0ADR register selects the SmaRTClock internal register that will be targeted by subsequent reads or
writes. Recommended instruction timing is provided in this section. If the recommended instruction timing
is not followed, then BUSY (RTC0ADR.7) should be checked prior to each read or write operation to make
sure the SmaRTClock Interface is not busy performing the previous read or write operation. A
SmaRTClock Write operation is initiated by writing to the RTC0DAT register. Below is an example of
writing to a SmaRTClock internal register.
1. Poll BUSY (RTC0ADR.7) until it returns 0 or follow recommended instruction timing.
2. Write 0x05 to RTC0ADR. This selects the internal RTC0CN register at SmaRTClock Address
0x05.
3. Write 0x00 to RTC0DAT. This operation writes 0x00 to the internal RTC0CN register.
A SmaRTClock Read operation is initiated by setting the SmaRTClock Interface Busy bit. This transfers
the contents of the internal register selected by R TC0ADR to R TC0DAT. The tr ansferred data will remain in
RTC0DAT until the next read or write operation. Below is an example of reading a SmaRTClock internal
register.1. Poll BUSY (RTC0ADR.7) until it returns 0 or follow recommended instruction timing.
2. Write 0x05 to RTC0ADR. This selects the internal RTC0CN register at SmaRTClock Address
0x05.
3. Write 1 to BUSY. This initiates the transfer of data from RTC0CN to RTC0DAT.
4. Poll BUSY (RTC0ADR.7) until it returns 0 or follow recommend instruction timing.
5. Read data from RTC0DAT. This data is a copy of the RTC0CN register.
Note: The RTC0ADR and RTC0DAT registers will retain their state upon a device reset.
20.1.3. RTC0ADR Short S trob e Feature
Reads and writes to indirect SmaRTClock registers normally take 7 system clock cycles . To minimize the
indirect register access time, the Short Strobe feature decreases the read and write access time to 6
system clocks. The Short Strobe feature is automatically enabled on reset and can be manually
enabled/disabled using the SHORT (RTC0ADR.4) control bit.
Recommended Instruction Timing for a single register read with short strobe enabled:
mov RTC0ADR, #095h
nop
nop
nop
mov A, RTC0DAT
Recommended Instruction Timing for a single register write with short strobe enabled:
mov RTC0ADR, #095h
mov RTC0DAT, #000h
nop
20.1.4. SmaRTClock Interface Autoread Feature
When Autoread is enabled, each read from RTC0DAT initiates the next indirect read operation on the
SmaRTClock internal register selected by RTC0ADR. Software should set the BUSY bit once at the
beginning of each series of consecutive reads. Software should follow recommende d instruction timing or
check if the SmaRTClock Interface is busy prior to reading RTC0DAT. Autoread is enabled by setting
AUTORD (RTC0ADR.6) to logic 1.
Rev. 1.1 191
C8051F91x-C8051F90x
20.1.5. RTC0ADR Autoincrement Feature
For ease of reading and writing the 32-bit CAPTURE and ALARM values, RTC0ADR automatically
increments after each read or write to a CAPTUREn or ALARMn register. This speeds up the process of
setting an alarm or reading the current SmaRTClock timer value. Autoincrement is always enabled.
Recommended Instruction Timing for a multi-byte register read with sho rt strobe and auto read enabled:
mov RTC0ADR, #0d0h
nop
nop
nop
mov A, RTC0DAT
nop
nop
mov A, RTC0DAT
nop
nop
mov A, RTC0DAT
nop
nop
mov A, RTC0DAT
Recommended Instruction Timing for a multi-byte register write with short strobe enabled:
mov RTC0ADR, #010h
mov RTC0DAT, #05h
nop
mov RTC0DAT, #06h
nop
mov RTC0DAT, #07h
nop
mov RTC0DAT, #08h
nop
C8051F91x-C8051F90x
192 Rev. 1.1
SFR Page = 0x0; SFR Address = 0xAE
SFR Definition 20.1. RTC0KEY: SmaRTClock Lock and Key
Bit76543210
Name RTC0ST[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 RTC0ST SmaRTClock Interface Lock/Key and Status.
Locks/unlocks the SmaRTClock interface when written. Provides lock status when
read.
Read:
0x00: SmaRTClock Interface is locked.
0x01: SmaRTClock Interface is locked.
First key code (0xA5) has been written, waiting for second key code.
0x02: SmaRTClock Interface is unlocked.
First and second key codes (0xA5, 0xF1) have been written.
0x03: SmaRTClock Interface is disabled until the next system reset.
Write:
When RTC0ST = 0x00 (locked), writing 0xA5 followe d by 0xF1 unlocks the
SmaRTClock Interface.
When RTC0ST = 0x01 (waiting for second key code), writing any value other
than the second key code (0xF1) will change RTC0STATE to 0x03 and disable
the SmaRTClock Interface until the next system reset.
When RTC0ST = 0x02 (unlocked), any write to RTC0KEY will lock the SmaRT-
Clock Interface.
When RTC0ST = 0x03 (disabled), writes to RTC0KEY have no effect.
Rev. 1.1 193
C8051F91x-C8051F90x
SFR Page = 0x0; SFR Address = 0xAC
SFR Page= 0x0; SFR Address = 0xAD
SFR Definition 20.2. RTC0ADR: SmaRTClock Address
Bit76543210
Name BUSY AUTORD SHORT ADDR[3:0]
Type R/W R/W R R/W R/W
Reset 00000000
Bit Name Function
7BUSY SmaRTClock Interface Busy Indicator.
Indicates SmaRTClock interface status. Writing 1 to this bit initiates an indirect read.
6AUTORD SmaRTClock Interface Autoread Enable.
Enables/disables Autoread.
0: Autoread Disabled.
1: Autoread Enabled.
5Unused Unused. Read = 0b; Write = Don’t Care.
4SHORT Short Strobe Enable.
Enables/disables the Short Strobe Feature.
0: Short Strob e disa b led .
1: Short Strob e en ab le d.
3:0 ADDR[3:0] SmaRTClock Indirect Register Address.
Sets the currently selected SmaRTClock register.
See Table 20.1 for a listing of all SmaRTClock indirect registers.
Note: The ADDR bits increment after each indirect read/write operation that targets a CAPTUREn or ALARMn
internal SmaRTClock register.
SFR Definition 20.3. RTC0DAT: SmaRTClock Data
Bit76543210
Name RTC0DAT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 RTC0DAT SmaRTClock Data Bits.
Holds data transferred to/from the internal SmaRTClock register selected by
RTC0ADR.
Note: Read-modify-write instructions (orl, anl, etc.) should not be used on this register.
C8051F91x-C8051F90x
194 Rev. 1.1
20.2. SmaRTClock Clocking Sources
The SmaRTClock peripheral is clocked from its own timebase, independent of the system clock. The
SmaRTClock timebase can be derived from an external CMOS clock, the internal LFO (‘F912 and ‘F902
devices only), or the SmaRTClock oscillator circuit, which has two modes of operation: Crystal Mode, and
Self-Oscillate Mode. The oscillation frequency is 32.768 kHz in Crystal Mode and can be programmed in
the range of 10 kHz to 40 kHz in Self-Oscillate Mode. The internal LFO frequency is 16.4 kHz ±20%. The
frequency of the SmaRTClock oscillator can be measured with respect to another oscillator using an on-
chip timer. See Section “25. Timers” on page 270 for more information on how this can be accomplished.
Note: The SmaRTClock timebase can be selected as the system clock and routed to a port pin. See Section
“19. Clocking Sources” on page 179 for information on selecting the system clock source and Section “21. Port
Input/Outpu t” on page 205 for information on how to route the system clock to a port pin. On ‘F912 and ‘F902
devices, the SmaRTClock timebase can be routed to a port pin while the device is in its ultra low power sleep
mode. See the PMU0MD register description for details.
20.2.1. Using the SmaRTClock Oscillator with a Crystal or External CMOS Clock
When using Crystal Mode, a 32.768 kHz crystal should be connected between XTAL3 and XTAL4. No
other external components are required. The following steps show how to start the SmaRTClock crystal
oscillator in software:
1. Set SmaRTClock to Crystal Mode (XMODE = 1).
2. Disable Automatic Gain Control (AGCEN) and enable Bias Doubling (BIASX2) for fast crystal
startup.
3. Set the desired loading capacitance (RTC0XCF).
4. Enable power to the SmaRTClock oscillator circuit (RTC0EN = 1).
5. Wait 20 ms.
6. Poll the SmaRTClock Clock Valid Bit (CLKVLD) until the crystal oscillator stabilizes.
7. Poll the SmaRTClock Load Capacitance Ready Bit (LOADRDY) until the load capacitance
reaches its programmed value.
8. Enable Automatic Gain Control (AGCEN) and disable Bias Doubling (BIASX2) for maximum
power savings.
9. Enable the SmaRTClock missing clock detector.
10. Wait 2 ms.
11. Clear the PMU0CF wake-up source flags.
In Crystal Mode, the SmaRTClock osc illator may be driven by an external CMOS clock. The CMOS clock
should be applied to XTAL3. XTAL4 should be left floating. The input low voltage (VIL) and input high
voltage (VIH) for XTAL3 when used with an external CMOS clock are 0.1 and 0.8 V, respectively. The
SmaRTClock oscillator should be configured to its lowest bias setting with AGC disabled. The CLKVLD bit
is indeterminate when using a CMOS clock, however, the OSCFAIL bit may be checked 2 ms after
SmaRTClock oscillator is powered on to ensure that there is a valid clock on XTAL3.
Rev. 1.1 195
C8051F91x-C8051F90x
20.2.2. Using the SmaRTClock Oscillator in Self-Oscillate Mode
When using Self-Oscillate Mode, the XTAL3 and XTAL4 pins should be shorted together. The RTC0PIN
register can be used to internally short XTAL3 and XTAL4. The following steps show how to configure
SmaRTClock for use in Self-Oscillate Mode:
1. Set SmaRTClock to Self-Oscillate Mode (XMODE = 0).
2. Set the desired oscillation frequency:
For oscillation at about 20 kHz, set BIASX2 = 0.
For oscillation at about 40 kHz, set BIASX2 = 1.
3. The oscillator starts oscillating instantaneously.
4. Fine tune the oscillation frequency by adjusting the load capacitance (RTC0XCF).
20.2.3. Using the Low Frequency Oscillator (LFO)
The low frequency oscillator provides an ultra low power, on-chip clock source to the SmaRTClock. The
typical frequency of oscillation is 16.4 kHz ±20%. No external component s are requir ed to use the LFO an d
the XTAL3 and XTAL4 pins do not need to be shorted together. The LFO is only available on ‘F912 and
‘F902 devices.
The following step s show how to configure SmaRTClock fo r use with the LFO:
1. Enable and select the Low Frequency Oscillator (LFOEN = 1).
2. The LFO starts oscillating instantaneously.
When the LFO is enabled, the SmaRTClock oscillator increments bit 1 of the 32-bit timer (instead of bit 0).
This effectively multiplies the LFO frequency by 2, making the RTC timebase behave as if a 32.768 kHz
crystal is connected at the ou tp ut .
C8051F91x-C8051F90x
196 Rev. 1.1
20.2.4. Programmable Load Capacitance
The programmable load capacitance has 16 values to support crystal oscillators with a wide range of
recommended load capacitance. If Automatic Load Capacitance Stepping is enabled, the crystal load
capacitors start at the smallest setting to allow a fast startup time, then slowly increase the capacitance
until the final programmed value is reached. The final programmed loading capacitor value is specified
using the LOADCAP bits in the RTC0XCF register. The LOADCAP setting specifies the amount of on-chip
load capacitance and does not include any stray PCB capacitance. Once the final programmed loading
capacitor value is reached, the LOADRDY flag will be set by hardware to logic 1.
When using the SmaRTClock oscillator in Self-Oscillate mode, the programmable load capa cita nce can be
used to fine tune the oscillation frequency. In most cases, inc reasing the load capacitor value will result in
a decrease in oscillation frequency.Table 20.2 shows the crystal load capacitance for various settings of
LOADCAP.
Table 20.2. SmaRTClock Load Capacitance Settings
LOADCAP Crystal Load Capacitance Equivalent Capacitance seen on
XTAL3 and XTAL4
0000 4. 0 pF 8.0 pF
0001 4.5 pF 9.0 pF
0010 5. 0 pF 10.0 pF
0011 5.5 pF 11.0 pF
0100 6. 0 pF 12.0 pF
0101 6. 5 pF 13.0 pF
0110 7.0 pF 14.0 pF
0111 7. 5 pF 15.0 pF
1000 8. 0 pF 16.0 pF
1001 8. 5 pF 17.0 pF
1010 9. 0 pF 18.0 pF
1011 9.5 pF 19.0 pF
1100 10.5 pF 21.0 pF
1101 11.5 pF 23.0 pF
1110 12.5 pF 25.0 pF
1111 13.5 pF 27.0 pF
Rev. 1.1 197
C8051F91x-C8051F90x
20.2.5. Automatic Gain Control (Crystal Mode Only) and SmaRTClock Bias Doubling
Automatic Gain Control allows the SmaRTClock oscillator to trim the oscillation amplitude of a crystal in
order to achieve the lowest possible power consumption. Automatic Gain Control automatically detects
when the oscillation amplitude has reached a point where it safe to reduce the drive current, therefore, it
may be enabled during crystal startup. It is recommended to enable Automatic Gain Control in most
systems which use the SmaRTClock oscillator in Crystal Mode. The following are recommended crystal
specifications and operating conditions when Automatic Gain Control is enabled:
• ESR < 50 k
• Load Capacitance < 10 pF
• Supply Voltage < 3.0 V
• Temperature > –20 °C
When using Automatic Gain Control, it is recommended to perform an oscillation robustness test to ensure
that the chosen crystal will oscillate under the worst case condition to which the system will be exposed.
The worst case condition that should result in the least robust oscillation is at the following system
conditions: lowest temperature, highest supply voltage, highest ESR, highest load capa cit ance, and lowest
bias current (AGC enabled, Bias Double Disabled).
To perform the oscillation robustness test, the SmaRTClock oscillator should be enabled and selected as
the system clock source. Next, the SYSCLK signa l should be ro uted to a port pi n configured as a push-pull
digital output. The positive duty cycle of the output clock can be used as an indicator of oscillation
robustness. As shown in Figure 20.2, duty cycles less than 55% indicate a robust oscillation. As the duty
cycle approaches 60%, oscillation becomes less reliable and the ris k of clock failure increases. Increasing
the bias current (by disabling AGC) will always improve oscillation robustness and will reduce the output
clock’s duty cycle. This test should be performed at the worst case system conditions, as results at very
low temperatures or high supply voltage will vary from results taken at room temperature or low supply
voltage.
Figure 20.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results
As an alternative to performing the oscillation robustness test, Automatic Gain Control may be disabled at
the cost of increased power consumption (approximately 200 nA). Disabling Automatic Gain Control will
provide the crystal oscillator with higher immunity against external factors which may lead to clock failure.
Automatic Gain Control must be disabled if using the SmaRTClock oscillator in self-oscillate mode.
Table 20.3 shows a summary of the oscillator bias settings. The SmaR TClock Bias Doubling feature allows
the self-oscillation frequency to be increased (almost doubled) and allows a higher crystal drive strength in
crystal mode. High crystal drive strength is recommended when the crystal is exposed to poor
environmental conditions such as excessive moisture. SmaRTClock Bias Doubling is enabled by setting
BIASX2 (RTC0XCN.5) to 1.
Duty Cycle
25% 55% 60%
Safe Operating Zone Low Risk of Clock
Failure High Risk of Cl ock
Failure
C8051F91x-C8051F90x
198 Rev. 1.1
.Table 20.3. SmaRTClock Bias Settings
Mode Setting Power
Consumption
Crystal Bias Double Off, AGC On Lowest
600 nA
Bias Double Of f, AGC Off Low
800 nA
Bias Double On, AGC On High
Bias Double On, AGC Off Highest
Self-Oscillate Bias Double Off Low
Bias Double On High
Rev. 1.1 199
C8051F91x-C8051F90x
20.2.6. Missing SmaRTClock Detector
The missing SmaRTClock detector is a one-shot circuit enabled by setting MCLKEN (RTC0CN.6) to 1.
When the SmaRTClock Missing Clock Detector is enabled, OSCFAIL (RTC0CN.5) is set by hardware if
SmaRTClock oscillator remains high or low for more than 100 µs.
A SmaRTClock Missing C lock d etector timeo ut can t rigge r an interru pt, wa ke the d evice from a low power
mode, or reset the device. See Section “12. Interrupt Handler” on page 120, Section “14. Power
Management” on page 143, and Section “18. Reset Sources” on page 171 for more information.
Note: The SmaRTClock Missing Clock Detector should be disabled when making changes to the oscillator settings in
RTC0XCN.
20.2.7. SmaRTClock Oscillator Crystal Valid Detector
The SmaRTClock oscillator crystal valid detector is an oscillation amplitude detector circuit used during
crystal startup to determine when oscillation has started and is nearly stable. The output of this detector
can be read from the CLKVLD bit (RTX0XCN.4).
Notes:
• The CLKVLD bit has a blanking interval of 2 ms. During the first 2 ms after turning on the crystal oscillator , the out-
put of CLKVLD is not valid.
•This SmaRTClock crystal valid detector (CLKV LD) is not intended for detecting an oscillator failure. The missing
SmaRTClock detector (CLKFAI L) should be used for this purpose.
20.3. SmaRTClock Timer and Alarm Function
The SmaRTClock timer is a 32-bit counter that, when running (RTC0TR = 1), is incremented every
SmaRTClock oscillator cycle. The timer has an alarm function that can be set to generate an interrupt,
wake the device from a low power mode, or reset the device at a specific time. See Section “1 2. Interrupt
Handler” on page 120, Section “14. Power Management” on page 143, and Section “18. Reset Sources”
on page 171 for more information.
The SmaRTClock timer includes an Auto Reset feature, which automatically resets the timer to zero one
SmaRTClock cycle after an a larm occurs. Whe n using Auto Reset, the Alarm match value should always
be set to 1 count less than the desired match value. Auto Reset can be enabled by writing a 1 to ALRM
(RTC0CN.2).
20.3.1. Setting and Reading the SmaRTClock Timer Value
The 32-bit SmaRTClock timer can be set or read using the six CAPTUREn internal registers. Note that the
timer does not need to be stopped before reading or setting its value. The following steps can be used to
set the timer value:
1. Write the desired 32-bit set value to the CAPTUREn registers.
2. Write 1 to RTC0SET. This will transfer the contents of the CAPTUREn registers to the SmaR T-
Clock timer.
3. Operation is complete when RTC0SET is cleared to 0 by hardware.
The following steps can be used to read the current timer value:
1. Write 1 to RTC0CAP. This will transfer the contents of the timer to the CAPTUREn registers.
2. Poll RTC0CAP until it is cleared to 0 by hardware.
3. A snapshot of the timer value can be read from the CAPTUREn registers
C8051F91x-C8051F90x
200 Rev. 1.1
20.3.2. Setting a SmaRTClock Alarm
The SmaRTClock alarm function compares the 32-bit value of SmaRTClock Timer to the value of the
ALARMn registers. An alarm e vent is triggered if the SmaR TClock timer is equal to the ALARMn registers.
If Auto Reset is enabled, the 32-bit timer will be cleared to zero one SmaRTClock cycle after the alarm
event.
The SmaRTClock alarm event can be configured to reset the MCU, wake it up from a low power mode, or
generate an interr upt. Se e Section “12. Interrupt Handler” on page 120, Section “14. Power Management”
on page 143, and Section “18. Reset Sources” on page 171 for more information.
The following step s can be used to set up a SmaRTClock Alarm:
1. Disable SmaRTClock Alarm Events (RTC0AEN = 0).
2. Set the ALARMn registers to the desired value.
3. Enable SmaRTClock Alarm Events (RTC0AEN = 1).
Notes:
• T he ALR M bit, wh ich is used as th e Sma RTClock Alarm Event flag, is cleared by disabling SmaRTClock Alarm
Events (RTC0AEN = 0).
• If AutoReset is disabled, disabling (RTC0AEN = 0) then Re-enabling Alarm Events (RTC0AEN = 1) after a
SmaRTClock Alarm without modifying ALARMn registers will automatically schedule the next alarm after 2^32
SmaRTClock cycles (approximately 36 hours using a 32.768 kHz crystal).
• The SmaRTClock Alarm Event flag will remain asserted for a maximum of one SmaRTClock cycle. See Section
“14. Power Management” on page 143 for information on how to capture a SmaRTClock Alarm event using a flag
which is not automatically cleared by hardware.
20.3.3. Software Considerations for using the SmaRTClock Timer and Alarm
The SmaRTC lock timer and alarm have two operating modes to suit varying applications. The two modes
are described below:
Mode 1:
The first mode uses th e Sma RTClock timer as a perpet ual tim ebase which is never reset to zero. Eve ry 36
hours, the timer is allowed to overflow without being stopped or disrupted. The alarm interval is software
managed and is added to the ALRMn registers by software after each alarm. This allows the alarm match
value to always stay a head of the timer b y one sof tware manage d interval. If soft ware uses 32-b it unsigne d
addition to increment the a larm match value, then it does not need to handle overflows since both the timer
and the alarm match value will overflow in the same manner.
This mode is ideal for applications which have a long alarm interval (e.g., 24 or 36 hours) and/or have a
need for a perpetual timebase. An example of an application that needs a perpetual timebase is one
whose wake-up interval is constantly changing. For these applications, software can keep track of the
number of timer overflows in a 16-bit variable, extending the 32-bit (36 hour) timer to a 48-bit (272 year)
perpetual timebase.
Mode 2:
The second mode uses the Sm aRTClock timer a s a general purpose up counter which is auto r eset to zero
by hardware after each alarm. The alarm interval is managed by hardware and stored in the ALRMn
registers. Software only needs to set the alarm interval once during dev ice initialization. After each alarm,
software should keep a count of the number of alarms that have occurred in order to keep track of time.
This mode is ideal for applications that require minimal software intervention and/or have a fixed alarm
interval. This mode is the most power efficient since it requires less CPU time per alarm.
Rev. 1.1 201
C8051F91x-C8051F90x
SmaRTClock Address = 0x04
Internal Register Definition 20.4. RTC0CN: SmaRTClock Control
Bit76543210
Name RTC0EN MCLKEN OSCFAIL RTC0TR RTC0AEN ALRM RTC0SET RTC0CAP
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00Varies00000
Bit Name Function
7RTC0EN SmaRTClock Enable.
Enables/disables the SmaRTClock oscillator and associated bias currents.
0: SmaRTClock oscillator disabled.
1: SmaRTClock oscillator enabled.
6MCLKEN Missing SmaRTClock Detect or Enable.
Enables/disables the missing SmaRTClock detector.
0: Missing SmaRTClock dete ctor disabled.
1: Missing SmaRTClock detector enabled.
5OSCFAIL SmaRTClock Oscillator Fail Event Flag.
Set by hardware when a missing SmaRTClock detector timeout occurs. Must be
cleared by softwar e. The value of this bit is not defined when the SmaRTClock
oscillator is disabled.
4RTC0TR SmaRTClock Timer Run Control.
Controls if the SmaRTClock timer is running or stopped (holds current value).
0: SmaRTClock tim er is stopped.
1: SmaRTClock timer is running.
3RTC0AEN SmaRTClock Alarm Enable.
Enables/disables the SmaRTClock alarm function. Also clears the ALRM flag.
0: SmaRTClock alarm disabled.
1: SmaRTClock alarm enabled.
2ALRM SmaRTClock Alarm Event
Flag and Auto Reset
Enable.
Reads return the state of the
alarm event f lag .
Writes enable/disable the
Auto Reset function.
Read:
0: SmaRTClock alarm
event flag is de-asserted.
1: SmaRTClock alarm
event flag is asserted.
Write:
0: Disable Auto Reset.
1: Enable Auto Reset.
1RTC0SET SmaRTClock Timer Set.
Writing 1 initiates a SmaRTClock timer set operation. This bit is clear ed to 0 by hard-
ware to indicate that the timer set operation is complete.
0RTC0CAP SmaRTClock Timer Capture.
Writing 1 initiates a SmaRTClock timer capture operation. This bit is cleared to 0 by
hardware to indicate that the timer capture operation is complete.
Note: The ALRM flag will remain asserted for a maximum of one SmaRTClock cycle. See Section “Power
Management” on page 143 for information on how to capture a SmaRTClock Alarm event using a flag which
is not automatically cleared by hardware.
C8051F91x-C8051F90x
202 Rev. 1.1
SmaRTClock Address = 0x05
Internal Register Definition 20.5. RTC0XCN: SmaRTClock Oscillator Control
Bit76543210
Name AGCEN XMODE BIASX2 CLKVLD LFOEN
Type R/WR/WR/WRRRRR
Reset 00000000
Bit Name Function
7AGCEN SmaRTClock Oscillator Automatic Gain Control (AGC) Enable.
0: AGC disabled.
1: AGC enabled.
6XMODE SmaRTClock Oscillator Mode.
Selects Crystal or Self Oscillate Mode.
0: Self-Oscillate Mode selected.
1: Crystal Mode selected.
5BIASX2 SmaRTClock Oscillator Bias Double Enable.
Enables/disables the Bias Double feature.
0: Bias Double disabled.
1: Bias Double enabled.
4CLKVLD SmaRTClock Oscillator Crystal Valid Indicator.
Indicates if oscillation amplitude is sufficient for maintaining oscillation.
0: Oscillation has not started or oscillation amplitude is too low to maintain oscillation.
1: Sufficient oscillation amplitude detected.
3LFOEN Low Frequency Oscillator Enable and Select.
Overrides XMODE and selects the internal low frequency oscillator (LFO) as the
SmaRTClock oscillator source. Only available on ‘F912 and ‘F902 devices.
0: XMODE determines SmaRTClock oscillator source.
1: LFO enabled and selected as SmaRTClock oscillator source.
2:0 Unused Unused.
Read = 000b; Write = Don’t Care.
Rev. 1.1 203
C8051F91x-C8051F90x
SmaRTClock Address = 0x06
SmaRTClock Address = 0x07
Internal Register Definition 20.6. RTC0XCF: SmaRTClock Oscillator Configuration
Bit 7 6 5 4 3 2 1 0
Name AUTOSTP LOADRDY LOADCAP
Type R/W R R R R/W
Reset 0 0 0 0 Varies Varies Varies Varies
Bit Name Function
7AUTOSTP Automatic Load Capacitance Stepping Enable.
Enables/disables automatic load capacitance stepping.
0: Load capacitance stepping disabled.
1: Load capacitance stepping enabled.
6LOADRDY Load Capacitance Ready Indicator.
Set by hardware when the load capacitance matches the programmed value.
0: Load capacitance is currently stepping.
1: Load capacitance has reached it programmed value.
5:4 Unused Unused.
Read = 00b; Write = Don’t Care.
3:0 LOADCAP Load Capacitance Programmed Value.
Holds the user’s desired value of the load capacitance. See Table 20.2 on
page 196.
Internal Register Definition 20.7. RTC0PIN: SmaRTClock Pin Configuration
Bit76543210
Name RTC0PIN
Type W R/W R/W R/W R/W R/W R/W R/W
Reset 0 Varies Varies Varies Varies Varies Varies Varies
Bit Name Function
7RTC0PIN SmaRTClock Pin Configuration.
0: XTAL3 and XTAL4 in their normal configuration.
1: XTAL3 and XTAL4 internally shorted for use with Self Oscillate Mode.
6:0 Reserved Reserved.
Read = Varies. Software should not modify the value of these bits. To change the
RTC0PIN setting, the entir e re gi ster co nten ts should be read, modified, then rewritten.
C8051F91x-C8051F90x
204 Rev. 1.1
SmaRTClock Addresses: CAPTURE0 = 0x00; CAPTURE1 = 0x01; CAPT URE2 =0x02; CAPTURE3: 0 x03.
SmaRTClock Addresses: ALARM0 = 0x08; ALARM1 = 0x09; ALARM2 = 0x0A; ALARM3 = 0x0B
Internal Register Definition 20.8. CAPTUREn: SmaRTClock Timer Capture
Bit76543210
Name CAPTURE[31:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 CAPTURE[31:0] SmaRTClock Timer Capture.
These 4 registers (CAPTURE3–CAPTURE0) are used to read or set the 32-bit
SmaRTClock timer. Data is transferred to or from the SmaRTClock timer when
the RTC0SET or RTC0CAP bits are set.
Note: The least significant bit of the timer capture value is in CAPTURE0.0.
Internal Register Definition 20.9. ALARMn: SmaRTClock Alarm Programmed Value
Bit76543210
Name ALARM[31:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 ALARM[31:0] SmaRTClock Alarm Programmed Value.
These 4 registers (ALARM3–ALARM0) are used to set an alarm event for the
SmaRTClo ck timer. The SmaRTClock alarm should be disabled (RTC0AEN=0)
when updating these registers.
Note: The least significant bit of the alarm programmed value is in ALARM0.0.
Rev. 1.1 205
C8051F91x-C8051F90x
21. Port Input/Output
Digital and analog resource s are av ailable thr oug h 16 I/O pins. Port pins are organized as three byte-wide
ports. Port pins P0. 0–P1.6 c an be defined as digital or analog I/O. Digital I/O pins can be assigned to one
of the internal digital resources or used as general purpose I/O (GPIO). Analog I/O pins are used by the
internal analog resources. P2.7 can be used as GPIO and is shared with the C2 Interface Data signal
(C2D). See Section “27. C2 Interface” on page 312 for more details.
The designer has complete control over which digital and analog functions are assigned to individual Port
pins, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a Priority Crossbar Decoder. See Section 21.3 for more information on the Crossbar.
All Port I/Os are 5 V tolerant when used as digital inputs or open-drain outputs . For Port I/Os configure d as
push-pull outputs, current is sourced from the VDD/DC+ supply. Port I/Os used for analog functions can
operate up to the VDD/DC+ supply voltage. See Section 21.1 for more information on Port I/O operating
modes and the electrical specifications chapter for detailed electrical specifications.
Figure 21.1. Port I/O Functional Block Diagram
XBR0, XBR1,
XBR2, PnSKIP
Registers
Digital
Crossbar
Priority
Decoder
2
P0
I/O
Cells
P0.0
P0.7
8
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
UART
(Internal Digital Signals)
Highest
Priority
Lowest
Priority
SYSCLK
2
SMBus
T0, T1 2
7
PCA
4
CP0
CP1
Outputs
SPI0
SPI1 4
P1
I/O
Cells
P1.0
P1.6
7
(Port La t c he s )
P0 (P0.0-P0.7)
(P1.0-P1.6)
8
7
P1
P2
I/O
Cell
P2 (P2.7)
1
1
PnMDOUT,
PnMDIN Registers
P2.7
To Analog Peripherals
(ADC0, CP0, and CP1 inputs,
VREF, IREF0, AGND)
External Interrupts
EX0 and EX1
C8051F91x-C8051F90x
206 Rev. 1.1
21.1. Port I/O Modes of Operation
Port pins P0.0–P1.6 use the Port I/O cell shown in Figure 21.2. Each Port I/O cell can be configured by
software for analog I/O or digi tal I/O using the PnMDIN regi sters. On rese t, all Port I/O cells defaul t to a dig -
ital high impedance state with weak pull-ups enabled.
21.1.1. Port Pins Configured for Analog I/O
Any pins to be used as Comparator or ADC input, external oscillator input/output, or AGND, VREF, or Cur-
rent Reference output should be configured for analog I/O (PnMDIN.n = 0). When a pin is configured for
analog I/O, its weak pullup and digital receiver are disabled. In most cases, software should also disable
the digital output drivers. Port pins configured for analog I/O will always read back a value of 0 regardless
of the actual voltage on the pin.
Configuring pins as analog I/O saves power and isolates the Port pin from digital interference. Port pins
configured as digital inputs may still be used by analog peripherals; however, this practice is not recom-
mended and may result in measurement errors.
21.1.2. Port Pins Configured For Digital I/O
Any pins to be used by digital peripherals (UART, SPI, SMBus, etc.), external digital event capture func-
tions, or as GPIO should be co nfigured as d igital I/O (PnMDIN.n = 1). For digit al I/O pins, one of two ou tput
modes (push-pull or open-drain) must be selected using the PnMDOUT registers.
Push-pull outputs (PnMDOUT.n = 1) drive the Port pad to the VDD/DC+ or GND supply rails based on the
output logic value of the Port pin. Open-drain outputs have the high side driver disabled; therefore, they
only drive the Port pad to GND when the output logic value is 0 and become high impedance inputs (both
high and low drivers tu rned off) when the output logic value is 1.
When a digit a l I/O cell is placed in th e hi gh imped an ce state, a weak pull-up transistor pulls the Port pad to
the VDD/DC+ supp ly voltage to ensure the digital input is at a defined logic state. Weak pull-ups are dis-
abled when the I/O cell is driven to GND to minimize power consumption and may be globally disabled by
setting WEAKPUD to 1. The user must en sure that digita l I/O are always internally or externally pulled or
driven to a valid logic state. Port pins configured for digital I/O always read back the logic state of the Port
pad, regardless of the output logic value of the Port pin.
Figure 21.2. Port I/O Cell Block Diagram
GND
VDD/DC+ VDD/DC+
(WEAK)
PORT
PAD
To/From Analog
Peripheral
PnMDIN.x
(1 for digital)
(0 for analog)
Pn.x – Output
Logic Value
(Port Latch or
Crossbar)
XBARE
(Crossbar
Enable)
Pn.x – Input Logic Value
(Reads 0 when pin is con f igu red as an anal og I/O)
PnMDOUT.x
(1 for push-pull)
(0 for open-drain)
WEAKPUD
(Weak Pull -Up Di sa bl e )
Rev. 1.1 207
C8051F91x-C8051F90x
21.1.3. Interfacing Port I/O to 5 V and 3.3 V Logic
All Port I/O configured for digit al, open-drain o peration are cap able of interfacing to digit al logic operating at
a supply voltage higher than 4.5 V and less than 5.25 V. When the supply voltage is in the range of 1.8 to
2.2 V, the I/O may also interface to digital logic operating between 3.0 to 3.6 V if the input signal frequency
is less than 12.5 MHz or less than 25 MHz if the signal rise time (10% to 90%) is less than 1.2 ns. When
operating at a supply voltage above 2.2 V, the device should not interface to 3.3 V logic; however, interfac-
ing to 5 V logic is permitted. An external pull-up resistor to the higher supply volt age is typica lly required for
most systems.
Important Note:
When interfacing to a signal that is between 4.5 and 5.25 V, the maximum clock frequency that may be
input on a GPIO pin is 12.5 MHz. The exception to this rule is when routing an external CMOS clock to
P0.3, in which case, a signal up to 25 MHz is valid as long as the rise time (10% to 90%) is sh orter than
1.8 ns.
When the supply volt age is less than 2.2 V and interfacing to a signal that is betwe en 3.0 and 3.6 V, the
maximum clock frequency that may be input on a GPIO pin is 3.125 MHz. The exception to this rule is
when routing an external CMOS clock to P0.3, in which case, a signal up to 25 MHz is valid as long as
the rise time (10% to 90%) is shorter than 1.2 ns.
In a multi-voltage interface, the external pull-up resistor should be sized to allow a current of at least
150 µA to flow into the Port pin when the supply voltage is between (VDD/DC+ plus 0.4 V) and
(VDD/DC+ plus 1.0 V). Once the Port p ad volt age in crea ses be yond this ra nge, the cu rrent flowin g into
the Port pin is minimal.
These guidelines only apply to multi-voltage interfaces. Port I/Os may always interface to digital logic
operating at the same supply voltage.
21.1.4. Increasing Port I/O Drive Strength
Port I/O output drivers support a high and low drive strength; the default is low drive strength. The drive
strength of a Port I/O can be configured using the PnDRV registers. See Section “4. Electrical Characteris-
tics” on page 36 for the difference in output drive strength between the two modes.
21.2. Assigning Port I/O Pins to Analog and Digital Functions
Port I/O pins P0.0–P1.6 can be assigned to various analog, digital, and external interrupt functions. The
Port pins assuaged to anal og functio ns should b e configur ed fo r analo g I/O and Po rt pin s assu ag ed to dig-
ital or external interrupt functions should be configured for digital I/O.
21.2.1. Assigning Port I/O Pins to Analog Functions
Table 21.1 shows all available analog functions that need Port I/O assignments. Port pins selected for
these analog functions should have their digital drivers disabled (Pn MDOUT.n = 0 an d Po rt La tch =
1) and their corresponding bit in PnSKIP set to 1. This reserves the pin for use by the analog function
and does not allow it to be claimed by the Crossbar. Table 21.1 shows the potential mapping of Port I/O to
each analog function.
Table 21.1. Port I/O Assignment for Analog Functions
Analog Function Potentially
Assignable Port Pins SFR(s) used for
Assignment
ADC Input P0.0–P1.6 ADC0MX, PnSKIP
Comparator0 Inpu t P0.0–P1.6 CPT0MX, PnSKIP
Comparator1 Inpu t P0.0–P1.6 CPT1MX, PnSKIP
C8051F91x-C8051F90x
208 Rev. 1.1
21.2.2. Assigning Port I/O Pins to Digital Functions
Any Port pins not assigned to analog functions may be assigned to digit al functions or used as GPIO. Most
digital functions rely on the Crossbar for pin assignment; however, some digital functions bypass the
Crossbar in a manner similar to the analog functions listed above. Port pins used by these digital func-
tions and any Port pins sele cted for use as GPIO should hav e their corresponding bit in Pn SKIP set
to 1. Table 21.2 shows all available digital functions and the potential mapping of Port I/O to each digital
function.
21.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions
External digital event capture functions can be used to trigger an interrupt or wake the device from a low
power mode when a transition occurs on a digital I/O pin. The digital event capture functions do not require
dedicated pins and will function on both GPIO pins (PnSKIP = 1) and pins in use by the Crossbar (PnSKIP
= 0). External digital even capture functions cannot be used on pins configured for analog I/O. Table 21.3
shows all available external digital event capture functions.
Voltage Reference (VREF0) P0.0 REF0CN, PnSKIP
Analog Ground Refe rence (AGND) P0.1 REF0CN, PnSKIP
Current Reference (IREF0) P0.7 IREF0CN, PnSKIP
External Oscillator Input (XTAL1) P0.2 OSCXCN, PnSKIP
External Oscillator Output (XTAL2) P0.3 OSCXCN, PnSKIP
Table 21.2. Port I/O Assignment for Digital Functions
Digital Function Potentially As sig n a bl e Po rt Pins SFR(s) used for
Assignment
UART0, SPI1, SPI0, SMBus,
CP0 and CP1 Outputs, Sys-
tem Clock Output, PCA0,
Timer0 and Timer1 External
Inputs.
Any Port pin available for assignment by the
Crossbar. This includes P0.0–P1.6 pins which
have their PnSKIP bit set to 0.
Note: The Crossbar will always assign UART0
and SPI1 pins to fixed locations.
XBR0, XBR1, XBR2
Any pin used for GPIO P0.0–P1.6, P2.7 P0SKIP, P1SKIP
Table 21.3. Port I/O Assignment for External Digital Event Capture Functions
Digital Function Potentially As sig n a bl e Po rt Pins SFR(s) used for
Assignment
External Interrupt 0 P0.0–P0.7 IT01CF
External Interrupt 1 P0.0–P0.7 IT01CF
Port Match P0.0–P1.6 P0MASK, P0MAT
P1MASK, P1MAT
Table 21.1. Port I/O Assignment for Analog Functions
Analog Function Potentially
Assignable Port Pins SFR(s) used for
Assignment
Rev. 1.1 209
C8051F91x-C8051F90x
21.3. Priority Crossbar Decoder
The Priority Crossbar Decoder assigns a Port I/O pin to each software selected digital function using the
fixed periph er a l pr ior i ty or de r sh ow n in Figure 21.3. The registers XBR0, XBR1, and XBR2 defined in SFR
Definition 21.1, SFR Definition 21.2, and SFR Definition 21.3 are used to select digital functions in the
Crossbar. The Port pins available for assignment by the Crossbar include all Port pins (P0.0–P1.6) which
have their corresponding bit in PnSKIP set to 0.
From Figure 21.3, the highest priority peripheral is UAR T0. If UAR T0 is selected in the Crossbar (using the
XBRn registers), then P0.4 and P0.5 will be assigned to UART0. The next highest priority peripheral is
SPI1. If SPI1 is selected in the Crossbar, then P1.0–P1.3 will be assigned to SPI1. The user should ensure
that the pins to be assigned by the Crossbar have their PnSKIP bits set to 0.
For all remaining digital functions selected in the Crossbar, starting at the top of Figure 21.3 going down,
the least-significant unskippe d, unassigned Port pin( s) ar e assigned to th at functio n. If a Port pin is al ready
assigned (e.g. UART0 or SPI1 pins), or if its PnSKIP bit is set to 1, then the Crossbar will skip over the pin
and find next available unskipped, unassigned Port pin. All Port pins used for analog functions, GPIO, or
dedicated digital functions such as the EMIF should have their PnSKIP bit set to 1.
Figure 21.3 shows the Crossbar Decoder priority with no Port pins skipped (P0SKIP, P1SKIP = 0x00);
Figure 21.4 shows the Crossbar Decoder priority with the External Oscillator pins (XTAL1 and XTAL2)
skipped (P0SKIP = 0x0C).
Notes:
• The Crossbar must be enabled (XBARE = 1) before any Port pin is used as a digital output. Port output drivers are
disabled while the Crossbar is disabled.
• When SMBus is selected in the Crossbar, the pins associated with SDA and SCL will automatically be forced into
open-drain output mode regardless of the PnMDOUT setting.
• SPI0 can be operated in either 3-wire or 4-wire modes, depending on the state of the NSSMD1-NSSMD0 bits in
register SPI0CN. The NSS signal is only routed to a Port pin when 4-wire mode is selected. When SPI0 is
selected in the Crossbar, the SPI0 mode (3-wire or 4-wire) will affect the pinout of all digital functions lower in pri-
ority than SPI0.
• For given XBRn, PnSKIP, and SPInCN register settings, one can determine the I/O pin-out of the device using
Figure 21.3 and Figure 21.4.
C8051F91x-C8051F90x
210 Rev. 1.1
Figure 21.3. Crossbar Priority Decoder with No Pins Skipped
VREF
AGND
XTAL1
XTAL2
CNVSTR
IREF0
C2D
012345670123456 7
SCK ( S PI1)
MISO ( SPI1)
MOSI ( SPI1)
NSS* (SPI1) (*4-W ire SPI Only)
SCK ( S PI0)
MISO ( SPI0)
MOSI ( SPI0)
NSS* (SPI0) (*4-Wire SPI Only )
CP0
CP0A
CP1
CP1A
/SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1 000000000000000X
SDA
P0SKIP[0:7]
SCL
RX0
SF Signals
PIN I/O
TX0
P2P0 P1
P1SKIP[0:7]
Rev. 1.1 211
C8051F91x-C8051F90x
Figure 21.4. Crossbar Priority Decoder with Crystal Pins Skipped
VREF
AGND
XTAL1
XTAL2
CNVSTR
IREF0
C2D
012345670123456 7
SCK (SPI1)
MISO (SPI1)
MOSI (SPI1)
NSS* (SPI1) (*4-Wire SPI Only )
SCK (SPI0)
MISO (SPI0)
MOSI (SPI0)
NSS* (SPI0) (*4-W ire SPI Only)
CP0
CP0A
CP1
CP1A
/SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1 001100000000000X
P2P0 P1
P1SKIP[0:7]
RX0
SF Signals
PIN I/ O
TX0
SDA
P0SKIP[0:7]
SCL
C8051F91x-C8051F90x
212 Rev. 1.1
SFR Page = 0x0; SFR Address = 0xE1
SFR Definition 21.1. XBR0: Port I/O Crossbar Register 0
Bit76543210
Name CP1AE CP1E CP0AE CP0E SYSCKE SMB0E SPI0E URT0E
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7CP1AE Comparator1 Asynchronous Output Enable.
0: Asynchronous CP1 output unavailable at Port pin.
1: Asynchronous CP1 output routed to Port pin.
6CP1E Comparator1 Output Enable.
0: CP1 output unavailable at Port pin.
1: CP1 output routed to Port pin.
5CP0AE Comparator0 Asynchronous Output Enable.
0: Asynchronous CP0 output unavailable at Port pin.
1: Asynchronous CP0 output routed to Port pin.
4CP0E Comparator0 Output Enable.
0: CP1 output unavailable at Port pin.
1: CP1 output routed to Port pin.
3SYSCKE SYSCLK Output Enable.
0: SYSCLK output unavailable at Port pin.
1: SYSCLK output routed to Port pin.
2SMB0E SMBus I/O Enable.
0: SMBus I/O unavailable at Port pin.
1: SDA and SCL routed to Port pins.
1SPI0E SPI0 I/O Enable.
0: SPI0 I/O unavailable at Port pin.
1: SCK, MISO, and MOSI (for SPI0) routed to Port pins.
NSS (for SPI0) routed to Port pin only if SPI0 is configured to 4-wire mode.
0URT0E UART0 Output Enable.
0: UART I/O unavailable at Port pin.
1: TX0 and RX0 routed to Port pins P0.4 and P0.5.
Note: SPI0 can be assigned either 3 or 4 Port I/O pins.
Rev. 1.1 213
C8051F91x-C8051F90x
SFR Page = 0x0; SFR Address = 0xE2
SFR Definition 21.2. XBR1: Port I/O Crossbar Register 1
Bit76543210
Name SPI1E T1E T0E ECIE PCA0ME[2:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7Unused Unused.
Read = 0b; Write = Don’t Care.
6SPI1E SPI1 I/O Enable.
0: SPI0 I/O unavailable at Port pin.
1: SCK (for SPI1) routed to P1.0.
MISO (for SPI1) routed to P1.1.
MOSI (for SPI1) routed to P1.2.
NSS (for SPI1) routed to P1.3 only if SPI1 is configured to 4-wire mode.
5T1E Timer1 Input Enable.
0: T1 input unavailable at Port pin.
1: T1 input routed to Port pin.
4T0E Timer0 Input Enable.
0: T0 input unavailable at Port pin.
1: T0 input routed to Port pin.
3ECIE PCA0 Ex ternal Counter Input (ECI) Enable.
0: PCA0 external cou n ter input un a vaila b le at Po rt pin .
1: PCA0 external counter input routed to Port pin.
2:0 PCA0ME PCA0 Module I/O Enable.
000: All PCA0 I/O unavailable at Port pin.
001: CEX0 routed to Port pin.
010: CEX0, CEX1 routed to Port pins.
011: CEX0, CEX1, CEX2 routed to Port pins.
100: CEX0, CEX1, CEX2 CEX3 routed to Port pins.
101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to Port pins.
110: CEX0, CEX1, CEX2, CEX3, CEX4, CEX5 routed to Port pins.
111: Reserved.
Note: SPI1 can be assigned either 3 or 4 Port I/O pins.
C8051F91x-C8051F90x
214 Rev. 1.1
SFR Page = 0x0; SFR Address = 0xE3
SFR Definition 21.3. XBR2: Port I/O Crossbar Register 2
Bit 7 6 5 4 3 2 1 0
Name WEAKPUD XBARE
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0000000
Bit Name Function
7WEAKPUD Port I/O Weak Pullup Disable.
0: Weak Pullups enabled (except for Port I/O pins configured for analog mode).
6XBARE Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
5:0 Unused Unused.
Read = 000000b; Write = Don’t Care.
Note: The Crossbar must be enabled (XBARE = 1) to use any Port pin as a digital output.
Rev. 1.1 215
C8051F91x-C8051F90x
21.4. Port Match
Port match functionality allows system events to be triggered by a logic value change on P0 or P1. A soft-
ware controlled value stored in the PnMAT registers specifies the expected or normal logic values of P0
and P1. A Port mismatch event occurs if the logic levels of the Port’s input pins no longer match the soft-
ware controlled value. This allows Software to be notified if a certain change or pattern occurs on P0 or P1
input pins regardless of the XBRn settings.
The PnMASK registers can be used to individually select which P0 and P1 pins should be compared
against the PnMAT registers. A Port mismatch event is generated if (P0 & P0MASK) does not equal
(PnMAT & P0MASK) or if (P1 & P1MASK) does not equal (PnMAT & P1MASK).
A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode.
See Section “12. Interrupt Handler” on page 120 and Section “14. Power Management” on page 143 for
more details on interrupt and wake-up sou rces.
SFR Page= 0x0; SFR Address = 0xC7
SFR Page= 0x0; SFR Address = 0xD7
SFR Definition 21.4. P0MASK: Port0 Mask Register
Bit76543210
Name P0MASK[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P0MASK[7:0] Port0 Mask Value.
Selects the P0 pins to be compared with the corresponding bits in P0MAT.
0: P0.n pin pad logic value is ignored and cannot cause a Port Mismatch event.
1: P0.n pin pad logic value is compared to P0MAT.n.
SFR Definition 21.5. P0MAT: Port0 Match Register
Bit76543210
Name P0MAT[7:0]
Type R/W
Reset 11111111
7:0P0MAT[7:0] Port 0 Match Value.
Match comparison value used on Port 0 for bits in P0MASK which are set to 1.
0: P0.n pin logic value is compared with logic LOW.
1: P0.n pin logic value is compared with logic HIGH.
C8051F91x-C8051F90x
216 Rev. 1.1
SFR Page= 0x0; SFR Address = 0xBF
SFR Page = 0x0; SFR Address = 0xCF
SFR Definition 21.6. P1MASK: Port1 Mask Register
Bit76543210
Name P1MASK[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P1MASK[7:0] Port 1 Mask Value.
Selects P1 pins to be compared to the corresponding bits in P1MAT.
0: P1.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P1.n pin logic value is compared to P1MAT.n.
SFR Definition 21.7. P1MAT: Port1 Match Register
Bit76543210
Name P1MAT[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P1MAT[7:0] Port 1 Match Value.
Match comparison value used on Port 1 for bits in P1MASK which are set to 1.
0: P1.n pin logic value is compared with logic LOW.
1: P1.n pin logic value is compared with logic HIGH.
Rev. 1.1 217
C8051F91x-C8051F90x
21.5. Special Function Registers for Accessing and Configuring Port I/O
All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte
addressable and bit addressable. When writing to a Port, the value written to the SFR is latched to ma in-
tain the output da ta value at each pin . When reading, the logic levels of the Port's inpu t pins are re turned
regardless of the XBRn settings (i.e., even when the pin is a ssigned to another signal by the Crossbar, the
Port register can alwa ys read its corresponding Port I/O pin). The exception to this is the execution of the
read-modify-write instructions that target a Port Latch register as the destination. The read-modify-write
instructions when opera ting o n a Port SFR ar e the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ
and MOV, CLR or SETB, when the destin ation is a n in di vidua l bit in a Por t SFR. Fo r these instru ctio ns, the
value of the latch register (not the pin) is read, modified, and written back to the SFR.
Each Port has a corr es po n ding Pn SKIP register which allows its individual Port pins to be assigned to dig-
ital functions or skipped by the Crossbar . All Port pins used for analog functions, GPIO, or dedicated digital
functions such as the EMIF should have th eir PnSKIP bit set to 1.
The Port input mode of the I/O pins is defined using the Port Input Mode registers (PnMDIN). Each Port
cell can be configured for analog or digital I/O. This selection is required even for the digital resources
selected in the XBRn registers, and is not automatic. The only exception to this is P2.7, which can only be
used for digital I/O.
The output driver characteristics of the I/O pins are defined using the Port Output Mode register s (PnMD-
OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings.
The drive strength of the output drivers are controlled by the Port Drive Strength (PnDRV) registers. The
default is low drive strength. Se e Section “4. Electrical Cha racteristics” on p age 36 for the di ff erence in out-
put drive strength between the two modes.
C8051F91x-C8051F90x
218 Rev. 1.1
SFR Page = All Pages; SFR Address = 0x80; Bit-Addressable
SFR Page= 0x0; SFR Address = 0xD4
SFR Definition 21.8. P0: Port0
Bit76543210
Name P0[7:0]
Type R/W
Reset 11111111
Bit Name Description Write Read
7:0 P0[7:0] Port 0 Data.
Sets the Port latch log ic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P0.n Port pin is logic
LOW.
1: P0.n Port pin is logic
HIGH.
SFR Definition 21.9. P0SKIP: Port0 Skip
Bit76543210
Name P0SKIP[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P0SKIP[7:0] Port 0 Crossbar Skip Enable Bits.
These bit s select Por t 0 pins to be skippe d by the Crossbar Decoder. Port pins used
for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
Rev. 1.1 219
C8051F91x-C8051F90x
SFR Page= 0x0; SFR Address = 0xF1
SFR Page = 0x0; SFR Address = 0xA4
SFR Definition 21.10. P0MDIN: Port0 Input Mode
Bit76543210
Name P0MDIN[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P0MDIN[7:0] Analog Configuration Bits for P0.7–P0.0 (respectively).
Port pins configured for analog mode have their weak pullup, and digital receiver
disabled. The digi tal driver is not explicitly disabled.
0: Corresponding P0.n pin is configured for analog mode.
1: Corresponding P0.n pin is not configured for analog mode.
SFR Definition 21.11. P0MDOUT: Port0 Output Mode
Bit76543210
Name P0MDOUT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P0MDOUT[7:0] Output Configuration Bits for P0.7–P0.0 (respectively).
These bits control the digital drive r even when the corresponding bit in register
P0MDIN is logic 0.
0: Corresponding P0.n Output is open-dra in.
1: Corresponding P0.n Output is push-pull.
C8051F91x-C8051F90x
220 Rev. 1.1
SFR Page = 0xF; SFR Address = 0xA4
SFR Definition 21.12. P0DRV: Port0 Drive Strength
Bit76543210
Name P0DRV[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P0DRV[7:0] Drive Strength Configuration Bits for P0.7–P0.0 (respe ct iv ely ) .
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P0.n Output has low output drive strength.
1: Corresponding P0.n Output has high ou tput drive str ength.
Rev. 1.1 221
C8051F91x-C8051F90x
SFR Page = All Pages; SFR Address = 0x90; Bit-Addressable
SFR Page = 0x0; SFR Address = 0xD5
SFR Definition 21.13. P1: Port1
Bit76543210
Name P1[6:0]
Type R/W
Reset 01111111
Bit Name Description Write Read
7Unused Unused.
Read =0b; Write = Don’t Care.
6:0 P1[6:0] Port 1 Data.
Sets the Port latch log ic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P1.n Port pin is logic
LOW.
1: P1.n Port pin is logic
HIGH.
SFR Definition 21.14. P1SKIP: Port1 Skip
Bit76543210
Name P1SKIP[6:0]
Type R/W
Reset 00000000
Bit Name Function
7Unused Unused.
Read =0b; Write = Don’t Care.
6:0 P1SKIP[6:0] Port 1 Crossbar Skip Enable Bits.
These bit s select Por t 1 pins to be skippe d by the Crossbar Decoder. Port pins used
for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
C8051F91x-C8051F90x
222 Rev. 1.1
SFR Page = 0x0; SFR Address = 0xF2
SFR Page = 0x0; SFR Address = 0xA5
SFR Definition 21.15. P1MDIN: Port1 Input Mode
Bit76543210
Name P1MDIN[6:0]
Type R/W
Reset 11111111
Bit Name Function
7Unused Unused.
Read =0b; Write = Don’t Care.
6:0 P1MDIN[6:0] Analog Configuration Bits for P1.6–P1.0 (respectively).
Port pins configured for analog mode have their weak pullup and digital receive r
disabled. The digi tal driver is not explicitly disabled.
0: Corresponding P1.n pin is configured for analog mode.
1: Corresponding P1.n pin is not configured for analog mode.
SFR Definition 21.16. P1MDOUT: Port1 Output Mode
Bit76543210
Name P1MDOUT[6:0]
Type R/W
Reset 00000000
Bit Name Function
7Unused Unused.
Read =0b; Write = Don’t Care.
6:0 P1MDOUT[6:0] Output Configuration Bits for P1.6–P1.0 (respectively).
These bits control the digital drive r even when the corresponding bit in register
P1MDIN is logic 0.
0: Corresponding P1.n Output is open-dra in.
1: Corresponding P1.n Output is push-pull.
Rev. 1.1 223
C8051F91x-C8051F90x
SFR Page = 0xF; SFR Address = 0xA5
SFR Page = All Pages; SFR Address = 0xA0; Bit-Addressable
SFR Definition 21.17. P1DRV: Port1 Drive Strength
Bit76543210
Name P1DRV[6:0]
Type R/W
Reset 00000000
Bit Name Function
7Unused Unused.
Read =0b; Write = Don’t Care.
6:0 P1DRV[6:0] Drive Strength Configuration Bits for P1.6–P1.0 (respe ct iv ely ) .
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P1.n Output has low output drive strength.
1: Corresponding P1.n Output has high ou tput drive str ength.
SFR Definition 21.18. P2: Port2
Bit76543210
Name P2
Type R/W
Reset 10000000
Bit Name Description Read Write
7P2 Port 2 Data.
Sets the Port latch log ic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P2.7 Port pin is logic
LOW.
1: P2.7 Port pin is logic
HIGH.
6:0 Unused Unused.
Read = 0000000b; Write = Don’t Care.
C8051F91x-C8051F90x
224 Rev. 1.1
SFR Page = 0x0; SFR Address = 0xA6
SFR Page = 0x0F; SFR Address = 0xA6
SFR Definition 21.19. P2MDOUT: Port2 Output Mode
Bit 7 6 5 4 3 2 1 0
Name P2MDOUT
Type R/W
Reset 00000000
Bit Name Function
7P2MDOUT Output Configuration Bits for P2.7.
These bits control the digital drive r.
0: P2.7 Output is open-dr ain.
1: P2.7 Output is push-pull.
6:0 Unused Unused.
Read = 0000000b; Write = Don’t Care.
SFR Definition 21.20. P2DRV: Port2 Drive Strength
Bit76543210
Name P2DRV
Type R/W
Reset 00000000
Bit Name Function
7P2DRV Drive Strength Configuration Bits for P2.7.
Configures digital I/O Port cells to high or low output drive strength.
0: P2.7 Output has low output drive strength.
1: P2.7 Output has high output drive strength.
6:0 Unused Unused.
Read = 0000000b; Write = Don’t Care.
Rev. 1.1 225
C8051F91x-C8051F90x
22. SMBus
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SM Bus is compliant wit h the System
Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to
the interface by the system controller are byte oriented with the SMBus interface autonomously controlling
the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or
slave (this can be faster than allowed by the SMBus specification, dependin g on the system clock used). A
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface m ay opera te as a ma ster an d/or slav e, and may function on a bus with multip le ma s-
ters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation. The SMBus peripheral can be fully driven by
software (i.e. software accepts/rejects slave addresses, and generates ACKs), or hardware slave address
recognition and automatic ACK generation can be enabled to minimize software overhead. A block dia-
gram of the SMBus peripheral and the associated SF Rs is shown in Figure 22.1.
Figure 22.1. SMBus Block Diagram
Data Path
Control
SMBUS CONTROL LOGIC
C
R
O
S
S
B
A
R
SCL
FILTER
N
SDA
Control
SCL
Control
Interrupt
Request
Port I/O
SMB0CN
S
T
A
A
C
K
R
Q
A
R
B
L
O
S
T
A
C
K
S
I
T
X
M
O
D
E
M
A
S
T
E
R
S
T
O
01
00
10
11
T0 Overflow
T1 Overflow
TMR2H Overflo w
TMR2L Overflow
SMB0CF
E
N
S
M
B
I
N
H
B
U
S
Y
E
X
T
H
O
L
D
S
M
B
T
O
E
S
M
B
F
T
E
S
M
B
C
S
1
S
M
B
C
S
0
01234567 SMB0DAT SDA
FILTER
N
SMB0ADR
S
L
V
4
S
L
V
2
S
L
V
1
S
L
V
0
G
C
S
L
V
5
S
L
V
6
S
L
V
3
SMB0ADM
S
L
V
M
4
S
L
V
M
2
S
L
V
M
1
S
L
V
M
0
E
H
A
C
K
S
L
V
M
5
S
L
V
M
6
S
L
V
M
3
Arbitration
SCL Synchronization
Hardware ACK Generation
SCL Generation (Master Mode)
SDA Control
Hardware Slave Address Recognition
IRQ Generation
C8051F91x-C8051F90x
226 Rev. 1.1
22.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor.
2. The I2C-Bus Specification— Version 2.0, Philips Semiconductor.
3. System Management Bus Specification—Version 1.1, SBS Implementers Forum.
22.2. SMBus Configuration
Figure 22.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage
between 3.0 V and 5.0 V; different de vices on the bus may operate at dif f erent volt ag e levels. The bi-direc-
tional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage
through a pullup resistor or similar circuit. Every device connected to the bus must have an open-drain or
open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when
the bus is free. The maximum number of devices on th e bus is limited only by the re qu irement that the r ise
and fall times on the bus not exceed 300 ns and 1000 ns, respectively.
Figure 22.2. Typical SMBus Configuration
VDD = 5 V
Master
Device Slave
Device 1 Slave
Device 2
VDD = 3 V VDD = 5 V VDD = 3 V
SDA
SCL
Rev. 1.1 227
C8051F91x-C8051F90x
22.3. SMBus Operation
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave
receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ).
The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The
SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are
supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme
is employed with a single master always winning the arbitration. Note that it is not n ecessary to specify one
device as the Master in a system; any device who transmits a START and a slave address becomes the
master for the duration of that transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit
slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Bytes that are
received (by a master or slave) are acknowledged (ACK) with a low SDA during a high SCL (see
Figure 22.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowl-
edge), which is a high SDA during a high SCL.
The direction bi t (R/W) occupies the least-significan t bit position of th e address byte. The di rection bit is set
to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation.
All transactions are initiated by a master, with one or more addressed slave devices as the target. The
master generates the START condition and then transmits the slave address and direction bit. If the trans-
action is a WRITE operation from the master to the slave, the master transmits the data a byte at a time
waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the
data waiting for an ACK from the master at the end of each byte. At the end of the data transfer , the master
generates a STOP condition to terminate the transaction and free the bus. Figure 22.3 illustrates a typical
SMBus transaction.
Figure 22.3. SMBus Transaction
22.3.1. Transmitter Vs. Receiver
On the SMBus communications interface, a device is the “transmitter” when it is sending an address or
data byte to another device on the bu s. A device is a “receiver” when an address or data byte is being se nt
to it from another device on the bus. The transmitter controls the SDA line during the address or data byte.
After each byte of address or data information is sent by the transmitter, the receiver sends an ACK or
NACK bit during the ACK ph ase of the transfer, during which time the receiver controls the SDA line.
22.3.2. Arbitration
A master may star t a transfer on ly if the bus is free. The b us is free af ter a ST OP con dition or after the SCL
and SDA lines remain high for a specified time (see Section “22.3.5. SC L H igh ( SMBu s Fr ee) Timeout” on
page 228). In the event that two or more devices attempt to begin a transfer at the same time, an arbitra-
tion scheme is employed to force one master to give up the bus. The master devices continue transmitting
until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will be
pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The winning
SLA6
SDA SLA5-0 R/W D7 D6-0
SCL
Slave Address + R/W Data ByteSTART ACK NACK STOP
C8051F91x-C8051F90x
228 Rev. 1.1
master continues its transmission without interru ption; the losing master becomes a slave and receives the
rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and
no data is lost.
22.3.3. Clock Low Extension
SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different
speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow
slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line
LOW to extend the clock low period, effectively decreasing the serial clock frequency.
22.3.4. SCL Low Timeout
If the SCL line is held low b y a slave device on the bus, n o further communica tion is possible . Furthermore,
the master ca nnot for ce the SCL lin e high t o correct th e error condition. To solve this problem, the SMBus
protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than
25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communi-
cation no later than 10 ms after detecting the timeout condition.
When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeou ts. Timer 3 is forced to
reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to
overflow af ter 25 ms (and SMBTOE set), the T imer 3 interrup t service routine ca n be used to rese t (disable
and re-enable) the SMBus in the event of an SCL low timeout.
22.3.5. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus
is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and
SDA remain high for more than 10 SMBus clock source periods (as defined by the timer configured for the
SMBus clock source). If the SMBus is waiting to generate a Master START, the START will be generated
following this tim eout. Note that a clock source is re quired for free t imeout detection , even in a slave- only
implementation.
Rev. 1.1 229
C8051F91x-C8051F90x
22.4. Using the SMBus
The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con-
trol for serial transfers; higher level protocol is determined by user sof tware. The SMBus interface provides
the following application-independent features:
• Byte-wise serial data transfers
• Clock signal generation on SCL (Master Mode only) and SDA data synchronization
• Timeout/bus error recognition, as defined by the SMB0CF conf igu ra tio n re gis te r
• START/STOP timing , detection, and generation
• Bus arbitration
• Interrupt generation
• Status information
• Optional hardware recognition of slave address and automatic acknowledgement of address/data
SMBus interrupts are generated for each data byte or slave address that is transferred. When hardware
acknowledgement is disabled, the point at which the interrupt is generated depends on whether the hard-
ware is acting as a dat a transmitter or receiver. When a transmitter (i.e. sending address/data, receiving an
ACK), this interrupt is generated after the ACK cycle so that software may read the received ACK value;
when receiving data (i.e. receiving address/data, sending an ACK), this interrupt is generated before the
ACK cycle so that software may define the outgoing ACK value. If hardware ackn owled ge ment is en able d,
these interrupts are always generated after the ACK cycle. See Section 22.5 for more details on transmis-
sion sequences.
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or
the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control
register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section 22.4.2;
Table 22.5 provides a quick SMB0CN decoding reference.
C8051F91x-C8051F90x
230 Rev. 1.1
22.4.1. SMBus Configuration Register
The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes,
select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is
set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the
INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however,
the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit
is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of
the current tra ns fe r) .
The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolu te minimum SCL low and high times as defined in Equation 22.1. Note that the
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “25. Timers” on page 270.
Equation 22.1. Minimum SCL High and Low Times
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 22.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus ), th e typ ica l SMBus bit rate is approximated by Equation 22.2.
Equation 22.2. Typical SMBus Bit Rate
Figure 22.4 shows the typical SCL generation described by Equation 22.2. Notice that THIGH is typically
twice as large as TLOW. The actual SCL output may vary due to other devices on the bus (SCL may be
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 22.1.
Figure 22.4. Typical SMBus SCL Generation
Table 22.1. SMBus Clock Source Selection
SMBCS1 SMBCS0 SMBus Clock Source
0 0 Timer 0 Overflow
0 1 Timer 1 Overflow
1 0 Timer 2 High Byte Overflow
1 1 Timer 2 Low Byte Overflow
THighMin TLowMin 1
fClockSourceOverflow
----------------------------------------------
==
BitRate fClockSourceOverflow
3
----------------------------------------------
=
SCL
Timer Source
Overflows
SCL High Ti meoutT
Low
T
High
Rev. 1.1 231
C8051F91x-C8051F90x
Setting the EXTHOLD bit ext ends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time th at SDA is stable before SCL transit ions from low-to- high.
The minimum SDA hold time defin es the absolute minimum time that the curre nt SDA value remains stabl e
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Spe cification requir ements of 250 ns and 300 ns, respectively. Table 22.2 shows the min-
imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see Section “22.3.4. SCL Low Timeout” on page 228). The SMBus interface will force Timer 3 to
reload while SCL is hig h, and allow Timer 3 to count when SCL is low. The T imer 3 interrupt ser vice routin e
should be used to reset SMBus communication by disabling and re-enabling the SMBus.
SMBus Free T imeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 22.4).
Table 22.2. Minimum SDA Setup and Hold Times
EXTHOLD Minimum SDA Setup Time Minimum SDA Hold Time
0
Tlow – 4 system clocks
or
1 system clock + s/w delay*
3 system clocks
1 11 system clocks 12 system clocks
*Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When
using software acknowledgement, the s/w delay occurs between the time SMB0DAT
or ACK is written and when SI is cleared. Note that if SI is cleared in the same write
that defines the out going ACK value, s/w delay is zero.
C8051F91x-C8051F90x
232 Rev. 1.1
SFR Page = 0x0; SFR Address = 0xC1
SFR Definition 22.1. SMB0CF: SMBus Clock/Configuration
Bit76543210
Name ENSMB INH BUSY EXTHOLD SMBTOE SMBFTE SMBCS[1:0]
Type R/W R/W RR/W R/W R/W R/W
Reset 00000000
Bit Name Function
7ENSMB SMBus Enable.
This bit enables the SMBus interface when set to 1. When enabled, the interface
constantly monitors the SDA and SCL pins.
6INH SMBus Slave Inhibit.
When this bit is set to logic 1, the SMBus does not generate an interrupt when slave
events occur. This effectively rem oves the SMBus slave from the bus. Master Mode
interrupts are not affecte d.
5BUSY SMBus Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to
logic 0 when a STOP or free-timeout is sensed.
4EXTHOLD SMBus Setup and Hold Time Extension Enable.
This bit controls the SDA setup and hold times according to Table 22.2.
0: SDA Extended Setup and Hold Times disabled.
1: SDA Extended Setup and Hold Times enabled.
3SMBTOE SMBus SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces
Timer 3 to re load while SCL is hig h and allows Timer 3 to count when SCL goes low.
If T imer 3 is configured to Split Mode, only the High Byte of the timer is held in reload
while SCL is high. Timer 3 should be programmed to generate interrupts at 25 ms,
and the Timer 3 interrupt service routine should reset SMBus communication.
2SMBFTE SMBus Free T imeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain
high for more than 10 SMBus clock source periods.
1:0SMBCS[1:0] SMBus Clock Source Selection.
These two bit s select th e SMBus clock sour ce, which is used to generate the SMBus
bit rate. The selected device should be configured according to Equation 22.1.
00: Timer 0 Overflow
01: Timer 1 Overflow
10:Timer 2 High Byte Overflow
11: Ti mer 2 Low Byte Overflow
Rev. 1.1 233
C8051F91x-C8051F90x
22.4.2. SMB0CN Control Register
SMB0CN is used to control the interface and to provide status information (see SFR Definition 22.2). The
higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to
jump to service routines. MASTER indicates whether a device is the master or slave during the current
transfer. TXMODE indicates whether the device is transmitting or receiving data for the current byte.
STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus
interrupt. STA and STO are also used to genera te START and STOP conditions when operating as a mas-
ter. Writing a 1 to STA will cause the SMBus interface to enter Master Mode and generate a START when
the bus be comes fr ee (STA is not c leared b y hardwa re after the START is generated). Writing a 1 to STO
while in Master Mode will cause the interface to generate a STOP and end the current transfer after the
next ACK cycle. If STO and STA are both set (while in Master Mode), a STOP followed by a START will be
generated.
The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface
is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error condi-
tion. ARBLOST is cleared by hardware each time SI is cleared.
The SI bit (SMBus Interrupt Flag) is set at the beginn ing and end of each transfe r, after each byte frame, or
when an arbitration is lost; see Table 22.3 for more details.
Import ant Note About t he SI Bit : The SMBus interface is stalled while SI is set; thus SCL is held low, and
the bus is stalled until software clears SI.
22.4.2.1.Software ACK Generation
When the EHACK bit in register SMB0ADM is cleared to 0, the firmware on the device must detect incom-
ing slave addresses and ACK or NACK the slave address and incoming data bytes. As a receiver, writing
the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit indicates the value
received during the last ACK cycle. ACKRQ is set each time a byte is received, indicating that an outgoing
ACK value is needed. When ACKRQ is set, software should write the desired outgoing value to the ACK
bit before clearing SI. A NACK will be generated if software does not write the ACK bit before clearing SI.
SDA will reflect the defined ACK value immediately following a write to the ACK bit; however SCL will
remain low until SI is cleared. If a received slave address is not acknowledged, further slave events will be
ignored until the next START is detected.
22.4.2.2.Hardware ACK Generation
When the EHACK bit in register SMB0ADM is set to 1, automatic slave address recognition and ACK gen-
eration is enabled . More detail about automatic slave address recognition can be found in Sectio n 22.4.3.
As a receiver, the value currently s pecified by the ACK bit will be automatically sent on the bus during the
ACK cycle of an incoming data byte. As a transmitter, reading the ACK bit indicates the value received on
the last ACK cyc le. The ACKRQ bit is no t used when hardware ACK generation is enabled. If a received
slave address is NACKed by hardware, further slave events will be ignored until the next START is
detected, and no interrupt will be generated.
Table 22.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 22.5 for SMBus sta-
tus decoding using the SMB0CN register.
C8051F91x-C8051F90x
234 Rev. 1.1
SFR Page = 0x0; SFR Address = 0xC0; Bit-Addressable
SFR Definition 22.2. SMB0CN: SMBus Control
Bit76543210
Name MASTER TXMODE STA STO ACKRQ ARBLOST ACK SI
Type RRR/WR/WRRR/WR/W
Reset 00000000
Bit Name Description Read Write
7MASTER SMBus Master/Slave
Indicator. This read-on ly bit
indicates when the SMBus is
operating as a master.
0: SMBus operating in
slave mode.
1: SMBus operating in
master mode.
N/A
6TXMODE SMBus Transmit Mode
Indicator. This read-on ly bit
indicates when the SMBus is
operating as a tran smitter.
0: SMBus in Receiver
Mode.
1: SMBus in Transmitter
Mode.
N/A
5STA SMBus Start Flag. 0: No Start or repeated
Start detected.
1: Start or repeated Start
detected.
0: No Start generated.
1: When Configured as a
Master, initiates a START
or repeated START.
4STO SMBus Stop Flag. 0: No Stop condition
detected.
1: Stop condition detected
(if in Slave Mode) or pend-
ing (if in Master Mode).
0: No STOP condition is
transmitted.
1: When configured as a
Master, causes a STOP
condition to be transmit-
ted after the next ACK
cycle.
Cleared by Hardware.
3ACKRQ SMBus Acknowledge
Request. 0: No Ack requested
1: ACK requested N/A
2ARBLOST SMBus Arbitration Lost
Indicator. 0: No arbitration error.
1: Arbitration Lost N/A
1ACK SMBus Acknowledge. 0: NACK rece ived.
1: ACK received. 0: Send NACK
1: Send ACK
0SI SMBus Interrupt Flag.
This bit is set by hardware
under the conditions listed in
Table 15.3. SI must be cleared
by software. While SI is set,
SCL is held low and the
SMBus is stalled.
0: No interrupt pending
1: Interrupt Pending 0: Clear interrupt, and initi-
ate next state machine
event.
1: Force interrupt.
Rev. 1.1 235
C8051F91x-C8051F90x
Table 22.3. Sources for Hardware Changes to SMB0CN
Bit Set by Hardware When: Cleared by Hardware When:
MASTER • A START is generat ed. • A STOP is generated.
• Arbitration is lost.
TXMODE • START is generated.
• SMB0DAT is written before the start of an
SMBus frame.
• A START is detected.
• Arbitration is lost.
• SMB0DAT is not written before the
start of an SMBus frame.
STA • A START followed by an address byte is
received. • Must be cleared by software.
STO • A STOP is detected while addressed as a
slave.
• Arbitration is lost due to a detected STOP. • A pending STOP is generated.
ACKRQ • A byte has been received and an ACK
response value is needed (only when hard -
ware ACK is not enabled). • After each ACK cycle.
ARBLOST
• A repeated START is detected as a MASTER
when STA is low (unwanted repeated START).
• SCL is sensed low while attempting to gener-
ate a STOP or repeated START condition.
• SDA is sensed low while transmitting a 1
(excluding ACK bits).
• Each time SI is cleared.
ACK • The incoming ACK value is low
(ACKNOWLEDGE). • The incoming ACK value is high (NOT
ACKNOWLEDGE).
SI
• A START has been generated.
• Lost arbit ra tio n.
• A byte has been transmitted and an
ACK/NACK received.
• A byte has been received.
• A START or repeated START followed by a
slave address + R/W has been received.
• A STOP has been received.
• Must be cleared by software.
C8051F91x-C8051F90x
236 Rev. 1.1
22.4.3. Hardware Slave Address Recognition
The SMBus hardware has the capa bility to automatically recognize incoming slave addresses and send an
ACK without software intervention. Automatic slave address recognition is enabled by setting the EHACK
bit in register SMB0ADM to 1. This will enable both automatic slave address recognition and automatic
hardware ACK generation for received bytes (as a master or slave). More detail on automatic hardware
ACK generation can be found in Section 22.4.2.2.
The registers used to define which address(es) are recognized by the hardware are the SMBus Slave
Address register (SFR Definition 22.3) and the SMBus Slave Address Mask register (SFR Definitio n 22.4 ).
A single address or range of addresses (including the General Call Address 0x00) can be specified using
these two registers. The most-significant seven bits of the two registers are used to define which
addresses will be ACKed. A 1 in bit positions of the slave address mask SLVM[6:0] enable a comparison
between the received slave address and the hardware’s slave address SLV[6:0] for those bits. A 0 in a bit
of the slave address mask means that bit w ill be treated as a “don’t care” for comparison purposes. In this
case, either a 1 or a 0 value are acceptable on the incoming slave address. Additionally, if the GC bit in
register SMB0ADR is set to 1, hardware will recognize the General Call Address (0x00). Table 22.4 shows
some example parameter settings and the slave addresses that will be recognized by hardware under
those conditions.
Table 22.4. Hardware Address Recognition Examples (EHACK = 1)
Hardware Slave Address
SLV[6:0] Slave Address Mask
SLVM[6:0] GC bit Slave Addresses Recognized by
Hardware
0x34 0x7F 00x34
0x34 0x7F 10 x3 4, 0x00 (General Call)
0x34 0x7E 00x34, 0x35
0x34 0x7E 10 x34, 0x35, 0x00 (General Call)
0x70 0x73 00x70, 0x74, 0x78, 0x7C
Rev. 1.1 237
C8051F91x-C8051F90x
SFR Page = 0x0; SFR Address = 0xF4
SFR Page = 0x0; SFR Address = 0xF5
SFR Definition 22.3. SMB0ADR: SMBus Slave Address
Bit76543210
Name SLV[6:0] GC
Type R/W R/W
Reset 00000000
Bit Name Function
7:1SLV[6:0] SMBus Hardware Slave Address.
Defines the SMBus Slave Addr ess(es) for automatic hardware acknowledgement .
Only address bits which have a 1 in the corresponding bit position in SLVM[6:0]
are checked against the incoming address. This allows multiple addresses to be
recognized.
0GC General Call Address Enable.
When hardware address recognition is enabled (EHACK = 1), this bit will deter-
mine whether the General Call Address (0x00) is also recognized by hardware.
0: General Call Address is ignored.
1: General Call Address is recognized.
SFR Definition 22.4. SMB0ADM: SMBus Slave Address Mask
Bit76543210
Name SLVM[6:0] EHACK
Type R/W R/W
Reset 11111110
Bit Name Function
7:1SLVM[6:0] SMBus Slave Address Mask.
Defines which bits of register SMB0ADR are comp ared with an incoming address
byte, and which bits are ignored. Any bit set to 1 in SLVM[6:0] enables compari-
sons with the correspondin g bit in SL V[6:0]. Bit s set to 0 are ignored (ca n be either
0 or 1 in the incoming address).
0EHACK Hardware Acknowledge Enable.
Enables hardware acknowledgement of slave address and received data bytes.
0: Firmware must manually acknowledge all incoming address and data bytes.
1: Automatic Slave Address Recognition and Hardware Acknowledge is Enabled.
C8051F91x-C8051F90x
238 Rev. 1.1
22.4.4. Data Register
The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been
received. Software may safely read or write to the data register wh en the SI flag is se t. Sof tware should not
attempt to ac cess the SMB0DAT register when the SM Bus is enable d and the SI flag is cleared to logic 0,
as the interface may be in the process of shifting a byte of data into or out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received
data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously
being shifted in. SMB0DAT always contains the last data byte prese nt on the bu s. In th e even t of lost arb i-
tration, the transition from master transmitter to slave receiver is made with the correct data or address in
SMB0DAT.
SFR Page = 0x0; SFR Address = 0xC2
SFR Definition 22.5. SMB0DAT: SMBus Data
Bit76543210
Name SMB0DAT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0SMB0DAT[7:0] SMBus Data.
The SMB0DAT register contains a byte of data to be transmitted on the SMBus
serial interface or a byte th at has just been received on the SMBu s serial interface.
The CPU can read fr om or write to this re gister whenever the SI serial interrupt flag
(SMB0CN.0) is set to logic 1. The serial data in the register remains st able as long
as the SI flag is set. When the SI flag is not set, the system may be in the process
of shifting data in/out and the CPU should not attempt to access this register.
Rev. 1.1 239
C8051F91x-C8051F90x
22.5. SMBus Transfer Modes
The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be
operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or
Slave Receiver. The SMBus interface enters Master Mod e any time a START is generate d, an d remains in
Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end
of all SMBus byte frames. Note that the position of the ACK interrupt when operating as a receiver
depends on whether hardware ACK generation is enabled. As a receiver, the interrupt for an ACK occ urs
before the ACK with hardware ACK generation disabled, and after the ACK when hardware ACK genera-
tion is enabled. As a transm itter, interrupts occur after the ACK, regardless of whether hardware ACK gen-
eration is enabled or not.
22.5.1. Write Sequence (Master)
During a write sequence, an SMBus master writes data to a slave device. The master in this transfer will be
a transmitter during the ad dress byt e, and a tra nsmitte r during all data bytes. The SMBu s interfac e gener -
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then trans-
mits one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by
the slave. The transfer is ended when the STO bit is set and a STOP is generated. Note that the interface
will switch to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt.
Figure 22.5 shows a typical master write sequence. Two transmit data bytes are shown, though any num-
ber of bytes may be transmitted. Notice that all of the ‘data byte transferred’ interrupts occur after the ACK
cycle in this mode, regardless of whether hardware ACK generation is enabled.
Figure 22.5. Typical Master Write Sequence
A AAS W PData Byte Data ByteSLA
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Interrupts with Hardware ACK Disabled (EHACK = 0)
Interrupts with Hardware ACK Enabled (EHACK = 1)
C8051F91x-C8051F90x
240 Rev. 1.1
22.5.2. Read Sequence (Master)
During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will
be a transmitter during the a ddress byte, and a receiver during all dat a bytes. The SMBus interface gener-
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then
received from the slave o n SDA while th e SMBus outp ut s the seria l clock. The sla ve transmit s one o r more
bytes of serial data.
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,
and then post the interrupt. It is important to note that the appr opriate ACK or NACK value should be
set up by the software prior to receiving the byte when hardware ACK generat ion is enabled.
Writing a 1 to the ACK bit generates an ACK; writing a 0 generates a NACK. Software should write a 0 to
the ACK bit for the last data transfer, to transmit a NACK. The interface exits Master Receiver Mode after
the STO bit is set and a STOP is generated. The interface will switch to Master Transmitter Mode if
SMB0DAT is written while an active Master Receiver. Figure 22.6 shows a typical master read sequence.
Two received data bytes are shown, though any number of bytes may be received. Notice that the ‘data
byte transferred’ interrupt s occur at dif fere nt places in the sequence , depending on wheth er hardware ACK
generation is enabled. T he interrupt occurs before the ACK with hardware ACK generation disabled, and
after the ACK when har dware ACK generation is enabled.
Figure 22.6. Typical Master Read Sequence
Data ByteData Byte A NAS R PSLA
S = START
P = STOP
A = ACK
N = NACK
R = READ
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Interrupts with Hardware ACK Disabled (EHACK = 0)
Interrupts with Hardware ACK Enabled (EHACK = 1)
Rev. 1.1 241
C8051F91x-C8051F90x
22.5.3. Write Sequence (Slave)
During a write sequence, an SMBus master writes data to a slav e device. The slave in this transfer w ill be
a receiver during the address byte, and a receiver during all data bytes. When slave events are enabled
(INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direc -
tion bit (WRITE in this case) is received. If hardware ACK generation is disabled, upon entering Slave
Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The software must respond to the
received slave address with an ACK, or ignore the received slave address with a NACK. If hardware ACK
generation is enabled, the hardware will apply the ACK for a slave address which matches the criteria set
up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK cycle.
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the
next START is detected. If the received slave address is acknowledged, zero or more data bytes are
received.
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,
and then post the interrupt. It is important to note that the appr opriate ACK or NACK value should be
set up by the software prior to receiving the byte when hardware ACK generat ion is enabled.
The interface exits Slave Receiver Mode after receiving a ST OP. Note that the interface will switch to Slave
Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 22.7 shows a typical slave
write sequence. Two received data bytes are shown, though any number of bytes may be received. Notice
that the ‘data byte transferred’ interrupts occur at different places in the sequence, depending on whether
hardware ACK generation is enabled. The interrupt occurs before the ACK with hardware ACK generation
disabled, and after the ACK when hardware ACK generation is enabled.
Figure 22.7. Typical Slave Write Sequence
PWSLASData ByteData Byte A AA
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Interrupts with Hardware ACK Disabled (EHACK = 0)
Interrupts with Hardware ACK Enabled (EHACK = 1)
C8051F91x-C8051F90x
242 Rev. 1.1
22.5.4. Read Sequence (Slave)
During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will
be a receiver during the address byte, and a transmitter during all data bytes. When slave events are
enabled (INH = 0), the inter face enters Slave Receiver Mode (to receive the slave address) when a START
followed by a slave address and direction bit (READ in this case) is received. If hardware ACK gen eration
is disabled, upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The
software must respond to the received slave address with an ACK, or ignore the received slave address
with a NACK. If hardware ACK generation is enabled, the hardware will apply the ACK for a slave address
which matches the criteria set up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK
cycle.
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the
next START is detected. If the received slave ad dress is acknowledged , zero or more dat a b ytes are tr ans -
mitted. If the receiv ed sl ave ad dress is ac knowle dged, data should be writ ten to SMB0DAT to be transmit -
ted. The interface enter s Slave Transmitter Mode, an d transmit s one or more byte s of dat a. Af ter ea ch byte
is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT should
be written with the next data byte. If the acknowledge bit is a NACK, SMB0DAT should not be written to
before SI is cleared (Note: an error condition may be generated if SMB0DAT is written following a received
NACK while in Slave Transmitter Mode). The interface exits Slave Transmitter Mode after receiving a
STOP. Note that the interface will switch to Slave Receiver Mode if SMB0DAT is not written following a
Slave Transmitter interrupt. Figure 22.8 show s a typical slave read se quence. Two transm itted data bytes
are shown, though any number of bytes may be transmitted. Notice that all of the ‘data byte transferred’
interrupts occur after the ACK cycle in this mode, regardless of whether hardware ACK generation is
enabled.
Figure 22.8. Typical Slave Read Sequence
22.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. The appropriate actions to
take in response to an SMBus event depend on whether hardware slave address recognition and ACK
generation is enabled or disabled. Table 22.5 describes the typical actions when hardware slave address
recognition and ACK gene ration is disabled. Table 22.6 describes the typical actions when hardware slave
address recognition and ACK generation is enabled. In the tables, STATUS VECTOR refers to the four
upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown response o ptions are only the typ-
ical responses; application-specific procedures are allowed as long as they conform to the SMBus specifi-
cation. Highlighted responses are allo wed by hardware but do not conform to the SMBus specification.
PRSLASData ByteData Byte A NA
S = START
P = STOP
N = NACK
R = READ
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Interrupts with Hardware ACK Disabled (EHACK = 0)
Interrupts with Hardware ACK Enabled (EHACK = 1)
Rev. 1.1 243
C8051F91x-C8051F90x
Table 22.5. SMBus St atus Decoding With Hardware ACK Generation Disabled (EHACK = 0)
Mode
Values Read
Current SMbus State Typical Response Options
Values to
Write
Next Status
Vector Expe ct ed
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
Master Transmitter
1110 0 0 X A master START was gener-
ated. Load slave address + R/W into
SMB0DAT. 00X1100
1100
000
A master dat a or ad dress byte
was transmitted; NACK
received.
Set STA to restart transfer. 10X1110
Abort transfer. 01X -
001
A master dat a or ad dress byte
was transmitted; ACK
received.
Load next data byte into
SMB0DAT. 00X1100
End transfer with STOP. 01X -
End transfer with STOP and start
another tran sfe r. 11X -
Send repeated START. 10X1110
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT). 0 0 X 1000
Master Receiver
1000 1 0 X A master data byte was
received; ACK requ ested.
Acknowledge received byte;
Read SMB0DAT. 0 0 1 1000
Send NACK to indicate last by te,
and send STOP. 010 -
Send NACK to indicate last by te,
and send STOP followed by
START. 1101110
Send ACK followed by repeated
START. 1011110
Send NACK to indicate last by te,
and send repeated START. 1001110
Send ACK and switch to Master
Transmitter Mode (write to
SMB0DAT before clearing SI). 0 0 1 1100
Send NACK and switch to Mas-
ter Transmitter Mode (write to
SMB0DAT before clearing SI). 0 0 0 1100
C8051F91x-C8051F90x
244 Rev. 1.1
Slave Tr an sm itt er
0100
000
A slave byte was transmitted;
NACK received. No action required (expecting
STOP condition). 0 0 X 0001
001
A slave byte was transmitted;
ACK rece ived. Load SMB0DAT with next data
byte to transmit. 0 0 X 0100
01X
A Slave byte was transmitted;
error detected. No action required (expecting
Master to end transfer). 0 0 X 0001
0101 0 X X An illegal STOP or bus error
was detected while a Slave
Transmission was in progress. Clear STO. 00X -
Slave Receiver
0010
10X
A slave address + R/W was
received; ACK requ ested.
If Write, Acknowledge received
address 0 0 1 0000
If Read, Load SMB0DAT with
data byte; ACK re ceived addr ess 0 0 1 0100
NACK received address. 000 -
11X
Lost arbitra tio n as m ast er ;
slave address + R/W received;
ACK requested.
If Write, Acknowledge received
address 0 0 1 0000
If Read, Load SMB0DAT with
data byte; ACK re ceived addr ess 0 0 1 0100
NACK received address. 000 -
Reschedule failed transfer;
NACK received address. 1001110
0001 00X
A STOP was detected while
addresse d as a Slav e Trans-
mitter or Slave Rec eiver. Clear STO. 00X -
11X
Lost arbitration while attempt-
ing a STOP. No action required (transfer
complete/aborted). 000 -
0000 1 0 X A slave byte was received;
ACK requested.
Acknowledge received byte;
Read SMB0DAT. 0 0 1 0000
NACK received byte. 000 -
Bus Error Condition
0010 0 1 X Lost arbitration while attempt-
ing a repeated START. Abort failed transfer. 00X -
Reschedule failed transfer. 10X1110
0001 0 1 X Lost arbitra tio n du e to a
detected STOP. Abort failed transfer. 00X -
Reschedule failed transfer. 10X1110
0000 1 1 X Lost arbitration while transmit-
ting a dat a byte as master. Abort failed transfer. 000 -
Reschedule failed transfer. 1001110
T able 22.5. SMBus St atus Decoding With Hardware ACK Generation Disabled (EHACK = 0)
(Continued)
Mode
Values Read
Current SMbus State Typical Response Options
Values to
Write
Next Status
Vector Expected
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
Rev. 1.1 245
C8051F91x-C8051F90x
Table 22.6. SMBus St atus Decoding W ith Hardware ACK Generation Enabled (EHACK = 1)
Mode
Values Read
Current SMbus State Typical Response Options
Values to
Write
Next Status
Vector Expe ct ed
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
Master Transmitter
1110 0 0 X A master START was gener-
ated. Load slave address + R/W into
SMB0DAT. 00X1100
1100
000
A master dat a or ad dress byte
was transmitted; NACK
received.
Set STA to restart transfer. 10X1110
Abort transfer. 01X -
001
A master dat a or ad dress byte
was transmitted; ACK
received.
Load next data byte into
SMB0DAT. 00X1100
End transfer with STOP. 01X -
End transfer with STOP and start
another tran sfe r. 11X -
Send repeated START. 10X1110
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT). Set ACK for initial
data byte.
0 0 1 1000
Master Receiver
1000
001
A master data byte was
received; ACK sent.
Set ACK for next data byte;
Read SMB0DAT. 0 0 1 1000
Set NACK to indica te n ext data
byte as the last data byte;
Read SMB0DAT. 0 0 0 1000
Initiate repeated START. 1001110
Switch to Master Trans m itter
Mode (write to SMB0DAT before
clearing SI). 0 0 X 1100
000
A master data byte was
received; NACK sent (last
byte).
Read SMB0DAT; send STOP. 010 -
Read SMB0DAT; Send STOP
followed by START. 1101110
Initiate repeated START. 1001110
Switch to Master Trans m itter
Mode (write to SMB0DAT before
clearing SI). 0 0 X 1100
C8051F91x-C8051F90x
246 Rev. 1.1
Slave Tr an sm itt er
0100
000
A slave byte was transmitted;
NACK received. No action required (expecting
STOP condition). 0 0 X 0001
001
A slave byte was transmitted;
ACK rece ived. Load SMB0DAT with next data
byte to transmit. 0 0 X 0100
01X
A Slave byte was transmitted;
error detected. No action required (expecting
Master to end transfer). 0 0 X 0001
0101 0 X X An illegal STOP or bus error
was detected while a Slave
Transmission was in progress. Clear STO. 00X -
Slave Receiver
0010
00X
A slave address + R/W was
received; ACK sent.
If Write, Set ACK for first data
byte. 0 0 1 0000
If Read, Load SMB0DAT with
data byte 0 0 X 0100
01X
Lost arbitra tio n as m ast er ;
slave address + R/W received;
ACK sent.
If Write, Set ACK for first data
byte. 0 0 1 0000
If Read, Load SMB0DAT with
data byte 0 0 X 0100
Reschedule failed transfer 10X1110
0001 00X
A STOP was detected while
addresse d as a Slav e Trans-
mitter or Slave Rec eiver. Clear STO. 00X -
01X
Lost arbitration while attempt-
ing a STOP. No action required (transfer
complete/aborted). 000 -
0000 0 0 X A slave byte was received.
Set ACK for next data byte;
Read SMB0DAT. 0 0 1 0000
Set NACK for next data byte;
Read SMB0DAT. 0 0 0 0000
Bus Error Condition
0010 0 1 X Lost arbitration while attempt-
ing a repeated START. Abort failed transfer. 00X -
Reschedule failed transfer. 10X1110
0001 0 1 X Lost arbitra tio n du e to a
detected STOP. Abort failed transfer. 00X -
Reschedule failed transfer. 10X1110
0000 0 1 X Lost arbitration while transmit-
ting a dat a byte as master. Abort failed transfer. 00X -
Reschedule failed transfer. 10X1110
Table 22.6. SMBus S t atus Decoding With Hardware ACK Generation Enabled (EHACK = 1)
(Continued)
Mode
Values Read
Current SMbus State Typical Response Options
Values to
Write
Next Status
Vector Expected
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
Rev. 1.1 247
C8051F91x-C8051F90x
23. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud ra te su pport allows a wide ran ge of clock sources to gene rate standard baud rates (det ails
in Section “23.1. Enhanced Baud Rate Generation” on page 248). Received data buffering allow s UART0
to start reception of a second incoming data byte before software has finished reading the previous data
byte.
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0
always access the Transmit register. Reads of SBUF0 always access t he buf fered Receive regist er;
it is not possible to read data from the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardwa re when the CPU vectors to the in terrupt ser vice routine. They must be cle ared manually
by software, allowing sof tware to determine the cause of the UART0 interrupt (tran smit complete or rece ive
complete).
Figure 23.1. UART0 Block Diagram
UART Baud
Rate Generator
RI
SCON
RI
TI
RB8
TB8
REN
MCE
SMODE
Tx Control
Tx Clock Send
SBUF
(TX Shift )
Start
Data
Write to
SBUF
Crossbar
TX
Shift
Zero Detector
Tx IRQ
SET
QD
CLR
Stop Bit
TB8
SFR Bus
Serial
Port
Interrupt
TI
Port I/O
Rx Contr o l
Start
Rx Clock
Load
SBUF
Shift 0x1FF RB8
Rx IRQ
Input Shift Register
(9 bits)
Load SBUF
Read
SBUF
SFR Bus
Crossbar
RX
SBUF
(RX Latch)
C8051F91x-C8051F90x
248 Rev. 1.1
23.1. Enhanced Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 23.2), which is not user-
accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detecte d, independent of the TX Timer state.
Figure 23.2. UART0 Baud Rate Logic
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “25.1.3. Mode 2: 8-bit Coun-
ter/Timer with Auto-Reload” on page 274). The Timer 1 reload value should be set so that overflows will
occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of six
sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, the external oscillator clock / 8, or an exter-
nal input T1. For an y given Timer 1 clock source, the UART0 baud rate is determined by Equation 23.1-A
and Equation 23.1-B.
Equation 23.1. UART0 Baud Rate
Where T1CLK is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload
value). Timer 1 clock frequency is selected as described in Section “25.1. Timer 0 and Timer 1” on
page 272. A quick reference for typical baud rates and system clock frequencies is given in Table 23.1
through Table 23.2. Note that the internal oscillator may still generate the s ystem clock when the external
oscillator is driving Timer 1.
RX Timer
Start
Detected
Overflow
Overflow
TH1
TL1
TX Clock
2
RX Cl ock
2
Timer 1 UART
UartBaudRate 1
2
---T1_Overflow_Rate=
T1_Overflow_Rate T1CLK
256 TH1–
--------------------------
=
A)
B)
Rev. 1.1 249
C8051F91x-C8051F90x
23.2. Operational Modes
UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is
selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below.
Figure 23.3. UART Interconnect Diagram
23.2.1. 8-Bit UART
8-Bit UART mode uses a tot al of 10 bits per data byte: one st art bit, ei ght data bit s (LSB first) , and one stop
bit. Data are transmitted LSB first from the TX0 pin and received at the RX0 pin. On receive, the eight data
bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2).
Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Inter-
rupt Flag ( SCON0.1) is set at th e end of the transm ission (the beginning of the stop-bit time). Data recep-
tion can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
RI0 must be logic 0, and if MCE0 is logic 1, the stop bit must be logic 1. In the event of a receive dat a over-
run, the first received 8 bits are latched into the SBUF0 r eceive register and the following overrun data bits
are lost.
If these condition s ar e me t, the eight bits of data is st ored in SBUF0, the stop bit is stored in RB80 and the
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not
be set. An interrupt will occur if enabled when either TI0 or RI0 is set.
Figure 23.4. 8-Bit UART Timing Diagram
OR
RS-232
C8051Fxxx
RS-232
LEVEL
XLTR
TX
RX
C8051Fxxx
RX
TX
MCU RX
TX
D1D0 D2 D3 D4 D5 D6 D7
START
BIT
MARK STOP
BIT
BIT TIMES
BIT SAMPLING
SPACE
C8051F91x-C8051F90x
250 Rev. 1.1
23.2.2. 9-Bit UART
9-bit UART mode uses a total of eleven bits pe r data byte: a start bit, 8 data bits (LSB first), a programma-
ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80
(SCON0.3), which is assigned by user so f twa re. It ca n be assigned the value of the parity flag (bit P in reg-
ister PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit
goes into RB80 (SCON0.2) and the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
(1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when MCE0 is logic 0, the
state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in
SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to 1. If the above conditions are not met,
SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to 1. A UART0 interrupt will occur if
enabled when either TI0 or RI0 is set to 1.
Figure 23.5. 9-Bit UART Timing Diagram
23.3. Multiprocessor Communications
9-Bit UART mode supports multiprocessor communication between a master processor and one or more
slave processors by special use of the ninth dat a bit. When a master p rocessor wants to transmit to one or
more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte
in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logi c 0.
Setting the MCE0 bit (SCON0.5) of a slave processor configures its UART such that when a stop bit is
received, the UART will generate an interrupt only if the ninth bit is logic 1 (R B80 = 1) signifying a n address
byte has been received. In the UART interrupt handler, software will compare the received address with
the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE0 bit to enable
interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE0
bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the
data. Once the entire message is received, the addressed slave resets its MCE0 bit to ignore all transmis-
sions until it receives the next address byte.
Multiple addresses ca n be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master
processor can be configured to receive all transmissions or a protocol can be implemented such that the
master/slave role is temporarily reversed to enable half-duplex transmission between the original master
and slave(s).
D1D0 D2 D3 D4 D5 D6 D7
START
BIT
MARK STOP
BIT
BIT TIMES
BIT SAMPLING
SPACE D8
Rev. 1.1 251
C8051F91x-C8051F90x
Figure 23.6. UART Multi-Processor Mode Interconnect Diagram
Master
Device Slave
Device
TXRX RX TX
Slave
Device
RX TX
Slave
Device
RX TX
V+
C8051F91x-C8051F90x
252 Rev. 1.1
SFR Page = 0x0; SFR Address = 0x98; Bit-Addressable
SFR Definition 23.1. SCON0: Serial Port 0 Control
Bit76543210
Name S0MODE MCE0 REN0 TB80 RB80 TI0 RI0
Type R/W R R/W R/W R/W R/W R/W R/W
Reset 01000000
Bit Name Function
7S0MODE Serial Port 0 Operation Mode.
Selects the UART0 Operation Mode.
0: 8-bit UART with Variable Baud Rate.
1: 9-bit UART with Variable Baud Rate.
6Unused Unused.
Read = 1b. Write = Don’t Care.
5MCE0 Multiprocessor Communication Enab le.
For Mode 0 (8-bit UART): Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop bit is logic level 1.
For Mode 1 (9-bit UART): Multiprocessor Communications Enable.
0: Logic level of ninth bit is ignored.
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1.
4REN0 Receive Enable.
0: UART0 reception disabled.
1: UART0 reception ena bled.
3TB80 Ninth Transmission Bit.
The logic level of this bit will be sent as the ninth transmission bit in 9-bit UART Mode
(Mode 1). Unused in 8-bit mode (Mode 0).
2RB80 Ninth Receive Bit.
RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the
9th data bit in Mode 1.
1TI0 Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit
in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When
the UART0 in terrupt is enable d, setting this bit causes the CPU to vector to the UAR T0
interrupt se rvic e ro ut ine . This bit must be cleared manually by software.
0 RI0 Receive Interrupt Flag.
Set to 1 by hardware when a byte of data has been received by UART0 (set at the
STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to 1
causes the CPU to vector to the UART0 interrupt service routine. This bit must be
cleared manually by software.
Rev. 1.1 253
C8051F91x-C8051F90x
SFR Page = 0x0; SFR Address = 0x99
SFR Definition 23.2. SBUF0: Serial (UART0) Port Data Buffer
Bit76543210
Name SBUF0[7:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 SBUF0 Serial Data Buffer Bits 7:0 (MSB–LSB).
This SFR accesses two registers; a transmit shift register a nd a receive latch reg ister .
When data is written to SBUF0, it goes to the transmit shift register and is held for
serial transm issio n. Writing a byte to SBUF0 initiates the transmission. A read of
SBUF0 returns the contents of the receive latch.
C8051F91x-C8051F90x
254 Rev. 1.1
Table 23.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator
Frequency: 24.5 MHz
Target
Baud Rate
(bps)
Baud Rate
% Error Oscilla-
tor Divide
Factor
Timer Clock
Source SCA1–SCA0
(pre-scale
select)1
T1M1Timer 1
Reload
Value (hex)
SYSCLK from
Internal Osc.
230400 –0.32% 106 SYSCLK XX21 0xCB
115200 –0.32% 212 SYSCLK XX 1 0x96
57600 0.15% 426 SYSCLK XX 1 0x2B
28800 –0.32% 848 SYSCLK/4 01 0 0x96
14400 0.15% 1704 SYSCLK/12 00 0 0xB9
9600 –0.32% 2544 SYSCLK/12 00 0 0x96
2400 –0.32% 10176 SYSCLK/48 10 0 0x96
1200 0.15% 20448 SYSCLK/48 10 0 0x2B
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 25.1.
2. X = Don’t care.
Table 23.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator
Frequency: 22.1184 MHz
Target
Baud Rate
(bps)
Baud Rate
% Error Oscilla-
tor Divide
Factor
Timer Clock
Source SCA1–SCA0
(pre-scale
select)1
T1M1Timer 1
Reload
Value (hex)
SYSCLK from
External Osc.
230400 0.00% 96 SYSCLK XX210xD0
115200 0.00% 192 SYSCLK XX 1 0xA0
57600 0.00% 384 SYSCLK XX 1 0x40
28800 0.00% 768 SYSCLK / 12 00 0 0xE0
14400 0.00% 1536 SYSCLK / 12 00 0 0xC0
9600 0.00% 2304 SYSCLK / 12 00 0 0xA0
2400 0.00% 9216 SYSCLK / 48 10 0 0xA0
1200 0.00% 18432 SYSCLK / 48 10 0 0x40
SYSCLK from
Internal Osc.
230400 0.00% 96 EXTCLK / 8 11 0 0xFA
115200 0.00% 192 EXTCLK / 8 11 0 0xF4
57600 0.00% 384 EXTCLK / 8 11 0 0xE8
28800 0.00% 768 EXTCLK / 8 11 0 0xD0
14400 0.00% 1536 EXTCLK / 8 11 0 0xA0
9600 0.00% 2304 EXTCLK / 8 11 0 0x70
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 25 . 1.
2. X = Don’t care.
Rev. 1.1 255
C8051F91x-C8051F90x
24. Enhanced Serial Peripheral Interface (SPI0 and SPI1)
The enhanced serial peripheral interfaces (SPI0 and SPI1) provide access to two identical, flexible, full-
duplex synchronous serial busses. Both SPI0 and SPI1 will be referred to collectively as SPIn. SPIn can
operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and
slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select SPIn in
slave mode, or to disable Master Mode operation in a multi-master environment, avoiding contention on
the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be config-
ured as a chip-select output in master mode, or disabled for 3-wire operation. Additional general purpose
port I/O pins can be used to select multiple slave devices in master mode.
Figure 24.1. SPI Block Diagram
SFR Bus
Data Path
Control
SFR Bus
Write
SPI0DAT
Receive Data Buffer
SPInDAT
01234567 Shift Register
SPI CONTROL LOGIC
SPInCKR
SCR7
SCR6
SCR5
SCR4
SCR3
SCR2
SCR1
SCR0
SPInCFG SPInCN
Pin Interface
Control
Pin
Control
Logic
C
R
O
S
S
B
A
R
Port I/O
Read
SPI0DAT
SPIn IRQ
Tx Data
Rx Data
SCK
MOSI
MISO
NSS
Tran smit Data Buffer
Clock Divide
Logic
SYSCLK
CKPHA
CKPOL
SLVSEL
NSSnMD1
NSSnMD0
SPIBSY
MSTEN
NSSIN
SRMT
RXBMT
SPIFn
WCOLn
MODFn
RXOVRNn
TXBMTn
SPInEN
C8051F91x-C8051F90x
256 Rev. 1.1
24.1. Signal Descriptions
The four signals used by each SPIn (MOSI, MISO, SCK, NSS) are described below.
24.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master dev ice an d an inpu t to s lave de vices. I t
is used to serially trans fer data from the ma ster to th e slave. This signal is an output when SPIn is operat-
ing as a master anSPInd an input when SPIn is operating as a slave. Data is transferred most-significant
bit first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire
mode.
24.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device.
It is used to serially transfer data from the slave to the master. This signal is an input when SPIn is operat-
ing as a master and an output when SPIn is operating as a slave. Data is transferred most-significant bit
first. The MISO pin is placed in a high-impeda nce sta te when the SPI module is di sabled and when th e SPI
operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is
always driven by the MSB of the shift register.
24.1.3. Serial Clock (SCK)
The serial cl ock (SCK) signal is an outp ut from the ma ster device and an input to slave devices. It is used
to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPIn gen-
erates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is
not selected (NSS = 1) in 4-wire slave mode.
24.1.4. Slave Select (NSS)
The function of the slave-select (NSS) signal is dependent on the setting of the NSSnMD1 and NSSnMD0
bits in the SPInCN register. There are three possible modes that can be selected with these bits:
1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPIn operates in 3-wire mode, and
NSS is disabled. When operating as a slave device, SP In is always selected in 3-wire mode.
Since no select signal is present, SPIn must be the only slave on the bus in 3-wire mode. This
is intended for point-to-point communication between a master and one slave.
2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPIn operates in 4-wire mode, and
NSS is enabled as an input. When operating as a slave, NSS selects the SPIn device. When
operating as a master, a 1-to-0 transition of the NSS signal disables the master function of
SPIn so that multiple master devices can be used on the same SPI bus.
3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPIn operates in 4-wire mode, and NSS is enabled as
an output. The setting of NSSMD0 determines what logic level the NSS pin will output. This
configuration should only be used when operating SPIn as a master device.
See Figure 24.2, Figure 24.3, and Figure 24.4 for typical connection diagrams of the various operational
modes. The setting of NSSMD bits affects the pinout of the device. When in 3-wire master or 3-wire
slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will be
mapped to a p in on the de vice. See Section “21. Port Input/Output” on p age 205 for g eneral purp ose port I/
O and crossbar information.
Rev. 1.1 257
C8051F91x-C8051F90x
24.2. SPI Master Mode Operation
A SPI master device initiates all data transfers on a SPI bu s. SPIn is p lac ed in m ast er m ode by se ttin g the
Master Enable flag (MSTENn, SPInCN.6 ). W riting a byte of d at a to the SPIn data register (SPInDAT) when
in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer
is moved to the shift registe r, and a da ta transfer begins. The SPIn master immediately shifts out the data
serially on the MOSI line while providing the serial clock on SCK. The SPIFn (SPInCN.7) flag is set to logic
1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag
is set. While the SPIn master transfers data to a slave on the MOSI line, the addressed SPI slave device
simultaneously transfer s the content s of it s sh if t register to the SPI master on the MISO line in a full-duplex
operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The
data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is
fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by
reading SPInDAT.
When configured as a master, SPIn can operate in one of three dif ferent mo des: multi-master mode, 3-wir e
single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when
NSSnMD1 (SPInCN.3) = 0 and NSSnMD0 (SPInCN.2) = 1. In this mode, NSS is an input to the device,
and is used to disable the master SPIn whe n another master is accessing the bus. When NSS is pulled low
in this mode, MSTENn (SPInCN.6) and SPIENn (SPInCN.0) are set to 0 to disable the SPI master device,
and a Mode Fault is generated (MODFn, SPInCN.5 = 1). Mode Fault will generate an interrupt if enabled.
SPIn must be manually re-enabled in software under these circumstances. In multi-master systems,
devices will typically default to being slave devices while they are not acting as the system master device.
In multi-master mode, slave devices can be addressed individually (if needed) using general-purpose I/O
pins. Figure 24.2 shows a connection diagram between two master devices in multiple-master mode.
3-wire single-master mode is active when NSSnMD1 (SPInCN.3) = 0 and NSSnMD0 (SPInCN.2) = 0. In
this mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave
devices that must be addressed in this mode should be selected using general-purpose I/O pins.
Figure 24.3 shows a connection diagram between a master device in 3-wire master mode and a slave
device.
4-wire single-master mode is active when NSSnMD1 (SPInCN.3) = 1. In this mode, NSS is configured as
an output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output
value of NSS is controlled (in sof tware ) with the bi t NSSn MD0 (SPIn CN.2). Addition al slave devices can be
addressed using gene ral-p urpose I/O pins. Figure 24.4 shows a connection diagra m for a master device i n
4-wire master mode and two slave devices.
C8051F91x-C8051F90x
258 Rev. 1.1
Figure 24.2. Multiple-Master Mode Connection Diagram
Figure 24.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
Figure 24.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
Master
Device 2
Master
Device 1
MOSI
MISO
SCK
MISO
MOSI
SCK
NSS
GPIO NSS
GPIO
Slave
Device
Master
Device
MOSI
MISO
SCK
MISO
MOSI
SCK
Slave
Device
Master
Device
MOSI
MISO
SCK
MISO
MOSI
SCK
NSS NSS
GPIO
Slave
Device
MOSI
MISO
SCK
NSS
Rev. 1.1 259
C8051F91x-C8051F90x
24.3. SPI Slave Mode Operation
When SPIn is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are
shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK sig-
nal. A bit counte r in the SPIn logic cou nts SCK edges. When 8 bits have be en shifted through the shif t reg -
ister, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the
receive buffer by reading SPInDAT. A slave device cannot initiate transfers. Data to be transferred to the
master device is pre-loaded into the shift register by writing to SPInDAT. Writes to SPInDAT are double-
buffe red, and are placed in the transmit bu f fer first. If the shif t re gister is e mpty, the contents of the transmit
buffer will immediately be transferred into the shift register. When the shift register already contains data,
the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or
current) SPI transfer.
When configured as a slave, SPIn can be configured for 4-wire or 3-wire operation. The default, 4-wire
slave mode, is active when NSSnMD 1 (SPIn CN.3) = 0 and NSSn MD0 (SPInCN.2) = 1. In 4-wir e mode, the
NSS signal is routed to a port pin and configured as a digital input. SPIn is enabled when NSS is logic 0,
and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS sig-
nal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer.
Figure 24.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master
device.
3-wire slave mode is active when NSSnMD1 (SPInC N.3) = 0 and NSSnMD0 (SPInCN.2) = 0. NSS is no t
used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of
uniquely addressing the device in 3-wire slave mode, SPIn must be the only slave device present on the
bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter
that determines when a full byte has been received. The bit counter can only be reset by disabling and re-
enabling SPIn with the SPIEN bit. Figure 24.3 shows a connection diagram between a slave device in 3-
wire slave mod e and a ma ster device.
24.4. SPI Interrupt Sources
When SPIn interrupts are enabled, the following four flags will generate an interrupt when they are set to
logic 1:
All of the following bits must be cleared by software.
1. The SPI Interrupt Flag, SPIFn (SPInCN.7) is set to logic 1 at the end of each byte transfer.
This flag can occur in all SPIn modes.
2. The Write Collision Flag, WCOLn (SPInCN.6) is set to logic 1 if a write to SPInDAT is
attempted when the transmit buffer has not been emptied to the SPI shift register. When this
occurs, the write to SPInDAT will be ignored, and the transmit buffer will not be written.This
flag can occur in all SPIn modes.
3. The Mode Fault Flag MODFn (SPInCN.5) is set to logic 1 when SPIn is configured as a
master, and for multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs,
the MSTENn and SPIENn bits in SPI0CN are set to logic 0 to disable SPIn and allow another
master device to access the bus.
4. The Receive Overrun Flag RXOVRNn (SPInCN.4) is set to logic 1 when configured as a slave,
and a transfer is completed and the receive buffer still holds an unread byte from a previous
transfer. The n ew byt e is no t tr an sf er re d to th e r eceive bu ffer, allowing th e p re vio us ly re ce ived
data byte to be read. The data byte which caused the overrun is lost.
C8051F91x-C8051F90x
260 Rev. 1.1
24.5. Serial Clock Phase and Polarity
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI
Configuration Register (SPInCFG). The CKPHA bit (SPInCFG.5) selects one of two clock phases (edge
used to latch the data). The CKPOL bit (SPInCFG.4) selects between an active-high or active-low clock.
Both master and slave devices must be configured to use the same clock phase and polarity. SPI0 should
be disabled (by clearing the SPIENn bit, SPInCN.0) when changing the clock phase or polarity. The clock
and data line relationships for master mode are shown in Figure 24.5. For slave mode, the clock and data
relationships are shown in Figure 24.6 and Figure 24.7. Note that CKPHA must be set to 0 on both the
master and slave SPI when communicating between two of the following devices: C8051F04x,
C8051F06x, C8051F12x, C8051F31x, C8051F32x, and C8051F33x.
The SPIn Clock Rate Register (SPInCKR) as shown in SFR Definition 24.3 controls the master mode
serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured
as a master, the maximum data transfe r rate (bit s/sec) is one-half the system clock frequency or 12.5 MHz,
whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for
full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4-
wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master
issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec)
must be less than 1/10 the system clock frequency. In the special case where the master only wants to
transmit data to the slave and does no t need to receive data from the slave (i.e. half-duplex operation), the
SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency.
This is provided that the master issues SCK, NSS, and the seri al input data synchronously with the slave’s
system clock.
Figure 24.5. Master Mode Data/Clock Timing
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MISO/MOSI
NSS (Must Remain High
in Multi-Master Mode)
Rev. 1.1 261
C8051F91x-C8051F90x
Figure 24.6. Slave Mode Data/Clock Timing (CKPHA = 0)
Figure 24.7. Slave Mode Data/Clock Timing (CKPHA = 1)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MISO
NSS (4-Wire Mode)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MOSI
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=1)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MISO
NSS (4-Wir e Mode)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MOSI
C8051F91x-C8051F90x
262 Rev. 1.1
24.6. SPI Special Function Registers
SPI0 and SPI1 are accessed and controlled through four special function registers (8 registers total) in the
system controller: SPInCN Control Register, SPInDAT Data Register, SPInCFG Configuration Register,
and SPInCKR Clock Rate Register. The special function registers related to the operation of the SPI0 and
SPI1 Bus are described in the following figures.
Rev. 1.1 263
C8051F91x-C8051F90x
SFR Addresses: SPI0CFG = 0xA1, SPI1CFG = 0x84
SFR Pages: SPI0CFG = 0x0, SPI1CFG = 0x0
SFR Definition 24.1. SPInCFG: SPI Configuration
Bit 7 6 5 4 3 2 1 0
Name SPIBSY MSTEN CKPHA CKPOL SLVSEL NSSIN SRMT RXBMT
Type R R/W R/W R/W R R R R
Reset 0000011 1
Bit Name Function
7SPIBSY SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
6MSTEN Master Mode Enable.
0: Disable master mo de . Op er at e in slave mode.
1: Enable master mode. Operate as a master.
5CKPHA SPI Clock Phase.
0: Data centered on first edge of SCK period.*
1: Data centered on secon d edge of SCK period.*
4CKPOL SPI Clock Polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
3SLVSEL Slave Selected Flag.
Set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected slave. It
is cleared to logic 0 when NSS is high (slave not selected). This bit does not indi-
cate the instant aneous va lue at the NSS pin, but rather a de-g litched version of the
pin input.
2NSSIN NSS Instantaneous Pin Input.
This bit mimics the instantaneous value that is present on the NSS port pin at the
time that the register is read. This input is not de-glitched.
1SRMT Shif t Register Empty (valid in slave mode only).
Set to logic 1 when data has been tr ansferred in/out of the shift register, and there
is no data is availabl e to read fr om the transmit b uf f er or write to the r eceive buffer.
Set to logic 0 when a data byte is transferred to the shift register from the transmit
buffer or by a transition on SCK. Note: SRMT = 1 in Master Mode.
0RXBMT Receive Buffer Empty (valid in slave mode only).
Set to logic 1 when the receive buffer has been read and contains no new informa-
tion. If there is new information available in the receive buffer that has not bee n
read, this bit will return to logic 0. Note: RXBMT = 1 in Master Mode.
*Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is
sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device.
See Table 24.1 for timing parameters.
C8051F91x-C8051F90x
264 Rev. 1.1
SFR Addresses: SPI0CN = 0xF8, Bit-Addressable; SPI1CN = 0xB0, Bit-Addressable
SFR Pages: SPI0CN = 0x0, SPI1CN = 0x0
SFR Definition 24.2. SPInCN: SPI Control
Bit 7 6 5 4 3 2 1 0
Name SPIFn WCOLn MODFn RXOVRNn NSSnMD1 NSSnMD0 TXBMTn SPInEN
Type R/W R/W R/W R/W R/W R/W R R/W
Reset 000 0 0 1 1 0
Bit Name Function
7SPIFn SPIn Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are
enabled, setting this bit causes the CPU to vector to the SPIn interrupt service
routine. This bit is not automatically cleared by hardware. It must be cleared by
software.
6WCOLn Write Collision Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) to indicate a
write to the SPI0 dat a register was attempted while a data transfe r was in progress.
It must be cleared by software.
5MODFn Mode Fault Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when a mas-
ter mode collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01).
This bit is not automatically cleared by hardware. It must be cleared by software.
4RXOVRNn Receive Overrun Flag (valid in slave mode only).
This bit is set to logic 1 by hardware (and generates a SPIn interrupt) when the
receive buffer still holds unread data from a previous transfer and the last bit of the
current transfer is shifted into the SPI shift register. This bit is not automatically
cleared by hardware. It must be cleared by software.
3:2 NSSnMD[1:0] Slave Select Mode.
Selects be tween the following NSS operation modes:
(See Section 24.2 and Section 24.3).
00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is no t routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the
device and will assume the value of NSSMD0.
1TXBMTn Transmit Buffer Empty.
This bit will be set to logic 0 when new dat a has been written to the transmit buffer .
When data in the transmit buffer is transferred to the SPI shift register, this bit will
be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer.
0SPInEN SPIn Enable.
0: SPIn disabled.
1: SPIn enabled.
Rev. 1.1 265
C8051F91x-C8051F90x
SFR Addresses: SPI0CKR = 0xA2, SPI1CKR = 0x85
SFR Pages: SPI0CKR = 0x0, SPI1CKR = 0x0
SFR Definition 24.3. SPInCKR: SPI Clock Rate
Bit 7 6 5 4 3 2 1 0
Name SCRn[7:0]
Type R/W
Reset 0000000 0
Bit Name Function
7:0 SCRn SPI Clock Rate.
These bits determine the frequency of the SCK output when the SPI module is
configured for master mode operation. The SCK clock frequency is a divided
version of the system clock, and is given in th e following equation, wher e SYSCLK
is the system clock frequency and SPInCKR is the 8-bit valu e held in the SPInCKR
register.
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPInCKR = 0x04,
fSCK SYSCLK
2 SPInCKR[7:0] 1+
-----------------------------------------------------------
=
fSCK 2000000
241+
--------------------------
=
fSCK 200kHz=
C8051F91x-C8051F90x
266 Rev. 1.1
SFR Addresses: SPI0DAT = 0xA3, SPI1DAT = 0x86
SFR Pages: SPI0DAT = 0x0, SPI1DAT = 0x0
SFR Definition 24.4. SPInDAT: SPI Data
Bit 7 6 5 4 3 2 1 0
Name SPInDAT[7:0]
Type R/W
Reset 0000000 0
Bit Name Function
7:0 SPInDAT SPIn Transmit and Receive Data.
The SPInDAT register is used to transmit and receive SPIn data. Writing data to
SPInDAT places the data into the transmit buffer and initiates a transfer when in
Master Mode. A read of SPInDAT returns the contents of the receive buffer.
Rev. 1.1 267
C8051F91x-C8051F90x
Figure 24.8. SPI Master Timing (CKPHA = 0)
Figure 24.9. SPI Master Timing (CKPHA = 1)
SCK*
T
MCKH
T
MCKL
MOSI
T
MIS
MISO
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
MIH
SCK*
T
MCKH
T
MCKL
MISO
T
MIH
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
MIS
C8051F91x-C8051F90x
268 Rev. 1.1
Figure 24.10. SPI Slave Timing (CKPHA = 0)
Figure 24.11. SPI Slave Timing (CKPHA = 1)
SCK*
T
SE
NSS
T
CKH
T
CKL
MOSI
T
SIS
T
SIH
MISO
T
SD
T
SOH
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
SEZ
T
SDZ
SCK*
T
SE
NSS
T
CKH
T
CKL
MOSI
T
SIS
T
SIH
MISO
T
SD
T
SOH
* SCK is shown for CKP OL = 0. SCK is the opposite polarity for CK POL = 1.
T
SLH
T
SEZ
T
SDZ
Rev. 1.1 269
C8051F91x-C8051F90x
Table 24.1. SPI Slave Timing Paramete rs
Parameter Description Min Max Units
Master Mode Timing* (See Figure 24.8 and Figure 24.9)
TMCKH SCK High Time 1 x TSYSCLK —ns
TMCKL SCK Low Time 1 x TSYSCLK —ns
TMIS MISO Valid to SCK Shift Edge 1 x TSYSCLK + 20 —ns
TMIH SCK Shift Edge to MISO Change 0 — ns
Slave Mode Timing* (See Figure 24.10 and Figure 24.11)
TSE NSS Falling to First SCK Edge 2 x TSYSCLK —ns
TSD Last SCK Edge to NSS Rising 2 x TSYSCLK —ns
TSEZ NSS Falling to MISO Valid — 4 x TSYSCLK ns
TSDZ NSS Rising to MISO High-Z — 4 x TSYSCLK ns
TCKH SCK High Time 5 x TSYSCLK —ns
TCKL SCK Low Time 5 x TSYSCLK —ns
TSIS MOSI Valid to SCK Sample Edge 2 x TSYSCLK —ns
TSIH SCK Sample Edge to MOSI Change 2 x TSYSCLK —ns
TSOH SCK Shift Edge to MISO Change — 4 x TSYSCLK ns
TSLH Last SCK Edge to MISO Change
(CKPHA = 1 ONLY) 6 x TSYSCLK 8 x TSYSCLK ns
*Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
C8051F91x-C8051F90x
270 Rev. 1.1
25. Timers
Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the
standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose
use. These timers can be used to measure time intervals, count external events and generate periodic
interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation.
Timer 2 and T imer 3 offer 16- bit and split 8-bit timer functionality with auto-reload. Add itionally, T imer 2 an d
Timer 3 have a Capture Mode that can be used to measure the SmaRTClock or a Comparator period with
respect to another oscillator. This is particularly useful when using Capacitive Touch Switches.
Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M–
T0M) and the Clock Scale bits (SCA1–SCA0). The Clock Scale bits define a pre-scaled clock from which
Timer 0 and/or Timer 1 may be clocked (Se e SFR Definition 25.1 for pre-scaled clock selection).
Timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. Timer 2 and
Timer 3 may be clocked by the system clock, the system clock divided by 12. Timer 2 may additionally be
clocked by the SmaRTClock divided by 8 or the Comparator0 output. Timer 3 may additionally be clocked
by the external oscillator clock source divided by 8 or the Comparator1 output.
Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer
register is incremented on each high-to-low transition at the selected input pin (T0 or T1). Events with a
frequency of up to one-fourth the system clock frequency can be counted. The input signal need not be
periodic, but it shou ld b e he ld at a giv en leve l for at least two full system clock cycles to ens ure the lev el is
properly sampled.
Timer 0 and Timer 1 Modes: Timer 2 Modes: Timer 3 Modes:
13-bit counter/timer 16-bit timer with auto -r elo a d 16 - bit timer wit h auto -r elo a d
16-bit counter/timer
8-bit counter/timer with auto-
reload Two 8-bit timers with auto-reload Two 8-bit timers with auto-reload
Two 8-bit counter/timers (Timer 0
only)
Rev. 1.1 271
C8051F91x-C8051F90x
SFR Page = 0x0; SFR Address = 0x8E
SFR Definition 25.1. CKCON: Clock Control
Bit76543210
Name T3MH T3ML T2MH T2ML T1M T0M SCA[1:0]
Type R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7T3MH Timer 3 High Byte Clock Select.
Selects the clock supplied to the Timer 3 high byte (split 8-bit timer mode only).
0: Timer 3 high byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 high byte uses the system clock.
6T3ML Timer 3 Low Byte Clock Select.
Selects the clock supplied to Timer 3. Selects the clock supplied to the lower 8-bit timer
in split 8-bit timer mode.
0: Timer 3 low byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 low byte uses the system clock.
5T2MH Timer 2 High Byte Clock Select.
Selects the clock supplied to the Timer 2 high byte (split 8-bit timer mode only).
0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 high byte uses the system clock.
4T2ML Timer 2 Low Byte Clock Select.
Selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer mode,
this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 low byte uses the system clock.
3T1M Timer 1 Clock Select.
Selects the clock sour ce supplied to Timer 1. Ignored when C/T1 is set to 1.
0: Timer 1 uses the clock defined by the prescale bits SCA[1:0].
1: Timer 1 uses the system clock.
2T0M Timer 0 Clock Select.
Selects the clock sour ce supplied to Timer 0. Ignored when C/T0 is set to 1.
0: Counter/Timer 0 uses the clock defined by the prescale bi ts SCA[1:0].
1: Counter/Timer 0 uses the system clock.
1:0 SCA[1:0] Timer 0/1 Prescale Bits.
These bits control the Timer 0/1 Clock Prescaler:
00: System clock divided by 12
01: System clock divided by 4
10: System clock divided by 48
11: External clock divided by 8 (synchronize d with the system clock)
C8051F91x-C8051F90x
272 Rev. 1.1
25.1. Timer 0 and Timer 1
Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1)
and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and
Timer 1 as we ll as indicate status. Timer 0 interrupts can be enable d by sett ing the ET 0 bit in th e IE regis -
ter (Section “12.5. Interrupt Reg ister Descrip tions” on page 123); Timer 1 interrupts can be enabled by set-
ting the ET1 bit in the IE register (Section “12.5. Interrupt Register Descriptions” on page 123). Both
counter/timers operate in on e of four primary modes selected by setting the Mode Select bits T1 M1–T0M0
in the Counter/Timer Mode register (TMOD). Each timer can be configured independently. Each operating
mode is described be low.
25.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration
and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same
manner as described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions
TL0.4–TL0.0. The three upper bits of TL0 (TL0.7–TL0.5) are indeterminate and should be masked out or
ignored when reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to
0x0000, the timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are
enabled.
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section
“21.3. Priority Crossbar Decoder” on page 209 for information on selecting and configuring external I/O
pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is
clocked by the system clock. When T0M is cleare d, Timer 0 is clocked by the so urce sele cted by the Clock
Scale bits in CKCON (see SFR Definition 25.1).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 12.7). Setting GATE0 to 1
allows the timer to be controlled by the external input signal INT0 (see Section “12.5. Interrupt Register
Descriptions” on page 123), facilitating pulse width measurements
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit reg ister for Timer 1 in the same ma nner as described ab ove for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal INT1 is used with Timer 1; the INT1 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 12.7).
Table 25.1. Timer 0 Running Modes
TR0 GATE0 INT0 Counter/Timer
0 X X Disabled
1 0 X Enabled
1 1 0 Disabled
1 1 1 Enabled
Note: X = Don't Care
Rev. 1.1 273
C8051F91x-C8051F90x
Figure 25.1. T0 Mode 0 Block Diagram
25.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The coun-
ter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
TCLK TL0
(5 bits ) TH0
(8 b its)
TCON
TF0
TR0
TR1
TF1
IE1
IT1
IE0
IT0
Interrupt
TR0
0
1
0
1
SYSCLK
Pre-scaled C lock
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
TMOD
T
1
M
1
T
1
M
0
C
/
T
1
G
A
T
E
1
G
A
T
E
0
C
/
T
0
T
0
M
1
T
0
M
0
GATE0
INT0
T0
Crossbar
IT01CF
I
N
1
S
L
1
I
N
1
S
L
0
I
N
1
S
L
2
I
N
1
P
L
I
N
0
P
L
I
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
IN0PL XOR
C8051F91x-C8051F90x
274 Rev. 1.1
25.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 conf igures Timer 0 and T imer 1 to oper ate as 8-bit counter/timers with automatic re load of the sta rt
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If
Timer 0 interrupts are enabled, an interr upt will occur when the TF0 flag is set. The reload value in TH0 is
not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be
correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signa l INT0
is active as defined by bit IN0PL in register IT01CF (see Section “12.6. External Interrupts INT0 and INT1”
on page 130 for details on the external input signals INT0 and INT1).
Figure 25.2. T0 Mode 2 Block Diagram
TCLK
TMOD
T
1
M
1
T
1
M
0
C
/
T
1
G
A
T
E
1
G
A
T
E
0
C
/
T
0
T
0
M
1
T
0
M
0
TCON
TF0
TR0
TR1
TF1
IE1
IT1
IE0
IT0
Interrupt
TL0
(8 bits)
Reload
TH0
(8 bits)
0
1
0
1
SYSCLK
Pre-scaled Clock
IT01CF
I
N
1
S
L
1
I
N
1
S
L
0
I
N
1
S
L
2
I
N
1
P
L
I
N
0
P
L
I
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
TR0
GATE0
IN0PL XOR
INT0
T0
Crossbar
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
Rev. 1.1 275
C8051F91x-C8051F90x
25.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The coun-
ter/timer in TL0 is controlle d using th e Timer 0 control/status bits in TCON an d TMOD : TR0, C/T0, GATE0
and TF0. TL0 can use either the system clock or an extern al inp ut signal as it s tim ebase. The TH0 r egister
is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled using the
Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls the
Timer 1 interrupt.
Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0,
1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However,
the Timer 1 overflow can be used to generate baud rates for the SMBus and/or UART, and/or initiate ADC
conversions. While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode set-
tings. To run Timer 1 while Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1,
configure it for Mode 3.
Figure 25.3. T0 Mode 3 Block Diagram
TL0
(8 bits)
TMOD
0
1
TCON
TF0
TR0
TR1
TF1
IE1
IT1
IE0
IT0
Interrupt
Interrupt
0
1
SYSCLK
Pre-scaled Clock TR1 TH0
(8 bits)
T
1
M
1
T
1
M
0
C
/
T
1
G
A
T
E
1
G
A
T
E
0
C
/
T
0
T
0
M
1
T
0
M
0
TR0
GATE0
IN0PL XOR
INT0
T0
Crossbar
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
C8051F91x-C8051F90x
276 Rev. 1.1
SFR Page = 0x0; SFR Address = 0x88; Bit-Addressable
SFR Definition 25.2. TCON: Timer Control
Bit76543210
Name TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7TF1 Timer 1 Overflow Flag.
Set to 1 by hardware whe n Timer 1 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 1 interrupt service
routine.
6TR1 Timer 1 Run Control.
Timer 1 is enabled by setting this bit to 1.
5TF0 Timer 0 Overflow Flag.
Set to 1 by hardware whe n Timer 0 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 0 interrupt service
routine.
4TR0 Timer 0 Run Control.
Timer 0 is enabled by setting this bit to 1.
3IE1 External Interru p t 1.
This flag is set by hardware when an edge/level o f type defined by IT1 is de te cted. It
can be cleared by sof twa re but i s automa tically cleared when the CPU vectors to the
External Interrupt 1 service routine in edge-triggered mode.
2IT1 Interrupt 1 Type Select.
This bit selects whether the configured INT1 interrupt will be edge or level sensitive.
INT1 is configured active low or high by the IN1PL bit in the IT01CF register (see
SFR Definition 12.7).
0: INT1 is level triggered.
1: INT1 is edge triggered.
1IE0 External Interru p t 0.
This flag is set by hardware when an edge/level o f type defined by IT1 is de te cted. It
can be cleared by sof twa re but i s automa tically cleared when the CPU vectors to the
External Interrupt 0 service routine in edge-triggered mode.
0IT0 Interrupt 0 Type Select.
This bit selects whether the configured INT0 interrupt will be edge or level sensitive.
INT0 is configured active low or high by the IN0PL bit in register IT01CF (see SFR
Definition 12.7).
0: INT0 is level triggered.
1: INT0 is edge triggered.
Rev. 1.1 277
C8051F91x-C8051F90x
SFR Page = 0x0; SFR Address = 0x89
SFR Definition 25.3. TMOD: Timer Mode
Bit76543210
Name GATE1 C/T1 T1M[1:0] GATE0 C/T0 T0M[1:0]
Type R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7GATE1 Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level.
1: Timer 1 enabled only when TR1 = 1 AND INT1 is active as defined by b it IN1PL in
register IT01CF (see SFR Definition 12.7).
6C/T1 Counter/Timer 1 Select.
0: Timer: Timer 1 incremented by clock defined by T1M bit in register CKCON.
1: Counter: Timer 1 incremented by high-to-low transitions on external pin (T1).
5:4 T1M[1:0] Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Re load
11: Mode 3, Timer 1 Inactive
3GATE0 Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND INT0 is active as defined by b it IN0PL in
register IT01CF (see SFR Definition 12.7).
2C/T0 Counter/Timer 0 Select.
0: Timer: Timer 0 incremented by clock defined by T0M bit in register CKCON.
1: Counter: Timer 0 incremented by high-to-low transitions on external pin (T0).
1:0 T0M[1:0] Timer 0 Mode Select.
These bits select the Timer 0 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Re load
11: Mode 3, Tw o 8- bit Counter/Time rs
C8051F91x-C8051F90x
278 Rev. 1.1
SFR Page = 0x0; SFR Address = 0x8A
SFR Page = 0x0; SFR Address = 0x8B
SFR Definition 25.4. TL0: Timer 0 Low Byte
Bit76543210
Name TL0[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TL0[7:0] Timer 0 Low Byte.
The TL0 register is the low byte of the 16-bit Timer 0.
SFR Definition 25.5. TL1: Timer 1 Low Byte
Bit76543210
Name TL1[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TL1[7:0] Timer 1 Low Byte.
The TL1 register is the low byte of the 16-bit Timer 1.
Rev. 1.1 279
C8051F91x-C8051F90x
SFR Page = 0x0; SFR Address = 0x8C
SFR Page = 0x0; SFR Address = 0x8D
SFR Definition 25.6. TH0: Timer 0 High Byte
Bit76543210
Name TH0[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TH0[7:0] Timer 0 High Byte.
The TH0 register is the high byte of the 16-bit Timer 0.
SFR Definition 25.7. TH1: Timer 1 High Byte
Bit76543210
Name TH1[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TH1[7:0] Timer 1 High Byte.
The TH1 register is the high byte of the 16-bit Timer 1.
C8051F91x-C8051F90x
280 Rev. 1.1
25.2. Timer 2
Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L ( low byte) and T MR2H (high byte). Timer 2 may
operate in 16-bit auto-r eload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines
the Timer 2 operation mode. Timer 2 can also be used in Capture Mode to measure the SmaRTClock or
the Comparator 0 period with respect to another oscillator. The ability to measure the Comparator 0 period
with respect to the system clock is makes using Touch Sense Switches very easy.
Timer 2 may be clocked by the system clock, the system clock divided by 1 2, SmaR TClock divided by 8, or
Comparator 0 output. Note that the SmaRTClock divided by 8 and Comparator 0 output is synchronized
with the system clock.
25.2.1. 16-bit Timer with Auto-Reload
When T2SPLIT (TMR2CN.3) is zero, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be
clocked by SYSCLK, SYSCLK divided by 12, SmaRTClock divided by 8, or Comparator 0 output. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2
reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 25.4,
and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is
set), an interrupt will be generated on each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled
and the TF2LEN bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L)
overflow fro m 0x FF to 0x00.
Figure 25.4. Timer 2 16-Bit Mode Block Diagram
SYSCLK
TMR2L TMR2H
TMR2RLL TMR2RLH Reload
TCLK
0
1
TR2
TMR2CN
T2SPLIT
TF2CEN
TF2L
TF2H
T2XCLK
TR2
Interrupt
TF2LEN
To ADC,
SMBus
To SMBus
TL2
Overflow
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
Sm aR T C lock / 8
SYSCLK / 12 00
T2XCLK[1:0]
01
11
Compara tor 0
Rev. 1.1 281
C8051F91x-C8051F90x
25.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 25.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH
holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, SmaRTClock divided by 8 or
Comparator 0 output. The T imer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bits (T2XCLK[1:0] in TMR2CN), as follows:
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H over fl o w s. I f Timer 2 interrupts ar e enab led an d TF 2LEN (TMR2CN.5 ) is set, a n in te rrupt is g ene r -
ated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and T F2L fl ags to d eterm ine the source of the Ti mer 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cleared by software.
Figure 25.5. Timer 2 8-Bit Mode Block Diagram
T2MH T2XCLK[1:0] TMR2H Clock
Source T2ML T2XCLK[1:0] TMR2L Clock
Source
0 00 SY SCLK / 12 0 00 SYSCLK / 12
0 01 SmaRTClock / 8 0 01 SmaRTClock / 8
0 10 Reserved 0 10 Reserved
0 11 C omparator 0 0 11 Comparator 0
1 X SYSCLK 1 X SYSCLK
SYSCLK
TCLK
0
1TR2
1
0
TMR2H
TMR2RLH Reload
Reload
TCLK TMR2L
TMR2RLL
Interrupt
TMR2CN
T2SPLIT
TF2CEN
TF2LEN
TF2L
TF2H
T2XCLK
TR2
To ADC,
SMBus
To SMBus
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
SmaRTClock / 8
SYSCLK / 12 00
T2XCLK[1:0]
01
11
Comparator 0
C8051F91x-C8051F90x
282 Rev. 1.1
25.2.3. Comparator 0/SmaRTClock Capture Mode
The Capture Mode in Timer 2 allows either Comparator 0 or the SmaRTClock period to be measured
against the system clock or the system clock divided by 12. Comparator 0 and the SmaR TClock period can
also be compared against each other. Timer 2 Capture Mode is enabled by setting TF2CEN to 1. Timer 2
should be in 16-bit auto-reload mode when using Capture Mode.
When Capture Mode is enabled, a capture event will be generated either every Comparator 0 rising edge
or every 8 SmaR TClock cl ock cycles, depend ing on th e T2XCLK1 setting. When the capture event occurs,
the contents of Timer 2 (TMR2H:TMR2L) are loaded into the Timer 2 reload registers
(TMR2RLH:TMR2RLL) and the TF2H flag is set (triggering an interrupt if Timer 2 interrup ts ar e enabled).
By recording the difference between two successive timer capture values, the Comparator 0 or SmaRT-
Clock period can be determined with resp ect to the T imer 2 clock. The T imer 2 clock should be much faster
than the capture clock to achieve an accurate reading.
For example, if T2ML = 1b, T2XCLK1 = 0b, and TF 2CE N = 1b, Timer 2 will clock every SYSCLK and cap -
ture every SmaRTClock clock divided by 8. If the SYSCLK is 24.5 MHz and the difference between two
successive captures is 5984, then the SmaRTClock clock is as follows:
24.5 MHz/(5984/8) = 0.032754 MHz or 32.754 kHz.
This mode allows software to determine the exact SmaRTClock frequency in self-oscillate mode and the
time between co nsecutiv e Comparator 0 rising edges, which is useful for detecting changes in the capaci-
tance of a Touch Sense Switch.
Figure 25.6. Timer 2 Capture Mode Block Diagram
SmaRT C lo ck / 8
SYSCLK
0
1
T2XCLK1
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
TMR2L TMR2H
TCLK
TR2
TMR2RLL TMR2RLH
Capture
TMR2CN
T2SPLIT
T2XCLK1
TF2CEN
TF2L
TF2H
T2XCLK0
TR2
TF2LEN
TF2CEN Interrupt
SYSCLK / 12 X0
T2XCLK[1:0]
01
11
Comparator 0
0
1
SmaRTClock / 8
Comparator 0
Rev. 1.1 283
C8051F91x-C8051F90x
SFR Page = 0x0; SFR Address = 0xC8; Bit-Addressable
SFR Definition 25.8. TMR2CN: Timer 2 Control
Bit76543210
Name TF2H TF2L TF2LEN TF2CEN T2SPLIT TR2 T2XCLK[1:0]
Type R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7TF2H Timer 2 High Byte Overflow Flag.
Set by hardware when the T imer 2 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 2 overflows from 0xFFFF to 0x000 0. When the
Timer 2 interrupt is enabled, setting this bit causes the CPU to vector to the
Timer 2 interrupt service routine. This bit is not automatically cleared by hardware.
6TF2L Timer 2 Low Byte Overflow Flag.
Set by hardware when the T imer 2 low byte overflows from 0xFF to 0x00. TF 2L will
be set when the low byte overflows regardless of the Timer 2 mode. This bit is not
automatically cleared by hardware.
5TF2LEN Timer 2 Low Byte Interrupt Enabl e.
When set to 1, this bit enables Timer 2 Low Byte interrupts. If Timer 2 interrupts
are also enabled, an interrupt will be generated when the low byte of Timer 2 over-
flows.
4TF2CEN Timer 2 Capture Enable.
When set to 1, this bit enables Timer 2 Capture Mode.
3T2SPLIT Timer 2 Split Mode Enable.
When set to 1, Timer 2 operates as two 8-bit timers with auto-reload. Otherwise,
Timer 2 operates in 16-bit auto-reload mode.
2TR2 Timer 2 Run Control.
Timer 2 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR2H only; TMR2L is always enabled in split mode.
1:0 T2XCLK[1:0] Timer 2 Exter nal Clock Select.
This bit selects the “external” and “capture trigger” clock sources for Timer 2. If
Timer 2 is in 8-bit mode, this bit selects the “external” clock source for both timer
bytes. T imer 2 Clock Select bits (T2MH and T2ML in register CKCON) may still be
used to select between the “external” clock and the system clock for either timer.
Note: External clock sources are synchronized with the system clock.
00: External Clock is SYSCLK/12. Capture trigger is SmaRTClock/8.
01: External Clock is Comparator 0. Capture trigger is SmaRTClock/8.
10: External Clock is SYSCLK/12. Capture trigger is Comparator 0.
11: External Clock is SmaRTClock/8. Capture trigger is Comparator 0.
C8051F91x-C8051F90x
284 Rev. 1.1
SFR Page = 0x0; SFR Address = 0xCA
SFR Page = 0x0; SFR Address = 0xCB
SFR Definition 25.9. TMR2RLL: Timer 2 Reload Register Low Byte
Bit76543210
Name TMR2RLL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2RLL[7:0] Timer 2 Reload Register Low Byte.
TMR2RLL holds the low byte of the reload value for Timer 2.
SFR Definition 25.10. TMR2RLH: Timer 2 Reload Register High Byte
Bit76543210
Name TMR2RLH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2RLH[7:0] Timer 2 Reload Register High Byte.
TMR2RLH holds the high byte of the reload value for Timer 2.
Rev. 1.1 285
C8051F91x-C8051F90x
SFR Page = 0x0; SFR Address = 0xCC
SFR Page = 0x0; SFR Address = 0xCD
SFR Definition 25.11. TMR2L: Timer 2 Low Byte
Bit76543210
Name TMR2L[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2L[7:0] Timer 2 Low Byte.
In 16-bit mode, the TMR2L register contains the low byte of the 16-bit Timer 2. In 8-
bit mode, TMR2L contains the 8-bit low byte timer value.
SFR Definition 25.12. TMR2H Timer 2 High Byte
Bit76543210
Name TMR2H[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2H[7:0] Timer 2 Low Byte.
In 16-bit mode, the TM R 2H re gis te r con tains the hig h by te of the 16-bit Timer 2. In 8-
bit mode, TMR2H contains the 8-bit high byte timer value.
C8051F91x-C8051F90x
286 Rev. 1.1
25.3. Timer 3
Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L ( low byte) and T MR3H (high byte). Timer 3 may
operate in 16-bit auto-r eload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR2CN.3) defines
the Timer 3 operation mode. Timer 3 can also be used in Capture Mode to measure the external oscillator
source or the Comparator 1 period with respect to another oscillator. The ability to measure the
Comparator 1 period with respect to the system clock is m akes using Touch Sense Switches very easy.
Timer 3 may be clocked by the system clock, the system clock divided by 12, external oscillator source
divided by 8, or Comparator 1 output. The external oscillator source divided by 8 and Comparator 1 output
is synchronized with the system clock.
25.3.1. 16-bit Timer with Auto-Reload
When T3SPLIT (TMR3CN.3) is zero, Timer 3 operates as a 16-bit timer with auto-reload. Timer 3 can be
clocked by SYSCLK, SYSCLK divided by 12, external oscillator clock source divided by 8, or Comparator 1
output. As the 16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in
the Timer 3 reload registers (TMR3RLH and TMR3RLL) is loaded into the Timer 3 register as shown in
Figure 25.7, and the Timer 3 High Byte Overflow Flag (TMR3CN.7) is set. If T ime r 3 interru pts are enabled
(if EIE1.7 is set), an interrupt will be generated on each Time r 3 overflow. Additionally, if Timer 3 interrupts
are enabled and the TF3LEN bit is set (TMR3CN.5), an interrupt will be generated each time the lower 8
bits (TMR3L) overflow from 0xFF to 0x00.
Figure 25.7. Timer 3 16-Bit Mode Block Diagram
SYSCLK
TMR3L TMR3H
TMR3RLL TMR3RLH Reload
TCLK
0
1
TR3
TMR3CN
T3SPLIT
T3XCLK1
TF3CEN
TF3L
TF3H
T3XCLK0
TR3
Interrupt
TF3LEN
To ADC
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
External Clock / 8
SYSCLK / 12 00
T3XCLK[1:0]
01
11
Comparator 1
Rev. 1.1 287
C8051F91x-C8051F90x
25.3.2. 8-bit Timers with Auto-Reload
When T3SPLIT is s et, Time r 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 25.8. TMR3RLL holds the reload value for TMR3L; TMR3RLH
holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, the external oscillator clock
source divided by 8, or Comparator 1. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON) select
either SYSCLK or the clock defined by the Timer 3 External Clock Select bits (T3XCLK[1:0] in TMR3CN),
as follows:
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows
from 0xFF to 0x00. When Timer 3 interrupt s are enabled, an inter rupt is generated e ach time TMR3H over-
flows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and
TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not
cleared by hardware and must be manually cleared by software.
Figure 25.8. Timer 3 8-Bit Mode Block Diagram.
T3MH T3XCLK[1:0] TMR3H Clock
Source T3ML T3XCLK[1:0] TMR3L Clock
Source
0 00 SY SCLK / 12 0 00 SYSCLK / 12
0 01 Comparator 1 0 01 Comparator 1
0 10 Reserved 0 10 Reserved
0 11 External Clock / 8 0 11 External Clock / 8
1 X SYSCLK 1 X SYSCLK
SYSCLK
TCLK
0
1TR3
1
0
TMR3H
TMR3RLH Reload
Reload
TCLK TMR3L
TMR3RLL
Interrupt
TMR3CN
T3SPLIT
T3XCLK1
TF3CEN
TF3LEN
TF3L
TF3H
T3XCLK0
TR3
To ADC
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
External Clock / 8
SYSCLK / 12 00
T3XCLK[1:0]
01
11
Comparator 1
C8051F91x-C8051F90x
288 Rev. 1.1
25.3.3. Comparator 1/External Oscillator Capture Mode
The Captur e Mode in Timer 3 allows either Co mparator 1 or the external oscillator period to be measured
against the system clock or the system clock divided by 12. Comparator 1 and the external oscillator
period can also be compared against each oth er.
Setting TF3CEN to 1 enables the Comparator 1/External Oscillator Capture Mode for Timer 3. In this
mode, T3SPLIT should be se t to 0, as the full 16-bit timer is used.
When Capture Mode is enabled, a capture event will be generated either every Comparator 1 rising edge
or every 8 external clock cycles, depending on the T3XCLK1 setting. When the capture event occurs, the
contents of Timer 3 (TMR3H:TMR3L) are loaded into the Timer 3 reload registers (TMR3RLH:TMR3RLL)
and the TF3H flag is set (triggering an interrupt if Timer 3 interrupts are en abled). By record ing the differ-
ence between two successive timer capture values, the Comparator 1 or external clock period can be
determined with respect to the Timer 3 clock. The Timer 3 clock should be much faster than the capture
clock to achieve an accurate reading.
For example, if T3ML = 1b, T3XCLK1 = 0b, and TF 3CE N = 1b, Timer 3 will clock every SYSCLK and cap -
ture every Comparator 1 rising edge. If SYSCLK is 24.5 MHz and the difference between two successive
captures is 350 counts, then the Comparator 1 period is:
350 x (1 / 24.5 MHz) = 14.2 µs.
This mode allows software to determine the exact frequency of the external oscillator in C and RC mode or
the time between consecutive Comparator 0 rising edges, which is useful for detecting changes in the
capacitance of a Touch Sense Switch.
Figure 25.9. Timer 3 Capture Mode Block Diagram
External Clock / 8
SYSCLK
0
1
T3XCLK1
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
TMR3L TMR3H
TCLK
TR3
TMR3RLL TMR3RLH
Capture
TMR3CN
T3SPLIT
T3XCLK1
TF3CEN
TF3L
TF3H
T3XCLK0
TR3
TF3LEN
TF3CEN Interrupt
SYSCLK / 12 X0
T3XCLK[1:0]
01
11
Com parator 1
0
1
Com parator 1
External Clock / 8
Rev. 1.1 289
C8051F91x-C8051F90x
SFR Page = 0x0; SFR Address = 0x91
SFR Definition 25.13. TMR3CN: Timer 3 Control
Bit76543210
Name TF3H TF3L TF3LEN TF3CEN T3SPLIT TR3 T3XCLK[1:0]
Type R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7TF3H Timer 3 High Byte Overflow Flag.
Set by hardware when the Timer 3 high byte overflows from 0x FF to 0x00. In 16 bit
mode, this will occur when Timer 3 overflows from 0xFFFF to 0x0000. When the
Timer 3 interrupt is enable d, setting this bit causes the CPU to vector to the Timer 3
interrupt service routine. This bit is not automatically cleared by hardware.
6TF3L Timer 3 Low Byte Overflow Flag.
Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. TF3L will
be set when the low byte overflows regardless of the Timer 3 mode. This bit is not
automatically cleared by hardware.
5TF3LEN Timer 3 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 3 Low Byte interrupts. If Timer 3 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 3 overflows.
4TF3CEN Timer 3 Comparator 1/External Oscillator Capture Enable.
When set to 1, this bit enables Timer 3 Capture Mode.
3T3SPLIT Timer 3 Split Mode Enable.
When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload.
0: Timer 3 operates in 16-bit auto-reload mode.
1: Timer 3 operates as two 8-bit auto-reload timers.
2TR3 Timer 3 Run Control.
Timer 3 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR3H only; TMR3L is always enabled in split mode.
1:0 T3XCLK[1:0] Timer 3 External Clock Select.
This bit select s the “external” and “capture trigger” clock sources for Timer 3. If
Timer 3 is in 8-bit mode, this bit selects the “external” clock source for both timer
bytes. Timer 3 Clock Select bits (T3MH and T3ML in register CKCON) may still be
used to select between the “external” clock and the syst em clock for either timer.
Note: External clock sources are synchronized with the system clock.
00: External Clock is SYSCLK /12. Capture trigger is Comparator 1.
01: External Clock is External Oscillator/8. Capture trigger is Comparator 1.
10: External Clock is SYSCLK/12. Capture trigger is External Oscillator/8.
11: External Clock is Comparator 1. Capture trigger is External Oscillator/8.
C8051F91x-C8051F90x
290 Rev. 1.1
SFR Page = 0x0; SFR Address = 0x92
SFR Page = 0x0; SFR Address = 0x93
SFR Definition 25.14. TMR3RLL: Timer 3 Reload Register Low Byte
Bit76543210
Name TMR3RLL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3RLL[7:0] Timer 3 Reload Register Low Byte.
TMR3RLL holds the low byte of the reload value for Timer 3.
SFR Definition 25.15. TMR3RLH: Timer 3 Reload Register High Byte
Bit76543210
Name TMR3RLH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3RLH[7:0] Timer 3 Reload Register High Byte.
TMR3RLH holds the high byte of the reload value for Timer 3.
Rev. 1.1 291
C8051F91x-C8051F90x
SFR Page = 0x0; SFR Address = 0x94
SFR Page = 0x0; SFR Address = 0x95
SFR Definition 25.16. TMR3L: Timer 3 Low Byte
Bit76543210
Name TMR3L[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3L[7:0] Timer 3 Low Byte.
In 16-bit mode, the TMR3L register contains the low byte of the 16-bit Timer 3. In
8-bit mode, TMR3L contains the 8-bit low byte timer value.
SFR Definition 25.17. TMR3H Timer 3 High Byte
Bit76543210
Name TMR3H[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3H[7:0] Timer 3 High Byte.
In 16-bit mode, the TMR3H register contains the high byte of the 16-bit Timer 3. In
8-bit mode, TMR3H contains the 8-bit high byte timer value.
C8051F91x-C8051F90x
292 Rev. 1.1
26. Programmable Counter Array
The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU
intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer
and six 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the Crossbar to Port I/O when enabled. The counter/timer is driven by a
programmable timebase that can select between seven sources: system clock, system clock divided by
four, system clock divided by twelve, the external oscillator clock source divided by 8, SmaRTClock divided
by 8 ('F912 and 'F902 devices only), Timer 0 overflows, or an external clock signal on the ECI input pin.
Each capture/compare module may be configured to operate independently in one of six modes: Edge-
Triggered Capture, Software Timer, High-Speed Output, Frequency Output, 8 to 11-Bit PWM, or 16-Bit
PWM (each mode is described in Section “26.3. Capture/Compare Modules” on page 296). The external
oscillator clock option is ideal for real-time clock (RTC) functionality, allowing the PCA to be clocked by a
precision external oscillator while the internal oscillator drives the system clock. The PCA is configured and
controlled through the system controller's Special Function Registers. Th e P CA bloc k di agr am is show n in
Figure 26.1.
Import ant Note: The PCA Module 5 may be used as a watchdog timer (WDT), and is enabled in this mod e
following a system reset. Access to certain PCA registers is restricted while WDT mode is enabled.
See Section 26.4 for details.
Figure 26.1. PCA Block Diagram
Capture/Com pare
Module 1
Capture/Com pare
Module 0 C apture/Com pare
Modu le 2
CEX1
ECI
Crossbar
CEX2
CEX0
P o rt I/O
16 -B it C o u n ter /Timer
PCA
CLOCK
MUX
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
Capture/Com pare
Module 4
Capture/Com pare
Mo dule 3 Capture/C ompare
Module 5 / WDT
CEX4
CEX5
CEX3
SmaRTClock/8*
*Only available on ‘F91 2 and ‘F902 devices.
Rev. 1.1 293
C8051F91x-C8051F90x
26.1. PCA Counter/T imer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches
the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.
Reading the PCA0L Regist er first guaran tees an a ccurate r eading of the entire 16 -bit PCA0 cou nter.
Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2–CPS0 bits in the PCA0MD
register select the timebase for the counter/timer as shown in Table 26.1.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is
set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by
software. Cle aring th e CIDL b it in the PCA0MD r egister allows the PCA to co ntinu e norm al op eration while
the CPU is in Idle mode.
Table 26.1. PCA Timebase Input Options
CPS2 CPS1 CPS0 Timebase
0 0 0 System clock divided by 12
0 0 1 System clock divided by 4
0 1 0 Timer 0 over flo w
011
High-to-low transitions on ECI (max rate = system clock divided
by 4)
100System clock
101
External oscillator source divided by 81
110
SmaRTClock oscillator source divided by 82
111Reserved
Notes:
1. External oscillator source divid ed by 8 is synchronized with the system clock.
2. SmaRTClock oscillator source divided by 8 is synchronized with the system clock and is only
available on 'F912 and 'F902 devices. This setting is reserved on all other devices.
C8051F91x-C8051F90x
294 Rev. 1.1
Figure 26.2. PCA Counter/Timer Block Diagram
26.2. PCA0 Interrupt Sources
Figure 26.3 shows a diagram of the PCA interrupt tree. There are eight independent event flags that can
be used to generate a PCA0 interrupt. They are: the main PCA counter overflow flag (CF), which is set
upon a 16-bit overflow of the PCA0 counter, an intermediate overflow flag (COVF), wh ich can be set on an
overflow from the 8th, 9th, 10th, or 11th bit of the PCA0 counter, and the individual flags for each PCA
channel (CCF0, CCF1, CCF2, CCF3, CCF4, and CCF5), which ar e set according to the operatio n mode of
that module. These event flags are always set when the trigger condition occurs. Each of these flags can
be individually selected to generate a PCA0 interrupt, using the corresponding interrupt enable flag (ECF
for CF, ECOV for COVF, and ECCFn for each CCFn). PCA0 interrupts must be glob ally enabled before a ny
individual interrupt sources are recognized by the processor. PCA0 interrupts are globally enabled by
setting the EA bit and the EPCA0 bit to logic 1.
PCA0CN
C
FC
RC
C
F
0
C
C
F
2
C
C
F
1
C
C
F
5
C
C
F
4
C
C
F
3
PCA0MD
C
I
D
L
W
D
T
E
E
C
F
C
P
S
1
C
P
S
0
W
D
L
C
K
C
P
S
2
IDLE
0
1PCA0H PCA0L
Snapshot
Register
To SFR Bus
Overflow To PCA Interrupt System
CF
PCA0L
read
To PCA Modules
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
000
001
010
011
100
101
SYSCLK
External Clock/8
110
SmaRTClock/8*
*Only available on ‘F912 and ‘F902 devices.
Rev. 1.1 295
C8051F91x-C8051F90x
Figure 26.3. PCA Interrupt Block Diagram
PCA0CN
C
FC
RC
C
F
0
C
C
F
2
C
C
F
1
C
C
F
5
C
C
F
4
C
C
F
3
PCA0MD
C
I
D
L
W
D
T
E
E
C
F
C
P
S
1
C
P
S
0
W
D
L
C
K
C
P
S
2
0
1
PCA Module 0
(CCF0)
PCA Module 1
(CCF1)
ECCF1
0
1
ECCF0
0
1
PCA Module 2
(CCF2)
ECCF2
PCA Counter/Timer 16-
bit Overflow 0
1
Interrupt
Priority
Decoder
EPCA0
0
1
EA
0
1
PCA0CPMn
(for n = 0 to 5)
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
PCA0PWM
A
R
S
E
L
C
O
V
F
C
L
S
E
L
0
C
L
S
E
L
1
E
C
O
V
PCA Counter/Timer 8, 9,
10 or 11-bit Overflow
0
1
Set 8, 9, 10 , or 1 1 bit Operation
0
1
PCA Module 3
(CCF3)
PCA Module 4
(CCF4)
ECCF4
0
1
PCA Module 5
(CCF5)
ECCF5
ECCF3 0
1
C8051F91x-C8051F90x
296 Rev. 1.1
26.3. Capture/Compare Modules
Each module can be configured to operate independently in one of six operation modes: edge-triggered
capture, software timer, high speed output, frequency output, 8 to 11-bit pulse width modulator, or 16-bit
pulse width modulator. Ea ch m odule h as sp ecial fu nctio n regis ters ( SFR s) as sociated with it in th e CIP- 51
system controller. These registers are used to exchange data with a module and configure the module's
mode of operation. Table 26.2 summarizes the bit settings in the PCA0CPMn and PCA0PWM registers
used to sele ct the PCA captur e/compare module’s operating mode. Note that all modules set to use 8, 9,
10, or 11-bit PWM mode must use the same cycle length (8-11 bits). Setting the ECCFn bit in a
PCA0CPMn register enables the module's CCFn interrupt.
Table 26.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules
Operational Mode PCA0CPMn PCA0PWM
Bit Number76543210765 4-2 1–0
Capture triggered by positive edge on CEXn XX10000A0XBXXXXX
Capture triggered by negative edge on CEXn XX01000A0XBXXXXX
Capture triggered by any transition on CEXn XX11000A0XBXXXXX
Software Timer XC00100A0XBXXXXX
High-Speed Output XC00110A0XBXXXXX
Frequency Output XC00011A0XBXXXXX
8-Bit Pulse Width Mod ulator (Note 7) 0 C 0 0 E 0 1 A 0 X B XXX 00
9-Bit Pulse Width Mod ulator (Note 7) 0 C 0 0 E 0 1 A D X B XXX 01
10-Bit Pulse Width Modulator (Note 7) 0 C 0 0 E 0 1 A D X B XXX 10
11-Bit Pulse Width Modulator (Note 7) 0 C 0 0 E 0 1 A D X B XXX 11
16-Bit Pulse Width Modulator 1 C 0 0 E 0 1 A 0 X B XXX XX
Notes:
1. X = Don’t Care (no functional difference for individual module if 1 or 0).
2. A = Enable interrupts for this module (PCA interrupt triggered on CCFn set to 1).
3. B = Enable 8th, 9th, 10th or 11th bit overflow interrupt (Depends on setting of CLSEL[1:0]).
4. C = When set to 0, the digital comparator is off. For high speed and frequency output modes, the
associated pin will not toggle. In any of the PWM modes, this generates a 0% duty cycle (output = 0).
5. D = Selects whether the Capture/Compare register (0) or the Auto-Reload register (1) for the associated
channel is accessed via addresses PCA0CPHn and PCA0CPLn.
6. E = When set, a match event will cause the CCFn flag for the associated chan nel to be set.
7. All modules set to 8, 9, 10 or 11-bit PWM mode use the same cycle length setting.
Rev. 1.1 297
C8051F91x-C8051F90x
26.3.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA
counter/timer and load it in to the corr esponding mo dule 's 16- bit ca pture/co mpare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of
transition that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative
edge), or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag
(CCFn) in PCA0CN is set to logic 1. An interrupt request is g enerated if the CCFn interrupt fo r that module
is enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt
service routine, and must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then
the state of the Port pin associated with CEXn can be read dire ctly to determine whether a rising-edge or
falling-edge caused the capture.
Figure 26.4. PCA Capture Mode Diagram
Note: The CEXn input signal must remai n high or low for at least 2 system clock cycles to be recognized by the
hardware.
PCA0L
PCA0CPLn
PCA
Timebase
CEXn
CrossbarPort I/O
PCA0H
Capture
PCA0CPHn
0
1
0
1
(to CCFn)
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
PCA0CN
C
FC
RC
C
F
0
C
C
F
2
C
C
F
1
PCA Interrupt
x000xx
C8051F91x-C8051F90x
298 Rev. 1.1
26.3.2. Software Timer (Compare) Mode
In Softwa re Timer mode, the PCA counter/timer value is compared to the module's 16- bit ca pture/ co mpare
register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in
PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt
service routine, and must be cleared by software. Setting the ECOMn and MATn bits in the PCA0CPMn
register enables Software Timer mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0
Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Figure 26.5. PCA Software Timer Mode Diagram
Match
16-bit Comparator
PCA0H
PCA0CPHn
Enable
PCA0L
PCA
Timebase
PCA0CPLn
00 00
0
1
x
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
x
PCA0CN
C
FC
RC
C
F
0
C
C
F
2
C
C
F
1
PCA Interrupt
Rev. 1.1 299
C8051F91x-C8051F90x
26.3.3. High-Speed Output Mode
In High-speed output mode, a module’s associated CEXn pin is toggled each time a match occurs
between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and
PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An
interrupt request is generated if the CCFn interrupt for that module is enabled. The CCFn bit is not
automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be
cleared by software. Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the
High-Speed Output mode. If ECOMn is cleared, the associated pin will retain its state, and not toggle on
the next match ev ent.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0
Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Figure 26.6. PCA High-Speed Output Mode Diagram
Match
16-bit Comparator
PCA0H
PCA0CPHn
Enable
PCA0L
PCA
Timebase
PCA0CPLn
0
1
00 0x
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
x
CEXn Crossbar Port I/O
Toggle 0
1
TOGn
PCA0CN
C
FC
RC
C
F
0
C
C
F
2
C
C
F
1
PCA Interrupt
C8051F91x-C8051F90x
300 Rev. 1.1
26.3.4. Frequency Output Mode
Frequency Output Mode produces a programmable-frequency square wave on the module’s associated
CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the
output is toggled. The frequency of the square wave is then defined by Equation 26.1.
Equation 26.1. Square Wave Frequency Output
Where FPCA is the frequency of the clock selected by the CPS2–0 bits in the PCA mode register,
PCA0MD. The lower byte of the capture/compare module is compared to the PCA counter low byte; on a
match, CEXn is toggled and the offset held in the high byte is added to the matche d value in PCA0CPLn .
Frequency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn
register. Note that the MATn bit should normally be set to 0 in this mode. If the MATn bit is set to 1, the
CCFn flag for the channel will be set when the 16-bit PCA0 counter and the 16-bit capture/compare
register for the channel are equal.
Figure 26.7. PCA Frequency Output Mode
FCEXn FPCA
2PCA0CPHn
-----------------------------------------
=
Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation.
8-bit
Comparator
PCA0L
Enable
PCA Timebase
match
PCA0CPHn8-bit AdderPCA0CPLn
Adder
Enable
CEXn Crossbar Port I/O
Toggle 0
1
TOGn
000 x
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
x
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
Rev. 1.1 301
C8051F91x-C8051F90x
26.3.5. 8-Bit, 9-Bit, 10-Bit and 11-Bit Pulse Width Modulator Modes
Each module can be used independently to generate a pulse width modulated (PWM) output on its
associated CEXn pin. The freq uency of the output is dependent on the timebase for the PCA counter/timer,
and the setting of the PWM cycle length (8, 9, 10 or 11-bits). For backwards-compatibility with the 8-bit
PWM mode availa ble on o ther devices, the 8-bit PWM mode operates slightly different than 9, 10 and 11-
bit PWM modes. It is important to note that all channels configured for 8/9/10/11-bit PWM mode will
use the same cycle length. It is not possible to configure one channel for 8-bit PWM mode and another
for 11-bit mode (for example). However, other PCA channels can be configured to Pin Capture, High-
Speed Output, Software Timer, Frequency Output, or 16-bit PWM mode independently.
26.3.5.1. 8-Bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn
capture/comp are register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to th e
value in PCA0CPLn, the output on th e CEXn pin will be set. When the count value in PCA0L overflows, the
CEXn output will be reset (see Figure 26.8). Also, when the counter/timer low byte (PCA0L) overflows from
0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the module’s capture/compare
high byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the
PCA0CPMn register, and setting the CLSEL bits in register PCA0PWM to 00b enables 8-Bit Pulse Width
Modulator mode. If the MATn bit is set to 1, the CCFn flag for the module will be set each time an 8-bit
comparator match (r ising edge) occurs. The COVF flag in PCA0PWM can be used to dete ct the overflow
(falling edge), which will occur every 256 PCA clock cycles. The duty cycle for 8-Bit PWM Mode is given in
Equation 26.2.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0
Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Equation 26.2. 8-Bit PWM Duty Cycle
Using Equation 26.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is
0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Figure 26.8. PCA 8-Bit PWM Mode Diagram
Duty Cycle 256 PCA0CPHn–
256
---------------------------------------------------
=
8-bit
Comparator
PCA0L
PCA0CPLn
PCA0CPHn
CEXn Crossbar Port I/O
Enable
Overflow
PCA Timebase
00x0 x
Q
Q
SET
CLR
S
R
match
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
0
PCA0PWM
A
R
S
E
L
C
L
S
E
L
0
C
L
S
E
L
1
E
C
O
V
x000
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
COVF
C
O
V
F
C8051F91x-C8051F90x
302 Rev. 1.1
26.3.5.2. 9/10/11-bit Pulse Width Mod ulator Mode
The duty cycle of the PWM output signal in 9/10/11-bit PWM mode should be varied by writin g to an “Auto-
Reload” Register, which is dual-mapped into the PCA0CPHn and PCA0CPLn register locations. The data
written to define the duty cycle should be right-justified in the registers. The auto-reload registers are
accessed (read or written) when the bit ARSEL in PCA0PWM is set to 1. The capture/compare registers
are accessed when ARSEL is set to 0.
When the least-significant N bits of the PCA0 counter match the value in the associated module’s
capture/compare register (PCA0CPn), the output on CEXn is asserted high. When the counter overflows
from the Nth bit, CEXn is asserted low (see Figure 26.9). Upon an overflow from the Nth bit, the COVF flag
is set, and the value stored in the module’s auto-reload register is loaded into the capture/compare
register. The value of N is determined by the CLSE L bits in register PC A0PW M .
The 9, 10 or 11-bit PWM mode is selected by setting the ECOMn and PWMn bits in the PCA0CPMn
register, and setting the CLSEL bits in register PCA0PWM to the desired cycle length (other than 8-bits). If
the MATn bit is set to 1, the CCFn flag for the module will be set each time a comparator match (rising
edge) occurs. The COVF flag in PCA0PWM can be used to detect the overflow (falling edge), which will
occur every 512 (9-bit), 1024 (10-bit) or 2048 (11-bit) PCA clock cycles. The duty cycle for 9/10/11-Bit
PWM Mode is given in Equation 26.2, where N is the number of bits in the PWM cycle.
Important Note About PCA0CPHn and PCA0CPLn Registers: When writing a 16-bit value to the
PCA0CPn registers, the low byte should always be written first. Wr iting to PCA0CPLn clears the ECOMn
bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Equation 26.3. 9, 10, and 11-Bit PWM Duty Cycle
A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Figure 26.9. PCA 9, 10 and 11-Bit PWM Mode Diagram
Duty Cycle 2NPCA0CPn–
2N
--------------------------------------------
=
N-bit Comparator
PCA0H:L
(Capture/Compare)
PCA0CPH:Ln
(right-justified)
(Auto-Reload)
PCA0CPH:Ln
(right-justified)
CEXn Crossbar Port I/O
Enable
Overflow of Nth Bit
PCA Timebase
00x0 x
Q
Q
SET
CLR
S
R
match
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
0
PCA0PWM
A
R
S
E
L
C
L
S
E
L
0
C
L
S
E
L
1
E
C
O
V
x
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset R/W when
ARSEL = 1
R/W when
ARSEL = 0 Set “N” bits:
01 = 9 bits
10 = 10 bits
11 = 11 bits
C
O
V
F
Rev. 1.1 303
C8051F91x-C8051F90x
26.3.6. 16-Bit Pulse Width Modulator Mode
A PCA module may also be operated in 16-Bit PWM mode. 16-bit PWM mode is independent of the other
(8/9/10/11-bit) PWM modes. In this mode, the 16-bit capture/compare module defines the number of PCA
clocks for the low time of the PWM signal. When the PCA counter matches the module contents, the
output on CEXn is asserted high; when the 16-bit counter overflows, CEXn is asserted low. To output a
varying duty cycle, new value writes should be synchronized with PCA CCFn match interrupts. 16-Bit
PWM Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn register. For a
varying duty cycle, match interrupts should be enabled (ECCFn = 1 AND MATn = 1) to help synchronize
the capture/compare register writes. If the MATn bit is set to 1, the CCFn flag for the module will be set
each time a 16-bit comparator match (rising edge) occurs. The CF flag in PCA0CN can be used to detect
the overflow (falling edge). The duty cycle for 16-B it PWM Mode is given by Equation 26.4.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0
Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Equation 26.4. 16-Bit PWM Duty Cycle
Using Equation 26.4, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bi t to 0.
Figure 26.10. PCA 16-Bit PWM Mode
Duty Cycle 65536 PCA0CPn–
65536
-----------------------------------------------------
=
PCA0CPLnPCA0CPHn
Enable
PCA Timebase
00x0 x
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
1
16-bit Com parator CEXn Crossbar Port I/O
Overflow
Q
Q
SET
CLR
S
R
match
PCA0H PCA0L
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
C8051F91x-C8051F90x
304 Rev. 1.1
26.4. Watchdog Timer Mode
A programmable wa tchdog timer (WDT) function is avail able throu gh the PCA Module 5. The WDT is used
to generate a reset if the time between writes to the WDT up date register (PCA0CPH2 ) exceed a specified
limit. The WDT can be configured and en abled/disabled as needed by software.
With the WDTE bit set in the PCA0MD register, Module 5 operates as a watchdog timer (WDT). The
Module 5 high byte is comp ared to the PCA counter high byte; the Module 5 lo w byte h old s the offset to be
used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some
PCA registers are restricted while the Watchdog Timer is enabled. The WDT will generate a reset
shortly after code begins execution. To avoid this reset, the WDT should be explicitly disabled (and
optionally re-configured and re-enabled if it is used in the system).
26.4.1. Watchdog Timer Operation
While the WDT is enabled:
• PCA counter is forced on.
• Writes to PCA0L and PCA0H are not allowed.
• PCA clock source bits (CPS2–CPS0) are frozen.
• PCA Idle control bit (CIDL) is frozen.
• Module 5 is forced into software timer mode.
• Writes to the Module 5 mode register (PCA0CPM5) are disabled.
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control bit (CR) will read zero if the WDT is enabled but
user software has not enabled the PCA counter. If a match occurs between PCA0CPH5 and PCA0H while
the WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a
write of any value to PCA0CPH5. Upon a PCA0CPH5 write, PCA0H plus the offset held in PCA0CPL5 is
loaded into PCA0CPH5 (See Figure 26.11).
Figure 26.11. PCA Module 5 with Watchdog Timer Enabled
PCA0H
Enable
PC A0 L O verflow
Reset
PCA0CPL5 8-bit A dder
PCA0CPH5
Adder
Enable
PCA0MD
C
I
D
L
W
D
T
E
E
C
F
C
P
S
1
C
P
S
0
W
D
L
C
K
C
P
S
2
Match
Write to
PCA0CPH2
8-bit
Comparator
Rev. 1.1 305
C8051F91x-C8051F90x
The 8-bit offset held in PCA0CPH5 is compared to the upper byte of the 16-bit PCA counter. This offset
value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the first
PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The total
offset is then given (in PCA cloc ks) by Equation 26.5, where PCA0L is the value of the PCA0L register at
the time of the update.
Equation 26.5. Watchdog Timer Offset in PCA Clocks
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH5 and
PCA0H. Software may force a WDT reset by writing a 1 to the CCF5 flag (PCA0CN.5) while the WDT is
enabled.
26.4.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
• Disable the WDT by writing a 0 to the WDTE bit.
• Select the desired PCA clock source (with the CPS2–CPS0 bits).
• Load PCA0CPL5 with the desired WDT update offset value.
• Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle
mode).
• Enable the WDT by setting the WDTE bit to 1.
• Reset the WDT timer by writing to PCA0CPH5.
The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLC K is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL5 defaults to 0x00. Using Equation 26.5, this results in a WDT
timeout interval of 256 PCA clock cycles, or 3072 system clock cycles. Table 26.3 lists some example
timeout intervals for typical system clocks.
Table 26.3. Watchdog Timer Timeout Intervals
System Clock (Hz) PCA0CPL5 Timeout Interval (ms)
24,500,000 255 32.1
24,500,000 128 16.2
24,500,000 32 4.1
3,062,500*255 257
3,062,500*128 129.5
3,062,500*32 33.1
32,000 255 24576
32,000 128 12384
32,000 32 3168
*Note: Internal SYSCLK reset frequency = Internal Oscillator divided by 8.
Offset 256 PCA0CPL5256 PCA0L–+=
C8051F91x-C8051F90x
306 Rev. 1.1
26.5. Register Descriptions for PCA0
Following are detailed descriptions of the special function registers related to the operation of the PCA.
SFR Page = 0x0; SFR Address = 0xD8; Bit-Addressable
SFR Definition 26.1. PCA0CN: PCA Control
Bit76543210
Name CF CR CCF5 CCF4 CCF3 CCF2 CCF1 CCF0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7CF PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000.
When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the
CPU to vector to th e PCA inte rrupt service r outin e. This b it is not au toma tically cleared
by hardware and must be cleared by software.
6CR PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
5:0 CCF[5:0] PCA Module n Capture/Compare Flag.
These bits are set by hardware when a match or capture occurs in the associated PCA
Module n. When the CCFn interrupt is enabled, setting this bit causes the CPU to
vector to the PCA interrupt service routine. This bit is not automatically cleared by
hardware and must be cleared by software.
Rev. 1.1 307
C8051F91x-C8051F90x
SFR Page = 0x0; SFR Address = 0xD9
SFR Definition 26.2. PCA0MD: PCA Mode
Bit76543210
Name CIDL WDTE WDLCK CPS2 CPS1 CPS0 ECF
Type R/W R/W R/W RR/W R/W R/W R/W
Reset 01000000
Bit Name Function
7CIDL PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
6WDTE Watchdog Timer Enable.
If this bit is set, PCA Module 2 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA Module 2 enabled as Watchdog Timer.
5WDLCK Watchdog Ti mer Lock.
This bit locks/unlocks the Watchdog T imer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
4Unused Read = 0b, Write = don't care.
3:1 CPS[2:0] PCA Counter/Timer Pulse Select.
These bits select the timebase source for the PCA counter
000: System clock divided by 12
001: System clock divided by 4
010: Timer 0 overflow
011: High-to-low transitions on ECI (max rate = system clock divided by 4)
100: System clock
101: External clock divided by 8 (synchronized with the system clock)
110: SmaRTClock divided by 8 (synchronized with the system clock and only avail-
able on ‘F912 and ‘F902 devices -- this setting is reserved on all other devices)
111: Reserved
0ECF PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is
set.
Note: When the WDTE bit is set to 1, the other bits in the PCA0MD register cannot be modified. To change the
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
C8051F91x-C8051F90x
308 Rev. 1.1
SFR Page = 0x0; SFR Address = 0xDF
SFR Definition 26.3. PCA0PWM: PCA PWM Configuration
Bit76543210
Name ARSEL ECOV COVF CLSEL[1:0]
Type R/W R/W R/W RRR R/W
Reset 00000000
Bit Name Function
7ARSEL Auto-Reload Register Select.
This bit selects whethe r to re ad an d writ e the norm a l PCA ca ptu r e/c om pare re gist er s
(PCA0CPn), or the Auto-Reload registers at the same SFR addresses. This function
is used to define the reload value for 9, 10, and 11-bit PWM modes. In all other
modes, the Aut o- Re loa d re gisters have no function.
0: Read/Write Capture/Compare Registers at PCA0CPHn and PCA0CPLn.
1: Read/Write Auto-Reload Registers at PCA0CPHn and PCA0CPLn.
6ECOV Cycle Overflow Interrupt Enable.
This bit sets the masking of the Cycle Overflow Flag (COVF) interrupt.
0: COVF will not generate PCA interrupts.
1: A PCA interrupt will be generated when COVF is set.
5COVF Cycle Overflow Flag.
This bit indicates an overflow of the 8th, 9th , 10th, or 11th bit of the main PCA counter
(PCA0). The specific bit used for this flag depends on the setting of the Cycle Length
Select bits. The bit can be set by hardware or software, but must be cleared by soft-
ware.
0: No overflow has occurred since the last time this bit was cleared.
1: An overflow has occurred since the last time this bit was cleared.
4:2 Unused Unused.
Read = 000b; Write = don’t care.
1:0 CLSEL[1:0] Cycle Length Select.
When 16-bit PWM mode is not selected, these bits select the length of the PWM
cycle, between 8, 9, 10, or 11 bits. This affects all channels configured for PWM which
are not using 16-bit PWM mode. The se bit s are ignored for individual channels config-
ured to16-bit PWM mode.
00: 8 bits.
01: 9 bits.
10: 10 bits.
11: 11 bits.
Rev. 1.1 309
C8051F91x-C8051F90x
SFR Address, Page: PCA0CPM0 = 0xDA, 0x0; PCA0CPM1 = 0xDB, 0x0; PCA0CPM2 = 0xDC, 0x0
PCA0CPM3 = 0xDD, 0x0; PCA0CPM4 = 0xDE, 0x0; PCA0CPM5 = 0xCE, 0x0
SFR Definition 26.4. PCA0CPMn: PCA Capture/Compare Mode
Bit76543210
Name PWM16n ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7PWM16n 16-bit Pulse Width Modulation Enable.
This bit enables 16-bit mode when Pulse Width Modulation mode is enabled.
0: 8 to 11-bit PWM se lected.
1: 16-bit PWM selected.
6ECOMn Comparator Function Enable.
This bit enables the compar ator function for PCA module n when set to 1.
5CAPPn Capture Positive Function Enable.
This bit enables the positive edge capture for PCA module n when set to 1.
4CAPNn Capture Negative Function Enable.
This bit enables the negative edge capture for PCA module n when set to 1.
3MATn Match Function Enable.
This bit enables the match function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a m odule's capture/comp are register cause the CCFn
bit in PCA0MD register to be set to logic 1.
2TOGn Toggle Function Enable.
This bit enables the toggle function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module's capture/compare register cause the logic
level on the CEXn pin to toggle. If the PWMn bit is also set to logic 1, the module oper-
ates in Frequency Output Mode.
1 PWMn Pulse Width Modulation Mode Enable.
This bit enables the PWM function for PCA module n when set to 1. When enabled, a
pulse width modulated signal is output on the CEXn pin. 8 to 11-bit PWM is used if
PWM16n is cleared; 16 -b it mo de is used if PWM1 6n is set to log ic 1. If the TOGn bit is
also set, the module operate s in Frequency Output Mode.
0ECCFn Capture/Compare Flag Interrupt Enable.
This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt.
0: Disable CCFn interrupts.
1: Enable a Capture/Compare Flag interrupt request when CCFn is set.
Note: When the WDTE bit is set to 1, the PCA0CPM5 register cannot be modified, and module 5 acts as the
watchdog timer . To change the contents of the PCA0CPM5 register or the function of module 5, the W atchdog
Timer must be disabled.
C8051F91x-C8051F90x
310 Rev. 1.1
SFR Page = 0x0; SFR Address = 0xF9
SFR Page = 0x0; SFR Address = 0xFA
SFR Definition 26.5. PCA0L: PCA Counter/Timer Low Byte
Bit76543210
Name PCA0[7:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0[7:0] PCA Counter/Timer Low Byte.
The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer.
Note: When the WDTE bit is set to 1, the PCA0L register cannot be modified by software. To change the contents of
the PCA0L register, the Watchdog Timer must first be disabled.
SFR Definition 26.6. PCA0H: PCA Counter/Timer High Byte
Bit76543210
Name PCA0[15:8]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0[15:8] PCA Counter/Timer High Byte.
The PCA0H register holds the high byte (MSB) of the 16-bit PCA Counter/Timer.
Reads of this register will read the contents of a “snapshot ” register, whose contents
are updated only when the contents of PCA0L are read (see Section 26.1).
Note: When the WDTE bit is set to 1, the PCA0H register cannot be modified by sof tware. To change the contents of
the PCA0H register, the Watchdog Timer must first be disabled.
Rev. 1.1 311
C8051F91x-C8051F90x
SFR Addresses: PCA0CPL0 = 0xFB, PCA0CPL1 = 0xE9, PCA0CPL2 = 0xEB,
PCA0CPL3 = 0xED, PCA0CPL4 = 0xFD, PCA0CPL5 = 0xD2
SFR Pages: PCA0CPL0 = 0x0, PCA0CPL1 = 0x0, PCA0CPL2 = 0x0,
PCA0CPL3 = 0x0, PCA0CPL4 = 0x0, PCA0CPL5 = 0x0
SFR Addresses: PCA0CPH0 = 0xFC, PCA0CPH1 = 0xEA, PCA0CPH2 = 0xEC,
PCA0CPH3 = 0xEE, PCA0CPH4 = 0xFE, PCA0CPH5 = 0xD3
SFR Pages: PCA0CPH0 = 0x0, PCA0CPH1 = 0x0, PCA0CPH2 = 0x0,
PCA0CPH3 = 0x0, PCA0CPH4 = 0x0, PCA0CPH5 = 0x0
SFR Definition 26.7. PCA0CPLn: PCA Capture Module Low Byte
Bit76543210
Name PCA0CPn[7:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0CPn[7:0] PCA Capture Module Low Byte.
The PCA0CPLn register holds the low byte (LSB) of the 16-bit capture module n.
This register address also allows access to the low byte of the corresponding
PCA channel’s auto-reload value for 9, 10, or 11-bit PWM mode. The ARSEL bit
in register PCA0PWM controls which register is accessed.
Note: A write to this register will clear the module’s ECOMn bit to a 0.
SFR Definition 26.8. PCA0CPHn: PCA Capture Module High Byte
Bit76543210
Name PCA0CPn[15:8]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0CPn[15:8] PCA Capture Module High Byte.
The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture module n.
This register address also allows access to the high byte of the corresponding
PCA channel’ s auto-reload value for 9, 10, or 11-bit PWM mode. The ARSEL bit in
register PCA0PWM controls which register is accessed.
Note: A write to this register will set the module’s ECOMn bit to a 1.
C8051F91x-C8051F90x
312 Rev. 1.1
27. C2 Interface
C8051F91x-C8051F90x devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow
Flash programming and in-system debugging with the production part installed in the end application. The
C2 interface uses a clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information
between the device and a host system. See the C2 Interface Specification for details on the C2 protocol.
27.1. C2 Interface Registers
The following describes the C2 registers necessary to perform Flash programming through the C2 inter-
face. All C2 registers are accessed throug h the C2 interface as de scribed in the C2 Interface Specification.
C2 Register Definition 27.1. C2ADD: C2 Address
Bit76543210
Name C2ADD[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 C2ADD[7:0] C2 Address.
The C2ADD register is accessed via the C2 interface to select the t arget Data register
for C2 Data Read and Data Write commands.
Address Description
0x00 Selects the Device ID register for Data Read instructions
0x01 Selects the Revision ID register for Data Read instructions
0x02 Selects the C2 Flash Programming Control register for Data
Read/Write instructions
0xB4 Selects the C2 Flash Programming Data register for Data
Read/Write instructions
Rev. 1.1 313
C8051F91x-C8051F90x
C2 Address: 0x00
C2 Address: 0x01
C2 Register Definition 27.2. DEVICEID: C2 Device ID
Bit76543210
Name DEVICEID[7:0]
Type R/W
Reset 00010100
Bit Name Function
7:0 DEVICEID[7:0] Device ID.
This read-only register returns the 8-bit device ID:
0x1F.
C2 Register Definition 27.3. REVID: C2 Revision ID
Bit76543210
Name REVID[7:0]
Type R/W
Reset Varies Varies Varies Varies Varies Varies Varies Varies
Bit Name Function
7:0 REVID[7:0] Revision ID.
This read-only register returns the 8-bit revision ID. For example: 0x00 = Revision
A.
C8051F91x-C8051F90x
314 Rev. 1.1
C2 Address: 0x02
C2 Address: 0xB4
C2 Register Definition 27.4. FPCTL: C2 Flash Programming Control
Bit76543210
Name FPCTL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 FPCTL[7:0] Flash Programming Control Register.
This register is used to enable Flash programming via the C2 interface. To enable C2
Flash programming, the followin g codes must be written in order: 0x02, 0x01. Note
that once C2 Flash programming is enabled, a system reset must be issued to
resume normal operation.
C2 Register Definition 27.5. FPDAT: C2 Flash Programming Data
Bit76543210
Name FPDAT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 FPDAT[7:0] C2 Flash Programming Data Register.
This register is used to pass Flash commands, addresses, and data during C2 Flash
accesses . Valid command s ar e lis te d be low.
Code Command
0x06 Flash Block Read
0x07 Flash Block W rite
0x08 Flash Page Erase
0x03 Device Erase
Rev. 1.1 315
C8051F91x-C8051F90x
27.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and
Flash programming may be performed. This is possible because C2 communication is typically performed
when the device is in the halt state, where all on-chip peripherals and user software are stalled. In this
halted state, the C2 interface can safely “borrow” the C2CK (RST) and C2D pins. In most applications,
external resistors are required to isolate C2 interface traffic from the user application. A typical isolation
configuration is shown in Figure 27.1.
Figure 27.1. Typical C2 Pin Sharing
The configuration in Figure 27.1 assumes the following:
1. The user input (b) cannot change state while the target device is halted.
2. The RST pin on the target device is used as an input only.
Additional resistors may be necessary depending on the specific application.
C2D
C2CK
RST (a)
Inpu t (b )
Output (c)
C2 Interface Master
C8051Fxxx
C8051F91x-C8051F90x
316 Rev. 1.1
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 1.0
Updated specification tables to remove TBDs.
Updated power management section to indicate that the low power or precision oscillator must be
selected when entering sleep or suspend mode.
Updated Port I/O chapter with addition al clarification on 5 V and 3.3 V tolerance.
Updated QFN-42 landing diagram a nd stencil recommendations.
Updated desc rip tion of ADC0 12 -b it mo de .
Revision 1.0 to Revision 1.1
Removed references to AN338.
Rev. 1.1 317
C8051F91x-C8051F90x
NOTES:
C8051F91x-C8051F90x
318 Rev. 1.1
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without
notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences
resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the function-
ing of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon
Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are
not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which
the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer
purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Silicon Laboratories harmless against all claims and damages.
