K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
1
Document Title
16M x 8 Bit NAND Flash Memory
Revision History
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
Revision No.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Remark
Advanced
Information
Preliminary
Preliminary
Final
History
Initial issue.
1. Revised real-time map-out algorithm(refer to technical notes)
1. Changed device name
- KM29U128AT -> K9F2808U0A-YCB0
- KM29U128AIT -> K9F2808U0A-YIB0
1. Changed sequential row read opera tion
- The Sequential Read 1 and 2 operation is allowed only within a block
2. Changed invalid block(s) marking method prior to shipping
- The invalid block(s) information is written the 1st or 2nd page of the
invalid block(s) with 00h data
--->The invalid block(s) status is defined by the 6th byte in the spare
area. Samsung makes sure that either the 1st or 2nd page of every
invalid block has 00h data at the column address of 517.
1. Changed endurance : 1million -> 100K program/erase cycles
2. Changed invalid block(s) marking method prior to shipping
- The invalid block(s) status is defined by the 6th byte in the spare
area. Samsung makes sure that either the 1st or 2nd page of every
invalid block has 00h data at the column address of 517.
--->The invalid block(s) status is defined by the 6th byte in the spare
area. Samsung makes sure that either the 1st or 2nd page of every
invalid block has non-FFh data at the column address of 517.
1. Changed SE pin description
- SE is recommended to coupled to GND or Vcc and should not be
toggled during reading or programming.
1. Changed don’t care mode in address cycles
- *X can be "High" or "Low" => *L must be set to "Low"
2. Explain how pointer operation works in detail.
3. Renamed GND input (pin # 6) on behalf of SE (pin # 6)
- The SE input controls the access of the spare area. When SE is high,
the spare area is not accessible for reading or programming. SE is rec
ommended to be coupled to GND or Vcc and should not be toggled
during reading or programming.
=> Connect this input pin to GND or set to static low state unless the
sequential read mode excluding spare area is used.
4. Updated operation for tRST timing
- If reset command(FFh) is written at Ready state, the device goes into
Busy for maximum 5us.
Draft Date
April 10th 1999
July 23th 1999
Sep. 15th 1999
Mar. 21th 2000
May 15th 2000
July 17th 2000
Nov. 20th 2000
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
2
16M x 8 Bit NAND Flash Memory
The K9F2808U0A is a 16M(16,777,216)x8bit NAND Flash
Memory with a spare 512K(524,288)x8bit. Its NAND cell pro-
vides the most cost-effective solution for the solid state mass
storage market. A program operation programs the 528-byte
page in typically 200µs and an erase operation can be per-
formed in typically 2ms on a 16K-byte block. Data in the page
can be read out at 50ns cycle time per byte. The I/O pins serve
as the ports for address and data input/output as well as com-
mand inputs. The on-chip write controller automates all pro-
gram and erase functions including pulse repetition, where
required, and internal verify and margining of data. Even the
write-intensive systems can take advantage of the
K9F2808U0A′s extended reliability of 100K program/erase
cycles by providing ECC(Error Correcting Code) with real time
mapping-out algorithm.
The K9F2808U0A is an optimum solution for large nonvolatile
storage applications such as solid state file storage, digital
voice recorder, digital still camera and other portable applica-
tions requiring non-volatility.
GENERAL DESCRIPTIONFEATURES
• Voltage Supply : 2.7V~3.6V
• Organization
- Memory Cell Array : (16M + 512K)bit x 8bit
- Data Register : (512 + 16)bit x8bit
• Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (16K + 512)Byte
• 528-Byte Page Read Operation
- Random Access : 10µs(Max.)
- Serial Page Access : 50ns(Min.)
• Fast Write Cycle Time
- Program Time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
• Command Register Operation
• Package : 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
PIN CONFIGURATION
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
K9F2808U0A-YCB0/YIB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
N.C
N.C
N.C
N.C
SE
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
Pin Name Pin Function
I/O0 ~ I/O7Data Input/Outputs
CLE Command Latch Enable
ALE Address Latch Enable
CE Chip Enable
RE Read Enable
WE Write Enable
WP Write Protect
GND GND input for enabling spare area
R/BReady/Busy output
VCC Power
VSS Ground
N.C No Connection
PIN DESCRIPTION
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
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512B Byte 16 Byte
Figure 1. FUNCTIONAL BLOCK DIAGRAM
Figure 2. ARRAY ORGANIZATION
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* L must be set to "Low".
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
1st Cycle A0A1A2A3A4A5A6A7
2nd Cycle A9A10 A11 A12 A13 A14 A15 A16
3rd Cycle A17 A18 A19 A20 A21 A22 A23 *L
VCC
X-Buffers
Command
I/O Buffers & Latches
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Register
Control Logic
& High Voltage
Generator Global Buffers Output
Driver
VSS
A9 - A23
A0 - A7
Command
CE
RE
WE
WP
I/0 0
I/0 7
VCC
VSS
A8
1st half Page Register
(=256 Bytes) 2nd half Page Register
(=256 Bytes)
32K Pages
(=1024 Blocks)
512 Byte
8 bit
16 Byte
1 Block =32 Pages
= (16K + 512) Byte
I/O 0 ~ I/O 7
1 Page = 528 Byte
1 Block = 528 Bytes x 32 Pages
= (16K + 512) Byte
1 Device = 528Byte x 32Pages x 1024 Blocks
= 132 Mbits
Column Address
Row Address
(Page Address)
Page Register
128M + 4M Bit
NAND Flash
ARRAY
(512 + 16)Byte x 32768
Y-Gating
Page Register & S/A
CLE ALE
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
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PRODUCT INTRODUCTION
The K9F2808U0A is a 132Mbit(138,412,032 bit) memory organized as 32,768 rows(pages) by 528 columns. Spare sixteen columns
are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data
transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16
cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32
pages formed by one NAND structures, totaling 8448 NAND structures of 16 cells. The array organization is shown in Figure 2. The
program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory
array consists of 1024 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
K9F2808U0A.
The K9F2808U0A has addresses multiplexed into 8 I/O′s. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block
address loading. The 16M byte physical space requires 24 addresses, thereby requiring three cycles for byte-level addressing: col-
umn address, low row address and high row address, in that order. Page Read and Page Program need the same three address
cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used. Device
operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the
K9F2808U0A.
Table 1. COMMAND SETS
NOTE : 1. The 00h command defines starting address of the 1st half of registers.
The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is
automatically moved to the 1st half register(00h) on the next cycle.
2. The 50h command is valid only when the GND input(pin #6) is low level.
Function 1st. Cycle 2nd. Cycle Acceptable Command during Busy
Read 1 00h/01h(1) -
Read 2 50h(2) -
Read ID 90h -
Reset FFh -O
Page Program 80h 10h
Block Erase 60h D0h
Read Status 70h -O
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
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PIN DESCRIPTION
Command Latch Enable(CLE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of
WE with ALE high.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge
of RE which also increments the internal column address counter by one.
GND (Pin # 6)
Connect this input pin to GND or set to static low state unless the sequential read mode excluding spare area is used.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
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DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter Symbol Test Conditions Min Typ Max Unit
Operating
Current
Sequential Read ICC1tRC=50ns, CE=VIL, IOUT=0mA -10 20
mA
Program ICC2- - 10 20
Erase ICC3- - 10 20
Stand-by Current(TTL) ISB1CE=VIH, WP=GND input (Pin #6)
= 0V/VCC - - 1
Stand-by Current(CMOS) ISB2CE=VCC-0.2, WP=GND input (Pin
#6) = 0V/VCC -10 50
µA
Input Leakage Current ILI VIN=0 to 3.6V - - ±10
Output Leakage Current ILO VOUT=0 to 3.6V - - ±10
Input High Voltage VIH -2.0 -VCC+0.3
V
Input Low Voltage, All inputs VIL --0.3 -0.8
Output High Voltage Level VOH IOH=-400µA2.4 - -
Output Low Voltage Level VOL IOL=2.1mA - - 0.4
Output Low Current(R/B)IOL(R/B)VOL=0.4V 810 -mA
ABSOLUTE MAXIMUM RATINGS
NOTE :
1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter Symbol Rating Unit
Voltage on any pin relative to VSS VIN -0.6 to + 4.6 V
VCC -0.6 to + 4.6
Temperature Under Bias K9F2808U0A-YCB0 TBIAS -10 to +125 °C
K9F2808U0A-YIB0 -40 to +125
Storage Temperature TSTG -65 to +150 °C
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9F2808U0A-YCB0:TA=0 to 70°C, K9F2808U0A-YIB0:TA=-40 to 85°C)
Parameter Symbol Min Typ. Max Unit
Supply Voltage VCC 2.7 3.3 3.6 V
Supply Voltage VSS 000V
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
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MODE SELECTION
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
3. When GND input is high, spare area is deselected.
CLE ALE CE WE RE GND WP Mode
HL L HX X Read Mode Command Input
LHLHX X Address Input(3clock)
HL L HXHWrite Mode Command Input
LHLHXH Address Input(3clock)
L L L HL/H(3) H Data Input
L L L HL/H(3) X Sequential Read & Data Output
L L L H H L/H(3) X During Read(Busy)
X X X X X L/H(3) H During Program(Busy)
XXXXXXH During Erase(Busy)
XX(1) X X X X L Write Protect
X X HX X 0V/VCC(2) 0V/VCC(2) Stand-by
CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)
NOTE : Capacitance is periodically sampled and not 100% tested.
Item Symbol Test Condition Min Max Unit
Input/Output Capacitance CI/O VIL=0V -10 pF
Input Capacitance CIN VIN=0V -10 pF
VALID BLOCK
NOTE :
1. The K9F2808U0A may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid
blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try
to access these invalid blocks for program and erase. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block
Parameter Symbol Min Typ. Max Unit
Valid Block Number NVB 1004 -1024 Blocks
AC TEST CONDITION
(K9F2808U0A-YCB0:TA=0 to 70°C, K9F2808U0A-YIB0:TA=-40 to 85°C, VCC=2.7V~3.6V unless otherwise noted)
Parameter Value
Input Pulse Levels 0.4V to 2.4V
Input Rise and Fall Times 5ns
Input and Output Timing Levels 1.5V
Output Load (3.0V +/-10%) 1 TTL GATE and CL=50pF
Output Load (3.3V +/-10%) 1 TTL GATE and CL=100pF
Program/Erase Characteristics
Parameter Symbol Min Typ Max Unit
Program Time tPROG -200 500 µs
Number of Partial Program Cycles
in the Same Page Main Array Nop - - 2cycles
Spare Array - - 3cycles
Block Erase Time tBERS -2 3 ms
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
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AC Characteristics for Operation
NOTE :
1. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
2. To break the sequential read cycle, CE must be held high for longer time than tCEH.
3. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
Parameter Symbol Min Max Unit
Data Transfer from Cell to Register tR-10 µs
ALE to RE Delay( ID read ) tAR1 100 -ns
ALE to RE Delay(Read cycle) tAR2 50 -ns
CE to RE Delay( ID read) tCR 100 -ns
Ready to RE Low tRR 20 -ns
RE Pulse Width tRP 30 -ns
WE High to Busy tWB -100 ns
Read Cycle Time tRC 50 -ns
RE Access Time tREA -35 ns
RE High to Output Hi-Z tRHZ 15 30 ns
CE High to Output Hi-Z tCHZ -20 ns
RE High Hold Time tREH 15 -ns
Output Hi-Z to RE Low tIR 0-ns
Last RE High to Busy(at sequential read) tRB -100 ns
CE High to Ready(in case of interception by CE at read) tCRY -50 +tr(R/B)(1) ns
CE High Hold Time(at the last serial read)(2) tCEH 100 -ns
RE Low to Status Output tRSTO -35 ns
CE Low to Status Output tCSTO -45 ns
WE High to RE Low tWHR 60 -ns
RE access time(Read ID) tREADID -35 ns
Device Resetting Time(Read/Program/Erase) tRST -5/10/500(3) µs
AC Timing Characteristics for Command / Address / Data Input
Parameter Symbol Min Max Unit
CLE Set-up Time tCLS 0-ns
CLE Hold Time tCLH 10 -ns
CE Setup Time tCS 0-ns
CE Hold Time tCH 10 -ns
WE Pulse Width tWP 25 -ns
ALE Setup Time tALS 0-ns
ALE Hold Time tALH 10 -ns
Data Setup Time tDS 20 -ns
Data Hold Time tDH 10 -ns
Write Cycle Time tWC 50 -ns
WE High Hold Time tWH 15 -ns
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
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NAND Flash Technical Notes
Identifying Invalid Block(s)
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. Typically,
an invalid block will contain a single bad bit. The information regarding the invalid block(s) is so called as the invalid block informa-
tion. Devices with invalid block(s) have the same quality level or as devices with all valid blocks and have the same AC and DC char-
acteristics. An invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the
common source line by a select transistor. The system design must be able to mask out the invalid block(s) via address mapping.
The 1st block of the NAND Flash, however, is fully guaranteed to be a valid block.
All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid
block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid
block has non-FFh data at the column address of 517. Since the invalid block information is also erasable in most cases, it is impos-
sible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based
on the original invalid block information and create the invalid block table via the following suggested flow chart(Figure 1). Any inten-
tional erasure of the original invalid block information is prohibited.
*Check "FFh" at the column address 517
Figure 1. Flow chart to create invalid block table.
Start
Set Block Address = 0
Check "FFh" ?
Increment Block Address
Last Block ?
End
No
Yes
Yes
Create (or update) No
Invalid Block(s) Table
of the 1st and 2nd page in the block
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
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NAND Flash Technical Notes (Continued)
Program Flow Chart
Start
I/O 6 = 1 ?
Write 00h
I/O 0 = 0 ?
No
*
If ECC is used, this verification
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
Write Address
Wait for tR Time
Verify Data No
Program Completed
or R/B = 1 ?
Program Error
Yes
No
Yes
*
Program Error
Yes
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
operation is not needed.
Error in write or read operation
Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-
ure after erase or program, block replacement should be done. To improve the efficiency of memory space, it is recommended that
the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block
failure rate does not include those reclaimed blocks.
Failure Mode Detection and Countermeasure sequence
Write
Erase Failure Status Read after Erase --> Block Replacement
Program Failure Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
or ECC Correction
Read Single Bit Failure Verify ECC -> ECC Correction
ECC : Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
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Erase Flow Chart
Start
I/O 6 = 1 ?
I/O 0 = 0 ?
No
*
Write 60h
Write Block Address
Write D0h
Read Status Register
or R/B = 1 ?
Erase Error
Yes
No
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Erase Completed
Yes
Read Flow Chart
Start
Verify ECC
No
Write 00h
Write Address
Read Data
ECC Generation
Reclaim the Error
Page Read Completed
Yes
Block Replacement
NAND Flash Technical Notes (Continued)
When the error happens with page "a" of Block "A", try
to write the data into another Block "B" from an exter-
nal buffer. Then, prevent further system access to
Block "A" (by creating a "invalid block" table or other
appropriate scheme.)
Buffer
memory error occurs
Block A
Block B
Page a
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
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Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets
the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however, is effective
only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command, the
address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputted
before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting from
’B’ area, ’01h’ command must be inputted right before ’80h’ command is written.
00h
(1) Command input sequence for programming ’A’ area
Address / Data input
80h 10h 00h 80h 10h
Address / Data input
The address pointer is set to ’A’ area(0~255), and sustained
01h
(2) Command input sequence for programming ’B’ area
Address / Data input
80h 10h 01h 80h 10h
Address / Data input
’B’, ’C’ area can be programmed.
It depends on how many data are inputted. ’01h’ command must be rewritten before
every program operation
The address pointer is set to ’B’ area(256~512), and will be reset to
’A’ area after every program operation is executed.
50h
(3) Command input sequence for programming ’C’ area
Address / Data input
80h 10h 50h 80h 10h
Address / Data input
Only ’C’ area can be programmed. ’50h’ command can be omitted.
The address pointer is set to ’C’ area(512~527), and sustained
’00h’ command can be omitted.
It depends on how many data are inputted.
’A’,’B’,’C’ area can be programmed.
Pointer Operation of K9F2808U0A
Table 1. Destination of the pointer
Command Pointer position Area
00h
01h
50h
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
"A" area
256 Byte
(00h plane) "B" area
(01h plane) "C" area
(50h plane)
256 Byte 16 Byte
"A" "B" "C"
Internal
Page Register
Pointer select
commnad
(00h, 01h, 50h) Pointer
Figure 2. Block Diagram of Pointer Operation
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
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System Interface Using CE don’t-care.
CE
WE tWP
tCH
Timing requirements : If CE is is exerted high during data-loading,
tCS must be minimum 10ns and tWC must be increased accordingly.
tCS
(Min. 10ns)
Start Add.(3Cycle)80h Data Input
CE
CLE
ALE
WE
I/O0~7Data Input
CE don’t-care
≈
≈
10h
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-
ing would provide significant savings in power consumption.
Start Add.(3Cycle)00h
CE
CLE
ALE
WE
I/O0~7Data Output(sequential)
CE don’t-care
≈
R/BtR
RE
tCEA
out
tREA
(Max. 45ns)
CE
RE
I/O0~7
Timing requirements : If CE is exerted high during sequential
data-reading, the falling edge of CE to valid data(tCEA) must
be kept greater than 45ns.
Figure 3. Program Operation with CE don’t-care.
Figure 4. Read Operation with CE don’t-care.
Must be held
low during tR.
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
14
* Command Latch Cycle
CE
WE
CLE
ALE
I/O0~7Command
* Address Latch Cycle
tCLS
tCS
tCLH
tCH
tWP
tALS tALH
tDS tDH
CE
WE
CLE
ALE
I/O0~7A0~A7
tCLS
tCS tWC
tWP
tALS
tDS tDH
tALH tALS
tWH
A9~A16
tWC
tWP
tDS tDH
tALH tALS
tWH
A17~A23
tWP
tDS tDH
tALH
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
15
* Input Data Latch Cycle
CE
CLE
WE
I/O0~7DIN 0 DIN 1 DIN 511
ALE tALS
tCLH
tWC
tCH
tDS tDH tDS tDH tDS tDH
tWP
tWH
tWP tWP
* Sequential Out Cycle after Read(CLE=L, WE=H, ALE=L)
RE
CE
R/B
I/O0~7Dout Dout Dout
tRC
tREA
tRR
tRHZ*
tREA
tREH tREA tCHZ*
tRHZ*
≈
≈≈
≈≈≈≈
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
16
* Status Read Cycle
CE
WE
CLE
RE
I/O0~770h Status Output
tCLS
tCLH
tCS
tWP tCH
tDS tDH tRSTO
tIR tRHZ*
tCHZ*
tWHR
tCSTO
tCLS
READ1 OPERATION(READ ONE PAGE)
CE
CLE
R/B
I/O0~7
WE
ALE
RE
Busy
00h or 01h A0 ~ A7A9 ~ A16 A17 ~ A23 Dout N Dout N+1 Dout N+2 Dout N+3
Column
Address Page(Row)
Address
tWB tAR2
tRtRC tRHZ
tCHZ
tCEH
Dout 527
tRB
tCRY
tWC
tRR
≈
≈
≈
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
17
READ1 OPERATION(INTERCEPTED BY CE)
CE
CLE
R/B
I/O0~7
WE
ALE
RE
Busy
00h or 01h A0 ~ A7A9 ~ A16 A17 ~ A23 Dout N Dout N+1 Dout N+2 Dout N+3
Page(Row)
Address
Address
Column
tWB tAR2 tCHZ
tR
tRR
tRC
READ2 OPERATION(READ ONE PAGE)
CE
CLE
R/B
I/O0~7
WE
ALE
RE
50h A0 ~ A7A9 ~ A16 A17 ~ A23 Dout Dout 527
M Address
511+M Dout
511+M+1
tAR2
tR
tWB
tRR
A0~A3 : Valid Address
A4~A7 : Don′t care
≈
≈
Selected
Row
Start
address M
512 16
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
18
PAGE PROGRAM OPERATION
CE
CLE
R/B
I/O0~7
WE
ALE
RE
80h 70h I/O0
Din
NDin Din 10h
527
N+1
A0 ~ A7A17 ~ A23A9 ~ A16
Sequential Data
Input Command Column
Address Page(Row)
Address 1 up to 528 Byte Data
Serial Input Program
Command Read Status
Command
I/O0=0 Successful Program
I/O0=1 Error in Program
tPROG
tWB
tWC tWC tWC
SEQUENTIAL ROW READ OPERATION(WITHIN A BLOCK)
CE
CLE
R/B
I/O0~7
WE
ALE
RE
00h A0 ~ A7
Busy
M
Output
A9 ~ A16 A17 ~ A23 Dout
NDout
N+1 Dout
N+2 Dout
527 Dout
0Dout
1Dout
2Dout
527
Busy
M+1
Output
N
Ready
≈≈
≈
≈
≈
≈
≈
≈
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
19
BLOCK ERASE OPERATION(ERASE ONE BLOCK)
MANUFACTURE & DEVICE ID READ OPERATION
CE
CLE
I/O 0 ~ 7
WE
ALE
RE
90h
Read ID Command Maker Code Device Code
00h ECh 73h
tREADID
Address. 1cycle
CE
CLE
R/B
I/O0~7
WE
ALE
RE
60h A17 ~ A23A9 ~ A16
Auto Block Erase Erase Command Read Status
Command I/O0=1 Error in Erase
DOh 70h I/O 0
Busy
tWB tBERS
I/O0=0 Successful Erase
Page(Row)
Address
tWC
≈
Setup Command
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
20
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg-
ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Three types of operations are available : random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are trans-
ferred to the data registers in less than 10µs(tR). The system controller can detect the completion of this data transfer(tR) by analyz-
ing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially
pulsing RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last column
address(column 511 or 527 depending on the state of GND input pin).
After the data of last column address is clocked out, the next page is automatically selected for sequential row read.
Waiting 10µs again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. The
way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes
512 to 527 may be selectively accessed by writing the Read2 command with GND input pin low. Toggling SE during operation is pro-
hibited. Addresses A0 to A3 set the starting address of the spare area while addresses A4 to A7 are ignored. Unless the operation is
aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of
each page may be sequentially read. The Read1 command(00h/01h) is needed to move the pointer back to the main area. Figures 3
thru 6 show typical sequence and timings for each read operation.
Figure 3. Read1 Operation
Start Add.(3Cycle)
00h
A0 ~ A7 & A9 ~ A23
Data Output(Sequential)
(00h Command)
Data Field Spare Field
CE
CLE
ALE
R/B
WE
I/O0~7
RE
tR
* After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
array (00h) at next cycle.
(01h Command)*
Data Field Spare Field
1st half array 2st half array1st half array 2st half array
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
21
Figure 4. Read2 Operation
50h
A0 ~ A3 & A9 ~ A23
Data Output(Sequential)
Spare Field
CE
CLE
ALE
R/B
WE
Data Field Spare Field
Start Add.(3Cycle)
(A4 ~ A7 :
Don′t Care)
I/O0~7
RE
Figure 5. Sequential Row Read1 Operation
00h
01h A0 ~ A7 & A9 ~ A23
I/O0 ~ 7
R/B
Start Add.(3Cycle) Data Output Data Output Data Output
1st 2nd Nth
(528 Byte) (528 Byte)
tRtRtR
tR
≈
The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is read-
out, the sequential read operation must be terminated by bringing CE high. When the page address moves onto
the next block, read command and address must be given.
(GND Input=L, 00h Command)
Data Field Spare Field
(GND Input=L, 01h Command)
Data Field Spare Field
(GND Input=H, 00h Command)
Data Field Spare Field
1st half array 2nd half array
1st
2nd
Nth
1st half array 2nd half array
1st
2nd
Nth
Block
1st half array 2nd half array
1st
2nd
Nth
1st half array 2nd half array
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
22
Figure 6. Sequential Row Read2 Operation (GND Input=Fixed Low)
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive
bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be done
in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be
loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropri-
ate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the
attached technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three cycle address input and
then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm com-
mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-
gramming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify,
thereby freeing the CPU for other tasks. Once the program process starts, the Read Status Register command may be entered, with
RE and CE low, to read the status register. The CPU can detect the completion of a program cycle by monitoring the R/B output, or
the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in
progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 7). The internal write verify
detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command
mode until another valid command is written to the command register.
50h
A0 ~ A3 & A9 ~ A23
I/O0~7
R/B
Start Add.(3Cycle) Data Output Data Output Data Output
2nd Nth
(16Byte) (16Byte)
(A4 ~ A7 :
Don′t Care)
1st
Figure 7. Program & Read Status Operation
80h
A0 ~ A7 & A9 ~ A23
I/O0~7
R/B
Address & Data Input I/O0Pass
528 Byte Data
10h 70h
Fail
tRtRtR
tPROG
≈
Data Field Spare Field
1st
Block
Nth
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
23
Figure 8. Block Erase Operation
BLOCK ERASE
The Erase operation is done on a block(16K Bytes) basis. Block address loading is accomplished in two cycles initiated by an Erase
Setup command(60h). Only address A14 to A23 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the
block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked.
Figure 8 details the sequence.
60h
Block Add. : A9 ~ A23
I/O0~7
R/B
Address Input(2Cycle) I/O0Pass
D0h 70h
Fail
tBERS
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
I/O # Status Definition
I/O 0 Program / Erase "0" : Successful Program / Erase
"1" : Error in Program / Erase
I/O 1
Reserved for Future
Use
"0"
I/O 2 "0"
I/O 3 "0"
I/O 4 "0"
I/O 5 "0"
I/O 6 Device Operation "0" : Busy "1" : Ready
I/O 7 Write Protect "0" : Protected "1" : Not Protected
Table2. Read Status Register Definition
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
24
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Two read cycles sequentially output the manufacture code(ECh), and the device code (73h) respectively. The command register
remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence.
Figure 9. Read ID Operation
CE
CLE
I/O0~7
ALE
RE
WE
90h 00h ECh 73h
Address. 1cycle Maker code Device code
tCR
tAR1
tREADID
Figure 10. RESET Operation
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 10 below.
After Power-up After Reset
Operation Mode Read 1 Waiting for next command
FFhI/O0~7
R/B
Table3. Device Status
tRST
K9F2808U0A-YCB0, K9F2808U0A-YIB0 FLASH MEMORY
25
Figure 11. AC Waveforms for Power Transition
DATA PROTECTION
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL
during power-up and power-down as shown in Figure 11. The two step command sequence for program/erase provides additional
software protection.
VCC
WP
High
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg-
ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. An appropriate pull-up resister is required for proper
operation and the value may be calculated by the following equation.
VCC
R/B
open drain output
Device
GND
Rp = VCC(Max.) - VOL(Max.)
IOL +ΣIL = 3.2V
8mA + ΣIL
where IL is the sum of the input currents of all devices tied to the
R/B pin.
≈≈
~ 2.5V ~ 2.5V
Rp
FLASH MEMORY
26
Package Dimensions
PACKAGE DIMENSIONS
48-PIN LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F Unit :mm/Inch
0.787±0.008
20.00±0.20
#1
#24
0.20+0.07
-0.03
0.008+0.003
-0.001
0.50
0.0197
#48
#25
0.488
12.40MAX
12.00
0.472
0.10
0.004 MAX
0.25
0.010
( )
0.039±0.002
1.00±0.05 0.002
0.05 MIN
0.047
1.20 MAX
0.45~0.75
0.018~0.030
0.724±0.004
18.40±0.10
0~8¡Æ
0.010
0.25 TYP
0.125+0.075
0.035
0.005+0.003
-0.001
0.50
0.020
( )
