ACFL-6211T, ACFL-6212T Automotive High Speed, Low Power Digital Optocoupler with R2CouplerTM Isolation in a Stretched 12-Pin Surface Mount Plastic Package Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features The ACFL-6211T and ACFL-6212T are automotive grade dual channel, bi-directional, high speed digital CMOS optocouplers. The stretched SO-12 stretched package outline is designed to be compatible with standard surface mount processes and occupies the same land area as their single channel equivalent, ACPL-K71T and ACPL-K72T, in stretched SO8 package. * Qualified to AEC Q100 Grade 1 Test Guidelines This digital optocoupler uses an insulating layer between the light emitting diode and an integrated photo detector to provide electrical insulation between input and output. Each channel of the digital optocoupler has a CMOS detector IC with an integrated photodiode, a high speed trans-impedance amplifier, and a voltage comparator with an output driver. Each channel is also isolated from the other. * Automotive Wide Temperature Range: -40C to +125C * 5 V CMOS compatibility * 40 kV/s Common-Mode Rejection at VCM=1000V (typ) * Low Propagation Delay : * ACFL-6211T: 25ns @ IF = 10mA (typ) * ACFL-6212T: 60ns @ IF = 4mA (typ) * Compact, Auto-Insertable Stretched SO12 Packages * Worldwide Safety Approval: - UL 1577 recognized, 5kVRMS/1 min. - CSA Approved - IEC/EN/DIN EN 60747-5-5 Avago R2Coupler technology provides reinforced insulation and reliability that delivers safe signal isolation critical in automotive and high temperature industrial applications. Applications Functional Diagram * High Temperature Digital/Analog Signal Isolation * Automotive IPM Driver for DC-DC converters and motor inverters * CANBus and SPI Communications Interface * Power Transistor Isolation VDD1 1 12 CA1 VOUT1 2 11 AN1 GND 1 3 10 VDD2 AN2 4 9 VOUT2 CA2 LED VO 5 8 GND 2 ON LOW CA2 6 7 GND 2 OFF HIGH Truth Table Note: The connection of a 1 F bypass capacitor between pins 1 and 3 and pins 8 and 10 is recommended. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. The components featured in this datasheet are not to be used in military or aerospace applications or environments. Pin Description Pin No. Pin Name Description Pin No. Pin Name Description 1 VDD1 Primary Side Power Supply 7 GND2 Secondary Side Ground 2 VOUT1 Output 1 8 GND2 Secondary Side Ground 3 GND1 Primary Side Ground 9 VOUT2 Output 2 4 AN2 Anode 2 10 VDD2 Secondary Side Power Supply 5 CA2 Cathode 2 11 AN1 Anode 1 6 CA2 Cathode 2 12 CA1 Cathode 1 Ordering Information Part number Option (RoHS Compliant) ACFL-6211T -000E -060E ACFL-6212T Package Stretched SO-12 Surface Mount Tape & Reel UL 5000 Vrms/ 1 Minute rating X X X X -500E X X X -560E X X X -000E -060E Stretched SO-12 X IEC/EN/DIN EN 60747-5-5 Quantity 80 per tube X 1000 per reel X X X X -500E X X X -560E X X X 80 per tube 1000 per reel 80 per tube X 80 per tube 1000 per reel X 1000 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACFL-6212T-560E to order product of SSO-12 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval in RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. 2 Package Outline Drawing 12-Lead Surface Mount 0.015 (0.381) 0.032 (0.800) LAND PATTERN RECOMMENDATION 12 11 10 9 8 7 RoHS-COMPLIANCE INDICATOR TYPE NUMBER DATECODE 621xT YYWW EE 0.295 +- 0.005 0 1 2 3 4 5 6 0.230 +- 0.005 0 + 0.127 ( 5.842 - 0 0.458 (11.630) ( 7.493 +- 0.127 ) 0 EXTENDED DATECODE FOR LOT TRACKING 0.080 (2.030) 0.020 (0.500) ) 0.326 0.010 (8.284 0.254) 7 45 0.063 0.005 (1.590 0.127) 0.008 0.004 (0.200 0.100) 0.015 (0.381) 0.125 0.005 (3.180 0.127) 0.029 0.004 (0.731 0.100) 0.408 0.010 (10.363 0.250) Dimensions in inches (millimeters) Lead coplanarity = 0.004 inches (0.1mm) Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Note: Non-halide flux should be used 3 7 0 to 7 0.010 0.002 (0.254 0.050) Regulatory Information The ACFL-6211T and ACFL-6212T are approved by the following organizations: UL UL 1577, component recognition program up to VISO = 5kVRMS CSA Approved under CSA Component Acceptance Notice #5 IEC/EN/DIN EN 60747-5-5 Approved under IEC/EN/DIN EN 60747-5-5 Insulation and Safety Related Specifications Parameter Symbol ACFL-6211T / ACFL-6212T Units Conditions Minimum External Air Gap (Clearance) L(101) 8.3 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (Creepage) L(102) 8.5 mm Measured from input terminals to output terminals, shortest distance path along body. 0.08 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. 175 V Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) CTI Isolation Group (DIN VDE0109) IIIa DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0109) IEC / EN / DIN EN 60747-5-5 Insulation Related Characteristic (Option 060E and 560E) Description Symbol Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage 600 V rms for rated mains voltage < 1000 V rms Units I-III I-III Climatic Classification 40/125/21 Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage Characteristic 2 VIORM 1140 VPEAK Input to Output Test Voltage, Method b VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC VPR 2137 VPEAK Input to Output Test Voltage, Method a VIORM x 1.6 = VPR, Type and sample test, tm = 10 sec, Partial Discharge < 5 pC VPR 1824 VPEAK VIOTM 6000 VPEAK TS IS,INPUT PS,OUTPUT 175 230 600 C mA mW RS 109 W Highest Allowable Overvoltage (Transient Overvoltage, tini = 60 sec) Safety Limiting Values (Maximum values allowed in the event of a failure) Case Temperature Input Current Output Power Insulation Resistance at TS, VIO = 500 V 4 Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TS -55 +150 C Ambient Operating Temperature [1] TA -40 +125 C Junction Temperature TJ +150 C Supply Voltages VDD 0 6.5 V Output Voltage VO -0.5 VDD +0.5 V Average Forward Input Current IF - 20.0 mA Peak Transient Input Current (IF at 1us pulse width, <10% duty cycle) IF( TRAN) 1 80 A mA Reverse Input Voltage Vr 5 V Input Power Dissipation PI 40 mW Average Output Current Io 10 mA Output Power Dissipation Po 30 mW Lead Solder Temperature 260C for 10 sec., 1.6 mm below seating plane Solder Reflow Temperature Profile See Solder Reflow Temperature Profile Section - Condition 1us Pulse Width, 300pps 1us Pulse Width, <10%Duty Cycle Recommended Operating Conditions Parameter Symbol Min. Max. Units Supply Voltage VDD 3.0 5.5 V Operating Temperature TA -40 125 C Forward Input Current IF(ON) 4.0 15 mA Forward Off State Voltage VF(OFF) 0.8 V Input Threshold Current ITH 3.5 mA Note Electrical Specifications Over recommended operating conditions. All typical specifications are at TA=25C, VDD= 5V. Parameter Symbol Min. Typ. Max. Units Test Conditions LED Forward Voltage VF 1.45 1.5 1.75 V IF = 10mA, TA = 25C 1.25 1.5 1.85 V IF = 10mA VF Temperature Coefficient -1.5 Fig mV/C Input Threshold Current ITH 1.3 Input Capacitance CIN 90 Input Reverse Breakdown Voltage BVR 5.0 V IR = 10 A Logic High Output Voltage VOH VDD-0.6 V IOH = -3.2mA 4 Logic Low Output Voltage VOL 0.6 V IOL = 4mA 3 Logic Low Output Supply Current (per channel) IDDL 0.9 1.5 mA Logic High Output Supply Current (per channel) IDDH 0.9 1.5 mA 5 3.5 mA 2 pF ACFL-6211T High Speed Mode Switching Specifications Over recommended operating conditions: TA = -40C to +125C, 4.5 V VDD 5.5 V. All typical specifications are at TA=25C, VDD = 5V. Parameter Symbol Propagation Delay Time to Logic Low Output Min. Typ. Max. Units Test Conditions Fig Note tPHL 25 35 ns 5, 9, 11 1, 2, 3 Propagation Delay Time to Logic High Output tPLH 25 35 ns Vin = 4.5V-5.5V, Rin = 390W+/-5%, Cin = 100pF, CL = 15pF Pulse Width Distortion PWD 0 12 ns Propagation Delay Skew tPSK 15 ns Output Rise Time (10% - 90%) tR 10 ns Output Fall Time (90% - 10%) tF 10 ns Common Mode Transient Immunity at Logic High Output | CMH | 15 25 kV/s Vin = 0V Rin = 390W 5%, Cin = 100pF, Vcm = 1000V, TA = 25C 4 Common Mode Transient Immunity at Logic High Output | CML | 15 25 kV/s Vin = 4.5V-5.5V , Rin = 390W 5%, Cin = 100pF, Vcm = 1000V, TA = 25C 5 Output low threshold = 0.8V Output high threshold = 80% of Vdd ACFL-6212T Low Power Mode Switching Specifications Over recommended operating conditions: TA = -40C to +125C, 3.0 V VDD 5.5 V All typical specifications at 25C and VDD = 5V. Parameter Symbol Propagation Delay Time to Logic Low Output Typ. Max. Units Test Conditions Fig Note tPHL 60 100 ns IF = 4mA, CL= 15pF 7, 12 1, 2, 3 Propagation Delay Time to Logic High Output tPLH 35 100 ns Pulse Width Distortion PWD 25 50 ns Propagation Delay Skew tPSK 60 ns Output Rise Time (10% - 90%) tR 10 ns Output Fall Time (90% - 10%) tF 10 ns Common Mode Transient Immunity at Logic High Output | CMH | 25 40 kV/s Using Avago LED Driving Circuit, VIN = 0V, R1 = 330W 5%, R2 = 330W 5%, VCM = 1000V, TA = 25C 4 Common Mode Transient Immunity at Logic Low Output | CML | 25 40 kV/s Using Avago LED Driving Circuit, VIN=4.5-5.5V, R1 = 330W 5%, R2 = 330W 5%, VCM = 1000V, TA = 25C 5 6 Min. Package Characteristics All Typical at TA = 25C. Parameter Symbol Min. Input-Output Momentary Withstand Voltage VISO 5000 Input-Output Resistance RI-O Input-Output Capacitance CI-O Typ. Max. Units Test Conditions Notes Vrms RH 50%, t = 1 min. TA = 25C 6, 7 1014 W VI-O = 500 V dc 6 0.6 pF f = 1 MHz, TA = 25C 6 Notes: 1. tPHL propagation delay is measured from the 50% (VIN or IF) on the rising edge of the input pulse to the 0.8V of VDD of the falling edge of the VO signal. tPLH propagation delay is measured from the 50% (VIN or IF) on the falling edge of the input pulse to the 80% level of the rising edge of the VO signal. 2. PWD is defined as |tPHL - tPLH|. 3. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. 4. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state. 5. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state. 6. Device considered a two terminal device: pins 1 to 6 shorted together, and pins 7 to 12 shorted together. 7. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage > 6000VRMS for 1 second. 7 Typical Performance Plots 5 Temp=-40C Temp=25C Temp=125C 10.00 1.00 0.10 0.01 1.0 1.1 1.2 1.3 1.4 1.5 Forward Voltage 1.6 1.7 VOH - Logic High Output Voltage - V VOL - Logic Low Output Voltage - V 0.5 1.0 1.5 IF - Input Forward Current - mA 2.0 5.0 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2 60 4 6 IOL - Logic Low Output Current - mA 8 4.8 4.6 4.4 4.2 4.0 10 0 -2 -4 -6 -8 IOH - Logic High Output Current - mA -10 Figure 4. Typical Logic High Output Voltage vs Logic High Output Current 35 TPLH TPHL PWD TPLH TPHL PWD 30 TP - Propogation Delay - ns 50 TP - Propogation Delay - ns 0.0 Figure 2. Typical Output Voltage vs Input Forward Current Figure 3 Typical Logic Low Output Voltage vs Logic Low Output Current 40 30 20 10 0 25 20 15 10 5 0 -40 -20 0 20 40 60 80 TA - Temperature - C 100 Figure 5. ACFL-6211T (High Speed) Typical Propagation Delay vs Temperature, VIN=4.5V, RIN=390W, CIN=100pF 8 2 0 1.8 0.8 -10 3 1 Figure 1. Typical Diode Input Forward Current Characteristic 0.0 Temp=-40C Temp=25C Temp=125C 4 VO - Output Voltage - V IF - Input Forward Current - mA 100.00 120 140 -5 4 5 6 7 8 9 10 11 12 IF - Forward Current - mA 13 14 Figure 6. ACFL-6211T (High Speed) Typical Propagation Delay vs Input Forward Current, VIN=4.5V, RIN=390W, CIN=100pF, TA=25C 15 70 60 50 40 30 20 TPLH TPHL PWD 10 0 -40 -20 0 20 40 60 80 TA - Temperature - C 100 120 40 30 20 TPLH TPHL PWD 0 4 5 6 7 8 9 10 11 IF - Forward Current - mA 12 13 14 15 TPLH TPHL PWD VDD=3V, TA=25C 60 50 50 40 30 20 10 20 40 60 80 TA - Temperature - C 100 120 Figure 9. ACFL-6212T (3V) Typical Propagation Delay vs Temperature 9 20 70 TP - Propogation Delay - ns TP - Propogation Delay - ns 60 -20 30 Figure 8. ACFL-6212T (5V) Typical Propagation Delay vs Input Forward Current IF=4mA, VDD=3V -40 40 0 140 70 0 50 10 Figure 7. ACFL-6212T (5V) Typical Propagation Delay vs Temperature 10 TPLH TPHL PWD VDD=5V, TA=25C 60 TP - Propogation Delay - ns TP - Propogation Delay - ns 70 IF=4mA, VDD=5V 140 0 4 5 6 7 8 9 10 11 12 IF - Forward Current - mA 13 14 Figure 10. ACFL-6212T (3V) Typical Propagation Delay vs Input Forward Current 15 Application Circuits V DD LOGIC I/O C IN RO INPUT RLIMIT 1 12 2 11 3 10 4 9 5 8 6 7 1F Bypass Capacitor V OUT2 TRUTH TABLE INPUT LED OUTPUT L ON L H OFF H INPUT LED OUTPUT L ON L H OFF H GND 2 GND 1 Figure 11. Recommended Application Circuit for ACFL-6211T High Speed Performance V DD 1 12 2 11 LOGIC I/O 3 RO INPUT 10 4 9 5 8 6 7 TRUTH TABLE 1F Bypass Capacitor V OUT2 1/2 RLIMIT 1/2 RLIMIT GND 1 Figure 12. Recommended Application Circuit for ACFL-6212T Low Power Performance 10 GND 2 Test Circuits V DD PULSE GENERATOR ZO = 50 tr = tf = 5ns INPUT MONITORING NODE 1 12 2 11 3 10 4 9 5 8 6 7 V MONITOR 1F Bypass Capacitor V MON 2 V MON 2 0 VO 80% V O CL * 0.8V tPHL V OL tPLH GND2 R MONITOR *CL IS APPROXIMATELY 15pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE GND1 Figure 13. Test circuit for tPHL, tPLH, tF, and tR. VDD R1=330 A VIN=4.5 to 5.5V B + - R2=330 1 12 2 11 3 10 4 9 5 8 6 7 + VCM - Figure 14. Test circuit for common mode transient immunity. 11 VCM 1uF BYPASS OUTPUT MONITORING NODE VOH VOL VCM (PEAK) = 1000V 0V Switch at B (LED=OFF) VDD -1V Switch at A (LED=ON) Thermal Resistance Measurement The diagram of ACFL-6211T/6212T for measurement is shown in Figure 15. This is a multi-chip package with four heat sources, the effect of heating of one die due to the adjacent dice are considered by applying the theory of linear superposition. Here, one die is heated first and the temperatures of all the dice are recorded after thermal equilibrium is reached. Then, the 2nd die is heated and all the dice temperatures are recorded and so on until the 4th die is heated. With the known ambient temperature, the die junction temperature and power dissipation, the thermal resistance can be calculated. The thermal resistance calculation can be cast in matrix form. This yields a 4 by 4 matrix for our case of two heat sources. R11 R12 R13 R14 P1 T1 R21 R22 R23 R24 P2 T2 R31 R32 R33 R34 R41 R42 R43 R44 * = 1 12 Die 1: IC1 Die 4: LED2 T3 2 T4 3 10 R11: Thermal Resistance of Die1 due to heating of Die1 (C/W) R12: Thermal Resistance of Die1 due to heating of Die2 (C/W) R13: Thermal Resistance of Die1 due to heating of Die3 (C/W) R14: Thermal Resistance of Die1 due to heating of Die4 (C/W) 4 9 P3 P4 R21: Thermal Resistance of Die2 due to heating of Die1 (C/W) R22: Thermal Resistance of Die2 due to heating of Die2 (C/W) R23: Thermal Resistance of Die2 due to heating of Die3 (C/W) R24: Thermal Resistance of Die2 due to heating of Die4 (C/W) R31: Thermal Resistance of Die3 due to heating of Die1 (C/W) R32: Thermal Resistance of Die3 due to heating of Die2 (C/W) R33: Thermal Resistance of Die3 due to heating of Die3 (C/W) R34: Thermal Resistance of Die3 due to heating of Die4 (C/W) R41: Thermal Resistance of Die4 due to heating of Die1 (C/W) R42: Thermal Resistance of Die4 due to heating of Die2 (C/W) R43: Thermal Resistance of Die4 due to heating of Die3 (C/W) R44: Thermal Resistance of Die4 due to heating of Die4 (C/W) P1: Power dissipation of Die1 (W) P2: Power dissipation of Die2 (W) P3: Power dissipation of Die3 (W) P4: Power dissipation of Die4 (W) T1: Junction temperature of Die1 due to heat from all dice (C) T2: Junction temperature of Die2 due to heat from all dice (C) T3: Junction temperature of Die3 due to heat from all dice (C) T4: Junction temperature of Die4 due to heat from all dice (C) Ta: Ambient temperature. T1: Temperature difference between Die1 junction and ambient (C) T2: Temperature deference between Die2 junction and ambient (C) T3: Temperature difference between Die3 junction and ambient (C) T4: Temperature deference between Die4 junction and ambient (C) T1 = (R11 x P1 + R12 x P2 + R13 x P3 + R14 x P4 ) + Ta T2 = (R21 x P1 + R22 x P2 + R23 x P3 + R24 x P4) + Ta T3 = (R31 x P1 + R32 x P2 + R33 x P3 + R34 x P4) + Ta T4= (R41 x P1 + R42 x P2 + R43 x P3 + R44 x P4 ) + Ta 12 -- (1) -- (2) -- (3) -- (4) 5 Die 2: LED1 6 Die 3: IC2 11 8 7 Figure 15. Diagram of ACFL-6211T/6212T for measurement Measurement data on a low K (conductivity) board: R11 = 181 C/W R21 = 103 C/W R31 = 82 C/W R41 = 110 C/W R12 = 91 C/W R22 = 232 C/W R32 = 97 C/W R42 = 86 C/W R13 = 85 C/W R23 = 109 C/W R33 = 180 C/W R43 = 101 C/W R14 = 112 C/W R24 = 91 C/W R34 = 91 C/W R44 = 277 C/W Measurement data on a high K (conductivity) board: R11 = 117 C/W R21 = 37 C/W R31 = 35 C/W R41 = 47 C/W R12 = 42 C/W R22 = 161 C/W R32 = 53C/W R42 = 30 C/W R13 = 32 C/W R23 = 39 C/W R33 = 114 C/W R43 = 29 C/W R14 = 60 C/W R24 = 33 C/W R34 = 34 C/W R44 = 189 C/W For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright (c) 2005-2015 Avago Technologies. All rights reserved. AV02-4835EN - August 3, 2015 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Avago Technologies: ACFL-6211T-560E ACFL-6212T-500E ACFL-6212T-560E ACFL-6212T-060E ACFL-6211T-000E ACFL-6211T060E ACFL-6211T-500E ACFL-6212T-000E