ACFL-6211T, ACFL-6212T
Automotive High Speed, Low Power Digital Optocoupler with R2CouplerTM
Isolation in a Stretched 12-Pin Surface Mount Plastic Package
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD. The components
featured in this datasheet are not to be used in military or aerospace applications or environments.
Description
The ACFL-6211T and ACFL-6212T are automotive grade
dual channel, bi-directional, high speed digital CMOS op-
tocouplers. The stretched SO-12 stretched package out-
line is designed to be compatible with standard surface
mount processes and occupies the same land area as their
single channel equivalent, ACPL-K71T and ACPL-K72T, in
stretched SO8 package.
This digital optocoupler uses an insulating layer between
the light emitting diode and an integrated photo detector
to provide electrical insulation between input and out-
put. Each channel of the digital optocoupler has a CMOS
detector IC with an integrated photodiode, a high speed
trans-impedance amplier, and a voltage comparator
with an output driver. Each channel is also isolated from
the other.
Avago R2Coupler technology provides reinforced insula-
tion and reliability that delivers safe signal isolation criti-
cal in automotive and high temperature industrial appli-
cations.
Functional Diagram
Features
• Qualied to AEC Q100 Grade 1 Test Guidelines
• Automotive Wide Temperature Range: –40°C to +125°C
• 5 V CMOS compatibility
• 40 kV/µs Common-Mode Rejection at VCM=1000V (typ)
• Low Propagation Delay :
• ACFL-6211T: 25ns @ IF = 10mA (typ)
• ACFL-6212T: 60ns @ IF = 4mA (typ)
• Compact, Auto-Insertable Stretched SO12 Packages
• Worldwide Safety Approval:
- UL 1577 recognized, 5kVRMS/1 min.
- CSA Approved
- IEC/EN/DIN EN 60747-5-5
Applications
• Automotive IPM Driver for DC-DC converters and
motor inverters
• CANBus and SPI Communications Interface
• High Temperature Digital/Analog Signal Isolation
• Power Transistor Isolation
Truth Table
LED VO
ON LOW
OFF HIGH
Note: The connection of a 1 μF bypass capacitor between pins 1 and 3
and pins 8 and 10 is recommended.
1
2
3
4
5
6
12
11
10
9
8
7
VDD1
VOUT1
GND1
AN2
CA2
CA2
VDD2
VOUT2
GND 2
AN1
CA1
GND 2
2
Pin Description
Pin No. Pin Name Description Pin No. Pin Name Description
1 VDD1 Primary Side Power Supply 7 GND2 Secondary Side Ground
2 VOUT1 Output 1 8 GND2 Secondary Side Ground
3 GND1 Primary Side Ground 9 VOUT2 Output 2
4 AN2 Anode 2 10 VDD2 Secondary Side Power Supply
5 CA2 Cathode 2 11 AN1 Anode 1
6 CA2 Cathode 2 12 CA1 Cathode 1
Ordering Information
Part number
Option
(RoHS Compliant) Package
Surface
Mount
Tape
& Reel
UL 5000 Vrms/
1 Minute rating
IEC/EN/DIN
EN 60747-5-5 Quantity
ACFL-6211T -000E Stretched
SO-12
X X 80 per tube
-060E X X X 80 per tube
-500E X X X 1000 per reel
-560E X X X X 1000 per reel
ACFL-6212T -000E Stretched
SO-12
X X 80 per tube
-060E X X X 80 per tube
-500E X X X 1000 per reel
-560E X X X X 1000 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACFL-6212T-560E to order product of SSO-12 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN
60747-5-5 Safety Approval in RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
3
Package Outline Drawing
12-Lead Surface Mount
Dimensions in inches (millimeters)
Lead coplanarity = 0.004 inches (0.1mm)
Recommended Pb-Free IR Prole
Recommended reow condition as per JEDEC Standard, J-STD-020 (latest revision).
Note: Non-halide ux should be used
LAND PATTERN RECOMMENDATION
0.080 (2.030)
0.458 (11.630)
0.020 (0.500)
0.015
(0.381)
0.125 ± 0.005
(3.180 ± 0.127)
7°
0.015
(0.381)
0.032
(0.800)
1 2 3 4 5 6
12 11 10 9 8 7
621xT
YYWW
EE
0.230
( 5.842
0.295
( 7.493
TYPE NUMBER
DATECODE
EXTENDED
DATECODE FOR
LOT TRACKING
+ 0.005
− 0
+ 0.127
− 0 )
+ 0.005
− 0
+ 0.127
− 0 )
45°
0.326 ± 0.010
(8.284 ± 0.254)
0.029 ± 0.004
(0.731 ± 0.100)
0.408 ± 0.010
(10.363 ± 0.250)
0.010 ± 0.002
(0.254 ± 0.050)
7°
0.008 ± 0.004
(0.200 ± 0.100)
0.063 ± 0.005
(1.590 ± 0.127)
RoHS-COMPLIANCE
INDICATOR
0° to 7°
4
Regulatory Information
The ACFL-6211T and ACFL-6212T are approved by the following organizations:
UL UL 1577, component recognition program up to VISO = 5kVRMS
CSA Approved under CSA Component Acceptance Notice #5
IEC/EN/DIN EN 60747-5-5 Approved under IEC/EN/DIN EN 60747-5-5
Insulation and Safety Related Specications
Parameter Symbol
ACFL-6211T /
ACFL-6212T Units Conditions
Minimum External Air Gap
(Clearance)
L(101) 8.3 mm Measured from input terminals to output terminals,
shortest distance through air.
Minimum External Tracking
(Creepage)
L(102) 8.5 mm Measured from input terminals to output terminals,
shortest distance path along body.
Minimum Internal Plastic Gap
(Internal Clearance)
0.08 mm Through insulation distance conductor to conductor,
usually the straight line distance thickness between the
emitter and detector.
Tracking Resistance
(Comparative Tracking Index)
CTI 175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group (DIN VDE0109) IIIa Material Group (DIN VDE 0109)
IEC / EN / DIN EN 60747-5-5 Insulation Related Characteristic (Option 060E and 560E)
Description Symbol Characteristic Units
Installation classication per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 600 V rms
for rated mains voltage < 1000 V rms
I-III
I-III
Climatic Classication 40/125/21
Pollution Degree (DIN VDE 0110/1.89) 2
Maximum Working Insulation Voltage VIORM 1140 VPEAK
Input to Output Test Voltage, Method b
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC
VPR 2137 VPEAK
Input to Output Test Voltage, Method a
VIORM x 1.6 = VPR, Type and sample test, tm = 10 sec, Partial Discharge < 5 pC
VPR 1824 VPEAK
Highest Allowable Overvoltage (Transient Overvoltage, tini = 60 sec) VIOTM 6000 VPEAK
Safety Limiting Values (Maximum values allowed in the event of a failure)
Case Temperature
Input Current
Output Power
TS
IS,INPUT
PS,OUTPUT
175
230
600
°C
mA
mW
Insulation Resistance at TS, VIO = 500 V RS109W
5
Absolute Maximum Ratings
Parameter Symbol Min. Max. Units Condition
Storage Temperature TS–55 +150 °C
Ambient Operating Temperature [1] TA–40 +125 °C
Junction Temperature TJ+150 °C
Supply Voltages VDD 0 6.5 V
Output Voltage VO–0.5 VDD +0.5 V
Average Forward Input Current IF- 20.0 mA
Peak Transient Input Current
(IF at 1us pulse width, <10% duty cycle)
IF( TRAN) 1
80
A
mA
≤1us Pulse Width, 300pps
≤1us Pulse Width, <10%Duty Cycle
Reverse Input Voltage Vr- 5 V
Input Power Dissipation PI40 mW
Average Output Current Io 10 mA
Output Power Dissipation Po 30 mW
Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane
Solder Reow Temperature Prole See Solder Reow Temperature Prole Section
Recommended Operating Conditions
Parameter Symbol Min. Max. Units Note
Supply Voltage VDD 3.0 5.5 V
Operating Temperature TA-40 125 °C
Forward Input Current IF(ON) 4.0 15 mA
Forward O State Voltage VF(OFF) 0.8 V
Input Threshold Current ITH 3.5 mA
Electrical Specications
Over recommended operating conditions. All typical specications are at TA=25°C, VDD= 5V.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig
LED Forward Voltage VF1.45 1.5 1.75 V IF = 10mA, TA = 25°C
1.25 1.5 1.85 V IF = 10mA
VF Temperature Coecient -1.5 mV/°C
Input Threshold Current ITH 1.3 3.5 mA 2
Input Capacitance CIN 90 pF
Input Reverse Breakdown Voltage BVR5.0 V IR = 10 µA
Logic High Output Voltage VOH VDD-0.6 V IOH = -3.2mA 4
Logic Low Output Voltage VOL 0.6 V IOL = 4mA 3
Logic Low Output Supply
Current (per channel)
IDDL 0.9 1.5 mA
Logic High Output Supply
Current (per channel)
IDDH 0.9 1.5 mA
6
ACFL-6211T High Speed Mode Switching Specications
Over recommended operating conditions: TA = –40°C to +125°C, 4.5 V ≤ VDD ≤ 5.5 V. All typical specications are at
TA=25°C, VDD = 5V.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig Note
Propagation Delay Time
to Logic Low Output
tPHL 25 35 ns Vin = 4.5V-5.5V,
Rin = 390W+/-5%,
Cin = 100pF, CL = 15pF
Output low threshold =
0.8V
Output high threshold =
80% of Vdd
5, 9,
11
1, 2,
3
Propagation Delay Time
to Logic High Output
tPLH 25 35 ns
Pulse Width Distortion PWD 0 12 ns
Propagation Delay Skew tPSK 15 ns
Output Rise Time
(10% – 90%)
tR10 ns
Output Fall Time
(90% - 10%)
tF10 ns
Common Mode Transient
Immunity at Logic High
Output
| CMH | 15 25 kV/µs Vin = 0V Rin = 390W ± 5%,
Cin = 100pF, Vcm = 1000V,
TA = 25°C
4
Common Mode Transient
Immunity at Logic High
Output
| CML | 15 25 kV/µs Vin = 4.5V-5.5V ,
Rin = 390W ± 5%,
Cin = 100pF, Vcm = 1000V,
TA = 25°C
5
ACFL-6212T Low Power Mode Switching Specications
Over recommended operating conditions: TA = –40°C to +125°C, 3.0 V ≤ VDD ≤ 5.5 V All typical specications at 25°C and
VDD = 5V.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig Note
Propagation Delay Time
to Logic Low Output
tPHL 60 100 ns IF = 4mA, CL= 15pF 7, 12 1, 2,
3
Propagation Delay Time
to Logic High Output
tPLH 35 100 ns
Pulse Width Distortion PWD 25 50 ns
Propagation Delay Skew tPSK 60 ns
Output Rise Time (10% – 90%) tR10 ns
Output Fall Time (90% - 10%) tF10 ns
Common Mode Transient
Immunity at Logic High
Output
| CMH | 25 40 kV/µs Using Avago LED Driving
Circuit, VIN = 0V,
R1 = 330W ± 5%,
R2 = 330W ± 5%,
VCM = 1000V, TA = 25°C
4
Common Mode Transient
Immunity at Logic Low
Output
| CML | 25 40 kV/µs Using Avago LED Driving
Circuit, VIN=4.5-5.5V,
R1 = 330W ± 5%,
R2 = 330W ± 5%,
VCM = 1000V, TA = 25°C
5
7
Package Characteristics
All Typical at TA = 25°C.
Parameter Symbol Min. Typ. Max. Units Test Conditions Notes
Input-Output Momentary
Withstand Voltage
VISO 5000 Vrms RH ≤ 50%, t = 1 min.
TA = 25°C
6, 7
Input-Output Resistance RI-O 1014 WVI-O = 500 V dc 6
Input-Output Capacitance CI-O 0.6 pF f = 1 MHz, TA = 25°C 6
Notes:
1. tPHL propagation delay is measured from the 50% (VIN or IF) on the rising edge of the input pulse to the 0.8V of VDD of the falling edge of the VO
signal. tPLH propagation delay is measured from the 50% (VIN or IF) on the falling edge of the input pulse to the 80% level of the rising edge of the
VO signal.
2. PWD is dened as |tPHL - tPLH|.
3. tPSK is equal to the magnitude of the worst case dierence in tPHL and/or tPLH that will be seen between units at any given temperature within the
recommended operating conditions.
4. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.
5. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
6. Device considered a two terminal device: pins 1 to 6 shorted together, and pins 7 to 12 shorted together.
7. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage > 6000VRMS for 1 second.
8
Typical Performance Plots
0.01
0.10
1.00
10.00
100.00
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
IF - Input Forward Current - mA
Forward Voltage
Temp=-40°C
Temp=25°C
Temp=125°C
0
1
2
3
4
5
0.0 0.5 1.0 1.5 2.0
VO - Output Voltage - V
IF - Input Forward Current - mA
Temp=-40°C
Temp=25°C
Temp=125°C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0 2 4 6 8 10
VOL - Logic Low Output Voltage - V
IOL - Logic Low Output Current - mA
4.0
4.2
4.4
4.6
4.8
5.0
-10-8-6-4-20
VOH - Logic High Output Voltage - V
IOH - Logic High Output Current - mA
-10
0
10
20
30
40
50
60
-40 -20 0 20 40 60 80 100 120 140
TP - Propogation Delay - ns
TA - Temperature - °C
TPLH
TPHL
PWD
-5
0
5
10
15
20
25
30
35
4 5 6 7 8 9 10 11 12 13 14 15
TP - Propogation Delay - ns
IF - Forward Current - mA
TPLH
TPHL
PWD
Figure 1. Typical Diode Input Forward Current Characteristic Figure 2. Typical Output Voltage vs Input Forward Current
Figure 3 Typical Logic Low Output Voltage vs Logic Low Output Current Figure 4. Typical Logic High Output Voltage vs Logic High Output Current
Figure 5. ACFL-6211T (High Speed) Typical Propagation Delay vs
Temperature, VIN=4.5V, RIN=390W, CIN=100pF
Figure 6. ACFL-6211T (High Speed) Typical Propagation Delay vs Input
Forward Current, VIN=4.5V, RIN=390W, CIN=100pF, TA=25°C
9
0
10
20
30
40
50
60
70
-40 -20 0 20 40 60 80 100 120 140
TP - Propogation Delay - ns
TA - Temperature - °C
TPLH
TPHL
PWD 0
10
20
30
40
50
60
70
4 5 6 7 8 9 10 11 12 13 14 15
TP - Propogation Delay - ns
IF - Forward Current - mA
TPLH
TPHL
PWD
0
10
20
30
40
50
60
70
-40 -20 0 20 40 60 80 100 120 140
TP - Propogation Delay - ns
TA - Temperature - °C
TPLH
TPHL
PWD
0
10
20
30
40
50
60
70
4 5 6 7 8 9 10 11 12 13 14 15
TP - Propogation Delay - ns
IF - Forward Current - mA
TPLH
TPHL
PWD
IF=4mA, VDD=5V VDD=5V, TA=25°C
IF=4mA, VDD=3V VDD=3V, TA=25°C
Figure 7. ACFL-6212T (5V) Typical Propagation Delay vs Temperature Figure 8. ACFL-6212T (5V) Typical Propagation Delay vs Input Forward
Current
Figure 9. ACFL-6212T (3V) Typical Propagation Delay vs Temperature Figure 10. ACFL-6212T (3V) Typical Propagation Delay vs Input Forward
Current
10
Application Circuits
1µF Bypass
Capacitor
GND1GND 2
INPUT
RO
LOGIC I/O
½ RLIMIT
1
2
3
4
5
6
12
11
10
9
8
7
VOUT2
½ RLIMIT
VDD
1µF Bypass
Capacitor
GND1GND 2
INPUT
RO
LOGIC I/O CIN
RLIMIT
1
2
3
4
5
6
12
11
10
9
8
7
VOUT2
VDD
Figure 11. Recommended Application Circuit for ACFL-6211T High Speed Performance
Figure 12. Recommended Application Circuit for ACFL-6212T Low Power Performance
TRUTH TABLE
INPUT LED OUTPUT
L ON L
H OFF H
TRUTH TABLE
INPUT LED OUTPUT
L ON L
H OFF H
11
Test Circuits
VMONITOR VMON
2
VMON
2
0
VO
80% VO
VOL
0.8V
tPHL tPLH
PULSE
GENERATOR
ZO = 50Ω
tr = tf = 5ns
INPUT
MONITORING
NODE
RMONITOR
VDD
1µF Bypass
Capacitor
CL*
*CL IS APPROXIMATELY 15pF WHICH
INCLUDES PROBE AND STRAY WIRING
CAPACITANCE
GND1
GND2
1
2
3
4
5
6
12
11
10
9
8
7
OUTPUT
MONITORING
NODE
VDD
1uF
BYPASS
B
A
R1=330Ω
VCM
1
2
3
4
5
6
12
11
10
9
8
7
VIN=4.5
to 5.5V R2=330Ω
VCM VCM (PEAK) = 1000V
0V
VOH VDD –1V
VOL
Switch at B (LED=OFF)
Switch at A (LED=ON)
−
+
−+
Figure 13. Test circuit for tPHL, tPLH, tF, and tR.
Figure 14. Test circuit for common mode transient immunity.
12
Thermal Resistance Measurement
The diagram of ACFL-6211T/6212T for measurement is shown in Figure 15. This is a multi-chip package with four heat
sources, the eect of heating of one die due to the adjacent dice are considered by applying the theory of linear su-
perposition. Here, one die is heated rst and the temperatures of all the dice are recorded after thermal equilibrium is
reached. Then, the 2nd die is heated and all the dice temperatures are recorded and so on until the 4th die is heated.
With the known ambient temperature, the die junction temperature and power dissipation, the thermal resistance can
be calculated. The thermal resistance calculation can be cast in matrix form. This yields a 4 by 4 matrix for our case of
two heat sources.
Figure 15. Diagram of ACFL-6211T/6212T for measurement
R11: Thermal Resistance of Die1 due to heating of Die1 (˚C/W)
R12: Thermal Resistance of Die1 due to heating of Die2 (˚C/W)
R13: Thermal Resistance of Die1 due to heating of Die3 (˚C/W)
R14: Thermal Resistance of Die1 due to heating of Die4 (˚C/W)
R21: Thermal Resistance of Die2 due to heating of Die1 (˚C/W)
R22: Thermal Resistance of Die2 due to heating of Die2 (˚C/W)
R23: Thermal Resistance of Die2 due to heating of Die3 (˚C/W)
R24: Thermal Resistance of Die2 due to heating of Die4 (˚C/W)
R31: Thermal Resistance of Die3 due to heating of Die1 (˚C/W)
R32: Thermal Resistance of Die3 due to heating of Die2 (˚C/W)
R33: Thermal Resistance of Die3 due to heating of Die3 (˚C/W)
R34: Thermal Resistance of Die3 due to heating of Die4 (˚C/W)
R41: Thermal Resistance of Die4 due to heating of Die1 (˚C/W)
R42: Thermal Resistance of Die4 due to heating of Die2 (˚C/W)
R43: Thermal Resistance of Die4 due to heating of Die3 (˚C/W)
R44: Thermal Resistance of Die4 due to heating of Die4 (˚C/W)
P1: Power dissipation of Die1 (W)
P2: Power dissipation of Die2 (W)
P3: Power dissipation of Die3 (W)
P4: Power dissipation of Die4 (W)
T1: Junction temperature of Die1 due to heat from all dice (°C)
T2: Junction temperature of Die2 due to heat from all dice (°C)
T3: Junction temperature of Die3 due to heat from all dice (°C)
T4: Junction temperature of Die4 due to heat from all dice (°C)
Ta: Ambient temperature.
∆T1: Temperature dierence between Die1 junction and ambient (°C)
∆T2: Temperature deference between Die2 junction and ambient (°C)
∆T3: Temperature dierence between Die3 junction and ambient (°C)
∆T4: Temperature deference between Die4 junction and ambient (°C)
T1 = (R11 x P1 + R12 x P2 + R13 x P3 + R14 x P4 ) + Ta -- (1)
T2 = (R21 x P1 + R22 x P2 + R23 x P3 + R24 x P4) + Ta -- (2)
T3 = (R31 x P1 + R32 x P2 + R33 x P3 + R34 x P4) + Ta -- (3)
T4= (R41 x P1 + R42 x P2 + R43 x P3 + R44 x P4 ) + Ta -- (4)
Measurement data on a low K (conductivity) board:
R11 = 181 °C/W
R21 = 103 °C/W
R31 = 82 °C/W
R41 = 110 °C/W
R12 = 91 °C/W
R22 = 232 °C/W
R32 = 97 °C/W
R42 = 86 °C/W
R13 = 85 °C/W
R23 = 109 °C/W
R33 = 180 °C/W
R43 = 101 °C/W
R14 = 112 °C/W
R24 = 91 °C/W
R34 = 91 °C/W
R44 = 277 °C/W
Measurement data on a high K (conductivity) board:
R11 = 117 °C/W
R21 = 37 °C/W
R31 = 35 °C/W
R41 = 47 °C/W
R12 = 42 °C/W
R22 = 161 °C/W
R32 = 53°C/W
R42 = 30 °C/W
R13 = 32 °C/W
R23 = 39 °C/W
R33 = 114 °C/W
R43 = 29 °C/W
R14 = 60 °C/W
R24 = 33 °C/W
R34 = 34 °C/W
R44 = 189 °C/W
1
2
3
4
5
6
12
11
10
9
8
7
Die 1:
IC1
Die 4:
LED2
Die 2:
LED1
Die 3:
IC2
R11 R12 R13 R14
•
P1
=
∆T1
R21 R22 R23 R24 P2 ∆T2
R31 R32 R33 R34 P3 ∆T3
R41 R42 R43 R44 P4 ∆T4
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2015 Avago Technologies. All rights reserved.
AV02-4835EN - August 3, 2015
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Avago Technologies:
ACFL-6211T-560E ACFL-6212T-500E ACFL-6212T-560E ACFL-6212T-060E ACFL-6211T-000E ACFL-6211T-
060E ACFL-6211T-500E ACFL-6212T-000E