Serial ATA Flash Drive
APS1845xxxx-ACMX
9
©2012 Apacer Technology Inc. Rev. 1.3
3. Flash Management
3.1 Error Correction/Detection
SAFD18S4-M implements a hardware ECC scheme, based on the BCH algorithm. It can detect and correct up
to 16 bits or 24 bits error in 1K bytes.
3.2 Bad Block Management
Although bad blocks on the flash media are already identified by the flash manufacturer, they can also be
accumulated over time during operation. SAFD18S4-M’s controller maintains a table that lists those normal
blocks with disk data, the free blocks for wear leveling, and bad blocks with errors. When a normal block is
detected broken, it is replaced with a free block and listed as a bad block. When a free block is detected broken,
it is then removed from the free block list and marked as a bad block.
During device operation, this ensures that newly accumulated bad blocks are transparent to the host. The
device will stop file write service once there are only two free blocks left such that the read function is still
available for copying the files from the disk into another.
3.3 Wear Leveling
The NAND flash devices are limited by a certain number of write cycles. When using a FAT-based file system,
frequent FAT table updates are required. If some area on the flash wears out faster than others, it would
significantly reduce the lifetime of the whole SSD, even if the erase counts of others are far from the write cycle
limit. Thus, if the write cycles can be distributed evenly across the media, the lifetime of the media can be
prolonged significantly. This scheme is called wear leveling.
Apacer’s wear-leveling scheme is achieved both via buffer management and Apacer-specific static wear
leveling. They both ensure that the lifetime of the flash media can be increased, and the disk access
performance is optimized as well.
3.4 Power Failure Management
Power Failure Recovery ensures data transmission when experiencing unstable power supply. When power
disruption takes places, NAND Flash will have to cache multiple write-to-flash cycles to securely store data.
This urgent operation requires about several milliseconds to get it done. When the supplied voltage is below a
certain percentage of the required, the flash controller will be signaled by a detector IC component with low
power detection signal and then the firmware will communicate the controller to flush all the data into the cache
of Flash storage area. This can prevent incomplete data transmission.
The crucial part lies in the strength of the capacitor of the SSD. The capacitor must be able to hold up some
milliseconds of remaining time before the power is totally out, for the urgent write-back-into-flash operations to
complete.
3.5 ATA Secure Erase
Accomplished by the Secure Erase (SE) command, which added to the open ANSI standards that control disk
drives, “ATA Secure Erase” is built into the disk drive itself and thus far less susceptible to malicious software
attacks than external software utilities. It is a positive easy-to-use data destroy command, amounting to
electronic data shredding. Executing the command causes a drive to internally completely erase all possible
user data. This command is carried out within disk drives, so no additional software is required. Once executed,
neither data nor the erase counter on the device would be recoverable, which blurs the accuracy of device