SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
Typical Size
(6,4 mm X 9,7 mm )
FEATURES
DTracks Externally Applied Reference Voltage
D30-mΩ, 12-A Peak MOSFET Switches for High
Efficiency at 6-A Continuous Output Source
or Sink Current
D6% to 90% VIN Output Tracking Range
DPWM Frequency Range:
Fixed 350 kHz or Adjustable 280 to 700 kHz
DLoad Protected by Peak Current Limit and
Thermal Shutdown
DIntegrated Solution Reduces Board Area and
Component Count
APPLICATIONS
DDDR Memory Termination Voltage
DActive Termination of GTL and STL
High-Speed Logic Families
DDAC Controlled High Current Output Stage
DPrecision Point of Load Power Supply
DESCRIPTION
As a member of the SWIFT family of dc/dc regulators, the
TPS54672 active bus termination synchronous PWM
converter integrates all required active components.
Included on the substrate with the listed features are a true,
high performance, voltage error amplifier that enables
maximum performance and flexibility in choosing the
output filter L and C components; an under-voltage-
lockout circuit to prevent start-up until the input voltage
reaches 3 V; a slow-start control to limit in-rush currents;
and a status output to indicate valid operating conditions.
The TPS54672 is available in a thermally enhanced 28-pin
TSSOP (PWP) PowerPAD package, which eliminates
bulky heatsinks. TI provides evaluation modules and the
SWIFT designer software tool to aid in quickly achieving
high-performance power supply designs to meet
aggressive equipment development cycles.
SIMPLIFIED SCHEMATIC
VIN PH
CBOOT COUT
BOOT
PGND
VSENSE
0.56 µHVTTQ
COMPAGND
VBIAS
CBIAS
CIN
CIN
Input Voltage
3 V − 6 V
TPS54672
Typical DDR Memory Termination Regulator Circuit
REFIN
VDDQ
ENA
LOAD TRANSIENT RESPONSE
10 µs/div
Output Voltage
(50 mV/div AC Coupled)
Output Current
(2A/div)
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
www.ti.com
Copyright 2001−2005, Texas Instruments Incorporated
PowerPAD and SWIFT are trademarks of Texas Instruments.
SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
www.ti.com
2
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TAREFIN V O LTAGE PACKAGE PART NUMBER
−40°C to 85°C0.2 V to 1.75 V Plastic HTSSOP (PWP)(1) TPS54672PWP
(1) The PWP package is also available taped and reeled. Add an R suf fix to the device type (i.e., TPS54672PWPR). See the application section
of the data sheet for PowerPAD drawing and layout information.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website
at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over o p e r ating free-air temperature range unless otherwise noted(1)
TPS54672
VIN, ENA −0.3 V to 7 V
Input voltage range, VI
RT −0.3 V to 6 V
Input voltage range, V
IVSENSE, REFIN −0.3 V to 4 V
BOOT −0.3 V to 17 V
Output voltage range, VO
VBIAS, COMP, STATUS −0.3 V to 7 V
Output voltage range, V
OPH −0.3 V to 10 V
Source current, IO
PH Internally Limited
Source current, I
OCOMP, VBIAS 6 mA
PH 12 A
Sink current, I
S
COMP 6 mA
Sink current, IS
STATUS 10 mA
Voltage differential, AGND to PGND ±0.6 V
Operating virtual junction temperature range, TJ−40°C to 125°C
Storage temperature, Tstg −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS(1)(2)
PACKAGE THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT TA =25°C
POWER RATING TA = 70°C
POWER RATING TA = 85°C
POWER RATING
28 Pin PWP with solder 18.2 °C/W 5.49 W(3) 3.02 W 2.20 W
28 Pin PWP without solder 40.5 °C/W 2.48 W 1.36 W 0.99 W
(1) For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
(2) Test board conditions:
1. 3” x 3”, 4 layers, thickness: 0.062”
2. 1.5 oz. copper traces located on the top of the PCB
3. 1.5 oz. copper ground plane on the bottom of the PCB
4. 0.5 oz. copper ground planes on the 2 internal layers
5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet)
(3) Maximum power dissipation may be limited by over current protection.
ADDITIONAL 6A SWIFT DEVICES, (REFER TO SLVS398 AND SLVS400)
DEVICE OUTPUT V O LTAGE DEVICE OUTPUT VOLTAGE DEVICE OUTPUT VOLTAGE
TPS54611 0.9 V TPS54614 1.8 V TPS54610 Adjustable
TPS54612 1.2 V TPS54615 2.5 V TPS54673 Disabled sink during
startup
TPS54613 1.5 V TPS54616 3.3 V TPS54680 Sequencing
SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
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3
ELECTRICAL CHARACTERISTICS
TJ = –40°C to +125°C, VI = 3 V to 6 V over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE, VIN
Input voltage range, VIN 3.0 6.0 V
VID Dif ferential voltage, AGND to PGND −0.30 0.30 V
Switching freq. = 350 kHz, RT open 10 16
I
(Q)
Quiescent current Switching freq. = 500 kHz, RT = 100 kΩ16 24 mA
I(Q)
Quiescent current
Shutdown, SS/ENA = 0 V 1 1.4
mA
UNDERVOLTAGE LOCKOUT
Start threshold voltage, UVLO 2.95 3.00 V
Stop threshold voltage, UVLO 2.70 2.80 V
Hysteresis voltage, UVLO 0.14 0.16 V
Rising and falling edge deglitch, UVLO(1) 2.5 µs
BIAS VOLTAGE
Output voltage, VBIAS I(VBIAS) = 0 2.70 2.80 2.90 V
Output current, VBIAS (2) 100 µA
CUMULATIVE REFERENCE
Cumulative regulation accuracy (relative to
REFIN)
IO = − 6A to 6A,
Switching frequency = 350 kHz,
REFIN = 1.25 V(1) −1.5% 1.5%
OSCILLATOR
Internally set—free running frequency RT open 280 350 420 kHz
Externally set—free running frequency range RT = 68 kΩ to 180 kΩ280 700 kHz
Externally set—free running frequency
accuracy RT = 100 kΩ (1% resistor to AGND) 460 500 540 kHz
Ramp valley 0.75 V
Ramp amplitude (peak-to-peak) 1 V
Minimum controllable on time(1) 200 ns
Maximum duty cycle (1) 90%
Error amplifier open loop voltage gain 1 kΩ COMP to AGND (1) 90 110 dB
Error amplifier unity gain bandwidth Parallel 10 kΩ, 160 pF COMP to AGND (1) 3 5 MHz
Error amplifier common mode input voltage
range(1) 0 2.85 V
Error amplifier common mode rejection ratio(1) 65 dB
Input bias current, VSENSE VSENSE = REFIN = 1 V 60 250 nA
Input bias current, REFIN VSENSE = REFIN = 1.25 V 60 250 nA
Input of fset voltage, REFIN VSENSE = REFIN = 1.25 V −1.5 1.5 mV
Input voltage range, REFIN(1) 0 1.8 V
Output voltage slew rate (symmetric), COMP 1 1.4 V/µs
Common mode output voltage range, COMP
IO = 3 mA 2.65
V
Common mode output voltage range, COMP
IO = −3 mA 0.2
V
PWM comparator propagation delay time,
PWM comparator input to PH pin (excluding
deadtime) 10-mV overdrive (1) 70 85 ns
Enable threshold voltage, ENA 0.82 1.20 1.40 V
Enable hysteresis voltage, ENA (1) 0.03 V
Falling edge deglitch, ENA (1) 2.5 µs
Leakage current, ENA VI= 5.5 V 1µA
(1) Ensured by design
(2) Static resistive loads only
SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
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4
ELECTRICAL CHARACTERISTICS Continued
TJ = –40°C to +125°C, VI = 3 V to 6 V over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OSCILLATOR (CONTINUED)
Output saturation voltage, STATUS I(sink) = 2.5 mA 0.18 0.3 V
Leakage current, STATUS VI = 5.5 V 1µA
Current limit trip point
VIN = 3 V (1) 7 10
A
Current limit trip point
VIN = 6 V (1) 10 12
A
Current limit leading edge blanking time 100 ns
Current limit total response time 200 ns
Thermal shutdown trip point (1) 135 150 165 °C
Thermal shutdown hysteresis (1) 10 °C
rDS(on)
Low/high-side N-MOSFET
IO = 6A, VI = 3 V (3) 36 65
mΩ
r
DS(on
)
Low/high-side N-MOSFET
IO = 6A, VI = 6 V (3) 26 47
m
Ω
(1) Ensured by design
(2) Static resistive loads only
(3) Matched MOSFETs, low side rDS(on) production tested, high side rDS(on) ensured by design
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AGND
VSENSE
COMP
STATUS
BOOT
PH
PH
PH
PH
PH
PH
PH
PH
PH
RT
ENA
REFIN
VBIAS
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
PGND
PWP PACKAGE
(TOP VIEW)
THERMAL
PAD
SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
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5
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME NO.
DESCRIPTION
AGND 1 Analog ground. Return for compensation network/output divider, VBIAS capacitor, and R T resistor. Connect PowerPAD to
AGND.
BOOT 5 Bootstrap output. 0.022 µF to 0.1 µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver .
COMP 3 Error amplifier output. Connect frequency compensation network from COMP to VSENSE
ENA 27 Enable input. Logic high enables oscillator, PWM control and MOSFET driver circuits. Logic low disables operation and
places device in low quiescent current state.
PGND 15−19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to
the input and output supply returns, and negative terminals of the input and output capacitors. A single point connection to
AGND is recommended.
PH 6−14 Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
REFIN 26 External reference input. High impedance input to slow-start and error amplifier circuits.
RT 28 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency.
STATUS 4 Open drain output. Asserted low when VIN < UVLO threshold, VBIAS and internal reference are not settled or thermal
shutdown active. Otherwise STATUS is high.
VBIAS 25 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a
high-quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
VIN 20−24 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device
package with a high-quality, low-ESR 10-µF ceramic capacitor.
VSENSE 2 Error amplifier inverting input. Connect to output voltage through compensation network/output divider.
SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
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6
INTERNAL BLOCK DIAGRAM
Falling
Edge
Deglitch
Enable
Comparator
1.2 V
2.95 V
Hysteresis: 0.03
V2.5 µs
Falling
and
Rising
Edge
Deglitch
2.5 µs
VIN UVLO
Comparator
Hysteresis: 0.16
V
Slow-start
(0.25 V/ms minimum) −
+
Error
Amplifier
Thermal
Shutdown
150°C
SHUTDOWN
SS_DIS
PWM
Comparator
OSC
Leading
Edge
Blanking
100 ns
RQ
S
Adaptive Dead-Time
and
Control Logic
SHUTDOWN
30 mΩ
VIN
REG
VBIAS
VIN
BOOT
VIN
PH LOUT
CO
PGND
STATUS
AGND VBIAS
ILIM
Comparator VIN
Vtt
RTCOMPVSENSE
ENA
TPS54672
30 mΩ
SS_DIS
REFIN
VDDQ
RELATED DC/DC PRODUCTS
DTPS54372
DTPS54972
DTPS54872
SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
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7
TYPICAL CHARACTERISTICS
Figure 1
0
10
20
30
40
50
60
−40 0 25 85 125
VIN = 3.3 V IO = 6 A
IO = 3 A
Drain Source On-State Resistance − m
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
Ω
TJ − Junction Temperature − °CFigure 2
0
10
20
30
40
50
60
−40 0 25 85 125
VIN = 5 V
IO = 6 A
IO = 3 A
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
JUNCT I O N T E M P E R ATURE
TJ − Junction Temperature − °C
Drain Source On-State Resistance − m Ω
Figure 3
250
300
350
400
450
−40 0 25 85 125
TJ − Junction Temperature − °C
f − Internally Set Oscillator Frequency − kHz
INTERNALLY SET OSCILLATOR
FREQUENCY
vs
JUNCTION TEMPERATURE
Figure 4
200
300
400
500
600
700
800
−40 0 25 85 125
TJ − Junction Temperature − °C
f − Externally Set Oscillator Frequency − kHz
EXTERNALLY SET OSCILLATOR
FREQUENCY
vs
JUNCTION TEMPERATURE
Figure 5
1.240
1.245
1.250
1.255
1.260
0123456
TA = 85°C
REFIN = 1.25 V
IO − Output Current − A
− Output Voltage Regulation − V
OUTPUT VOLTAGE REGULATION
vs
OUTPUT CURRENT
VO
Figure 6
1.247
1.248
1.249
1.251
1.252
1.253
3 3.5 4 4.5 5 5.5 6
TA = 85°C
REFIN = 1.25 V,
IO = 3 A
IO − Input Voltage − V
OUTPUT VOLTAGE REGULATION
vs
INPUT VOLTAGE
1.250
− Output Voltage Regulation − V
VO
Figure 7
−20
0
20
40
60
80
100
120
140
1 100 1 k 1 M −200
−180
−160
−140
−120
−100
−80
−60
−40
−20
0
10 10 k 100 k 10 M
f − Frequency − Hz
Gain − dB
ERROR AMPLIFIER OPEN LOOP RESPONSE
Phase − Degrees
Phase
Gain
RL = 10 kΩ,
CL = 160 pF,
TA = 25°C
Figure 8
5
6
7
8
9
−40 0 25 85 125
TJ − Junction Temperature − °C
Slow-Start Time − ms
SLOW-START TIME
vs
JUNCT I O N T E M P E R ATURE
10
SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
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8
APPLICATION INFORMATION
Figure 9 shows the schematic diagram for a typical DDR
memory or GTL bus termination application using the
TPS54672. The TPS54672 (U1) can provide greater than
6 A of output current. For proper operation, the exposed
thermal PowerPAD underneath the integrated circuit
package needs to be soldered to the printed-circuit board.
COMPONENT SELECTION
The values for the components used in this design
example were selected for best load transient and tracking
response. Additional design information is available at
www.ti.com.
INPUT VOLTAGE
The input voltage range is 3 to 5.5 VDC. The input filter
(C4) is a 1 0 - µF ceramic capacitor (Taiyo Yuden). C8, also
a 10-µF ceramic capacitor (Taiyo Yuden) that provides
high frequency decoupling of the TPS54672 from the input
supply, must be located as close as possible to the device.
Ripple current is carried in both C8 and C4, and the return
path to PGND should avoid the current circulating in the
output capacitors C7 and C10.
FEEDBACK CIRCUIT
R1, R2, R3, C1, C2 and C3 form the loop compensation
network for the circuit. For this design, a Type 3 topology
is used. The compensation network, along with the output
filter inductor and capacitor delivers a crossover frequency
of 135 kHz with 50° of phase margin.
OPERATING FREQUENCY
In the application circuit, RT is grounded through a 71.5-kΩ
resistor to select the maximum frequency of 700 kHz. To
set a d i fferent frequency, place a 68-kΩ to 180-kΩ resistor
between RT (pin 28) and analog ground or leave RT
floating to select the default 350 kHz. The resistance can
be calculated using the following equation:
R+500 kHz
SwitchingFrequency 100 [kW]
28
27
26
25
24
23
22
21
20
19
18
17
16
RT
ENA
REFIN
VBIAS
VIN
15
PGND
STATUS
COMP
AGND
1
3
5
7
9
11
U1
TPS54672
C4
10 µF
R2
4.75 kΩ
C6
0.047 µF
2
4
6
8
10
12
13
14
C9
0.1 µF
R7
10 kΩ
R6
10 kΩ
VDDQ
C8
10 µF
PwrPad
C2
2700 pF
C1
100 pF
R1
10 kΩ
R3
182 Ω
C3
0.01 µF
L1
0.56 µHC7
150 µF
+C10
150 µF
+C11
1 µF
VTTQ
VSENSE
BOOT
PH
PH
PH
PH
PH
PH
PH
PH
PH
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
VI
Figure 9. Application Circuit Optimized For Size And Performance
(1)
SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
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9
OUTPUT FILTER
The output filter is composed of a 0.56-µH Coilcraft
inductor (D01813P−561HC) and two 150-µF Cornell
Dublier capacitors (ESRD151M06R). The inductor is a low
dc resistance type. The capacitors used are 4 V POSCAP
types with a maximum ESR of 0.040 Ω.
PCB LAYOUT
Figure 10 shows a generalized PCB layout guide for the
TPS54672. The VIN pins should be connected together on
the printed circuit board (PCB) and bypassed with a low
ESR ceramic bypass capacitor. Minimize the loop area
formed by the bypass capacitor connections, the VIN pins,
and the TPS54672 ground pins. The minimum
recommended bypass capacitance is 10 µF ceramic with
a X5R or X7R dielectric and the optimum placement is
closest to the VIN pins and the PGND pins.
The TPS54672 has two internal grounds (analog and
power). Inside the TPS54672 the analog ground ties to all
of the noise sensitive signals, while the power ground ties
to the noisier power signals. Noise injected between the
two grounds can degrade the performance of the
TPS54672, particularly at higher output currents. Ground
noise on a n analog ground plane can also cause problems
with some of the control and bias signals. For these
reasons, separate analog and power ground traces are
recommended. There should be an area of ground on the
top layer under the IC, with an exposed area for connection
to the PowerPAD. Use vias to connect this ground area to
any internal ground planes. Use additional vias at the
ground side of the input and output filter capacitors as well.
The AGND and PGND pins should be tied to the PCB
ground by connecting them to the ground area under the
device as shown. The only components that should tie
directly to the power ground plane are the input capacitors,
the output capacitors, the input voltage decoupling
capacitor, and the PGND pins of the TPS54672. Use a
separate wide trace for the analog ground signal path. This
analog ground should be used for the voltage set point
divider, timing resistor RT, and bias capacitor grounds.
Connect this trace directly to AGND (pin 1).
The PH pins should be tied together and routed to the
output inductor. Since the PH connection is the switching
node, the inductor should be located very close to the PH
pins and the area of the PCB conductor minimized to
prevent excessive capacitive coupling.
Connect the boot capacitor between the phase node and
the BOOT pin as shown. Keep the boot capacitor close to
the IC and minimize the conductor trace lengths.
Connect the output filter capacitor(s) as shown between
the VOUT trace and PGND. It is important to keep the loop
formed by the PH pins, Lout, Cout, and PGND as small as
practical.
Place the compensation components from the VOUT trace
to the VSENSE, and COMP pins. Do not place these
components too close to the PH trace. Due to the size of
the IC package and the device pin out, the components
must be routed somewhat close, however maintaining as
much separation as possible while still keeping the layout
compact.
Connect the bias capacitor from the VBIAS pin to analog
ground using the isolated analog ground trace. If an RT
resistor is used, connect it to this trace as well.
SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
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10
AGND
BOOT
VSENSE
COMP
PWRGD
PH
PH
PH
PH
PH
PH
PH
PH
PH
RT
ENA
REFIN
VBIAS
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
PGND
VOUT
PH VIN
TOPSIDE GROUND AREA
VIA to Ground Plane
ANALOG GROUND TRACE
EXPOSED
POWERPAD
AREA
COMPENSATION
NETWORK
OUTPUT INDUCTOR
OUTPUT
FILTER
CAPACITOR
BOOT
CAPACITOR
INPUT
BYPASS
CAPACITOR
INPUT
BULK
FILTER
BIAS CAPACITOR
TRACKING VOLTAGE
RESISTOR DIVIDER
NETWORK
Figure 10. TPS54672 PCB Layout
SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
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11
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
For operation at full rated load current, the analog ground
plane must provide adequate heat dissipating area. A 3
inch by 3 inch plane of 1 ounce copper is recommended,
though not mandatory, depending on ambient temperature
and airflow. Most applications have larger areas of internal
ground plane available, and the PowerPAD should be
connected to the largest area available. Additional areas
on the top or bottom layers also help dissipate heat, and
any area available should be used when 6 A or greater
operation is desired. Connection from the exposed area of
the PowerPAD to the analog ground plane layer should be
made using 0.013 inch diameter vias to avoid solder
wicking through the vias. Eight vias should be in the
PowerPAD area with four additional vias located under the
device package. The size of the vias under the package,
but not in the exposed thermal pad area, can be increased
to 0.018. Additional vias beyond the twelve recommended
that enhance thermal performance should be included in
areas not under the device package.
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
Minimum Recommended Top
Side Analog Ground Area
0.3478
0.0150
0.06
0.0256
0.1700
0.1340
0.0630
0.0400
Ø0.01804 PL
0.2090
Ø0.0130
8 PL
Minimum Recommended Exposed
Copper Area for Powerpad. 5mm
Stencils May Require 10 Percent
Larger Area
0.0650
0.0500
0.0500
0.0650
0.0339
0.0339
0.0500
Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside
Powerpad Area 4 x 0.018 Diameter Under Device as Shown.
Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground
Area Is Extended.
0.3820
Figure 11. Recommended Land Pattern for 28-Pin PWP PowerPAD
Figure 12
LOAD TRANSIENT RESPONSE
10 µs/div
Output Voltage
(50 mV/div AC Coupled)
Output Current
(2A/div)
Figure 13
50
55
60
65
70
75
80
85
90
95
01234567
VI = 3.3 V, VO = 1.25 V, L = 2.2 uH
VI = 5 V,
VO = 1.75 V,
L = 0.56 uH
VI = 3.3 V,
VO = 0.9 V,
L = 0.56 uH
IO − Output Current − A
Efficiency − %
EFFICIENCY
vs
OUTPUT CURRENT
DETAILED DESCRIPTION
Under Voltage Lock Out (UVLO)
The TPS54672 incorporates an under voltage lockout
circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are
held inactive until VIN exceeds the nominal UVLO
threshold voltage of 2.95 V. Once the UVLO start threshold
is reached, device start-up begins. The device operates
until VIN falls below the nominal UVLO stop threshold of
SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
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12
2.8 V. Note that hysteresis in the UVLO comparator and a
2.5-µs rising and falling edge deglitch circuit reduce the
likelihood of shutting the device down due to noise on VIN.
Enable (ENA)
The enable pin, ENA, provides a digital control to enable
or disable (shutdown) the TPS54672. An input voltage of
1.4 V or greater ensures that the TPS54672 is enabled. An
input of 0.82 V or less ensures that device operation is
disabled. These are not standard logic thresholds, even
though they are compatible with TTL outputs.
When ENA is low, the oscillator, slow-start, PWM control
and MOSFET drivers are disabled and held in an initial
state ready for device start-up. On an ENA transition from
low to high, device start-up begins with the output starting
from 0 V.
Slow-Start
The slow-start circuit provides start-up slope control of the
output voltage to limit in-rush currents. The nominal
internal slow-start rate is 0.25 V/ms with the maximum rate
being 0.35 V/ms. When the voltage on REFIN rises faster
than the internal slope or is present when device operation
is enabled, the output rises at the internal rate. If the
reference voltage on REFIN rises more slowly, then the
output rises at about the same rate as REFIN.
VBIAS Regulator (VBIAS)
The VBIAS regulator provides internal analog and digital
blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality,
low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are
recommended because their values are more stable over
temperature. The bypass capacitor should be placed close
to the VBIAS pin and returned to AGND.
External loading on VBIAS is allowed, with the caution that
internal circuits require a minimum VBIAS of 2.7 V, and
that loads with ac or digital switching noise may degrade
performance. Th e V BIAS pin may be useful as a reference
voltage for external circuits.
Oscillator Frequency (RT)
The oscillator frequency can be set to an internally fixed
value of 350 kHz by leaving the RT pin unconnected
(floating). If a different frequency of operation is required
for the application, the oscillator frequency can be
externally adjusted from 280 kHz to 700 kHz by connecting
a resistor to the R T pin to ground. The operating frequency
is approximated by the following equation, where R is the
resistance from RT to AGND:
Switching Frequency +100 kW
R 500 [kHz]
The following table summarizes the frequency selection
configurations:
FREE RUNNING FREQUENCY RT PIN
350 kHz, internally set Float
Externally set 280 kHz to 700 kHz R = 68 k to 180 k
Error Amplifier (REFIN, VSENSE, COMP)
The high performance voltage error amplifier, with wide
5MHz bandwidth, low 1.5 mV-max offset, 1.4 V/µs slew
rate, and ground rail input range differentiates the
TPS54672 from most dc/dc converters. The user is given
the flexibility to use a wide range of output L and C filter
components to suit the particular application needs. Type
2 or type 3 compensation can be employed using external
compensation components.
The REFIN input range includes ground which allows 0%
duty cycle during transient conditions. The user should
note that steady state regulation accuracy of voltages less
than 0.84 V is limited by the minimum controllable ON
time.
PWM Control
Signals from the error amplifier output, oscillator and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control
logic includes the PWM comparator, OR gate, PWM latch
and portions of the adaptive dead time and control logic
block. During steady state operation below the current limit
threshold, the PWM comparator output and oscillator
pulse train alternately reset and set the PWM latch. Once
the PWM latch is set, the low-side FET remains on for a
minimum duration set by the oscillator pulse width. During
this period, the PWM ramp discharges rapidly to its valley
voltage. When the ramp begins to charge back up, the
low-side FET turns off and high-side FET turns on. As the
PWM ramp voltage exceeds the error amplifier output
voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side
FET. The low-side FET remains on until the next oscillator
pulse discharges the PWM ramp.
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM
latch is never reset and the high-side FET remains on until
the oscillator pulse signals the control logic to turn the
high-side FET off and the low-side FET on. The device
operates at its maximum duty cycle until the output voltage
rises to the regulation set-point, setting VSENSE to
approximately the same voltage as REFIN. If the error
amplifier output is low, the PWM latch is continually reset
and the high-side FET does not turn on. The low-side FET
remains on until the VSENSE voltage decreases to a
range that allows the PWM comparator to change states.
The TPS54672 is capable of sinking current continuously
until the output reaches the regulation set-point.
(2)
SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
www.ti.com
13
If the current limit comparator trips for longer than 100 ns,
the PWM latch resets before the PWM ramp exceeds the
error amplifier output. The high-side FET turns off and
low-side FET on to decrease the output current. This
process is repeated each cycle in which the current limit
comparator is tripped.
Dead-Time Control and MOSFET Drivers
Adaptive dead-time control prevents shoot-through
current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the
turnon times of the MOSFET drivers. The high-side driver
does not turn on until the gate drive voltage to the low-side
FET is below 2 V, while the low-side driver does not turn
on until the voltage at the junction of the power MOSFETs
(PH pin) is below 2 V.
The high-side and low-side drivers are designed with
300-mA source and sink capability to quickly drive the
power MOSFETs gates. The low-side driver is supplied
from VIN, while the high-side drive is supplied from the
BOOT pin. A bootstrap circuit uses an external BOOT
capacitor and internal 2.5-Ω bootstrap switch connected
between the VIN and BOOT pins. The bootstrap switch is
turned o n when the low-side FET is on to charge the BOOT
capacitor. The low resistance of the bootstrap switch
improves drive ef ficiency and reduces external component
count.
Overcurrent Protection
The cycle by cycle current limiting is achieved using a
sense-FET on the high-side MOSFET and differential
amplifier with preset overcurrent threshold. The high-side
MOSFET is turned off within 200 ns of the voltage on the
sense-FET exceeding the current limit threshold. A 100-ns
leading edge blanking circuit prevents false tripping of the
current limit when the high-side switch is turning on.
Current limit detection occurs only when current flows from
VIN to PH when current is being sourced to the output filter.
Load protection during current sink operation is provided
by thermal shutdown.
Thermal Shutdown
Thermal shutdown turns off the power MOSFETs and
disables the control circuits if the junction temperature
exceeds the 150°C. The device is released from shutdown
automatically when the junction temperature decreases to
10°C, and starts up under control of the slow-start circuit.
Status (STATUS)
The status pin is an open drain output that indicates when
internal conditions are sufficient for proper operation.
STATUS can be coupled back to a system controller or
monitor circuit to indicate that the termination or tracking
regulator is ready for start up. STATUS is high impedance
when the TPS54672 is operating or ready to be enabled.
STATUS is active low if any of the following occur:
DVIN < UVLO threshold
DVBIAS or internal reference have not settled.
DThermal shutdown is active.
PACKAGE OPTION ADDENDUM
www.ti.com 30-Apr-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS54672PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS54672PWPG4 ACTIVE HTSSOP PWP 28 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS54672PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS54672PWPRG4 ACTIVE HTSSOP PWP 28 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS54672PWPR HTSSOP PWP 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Apr-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS54672PWPR HTSSOP PWP 28 2000 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Apr-2011
Pack Materials-Page 2
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