QUAD NON-PROGRAMMABLE
PCM CODEC IDT821024
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc
INDUSTRIAL TEMPERATURE RANGE FEBRUARY 9, 2009
2003 Integrated Device Technology, Inc.
DSC-6034/4
FEATURES
•4 channel CODEC with on-chip digital filters
•Selectable A-law or µ-law companding
•Master clock frequency selection: 2.048 MHz, 4.096 MHz or
8.192 MHz
- Internal timing automatically adjusted based on MCLK and
frame sync signal
•Separate PCM and master clocks
•Single PCM port with up to 8.192 MHz data rate (128 time slots)
•Transhybrid balance impedance hardware adjustable via external
components
•Transmit gains hardware adjustable via external components
•Low power +5.0 V CMOS technology
•+5.0 V single power supply
•Package available: 32 pin PLCC, 44 pin TQFP
FUNCTIONAL BLOCK DIAGRAM
Anolog Front End
CH2
Anolog Front End
CH1
Anolog Front End
CH3
Anolog Front End
CH4
DSP
PCM Interface
PCM TSA 1
PCM TSA 2
PCM TSA 3
PCM TSA 4
Clock
&
Reference Circuits
Control
PDN 1~ 4
A/µ
IIN1
VOUT1
IIN2
VOUT2
IIN3
VOUT3
IIN4
VOUT4
MCLK
IREF
CNF
FSX1
FSR1
FSX2
FSR2
FSX3
FSR3
FSX4
FSR4
DX
TSC
DR
PCLK
VCCA
AGND
VCCD
DGND
DESCRIPTION
The IDT821024 is a single-chip, four channel PCM CODEC with on-
chip filters. The device provides analog-to-digital and digital-to-analog
conversions and supports both a-law and µ−law companding. The digital
filters in IDT821024 provides the necessary transmit and receive filtering
for voice telephone circuit to interface with time-division multiplexed
systems. All of the digital filters are performed in digital signal processors
operating from an internal clock, which is derived from MCLK. The fixed
filters set the transmit and receive gain and frequency response.
In the IDT821024 the PCM data is transmitted to and received from
the PCM highway in time slots determined by the individual Frame Sync
signals (FSRn and FSXn, where n = 1-4) at rates from 256 KHz to 8.192
MHz. Both Long and Short Frame Sync modes are available in the
IDT821024.
The IDT821024 can be used in digital telecommunication applications
such as PBX, Central Office Switch, Digital Telephone and Integrated Voice/
Data Access Unit.
2
INDUSTRIAL TEMPERATURE RANGEIDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
PIN CONFIGURATIONS
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
4
3
2
1
32
31
30
32-Pin
PLCC
VOUT4
A/µ
FSX4
FSR4
FSX3
FSR3
FSX2
VOUT1
CNF
PDN1
PDN2
PDN3
PDN4
MCLK
29
28
27
26
25
24
23
22
21
PCLK
TSC
DGND
DX
VCCD
DR
FSR1
FSX1
FSR2
IIN1
IIN2
VOUT2
VCCA
IREF
AGND
VOUT3
IIN3
IIN4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
44-Pin
TQFP
IIN4
VOUT4
NC
NC
A/µ
NC
FSX4
FSR4
FSX3
FSR3
FSX2
IIN1
VOUT1
NC
CNF
NC
PDN1
PDN2
PDN3
PDN4
MCLK
PCLK
33
32
31
30
29
28
27
26
25
24
23
NC
NC
TSC
DGND
NC
DX
VCCD
DR
FSR1
FSX1
FSR2
IIN2
VOUT2
NC
NC
VCCA
IREF
AGND
NC
NC
VOUT3
IIN3
3
INDUSTRIAL TEMPERATURE RANGEIDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
PIN DESCRIPTION
Pin Number
Name I/O PLCC TQFP Description
AGND -- 10 7 Analog Ground.
All ground pins should be connected to the ground plane of the circuit board.
VCCA -- 8 5 +5 V Analog Power Supply.
All power supply pins should be connected to the power plane of the circuit board.
DGND -- 27 30 Digital Ground.
All ground pins should be connected to the ground plane of the circuit board.
VCCD -- 25 27 +5 V Digital Power Supply.
All power supply pins should be connected to the power plane of the circuit board.
DR I 24 26
Receive PCM Data Input.
The PCM data for Channel 1, 2, 3 and 4 is shifted serially into DR pin by the Receive Frame Sync Signal
(FSR) with MSB first. A byte of data for each channel is received every 125 µs at the PCLK rate.
DX O 26 28
Transmit PCM Data Output.
The PCM data for Channel 1, 2, 3 and 4 is shifted serially out to the DX pin by the Transmit Frame Sync Signal
(FSX) with MSB first. A byte of data for each channel is transmitted every 125 µs at the PCLK rate. DX is high
impedance between time slots.
FSR1
FSR2
FSR3
FSR4
I
23
21
19
17
25
23
21
19
Receive Frame Sync Input for Channel 1/2/3/4
This 8kHz signal pulse identifies the receive time slot for Channel N on a system’s receive PCM frame. It must
be synchronized to PCLK.
FSX1
FSX2
FSX3
FSX4
I
22
20
18
16
24
22
20
18
Transmit Frame Sync Input for Channel 1/2/3/4
This 8 kHz signal pulse identifies the transmit time slot for Channel N on a system’s transmit PCM frame. It
must be synchronized to PCLK.
IREF O 9 6
Reference Current.
The IREF output is biased at the internal reference voltage. A resistor placed from IREF to ground sets the
reference current used by the analog-to-digital converter to encode the signal current present on IINn pin (n is
channel number, n = 1 to 4) into digital form.
VOUT1
VOUT2
VOUT3
VOUT4
O
4
7
11
14
43
2
10
13
Voice Frequency Receiver Output for Channel 1/2/3/4
This is the output of receiver amplifier for Channel N. The received digital data from DR is processed and
converted to an analog signal at this pin.
IIN1
IIN2
IIN3
IIN4
I
5
6
12
13
44
1
11
12
Voice Frequency Transmitter Input for Channel 1/2/3/4
This is the input to the gain setting amplifier in the transmit path for Channel N. The analog voice band voltage
signal is applied to this pin through a resistor. This input is a virtual AC ground input, which is biased at the
IREF pin.
MCLK I 30 35
Master Clock.
The Master Clock provides the clock for the DSP. It can be either 2.048 MHz or 4.096 MHz. The IDT821024
determines the MCLK frequency via the FSX inputs and makes the necessary internal adjustments
automatically. The MCLK frequency must be an integer multiple of the FSX frequency.
PCLK I 29 34
PCM Clock.
The PCM Clock shifts out the PCM data to the DX pin and shifts in PCM data from the DR pin. The PCM clock
frequency is an integer multiple of the frame sync frequency. When PCLK is connected to MCLK, the PCM
clock can generate the DSP clock as well.
TSC O 28 31
Time Slot Control.
This open drain output is low active. When the PCM data is transmitted to the DX pin for any of the four
channels, this pin will be pulled low.
A/µ I 15 16
A/µ-Law Selection.
When this pin is low, µ-Law is selected; when this pin is high, A-Law is selected. This pin can be connected to
VCCD or DGND pin directly.
4
INDUSTRIAL TEMPERATURE RANGEIDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
Pin Number
Name I/O PLCC TQFP Description
PDN1
PDN2
PDN3
PDN4
I
2
1
32
31
39
38
37
36
Channel 1/2/3/4 Power Down.
When this pin is high, Channel N is powered down.
CNF O 3 41 Capacitor For Noise Filter.
This pin should be connected to AGND through a 0.1µF capacitor.
NC --
3, 4, 8, 9,
14, 15, 17,
29, 32, 33,
40, 42
No connection
PIN DESCRIPTION (cont’d)
5
INDUSTRIAL TEMPERATURE RANGEIDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
FUNCTIONAL DESCRIPTION
The IDT821024 contains four channel PCM CODEC with on chip digital
filters. It provides the four-wire solution for the subscriber line circuitry in
digital switches. The device converts analog voice signal to digital PCM
data, and converts digital PCM data back to analog signal. Digital filters
are used to bandlimit the voice signals during the conversion. Either A-law
or µ-law is supported by the IDT821024. The law selection is performed
by A/µ pin.
The frequency of the master clock (MCLK) can be 2.048 MHz, 4.096
MHz, or 8.192 MHz. Internal circuitry determines the master clock frequency
automatically.
The serial PCM data for four channels are time multiplexed via two pins,
DX and DR. The time slots of the four channels are determined by the
individual Frame Sync signals at rates from 256 kHz to 8.192 MHz. For
each channel, the IDT821024 provides a transmit Frame Sync signal and
a receive Frame Sync signal.
Each channel of the IDT821024 can be powered down independently
to save power consumption. The Channel Power Down Pins PDN1-4
configure channels to be active (power-on) or standby (power-down)
separately.
Signal Processing
High performance oversampling Analog-to-Digital Converters (ADC) and
Digital-to-Analog Converters (DAC) are used in the IDT821024 to provide
the required conversion accuracy. The associated decimation and interpo-
lation filtering are realized with both dedicated hardware and Digital Signal
Processor (DSP). The DSP also handles all other necessary functions such
as PCM bandpass filtering and sample rate conversion.
Transmit Signal Processing
In the transmit path, the analog input signal is received by the ADC and
converted into digital data. The digital output of the oversampling ADC is
decimated and sent to the DSP. The transmit filter is implemented in the
DSP as a digital bandpass filter. The filtered signal is further decimated
and compressed to PCM format.
Transmit PCM Interface
The transmit PCM interface clocks out 1 byte (8 bits) PCM data out of
DX pin every 125 µs. The transmit logic, synchronized by the Transmit
Frame Sync signal (FSXn), controls the data transmission. The FSXn
pulse identifies the transmit time slot of the PCM frame for Channel N.
The PCM Data is transmitted serially on DX pin with the Most Significant
Bit (MSB) first. When the PCM data is being output on DX pin, the TSC
signal will be pulled low.
Receive Signal Processing
In the receive path, the PCM code is received at the rate of 8,000 samples
per second. The PCM code is expanded and sent to the DSP for
interpolation. A receive filter is implemented in the DSP as a digital lowpass
filter. The filtered signal is then sent to an oversampling DAC. The DAC
output is post-filtered and delivered at VOUT pin by an amplifier. The
amplifier can drive resistive load higher than 2 KΩ.
Receive PCM Interface
The receive PCM interface clocks 1 byte (8 bits) PCM data into DR pin
every 125 µs. The receive logic, synchronized by the Receive Frame Sync
signal (FSRn), controls the data receiving process. The FSRn pulse
identifies the receive time slot of the PCM frame for Channel N. The PCM
Data is received serially on DR pin with the Most Significant Bit (MSB)
first.
Hardware Gain Setting In Transmit Path
The transmit gain of the IDT821024 for each channel can be set by 2
resistors, RREF and RTXn (as shown in Figure 1), according to the follow-
ing equation:
TXn
REF
tR
R3
G×
=
The receive gain of IDT821024 is fixed and equal to 1.
A/D
I
REF
V
REF
to
I
REF
V
REF
D/A
Bal
Net
R
REF
1
I
REF
1
V
REF
1C
FIL
V
IN
1
V
OUT
1
IDT821024
C
TX
1
R
TX
1
R
RX
1C
RX
1
to
SLIC
RSN
to
SLIC
VTX
Figure 1. IDT821024 Transmit Gain Setting for Channel 1
6
INDUSTRIAL TEMPERATURE RANGEIDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
OPERATING THE IDT821024
The following descriptions about operation applies to all four channels of
the IDT821024.
Power-on Sequence and Master Clock Configuration
To power on the IDT821024 users should follow this sequence:
1. Apply ground;
2. Apply VCC, finish signal connections;
3. Set PDN1-4 pins high, thus all of the 4 channels are powered down;
The master clock (MCLK) frequency of IDT821024 can be configured as
2.048 MHz, 4.096 MHz or 8.192 MHz. Using the Transmit Frame Sync
(FSX) inputs, the device determines the MCLK frequency and makes the
necessary internal adjustments automatically. The MCLK frequency must
be an integer multiple of the Frame Sync frequency.
Operating Modes
There are two operating modes for each transmit or receive channel:
standby mode (when the channel is powered down) and normal mode (when
the channel is powered on). The mode selection of each channel is done
by its corresponding PDN pin. When PDNn is 1, Channel N is in standby
mode; when PDNn is 0, Channel N is in normal mode.
In standby mode, all circuits are powered down with the analog outputs
placed in high impedance state.
In normal mode, each channel of the IDT821024 is able to transmit and
receive both PCM and analog information. The normal mode is used when
a telephone call is in progress.
Companding Law Selection
An A/µ pin is provided by IDT821024 for the companding law selection.
When this pin is low, µ-law is selected; when the pin is high, A-law is
selected.
7
INDUSTRIAL TEMPERATURE RANGEIDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
Analog Interface
ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Power Dissipation
RECOMMENDED DC OPERATING
CONDITIONS
NOTE: MCLK: 2.048 MHz, 4.096 MHz or 8.192 MHz with tolerance of ± 50 ppm
Rating Com’I & Ind’I Unit
Power Supply Voltage ≤ 6.5 V
Voltage on Any Pin with Respect to
Ground
-0.5 to 5.5 V
Package Power Dissipation ≤ 600 mW
Storage Temperature -65 to +150 °C
Parameter Min. Typ. Max. Unit
Operating Temperature -40 +85 °C
Power Supply Voltage 4.75 5.25 V
Digital Interface
ELECTRICAL CHARACTERISTICS
Parameter Description Min Typ Max Units Test Conditions
VIL Input Low Voltage 0.8 V All digital inputs
VIH Input High Voltage 2.0 V All digital inputs
0.4 V DX, TSC,IL = 14mA
0.8 V All other digital outputs,
IL = 4mA.
VOL Output Low Voltage
0.2 V All digital pins, IL = 14mA
VDD-0.6
V
DX, IH = -7 mA, all other outputs, IH = -4 mA VOH Output High Voltage
VDD-0.2
V All digital pins, IH = -1mA
II Input Current -10 10 µA Any digital inputs GND<VIN<VDD
IOZ Output Current in High-impedance State -10 10 µA DX
CI Input Capacitance 5 pF
Note: Total current must not exceed absolute maximum ratings.
Note: Power measurements are made at MCLK = 4.096 MHz, outputs unloaded
Parameter Description Min Typ Max Units Test Conditions
VOUT1 Output Voltage 2.25 2.4 2.6 V Alternating±zero µ-law PCM code applied to DR.
VOUT2 Output Voltage Swing 3.25 V P-P RL=2000Ω
RO Output Resistance 1 4 Ω 0dBm0, 1020Hz PCM code applied to DR
RL Load Resistance 2000 Ω External loading
IIR Analog Input Current Range ±40 µA RREF = 13kΩ
IIOS Offset Current Allowed on IIN -1.6 +1.6 µA
IOUT VOUT Output Current (F< 3400Hz) -5 5 mA
IZ Output Leakage Current -10 10 µA Power down
CL Load Capacitance 100 pF External loading
Parameter Description Min Typ Max Units Test Conditions
PD2 Operating Power Dissipation 1 180 240 mW All channels are active
PD1 Operating Power Dissipation 1 60 90 mW Only one channel is active
PD0 Standby Power Dissipation 4 10 mW All channels are powered down,with only MCLK present
8
INDUSTRIAL TEMPERATURE RANGEIDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
TRANSMISSION CHARACTERISTICS
0dBm0 is defined as 0.6832Vrms for A-law and 0.6778 Vrms for µ-law, both for 600 Ω load. Unless otherwise noted, the analog input is a 0
dBm0, 1020 Hz sine wave; the input amplifier is set for unity gain. The digital input is a PCM bit stream equivalent to that obtained by passing a 0
dBm0, 1020 Hz sine wave through an ideal encoder. The output level is sin(x)/x-corrected. Typical value are tested at VDD = 5V and TA = 25°C.
Absolute Gain
Gain Tracking
Frequency Response
Group Delay
Note*: Minimum value in transmit and receive path.
Parameter Description Min Typ Max Units Test Conditions
GXA Transmit Gain, Absolute
0°C to 85°C
-40°C
-0.25
-0.35
0.25
0.35
dB
dB
Signal input of 0 dBm0, µ-law or A-law
GRA Receive Gain, Absolute
0°C to 85°C
-40°C
-0.25
-0.35
0.25
0.35
dB
dB
Measured relative to 0 dBm0, µ-law or A-law, PCM input of 0
dBm0 1020 Hz , RL = 10 kΩ
Parameter Description Min Typ Max Units Test Conditions
GTX Transmit Gain Tracking
+3 dBm0 to –40 dBm0
-40 dBm0 to -50 dBm0
-50 dBm0 to -55 dBm0
-0.10
-0.25
-0.50
0.10
0.50
0.50
dB
dB
dB
Tested by Sinusoidal Method, µ-law/A-law
GTR Receive Gain Tracking
+3 dBm0 to –40 dBm0
-40 dBm0 to -50 dBm0
-50 dBm0 to -55 dBm0
-0.10
-0.25
-0.50
0.10
0.50
0.50
dB
dB
dB
Tested by Sinusoidal Method, µ-law/A-law
Parameter Description Min Typ Max Units Test Conditions
GXR Transmit Gain, Relative to GXA
f = 50 Hz
f = 60 Hz
f = 300 Hz to 3400 Hz
f = 3600 Hz
f = 4600 Hz and above
-0.15
-40
-40
0.15
-0.1
-35
dB
dB
dB
dB
dB
GRR Receive Gain, Relative to GRA
f below 300 Hz
f = 300 Hz to 3400 Hz
f = 3600 Hz
f = 4600 Hz and above
-0.15
0
0.15
-0.2
-35
dB
dB
dB
dB
Parameter Description Min Typ Max Units Test Conditions
DXA Transmit Delay, Absolute * 340 µs
DXR Transmit Delay, Relative to 1800 Hz
f = 500 Hz – 600 Hz
f = 600 Hz –1000 Hz
f = 1000 Hz – 2600 Hz
f = 2600 Hz – 2800 Hz
280
150
80
280
µs
µs
µs
µs
DRA Receive Delay, Absolute * 260 µs
DRR Receive Delay, Relative to 1800 Hz
f = 500 Hz – 600 Hz
f = 600 Hz –1000 Hz
f = 1000 Hz – 2600 Hz
f = 2600 Hz – 2800 Hz
50
80
120
150
µs
µs
µs
µs
9
INDUSTRIAL TEMPERATURE RANGEIDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
Distortion
Noise
Parameter Description Min Typ Max Units Test Conditions
STDX Transmit Signal to Total Distortion Ratio
A-law :
Input level = 0 dBm0
Input level = -30 dBm0
Input level = -40 dBm0
Input level = -45 dBm0
µ-law :
Input level = 0 dBm0
Input level = -30 dBm0
Input level = -40 dBm0
Input level = -45 dBm0
36
36
30
24
36
36
31
27
dB
dB
dB
dB
dB
dB
dB
dB
ITU-T O.132
Sine Wave Method,Psophometric Weighted for A-
law, C Message Weighted for µ-law.
STDR Receive Signal to Total Distortion Ratio
A-law :
Input level = 0 dBm0
Input level = -30 dBm0
Input level = -40 dBm0
Input level = -45 dBm0
µ-law :
Input level = 0 dBm0
Input level = -30 dBm0
Input level = -40 dBm0
Input level = -45 dBm0
36
36
30
24
36
36
31
27
dB
dB
dB
dB
dB
dB
dB
dB
ITU-T O.132
Sine Wave Method,Psophometric Weighted for A-
law;Sine Wave Method,C Message Weighted for µ-
law;
SFDX Single Frequency Distortion, Transmit -42 dBm0 200 Hz - 3400 Hz, 0 dBm0 input, output any other
single frequency ≤ 3400 Hz
SFDR Single Frequency Distortion, Receive -42 dBm0 200 Hz - 3400 Hz, 0 dBm0 input, output any other
single frequency ≤ 3400 Hz
IMD Intermodulation Distortion -42 dBm0 Transmit or receive,two frequencies in the range
(300 Hz− 3400 Hz) at −6 dBm0
Parameter Description Min Typ Max Units Test Conditions
NXC Transmit Noise, C Message Weighted for µ-law 16 dBrnC0
NXP Transmit Noise, Psophometric Weighted for A-law -68 dBm0p
NRC Receive Noise, C Message Weighted for µ-law 12 dBrnC0
NRP Receive Noise, Psophometric Weighted for A-law -78 dBm0p
NRS Noise, Single Frequency
f = 0 kHz – 100 kHz
-53 dBm0 IIN = 0 A, tested at VOUT
PSRX Power Supply Rejection Transmit
f = 300 Hz – 3.4 kHz
f = 3.4 kHz – 20 kHz
40
25
dB
dB
VDD = 5.0 VDC + 100 mVrms
PSRR Power Supply Rejection Receive
f = 300 Hz – 3.4 kHz
f = 3.4 kHz – 20 kHz
40
25
dB
dB
PCM code is positive one LSB, VDD = 5.0 VDC +
100 mVrms
SOS Spurious Out-of-Band Signals at VOUT Relative to
Input PCM code applied:
4600 Hz – 20 kHz
20 kHz – 50 kHz
-40
-30
dB
dB
0 dBm0, 300 Hz – 3400 Hz input
10
INDUSTRIAL TEMPERATURE RANGEIDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
Interchannel Crosstalk
Intrachannel Crosstalk
Parameter Description Min Typ Max Units Test Conditions
XTX-R Transmit to Receive Crosstalk -85 -78 dB 300 Hz – 3400 Hz, 0 dBm0 signal into IIN of interfering channel.
Idle PCM code into channel under test.
XTR-X Receive to Transmit Crosstalk -85 -80 dB 300 Hz – 3400 Hz, 0 dBm0 PCM code into interfering channel. IIN
= 0 A for channel under test.
XTX-X Transmit to Transmit Crosstalk -85 -78 dB 300 Hz – 3400 Hz, 0 dBm0 signal into IIN of interfering channel.
IIN = 0 A for channel under test.
XTR-R Receive to Receive Crosstalk -85 -80 dB 300 Hz – 3400 Hz, 0 dBm0 PCM code into interfering channel. Idle
PCM code into channel under test.
Parameter Description Min Typ Max Units Test Conditions
XTX-R Transmit to Receive Crosstalk -80 -70 dB 300 Hz – 3400 Hz, 0 dBm0 signal into IIN. Idle PCM code into DR.
XTR-X Receive to Transmit Crosstalk -80 -70 dB 300 Hz – 3400 Hz, 0 dBm0 PCM code into DR. IIN = 0 A.
11
INDUSTRIAL TEMPERATURE RANGEIDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
TIMING CHARACTERISTICS
Clock
Parameter Description Min Typ Max Units Test Conditions
t1 PCLK Duty Cycle 40 60 %PCLK=512kHz to 8.192MHz
t2 PCLK Rise and Fall Time 25 ns PCLK=512kHz to 8.192MHz
t3 MCLK Duty Cycle 40 60 %MCLK=2.048Hz,4.096MHz
or 8.192MHz
t4 MCLK Rise and Fall Time 15 ns MCLK=2.048Hz,4.096MHz
or 8.192MHz
t5 PCLK Clock Period 244 ns PCLK=512kHz to 8.192MHz
Transmit
Parameter Description Min Typ Max Units Test Conditions
t11 Data Output Delay Time (for Short
Frame Sync Mode)
5 70 ns
t12 Data Hold Time 5 70 ns
t13 Data Delay to High-Z 50 220
t5+70
ns
t14 Frame sync Hold Time 50 ns
t15 Frame sync High Setup Time 55 t5-50 ns
t16 TSC Enable Delay Time(for Short
Frame Sync Mode)
5 80 ns
t17 TSC Disable Delay Time 50 220
t5+70
ns
t18 Data Output Delay Time(for Long
Frame Sync Mode)
5 40 ns
t19 TSC Enable Delay Time(for Long
Frame Sync Mode)
5 40 ns
t21 Receive Data Setup Time 25 ns
t22 Receive Data Hold Time 5ns
Figure 2. MCLK Timing
Note: Timing parameter t13 is referenced to a high-impedance state.
MCLK
t4 t4
12
INDUSTRIAL TEMPERATURE RANGEIDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
Figure 3. PCM Interface Timing for Short Frame Mode
Figure 4. PCM Interface Timing for Long Frame Mode
12345678
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
PCLK
FSX/
FSR
DX
DR
t15 t14 t2
Time Slot
t2
t13
t12
t11
t21 t22
TSC
t16 t17
t5
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
12345678
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
PCLK
FSX/
FSR
DX
DR
t15
Time Slot
t2
t13
t12
t18
t21 t22
TSC
t19 t17
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
1
t2
t5
13
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2975 Stender Way 800-345-7015 or 408-727-6116 408-330-1552
Santa Clara, CA 95054 fax: 408-492-8674 email: telecomhelp@idt.com
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Data Sheet Document History
01/16/2002 pgs. 4, 5
02/21/2002 pgs. 1-4, 13
09/10/2002 pg. 8
01/08/2003 pgs. 1, 13
04/03/2003 pg. 1
02/09/2009 pg. 13 removed IDT from orderable part number
XXXXXX XX X
Device Type
Blank
Process/
Temperature
Range
J
821024
Industrial (-40 °C to +85 °C)
Plastic Leaded Chip Carrier (PLCC, PL32)
Quad Non-Programmable PCM CODEC
Package
PP Thin Quad Flat Pack (TQFP, PP44)
ORDERING INFORMATION
