Page 1 of 12
Document No. DOC-44014-4 │www.psemi.com ©2014 Peregrine Semiconductor Corp. All rights reserved.
Voltage Control and ESD
RF1
VCTRL
RF2
P
OUT
P1dB
P
IN
Product Description
The PE45140 is a HaRP™ technology-enhanced RF
power limiter designed for use in tactical and military
communications receivers, land mobile radio and other
high performance power limiting applications.
Unlike traditional PIN diode solutions the limiting
threshold can be adjusted through a low current control
voltage (VCTRL), eliminating the need for external
components such as DC blocking capacitors, RF choke
inductors, and bias resistors.
This power limiter has symmetric RF ports that limit
incident power up to 50W pulsed in both biased and
unbiased conditions. It provides an extremely fast limiting
response to undesired high power signals while delivering
low insertion loss and high linearity under safe operating
power levels.
The PE45140 is manufactured on Peregrine’s
UltraCMOS® process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate.
Peregrine’s HaRP™ technology enhancements deliver
high linearity and excellent harmonics performance. It is
an innovative feature of the UltraCMOS process, offering
the performance of GaAs with the economy and
integration of conventional CMOS.
Product Specification
UltraCMOS® Power Limiter
20 MHz–2 GHz
Figure 1. Functional Diagram
PE45140
Features
Monolithic drop in solution with no
external components required
Adjustable power limiting threshold
from +22 dBm to +32 dBm
Max power handling
+47 dBm Pulsed (50W)
+40 dBm CW (10W)
Superior ESD rating and ESD protection
8 kV HBM on RF pins to GND
1 kV CDM on all pins
200V MM on all pins
Unbiased power limiting operation
Fast response and recovery time of 1 ns
Dual mode operation
Power limiting mode
Power reflecting mode
Figure 2. Package Type
12-lead 3x3 mm QFN
DOC-62357
Product Specification
PE45140
Page 2 of 12
Document No. DOC-44014-4 │ UltraCM OS® RFIC Solutions ©2014 Peregrine Semiconductor Corp. All rights reserved.
Table 1. Electrical Specifications @ +25°C (ZS = ZL = 50Ω), unless otherwise noted
Parameter Condition
Min Typ Max Unit
Operating frequency 20 2000 MHz
Power limiting mode
Insertion loss 20 MHz–1 GHz
1–2 GHz 0.20
0.60 0.45
1.00 dB
dB
Return loss 20 MHz–1 GHz
1–2 GHz 16
10 dB
dB
P1dB / limiting threshold VCTRL = –2.5V @ 915 MHz
VCTRL = –0.5V @ 915 MHz 32
22 dBm
dBm
Leakage power1 VCTRL = –2.5V @ 915 MHz
VCTRL = –0.5V @ 915 MHz 31.5
29 34
31.5 dBm
dBm
Leakage power slope VCTRL = –1.0V @ 915 MHz 0.4 dB/dB
Unbiased leakage power1 V
CTRL = 0V 23.5 27 dBm
Input IP2 VCTRL = –2.5V @ 915 MHz 104 dBm
Input IP3 VCTRL = –2.5V @ 915 MHz 64 dBm
Response / recovery time 1 GHz 1 ns
Leakage power1 V
CTRL = +2.5V @ 915 MHz –1 4.5 dBm
Switching time3 State change to 10% RF 390 µs
Power reflecting mode2
Notes: 1. Measured with +40 dBm CW applied at input.
2. This mode requires the control voltage to toggle between +2.5V and -2.5V. At +2.5V, the limiter equivalent
circuit is a low impedance to ground, reflecting mo st of the incident power ba ck to the source.
3. State change is VCTRL toggle from –2.5V to +2.5V.
Product Specification
PE45140
Page 3 of 12
Document No. DOC-44014-4 │www.psemi.com ©2014 Peregrine Semiconductor Corp. All rights reserved.
Figure 3. Pin Configuration (Top View)
Table 2. Pin Descriptions
Pin No. Pin Name Description
1, 3, 4, 6,
7, 9 GND Ground
2 RF1* RF port 1
5 VCTRL Control
8 RF2* RF port 2
Pad GND Exposed pad: Ground for proper operation
11 VDC DC voltage
10, 12 N/C No connect
VCTRL
GND
GND
N/C
VDC
N/C
Table 3. Operating Ranges
Parameter Symbol Min Typ Max Unit
DC voltage VDC 2.5 3.3 V
Control voltage
Power limiting mode
Power reflecting mode VCTRL
–2.5
–2.5
–0.5
+2.5
V
V
RF input power, CW1 PMAX,CW 40 dBm
RF input power, pulsed2 PMAX,PULSED 47 dBm
RF input power, unbiased2,3 PMAX,UNB 47 dBm
Operating temperature
range TOP –55 +25 +85 °C
Operating junction
temperature1 TJ +270 °C
Table 4. Absolute Maximum Ratings
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Notes: 1. Human Body Model (HBM, MIL_STD 883 Method 3015.7)
2. Machine Model (JEDEC JESD22-A115)
3. Charged Device Model (JEDEC JESD22-C101)
Parameter Symbol Min Max Unit
DC voltage VDC -0.3 3.6 V
Control voltage
Power limiting mode
Power reflecting mode VCTRL –3.3 3.6 V
Storage temperature range TST –65 +150 °C
ESD voltage HBM1
All pins
RF pins to GND VESD,HBM
7000
8000
V
V
ESD voltage MM2, all pins VESD,MM 200 V
ESD voltage CDM3, all pins VESD,CDM 1000 V
Notes: 1. CW, 100% duty cycle, in 10 min, 50Ω
2. Pulsed, 0.1% duty cycle of 1 µs pulse width in 10 min, 50Ω
3. VCTRL = 0V or VCTRL pin left not connected
Note: * RF pins 2 and 8 must be at 0 VDC. The RF pins do not require DC
blocking capacitors for proper operation if the 0 VDC requirement is
met.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
devices are immune to latch-up.
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE45140 in the 12-lead 3x3 mm QFN package is
MSL1. Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified.
Product Specification
PE45140
Page 4 of 12
Document No. DOC-44014-4 │ UltraCM OS® RFIC Solutions ©2014 Peregrine Semiconductor Corp. All rights reserved.
Dual Mode Operation
Power Limiting Mode
The PE45140 performs as a linear power limiter
with adjustable P1dB / limiting threshold. The
P1dB / limiting threshold can be adjusted by
changing the control voltage between –2.5V and
–0.5V. If unbiased, or if VCTRL = 0V, the PE45140
still offers power limiting protection.
Power Reflecting Mode
Power reflecting mode requires a power detector
to sample the RF input power and a
microcontroller to toggle the limiter control voltage
between +2.5V and –2.5V based on the system
protection requirements. At +2.5V, the limiter
impedance to ground is less than 1Ω and most of
the incident power will be reflected back to the
source. At –2.5V, the device operates as in power
limiting mode.
ESD Protection Capability
The PE45140 has the unique capability of being
used as a voltage clamp in the event of an ESD
strike. Clamping the output voltage can protect
devices that follow from ESD damage and enable
overall system ESD ratings to be increased.
The PE45140's ESD protection capability under
biased and unbiased conditions is observed with a
Transmission Line Pulse (TLP) measurement
characterizing the product as an ESD clamp from
each RF port to ground.
Figure 4. Transmission Line Pulse Measurement
Table 5. Transmission Line Pulse Data vs. HBM
VCTRL HBM (V) Max Current (A) Voltage (V)
0 1000 0.7 4.5
–1.5 1000 0.7 14.5
0 2000 1.3 8
–1.5 2000 1.3 16
0 3000 2.0 11
–1.5 3000 2.0 17
0
1
2
3
4
5
6
7
8
9
10
0 5 10 15 20 25
Current(A)
Voltage(V)
Vctrl=0V
Vctrl=‐1.5V
Product Specification
PE45140
Page 5 of 12
Document No. DOC-44014-4 │www.psemi.com ©2014 Peregrine Semiconductor Corp. All rights reserved.
Thermal Data
When limiting high power RF signals, the junction
temperature of the power limiter can rise
significantly.
Special consideration needs to be made in the
design of the PCB to properly dissipate the heat
away from the part and maintain the +270°C
maximum junction temperature.
It is recommended to use best design practices for
high power QFN packages: multi-layer PCBs with
thermal vias in a thermal pad soldered to the slug
of the package. Special care also needs to be
made to alleviate solder voiding under the part.
Table 5. Theta JC
Parameter Min Typ Max Unit
Theta JC 16 °C/W
Product Specification
PE45140
Page 6 of 12
Document No. DOC-44014-4 │ UltraCM OS® RFIC Solutions ©2014 Peregrine Semiconductor Corp. All rights reserved.
Figure 6. Input Return Loss vs. Temperature Figure 7. Output Return Loss vs. Temperature
Figure 5. Insertion Loss vs. Temperature
Typical Performance Data @ +25°C (ZS = ZL = 50Ω), unless otherwise noted
Product Specification
PE45140
Page 7 of 12
Document No. DOC-44014-4 │www.psemi.com ©2014 Peregrine Semiconductor Corp. All rights reserved.
Figure 10. P1dB vs. VCTRL Over Temperature
Figure 8. POUT vs. PIN Over VCTRL Figure 9. POUT vs. PIN Over Frequency @
VCTRL = –0.7V
Figure 11. POUT vs. PIN Over Frequency @
VCTRL = –1.5V
‐5
0
5
10
15
20
25
30
35
40
10 15 20 25 30 35 40
Pout(dBm)
Pin(dBm)
–2.5V –1.5V –0.7V –0.5V 0V 2.5V
0
5
10
15
20
25
30
35
10 15 20 25 30 35 40
Pout(dBm)
Pin(dBm)
–0.7V@915MHz –0.7V@2GHz
0
5
10
15
20
25
30
35
10 15 20 25 30 35 40
Pout(dBm)
Pin(dBm)
–1.5V@915MHz –1.5V@2GHz
Typical Performance Data @ +25°C, 915 MHz (ZS = ZL = 50Ω), unless otherwise noted
15
20
25
30
35
40
‐2.5 ‐2‐1.5 ‐1‐0.5
P1dB(dBm)
VCTRL (V)
P1dB@–55°C(dBm) P1dB@25°C(dBm) P1dB@85°C(dBm)
Product Specification
PE45140
Page 8 of 12
Document No. DOC-44014-4 │ UltraCM OS® RFIC Solutions ©2014 Peregrine Semiconductor Corp. All rights reserved.
Figure 15. P1dB, IIP3, IIP2, Leakage Power @
PMAX vs. VCTRL
Figure 12. IIP3 / IIP2 vs. VCTRL Over Temperature Figure 13. IIP3 / IIP2 vs. PIN Over VCTRL
20
30
40
50
60
70
80
90
100
110
120
10 15 20 25 30 35
IIP3/IIP2(dBm)
Pin(dBm)
IIP3@VCTRL=–2.5V(dBm) IIP2@VCTRL=–2.5V(dBm) IIP3@VCTRL=–1.5V(dBm)
IIP2@VCTRL=–1.5V(dBm) IIP3@VCTRL=–0.7V(dBm) IIP2@VCTRL=–0.7V(dBm)
IIP3@VCTRL=–0.5V(dBm) IIP2@VCTRL=–0.5V(dBm)
18
20
22
24
26
28
30
32
34
36
38
10
20
30
40
50
60
70
80
90
100
110
‐2.5 ‐2‐1.5 ‐1‐0.5
LeakagePower@P
max
(dBm)
P1dB/IIP3/IIP2(dBm)
V
CTRL
(V)
P1dB(dBm) IIP3(dBm) IIP2(dBm) LeakagePower@Pmax
Typical Performance Data @ +25°C, 915 MHz (ZS = ZL = 50Ω), unless otherwise noted
30
40
50
60
70
80
90
100
110
120
130
‐2.5 ‐2‐1.5 ‐1‐0.5
IIP3/IIP2(dBm)
V
CTRL
(V)
IIP3@–55°C(dBm) IIP3@25°C(dBm) IIP3@85°C(dBm)
IIP2@–55°C(dBm) IIP2@25°C(dBm) IIP2@85°C(dBm)
Figure 14. Leakage Power @ PMAX vs. VCTRL
Over Temperature
‐10
‐5
0
5
10
15
20
25
30
35
40
‐2.5 ‐2‐1.5 ‐1‐0.5 0 0.5 1 1.5 2 2.5
LeakagePower(dBm)
V
CTRL
(V)
LeakagePower(–55°C)@PmaxLeakagePower(25°C)@Pmax
LeakagePower(85°C)@Pmax
Product Specification
PE45140
Page 9 of 12
Document No. DOC-44014-4 │www.psemi.com ©2014 Peregrine Semiconductor Corp. All rights reserved.
Evaluation Kit
The power limiter EVK board was designed to
ease customer evaluation of Peregrine’s
PE45140. The bi-directional RF input and
output are connected to RF1 and RF2 port
through a 50Ω transmission line via SMA
connectors J2 and J3. A through 50Ω
transmission line is available via SMA
connectors J5 and J6. This transmission line
can be used to estimate the loss of the PCB
over the environmental conditions being
evaluated. The 2-pin connectors J1 and J4
are connected to the external DC voltage VDC
and VCTRL, respectively.
The board is constructed of a four metal layer
material with a total thickness of 62 mils. The
top RF layer is Rogers RO4350B material with
a 6.6 mil RF core and Er = 3.66. The middle
layers provide ground for the transmission
lines. The transmission lines were designed
using a coplanar waveguide with ground
plane model using a trace width of 13.5 mils,
trace gaps of 10 mils, and metal thickness of
2.1 mils.
Figure 16. Evaluation Board Layout
PRT-51452
Product Specification
PE45140
Page 10 of 12
Document No. DOC-44014-4 │ UltraCM OS® RFIC Solutions ©2014 Peregrine Semiconductor Corp. All rights reserved.
Figure 17. Evaluation Board Schematic
DOC-44027
Caution: Contains parts and assemblies susceptible to damage by electrostatic discharge (ESD)
50 OHM
50 OHM 50 OHM
THRU
J2 J3
R1
0Ohm
C3
DNI
R2
0Ohm
C4
DNI
1GND
2RF1
3GND
4GND
5VCTRL
6GND
7
GND 8
RF2 9
GND
10
N/C 11
VDC 12
N/C
13 DAP
U1
PE45140
1
12
2
J1
HEADER2
1
12
2
J4
HEADER2
J5 J6
C1
DNI
C2
DNI
VDC
Product Specification
PE45140
Page 11 of 12
Document No. DOC-44014-4 │www.psemi.com ©2014 Peregrine Semiconductor Corp. All rights reserved.
TOP VIEW BOTTOM VIEW
SIDE VIEW
RECOMMEND E D LAND PATTERN
A0.10 C
(2X)
C
0.10 C
0.05 C
SEATIN G PLAN E
B
0.10 C
(2X)
0.10 C A B
0.05 C
ALL FEATURES
PIN #1 CO R NE R
3.00
3.00
0.50±0.05
0.02
0.152
Ref.
1.80±0.10
1.80±0.10
1.00
Ref.
0.50
0.25±0.05
(x12)
0.30±0.05
(x12)
(x8)
0.30
(x12)
0.70
(x12)
1.90
3.80
3.101.90
0.50
(x8)
Figure 18. Package Drawing
12-lead 3x3 mm QFN
Figure 19. Top Marking Specifications
DOC-52193
45140
YYWW
ZZZZZ
DOC-51207
= Pin 1 designator
45140 = Five digit part number
YYWW = Date code, last two digits of the year and work week
ZZZZZ = Five digits of the lot number
Product Specification
PE45140
Page 12 of 12
Document No. DOC-44014-4 │ UltraCM OS® RFIC Solutions ©2014 Peregrine Semiconductor Corp. All rights reserved.
Advance Information:
The product is in a formative or design stage. The datasheet contains design target
specifications for product development. Specifications and features may change in any manner without notice.
Preliminary Specification:
The datasheet contains preliminary data. Additional data may be added at a later
date. Peregrine reserves the right to change specif ications at any time without notice in order to supply the best
possible product.
Product Specification:
The datasheet contains final data. In the event Peregri ne decides to
change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer
Notification Form).
The informatio n in this datasheet i s believed to b e reliable. Ho wever, Peregrin e assume s no liability for the us e
of this inf o r m ati o n. U s e s hal l b e ent i rel y at th e u se r’ s o w n ri sk.
No patent rights or licenses t o any circuits described in this datasheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in devices or systems intended for surgi cal implant,
or in other applications intended to support or sustain life, or in any application in which the failure of the
Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no
liability for damages, including consequential or incidental damages, arising out of the use of its products in
such applications.
The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE
are trademarks of Peregrine Semiconductor Corp. Peregrine products are protected under one or more of the
following U.S. Patents: http://patents.psemi.com.
Sales Contact and Information
For sales and contact information please visit www.psemi.com.
Table 6. Ordering Information
Order Code Description Package Shipping Method
PE45140A-X PE45140 Power limiter Green 12-lead 3x3 mm QFN 500 units / T&R
EK45140-02 PE45140 Evaluation kit Evaluation kit 1 / box
Figure 20. Tape and Reel Drawing
