INTEGRATED CIRCUITS DATA SEE | The [CO4 LOCMOS HE40008 Logie Fariy Soeciieations HEP, HEC | os The [C04 LOCMOS HE40008 Logie HEF4044B MSI Outputs For a complete data sheal, pease alsa download! Package Ouilines/infarmation HEF, AEG Quadruple R/S latch with 3-state Product specification File under Integrated Circuits, |C04 Philips Semiconductors PHILIPS January 1995 PHILIPSPhilips Semiconductors Product specification . HEF4044B Quadruple R/S latch with 3-state outputs MSI The HEF4044B is a quadruple R/S latch with 3-state outputs with a common output enable input (EO). Each MBL S| ag 3 ee es latch has an active LOW set input (So to S3), an active Voor $3 Ry Og Ro Sz, O72 O; LOW reset input (Rg ta R3) and an active HIGH 3-state > HEFLOLLB output (Qg to Q3). _ 8 8 3 nc, Sa Ro EO Ry 34 Ves When EO is HIGH, the state of the latch output (O,) can be determined from the function table below. When EO is LOW, the latch outputs are in the high impedance OFF-state. EO does not affect the state of the latch. The high impedance off-state feature allows common busing of the outputs. 3| So 7? a So |13 R Ayo, 7| 83 EY OL 1/9 R S11, 3-STATE = OUTPUTS 11] S2 | _ ? || O2h10 R 2|026 15/83 yo 03/4 5 | 14/R3 5/E0 | 72736389.3 Fig.1 Functional diagram. January 1995 1 2 3 a 5 6 7 a TETIGAB 2 Fig.2 Pinning diagram. HEF4044BP(N): 16-lead DIL; plastic (SOT38-1) HEF4044BD(F}: 16-lead DIL; ceramic (cerdip) (SOT?74) HEF4044BT(D): 16-lead SO; plastic (SOT109-1)} (): Package Designator North America PINNING EO common oulpui enable input So to 83 sel inputs (active LOW) Ro to Rg reset inputs (active LOW) Op ta Og 3-state buffered latch outputs FUNCTION TABLE Inpurs = OUTPUT EO Sh Ry oO, L Xx x Z H L H H H X L L H H H latched Notes 1. H=HIGH state (ihe more positive voltage) L = LOW state (the less positive voltage) X = state immaterial Z = high impedance OFF-state FAMILY DATA, Ipp LIMITS category MSI See Family SpecificationsPhilips Semiconductors Product specification HEF4044B Quadruple R/S latch with 3-state outputs MSI > t> 7Z82342 Fig.4 Logic diagram (one latch). EO | > 7273812.3 Fig.3 Logic diagram. January 1995 3Philips Semiconductors Product specification Quadruple R/S latch with 3-state outputs HEF4044B MSI AC CHARACTERISTICS Vss = 0 V; Tamb = 25C; C_ = 50 pF; input transition times s 20 ns Vv TYPICAL EXTRAPOLATION v SYMBOL |MIN. TYP. MAX. FORMULA Propagation delays Rn On 5 90 185 ns 638ns + (0,55 ns/pF) Cy HIGH to LOW 10 tPHL 40 80 ns 29ns + (0,23 ns/pF} CL 15 30 60 ns 22ns + (0,16 ns/pF) CG, Sn On 5 90 180 ns 638ns + (0,55 ns/pF) CL LOW to HIGH 10 tPLH 40 80 ns 29ns + (0,23 ns/pF) C, 15 30 60 ns 22ns + (0,16 ns/pF) CL Output transition 5 60 120 ns 10 ns + (1,0 ns/pF) C, times 10 HL 30 60 ns 9ns + (0,42 ns/pF) C, HIGH to LOW 15 20 40 ns 6ns + (0,28 ns/pF) C. 5 60 =120 ns 10ns + (1,0 ns/pF) CL LOW to HIGH 10 LH 30 60 ns 9ns + (0,42 ns/pF) C. 15 20 40 ns 6ns + (0,28 ns/pF) C. 3-siate propagation delays Qutput disable times EO> On 5 50 =100 ~ns HIGH 10 tpHz 30 60 ns 15 25 50 ns 5 30 60 ns LOW 10 tpiz 25 45 ns 15 20 40 ns Output enable times EQ > On 5 50 =6100 ns HIGH 10 Ip7H 25 50 ns 15 20 40 ns 5 50 95 ns LOW 10 ipa 25 45 ns 15 20 35 ns Minimum S, 5 30 15 ns pulse width; LOW 10 RWSL 20 10 ns 15 16 8 ns see also waveforms Minimum R, 5 30 15 ns Fig.5 pulse width; LOW 10 tWRL 20 10 ns 15 16 8 ns January 1995 4Philips Semiconductors Product specification . HEF4044B Quadruple R/S latch with 3-state outputs MSI vo TYPICAL FORMULA FOR P (uW) Dynamic power 5 1300 f+ 2 (fgCL) x Vpp 2 where dissipation per 10 5200 f+ E (foCL) x Vpp 2 f= input freq. (MHz) package (P) 15 12 900 f+ E (foCL) x Von 2 fg = output freq. (MHz) C, = total load capacitance (pF) X (f,C_) = sum of outpuis Vpp = supply voltage (V) _ R,, INPUT 50% S,, INPUT 50% 'WRL j twsLe 7273813.1 Fig.6 Waveforms showing minimum S,, and R, pulse widths. APPLICATION INFORMATION An example of application for the HEF4044B is: Four-bit storage with output enable January 1995 5