
AN74
Rev. 0.2 3
2.4. Low Voltage VDD Supply
The low-voltage supply provides a switchable 3.3 V or
5 V output with a 1 A maximum load current. The
schematic for this power supply circuit is illustrated in
Figure 4 on page 5. The LT1375 IC integrated 1.5 A
bipolar switching transistor and current-sensing circuitry
eliminate external power transistors and sense resistors
and provide a high-efficiency VDD supply in a small
footprint. The switching frequency is internally fixed at
500 kHz and can be synchronized to higher frequencies
up to 1 MHz when a higher frequency signal (above
550 kHz) is provided on the SYNC pin. Table 3 provides
the jumper settings for selecting a 3.3 V or 5 V output as
well as for disconnecting the VDD supply altogether.
2.5. Frequency Synchronization
The LTC3704 is wired as a clock master device to
provide its switching frequency to the SYNC pin on the
LT1375 IC. To synchronize the frequency between the
two power circuits, R18 needs to be adjusted to set the
LTC3704 switching frequency at or above 550 kHz. The
LT1375 IC operates at its internal fixed 500 kHz and is
only synchronized with the LTC3704 frequency when it
senses the frequency on the SYNC pin going above
550 kHz. The SiLinkPS-EVB power circuits are
designed to operate safely with switching frequency on
the LTC3704 ranging from 200 kHz to 1 MHz.
2.6. Initialization Steps
1. Configure all jumpers according to the application
requirements.
2. (Optional) Plug in the input power source and
measure all outputs to verify correct settings.
3. Unplug input power source.
4. Assemble all ProSLIC daughter cards.
5. Plug in the input power source.
2.7. Cost-Optimized Design
The negative high-voltage circuit can be reduced for
cost optimization. The four equal VNEG outputs in
series arrangement provide some discrete voltage
adjustments to the outputs but require additional
rectifying diode circuits and increase cost. Figure 6 on
page 8 illustrates a lost-optimized design with two
negative outputs. The first secondary winding produces
a negative voltage according to the VNEG equation
described in the previous section to produce the VBLO
voltage. The other three secondary windings are
connected in series to produce a negative voltage with
an amplitude of 3 x VNEG. This output is connected in
series with the VBLO output to generate VBHI output
with a voltage level of 4 x VNEG.
The use of the simplified secondary rectifying circuit,
smaller transformer, and switching MOSFET lower the
component costs and also reduce the maximum output
power of the negative high-voltage circuit to 13 W.
Table 3. VDD Supply Jumper Settings
Function JP5 JP6 Comments
VDD output
enable
— 1–2 VDD connected
— 2–3 VDD disconnected
3.3 V/5 V
configuration
1–2 — 5 V selected
2–3 — 3.3 V selected