FEATURES 10 mV sensitivity rail to rail at VCC = 2.5 V Input common-mode voltage from -0.2 V to VCC + 0.2 V Low glitch CMOS-/TTL-compatible output stage 3 ns propagation delay 15 mW at 3.3 V Shutdown pin Single-pin control for programmable hysteresis and latch Power supply rejection > 60 dB Improved replacement for MAX999 -40C to +125C operation FUNCTIONAL BLOCK DIAGRAM NONINVERTING INPUT INVERTING INPUT ADCMP600/ ADCMP601/ ADCMP602 LE/HYS (Except ADCMP600) SDN (ADCMP602 Only) Q OUTPUT 05914-001 Preliminary Technical Data Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparators ADCMP600/ADCMP601/ADCMP602 Figure 1. APPLICATIONS High speed instrumentation Clock and data signal restoration Logic level shifting or translation Pulse spectroscopy High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current-/voltage-controlled oscillators Automatic test equipment (ATE) GENERAL DESCRIPTION The ADCMP600, ADCMP601, and ADCMP602 are very fast comparators fabricated on Analog Devices' proprietary XFCB2 process. These comparators are exceptionally versatile and easy to use. Features include an input range from VEE - 0.5 V to VCC + 0.5 V, low noise TTL-/CMOS-compatible output drivers, and latch inputs with adjustable hysteresis and/or shutdown inputs. The devices offer 3 ns propagation delay with 5 mV overdrive on 4 mA typical supply current. A flexible power supply scheme allows the devices to operate with a single +2.5 V positive supply and a -0.5 V to +3.0 V input signal range up to a +5.5 V positive supply with a -0.5 V to +6 V input signal range. Split input/output supplies with no sequencing restrictions on the ADCMP602 support a wide input signal range while still allowing independent output swing control and power savings. The TTL-/CMOS-compatible output stage is designed to drive up to 5 pF with full timing specs and to degrade in a graceful and linear fashion as additional capacitance is added. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. High speed latch and programmable hysteresis features are also provided with a unique single-pin control option. The ADCMP600 is available in both 5-lead SC70 and SOT-23 packages, the ADCMP601 is available in a 6-lead SC70 package, and the ADCMP602 is available in 8-lead MSOP and LSCFP packages. Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved. ADCMP600/ADCMP601/ADCMP602 Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 Power/Ground Layout and Bypassing........................................9 Applications....................................................................................... 1 TTL-/CMOS-Compatible Output Stage ....................................9 Functional Block Diagram .............................................................. 1 Using/Disabling the Latch Feature..............................................9 General Description ......................................................................... 1 Optimizing Performance........................................................... 10 Revision History ............................................................................... 2 Comparator Propagation Delay Dispersion ........................... 10 Electrical Characteristics ................................................................. 3 Comparator Hysteresis .............................................................. 10 Absolute Maximum Ratings............................................................ 5 Crossover Bias Point .................................................................. 11 Thermal Resistance ...................................................................... 5 Minimum Input Slew Rate Requirement ................................ 11 ESD Caution.................................................................................. 5 Typical Application Circuits ......................................................... 12 Pin Configuration and Function Descriptions............................. 6 Timing Information ....................................................................... 13 Typical Performance Characteristics ............................................. 7 Application Information.................................................................. 9 REVISION HISTORY 3/06--Revision PrA: Preliminary Version Rev. PrA | Page 2 of 16 Preliminary Technical Data ADCMP600/ADCMP601/ADCMP602 ELECTRICAL CHARACTERISTICS VCCI = VCCO = 2.5 V, TA = 25C, unless otherwise noted. Table 1. Parameter DC INPUT CHARACTERISTICS Voltage Range Common-Mode Range Differential Voltage Offset Voltage Bias Current Offset Current Capacitance Resistance, Differential Mode Resistance, Common Mode Active Gain Common-Mode Rejection Symbol Conditions Min VP, VN VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V -0.5 -0.2 VOS IP, IN -5.0 -5.0 2.0 CP, CN 0.1 V to VCC -0.5 V to VCC + 0.5 V AV CMRR VCCI = 2.5 V, VCCO = 2.5 V, VCM = -0.2 V to +2.7 V VCCI = 5.5 V, VCCO = 3.3 V, VCM = -0.2 V to +6.0 V Hysteresis ADCMP600 Hysteresis ADCMP601/ADCMP602 LATCH ENABLE PIN CHARACTERISTICS (ADCMP601/ADCMP602 Only) VIH VIL IIH IOL HYSTERESIS MODE AND TIMING Hysteresis Mode Bias Voltage Minimum Resistor Value Latch Setup Time Latch Hold Time Latch-to-Output Delay Latch Minimum Pulse Width SHUTDOWN PIN CHARACTERISTICS (ADCMP602 Only) VIH VIL IIH IOL Sleep Time Wake-Up Time DC OUTPUT CHARACTERISTICS Output Voltage High Level Output Voltage Low Level 1.5 RHYS = tS tH tPLOH, tPLOL tPL tSD tH VOH VOL Hysteresis is shut off Latch mode guaranteed VIH = VCC VIL = 0.4 V 2.0 -0.2 Current sink 0 A Hysteresis = 16 mV VOD = 100 mV VOD = 100 mV VOD = 100 mV VOD = 100 mV 1.145 150 Comparator is operating Shutdown guaranteed VIH = VCC VIL = 0 V ICC < 500 A VOD = 10 mV, output valid VCCO = 2.5 V to 6 V IOH = 12 mA, VCCO = 2.5 V IOL = 12 mA, VCCO = 2.5 V 2.0 -0.2 Rev. PrA | Page 3 of 16 Typ Max Unit VCC + 0.5 V VCC + 0.2 V VCC +5.0 +5.0 2.0 TBD 100 100 85 50 V V V mV A A pF k k dB dB 60 dB 2.0 2 0.1 +0.4 1.25 2.5 mV mV VCC +0.8 0.2 -0.2 V V mA mA 1.35 V k ns ns ns ns VCCO +0.6 0.3 -0.3 V V mA mA ns ns 2 5 3 3 +0.4 60 40 VCC - 0.4 0.4 V V ADCMP600/ADCMP601/ADCMP602 Parameter AC PERFORMANCE Propagation Delay Symbol Conditions tPD VCCO = 2.5 V to 5.5 V VOD = 5 mV VCCO = 2.5 V to 5.5 V VOD = 200 mV VOD = 50 mV Propagation Delay Skew--Rising to Falling Transition Overdrive Dispersion Slew Rate Dispersion Pulse-Width Dispersion 10% to 90% Duty Cycle Dispersion Common-Mode Dispersion Toggle Rate Deterministic Jitter TTL/CMOS Outputs RMS Random Jitter DJ Minimum Pulse Width Rise Time PWMIN tR Fall Time tF POWER SUPPLY Input Supply Voltage Range Output Supply Voltage Range Positive Supply Differential (ADCMP602 Only) Positive Supply Differential (ADCMP602 Only) Positive Supply Current Input Section Supply Current (ADCMP602 Only) Output Section Supply Current (ADCMP602 Only) Power Dissipation Power Supply Rejection Preliminary Technical Data RJ VCCI VCCO VCCI - VCCO VCCI - VCCO IVCC IVCCI Min 10 mV < VOD < 2.5 V 0.05 V/ns to 2.5 V/ns 3 ns to 30 ns VOD = 5 V, 1 V/ns, VCM = 2.5 V 0 < VCM < VCC >50% output swing, CLOAD = 5 pF, VCCO = 5 V VOD = 200 mV, 5 V/ns, PRBS31 - 1 NRZ, 0.25 Gbps VOD = 200 mV, 5 V/ns, PRBS31 - 1 NRZ, 0.525 Gbps tPD/PW < 50 ps 10% to 90%, CLOAD = 5 pF, VCCO = 5 V 10% to 90%, CLOAD = 5 pF, VCCO = 5 V Typ Max Unit 3 ns 2 ns 200 ps TBD TBD TBD TBD TBD TBD ps ps ps ps ps Mbps TBD ns TBD ps 3 2.0 ns ns 2.0 ns Operating 2.5 2.5 -3.0 5.5 5.5 +3.0 V V V Nonoperating -5.5 +5.5 V VCC = 2.5 V VCCI = 2.5 V to 5 V 3 0.8 mA mA IVCCO VCCI = 2.5 V to 5.5 V 2 mA PD PD PSRR VCC = 2.5 V VCC = 5.5 V VCCI = 2.5 V to 5 V 9 20 -50 mW mW dB Rev. PrA | Page 4 of 16 Preliminary Technical Data ADCMP600/ADCMP601/ADCMP602 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltages Input Supply Voltage (VCCI to GND) Output Supply Voltage (VCCO to GND) Positive Supply Differential (VCCI - VCCO) Input Voltages Input Voltage Differential Input Voltage Maximum Input/Output Current Shutdown Control Pin Applied Voltage (HYS to GND) Maximum Input/Output Current Latch/Hysteresis Control Pin Applied Voltage (HYS to GND) Maximum Input/Output Current Output Current Temperature Operating Temperature, Ambient Operating Temperature, Junction Storage Temperature Range Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating -0.5 V to +6.0 V -0.5 V to +6.0 V -6.0 V to +6.0 V -0.5 V to VCCI + 0.5 V (VCCI + 0.5 V) 50 mA THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance -0.5 V to VCCO + 0.5 V 50 mA -0.5 V to VCCO + 0.5 V 50 mA 50 mA Package Type ADCMP600 SC70 5-lead ADCMP600 SOT-23 5-lead ADCMP601 SC70 6-lead ADCMP602 MSOP 5-lead 1 Measurement in still air. -40C to +125C 150C -65C to +150C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrA | Page 5 of 16 JA 1 426 302 426 130 Unit C/W C/W C/W C/W ADCMP600/ADCMP601/ADCMP602 Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 6 4 VN VCCI /VCCO VCCI 1 ADCMP601 VEE 2 TOP VIEW (Not to Scale) VP 3 Q 1 VCCI /VCCO Figure 2. ADCMP600 Pin Configuration 5 LE/HYS TOP VIEW (Not to Scale) VP 3 4 VN VP 2 Figure 3. ADCMP601 Pin Configuration VN 3 SDN 4 ADCMP602 TOP VIEW (Not to Scale) 8 VCCO 7 Q 6 VEE 5 LE/HYS 05914-004 5 05914-003 VEE 2 ADCMP600 05914-002 Q 1 Figure 4. ADCMP602 Pin Configuration Table 4. ADCMP600 (SOT-23-5 and SC70-5) Pin Function Descriptions Pin No. 1 Mnemonic Q 2 3 4 5 VEE VP VN VCCI/VCCO Description Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN. Negative Supply Voltage. Noninverting Analog Input. Inverting Analog Input. Input Section Supply/Output Section Supply. Shared pin. Table 5. ADCMP601 (SC70-6) Pin Function Descriptions Pin No. 1 Mnemonic Q 2 3 4 5 6 VEE VP VN LE/HYS VCCI/VCCO Description Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, provided that the comparator is in compare mode. Negative Supply Voltage. Noninverting Analog Input. Inverting Analog Input. Latch/Hysteresis Control. Bias with resistor or current for hysteresis adjustment; drive low to latch. Input Section Supply/Output Section Supply. Shared pin. Table 6. ADCMP602 (MSOP-8) Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 Mnemonic VCCI VP VN SDN LE/HYS VEE Q 8 VCCO Description Input Section Supply. Noninverting Analog Input. Inverting Analog Input. Shutdown. Drive this pin low to shut down the device. Latch/Hysteresis Control. Bias with resistor or current for hysteresis adjustment; drive low to latch. Negative Supply Voltage. Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, provided that the comparator is in compare mode. Output Section Supply. Rev. PrA | Page 6 of 16 Preliminary Technical Data ADCMP600/ADCMP601/ADCMP602 TYPICAL PERFORMANCE CHARACTERISTICS VCCI = VCCO = 2.5 V, TA = 25C, unless otherwise noted. Figure 5. Propagation Delay vs. Input Overdrive Figure 8. Hysteresis vs. VCC Figure 6. Propagation Delay vs. Input Common Mode Figure 9. Hysteresis vs. RHYS Control Resistor Figure 7. Propagation Delay vs. Temperature Figure 10. Input Bias Current vs. Input Common Mode Rev. PrA | Page 7 of 16 ADCMP600/ADCMP601/ADCMP602 Preliminary Technical Data Figure 11. Input Bias Current vs. Temperature Figure 13. Latch/Hysteresis Control Pin I/V Characteristics Figure 12. Input Offset Voltage vs. Temperature Rev. PrA | Page 8 of 16 Preliminary Technical Data ADCMP600/ADCMP601/ADCMP602 APPLICATION INFORMATION The ADCMP600/ADCMP601/ADCMP602 comparators are very high speed devices. Despite the low noise output stage, it is essential to use proper high speed design techniques to achieve the specified performance. Because comparators are uncompensated amplifiers, feedback in any phase relationship is likely to cause oscillations or undesired hysteresis. Of critical importance is the use of low impedance supply planes, particularly the output supply plane (VCCO) and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. It is also important to adequately bypass the input and output supplies. Multiple high quality 0.01 F bypass capacitors should be placed as close as possible to each of the VCCI and VCCO supply pins and should be connected to the GND plane with redundant vias. At least one of these should be placed to provide a physically short return path for output currents flowing back from ground to the VCC pin. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. Parasitic layout inductance should also be strictly controlled to maximize the effectiveness of the bypass at high frequencies. If the package allows and the input and output supplies have been connected separately such that VCCI VCCO, care should be taken to bypass each of these supplies separately to the GND plane. A bypass capacitor should never be connected between them. It is recommended that the GND plane separate the VCCI and VCCO planes when the circuit board layout is designed to minimize coupling between the two supplies and to take advantage of the additional bypass capacitance from each respective supply to the ground plane. This enhances the performance when split input/output supplies are used. If the input and output supplies are connected together for single-supply operation such that VCCI = VCCO, coupling between the two supplies is unavoidable; however, careful board placement can help keep output return currents away from the inputs. TTL-/CMOS-COMPATIBLE OUTPUT STAGE Specified propagation delay performance can be achieved only by keeping the capacitive load at or below the specified minimums. The outputs of the ADCMP600/ADCMP601/ADCMP602 are designed to directly drive one Schottky TTL or three low power Schottky TTL loads or equivalent. For large fan outputs, buses, or transmission lines, an appropriate buffer should be used to maintain the comparator's excellent speed and stability. With the rated 5 pF load capacitance applied, more than half of the total device propagation delay is output stage slew time, even at 2.5 V VCC. Because of this, the total prop delay decreases as VCCO decreases, and instability in the power supply may appear as excess delay dispersion. This delay is measured to the 50% point for the supply in use; therefore, the fastest times are observed with the VCC supply at 2.5 V, and larger values are observed when driving loads that switch at other levels. When duty cycle accuracy is critical, the logic being driven should switch at 50% of VCC and load capacitance should be minimized. When in doubt, it is best to power VCCO or the entire device from the logic supply and rely on the input PSRR and CMRR to reject noise. Overdrive and input slew rate dispersions are not significantly affected by output loading and VCC variations. The TTL-/CMOS-compatible output stage is shown in the simplified schematic diagram (Figure 14). Because of its inherent symmetry and generally good behavior, this output stage is readily adaptable for driving various filters and other unusual loads. VLOGIC A1 Q1 +IN -IN OUTPUT AV A2 GAIN STAGE Q2 OUTPUT STAGE 05914-014 POWER/GROUND LAYOUT AND BYPASSING Figure 14. Simplified Schematic Diagram of TTL-/CMOS-Compatible Output Stage USING/DISABLING THE LATCH FEATURE The latch input is designed for maximum versatility. It can safely be left floating for fixed hysteresis or be tied to VCC to remove the hysteresis, or it can be driven low by any standard TTL/CMOS device as a high speed latch. In addition, the pin can be operated as a hysteresis control pin with a bias voltage of 1.25 V nominal and an input resistance of approximately 7000 , allowing the comparator hysteresis to be easily and accurately controlled by either a resistor or an inexpensive CMOS DAC. Hysteresis control and latch mode can be used together if an open drain, an open collector, or a three-state driver is connected parallel to the hysteresis control resistor or current source. Rev. PrA | Page 9 of 16 ADCMP600/ADCMP601/ADCMP602 Preliminary Technical Data Due to the programmable hysteresis feature, the logic threshold of the latch pin is approximately 1.1 V regardless of VCC. INPUT VOLTAGE 1V/ns VN VOS OPTIMIZING PERFORMANCE 10V/ns COMPARATOR PROPAGATION DELAY DISPERSION The ADCMP600/ADCMP601/ADCMP602 comparators are designed to reduce propagation delay dispersion over a wide input overdrive range of 5 mV to TBD. Propagation delay dispersion is the variation in propagation delay that results from a change in the degree of overdrive or slew rate (that is, how far or how fast the input signal exceeds the switching threshold). Figure 16. Propagation Delay--Slew Rate Dispersion COMPARATOR HYSTERESIS The addition of hysteresis to a comparator is often desirable in a noisy environment, or when the differential input amplitudes are relatively small or slow moving. Figure 17 shows the transfer function for a comparator with hysteresis. As the input voltage approaches the threshold (0.0 V, in this example) from below the threshold region in a positive direction, the comparator switches from low to high when the input crosses +VH/2, and the new switching threshold becomes -VH/2. The comparator remains in the high state until the new threshold, -VH/2, is crossed from below the threshold region in a negative direction. In this manner, noise or feedback output signals centered on 0.0 V input cannot cause the comparator to switch states unless it exceeds the region bounded by VH/2. OUTPUT Propagation delay dispersion is a specification that becomes important in high speed, time-critical applications, such as data communication, automatic test and measurement, and instrumentation. It is also important in event-driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. Dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed (Figure 15 and Figure 16). ADCMP600/ADCMP601/ADCMP602 dispersion is typically <TBD ps as the overdrive varies from 5 mV to 500 mV and the input slew rate varies from TBD V/ns to TBD V/ns. This specification applies to both positive and negative signals because the device has very closely matched delays both for positive-going and negative-going inputs. 500mV OVERDRIVE INPUT VOLTAGE 10mV OVERDRIVE DISPERSION Q/Q OUTPUT 05914-015 VN VOS Figure 15. Propagation Delay--Overdrive Dispersion 05914-016 DISPERSION Q/Q OUTPUT VOH VOL -VH 2 0 +VH 2 INPUT 05914-017 As with any high speed comparator, proper design and layout techniques are essential for obtaining the specified performance. Stray capacitance, inductance, inductive power and ground impedances, or other layout issues can severely limit performance and often cause oscillations. Large discontinuities along input and output transmission lines can also limit the specified pulsewidth dispersion performance. The source impedance should be minimized as much as is practicable. High source impedance, in combination with the parasitic input capacitance of the comparator, causes an undesirable degradation in bandwidth at the input, thus degrading the overall response. Thermal noise from large resistances can easily cause extra jitter with slowly slewing input signals; higher impedances encourage undesired coupling. Figure 17. Comparator Hysteresis Transfer Function The customary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input. One limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that is not symmetric about the threshold. The external feedback network can also introduce significant parasitics that reduce high speed performance and induce oscillation in some cases. The ADCMP600 features a fixed hysteresis of approximately 2 mV. The ADCMP601 and ADCMP602 comparators offer a programmable hysteresis feature that can significantly improve accuracy and stability. Connecting an external pull-down resistor or a current source from the LE/HYS pin to GND, varies the amount of hysteresis in a predictable, stable manner. Rev. PrA | Page 10 of 16 Preliminary Technical Data ADCMP600/ADCMP601/ADCMP602 Leaving the LE/HYS pin disconnected results in a fixed hysteresis of 2 mV; driving this pin high removes the hysteresis. The maximum hysteresis that can be applied using this pin is approximately 160 mV. Figure 18 illustrates the amount of hysteresis applied as a function of the external resistor value, and Figure TBD illustrates hysteresis as a function of the current. The hysteresis control pin appears as a 1.25 V bias voltage seen through a series resistance of 7k 20% throughout the hysteresis control range. The advantages of applying hysteresis in this manner are improved accuracy, improved stability, reduced component count, and maximum versatility. An external bypass capacitor is not recommended on the HYS pin because it impairs the latch function and often degrades the jitter performance of the device. As described in the Using/Disabling the Latch Feature section, hysteresis control need not compromise the latch function. Figure 18. Hysteresis vs. RHYS Control Resistor MINIMUM INPUT SLEW RATE REQUIREMENT (Remove if device is stable.) CROSSOVER BIAS POINT In both op amps and comparators, rail-to-rail inputs of this type have a dual front-end design. Certain devices are active near the VCC rail and others are active near the VEE rail. At some predetermined point in the common-mode range, a crossover occurs. At this point, normally VCC/2, the direction of the bias current reverses and the measured offset voltages and currents change. The ADCMP600/ADCMP601/ADCMP602 slightly elaborate on this scheme. With VCC less than 4 V, this crossover is at the expected VCC/2, but with VCC greater than 4 V, the crossover point instead follows VCC 1:1, bringing it to approximately 3 V with VCC at 5 V. This means that when VCC is greater than 4, the comparator input characteristics more closely resemble those of common types of inputs that are not rail to rail. As with most high speed comparators without hysteresis, a minimum slew rate must be met to ensure that the device does not oscillate as the input signal crosses the threshold. This oscillation is due to the high gain bandwidth of the comparator in combination with feedback parasitics inherent in the package and PC board. A minimum slew rate of TBD V/s ensures clean output transitions from the ADCMP601 or ADCMP602 comparator without hysteresis. In many applications, chattering is not harmful. Rev. PrA | Page 11 of 16 ADCMP600/ADCMP601/ADCMP602 Preliminary Technical Data TYPICAL APPLICATION CIRCUITS 2.5V ADCMP600 INPUT 1.25V 50mV INPUT 1.25V REF 5V CMOS PWM OUTPUT 10k 10k 0.1F ADCMP601 ADCMP600 OUTPUT 10k 82pF 0.1F LE/HYS 40k 05914-022 2k 05914-019 2k Figure 22. Oscillator and Pulse-Width Modulator Figure 19. Self-Biased, 50% Slicer 2.5V TO 5V ADCMP601 CMOS VDD 2.5V TO 5V DIGITAL INPUT ADCMP600 2.5V 10k 20k ADCMP601 100k OUTPUT 1.5MHz TO 30MHz LE/HYS 100k 05914-021 CONTROL VOLTAGE 0V TO 2.5V 82pF 10k Figure 23. Hysteresis Adjustment with Latch Figure 21. Voltage-Controlled Oscillator Rev. PrA | Page 12 of 16 05914-023 HYSTERESIS CURRENT Figure 20. LVDS-to-CMOS Receiver 20k LE/HYS CMOS 05914-020 100 74 AHC 1G07 Preliminary Technical Data ADCMP600/ADCMP601/ADCMP602 TIMING INFORMATION Figure 24 illustrates the ADCMP600/ADCMP601/ADCMP602 latch timing relationships. Table 7 provides definitions of the terms shown in the figure. 1.1V LATCH ENABLE tS tPL tH DIFFERENTIAL INPUT VOLTAGE VIN VN VOS VOD tPDL tPLOH Q OUTPUT tF 05914-025 50% Figure 24. System Timing Diagram Table 7. Timing Descriptions Symbol tPDH Timing Input to output high delay tPDL Input to output low delay tPLOH Latch enable to output high delay tPLOL Latch enable to output low delay tH Minimum hold time tPL tS Minimum latch enable pulse width Minimum setup time tR Output rise time tF Output fall time VOD Voltage overdrive Description Propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output low-to-high transition. Propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output high-to-low transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition. Minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs. Minimum time that the latch enable signal must be high to acquire an input signal change. Minimum time before the negative transition of the latch enable signal occurs that an input signal change must be present to be acquired and held at the outputs. Amount of time required to transition from a low to a high output as measured at the 20% and 80% points. Amount of time required to transition from a high to a low output as measured at the 20% and 80% points. Difference between the input voltages VA and VB. Rev. PrA | Page 13 of 16 ADCMP600/ADCMP601/ADCMP602 Preliminary Technical Data NOTES Rev. PrA | Page 14 of 16 Preliminary Technical Data ADCMP600/ADCMP601/ADCMP602 NOTES Rev. PrA | Page 15 of 16 ADCMP600/ADCMP601/ADCMP602 Preliminary Technical Data NOTES (c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05914-0-3/06(PrA) T T Rev. PrA | Page 16 of 16