W78LE365/W78L365A Data Sheet 8-BIT MICROCONTROLLER Table of Contents1. GENERAL DESCRIPTION ......................................................................................................... 3 2. FEATURES ................................................................................................................................. 3 3. PIN CONFIGURATIONS ............................................................................................................ 4 4. PIN DESCRIPTION..................................................................................................................... 5 5. FUNCTIONAL DESCRIPTION ................................................................................................... 6 5.1 RAM ................................................................................................................................ 6 5.2 Timers 0, 1 and 2............................................................................................................ 7 5.2.1 5.3 5.4 5.5 Clock ............................................................................................................................... 7 5.3.1 Crystal Oscillator ..............................................................................................................7 5.3.2 External Clock ..................................................................................................................7 Power Management........................................................................................................ 8 5.4.1 Idle Mode..........................................................................................................................8 5.4.2 Power-down Mode............................................................................................................8 5.4.3 Reduce EMI Emission ......................................................................................................8 Reset............................................................................................................................... 9 5.5.1 5.6 7. W78L365A Special Function Registers (SFRs) and Reset Values...................................9 Port 4 ............................................................................................................................ 10 5.6.1 Port Options Register .....................................................................................................10 5.6.2 INT2 / INT3 ..................................................................................................................10 5.6.3 Port 4 Base Address Registers ......................................................................................13 5.7 Pulse Width Modulated Outputs (PWM)....................................................................... 14 5.8 Watchdog Timer ........................................................................................................... 17 5.9 In-System Programming (ISP) Mode............................................................................ 19 5.9.1 6. Timer 2 Output .................................................................................................................7 In-System Programming Control Register (CHPCON) ...................................................20 5.10 Software Reset ............................................................................................................. 21 5.11 H/W Reboot Mode (Boot from LDROM) ....................................................................... 21 SECURITY ................................................................................................................................ 24 6.1 Lock Bit ......................................................................................................................... 24 6.2 MOVC Inhibit................................................................................................................. 24 6.3 Encryption ..................................................................................................................... 25 6.4 Oscillator Control .......................................................................................................... 25 ELECTRICAL CHARACTERISTICS......................................................................................... 26 -1- Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A 8. 9. 10. 11. 7.1 Absolute Maximum Ratings .......................................................................................... 26 7.2 D.C. Characteristics...................................................................................................... 26 7.3 A.C. Characteristics ...................................................................................................... 28 TIMING WAVEFORMS ............................................................................................................. 29 8.1 Program Fetch Cycle .................................................................................................... 29 8.2 Data Read Cycle........................................................................................................... 30 8.3 Data Write Cycle........................................................................................................... 31 8.4 Port Access Cycle......................................................................................................... 32 TYPICAL APPLICATION CIRCUIT........................................................................................... 33 9.1 External Program Memory and Crystal ........................................................................ 33 9.2 Expanded External Data Memory and Oscillator ......................................................... 34 PACKAGE DIMENSIONS ......................................................................................................... 35 10.1 40-pin DIP ..................................................................................................................... 35 10.2 44-pin PLCC ................................................................................................................. 35 10.3 44-pin PQFP ................................................................................................................. 36 10.4 48-pin LQFP.................................................................................................................. 36 APPLICATION NOTE ............................................................................................................... 37 11.1 12. In-system Programming Software Examples ............................................................... 37 REVISION HISTORY ................................................................................................................ 42 -2- W78LE365/W78L365A 1. GENERAL DESCRIPTION The W78L365A is an 8-bit microcontroller which has an in-system programmable Flash EPROM for firmware updating. The instruction set of the W78L365A is fully compatible with the standard 8052. The W78L365A contains a 64K bytes of main ROM and a 4K bytes of auxiliary ROM which allows the contents of the 64KB main ROM to be updated by the loader program located at the 4KB auxiliary ROM; 256+1K bytes of on-chip RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit port P4; three 16-bit timer/counters; a serial port. These peripherals are supported by a eight sources two-level interrupt capability. To facilitate programming and verification, the ROM inside the W78L365A allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security. The W78L365A microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor. 2. FEATURES * Fully static design 8-bit CMOS microcontroller * 64K bytes of in-system programmable Flash EPROM for Application Program (APROM) * 4K bytes of auxiliary ROM for Loader Program (LDROM) * 256+1K bytes of on-chip RAM. (Including 1K bytes of AUX-RAM, software selectable) * Four 8-bit bi-directional ports * One 4-bit multipurpose programmable port (I/O, interrupt, Chip select function) * Three 16-bit timer/counters * One full duplex serial port * Watchdog timer * Software Reset * P1.0 T2 programmable clock out * Eight-sources, two-level interrupt capability * Up to 20 MHz * Built-in power management * Code protection * Packaged in - Lead Free (RoHS) DIP 40: W78L365A24DL - Lead Free (RoHS) PLCC 44: W78L365A24PL - Lead Free (RoHS) QFP 44: W78L365A24FL - Lead Free (RoHS) LQFP 48: W78L365A24LL -3- Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A 3. PIN CONFIGURATIONS 44-pin PLCC 40-pin DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 T2, P1.0 T2EX, P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RXD, P3.0 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 WR, P3.6 RD, P3.7 XTAL2 XTAL1 VSS T 2 E X , P P P P 1 1 1 1 . . . . 4 3 2 1 VDD 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P0.0, AD0 P0.1, AD1 P0.2, AD2 P0.3, AD3 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 RXD, P3.0 INT2, P4.3 TXD, P3.1 PSEN P2.7, A15 P2.6, A14 P2.5, A13 P2.4, A12 P2.3, A11 P2.2, A10 P2.1, A9 P2.0, A8 A D 0 , P 0 . 0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3 6 5 4 3 2 1 44 43 42 41 40 7 39 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 18 19 20 21 22 23 24 25 26 27 28 P1.5 P1.6 P1.7 RST EA ALE / I N T T 2 3 , , P P 1 4 V . . D 0 2 D INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 X V P P P T S 4 2 2 A S . . . L 0 0 1 1 , , A A 8 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 P 2 . 4 , A 1 2 44-pin PQFP T 2 E X , P P P P 1 1 1 1 . . . . 4 3 2 1 P1.5 P1.6 P1.7 RST RXD, P3.0 INT2, P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 T 2 , P 1 . 0 / I A N D T 0 3 , , P P 4 V 0 . D . 2 D 0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 44 43 42 41 40 39 38 37 36 35 34 1 33 32 2 31 3 30 4 29 5 28 6 27 7 26 8 9 25 10 24 23 11 12 13 14 15 16 17 18 19 20 21 22 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 X V P P T S 4 2 A S . . L 0 0 1 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 48-pin LQFP A D 3 , P 0 . 3 P1.5 P1.6 P1.7 RST P3.0 P4.3 P3.1 P3.2 P3.3 P3.4 P3.5 NC P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 P 2 . 4 , A 1 2 -4- 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 NC P0.4 P0.5 P0.6 P0.7 EA P4.1 ALE PSEN P2.7 P2.6 P2.5 W78LE365/W78L365A 4. PIN DESCRIPTION SYMBOL TYPE DESCRIPTIONS EA I EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the external ROM. The ROM address and data will not be presented on the bus if the EA pin is high. PSEN O H PROGRAM STORE ENABLE: PSEN enables the external ROM data in the Port 0 address/data bus. When internal ROM access is performed, no PSEN strobe signal outputs originate from this pin. ALE O H ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. RST I L RESET: A high on this pin for two machine cycles while the oscillator is running resets the device. XTAL1 I CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an external clock. XTAL2 O CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1. VSS I GROUND: ground potential. VDD I POWER SUPPLY: Supply voltage for operation. P0.0-P0.7 I/O D PORT 0: Function is the same as that of standard 8052. P1.0-P1.7 I/O H PORT 1: Function is the same as that of standard 8052. PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory. The P2.6 P2.0-P2.7 I/O H P3.0-P3.7 I/O H PORT 3: Function is the same as that of the standard 8052. P4.0-P4.7 I/O H and P2.7 also provide the alternate function REBOOT which is H/W reboot from LD flash. PORT 4: A bi-directional I/O. The P4.3 also provide the alternate function REBOOT which is H/W reboot from LD flash. * Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain -5- Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A 5. FUNCTIONAL DESCRIPTION The W78L365A architecture consists of a core controller surrounded by various registers, four general purpose I/O ports, one special purpose programmable 4-bits I/O port, 256+1K bytes of RAM, three timer/counters, a serial port. The processor supports 111 different opcodes and references both a 64K program address space and a 64K data storage space. 5.1 RAM The internal data RAM in the W78L365A is 256+1K bytes. It is divided into two banks: 256 bytes of scratchpad RAM and 1K bytes of AUX-RAM. These RAMs are addressed by different ways. * RAM 0H-7FH can be addressed directly and indirectly as the same as in 8051. Address pointers are R0 and R1 of the selected register bank. * RAM 80H-FFH can only be addressed indirectly as the same as in 8051. Address pointers are R0, R1 of the selected registers bank. * AUX-RAM 0H-3FFH is addressed indirectly as the same way to access external data memory with the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and DPTR register. An access to external data memory locations higher than 3FFH will be performed with the MOVX instruction in the same way as in the 8051. The AUX-RAM is enable after a reset. Setting the bit 4 in CHPCON register will enable the access to AUX-RAM. When executing from internal program memory, an access to AUX-RAM will not affect the Ports P0, P2, WR and RD . Example: CHPENR CHPCON XRAMAH MOV MOV ORL MOV MOV MOV MOV MOVX MOV MOV MOVX MOV MOV MOVX MOV MOVX REG REG REG F6H BFH A1H CHPENR, #87H CHPENR, #59H CHPCON, #00010000B CHPENR, #00H XRAMAH, #01H R0, #23H A, #55H @R0, A XRAMAH, #02H R1, #FFH A, @R1 DPTR, #0134H A, #78H @DPTR,A DPTR, #7FFFH A, @DPRT ; enable AUX-RAM ; internal high address ; Write 55h data to 0123h AUX-RAM address. ; Read data from 02FFh AUX-RAM address. ; Write 78h data to 0134h AUX-RAM address. ; Read data from the external 7FFFh address SRAM -6- W78LE365/W78L365A 5.2 Timers 0, 1 and 2 Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1. 5.2.1 Timer 2 Output If set T2OE (T2MOD.1) bit and clear C/T2 (T2CON.1) bit at auto-reload mode, P1.0 will be toggled once overflow. TIMER 2 Mode Bit: 7 6 5 4 Mnemonic: T2MOD 3 2 1 T2OE 0 Address: C9H T2OE: Enable this bit to toggle P1.0 pin while Timer2 has been overflowed. 5.3 Clock The W78L365A is designed with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used by default. This makes the W78L365A relatively insensitive to duty cycle variations in the clock. 5.3.1 Crystal Oscillator The W78L365A incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground. 5.3.2 External Clock An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. -7- Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A 5.4 Power Management 5.4.1 Idle Mode Setting the IDL bit in the PCON register enters the idle mode. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs. 5.4.2 Power-down Mode When the PD bit in the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a hardware reset or external interrupts INT0 to INT1 when enabled and set to level triggered. 5.4.3 Reduce EMI Emission The W78L365A allows user to diminish the gain of on-chip oscillator amplifier by using programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the external crystal operating improperly at high frequency. The value of C1 and C2 may need some adjustment while running at lower gain. ALE OFF Function Auxiliary Register Bit: 7 - 6 - 5 - 4 - Mnemonic: AUXR 3 - 2 - Address: 8EH ALEOFF : Set this bit to disable ALE output. -8- 1 - 0 ALEOFF W78LE365/W78L365A 5.5 Reset The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78L365A is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset. 5.5.1 W78L365A Special Function Registers (SFRs) and Reset Values F8 F0 +B CHPENR 00000000 00000000 E8 +ACC E0 00000000 D8 +P4 PWMP PWM0 PWM1 PWMCON1 PWM2 PWM3 11111111 00000000 00000000 00000000 00000000 00000000 00000000 +PSW D0 00000000 C8 C0 +T2CON T2MOD RCAP2L RCAP2H TL2 TH2 PWMCON2 PWM4 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +XICON P4CONA P4CONB SFRAL SFRAH SFRFD SFRCN 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +IP B8 CHPCON 00000000 B0 A8 0xx00000 +P3 P43AL P43AH 00000000 00000000 00000000 +IE P42AL P42AH P4CSIN 00000000 00000000 00000000 00000000 A0 98 90 88 80 +P2 XRAMAH 11111111 00000000 +SCON SBUF 00000000 xxxxxxxx +P1 P41AL P41AH 11111111 00000000 00000000 +TCON TMOD TL0 TL1 TH0 TH1 AUXR WDTC 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +P0 SP DPL DPH P40AL P40AH POR PCON 11111111 00000111 00000000 00000000 00000000 00000000 00000000 00110000 Notes: 1. The SFRs marked with a plus sign(+) are both byte- and bit-addressable. 2. The text of SFR with bold type characters are extension function registers. -9- Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A 5.6 Port 4 Port 4, address D8H, is a 8-bit multipurpose programmable I/O port. Each bit can be configured individually by software. The Port 4 has four different operation modes. Mode 0: P4.0-P4.3 is a bi-directional I/O port which is same as port 1. P4.2 and P4.3 also serve as external interrupt PSEN and INT2 if enabled. Mode 1: P4.0-P4.3 are read strobe signals that are synchronized with RD signal at specified addresses. These signals can be used as chip-select signals for external peripherals. Mode 2: P4.0-P4.3 are write strobe signals that are synchronized with WR signal at specified addresses. These signals can be used as chip-select signals for external peripherals. Mode 3: P4.0-P4.3 are read/write strobe signals that are synchronized with RD or WR signal at specified addresses. These signals can be used as chip-select signals for external peripherals. When Port 4 is configured with the feature of chip-select signals, the chip-select signal address range depends on the contents of the SFR P4xAH, P4xAL, P4CONA and P4CONB. The registers P4xAH and P4xAL contain the 16-bit base address of P4.x. The registers P4CONA and P4CONB contain the control bits to configure the Port 4 operation mode. The high nibble of port4(P4.4 to P4.7) can be selected to serve to the direct LED display drive outputs by setting the HDx bit is set, the corresponding pin p4.x can sink about 20 mA current for driving LED display directly. 5.6.1 Port Options Register Bit: 7 6 5 4 3 2 1 0 - - - HD47 HD46 HD45 HD44 P0UP Mnemonic: POR Address: 86H HD47-44: Enable pins P4.4 to P4.7 individually with high drive outputs. P0UP: Enable Port 0 weak up. The pins of Port 0 can be configured with either the open drain or standart port with internal pull-up. By the default, Port 0 is an open drain bi-directional I/O port. When the P0UP bit in the POR register is set, the pins of port 0 will perform a bi-directional I/O port with internal pull-up that is structurally the same Port2. 5.6.2 INT2 / INT3 Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To set/clear bits in the XICON register, one can use the "SETB ( CLR ) bit" instruction. For example, "SETB 0C2H" sets the EX2 bit of XICON. - 10 - W78LE365/W78L365A XICON - external interrupt control (C0H) PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2 PX3: External interrupt 3 priority high if set EX3: External interrupt 3 enable if set IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software PX2: External interrupt 2 priority high if set EX2: External interrupt 2 enable if set IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software Eight-source interrupt information: VECTOR ADDRESS POLLING SEQUENCE WITHIN PRIORITY LEVEL ENABLE REQUIRED SETTINGS INTERRUPT TYPE EDGE/LEVEL External Interrupt 0 03H 0 (highest) IE.0 TCON.0 Timer/Counter 0 0BH 1 IE.1 - External Interrupt 1 13H 2 IE.2 TCON.2 Timer/Counter 1 1BH 3 IE.3 - Serial Port 23H 4 IE.4 - Timer/Counter 2 2BH 5 IE.5 - External Interrupt 2 33H 6 XICON.2 XICON.0 External Interrupt 3 3BH 7 (lowest) XICON.6 XICON.3 INTERRUPT SOURCE P4CONB (C3H) BIT NAME FUNCTION 00: Mode 0. P4.3 is a general purpose I/O port which is the same as Port1. 01: Mode 1. P4.3 is a Read Strobe signal for chip select purpose. The address range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0. 7, 6 P43FUN1 10: Mode 2. P4.3 is a Write Strobe signal for chip select purpose. The address range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0. P43FUN0 11: Mode 3. P4.3 is a Read/Write Strobe signal for chip select purpose. The address range depends on the SFR P43AH, P43AL, P43CMP1, and P43CMP0. - 11 - Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A P4CONB (C3H), continued BIT NAME FUNCTION Chip-select signals address comparison: 00: Compare the full address (16 bits length) with the base address register P43AH, P43AL. 5, 4 P43CMP1 01: Compare the 15 high bits (A15-A1) of address bus with the base address register P43AH, P43AL. P43CMP0 10: Compare the 14 high bits (A15-A2) of address bus with the base address register P43AH, P43AL. 11: Compare the 8 high bits (A15-A8) of address bus with the base address register P43AH, P43AL. 3, 2 P42FUN1 The P4.2 function control bits which are the similar definition as P43FUN1, P42FUN0 P43FUN0. 1, 0 P42CMP1 The P4.2 address comparator length control bits which are the similar definition P42CMP0 as P43CMP1, P43CMP0. P4CONA (C2H) BIT NAME FUNCTION 7, 6 P41FUN1 The P4.1 function control bits which are the similar definition as P43FUN1, P41FUN0 P43FUN0. 5, 4 P41CMP1 The P4.1 address comparator length control bits which are the similar definition P41CMP0 as P43CMP1, P43CMP0. 3, 2 P40FUN1 The P4.0 function control bits which are the similar definition as P43FUN1, P40FUN0 P43FUN0. 1, 0 P40CMP1 The P4.0 address comparator length control bits which are the similar definition P40CMP0 as P43CMP1, P43CMP0. P4CSIN (AEH) BIT NAME FUNCTION 7 P43CSINV The active polarity of P4.3 when pin P4.3 is defined as read and/or write strobe signal. = 1: P4.3 is active high when pin P4.3 is defined as read and/or write strobe signal. = 0: P4.3 is active low when pin P4.3 is defined as read and/or write strobe signal. 6 P42CSINV The similarity definition as P43SINV. 5 P41CSINV The similarity definition as P43SINV. 4 P40CSINV The similarity definition as P43SINV. 3 - Reserve 2 - Reserve 1 - 0 0 - 0 - 12 - W78LE365/W78L365A 5.6.3 Port 4 Base Address Registers P40AH, P40AL: The Base address register for comparator of P4.0. P40AH contains the high-order byte of address, P40AL contains the low-order byte of address. P41AH, P41AL: The Base address register for comparator of P4.1. P41AH contains the high-order byte of address, P41AL contains the low-order byte of address. P42AH, P42AL: The Base address register for comparator of P4.2. P42AH contains the high-order byte of address, P42AL contains the low-order byte of address. P43AH, P43AL: The Base address register for comparator of P4.3. P43AH contains the high-order byte of address, P43AL contains the low-order byte of address. P4 (D8H) BIT NAME FUNCTION 7 P47 I/O pin 6 P46 I/O pin. 5 P45 I/O pin. 4 P44 I/O pin. 3 P43 Port 4 Data bit which outputs to pin P4.3 at mode 0. 2 P42 Port 4 Data bit. which outputs to pin P4.2 at mode 0. 1 P41 Port 4 Data bit. which outputs to pin P4.1at mode 0. 0 P40 Port 4 Data bit which outputs to pin P4.0 at mode 0. Here is an example to program the P4.0 as a write strobe signal at the I/O port address 1234H-1237H and positive polarity, and P4.1-P4.3 are used as general I/O ports. P4.4-P4.7 is only available for 48 pin package. MOV P40AH, #12H MOV P40AL, #34H MOV P4CONA, #00001010B MOV P4CONB, #00H MOV P2ECON, #10H ; Base I/O address 1234H for P4.0 ; P4.0 a write strobe signal and address line A0 and A1 are masked. ; P4.1-P4.3 as general I/O port which are the same as PORT1 ; Write the P40SINV = 1 to inverse the P4.0 write strobe polarity ; default is negative. Then any instruction MOVX @DPTR, A (with DPTR = 1234H-1237H) will generate the positive polarity write strobe signal at pin P4.0. And the instruction MOV P4, #XX will output the bit3 to bit1 of data #XX to pin P4.3-P4.1. - 13 - Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A P4xCSINV P4 REGISTER P4.x DATA I/O RD_CS MUX 4->1 WR_CS READ WRITE RD/WR_CS PIN P4.x ADDRESS BUS P4xFUN0 P4xFUN1 EQUAL REGISTER P4xAL P4xAH Bit Length Selectable comparator P4.x INPUT DATA BUS REGISTER P4xCMP0 P4xCMP1 5.7 Pulse Width Modulated Outputs (PWM) There are five pulse width modulated output channels to generate pulses of programmable length and interval. The repetition frequency is defined by an 8-bit prescaler PWMP, which supplies the clock for the counter. The prescaler and counter are common to both PWM channels. The 8-bit counter counts modular 255 (0-254). The value of the 8-bit counter compared to the contents of five registers: PWM0, PWM1, PWM2, PWM3 and PWM4. Provided the contents of either these registers is greater than the counter value, the corresponding PWM0, PWM1, PWM2, PWM3 or PWM4 output is set HIGH. If the contents of these registers are equal to, or less than the counter value, the output will be LOW. The pulse-width-ratio is defined by the contents of the registers PWM0, PWM1, PWM2, PWM3 and PWM4. The pulse-width-ratio is in the range of 0 to 1 and may be programmed in increments of 1/255. ENPWM0, ENPWM1, ENPWM2, ENPWM3 and ENPWM4 bit will enable or disable PWM output. Buffered PWM outputs may be used to drive DC motors. The rotation speed of the motor would be proportional to the contents of PWM0/1/2/3/4. The repetition frequency fpwm , at the PWM0/1/2/3/4 output is given by: fpwm = fosc 2 x (1 + PWMP) x 255 Prescaler division factor = PWM + 1 PWMn high/low ratio of PWMn = (PWMn) 255 - (PWMn) - 14 - W78LE365/W78L365A This gives a repetition frequency range of 123 Hz to 31.4 KHz ( fosc = 16 MHz). By loading the PWM registers with either 00H or FFH, the PWM channels will output a constant HIGH or LOW level, respectively. Since the 8-bit counter counts modulo 255, it can never actually reach the value of the PWM registers when they are loaded with FFH. When a compare register (PWM0, PWM1, PWM2, PWM3, PWM4) is loaded with a new value, the associated output updated immediately. It does not have to wait until the end of the current counter period. There is weakly pulled high on PWM output. comparator ENPWM0/1/2/3/4 PWM0OE PWM0 PWM0 (P1.3) f osc 1/2 Prescaler 8bit counter PWM1OE PWMP PWM1 (P1.4) PWM1 comparator comparator PWM2OE PWM2 PWM2 (P1.5) 8bit counter PWM3OE PWM3 (P1.6) PWM3 comparator 8bit counter PWM4OE PWM4 (P1.7) PWM4 comparator FIGURE 1 PWM DIAGRAM Please refer as below code. mov pwmcon1, #00110011b ; enable pwm3, 2, 1, 0 mov pwmcon2, #00000101b ; enable pwm4 mov pwmp, #40h ; Fpwm = XT/(2*(1+pwmp)*255) jb p1.3, $ mov pwm0, #14h jb p1.4, $ mov pwm1, #18h ; duty cycle high/low = pwm0/(255-pmw0) - 15 - Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A jb p1.5, $ mov pwm2, #20h jb p1.6, $ mov pwm3, #b0h jb p1.7, $ mov pwm4, #40h mov pwmcon1, #11111111b ;output enable pwm3, 2, 1, 0 PWM3 Register Bit: 7 6 5 4 Mnemonic: PWM3 3 2 1 0 1 0 Address: DEH PWM2 Register Bit: 7 6 5 4 Mnemonic: PWM2 3 2 Address: DDH PWM Control 1 Register Bit: 7 6 5 4 3 2 1 0 PWM3OE PWM2OE ENPWM3 ENPWM2 PWM1OE PWM0OE ENPWM1 ENWPM0 1 0 Mnemonic: PWMCON1 Address: DCH PWM3OE: Output enable for PWM3 PWM2OE: Output enable for PWM2 ENPWM3: Enable PWM3 ENPWM2: Enable PWM2 PWM1OE: Output enable for PWM1 PWM0OE: Output enable for PWM0 ENPWM1: Enable PWM1 ENPWM0: Enable PWM0 PWM1 Register Bit: 7 6 5 4 Mnemonic: PWM1 - 16 - 3 2 Address: DBH W78LE365/W78L365A PWM0 Register Bit: 7 6 5 4 Mnemonic: PWM0 3 2 1 0 1 0 1 0 Address: DAH PWMP Register Bit: 7 6 5 4 Mnemonic: PWMP 3 2 Address: D9H PWM4 Register Bit: 7 6 5 4 Mnemonic: PWM4 3 2 Address: CFH PWM Control 2 Register Bit: 7 - 6 - 5 - 4 - Mnemonic: PWMCON2 3 - 2 PWM4OE 1 - 0 ENWPM4 Address: CEH PWM4OE: Output enable for PWM4 ENPWM: Enable for PWM4 5.8 Watchdog Timer The Watchdog timer is a free-running timer which can be programmed by the user to serve as a system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the system clock. The divider output is selectable and determines the time-out interval. When the time-out occurs, a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a system monitor. This is important in real-time control applications. In case of power glitches or electromagnetic interference, the processor may begin to execute errant code. If this is left unchecked the entire system may crash. The watchdog time-out selection will result in different time-out values depending on the clock speed. The Watchdog timer will de disabled on reset. In general, software should restart the Watchdog timer to put it into a known state. The control bits that support the Watchdog timer are discussed below. Watchdog Timer Control Register Bit: 7 ENW 6 CLRW 5 WIDL 4 - Mnemonic: WDTC 3 - 2 PS2 1 PS1 0 PS0 Address: 8FH ENW : Enable watch-dog if set. CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled under IDLE mode. Default is cleared. - 17 - Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS2-0 as follows: PS2 PS1 PS0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 PRESCALER SELECT 0 1 0 1 0 1 0 1 2 4 8 16 32 64 128 256 The time-out period is obtained using the following equation: 1 x 214 x PRESCALER x 1000 x 12 mS OSC Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6 (CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next instruction cycle. The Watchdog timer is cleared on reset. ENW WIDL IDLE EXTERNAL RESET OSC 1/12 Watchdog Timer Block Diagram PRESCALER 14-BIT TIMER CLEAR CLRW Typical Watch-Dog time-out period when OSC = 20 MHz PS2 PS1 PS0 WATCHDOG TIME-OUT PERIOD 0 0 0 19.66 mS 0 0 1 39.32 mS 0 1 0 78.64 mS 0 1 1 157.28 mS 1 0 0 314.57 mS 1 0 1 629.14 mS 1 1 0 1.25 S 1 1 1 2.50 S - 18 - INTERNAL RESET W78LE365/W78L365A 5.9 In-System Programming (ISP) Mode The W78L365A equips one 64K byte of main ROM bank for application program (called APROM) and one 4K byte of auxiliary ROM bank for loader program (called LDROM). In the normal operation, the microcontroller executes the code in the APROM. If the content of APROM needs to be modified, the W78L365A allows user to activate the In-System Programming (ISP) mode by setting the CHPCON register. The CHPCON is read-only by default, software must write two specific values 87H, then 59H sequentially to the CHPENR register to enable the CHPCON write attribute. Writing CHPENR register with the values except 87H and 59H will close CHPCON register write attribute. The W78L365A achieves all in-system programming operations including enter/exit ISP Mode, program, erase, read ... etc, during device in the idle mode. Setting the bit CHPCON.0 the device will enter in-system programming mode after a wake-up from idle mode. Because device needs proper time to complete the ISP operations before awaken from idle mode, software may use timer interrupt to control the duration for device wake-up from idle mode. To perform ISP operation for revising contents of APROM, software located at APROM setting the CHPCON register then enter idle mode, after awaken from idle mode the device executes the corresponding interrupt service routine in LDROM. Because the device will clear the program counter while switching from APROM to LDROM, the first execution of RETI instruction in interrupt service routine will jump to 00H at LDROM area. The device offers a software reset for switching back to APROM while the content of APROM has been updated completely. Setting CHPCON register bit 0, 1 and 7 to logic-1 will result a software reset to reset the CPU. The software reset serves as a external reset. This in-system programming feature makes the job easy and efficient in which the application needs to update firmware frequently. In some applications, the in-system programming feature make it possible to easily update the system firmware without opening the chassis. SFRAH, SFRAL: The objective address of on-chip ROM in the in-system programming mode. SFRAH contains the high-order byte of address, SFRAL contains the low-order byte of address. SFRFD: The programming data for on-chip ROM in programming mode. SFRCN: The control byte of on-chip ROM programming mode. SFRCN (C7) BIT NAME 7 - FUNCTION Reserve. On-chip ROM bank select for in-system programming. 6 WFWIN = 0: 64K bytes ROM bank is selected as destination for re-programming. = 1: 4K bytes ROM bank is selected as destination for re-programming. 5 OEN ROM output enable. 4 CEN ROM chip enable. 3, 2, 1, 0 CTRL[3:0] The flash control signals - 19 - Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A MODE WFWIN CTRL<3:0> OEN CEN SFRAH, SFRAL SFRFD Erase 64KB APROM 0 0010 1 0 X X Program 64KB APROM 0 0001 1 0 Address in Data in Read 64KB APROM 0 0000 0 0 Address in Data out Erase 4KB LDROM 1 0010 1 0 X X Program 4KB LDROM 1 0001 1 0 Address in Data in Read 4KB LDROM 1 0000 0 0 Address in Data out 5.9.1 In-System Programming Control Register (CHPCON) CHPCON (BFH) BIT NAME FUNCTION 7 SWRESET When this bit is set to 1, and both FBOOTSL and FPROGEN are set to 1. It will enforce microcontroller reset to initial condition just like power on reset. 6 - 5 LD/AP 4 ENAUXRAM 3 1 Must be 1 2 - Reserve. 1 FBOOTSL When this bit is set to 1, and both SWRESET and FPROGEN are set to 1. It will enforce microcontroller reset to initial condition just like power on reset. 0 FPROGEN When this bit is set to 1, and both SWRESET and FBOOTSL are set to 1. It will enforce microcontroller reset to initial condition just like power on reset. Reserve. This bit is read only. 1: CPU is running LDROM program. 0: CPU is running APROM program. 1: Enable on-chip AUX-RAM. 0: Disable the on-chip AUX-RAM This register is protected by CHPENR register. Please write as below procedures while you would like to write CHPCON register. Mov CHPENR, #87h Mov CHPENR, #59h Anl CHPCON, #EFh ;Disable AUX-RAM Mov CHPENR, #0h - 20 - W78LE365/W78L365A 5.10 Software Reset Set CHPCON = 0X83, timer and enter IDLE mode. CPU will reset and restart from APFLASH after time out. 5.11 H/W Reboot Mode (Boot from LDROM) By default, the W78L365A boots from APROM program after a power on reset. On some occasions, user can force the W78L365A to boot from the LDROM program via following settings. The possible situation that you need to enter H/W REBOOT mode when the APROM program can not run properly and device can not jump back to LDROM to execute in-system programming function. Then you can use this H/W REBOOT mode to force the W78L365A jumps to LDROM and executes in-system programming procedure. When you design your system, you may reserve the pins P2.6, P2.7 to switches or jumpers. For example in a CD-ROM system, you can connect the P2.6 and P2.7 to PLAY and EJECT buttons on the panel. When the APROM program fails to execute the normal application program. User can press both two buttons at the same time and then turn on the power of the personal computer to force the W78L365A to enter the H/W REBOOT mode. After power on of personal computer, you can release both buttons and finish the in-system programming procedure to update the APROM code. In application system design, user must take care of the P2, P3, ALE, EA and PSEN pin value at reset to prevent from accidentally activating the programming mode or H/W REBOOT mode. It is necessary to add 10K resistor on these P2.6, P2.7 and P4.3 pins. H/W Reboot MODE P4.3 P2.7 P2.6 MODE X L L REBOOT L X X REBOOT The Reset Timing For Entering F04KBOOT Mode P2.7 Hi-Z P2.6 Hi-Z RST 30 mS 10 mS - 21 - Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A The Algorithm of In-System Programming Part 1:32KB APROM procedure of entering In-System Programming Mode START Enter In-System Programming Mode ? (conditions depend on user's application) No Yes Setting control registers MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#03H Execute the normal application program Setting Timer (about 1.5 us) and enable timer interrupt END Start Timer and enter idle Mode. (CPU will be wakened from idle mode by timer interrupt, then enter In-System Programming mode) CPU will be wakened by interrupt and re-boot from 4KB LDROM to execute the loader program. Go - 22 - W78LE365/W78L365A Part 2: 4KB LDROM Go Procedure of Updating the 32KB APROM Timer Interrupt Service Routine: Stop Timer & disable interrupt PGM Yes Yes Is F04KBOOT Mode? (CHPCON.7=1) End of Programming ? No No Reset the CHPCON Register: MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#03H Setting Timer and enable Timer interrupt for wake-up . (50us for program operation) Yes Is currently in the F04KBOOT Mode ? No Get the parameters of new code Setting Timer and enable Timer interrupt for wake-up . (15 ms for erasing operation) Setting erase operation mode: MOV SFRCN,#22H (Erase 32KB APROM) Start Timer and enter IDLE Mode. (Erasing...) (Address and data bytes) through I/O ports, UART or other interfaces. Software reset CPU and re-boot from the 32KB APROM. MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#83H Setting control registers for programming: Hardware Reset to re-boot from new 32 KB APROM. (S/W reset is invalid in F04KBOOT Mode) MOV SFRAH,#ADDRESS_H MOV SFRAL,#ADDRESS_L MOV SFRFD,#DATA MOV SFRCN,#21H End of erase operation. CPU will be wakened by Timer interrupt. END Executing new code from address 00H in the 32KB APROM. PGM - 23 - Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A 6. SECURITY During the on-chip ROM programming mode, the ROM can be programmed and verified repeatedly. Until the code inside the ROM is confirmed OK, the code can be protected. The protection of ROM and those operations on it are described below. The W78L365A has a Security Register that can be accessed in programming mode. Those bits of the Security Registers can not be changed once they have been programmed from high to low. They can only be reset through erase-all operation. The Security Register is located at the 0FFFFH of the LDROM space. B7 Reserved B2 B1 B0 4KB On-chip ROM Program Memory LDROM Security Bits 0000h 32KB On-chip ROM Program Memory 0FFFh B0: Lock bit, logic 0: active B1: MOVC inhibit, logic 0: the MOVC instruction in external memory cannot access the code in internal memory. logic 1: no restriction. B2: Encryption logic 0: the encryption logic enable logic 1: the encryption logic disable B07: Osillator Control logic 0: 1/2 gain logic 1: Full gain Default 1 for all security bits. Reserved bits must be kept in logic 1. Reserved Reserved Security Register APROM 7FFFh FFFFh Special Setting Register 6.1 Lock Bit This bit is used to protect the customer's program code in the W78L365A. It may be set after the programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the ROM data and Security Register can not be accessed again. 6.2 MOVC Inhibit This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC instruction in external program memory from reading the internal program code. When this bit is set to logic 0, a MOVC instruction in external program memory space will be able to access code only in the external memory, not in the internal memory. A MOVC instruction in internal program memory space will always be able to access the ROM data in both internal and external memory. If this bit is logic 1, there are no restrictions on the MOVC instruction. - 24 - W78LE365/W78L365A 6.3 Encryption This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will reset this bit. 6.4 Oscillator Control W78L365A/E516 allow user to diminish the gain of on-chip oscillator amplifier by using programmer to set the bit B7 of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may improperly affect the external crystal operation at high frequency above 20 MHz. The value of R and C1, C2 may need some adjustment while running at lower gain. - 25 - Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A 7. ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings PARAMETER SYMBOL MIN. MAX. UNIT VDD-VSS VIN -0.3 +6.0 V VSS -0.3 VDD +0.3 V Operating Temperature TA 0 70 C Storage Temperature TST -55 +150 C DC Power Supply Input Voltage Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 7.2 D.C. Characteristics (VSS = 0v, TA = 25C, unless otherwise specified.) SYMBOL PARAMETER MAX. UNIT 2.4 5.5 V 2.7 - 5.5 20 2.5 V mA mA With ISP No load VDD = 5.5V No load VDD = 2.4V - 6 mA VDD = 5.5V, Fosc = 20 MHz 1 10 mA - A VDD = 2.4V, Fosc = 12 MHz VDD = 5.5V, Fosc = 20 MHz - 10 A VDD = 2.4V, Fosc = 12 MHz -50 +10 A VDD = 5.5V or 2.4V, VIN = 0V or VDD -10 +150 A VDD = 5.5V, 0<VIN<VDD -10 50 A VDD = 2.4V, 0<VIN<VDD -10 +10 A VDD = 5.5V or 2.4 V 0V<VIN<VDD Logic 1 to 0 Transition Current -500 -200 A VDD = 5.5V, VIN = 1.4V P1, P2, P3, P4 -50 -30 A VDD = 2.4V, VIN = 0.92V Operating Voltage IDD Operating Current IIDLE Idle Current Power Down Current IIN1 Input Current P1, P2, P3, P4 IIN2 Input Current RST ILK ITL[*4] TEST CONDITIONS MIN. VDD IPWDN SPECIFICATION Input Leakage Current P0, EA - 26 - Without ISP W78LE365/W78L365A D.C. Characteristics, continued SYMBOL VIL1 V IL3 VIH1 VIH2 VIH3 VOL Isk1 Isr1 TEST CONDITIONS MIN. MAX. UNIT Input Low Voltage 0 0.8 V VDD = 4.5V P0, P1, P2, P3, P4, RST, EA 0 0.5 V VDD = 2.4V Input Low Voltage 0 0.8 V VDD = 4.5V 0 0.4 V VDD = 2.4V Input High Voltage 2.4 VDD +0.2 V VDD = 5.5V P0, P1, P2, P3, P4, EA 1.4 VDD +0.2 V VDD = 2.4V Input High Voltage 3.5 VDD +0.2 V VDD = 5.5V RST 1.7 VDD +0.2 V VDD = 2.4V 3.5 VDD +0.2 V VDD = 5.5V 1.6 VDD +0.2 V VDD = 2.4V Output Low Voltage - 0.45 V VDD = 4.5V P1, P2, P3, P4, P0, ALE, PSEN - 0.4 V VDD = 2.4V Sink current 4 8 mA VDD = 4.5V, VOL = 0.45V P1, P3, P4 2.5 4.5 mA VDD = 2.4V, VOL = 0.4V Sink current 10 14 mA VDD = 4.5V, VOL = 0.45V P0, P2, ALE, PSEN 5 9 mA VDD = 2.4V, VOL = 0.4V Output High Voltage 2.4 - V VDD = 4.5V P1, P2, P3, P4, P0, ALE, PSEN 1.4 - V VDD = 2.4V Source current -150 -200 A VDD = 4.5V, VOH = 2.4V P1, P2, P3, P4 -20 -60 A VDD = 2.4V, VOH = 1.4V Source current -10 -14 mA VDD = 4.5V, VOH = 2.4V P0, P2, ALE, PSEN -1.9 -3.8 mA VDD = 2.4V, VOH = 1.4V XTAL1 [*4] Input High Voltage XTAL1 [*4] Isk2 VOH SPECIFICATION PARAMETER Isr2 Notes: *1. RST pin is a Schmitt trigger input. *2. P0, ALE and PSEN are tested in the external access mode. *3. XTAL1 is a CMOS input. *4. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0. - 27 - Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A 7.3 A.C. Characteristics The AC specifications are a function of the particular process used to manufacture the part, the ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually experience less than a 20 nS variation. Clock Input Waveform XTAL1 T CH T CL F OP, PARAMETER TCP SYMBOL MIN. TYP. MAX. UNIT NOTES Operating Speed FOP 0 - 20 MHz 1 Clock Period TCP 41.7 - - nS 2 Clock High TCH 20 - - nS 3 Clock Low TCL 20 - - nS 3 Notes: 1. The clock may be stopped indefinitely in either state. 2. The TCP specification is used as a reference in other specifications. 3. There are no duty cycle requirements on the XTAL1 input. - 28 - W78LE365/W78L365A 8. 8.1 TIMING WAVEFORMS Program Fetch Cycle S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 XTAL1 TALW ALE TAPL PSEN TPSW TAAS PORT 2 TAAH TPDA TPDH, TPDZ PORT 0 Code PARAMETER A0-A7 Data A0-A7 Code A0-A7 Data A0-A7 SYMBOL MIN. TYP. MAX. UNIT NOTES Address Valid to ALE Low TAAS 1 TCP- - - nS 4 Address Hold from ALE Low TAAH 1 TCP- - - nS 1, 4 ALE Low to PSEN Low TAPL 1 TCP- - - nS 4 PSEN Low to Data Valid TPDA - - 2 TCP nS 2 Data Hold after PSEN High TPDH 0 - 1 TCP nS 3 Data Float after PSEN High TPDZ 0 - 1 TCP nS ALE Pulse Width TALW 2 TCP- 2 TCP - nS 4 PSEN Pulse Width TPSW 3 TCP- 3 TCP - nS 4 Notes: 1. P0.0-P0.7, P2.0-P2.7 remain stable throughout entire memory cycle. 2. Memory access time is 3 TCP. 3. Data have been latched internally prior to PSEN going high. 4. "" (due to buffer driving delay and wire loading) is 20 nS. - 29 - Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A 8.2 Data Read Cycle S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 XTAL1 ALE PSEN PORT 2 A8-A15 DATA A0-A7 PORT 0 T DAR T DDA T DDH, T DDZ RD T DRD PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES ALE Low to RD Low TDAR 3 TCP- - 3 TCP+ nS 1, 2 RD Low to Data Valid TDDA - - 4 TCP nS 1 Data Hold from RD High TDDH 0 - 2 TCP nS Data Float from RD High TDDZ 0 - 2 TCP nS RD Pulse Width TDRD 6 TCP- 6 TCP - nS Notes: 1. Data memory access time is 8 TCP. 2. "" (due to buffer driving delay and wire loading) is 20 nS. - 30 - 2 W78LE365/W78L365A 8.3 Data Write Cycle S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 XTAL1 ALE PSEN PORT 2 PORT 0 A8-A15 A0-A7 WR T DAW PARAMETER DATA OUT T DWD TDAD T DWR SYMBOL MIN. TYP. MAX. UNIT ALE Low to WR Low TDAW 3 TCP- - 3 TCP+ nS Data Valid to WR Low TDAD 1 TCP- - - nS Data Hold from WR High TDWD 1 TCP- - - nS WR Pulse Width TDWR 6 TCP- 6 TCP - nS Note: "" (due to buffer driving delay and wire loading) is 20 nS. - 31 - Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A 8.4 Port Access Cycle S5 S6 S1 XTAL1 ALE TPDS T PDA TPDH DATA OUT PORT INPUT SAMPLE PARAMETER SYMBOL MIN. TYP. MAX. UNIT Port Input Setup to ALE Low TPDS 1 TCP - - nS Port Input Hold from ALE Low TPDH 0 - - nS Port Output to ALE TPDA 1 TCP - - nS Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to ALE, since it provides a convenient reference. - 32 - W78LE365/W78L365A 9. TYPICAL APPLICATION CIRCUIT 9.1 External Program Memory and Crystal VDD 31 19 XTAL1 10 u R 18 XTAL2 CRYSTAL 8.2 K 9 C1 EA C2 RST 12 INT0 13 INT1 14 T0 15 T1 1 2 3 4 5 6 7 8 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 39 AD0 38 AD1 37 AD2 36 AD3 35 AD4 34 AD5 33 AD6 32 AD7 AD0 3 AD1 4 AD2 7 AD3 8 AD413 AD514 AD617 AD718 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 21 22 23 24 25 26 27 28 GND1 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 A0 5 A1 6 A2 9 A3 12 A4 15 A5 16 A6 19 A7 OC 11 G 74LS373 A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 A10 21 A11 23 A12 2 A13 26 A1427 A15 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND20 CE 22 OE RD 17 WR 16 29 PSEN 30 ALE TXD 11 RXD 10 27512 W78LE365/W78L365A Figure A CRYSTAL C1 C2 R 6 MHz 47P 47P - 16 MHz 30P 30P - 20 MHz 15P 10P - Above table shows the reference values for crystal applications. Notes: 1. C1, C2, R components refer to Figure A 2. Crystal layout must get close to XTAL1 and XTAL2 pins on user's application board. - 33 - Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A 9.2 Expanded External Data Memory and Oscillator VDD VDD 31 19 10 u 8.2 K OSCILLATOR EA XTAL1 18 XTAL2 9 RST 12 13 14 15 1 2 3 4 5 6 7 8 INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 39 AD0 P0.1 38 AD1 P0.2 37 AD2 P0.3 36 AD3 P0.4 35 AD4 P0.5 34 AD5 P0.6 33 AD6 P0.7 32 AD7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 A8 A9 A10 A11 A12 A13 A14 21 22 23 24 25 26 27 28 AD0 3 AD1 4 AD2 7 AD3 8 AD4 13 AD5 14 AD6 17 AD7 18 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 GND 1 OC 11 G RD WR 17 16 29 PSEN 30 ALE 11 TXD RXD 10 74LS373 A0 A1 A2 A3 A4 A5 A6 A7 A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 A10 21 A11 23 A12 2 A13 26 A14 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 GND 20 22 27 CE OE WR 20256 W78LE365/W78L365A Figure B - 34 - D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 W78LE365/W78L365A 10. PACKAGE DIMENSIONS 10.1 40-pin DIP Symbol A A1 A2 B B1 c D E E1 e1 L D 40 21 E1 a eA S 20 1 Dimension in inch Dimension in m Min. Nom. Max. Min. Nom. Max. 5.334 0.210 0.010 0.254 0.150 0.155 0.160 3.81 3.937 4.064 0.016 0.018 0.022 0.406 0.457 0.559 0.048 0.050 0.054 1.219 1.27 1.372 0.008 0.010 0.014 0.203 0.254 0.356 2.055 2.070 52.20 52.58 0.590 0.600 0.610 14.986 15.24 15.494 0.540 0.545 0.550 13.72 13.84 13.97 0.090 0.100 0.110 2.286 2.54 2.794 0.120 0.130 0.140 3.048 3.302 3.556 0 15 0 15 0.630 0.650 0.670 16.00 16.51 17.01 0.090 2.286 Notes: E S c A A2 A1 Base Plane Seating Plane L B e1 10.2 eA a B1 1. Dimension D Max. & S include mold flash tie bar burrs. 2. Dimension E1 does not include interlead flas 3. Dimension D & E1 include mold mismatch a . mold parting line are determined at the 4. Dimension B1 does not include damba protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based final visual inspection spec. 44-pin PLCC HD D 6 1 44 40 Symbol 7 39 E 17 HE GE 29 18 28 c A A1 A2 b1 b c D E e GD GE HD HE L y Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max. 0.185 4.699 0.508 0.020 0.145 0.150 0.155 3.683 3.81 3.937 0.026 0.028 0.032 0.66 0.711 0.813 0.016 0.018 0.022 0.406 0.457 0.559 0.008 0.010 0.014 0.203 0.254 0.356 0.648 0.653 0.658 16.46 16.59 16.71 0.648 0.653 0.658 16.46 16.59 16.71 0.050 BSC 1.27 BSC 0.590 0.610 0.630 14.99 15.49 16.00 0.590 0.610 0.630 14.99 15.49 16.00 0.680 0.690 0.700 17.27 17.53 17.78 0.680 0.690 0.700 17.27 17.53 17.78 0.090 0.100 0.110 2.296 2.54 2.794 0.004 0.10 L Notes: A2 A 1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec. e b b1 Seating Plane A1 y GD - 35 - Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A 10.3 44-pin PQFP HD D Symbol 34 44 A A1 A2 b c D E e HD HE L L1 y 33 1 E HE 11 e 12 b 22 Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max. --- --- --- --- 0.002 0.01 0.02 0.05 0.25 0.5 0.075 0.081 0.087 1.90 2.05 2.20 0.01 0.014 0.018 0.25 0.35 0.45 0.004 0.006 0.010 0.101 0.152 0.254 0.390 0.394 0.398 9.9 10.00 10.1 0.390 0.394 0.398 9.9 10.00 10.1 --- --- 0.025 0.031 0.036 0.635 0.80 0.952 0.510 0.520 0.530 12.95 13.2 13.45 0.510 0.520 0.530 12.95 13.2 13.45 0.025 0.031 0.037 0.65 0.8 0.95 0.051 0.063 0.075 1.295 1.6 1.905 0.08 0.003 7 0 7 0 Notes: 1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeter 4. General appearance spec. should be based on final visual inspection spec. c A2 A Seating Plane A1 See Detail F L y L1 10.4 Detail F 48-pin LQFP HD D 25 36 Symbol A A1 A2 b c D E e HD HE L L1 y 0 24 37 E 48 HE 13 1 e b 12 Dimension in mm Min. Nom. Max. --- --- 1.60 0.05 --- 0.15 1.35 1.40 1.45 0.17 0.20 0.27 0.09 --- 0.20 7.00 7.00 0.50 9.00 9.00 0.45 0.60 0.75 1.00 --- 0.08 --- 0 3.5 7 Notes: c A2 Seating Plane See Detail F A1 y A L L1 - 36 - Detail F 1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec. W78LE365/W78L365A 11. APPLICATION NOTE 11.1 In-system Programming Software Examples This application note illustrates the in-system programmability of the Winbond W78E365 ROM microcontroller. In this example, microcontroller will boot from 64KB APROM bank and waiting for a key to enter in-system programming mode for re-programming the contents of 64KB APROM. While entering in-system programming mode, microcontroller executes the loader program in 4KB LDROM bank. The loader program erases the 64KB APROM then reads the new code data from external SRAM buffer (or through other interfaces) to update the 64KB APROM. Example 1: ;******************************************************************************************************************* ;* Example of 64K APROM program: Program will scan the P1.0. if P1.0 = 0, enters in-system ;* programming mode for updating the content of APROM code else executes the current ROM code. ;* XTAL = 16 MHz ;******************************************************************************************************************* .chip 8052 .RAMCHK OFF .symbols CHPCON CHPENR SFRAL SFRAH SFRFD SFRCN EQU EQU EQU EQU EQU EQU BFH F6H C4H C5H C6H C7H ORG 0H LJMP 100H ; JUMP TO MAIN PROGRAM ;************************************************************************ ;* TIMER0 SERVICE VECTOR ORG = 000BH ;************************************************************************ ORG 00BH CLR TR0 ; TR0 = 0, STOP TIMER0 MOV TL0, R6 MOV TH0, R7 RETI ;************************************************************************ ;* 64K APROM MAIN PROGRAM ;************************************************************************ ORG 100H MAIN_64K: MOV A, P1 ; SCAN P1.0 ANL A, #01H CJNE A, #01H, PROGRAM_64K ; IF P1.0 = 0, ENTER IN-SYSTEM PROGRAMMING MODE JMP NORMAL_MODE PROGRAM_64K: MOV CHPENR, #87H MOV CHPENR, #59H MOV CHPCON, #03H MOV TCON, #00H ; CHPENR = 87H, CHPCON REGISTER WRTE ENABLE ; CHPENR = 59H, CHPCON REGISTER WRITE ENABLE ; CHPCON = 03H, ENTER IN-SYSTEM PROGRAMMING MODE ; TR = 0 TIMER0 STOP - 37 - Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A MOV IP, #00H MOV IE, #82H MOV R6, #F0H MOV R7, #FFH MOV TL0, R6 MOV TH0, R7 MOV TMOD, #01H MOV TCON, #10H MOV PCON, #01H ; IP = 00H ; TIMER0 INTERRUPT ENABLE FOR WAKE-UP FROM IDLE MODE ; TL0 = F0H ; TH0 = FFH ; TMOD = 01H, SET TIMER0 A 16-BIT TIMER ; TCON = 10H, TR0 = 1, GO ; ENTER IDLE MODE FOR LAUNCHING THE IN-SYSTEM ; PROGRAMMING ;******************************************************************************** ;* Normal mode 64KB APROM program: depending user's application ;******************************************************************************** NORMAL_MODE: . ; User's application program . . . Example 2: ;****************************************************************************************************************************** Example of 4 KB LDROM program: This loader program will erase the 64KB APROM first, then reads the new ;* code from external SRAM and program them into 32 KB APROM bank. XTAL = 16 MHz ;***************************************************************************************************************************** .chip 8052 .RAMCHK OFF .symbols CHPCON CHPENR SFRAL SFRAH SFRFD SFRCN ORG LJMP EQU EQU EQU EQU EQU EQU 000H 100H BFH F6H C4H C5H C6H C7H ; JUMP TO MAIN PROGRAM ;************************************************************************ ;* 1. TIMER0 SERVICE VECTOR ORG = 0BH ;************************************************************************ ORG 000BH CLR TR0 ; TR0 = 0, STOP TIMER0 MOV TL0, R6 MOV TH0, R7 RETI ;************************************************************************ ;* 4KB LDROM MAIN PROGRAM ;************************************************************************ ORG 100H - 38 - W78LE365/W78L365A MAIN_4K: MOV SP, #C0H MOV CHPENR, #87H MOV CHPENR, #59H MOV CHPCON, #03H MOV CHPENR, #00H MOV TCON, #00H MOV TMOD, #01H MOV IP, #00H MOV IE, #82H MOV R6, #F0H MOV R7, #FFH MOV TL0, R6 MOV TH0, R7 MOV TCON, #10H MOV PCON, #01H UPDATE_64K: MOV TCON, #00H MOV IP, #00H MOV IE, #82H MOV TMOD, #01H MOV R6, #E0H ; CHPENR = 87H, CHPCON WRITE ENABLE. ; CHPENR = 59H, CHPCON WRITE ENABLE. ; CHPCON = 03H, ENABLE IN-SYSTEM PROGRAMMING. ; DISABLE CHPCON WRITE ATTRIBUTE ; TCON = 00H, TR = 0 TIMER0 STOP ; TMOD = 01H, SET TIMER0 A 16BIT TIMER ; IP = 00H ; IE = 82H, TIMER0 INTERRUPT ENABLED ; TCON = 10H, TR0 = 1, GO ; ENTER IDLE MODE ; TCON = 00H , TR = 0 TIM0 STOP ; IP = 00H ; IE = 82H, TIMER0 INTERRUPT ENABLED ; TMOD = 01H, MODE1 ; SET WAKE-UP TIME FOR ERASE OPERATION, ABOUT 15 mS. DEPENDING ; ON USER'S SYSTEM CLOCK RATE. MOV R7, #B1H MOV TL0, R6 MOV TH0, R7 ERASE_P_4K: MOV SFRCN, #22H MOV TCON, #10H MOV PCON, #01H ; SFRCN(C7H) = 22H ERASE 64K ; TCON = 10H, TR0 = 1, GO ; ENTER IDLE MODE (FOR ERASE OPERATION) ;********************************************************************* ;* BLANK CHECK ;********************************************************************* MOV SFRCN, #0H ; READ 64KB APROM MODE MOV SFRAH, #0H ; START ADDRESS = 0H MOV SFRAL, #0H MOV R6, #FEH ; SET TIMER FOR READ OPERATION, ABOUT 1.5 S. MOV R7, #FFH MOV TL0, R6 MOV TH0, R7 BLANK_CHECK_LOOP: SETB TR0 ; ENABLE TIMER 0 MOV PCON, #01H ; ENTER IDLE MODE MOV A, SFRFD ; READ ONE BYTE CJNE A, #FFH, BLANK_CHECK_ERROR INC SFRAL ; NEXT ADDRESS MOV A, SFRAL JNZ BLANK_CHECK_LOOP INC SFRAH MOV A, SFRAH - 39 - Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A CJNE A, #80H, BLANK_CHECK_LOOP ; END ADDRESS = 7FFFH JMP PROGRAM_64KROM BLANK_CHECK_ERROR: MOV P1, #F0H MOV P3, #F0H JMP $ ;******************************************************************************* ;* RE-PROGRAMMING 64KB APROM BANK ;******************************************************************************* PROGRAM_64KROM: MOV DPTR, #0H ; THE ADDRESS OF NEW ROM CODE MOV R2, #00H ; TARGET LOW BYTE ADDRESS MOV R1, #00H ; TARGET HIGH BYTE ADDRESS MOV DPTR, #0H ; EXTERNAL SRAM BUFFER ADDRESS MOV SFRAH, R1 ; SFRAH, TARGET HIGH ADDRESS MOV SFRCN, #21H ; SFRCN(C7H) = 21 (PROGRAM 64K) MOV R6, #BEH ; SET TIMER FOR PROGRAMMING, ABOUT 50 S. MOV R7, #FFH MOV TL0, R6 MOV TH0, R7 PROG_D_64K: MOV SFRAL, R2 MOVX A, @DPTR ; SFRAL(C4H) = LOW BYTE ADDRESS ; READ DATA FROM EXTERNAL SRAM BUFFER. BY ACCORDING USER? ; CIRCUIT, USER MUST MODIFY THIS INSTRUCTION TO FETCH CODE ; SFRFD(C6H) = DATA IN ; TCON = 10H, TR0 = 1, GO ; ENTER IDLE MODE (PRORGAMMING) MOV SFRFD, A MOV TCON, #10H MOV PCON, #01H INC DPTR INC R2 CJNE R2, #0H, PROG_D_64K INC R1 MOV SFRAH, R1 CJNE R1, #80H, PROG_D_64K ;***************************************************************************** ; * VERIFY 64KB APROM BANK ;***************************************************************************** MOV R4, #03H ; ERROR COUNTER MOV R6, #FEH ; SET TIMER FOR READ VERIFY, ABOUT 1.5 S. MOV R7, #FFH MOV TL0, R6 MOV TH0, R7 MOV DPTR, #0H ; The start address of sample code MOV R2, #0H ; Target low byte address MOV R1, #0H ; Target high byte address MOV SFRAH, R1 ; SFRAH, Target high address MOV SFRCN, #00H ; SFRCN = 00 (Read ROM CODE) READ_VERIFY_64K: MOV SFRAL, R2 MOV TCON, #10H MOV PCON, #01H INC R2 ; SFRAL(C4H) = LOW ADDRESS ; TCON = 10H, TR0 = 1,GO - 40 - W78LE365/W78L365A MOVX A, @DPTR INC DPTR CJNE A, SFRFD, ERROR_64K CJNE R2, #0H, READ_VERIFY_64K INC R1 MOV SFRAH, R1 CJNE R1, #80H, READ_VERIFY_64K ;****************************************************************************** ;* PROGRAMMING COMPLETLY, SOFTWARE RESET CPU ;****************************************************************************** MOV CHPENR, #87H ; CHPENR = 87H MOV CHPENR, #59H ; CHPENR = 59H MOV CHPCON, #83H ; CHPCON = 83H, SOFTWARE RESET. ERROR_64K: DJNZ R4, UPDATE_64K . . . . ; IF ERROR OCCURS, REPEAT 3 TIMES. ; IN-SYSTEM PROGRAMMING FAIL, USER'S PROCESS TO DEAL WITH IT. - 41 - Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A 12. REVISION HISTORY VERSION DATE PAGE DESCRIPTION A1 May 14, 2003 - A2 August, 2004 31 Revise the title of 9.1 A3 April 19, 2005 41 Add Important Notice A4 July 1, 2005 3 Add lead free (RoHS) parts A5 October 2, 2006 A6 December 4, 2006 3 Remove all Leaded package parts A7 January 10, 2007 3 4 36 Add 48-pin LQFP part. Add 48-pin LQFP package Add 48-pin LQFP package dimension Initial Issued Remove block diagram Change operating frequency into 20MHz Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 42 -