This is information on a product in full production.
December 2015 DocID4997 Rev 17 1/35
M93C86-x M93C76-x M93C66-x
M93C56-x M93C46-x
16-Kbit, 8-Kbit, 4-Kbit, 2-Kbit and 1-Kbit
(8-bit or 16-bit wide) MICROWIRE™ serial access EEPROM
Datasheet - production data
PDIP8 (BN)
SO8 (MN)
TSSOP8 (DW)
169 mil width
UFDFPN8 (MC)
2 x 3 mm
Features
Industry standard MICROWIRE™ bus
Single supply voltage:
–2.5 V to 5.5 V for M93Cx6-W
–1.8 V to 5.5 V for M93Cx6-R
Dual organization: by word (x16) or byte (x 8)
Programming instr uc tion s th at work on : by te,
word or entire memory
Self-timed programming cycle with auto-erase:
5 ms
READY/BUSY signal during program m i ng
2 MHz clock rate
Sequential read operation
Enhanced ESD/latch-up behavior
More than 4 million write cycles
More than 200-year data retention
Packages
SO8, TSSOP8, UFDFPN8 packages:
ECOPACK2®)
PDIP8 package:
ECOPACK1®
Table 1. Device summary
Reference Part
number Memory
size Supply
voltage
M93C46-x M93C46-W 1 Kbit 2.5 V to 5.5 V
M93C46-R 1.8 V to 5.5 V
M93C56-x M93C56-W 2 Kbit 2.5 V to 5.5 V
M93C56-R 1.8 V to 5.5 V
M93C66-x M93C66-W 4 Kbit 2.5 V to 5.5 V
M93C66-R 1.8 V to 5.5 V
M93C76-x M93C76-W 8 Kbit 2.5 V to 5.5 V
M93C76-R 1.8 V to 5.5 V
M93C86-x M93C86-W 16 Kbit 2.5 V to 5.5 V
M93C86-R 1.8 V to 5.5 V
www.st.com
Contents M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
2/35 DocID4997 R e v 17
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2Connecting to the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.3 Power-up and device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1 Read Data from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2 Erase and Write data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.1 Write Enable and Write Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.2 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.3 Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2.4 Erase Byte or Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2.5 Erase All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6READY/BUSY status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8Clock pulse counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11.1 PDIP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11.2 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DocID4997 Rev 17 3/35
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Contents
3
11.3 UFDFN8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11.4 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
12 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
List of tables M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
4/35 DocID4997 R e v 17
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Memory size versus organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Instruction set for the M93C46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Instruction set for the M93C56 and M93C66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Instruction set for the M93C76 and M93C86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8. Operating conditions (M93Cx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Operating conditions (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Cycling performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Memo ry ce ll data ret en tio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 12. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 13. Input and output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 14. DC characteristics (M93Cx6-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 16. AC characteristics (M93Cx6-W, M93Cx6-R, device grade 6). . . . . . . . . . . . . . . . . . . . . . . 22
Table 15. DC characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 17. AC characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 18. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 19. SO8N – 8-lead plastic small outline, 150 mils body width,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 20. UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 21. TSSOP8 – 8-lead thin shrink small outline, 3 x 4.4 mm, 0.5 mm pitch,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 22. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 23. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DocID4997 Rev 17 5/35
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x List of figures
5
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Bus master and memory devices on the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. M93Cx6 ORG input connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. READ, WRITE, WEN, WDS sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. WRAL sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. ERASE, ERAL sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Write sequence with one clock glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. AC testing input output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. Synchronous timing (Start and op-code input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11. Synchronous timing (Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Synchronous timing (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14. SO8N – 8-lead plastic small outline, 150 mils body width, package outline. . . . . . . . . . . . 26
Figure 15. SO8N – 8-lead plastic small outline, 150 mils body width,
package reco m me n de d fo ot pr int . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16. UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch
dual flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 17. TSSOP8 – 8-lead thin shrink small outline, 3 x 4.4 mm, 0.5 mm pitch,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Description M93C86-x M93C76-x M93C66-x M93C56-x M93C46 -x
6/35 DocID4997 R e v 17
1 Description
The M93C46 (1 Kbit), M93C56 (2 Kbit), M93C66 (4 Kbit), M93C76 (8 Kbit) and M93C86
(16 Kbit) are Electrically Erasable PROgrammable Memory (EEPROM) devices accessed
through the MICROWIRE™ bus protocol. The memory array can be configured either in
bytes (x8b) or in words (x16b).
The M93Cx6-W devices operate within a voltage supply range from 2.5 V to 5.5 V and the
M93Cx6-R devices operate within a voltage supply range from 1.8 V to 5.5 V. All these
devices operate with a clock frequency of 2 MHz (or less), over an ambient temperature
range of - 40 °C / + 85 °C.
Table 2. Memory size versus organization
Device Number of bits Number of 8-bit bytes Number of 16-bit words
M93C86 16384 2048 1024
M93C76 8192 1024 512
M93C66 4096 512 256
M93C56 2048 256 128
M93C46 1024 128 64
Figure 1. Logic diagram
!)
$
6##
-#X
633
#
1
3
/2'
Table 3. Signal names
Signal name Function Direction
SChip Select Input
DSerial Data input Input
QSerial Data output Output
CSerial Clock Input
ORG Organization Select Input
VCC Supply voltage -
VSS Ground -
DocID4997 Rev 17 7/35
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Description
34
Figure 2. 8-pin package connections (top view)
633
1
/2'
$5#
36
##
$
!)"
-#X
1. See Section 11: Package information for package dimensions, and how to identify pin-1.
2. DU = Don't Use. The DU (do not use) pin does not contribute to the normal operation of the device. It is
reserved for use by STMicroelectronics during test sequences. The pin may be left unconnected or may be
connected to VCC or VSS.
Connecting to the serial bus M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
8/35 DocID4997 R e v 17
2 Connecting to the serial bus
Figure 3 shows an example of three memory de vices connected to an MCU, on a serial bus.
Only one device is selecte d at a time, so only one device drives the Serial Data output (Q)
line at a time, the othe r de vice s ar e hig h imp e da n ce.
The pull-down resistor R (represented in Figure 3) ensures that no device is selected if the
bus master leaves the S line in the high impedance state.
In applications where the bus master may be in a state where all inputs/outputs are high
impedance at the same time ( for examp le, if the bus m aster is reset during the transmission
of an instruction), the clock line (C) must be connected to an external pull-down resistor so
that, if all inputs/outpu ts becom e high impedance, the C line is pulled low (while the S line is
pulled low): this ensures that C does not become high at the same time as S goes low, and
so, that the tSLCH requirement is met. The typical value of R is 100 kΩ.
Figure 3. Bus master and memory devices on the serial bus
!)B
"USMASTER
-XXX
MEMORYDEVICE
3$/
3$)
3#+
#1$
3
-XXX
MEMORYDEVICE
#1$
3
-XXX
MEMORYDEVICE
#1$
3
#3 #3 #3
/2' /2' /2'
22 2
6
##
6
##
6
##
6
##
6
33
6
33
6
33
6
33
2
DocID4997 Rev 17 9/35
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Operating features
34
3 Operating features
3.1 Supply voltage (VCC)
3.1.1 Operating supply voltage (VCC)
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] ran ge must be applied. In order to secu re a stable
DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor
(usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.
This voltage must remain st able and valid unt il the end o f the tr ansmission of the instr uction
and, for a Write instruction, until the completion of the internal write cycle (tW).
3.1.2 Power-up conditions
When the power supply is turned o n, VCC rises from VSS to VCC. During this time, the Chip
Select (S) line is not allowed to float and should be driven to VSS, it is therefore
recommended to connect the S line to VSS via a suitable pull-down resistor.
3.1.3 Power-up and device reset
In order to prevent inadvertent Write operations during power-up, a power on reset (POR)
circuit is included. At power-up (continuous rise of VCC), the device does not respond to an y
instruction until VCC has reached the power on reset threshold voltage (this threshold is
lower than the minimum VCC operating voltage defined in Operating conditions, in
Section 10: DC and AC parameters).
When VCC passes the POR threshold, the device is reset and is in the following state:
Standby Power mode
deselected (assuming that there is a pull-down resistor on the S line)
3.1.4 Power-down
At power-down (continuous decrease in VCC), as soon as VCC drops from the normal
operating voltage to below the power on reset th reshold voltage, the device stops
responding to any instruction sent to it.
During power- down, the device m ust be deselected and in the S t andby Power mode (that is,
there should be no internal Write cycle in progress).
Memory organization M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
10/35 DocID4997 Rev 17
4 Memory organization
The M93Cx6 memory is organized eith er as bytes (x8) or as words (x16). If Organization
Select (ORG) is left unconnected (or connected to VCC) the x16 organization is selected;
when Organization Select (ORG) is connected to Ground (VSS) the x8 organization is
selected. When the M93Cx6 is in Standby mode, Organization Select (ORG) should be set
either to VSS or VCC to reach the device minimum power consumption (as any voltage
between VSS and VCC applied to ORG input may increase the device Standby current).
Figure 4. M93Cx6 ORG input connect ion
06Y9
9FF
25*
9VV
9FF
25*
9VV
9FF
25*
9VV
1RW
FRQQHFWHG
[RUJDQL]DWLRQ [RUJDQL]DWLRQ [RUJDQL]DWLRQ
DocID4997 Rev 17 11/35
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Instructions
34
5 Instructions
The instruction set of the M93Cx6 devices contains seven instructions, as summarized in
Table 4 to Table 6. Each instruction consists of the following parts, as shown in Figure 5:
READ, WRITE, WEN, WDS sequences:
Each instruction is preceded by a rising edge on Chip Select Input (S) with Serial Clock
(C) being held low.
A start bit, which is the first ‘1’ read on Serial Data Input (D) duri ng the rising edge of
Serial Clock (C).
Two op-code bits, read on Serial Data Input (D) during the rising edge of Serial Clock
(C). (Some instructions also use the first two bits of the address to define the op-code).
The address bits of the byte or word that is to be accessed. For the M93C46, the
address is made up of 6 bits for the x16 organization or 7 bits for the x8 organization
(see Table 4). For the M93C56 an d M 93 C6 6, the ad d re ss is ma de up of 8 bits for the
x16 organization or 9 bits for the x8 organization (see Table 5). For the M93C76 and
M93C86, the address is made up of 10 bits for the x16 organization or 11 bits for th e x8
organization (see Table 6).
The M93Cx 6 device s ar e fa br ica ted in CMO S technology and are therefore able to run as
slow as 0 Hz (static input signals) or as fast as the maximum ratings specifie d in “AC
characteristics” tables, in Section 10: DC and AC parameters.
Table 4. Instruction set for the M93C46
Instruction Description Start
bitOp-
code
x8 origination (ORG = 0) x16 origination (ORG = 1)
Address
(1) Data Required
clock
cycles
Address
(1) Data Required
clock
cycles
READ Read Data from
Memory 110 A6-A0 Q7-Q0 -A5-A0 Q15-Q0 -
WRITE Write Data to
Memory 101 A6-A0 D7-D0 18 A5-A0 D15-D0 25
WEN Write Enable 100 11X XXXX -10 11 XXXX - 9
WDS Write Disable 100 00X
XXXX -10 00 XXXX - 9
ERASE Erase Byte or
Word 111 A6-A0 -10 A5-A0 - 9
ERAL Erase All Memory 100 10X
XXXX -10 10 XXXX - 9
WRAL Write All Memory
with same Data 100 01X
XXXX D7-D0 18 01 XXXX D15-D0 25
1. X = Don't Care bit.
Instructions M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
12/35 DocID4997 Rev 17
Table 5. Instruction set for the M93C56 and M93C66
Instruction Description Start
bitOp-
code
x8 origination (ORG = 0) x16 origination (ORG = 1)
Address
(1) (2) Data Required
clock
cycles
Address
(1) (3) Data Required
clock
cycles
READ Read Data from Memory 110 A8-A0 Q7-
Q0 -A7-A0 Q15-
Q0 -
WRITE Write Data to Memory 101 A8-A0 D7-
D0 20 A7-A0 D15-D0 27
WEN Write Enable 100 1 1XXX
XXXX -12 11XX
XXXX -11
WDS Write Disable 100 0 0XXX
XXXX -12 00XX
XXXX -11
ERASE Erase Byte or Word 111 A8-A0 -12 A7-A0 -11
ERAL Erase All Memor y 100 1 0XXX
XXXX -12 10XX
XXXX -11
WRAL Write All Memory with
same Data 100 0 1XXX
XXXX D7-
D0 20 01XX
XXXX D15-D0 27
1. X = Don't Care bit.
2. Address bit A8 is not decoded by the M93C56.
3. Address bit A7 is not decoded by the M93C56.
Table 6. Instruction set for the M93C76 and M93C86
Instruction Description Start
bitOp-
code
x8 Origination (ORG = 0) x16 Origination (ORG = 1)
Address
(1)(2) Data Required
clock
cycles
Address
(1) (3) Data Required
clock
cycles
READ Read Data from
Memory 110 A10-A0 Q7-Q0 -A9-A0 Q15-Q0 -
WRITE Write Data to
Memory 101 A10-A0 D7-D0 22 A9-A0 D15-D0 29
WEN Write Enable 100 11X XXXX
XXXX -14 11 XXXX
XXXX -13
WDS Write Disable 100 00X XXXX
XXXX -14 00 XXXX
XXXX -13
ERASE Erase Byte or Word 111 A10-A0 -14 A9-A0 -13
ERAL Erase All Memory 100 10X XXXX
XXXX -14 10 XXXX
XXXX -13
WRAL Write All Memory
with same Data 100 01X XXXX
XXXX D7-D0 22 01 XXXX
XXXX D15-D0 29
1. X = Don't Care bit.
2. Address bit A10 is not decoded by the M93C76.
3. Address bit A9 is not decoded by the M93C76.
DocID4997 Rev 17 13/35
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Instructions
34
5.1 Read Data from Memory
The Read Data from Memory (READ) instruction output s data on Serial Data Output (Q).
When the instruction is received, the op-code and address are decoded, and the data from
the memory is transferred to an output shift register. A dummy 0 bit is output first, followed
by the 8-bit byte or 16-bit word, with the most significant bit first. Output data changes are
triggered by the rising edge of Serial Clock (C). The M93Cx6 automatically increments the
internal address register and clocks out the next byte (or word) as long as the Chip Select
Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words)
and a continuous stream of dat a can be read ( the address counter automatically rolls over to
00h when the highest address is reached).
5.2 Erase and Write data
5.2.1 Write Enable and Write Disable
The Write Enable (WEN) instruction enables the future execution of erase or write
instructions, and the Write Disable (WDS) instruction disables it. When power is first
applied, the M93Cx6 initializes itself so that erase and write instructions are disabled. After a
Write Enable (WEN) instruction has been executed, erasing and writing remains enabled
until a Write Disable (WDS) instruction is executed, or until VCC falls below the power-on
reset threshold voltage. To protect the memory contents from accidental corruption, it is
advisable to issue the Write Disable (WDS) instruction after every write cycle. The Read
Data from Memory (READ) instruction is not affected by the Write Enable (WEN) or Write
Disable (WDS) instructions.
5.2.2 Write
For the Write Data to Memory (WRITE) instruction, 8 or 16 data bits follow the op-code and
address bit s. These form the byte or word that is to be written. As with th e other bits, Serial
Data Input (D) is sampled on the rising edge of Serial Clock (C).
After th e last data bit has been sampled, the Ch ip Select Input ( S) must be t aken low be fore
the next rising edge of Serial Clock (C). If Ch ip Select Input (S) is brought low before or after
this specific time frame, the self-timed programming cycle will not be started, and the
addressed location will not be programmed. The completion of the cycle can be detected by
monitoring the READY/BUSY line, as described later in this document.
Once the Write cycle has been st arted, it is internally self-timed (the extern al clock signal on
Serial Clock (C) may be stopped or left running after the start of a Write cycle). The Write
cycle is automatically preceded by an Eras e cycle, so it is unnecessary to execute an
explicit erase instruction before a Write Data to Memory (WRITE) instruction.
Instructions M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
14/35 DocID4997 Rev 17
Figure 5. READ, WRITE, WEN, WDS sequences
1. For the meanings of An, Xn, Qn and Dn, see Table 4, Table 5 and Table 6.
!)D
!N !
1N 1
$!4!/54
$
3
1
2EAD
37RITE
!$$2
/0
#/$%
!N !
$!4!).
$
1
/0
#/$%
$N $
"539 2%!$9
37RITE
%NABLE
8N8$
/0
#/$%

37RITE
$ISABLE
8N8$
/0
#/$%
#(%#+
34!453
!$$2
DocID4997 Rev 17 15/35
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Instructions
34
5.2.3 Write All
As with the Erase All Memory (ERAL) instruction, the format of the Write All Memory with
same Data (WRAL) instruction requires that a dummy address be provided. As with the
Write Data to Memory (WRITE) instruction , the format of the Write All Memory with same
Data (WRAL) instruction requires that an 8-bit data byte, or 16-bit data word, be provided.
This value is written to all the addresses of the memory device. The completion of the cycle
can be detected by monitoring the READY/BUSY line, as described next.
Figure 6. WRAL sequence
1. For the meanings of Xn and Dn, please see Table 4, Table 5 and Table 6.
!)#
372)4%
!,,
$!4!).
$
1
!$$2
/0
#/$%
$N $
"539 2%!$9
#(%#+
34!453
8N 8
Instructions M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
16/35 DocID4997 Rev 17
5.2.4 Erase Byte or Word
The Erase Byte or Word (ERASE) instruction set s the bits of the addressed memory byte (or
word) to 1. Once the address has been correctly decoded, the falling edge of the Chip
Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be
detected by monitoring the READY/BUSY line, as described in Section 6: READY/BUSY
status.
Figure 7. ERASE, ERAL sequences
1. For the meanings of An and Xn, please see Table 4, Table 5 and Table 6.
5.2.5 Erase All
The Erase All Memo ry (ERAL) instruction erases the whole memory (all me mory bits are set
to 1). The format of the instruction requires that a dummy address be provided. The Erase
cycle is conducted in the same way as the Erase instruction (ERASE). The completion of
the cycle can be detected by monitoring the READY/BUSY line, as described in Section 6:
READY/BUSY status.
!)"
3%2!3%
$
1
!$$2
/0
#/$%
"539 2%!$9
#(%#+
34!453
3%2!3%
!,,
$
1
/0
#/$%
"539 2%!$9
#(%#+
34!453
!N !
8N 8
!$$2
DocID4997 Rev 17 17/35
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x READY/BUSY status
34
6 READY/BUSY status
While the Write or Erase cycle is under way, for a WRITE, ERASE, WRAL or ERAL
instruction, the Busy signal (Q=0) is retu rn ed whenever Chip Select inpu t (S) is driven high.
(Please note, th ou gh , that th er e is an initial de lay, of t SLSH, before this status information
becomes available). In this state, the M93Cx6 ignores any data on the bus. When the Write
cycle is completed, and Chip Select Input (S) is driven high, the Ready signal (Q=1)
indicates that the M93Cx6 is ready to receive the ne xt instr uct ion . Ser ial Da ta Output (Q)
remains set to 1 until the Chip Select Input (S) is brought low or until a new start bit is
decoded.
7 Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each byte conta ins FFh).
Clock pulse counter M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
18/35 DocID4997 Rev 17
8 Clock pulse counter
In a noisy environment, the number of pulses received on Serial Clock (C) may be greater
than the number delive red by the master (the microcontroller ). This can lead to a
misalignment of the instruction of one or mor e bits (as shown in Figure 8) and may lead to
the writing of erroneous data at an erroneous address.
To avoid this problem, the M93Cx6 has an on-chip counter tha t counts the clock pu lses from
the start bit until the falling edge of the Chip Select Input (S). If the number of clock pulses
received is not the number expected, the WRITE, ERASE, ERAL or WRAL instruction is
aborted, and the contents of the memory are not modified.
The number of clock cycles expected for each instruction, and for each member of the
M93Cx6 family, are summarized in Table 4: Instruction set for the M93C46 to Table 6:
Instruction set for the M93C76 and M93C 86. For example, a Write Dat a to Memory (WRITE)
instruction on the M93C56 (or M93C66) expects 20 clock cycles (for the x8 organization)
from the start bit to the falling edge of Chip Select Input (S). That is:
1 Start bit
+ 2 Op-code bits
+ 9 Address bits
+ 8 Data bits
Figure 8. Write sequence with one clock glitch
!)
3
!N
#
$
72)4%
34!24 $
!N
'LITCH
!N
!$$2%33!.$$!4!
!2%3()&4%$"9/.%")4
DocID4997 Rev 17 19/35
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Maximum ratings
34
9 Maximum ratings
Stressing the device outside the ratings listed in the Absolute maximum ratings table may
cause permanent d amage to the device. The se are stress ratin gs only, and operation of the
device at these, or any other conditions outside those indicated in the operating sections of
this specification, is not implied. Exposure to absolute maximum rating cond itions for
extended periods may affect device reliability.
Table 7. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
Ambient operating temperature –40 130 °C
TSTG Storage temperature –65 150 °C
TLEAD Lead temperature during soldering PDIP -260(1)
1. TLEAD max must not be applied for more than 10 s.
°C
other packages See note (2)
2. Compliant with JEDEC standard J-STD-020D (for small-body, Sn-Pb or Pb free assembly), the ST
ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances
(RoHS directive 2011/65/EU of July 2011).
VOUT Output range (Q = VOH or Hi-Z) –0.50 VCC+0.5 V
VIN Input range –0.50 VCC+1 V
VCC Supply voltage –0.50 6.5 V
VESD Electrostatic discharge voltage (human body model)(3)
3. Positive and negative pulses applied on pin pairs, according to the AEC-Q100-002 (compliant with
ANSI/ESDA/JEDEC JS-001-2012), C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).
-4000 V
DC and AC parameters M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
20/35 DocID4997 Rev 17
10 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the de vice .
Table 8. Operating condition s (M93Cx6-W)
Symbol Parameter Min. Max. Unit
VCC Supply voltage 2.5 5.5 V
TAAmbient operating temperature –40 85 °C
Table 9. Operating conditions (M93Cx6- R)
Symbol Parameter Min. Max. Unit
VCC Supply voltage 1.8 5.5 V
TAAmbient operating temperature –40 85 °C
Ta bl e 10 . Cyc li n g pe rfo rma nc e(1)
1. Cycling performance for products identified by process letter K.
Symbol Parameter Test conditions Min. Max. Unit
Ncycle Write cycle endurance
TA 25 °C,
VCC(min) < VCC < VCC(max) -4,000,000 W r ite cycle
TA = 85 °C,
VCC(min) < VCC < VCC(max) -1,200,000
Table 11. Memory cell data retention(1)
Parameter Test conditions Min. Unit
Data retention TA = 55 °C 200 Year
1. For products identified by process letter K. The data retention behavior is checked in production, while the
200-year limit is defined from characterization and qualification results.
Table 12. AC measurement conditions
Symbol Parameter Min. Max. Unit
CLLoad capacitance 100 pF
-Input rise and fall times -50 ns
-Input voltage levels 0.2 VCC to 0.8 VCC V
-Input timing reference voltages 0.3 VCC to 0.7 VCC V
-Output timing reference voltages 0.3 VCC to 0.7 VCC V
DocID4997 Rev 17 21/35
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x DC and AC parameters
34
Figure 9. AC testing input output waveforms
Table 13. Input and output capacitance
Symbol Parameter Test condition(1)
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 1 MHz.
Min Max Unit
COUT Output capacitance VOUT = 0V - 8 pF
CIN Input capacitance VIN = 0V - 6 pF
Table 14. DC characteristics (M93Cx6-W, device grade 6)
Symbol Parameter Test condition ( in addition to
the conditions defined in
Table 8 and Table 12)Min. Max. Unit
ILI Input leakage current 0V VIN VCC -±2.5 µA
ILO Output leakage current 0V VOUT VCC, Q in Hi-Z -±2.5 µA
ICC Operating supply current
VCC = 5 V, S = VIH, f = 2 MHz,
Q = open - 2 mA
VCC = 2.5 V, S = VIH, f = 2 MHz,
Q = open - 1 mA
ICC1 Standby supply current
VCC = 2.5 V, S = VSS, C = VSS,
ORG = VSS or VCC,
pin7 = VCC, VSS or Hi-Z - 2(1)
1. 5 µA for previous devices identified with the process letter G.
µA
VCC = 5.5 V, S = VSS, C = VSS,
ORG = VSS or VCC,
pin7 = VCC, VSS or Hi-Z - 3(2)
2. Tested only for current devices identified with the process letter K.
µA
VIL Input low voltage (D, C, S) - –0.45 0.2 VCC V
VIH Input high voltage (D, C, S) - 0.7 VCC VCC + 1 V
VOL Output low voltage (Q) VCC = 5 V, IOL = 2.1 mA -0.4 V
VCC = 2.5 V, IOL = 100 µA -0.2 V
VOH Output high voltage (Q) VCC = 5 V, I OH = – 400 µA 0.8 VCC - V
VCC = 2.5 V, IOH = – 100 µA VCC–0.2 - V
-36
9&&
9&&
9&&
9&&
)NPUTANDOUTPUT
TIMINGREFERENCELEVELS
)NPUTVOLTAGELEVELS
-#88
DC and AC parameters M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
22/35 DocID4997 Rev 17
Table 15. DC characteristics (M93Cx6-R)
Symbol Parameter Test co ndition Min. Max. Unit
ILI Input leakage current 0V VIN VCC -±2.5 µA
ILO Output leakage current 0V VOUT VCC, Q in Hi-Z -±2.5 µA
ICC Operating supply current
VCC = 5 V, S = VIH, f = 2 MHz,
Q = open - 2 mA
VCC = 1.8 V, S = VIH, f = 1 MHz,
Q = open - 1 mA
ICC1 Standby supply current VCC = 1.8 V, S = VSS, C = VSS,
ORG = VSS or VCC,
pin7 = VCC, VSS or Hi-Z - 1(1) µA
VIL Input low voltage (D, C, S) -–0.45 0.2 VCC V
VIH Input high voltage (D, C, S) -0.8 VCC VCC + 1 V
VOL Output low voltage (Q) VCC = 1.8 V, IOL = 100 µA -0.2 V
VOH Output high voltage (Q) VCC = 1.8 V, IOH = –100 µA VCC–0.2 - V
1. 2 µA for previous devices identified with process letter G.
Table 16. AC characteristics (M93Cx6-W, M93Cx6-R(1), device grade 6)
1. All M93Cx6-R devices operate with a clock frequency of 1MHz, as defined in Table 17. Only the new
M93Cx6-R devices (identified with the process letter K) can operate with the 2 MHz timing values defined
in this table.
Test conditions specifie d in Table 8 and Table 12
Symbol Alt. Parameter Min. Max. Unit
fCfSK Clock frequency D.C. 2MHz
tSLCH Chip Select low to Clock high 50 -ns
tSHCH tCSS Chip Select setup time 50 -ns
tSLSH(2)
2. Chip Select Input (S) must be brought low for a minimum of tSLSH between consecutive instruction cycles.
tCS Chip Select low to Chip Select high 200 -ns
tCHCL(3)
3. tCHCL + tCLCH 1 / fC.
tSKH Clock high time 200 -ns
tCLCH(3) tSKL Clock low time 200 -ns
tDVCH tDIS Data in setup time 50 -ns
tCHDX tDIH Data in ho l d ti me 50 -ns
tCLSH tSKS Clock setup time (relative to S) 50 -ns
tCLSL tCSH Chip Select hold time 0 - ns
tSHQV tSV Chip Select to READY/BUSY status -200 ns
tSLQZ tDF Chip Select low to output Hi-Z -100 ns
tCHQL tPD0 Delay to output low -200 ns
tCHQV tPD1 Delay to output valid -200 ns
tWtWP Erase or Write cycle time - 5 ms
DocID4997 Rev 17 23/35
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x DC and AC parameters
34
Table 17. AC characteristics (M93Cx6-R)(1)
1. The new M93Cx6-R devices identified with the process letter K can operate with a clock frequency of
2 MHz and an Erase (or Write) cycle of 5 ms, as shown in Table 16.
Test conditions specifie d in Table 9 and Table 12
Symbol Alt. Parameter Min. Max. Unit
fCfSK Clock frequency D.C. 1MHz
tSLCH Chip Select low to Clock high 250 -ns
tSHCH tCSS Chip Select setup time 50 -ns
tSLSH(2)
2. Chip Select Input (S) must be brought low for a minimum of tSLSH between consecutive instruction cycles.
tCS Chip Select low to Chip Select high 250 -ns
tCHCL(3)
3. tCHCL + tCLCH 1 / fC.
tSKH Clock high time 250 -ns
tCLCH(3) tSKL Clock low time 250 -ns
tDVCH tDIS Data in setup time 100 -ns
tCHDX tDIH Data in hold time 100 -ns
tCLSH tSKS Clock setup time (relative to S) 100 -ns
tCLSL tCSH Chip Select hold time 0 - ns
tSHQV tSV Chip Select to READY/BUSY status -400 ns
tSLQZ tDF Chip Select low to output Hi-Z -200 ns
tCHQL tPD0 Delay to output low -400 ns
tCHQV tPD1 Delay to output valid -400 ns
tWtWP Erase or Write cycle time -10 ms
DC and AC parameters M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
24/35 DocID4997 Rev 17
Figure 10. Synchronous timing (Start and op-code input)
Figure 11. Synchronous timing (Read)
Figure 12. Synchronous timing (Write)
$,&
&
'
4
$''5(66,1387
+L=
W'9&+
W&/6/
$
6
'$7$287387
W&+49W&+';
W&+4/
$Q
W6/6+
W6/4=
44 4