1
January 2001
HM-6617/883
2K x 8 CMOS PROM
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby and Operating Power
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100µA
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . .20mA at 1MHz
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . . 90/120ns
• Industry Standard Pinout
• Single 5.0V Supply
• CMOS/TTL Compatible Inputs
• High Output Drive . . . . . . . . . . . . . . . . 12 LSTTL Loads
• Synchronous Operation
• On-Chip Address Latches
• Separate Output Enable
• Operating Temperature Range . . . . . . -55oC to +125oC
Description
The HM-6617/883 is a 16,384-bit fuse link CMOS PROM in
a 2K word by 8-bit/word format with “Three-State” outputs.
This PROM is available in the standard 0.600 inch wide 24
pin SBDIP, the 0.300 inch wide slim SBDIP, and the JEDEC
standard 32 pad CLCC.
The HM-6617/883 utilizes a synchronous design technique.
This includes on-chip address latches and a separate output
enable control which makes this device ideal for applications
utilizing recent generation microprocessors. This design
technique, combined with the Intersil advanced self-aligned
silicon gate CMOS process technology offers ultra-low
standby current. Low ICCSB is ideal for battery applications
or other systems with low power requirements.
The Intersil NiCr fuse link technology is utilized on this and
other Intersil CMOS PROMs. This gives the user a PROM
with permanent, stable storage characteristics over the full
industrial and military temperature voltage ranges. NiCr fuse
technology combined with the low power characteristics of
CMOS provides an excellent alternative to standard bipolar
PROMs or NMOS EPROMs.
All bits are manufactured storing a logical “0” and can be
selectively programmed for a logical “1” at any bit location.
Ordering Information
PACKAGE TEMPERATURE RANGE 90ns 120ns PACKAGE NO.
SBDIP -55oC to +125oC HM1-6617B/883 HM1-6617/883 D24.6
SLIM SBDIP -55oC to +125oC HM6-6617B/883 HM6-6617/883 D24.3
CLCC -55oC to +125oC HM4-6617B/883 HM4-6617/883 J32.A
Pinouts
HM-6617/883 (SBDIP)
TOP VIEW HM-6617/883 (CLCC)
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
21
22
23
24
15
14
13
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
VCC
A9
P
G
A10
Q7
Q5
Q4
Q3
A8
E
Q6
5
6
7
8
11
10
9
13
12
27
28
29
26
25
24
23
22
21
3 2 1
4 32 31 30
16 17 18 19 20
14 15
A6
A5
A4
A3
A2
A1
A0
NC
Q0
Q1
Q2
GND
NC
Q3
Q4
Q5
VCC
NC
NC
A7
NC
NC
NC
A8
A9
NC
G
A10
E
Q7
Q6
P
PIN DESCRIPTION
PIN DESCRIPTION
NC No Connect
A0-A10 Address Inputs
E Chip Enable
Q Data Output
VCC Power (+5V)
G Output Enable
P (Note) Program Enable
NOTE: P should be hardwired to VCC
except during programming.
File Number 3016.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Copyright © Intersil Corporation 2001
2
Functional Diagram
LATCHED
ADDRESS
REGISTER
GATED
ROW
DECODER
16
128 x 128
MATRIX
128
7
7
A
A
E
A
G
G
A10
A9
A7
A8
A6
A5
A4
MSB
L
LATCHED ADDRESS
REGISTER
A0A1A2A3
GATED COLUMN
DECODER AND DATA
OUTPUT CONTROL
4
L
MSB LSB
LSB
16 16 16 16 16 16 16
A4
G
ADDRESS LATCHES AND GATED DECODERS:
GATE ON FALLING EDGE OF G
LATCH ON FALLING EDGE OF E
ALL LINES POSITIVE LOGIC: ACTIVE HIGH
A HIGH OUTPUT ACTIVE
THREE-STATE BUFFERS:
8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
HM-6617/883
3
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
Typical Derating Factor. . . . . . . . . . . . 5mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.8V
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . +2.4V to VCC +0.3V
Thermal Resistance θJA θJC
SBDIP Package. . . . . . . . . . . . . . . . . . 48oC/W 9oC/W
Slim SBDIP . . . . . . . . . . . . . . . . . . . . . 65oC/W 14oC/W
CLCC Package . . . . . . . . . . . . . . . . . . 58oC/W 19oC/W
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+175oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . .+300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5473 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
TABLE 1. HM-6617/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER SYMBOL (NO TES 1, 4)
CONDITIONS GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
High Level Output Voltage VOH1 VCC = 4.5V, IO = -2.0mA 1, 2, 3 -55oC≤ TA ≤ +125oC 2.4 - V
Low Level Output Voltage VOL VCC = 4.5V, IO = +4.8mA 1, 2, 3 -55oC≤ TA ≤ +125oC - 0.4 V
High Impedance Output
Leakage Current IIOZ VCC = 5.5V, G = 5.5V,
VI/O = GND or VCC 1, 2, 3 -55oC≤ TA ≤ +125oC -1.0 1.0 µA
Input Leakage Current II VCC = 5.5V, VI = GND or
VCC, P Not Tested 1, 2, 3 -55oC≤ TA ≤ +125oC -1.0 1.0 µA
Standby Supply Current ICCSB VI = VCC or GND,
VCC = 5.5V, IO = 0mA 1, 2, 3 -55oC≤ TA ≤ +125oC - 100 µA
Operating Supply Current ICCOP VCC = 5.5V, G = GND,
(Note 3), f = 1MHz, IO =
0mA, VI = VCC or GND
1, 2, 3 -55oC≤ TA ≤ +125oC - 20 mA
Functional Test FT VCC = 4.5V (Note 6) 7, 8A, 8B -55oC≤ TA ≤ +125oC- -
TABLE 2. HM-6617/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER SYMBOL (NOTES 1, 2, 4)
CONDITIONS GROUP A
SUBGROUPS TEMPERATURE
LIMITS
HM-6617B/883 LIMITS
HM-6617/883
UNITSMIN MAX MIN MAX
Address Access Time TAVQV VCC = 4.5V and 5.5V
(Note 5) 9, 10, 11 -55oC≤ TA ≤ +125oC - 105 - 140 ns
Output Enable Access
Time TGLQV VCC = 4.5V and 5.5V 9, 10, 11 -55oC≤ TA ≤ +125oC- 40 - 50 ns
Chip Enable Access
Time TELQV VCC = 4.5V and 5.5V 9, 10, 11 -55oC≤ TA ≤ +125oC - 90 - 120 ns
Address Setup Time TAVEL VCC = 4.5V and 5.5V 9, 10, 11 -55oC≤ TA ≤ +125oC15 - 20 - ns
Address Hold Time TELAX VCC = 4.5V and 5.5V 9, 10, 11 -55oC≤ TA ≤ +125oC20 - 25 - ns
Chip Enable Low Width TELEH VCC = 4.5V and 5.5V 9, 10, 11 -55oC≤ TA ≤ +125oC 95 - 120 - ns
Chip Enable High Width TEHEL VCC = 4.5V and 5.5V 9, 10, 11 -55oC≤ TA ≤ +125oC40 - 40 - ns
HM-6617/883
4
Read Cycle Time TELEL VCC = 4.5V and 5.5V 9, 10, 11 -55oC≤ TA ≤ +125oC 136 - 160 - ns
NOTES:
1. All voltages referenced to Device GND.
2. AC measurements assume transition time ≤5ns; input levels = 0.0V to 3.0V; timing reference levels = 1.5V; output load = 1TTL equiva-
lent load and CL ≅ 50pF.
3. Typical derating = 5mA/MHz increase in ICCOP.
4. All tests performed with P hardwired to VCC.
5. TAVQV = TELQV + TAVEL.
6. Tested as follows: f = 1MHz, VIH = 2.4V, VIL = 0.8V, IOH = -1mA, IOL = +1mA, VOH ≥ 1.5V, VOL ≤ 1.5V.
TABLE 3. HM-6617/883 AC AND DC ELECTRICAL PERFORMANCE SPECIFICATIONS
PARAMETER SYMBOL (NOTES 1, 2)
CONDITIONS NOTES TEMPERATURE
LIMITS
HM-6617B/883 LIMITS
HM-6617/883
UNITSMIN MAX MIN MAX
Input Capacitance CIN VCC = Open, f = 1MHz, All
Measurements Referenced to
Device GND
2, 3 +25oC-10-10pF
VCC = Open, f = 1MHz, All
Measurements Referenced to
Device GND
2, 4 +25oC-12-12pF
2, 5 +25oC-10-10pF
I/O Capacitance CI/O VCC = Open, f = 1MHz, All
Measurements Referenced to
Device GND
2, 3 +25oC-12-12pF
VCC = Open, f = 1MHz, All
Measurements Referenced to
Device GND
2, 4 +25oC-14-14pF
2, 5 +25oC-12-12pF
Chip Enable Time TELQX VCC = 4.5V and 5.5V 2 -55oC≤ TA ≤ +125oC5 - 5 - ns
Output Enable Time TGLQX VCC = 4.5V and 5.5V 2 -55oC≤ TA ≤ +125oC5 - 5 - ns
Chip Disable Time TEHQZ VCC = 4.5V and 5.5V 2 -55oC≤ TA ≤ +125oC- 45 - 50 ns
Output Disable Time TGHQZ VCC = 4.5V and 5.5V 2 -55oC≤ TA ≤ +125oC- 40 - 50 ns
Output High Voltage VOH2 VCC = 4.5V, IO = 100µA 2 -55oC≤ TA ≤ +125oC VCC-
1V - VCC-
1V -V
NOTES:
1. All tests performed with P hardwired to VCC.
2. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are char-
acterized upon initial design changes which would affect these characteristics.
3. Applies to 0.600 inch SBDIP device types only.
4. Applies to 0.300 inch SBDIP device types only.
5. Applies to Ceramic Leadless Chip Carrier (CLCC) device types only.
TABLE 2. HM-6617/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Guaranteed and 100% Tested
PARAMETER SYMBOL (NOTES 1, 2, 4)
CONDITIONS GROUP A
SUBGROUPS TEMPERATURE
LIMITS
HM-6617B/883 LIMITS
HM-6617/883
UNITSMIN MAX MIN MAX
HM-6617/883
5
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS METHOD SUBGROUPS
Initial Test 100%/5004 -
Interim Test 100%/5004 1, 7, 9
PDA 100%/5004 1
Final Test 100%/5004 2, 3, 8A, 8B, 10, 11
Group A Samples/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Groups C & D Samples/5005 1, 7, 9
Switching Waveforms
FIGURE 1. READ CYCLE
Test Circuit
FIGURE 2. TEST CIRCUIT
TAVQV
TELEL
TELEH
TAVEL
TEHEL
TELQX TGHQZ
TEHQZ
TGLQX
TELQV
TGLQV
TELAX
ADDRESSES
E
G
DATA
1.5V 1.5V
1.5V
1.5V
3.0V
0V
3.0V
0V
3.0V
0V
TS
1.5V
ADDRESSES
VALID
DATA
VALID
ADDRESS
VALID
1.5V
1.5V
OUTPUT
Q0-Q7
1.5V
DUT
EQUIVALENT CIRCUIT
1.5V IOL
IOH
CL
TEST HEAD
CAPACITANCE
±
(NOTE)
NOTE:
HM-6617/883
6
Burn-In Circuits
HM-6617/883 (.300 INCH) SBDIP HM-6617/883 (.600 INCH) SBDIP
HM-6617/883 CLCC
NOTES:
f0 = 100KHz ± 10%.
All resistors = 47kΩ Unless Otherwise Noted.
VCC = 5.5V ± 0.05V.
C = 0.01 µF min.
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
21
22
23
24
15
14
13
GND
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
Q7
Q6
Q5
Q4
Q3
VCC
A8
A9
P
G
A10
E
VCC/2 VCC/2
C
2.4K
2.4K
2.4K
2.4K
2.4K
2.4K
2.4K
GND
VCC
f7
f6
f3
f4
f5
f1
f2
f12
VCC
f10
f0
f11
2.4K
f8
f9
1
2
3
4
5
6
7
8
9
11
12
16
17
18
19
20
21
22
23
24
15
14
13
10
VCC
f13
C
f1
f12
GND
f11
f0
VCC/2
f7
f6
f3
f4
f5
f1
f2
f8
VCC
VCC/2
Q7
Q6
Q5
Q4
Q3
VCC
A6
A5
P
G
A10
E
GND
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
27
28
29
26
25
24
23
3 2 1
4 32 31 30
5
6
7
8
11
10
9
16 17 18 19 20
14 15
22
21
12
13
NC
NC
NC
NC NC NC NCNC
f10
C
VCC
VCC
f12
VCC/2
f1
f13
f0
f11
VCC/2 VCC/2
VCC/2
f7
f6
f3
f4
f5
f8
f9
HM-6617/883
7
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Die Characteristics
DIE DIMENSIONS:
140 x 232 x 19 ± 1mils
METALLIZATION:
Type: Si - Al
Thickness: 11kű15kÅ
GLASSIVATION:
Type: SiO2
Thickness: 7kű 9kÅ
WORST CASE CURRENT DENSITY:
1.7 x 105 A/cm2
Metallization Mask Layout
HM-6617/883
A4 A5 A6 A7 VCC A8 A9 P
G
A10
E
Q7
Q6Q5Q4Q3GNDQ2Q1Q0
A0
A1
A2
A3
HM-6617/883
