SPICE D e vice Model SI4884DY
Siliconix 1
4/17/01
Document: 71601
N-Channel Reduced Qg, Fast Switching MOSFET
Characteristics
• N-channel Vertical DMOS
• Macro-Model (Sub-circuit)
• Level 3 MOS
• Applicable for Bo th Linear and Switch Mode
• Applicable Over a -55 to 125°C Temperature Range
• Models Gate Charge, Transient, and Diode Reverse
Recovery Characteristics
Description
The attached SPICE Model describes typical electrical
characteristics of the n-channel vertical DMOS. The
sub-circuit model was extracted and optimized over a
25°C to 125°C temperature range under pulse
conditions for 0 to 10 volts gate drives. Saturated
output impedance model accuracy has been maximized
for gate biases near threshold. A novel gate-to-drain
feedback capacitor network is used to model gate
charge characteristics while avoiding convergence
problems of switched Cgd model. Model parameter
values are optimized to provide a best fit to measure
electrical data and are not intended as an exact physical
description of a device.
Model Sub-circuit
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to
th e appropriate data sheet of t he same nu mber for guarant eed sp ecification limits.
GCGS
D
2
4
3
M1 DBD
M2
1
R1
S
SPICE D e vice Model SI4884DY
Siliconix 2
4/17/01
Document: 71601
Model Evaluation
N-Channel Device (TJ=25°C Unless Otherwise Noted)
Parameter Symbol Test Conditions Typical Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID= 250µA 1.73 V
On-State Drain Current aID(on) VDS ≥ 5V, VGS = 10V508 A
Drain-Source On-State Resistance arDS(on) VGS = 10V, ID = 12A0.0087 Ω
VGS = 4.5V, ID = 10A0.0132
Forward Transconductance agfs VDS = 15V, ID = 12A 34 S
Diode Forward Voltage aVSD IS = 2.3A, VGS = 0V 0.74 V
Dynamic b
Total Gate Charge Qg15.3
Gate-Source Charge Qgs VDS = 15V, VGS = 5V,
ID = 12A5.8 nC
Gate-Drain Charge Qgd 4.8
Turn-On Delay Time td(on) 10
Rise Ti me trVDD = 15V, RL = 15Ω14
Turn-Off Delay Time td(off) ID ≅ 1A, VGEN =10V,
RG = 6Ω30 ns
Fall Time tf52
Source-Drain Reverse Recovery Time trr IF = 2.3A, di/dt = 100A/µs44
Notes:
a) Pulse test: pulse width ≤ 300 µs, duty cycle ≤ 2%
b) Guaranteed by design, not subject to production testing
SPICE D e vice Model SI4884DY
Siliconix 3
4/17/01
Document: 71601
Comparison of Model with Measured Data
(TJ=25°C Unless Otherwise Noted)
0
10
20
30
40
50
ID - Drain C u rrent (A)
0 2 4 6 8 10
VDS - Drain-to-Source Voltage (V)
Vgs= 10,7,6,5,4V
Vgs = 3V
0
10
20
30
40
50
ID - Drain C u rrent (A)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
VGS - Gate-to-Source (V)
25C
125C
-55C
0
2
4
6
8
Sqrt (IDsat) (A )
0.00
0.05
0.10
0.15
0.20
rDS(on) - On-Resistance (Ohm)
0 2 4 6 8 10
VGS - Gate-to-Source Voltage (V)
Sqrt( IDsat)
rDS(on)
0.000
0.005
0.010
0.015
0.020
0.025
0.030
rDS(on) - On-Resistance (Ohm)
0 10 20 30 40 50
ID - Drain Current (A)
Vgs = 4.5V
Vgs = 10V
0
500
1000
1500
2000
2500
Capacitance (pF)
0 5 10 15 20 25 30
VDS - Drain-to-Source Voltage ( V )
Ciss
Coss
Crss 0
3
6
9
12
15
Vds (V)
0
2
4
6
8
10
Vgs (V)
0 5 10 15 20 25 30
Qg (nC)
Vgs
Vds
