MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14489B
M u Iti-Character
lED Display/lamp Driver
CMOS p SVFFiX
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The MC144898 is a flexible light-emitting-diode driver which directly in-
terfaces to individual lamps, 7-segment displays, or various combinations of
both. LEOs wired with common cathodes are driven in a multiplexed-by-5
fashion. Communication with an MCUIMPU is established through a synchro-
nous serial port. The MC 144898 features data retention plus decode and scan
circuitry, thus relieving processor overhead. A single, current-setting resistor
is the only ancillary component required.
A single device can drive anyone of the following: a 5-digit display plus
decimals, a 4-112-digit display plus decimals and sign, or 25 lamps. A special
technique allows driving 5 112 digits; see Figure 16. A configuration register
allows the drive capability to be partitioned off to suit many additional applica-
tions. The on-chip decoder outputs 7-segment-format numerals O to 9, hexa-
decimal characters A to F, plus 151etters and symbols.
The MC144898 is compatible with the Motorola SPI and National MI-
CRO-WIRETM serial data ports. The chip's patented 8itGrabberTM registers
augment the serial interface by allowing random access without steering or
address bits. A 24-bit transfer updates the display register. Changing the con-
figuration register requires an 8-bit transfer.
.Operating Voltage Range of Drive Circuitry: 4.5 to 5.5 V
.Operating Junction Temperature Range: -40° to 130°C
.Current Sources Controlled by Single Resistor Provide Anode Drive
.Low-Resistance FET Switches Provide Direct Common Cathode Interface
.Low-Power Mode (Extinguishes the LEDs) and Brightness Controlled via
Serial Port
.Special Circuitry Minimizes EMI when Display is Driven and Eliminates EMI
in Low-Power Mode
.Power-On Reset (POR) Blanks the Display on Power-Up, Independent of
Supply Ramp Up Time
.May Be Used with Double-Heterojunction LEDs for Optimum Efficiency
.Chip Complexity: 4300 Elements (FETs, Resistors, Capacitors, etc.)
BitGrabber is a trademark of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
REVO
November 2000
MC14489B MOTOROLA
2
BLOCK DIAGRAM
1
BitGrabber
CONFIGURATION REGISTER
8 BITS
Rx
DATA OUT
8
220
12
BitGrabber
DISPLAY REGISTER
24 BITS
NIBBLE MUX AND
DECODER ROM
ANODE DRIVERS
(CURRENT SOURCES)BANK SWITCHES (FETs)
194567
ab
DATA IN
cdefgh
24–1/2–STAGE
SHIFT REGISTER
11
10
7
4
444
44
4
44444
18
POR
913151617
5
5
CLOCK
ENABLE
OSCILLATOR AND
CONTROL LOGIC
BANK 1BANK 2BANK 3BANK 4BANK 5
PIN 3 = VDD
PIN 14 = VSS
h DIM/BRIGHT
BLANK a TO g
D
C
MAXIMUM RATINGS* (Voltages Referenced to VSS)
ÁÁÁÁ
ÁÁÁÁ
Symbol
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Parameter
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Value
ÁÁÁ
ÁÁÁ
Unit
ÁÁÁÁ
ÁÁÁÁ
VDD
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
DC Supply Voltage
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
– 0.5 to + 6.0
ÁÁÁ
ÁÁÁ
V
ÁÁÁÁ
ÁÁÁÁ
Vin
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
DC Input Voltage
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
– 0.5 to VDD + 0.5
ÁÁÁ
ÁÁÁ
V
ÁÁÁÁ
ÁÁÁÁ
Vout
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
DC Output Voltage
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
– 0.5 to VDD + 0.5
ÁÁÁ
ÁÁÁ
V
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
Iin
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
DC Input Current — per Pin
(Includes Pin 8)
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
±15
ÁÁÁ
Á
Á
Á
ÁÁÁ
mA
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
Iout
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
DC Output Current —
Pins 1, 2, 4 – 7, 19, 20 Sourcing
Sinking
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
– 40
10
ÁÁÁ
Á
Á
Á
ÁÁÁ
mA
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Pins 9, 13, 15, 16, 17 Sinking
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
320
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Pin 18
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
±15
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
IDD, ISS
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
DC Supply Current, VDD and VSS Pins
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
±350
ÁÁÁ
ÁÁÁ
mA
ÁÁÁÁ
ÁÁÁÁ
TJ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Chip Junction Temperature
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
– 40 to + 130
ÁÁÁ
ÁÁÁ
°C
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
RθJA
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Device Thermal Resistance,
Junction–to–Ambient (see Thermal
Considerations section) Plastic DIP
SOG Package
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
90
100
ÁÁÁ
Á
Á
Á
Á
Á
Á
ÁÁÁ
°C/W
ÁÁÁÁ
ÁÁÁÁ
Tstg
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Storage Temperature
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
– 65 to + 150
ÁÁÁ
ÁÁÁ
°C
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
TL
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Lead Temperature, 1 mm from Case for
10 Seconds
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
260
ÁÁÁ
Á
Á
Á
ÁÁÁ
°C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.
This device contains protection circuitry to
guard against damage due to high static volt-
ages or electric fields. However, precautions
must be taken to avoid applications of any volt-
age higher than maximum rated voltages to this
high–impedance circuit. For proper operation,
Vin and V out should be constrained to the range
VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an ap-
propriate logic voltage level (e.g., either VSS or
VDD). Unused outputs must be left open.
MC14489BMOTOROLA 3
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS, TJ = – 40° to 130°C* unless otherwise indicated)
Symbol Parameter Test Condition VDD
VGuaranteed
Limit Unit
VDD Power Supply Voltage Range of LED Drive Circuitry — 4.5 to 5.5 V
VDD (stby) Minimum Standby Voltage Bits Retained in Display and
Configuration Registers, Data
Port Fully Functional
— 3.0 V
VIL Maximum Low–Level Input Voltage
(Data In, Clock, Enable)3.0
5.5 0.9
1.65 V
VIH Minimum High–Level Input Voltage
(Data In, Clock, Enable)3.0
5.5 2.1
3.85 V
VHys Minimum Hysteresis Voltage
(Data In, Clock, Enable)3.0
5.5 0.2
0.4 V
VOL Maximum Low–Level Output Voltage
(Data Out) Iout = 20 µA3.0
5.5 0.1
0.1 V
Iout = 1.3 mA 4.5 0.4
VOH Minimum High–Level Output Voltage
(Data Out) Iout = – 20 µA3.0
5.5 2.9
5.4 V
Iout = – 800 µA 4.5 4.1
Iin Maximum Input Leakage Current
(DataInClockEnable)Vin = VDD or VSS 5.5 ± 2.0 µA
(Data In, Clock, Enable) Vin = VDD or VSS,
TJ = 25°C only 5.5 ± 0.1
iOL Minimum Sinking Current
(a, b, c, d, e, f, g, h) Vout = 1.0 V 4.5 0.2 mA
iOH Peak Sourcing Current — See Figure 7 for currents up to
35 mA (a, b, c, d, e, f, g, h) Rx = 2.0 kΩ, Vout = 3.0 V,
Dimmer Bit = High 5.0 13 to 17.5 mA
Rx = 2.0 kΩ, Vout = 3.0 V,
Dimmer Bit = Low 5.0 6 to 9
IOZ Maximum Output Leakage Current
(Bank1Bank2Bank3Bank4Bank5) Vout = VDD (FET Leakage) 5.5 50 µA
(Bank 1, Bank 2, Bank 3, Bank 4, Bank 5) Vout = VDD (FET Leakage),
TJ = 25°C only 5.5 1
Vout = VSS (Protection Diode
Leakage) 5.5 1
Ron Maximum ON Resistance
(Bank 1, Bank 2, Bank 3, Bank 4, Bank 5) Iout = 0 to 200 mA 5.0 10 Ω
IDD, ISS Maximum Quiescent Supply Current Device in Low–Power Mode,
Vin = VSS or VDD, Rx in
Place, Outputs Open
5.5 100 µA
Same as Above, TJ = 25°C 5.5 20
Iss Maximum RMS Operating Supply Current
(The VSS leg does not contain the Rx current component.
See Pin Descriptions.)
Device NOT in Low–Power
Mode, Vin = VSS or VDD,
Outputs Open
5.5 1.5 mA
*See Thermal Considerations section.
MC14489B MOTOROLA
4
AC ELECTRICAL CHARACTERISTICS (TJ = – 40° to 130°C*, CL = 50 pF, Input tr = tf = 10 ns)
Symbol Parameter VDD
VGuaranteed
Limit Unit
fclk Serial Data Clock Frequency, Single Device or Cascaded Devices
NOTE: Refer to Clock tw below
(Figure 1)
3.0
4.5
5.5
dc to 3.0
dc to 4.0
dc to 4.0
MHz
tPLH,
tPHL Maximum Propagation Delay, Clock to Data Out
(Figures 1 and 5) 3.0
4.5
5.5
140
80
80
ns
tTLH,
tTHL Maximum Output Transistion Time, Data Out
(Figures 1 and 5) 3.0
4.5
5.5
70
50
50
ns
fRRefresh Rate — Bank 1 through Bank 5
(Figures 2 and 6) 3.0
4.5
5.5
NA
700 to 1900
700 to 1900
Hz
Cin Maximum Input Capacitance — Data In, Clock, Enable — 10 pF
*See Thermal Considerations section.
TIMING REQUIREMENTS (TJ = – 40° to 130°C*, Input tr = tf = 10 ns unless otherwise indicated)
Symbol Parameter VDD
VGuaranteed
Limit Unit
tsu, thMinimum Setup and Hold Times, Data In versus Clock
(Figure 3) 3.0
4.5
5.5
50
40
40
ns
tsu, th,
trec Minimum Setup, Hold, ** and Recovery Times, Enable versus Clock
(Figure 4) 3.0
4.5
5.5
150
100
100
ns
tw(L) Minimum Active–Low Pulse Width, Enable
(Figure 4) 3.0
4.5
5.5
4.5
3.4
3.4
µs
tw(H) Minimum Inactive–High Pulse Width, Enable
(Figure 4) 3.0
4.5
5.5
300
150
150
ns
twMinimum Pulse Width, Clock
(Figure 1) 3.0
4.5
5.5
167
125
125
ns
tr, tfMaximum Input Rise and Fall Times — Data In, Clock, Enable
(Figure 1) 3.0
4.5
5.5
1
1
1
ms
*See Thermal Considerations section.
**For a high–speed 8–Clock access, th for Enable is determined as follows:
VDD = 3 to 4.5 V, fclk > 1.78 MHz: th = 4350 – (7500/fclk)
VDD = 4.5 to 5.5 V, f
clk > 2.34 MHz: th = 3300 – (7500/fclk)
where th is in ns and fclk is in MHz.
NOTES:
1.This restriction does NOT apply for fclk rates less than those listed above. For “slow” fclk rates, use the th limits in the above table.
2.This restriction does NOT apply for an access involving more than 8 Clocks. For > 8 Clocks, use the th limits in the above table.
MC14489BMOTOROLA 5
Figure 1. Figure 2.
10%
VDD
1/fclk
DATA OUT
CLOCK
90%
50%
90%
50%
10%
tPLH tPHL
tTLH tTHL
tw
tw
tftr
BANK
OUTPUT 50%
1/fR
VSS
Figure 3. Figure 4.
D
ATA IN
CLOCK
50%
VALID
50%
tsu thVDD
VDD
CLOCK
ENABLE
50%
tsu th
FIRST
CLOCK LAST
CLOCK
trec
50%
VDD
VDD
tw(H)tw(L)
VSS
VSS
VSS
VSS
Figure 5. Figure 6.
TEST POINT
DEVICE
UNDER
TEST CL*
*Includes all probe and fixture capacitance.
TEST POINT
DEVICE
UNDER
TEST CL*
*Includes all probe and fixture capacitance.
VDD
56
Ω
MC14489B MOTOROLA
6
PIN DESCRIPTIONS
DIGITAL INTERFACE
Data In (Pin 12)
Serial Data Input. The bit stream begins with the MSB and
is shifted in on the low–to–high transition of Clock. When the
device is not cascaded, the bit pattern is either 1 byte (8 bits)
long to change the configuration register or 3 bytes (24 bits)
long to update the display register. For two chips cascaded,
the pattern is either 4 or 6 bytes, respectively. The display
does not change during shifting (until Enable makes a low–
to–high transition) which allows slow serial data rates, if de-
sired.
The bit stream needs neither address nor steering bits due
to the innovative BitGrabber registers. Therefore, all bits in
the stream are available to be data for the two registers. Ran-
dom access of either register is provided. That is, the regis-
ters may be accessed in any sequence. Data is retained in
the registers over a supply range of 3 to 5.5 V. Formats are
shown in Figures 8 through 14 and summarized in Table 2.
Information on the segment decoder is given in Table 1.
Data In typically switches near 50% of VDD and has a
Schmitt–triggered input buffer. These features combine to
maximize noise immunity for use in harsh environments and
bus applications. This input can be directly interfaced to
CMOS devices with outputs guaranteed to switch near rail–
to–rail. When interfacing to NMOS or TTL devices, either a
level shifter (MC14504B, MC74HCT04A) or pullup resistor of
1 kΩ to 10 kΩ must be used. Parameters to be considered
when sizing the resistor are the worst–case IOL of the driving
device, maximum tolerable power consumption, and maxi-
mum data rate.
Clock (Pin 11)
Serial Data Clock Input. Low–to–high transitions on Clock
shift bits available at Data In, while high–to–low transitions
shift bits from Data Out. The chip’s 24–1/2–stage shift regis-
ter is static, allowing clock rates down to dc in a continuous or
intermittent mode. The Clock input does not need to be syn-
chronous with the on–chip clock oscillator which drives the
multiplexing circuit.
Eight clock cycles are required to access the configuration
register, while 24 are needed for the display register when the
MC14489B is not cascaded. See Figures 8 and 9.
As shown in Figure 10, two devices may be cascaded. In
this case, 32 clock cycles access the configuration register
and 48 access the display register, as depicted in Figure 10.
Cascading of 3, 4, 5, and 6 devices is shown in Figures 11,
12, 13, and 14, respectively. Also, reference Table 2.
Clock typically switches near 50% of VDD and has a
Schmitt–triggered input buffer. Slow Clock rise and fall times
are tolerated. See the last paragraph of Data In for more in-
formation. NOTE
To guarantee proper operation of the power–on
reset (POR) circuit, the Clock pin must NOT be
floated or toggled during power–up. That is, the
Clock pin must be stable until the VDD pin
reaches at least 3 V.
If control of the Clock pin during power–up is not
practical, then the MC14489B must be reset via bit
C0 in the C register. To accomplish this, C0 is re-
set low, then set high.
Enable (Pin 10)
Active–Low Enable Input. This pin allows the MC14489B to
be used on a serial bus, sharing Data In and Clock with other
peripherals. When Enable is in an inactive high state, Data
Out is forced to a known (low) state, shifting is inhibited, and
the port is held in the initialized state. To transfer data to the
device, Enable (which initially must be inactive high) is taken
low, a serial transfer is made via Data In and Clock, and
Enable is taken high. The low–to–high transition on Enable
transfers data to either the configuration or display register,
depending on the data stream length.
Every rising edge on Enable initiates a blanking interval
while data is loaded. Thus, continually loading the device with
the same data may cause the LEDs on some banks to appear
dimmer than others.
NOTE
Transitions on Enable must not be attempted
while Clock is high. This puts the device out of
synchronization with the microcontroller. Resyn-
chronization occurs when Enable is high and
Clock is low.
This input is also Schmitt–triggered and switches near 50%
of VDD, thereby minimizing the chance of loading erroneous
data in the registers. See the last paragraph of Data In for
more information.
Data Out (Pin 18)
Serial Data Output. Data is transferred out of the shift regis-
ter through Data Out on the high–to–low transition of Clock.
This output is a no connect, unless used in one of the man-
ners discussed below.
When cascading MC14489B’s, Data Out feeds Data In of the
next device per Figures 10, 11, 12, 13, and 14.
Data Out could be fed back to an MCU/MPU to perform a
wrap–around test of serial data. This could be part of a sys-
tem check conducted at power–up to test the integrity of the
system’s processor, pc board traces, solder joints, etc.
The pin could be monitored at an in–line Q.A. test during
board manufacturing.
Finally, Data Out facilitates troubleshooting a system.
DISPLAY INTERFACE
Rx (Pin 8)
External Current–Setting Resistor. A resistor tied between
this pin and ground (VSS) determines the peak segment drive
current delivered at pins a through h. Pin 8’s resistor ties into
a current mirror with an approximate current gain of 10 when
bit D23 = high (brighten). With D23 = low, the peak current is
reduced about 50%. Values for Rx range from 700 Ω to infin-
ity. When Rx = ∞ (open circuit), the display is extinguished.
For proper current control, resistors having ±1% tolerance
should be used. See Figure 7.
CAUTION
Small Rx values may cause the chip to overheat
if precautions are not observed. See Thermal
Considerations.
MC14489BMOTOROLA 7
a through h (Pins 1, 2, 4 – 7, 19, 20)
Anode–Driver Current Sources. These outputs are close-
ly–matched current sources which directly tie to the anodes
of external discrete LEDs (lamps) or display segment LEDs.
Each output is capable of sourcing up to 35 mA.
When used with lamps, outputs a, b, c, and d are used to
independently control up to 20 lamps. Output h is used to con-
trol up to 5 lamps dependently. (See Figure 17.) For lamps,
the
No Decode
mode is selected via the configuration regis-
ter, forcing e, f, and g inactive (low).
When used with segmented displays, outputs a through g
drive segments a through g, respectively. Output h is used to
drive the decimals. Refer to Figure 9. If unused, h must be left
open.
Bank 1 through Bank 5 (Pins 9, 13, 15, 16, 17)
Diode–Bank FET Switches. These outputs are low–resis-
tance switches to ground (VSS) capable of handling currents
of up to 320 mA each. These pins directly tie to the common
cathodes of segmented displays or the cathodes of lamps
(wired with cathodes common).
The display is refreshed at a nominal 1 kHz rate to achieve
optimum brightness from the LEDs. A 20% duty cycle is uti-
lized.
Special design techniques are used on–chip to accommo-
date the high currents with low EMI (electromagnetic interfer-
ence) and minimal spiking on the power lines.
POWER SUPPLY
VSS (Pin 14)
Most–negative supply potential. This pin is usually ground.
Resistor Rx is externally tied to ground (VSS). Therefore,
the chip’s VSS pin does not contain the Rx current compo-
nent.
VDD (Pin 13)
Most–positive supply potential.
To guarantee data integrity in the registers and to ensure
the serial interface is functional, this voltage may range from
3 to 6 volts with respect to VSS. For example, within this volt-
age range, the chip could be placed in and out of the low–
power mode.
To adequately drive the LEDs, this voltage must be 4.5 to
6 volts with respect to VSS.
The VDD pin contains the Rx current component plus the
chip’s current drain. In the low–power mode, the current mir-
ror and clock oscillator are turned off, thus significantly reduc-
ing the VDD current, IDD.
Figure 7. a through h Nominal Current per Output versus Rx
35
30
25
20
15
10
5400 800 1.2 k 2.0 k 2.4 k 2.8 k 3.2 k 3.6 k 4.0 k1.6 k
iOH, PEAK DRIVE CURRENT (mA)
5 V SUPPLY
BIT D23 = HIGH (BRIGHTEN LEDs)
WITH D23 = LOW, iOH IS CUT BY
∼
50%.
Rx, EXTERNAL RESISTOR (
Ω
)
NOTE:Drive current tolerance is approximately ± 15%.
Table 1. Triple-Mode Segment Decoder Function Table
Lamp Conditions
No DecodeG)
(Invoked via
Bits C1 to C7)
7-Segment Display
CharactersBank Nibble Value
Special
Decode
(Invoked via
Bits C1 to C7)
Hex Decode
(Invoked via
Bits C1 to C5)
Binary
MSB LSB
Hexadecimal dbc a
"
u
I
I
2
3
$0
$1
$2
$3
L L L
L L H
L H L
L H H
c
,','
,'I
on
on
on on
l./
s
G
,,
8
9
'-I
,-,
'c,
~
$4
$5
$6
$7
H L L
H L H
H H L
H H H
on
on on
on on
on on on
$8
$9
$A
$B
IH L L L
H L L H
H L H L
H L H H
on
,-
u
LI
on on
on on
on on on
,-
L
,
c'
E
F
$C
$0
$E
$F
~
H
H
H
H
on on
on on on
on on on
0on on on on
NOTES:
1. In the No Decode mode, outputs e, f, and g are unused and are all forced inactive (low). Output
h decoding is unaffected, i.e., unchanged from the other modes. The No Decode mode is used
for three purposes:
a. Individually controlling lamps.
b. Controlling a half digit with sign.
c. Controlling annunciators. examples: AM, PM, UHF, kV, mm Hg.
2. Can be used as capital S.
3. Can be used as capital B.
4. Can be used as small g.
MC14489B
8
MOTOROLA
@
~@
,
u
I
L
"
O
O
,
H
H
H
H r
L
H
L
H
MC14489BMOTOROLA 9
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
Figure 8. Timing Diagrams for Non–Cascaded Devices
ÇÇÇ
ÇÇÇ
ÇÇÇ
D22
ÇÇÇ
D21
ÇÇÇ
D20
ÇÇÇ
D19
ÇÇÇ
D18
ÇÇÇ
ÇÇÇ
D17
ÇÇÇ
D16
ÇÇÇ
ÇÇÇ
D15
ÇÇÇ
D14
ÇÇÇ
ÇÇÇ
D13
ÇÇÇ
D12
ÇÇÇ
D11
ÇÇÇ
D10
ÇÇÇ
D9
ÇÇÇ
ÇÇÇ
D8
ÇÇÇ
D7
ÇÇÇ
ÇÇÇ
D6
ÇÇÇ
D5
ÇÇÇ
ÇÇÇ
D4
ÇÇÇ
D3
ÇÇÇ
D2
ÇÇÇ
D1
ÇÇÇ
ÇÇÇ
ÇÇÇ
D0
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
D23
234567891011121314151617181920212223241
MSB LSB
L = DIM LEDs, H = BRIGHTEN LEDs
THE LSBs OF EACH BANK NIBBLE ARE D0, D4, D8, D12, AND D16.
BANK 5
NOTE: The low–power (standby) mode places the device
C6 C5 C4 C3 C2 C1C7
23456781
MSB
ENABLE
CLOCK
DATA IN
in a static state, thus eliminating EMI and mux switching
noise. Therefore, during precision analog measurements,
the low–power mode could be invoked by a system’s MCU.
Also, the low–power mode blanks the display, and could
be used to flash the LEDs on and off.
C0
L = LOW POWER MODE (BLANKS THE DISPLAY), FORCED LOW (L) BY POWER ON RESET
H = NORMAL MODE
CONTROLS BANK 1:
CONTROLS BANK 2: L = HEX DECODE, H = DEPENDS ON C6
CONTROLS BANK 3: L = HEX DECODE, H = DEPENDS ON C6
CONTROLS BANK 4: L = HEX DECODE, H = DEPENDS ON C7
CONTROLS BANK 5: L = HEX DECODE, H = DEPENDS ON C7
SEE TABLE 1
L = NO DECODE, H = SPECIAL DECODE (REFER T O C1, C2, AND C3)
L = NO DECODE, H = SPECIAL DECODE (REFER TO C4 AND C5)
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
= ALL h OUTPUTS INACTIVE
= ACTIVATE h IN BANK 1
= ACTIVATE h IN BANK 2
= ACTIVATE h IN BANK 3
= ACTIVATE h IN BANK 4
= ACTIVATE h IN BANK 5
= ACTIVATE h IN BOTH BANKS 1 AND 2
= ACTIVATE h IN ALL BANKS
NIBBLE BANK 4
NIBBLE BANK 3
NIBBLE BANK 2
NIBBLE BANK 1
NIBBLE
SEE TABLE 1
ENABLE
CLCOK
DATA IN
LSB
(a) Configuration Register Format (1 Byte)
(b) Display Register Format (3 Bytes)
NOTE: L = Low Voltage Level (Logic 0), H = High Voltage Level (Logic 1)
L = HEX DECODE, H = DEPENDS ON C6
MC14489B MOTOROLA
10
APPLICATIONS INFORMATION
Figure 9. Non–Cascaded Application Example: 5 Character Common Cathode
LED Display with Two Intensities as Controlled via Serial Port
#5 #4 #3 #2 #1
8
88888
d
a
b
ce
f
g
BANK 5
BANK 4
BANK 3
BANK 2
BANK 1
d
a
b
c
e
f
g
h
OPTIONAL
CMOS
MCU/MPU
+ 5 V Rx
VDD
VSS
DATA OUT
Rx
DATA IN
CLOCK
ENABLE
+ 5 V MC14489B
•
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15
MC14489B MOTOROLA
16
Table 2. Register Access for Two or More Cascaded Devices
Cii*
Configuration Register Access Display Register Access
Criteria* Total Number of Bytes Number of Leading
“Don’t Care” Bytes Total Number of Bytes Number of Leading
“Don’t Care” Bytes
If 3N is a Multiple of 4 3N 2 3N + 2 2
If 3N – 1 is a Multiple of 4 3N – 1 1 3N + 1 1
If 3N – 2 is a Multiple of 4 3N – 2 0 3N 0
If 3N – 3 is a Multiple of 4 3N – 2 0 3N 0
*N = number of devices that are cascaded. For example, to drive 10 digits, 2 devices are cascaded; therefore, N = 2. To drive 35 digits, seven
devices are cascaded; therefore N = 7.
Figure 15. Common–Cathode LED Display with Dial–Adjusted Brightness
VSS
CMOS
MCU/MPU Rx
LED DISPLAY
MC14489B
85
+ 5 V
R1
R2
VDD
+ 5 V
NOTE:R1 limits the maximum current to avoid damaging the display and/or the MC14489B
due to overheating. See the Thermal Considerations section. An 1/8 watt resistor
may be used for R1. R2 is a 1 kΩ or 5 kΩ potentiometer (≥ 1/8 watt). R2 may be a
light–sensitive resistor.
MC14489BMOTOROLA 17
Figure 16. Driving 5 1/2 Digits
4
UNIVERSAL OVERFLOW
(“1” OR “HALF–DIGIT”)
MC14489B
5h
3
a TO g321BANK OUTPUTS
7
USE TO DRIVE LAMP
OR MINUS SIGN
5–DIGIT DISPLAY
INPUT LINES
NOTE:A Universal Overflow pins out all anodes and cathodes.
MC14489B MOTOROLA
18
Figure 17. 25–Lamp Application
3
BANK 5
BANK 4
BANK 3
BANK 2
BANK 1
d
a
b
c
e
f
g
h
CMOS
MCU/MPU
NC
NC
NC
MC14489B
THESE LAMPS DEPENDENTLY
CONTROLLED WITH
BITS D20, D21, AND D22*
THESE LAMPS
INDEPENDENTLY
CONTROLLED WITH
BITS D0 TO D19
*If required, this group of lamps can be independently controlled. To accomplish independent control, only connect lamps to BANK 1 and
BANK 2 for output h (two lamps). Then, use bits D20, D21, and D22 for control of these two lamps.
MC14489BMOTOROLA 19
Figure 18. 4–Digit Display Plus Decimals with Four Annunciators
or 4–1/2–Digit Display Plus Sign
4
CMOS MCU/MPU
a TO d BANK 1
TO
BANK 4
BANK 5
MC14489B
4 4
e TO h
3
4
•
Figure 19. Compact Display System with Three Components
INPUT LINES
3
8
14
MC14489B
MUXED 5–DIGIT MONOLITHIC DISPLAY (CLUSTER)
HEWLETT–PACKARD 5082–7415 OR EQUIVALENT
123621085113497
6 5 4 2 1 20 19 17 16 15 13 97
MC14489B MOTOROLA
20
THERMAL CONSIDERATIONS
The MC14489B is designed to operate with a
chip–junction
temperature (TJ) ranging from – 40 to 130°C, as indicated in
the electrical characteristics tables. The
ambient
operating
temperature range (TA) is dependent on RθJA, the internal
chip current, how many anode drivers are used, the number
of bank drivers used, the drive current, and how the package
is cooled. The maximum ratings table gives the thermal resis-
tance, junction–to–ambient, of the MC14489B mounted on a
pc board using natural convection to be 90°C per watt for the
plastic DIP. The SOG thermal resistance is 100°C per watt.
The following general equation (1) is used to determine the
power dissipated by the MC14489B.
PT = PD + PI(1)
where
PT=Total power dissipation of the MC14489B
PD=Power dissipated in the driver circuitry (mW)
PI=Power dissipated by the internal chip
circuitry (mW)
The equations for the two terms of the general equation
are:
PD = (iOH) (N)(VDD – VLED)(B/5) (2)
(3)PI = (1.5 mA)(VDD) + IRx(VDD – IRxRx)
where
iOH =Peak anode driver current (mA)
IRx =i
OH /10, with iOH = the peak anode driver current
(mA) when the dimmer bit is high
N=Number of anode drivers used
B=Number of bank drivers used
Rx=External resistor value (kΩ)
VDD =Maximum supply voltage, referenced to VSS
(volts)
VLED =Minimum anticipated voltage drop across the
LED
1.5 mA=Operating supply current of the MC14489B
The following two examples show how to calculate the
maximum allowable ambient temperature.
Worst–Case Analysis Example 1:
5–digit display with decimals (5 banks and 8 anode drivers)
DIP without heat sink on PC board
iOH =20 mA max
VLED =1.8 V min
VDD =5.25 max
PD = (20)(8)(5.25 – 1.8)(5/5) = 552 mW Ref. (2)
PI = (1.5)(5.25) + 2[5.25 – 2(2)] = 10 mW Ref. (3)
Therefore, PT = 552 + 10 = 562 mW Ref. (1)
and ∆Tchip = RθJAPT = (90°C/W)(0.562) = 51°C
Finally, the maximum allowable
TA = TJmax – ∆Tchip = 130 – 51 = 79°C
That is, if TA = 79°C, the maximum junction temperature is
130°C. The chip’s average temperature for this example is
lower than 130°C because all segments are usually not illumi-
nated simultaneously for an indefinite period.
Worst–Case Analysis Example 2:
16 lamps (4 banks and 4 anode drivers)
SOG without heat sink on PC board
iOH =30 mA max
VLED =1.8 V min
VDD =5.5 max
PD = (30)(4)(5.5 – 1.8)(4/5) = 355 mW Ref. (2)
PI = (1.5)(5.5) + 3[5.5 – 3(1.0)] = 16 mW Ref. (3)
Therefore, PT = 355 + 16 = 371 mW Ref. (1)
and ∆Tchip = RθJAPT = (100°C/W)(0.371) = 37°C
Finally, the maximum allowable
TA = TJmax – ∆Tchip = 130 – 37 = 93°C
To extend the allowable ambient temperature range or to
reduce TJ, which extends chip life, a heat sink such as shown
in Figure 20 can be used in high–current applications. Alter-
natively, heat–spreader techniques can be used on the PC
board, such as running a wide trace under the MC14489B and
using thermal paste. Wide, radial traces from the MC14489B
leads also act as heat spreaders.
AAVID #5804 or equivalent
(Tel. 603/524–4443, FAX 603/528–1478)
Motorola cannot recommend one supplier over another and
in no way suggests that this is the only heat sink supplier.
Figure 20. Heat Sink
Table 3. LED Lamp and Common–Cathode Display
Manufacturers
Supplier
QT Optoelectronics
Hewlett–Packard (HP), Components Group
Industrial Electronic Engineers (IEE), Component Products Div.
Purdy Electronics Corp., AND Product Line
NOTE:Motorola cannot recommend one supplier over another
and in no way suggests that this is a complete listing of
LED suppliers.
MC14489BMOTOROLA 21
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC DIP
CASE 738–03
1.070
0.260
0.180
0.022
0.070
0.015
0.140
15
°
0.040
1.010
0.240
0.150
0.015
0.050
0.008
0.110
0
°
0.020
25.66
6.10
3.81
0.39
1.27
0.21
2.80
0
°
0.51
27.17
6.60
4.57
0.55
1.77
0.38
3.55
15
°
1.01
0.050 BSC
0.100 BSC
0.300 BSC
1.27 BSC
2.54 BSC
7.62 BSC
MIN MINMAX MAX
INCHES MILLIMETERS
DIM
A
B
C
D
E
F
G
J
K
L
M
N
NOTES:
1.DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2.CONTROLLING DIMENSION: INCH.
3.DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4.DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
-A-
C
K
NE
GF
D 20 PL
J 20 PL
L
M
-T-
SEATING
PLANE
110
1120
0.25 (0.010) T A
M M 0.25 (0.010) T B
M M
B
DW SUFFIX
SOG PACKAGE
CASE 751D–04
NOTES:
1.DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2.CONTROLLING DIMENSION: MILLIMETER.
3.DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4.MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5.DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
–A–
–B–
20
1
11
10
SA
M0.010 (0.25) BS
T
D20X
MB
M0.010 (0.25)
P10X
J
F
G18X K
C
–T–
SEATING
PLANE
M
RX 45
_
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 12.65 12.95 0.499 0.510
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029
____
MC14489 A
22
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MC14489B
