PGA2505 PG A 250 5 Burr-Brown Audio www.ti.com ......................................................................................................................................................... SBOS396B - MARCH 2009 - REVISED JUNE 2009 TM Digitally-Controlled MICROPHONE PREAMPLIFIER FEATURES APPLICATIONS * FULLY DIFFERENTIAL lNPUT-TO-OUTPUT ARCHITECTURE * DIGITALLY-CONTROLLED GAIN USING SPITM: - Gain Range: 9dB through 60dB, 3dB per Step - Unity (0dB) Gain Setting via Serial Port * DYNAMIC PERFORMANCE: - Equivalent Input Noise with ZS = 150 and Gain = 30dB: -123dBu - Total Harmonic Distortion plus Noise (THD+N) with Gain = 30dB: 0.0006% * ZERO CROSSING DETECTION MINIMIZES AUDIBLE ARTIFACTS WHEN GAIN SWITCHING * INTEGRATED DC SERVO MINIMIZES OUTPUT OFFSET VOLTAGE * COMMON-MODE SERVO IMPROVES CMRR * FOUR-WIRE SERIAL CONTROL PORT INTERFACE: - Simple Interface to Microprocessor or DSP Serial Ports - Supports Daisy-Chaining of Multiple PGA2505 Devices * OVER-RANGE OUTPUT PIN PROVIDES CLIPPING INDICATION * FOUR GENERAL-PURPOSE DIGITAL OUTPUT PINS * 5V POWER SUPPLIES * AVAILABLE IN AN SSOP-24 PACKAGE * * * * * 1 234 MICROPHONE PREAMPLIFIERS AND MIXERS DIGITAL MIXERS AND RECORDERS DIGITAL AUDIO EDITING SYSTEMS BROADCAST EQUIPMENT INTERCOMS DESCRIPTION The PGA2505 is a digitally-controlled, analog microphone preamplifier designed for use as a front-end for high-performance audio analog-to-digital converters (ADCs). The PGA2505 features include low noise, wide dynamic range, and a differential signal path. An on-chip dc servo loop is employed to minimize dc offset, while a common-mode servo function may be used to enhance common-mode rejection. SoundPlusTM The PGA2505 features a gain range of 9dB through 60dB (3dB/step), along with a unity gain setting. The wide gain range allows the PGA2505 to be used with a variety of microphones. Gain settings and internal functions are programmed using a 16-bit control word, which is loaded using a simple serial port interface. A serial data output pin provides support for daisy-chained connection of multiple PGA2505 devices. Four programmable digital outputs are provided for controlling the external switching of input pads, phantom power, and high-pass filters. The PGA2505 requires both +5V and -5V power supplies and is available in a small SSOP-24 package. 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SoundPlus is a trademark of Texas Instruments Incorporated. SPI is a trademark of Motorola, Inc.. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2009, Texas Instruments Incorporated PGA2505 SBOS396B - MARCH 2009 - REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. PGA2505 UNIT Supply Voltage, AGND or DGND to VA+ -0.3 to +5.5 V Supply Voltage, AGND or DGND to VA- +0.3 to -5.5 V Supply Voltage, AGND or DGND to VD- +0.3 to -5.5 V Voltage Difference, VA- to VD- 0.3 V Ground Difference, AGND to DGND 0.3 V Analog Input Voltage (VA-) -0.3 to (VA+) +0.3 V Digital Input Voltage (DGND) - 0.3 to (VA+) + 0.3 V 10 mA Input Current of All Pins Except Supply Power Dissipation See Electrical Characteristics, Thermal Resistance parameter Junction Temperature Range, TJ -40 to +150 C Operating Free-Air Temperature Range, TA -40 to +85 C Storage Temperature Range, TSTG -60 to +150 C Human Body Model (HBM) 2000 V Charged Device Model (CDM) 1000 V Machine Model (MM) 150 V ESD Ratings (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. ORDERING INFORMATION (1) (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING PGA2505 SSOP-24 DB PGA2505I For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. 2 Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): PGA2505 PGA2505 www.ti.com ......................................................................................................................................................... SBOS396B - MARCH 2009 - REVISED JUNE 2009 ELECTRICAL CHARACTERISTICS At TA = +25C, VA+ = +5V, VA- = -5V, VD- = -5V, and VCOMIN = 0V, unless otherwise noted. PGA2505 PARAMETERS CONDITIONS MIN TYP MAX UNIT DC CHARACTERISTICS Step Size Gain = 9dB through 60dB 3 dB Gain Error All gain settings 0.5 dB fIN = 1kHz, Gain = 0dB, VOUT = 3.5VRMS -110 -100 dB fIN = 1kHz, Gain = 30dB, VOUT = 3.5VRMS -105 -95 dB VA+ -2.0 V AC CHARACTERISTICS THD+N ANALOG INPUT Maximum Input Voltage Gain = 0dB VA- +1.5 Input Resistance Per Input Pin 4600 Differential 9200 ANALOG OUTPUT Output Voltage Range VCOMIN = 0V, RL = 600 Output Offset Voltage DC servo on, any gain Input-Referred Offset DC servo off, gain = 30dB Output Resistive Loading VA- +0.9 0.08 VA+ -0.9 V 1 mV 1 mV 100 pF 100 mA 600 Load Capacitance Stability Short Circuit Current 10-second duration DIGITAL CHARACTERISTICS High-Level Input Voltage VIH +2.0 VA+ V Low-Level Input Voltage VIL -0.3 0.8 V High-Level Output Voltage VOH IO = 200A Low-Level Output Voltage VOL IO = -3.2mA Input Leakage Current (VA+) - 1.0 IIN V 0.4 V 2 10 A POWER SUPPLY Operating Voltage VA+ +4.75 +5 +5.25 V VA- -4.75 -5 -5.25 V VD- -4.75 -5 -5.25 V Quiescent Current IA+ VA+ = +5V 30 40 mA IA- VA- = -5V 30 40 mA ID- VD- = -5V 1 2 mA /85 C TEMPERATURE RANGE Operating Free-Air Temperature Range TA -40 Thermal Resistance SSOP-24 JA High-K board 72 C/W JC High-K board 42 C/W 3 Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): PGA2505 PGA2505 SBOS396B - MARCH 2009 - REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com SWITCHING CHARACTERISTICS Over operating free-air temperature range (unless otherwise noted). PGA2505 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 6.25 MHz fSCLK Serial clock (SCLK) frequency 0 tPH Serial clock (SCLK) pulse width low 80 ns tPL Serial clock (SCLK) pulse width high 80 ns TIMING REQUIREMENTS Over operating free-air temperature range (unless otherwise noted). PGA2505 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT TIMING tSDS SDI setup time 20 ns tSDH SDI hold time 20 ns tCSCR CS falling to SCLK rising 90 ns tCFCS SCLK falling to CS rising 35 ns OUTPUT TIMING tCSO CS low to SDO active 35 ns tCFDO SCLK falling to SDO data valid 60 ns tCSZ CS high to SDO high impedance 100 ns SERIAL PORT TIMING DIAGRAM CS tSDS tCSCR tCFCS tSDH SCLK SDI MSB SDO MSB tCSO tCFDO 4 tCSZ Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): PGA2505 PGA2505 www.ti.com ......................................................................................................................................................... SBOS396B - MARCH 2009 - REVISED JUNE 2009 PIN CONFIGURATION DB PACKAGE SSOP-24 (TOP VIEW) AGND 1 24 VIN+ GPO1 2 23 VIN- GPO2 3 22 VCOMIN GPO3 4 21 CS11 GPO4 5 20 CS12 OVR 6 19 CS21 DGND 7 18 CS22 SDI 8 17 VA- CS 9 16 VA+ SCLK 10 15 VOUT+ SDO 11 14 VOUT- VD- 12 13 VA- PGA2505 PIN ASSIGNMENTS TERMINAL NAME PIN# AGND 1 Analog Ground DESCRIPTION GPO1 2 General-Purpose CMOS Logic Output GPO2 3 General-Purpose CMOS Logic Output GPO3 4 General-Purpose CMOS Logic Output GPO4 5 General-Purpose CMOS Logic Output OVR 6 Over Range Output (Active High) DGND 7 Digital Ground SDI 8 Serial Data Input CS 9 Chip Select Input (Active Low) SCLK 10 Serial Data Clock Input SDO 11 Serial Data Output VD- 12 -5V Digital Supply VA- 13 -5V Analog Supply VOUT- 14 Inverting Analog Output VOUT+ 15 Noninverting Analog Output VA+ 16 +5V Analog Supply VA- 17 -5V Analog Supply CS22 18 External DC Servo Capacitor #2, Terminal 2 CS21 19 External DC Servo Capacitor #2, Terminal 1 CS12 20 External DC Servo Capacitor #1, Terminal 2 CS11 21 External DC Servo Capacitor #1, Terminal 1 VCOMIN 22 Common Mode Voltage Input, 0V to +2.5V VIN- 23 Inverting Analog Input VIN+ 24 Noninverting Analog Input 5 Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): PGA2505 PGA2505 SBOS396B - MARCH 2009 - REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS At TA = +25C, VA+ = +5V, VA- = -5V, VD- = -5V, and VCOMIN = 0V, unless otherwise noted. EQUIVALENT INPUT NOISE AS A FUNCTION OF GAIN WITH ZS = 150 -110 -110 -112 -112 -114 -114 -116 -116 EIN (dBu) EIN (dBu) EQUIVALENT INPUT NOISE AS A FUNCTION OF GAIN WITH ZS = 0 -118 -120 -118 -120 -122 -122 -124 -124 -126 -126 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 Gain (dB) Gain (dB) Figure 1. Figure 2. THD+N vs GAIN THD+N vs GAIN AND NOISE vs GAIN -60 VOUT = 4.0VRMS ZS = 40W -70 THD+N and Noise (dB) Total Harmonic Distortion + Noise (%) 0.01 0.001 -80 THD+N with ZS = 40W VOUT = 4.0VRMS -90 -100 -110 Noise with ZS = 0W Reference 0dB = 4.0VRMS -120 -130 0.0001 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 Gain (dB) Gain (dB) Figure 3. Figure 4. THD + N vs FREQUENCY (ZS = 40, RL = 600, VCOMIN = 0V, BW = 22Hz to 22kHz) THD + N vs FREQUENCY (ZS = 40, RL = 600, VCOMIN = +2.5V, BW = 22Hz to 22kHz) 0.1 VOUT = 4.0VRMS Differential for Gains = 12dB, 24dB, 30dB, 36dB, 48dB, and 60dB VOUT = 3.5VRMS Differential for Gain = 0dB 0.01 48dB 24dB 30dB 0.001 VOUT = 2.0VRMS Differential for Gains = 12dB, 24dB, 30dB, 36dB, 48dB, and 60dB 60dB 60dB 36dB THD+N Ratio (%) THD+N Ratio (%) 0.1 0.01 VOUT = 1VRMS Differential for Gain = 0dB 48dB 36dB 0dB 0.001 30dB 12dB 0dB 12dB 24dB 0.0001 0.0001 20 100 1k 10k 20k 20 Frequency (Hz) 100 1k 10k 20k Frequency (Hz) Figure 5. Figure 6. 6 Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): PGA2505 PGA2505 www.ti.com ......................................................................................................................................................... SBOS396B - MARCH 2009 - REVISED JUNE 2009 TYPICAL CHARACTERISTICS (continued) At TA = +25C, VA+ = +5V, VA- = -5V, VD- = -5V, and VCOMIN = 0V, unless otherwise noted. THD + N vs FREQUENCY (ZS = 40, RL = 600, VCOMIN = +2.5V, BW = 22Hz to 22kHz) 0.1 THD + N vs OUTPUT SWING (ZS = 40, RL = 600, VCOMIN = 0V, BW = 22Hz to 22kHz) 0.1 VOUT = 1.0VRMS Differential for All Gain Settings 0.01 48dB 36dB 30dB 0.001 12dB Gain = 30dB f = 1kHz 0.0001 20 100 1k 0.01 0.001 0dB 24dB THD+N (%) THD+N Ratio (%) 60dB 10k 20k 0.0001 0.03 0.3 3 6 Output Amplitude (VRMS) Frequency (Hz) Figure 7. Figure 8. 7 Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): PGA2505 PGA2505 SBOS396B - MARCH 2009 - REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com APPLICATION INFORMATION space OVERVIEW The differential analog output of the PGA2505 is constantly monitored by a dc servo amplifier loop. The purpose of the servo loop is to minimize the dc offset voltage present at the analog outputs by feeding back an error signal to the input stage of the programmable gain amplifier. The error signal is then used to correct the offset. The DC servo may be disabled by setting the dc bit in the serial control word to '1'. The PGA2505 is a digitally-controlled microphone preamplifier integrated circuit designed to amplify the output of dynamic and condenser microphones and drive high-performance audio analog-to-digital converters (ADCs). A functional block diagram of the PGA2505 is shown in Figure 9. The analog input to the preamplifier is provided differentially at the VIN+ and VIN- inputs (pins 24 and 23, respectively). The programmable gain amplifier can be programmed to either pass through the signal at unity gain, or apply 9dB to 60dB of gain to the input signal. The gain of the amplifier is adjustable over the full 9dB to 60dB range in 3dB steps. The differential output of the PGA2505 is made available at VOUT+ and VOUT- (pins 15 and 14, respectively). Gain is controlled using a serial port interface. Two external capacitors are required for the dc servo function, with one capacitor connected between CS11 and CS12 (pins 21 and 20), and the second capacitor connected between CS21 and CS22 (pins 19 and 18). A capacitor value of 1F is recommended for use in most microphone preamplifier applications. Capacitor values up to 4.7F may be used. However, larger valued capacitors result in longer settling times for the dc servo loop. Smaller capacitors under 0.22F may result in additional distortion in the low frequency audio bandwidth. The four-wire serial port interface is used to program the PGA2505 gain and support functions. A 16-bit control word is utilized to program these functions (see Figure 10). A serial data output pin provides support for daisy-chaining multiple PGA2505 devices on a single serial interface bus (see Figure 11). GPO1 CS GPO2 SCLK SERIAL PORT and LOGIC CONTROL GPO3 GPO4 SDI SDO OVR VCOMIN VOUT+ VIN+ PGA VOUT- VIN(1) Gain Range (2) AGND VA+ VA- CS1 DGND DC Servo VD- CS2 (1) Gain Range: 0dB, or +9dB to +60dB (3dB/step). (2) CS1 and CS2 are external dc servo integrator capacitors, and are connected across the CS11/CS12 and CS21/CS22 pins, respectively. Figure 9. PGA2505 Functional Block Diagram 8 Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): PGA2505 PGA2505 www.ti.com ......................................................................................................................................................... SBOS396B - MARCH 2009 - REVISED JUNE 2009 The PGA2505 includes a common-mode servo function. This function is enabled and disabled using the CM bit in the serial control word; see Figure 10. When enabled, the servo provides common-mode negative feedback at the input differential pair, resulting in very low common-mode input impedance. The differential input impedance is not affected by this feedback. This function is useful when the source is floating, or has a high common-mode output impedance. When the source is floating, the only connection between the source and the ground is through the PGA2505 preamplifier input resistance. The input common-mode parasitic current is determined by high output impedance of the source, not by input impedance of the amplifier. Therefore, input common-mode interference can be reduced by lowering the common-mode input impedance while at the same time not increasing the input common-mode current. Increasing common-mode current degrades common-mode rejection. Using the common-mode servo, overall common-mode rejection can be improved by suppressing low and medium frequency common-mode interference. The common-mode servo function is designed to operate with a total common-mode input capacitance (including the microphone cable capacitance) of up to 10nF. Beyond this limit, stable servo operation is not assured. The common-mode voltage control input, named VCOMIN (pin 22), allows the PGA2505 output and input to be dc-biased to a common-mode voltage between 0V and +2.5V and should not be left floating. This configuration allows for a dc-coupled interface between the PGA2505 preamplifier output and the inputs of common single-supply audio ADCs. The zero crossing control input is provided for enabling and disabling the internal zero crossing detector function. This function is enabled and disabled using the ZC bit in the serial control word; see Figure 10. Zero crossing detection is used to force gain changes on zero crossings of the analog input signal. This configuration limits the glitch energy associated with switching gain, thereby minimizing audible artifacts at the preamplifier output. Because zero crossing detection can add some delay when performing gain changes (up to 16ms maximum for a detector timeout event), there may be cases where the user may wish to disable the function. Setting the ZC bit high enables zero crossing detection, with gain changes occurring immediately when programmed. An over-range indicator output, OVR, is provided at pin 6. The OVR pin is an active high, CMOS-logic-level output. The over-range output is forced high when the preamplifier output voltage exceeds one of two preset thresholds. The threshold is programmed through the serial port interface using the OR bit. If OR = '0', then the output threshold is set to 5.1VRMS differential, which is approximately 1dB below the specified output voltage range. If OR = '1', then the output threshold is set to 4.0VRMS differential, which is approximately 3dB below the specified output voltage range. The PGA2505 includes four programmable digital outputs, named GPO1, GPO2, GPO3, and GPO4 (pins 2, 3, 4, and 5 respectively), that are controlled via the serial port interface. These pins are CMOS-logic-level outputs. These pins may be used to control relay drivers or switches used for external preamplifier functions, including input pads, filtering, polarity reversal, or phantom power. ANALOG INPUTS AND OUTPUTS An analog signal is input differentially across the VIN+ (pin 24) and VIN- (pin 23) inputs. The input voltage range and input impedance are provided in the Electrical Characteristics table. The Applications Information section of this data sheet provides additional details regarding typical input circuit considerations when interfacing the PGA2505 to a microphone input. Both VIN+ and VIN- are biased at approximately 0.65V below the common-mode input voltage, supplied at VCOMIN (pin 22). The use of ac-coupling capacitors (see Figure 10) is highly recommended for the analog inputs of the PGA2505. If dc-coupling is required for a given application, the user must take this offset into account. It is recommended that a small capacitor be connected from each analog input pin to analog ground. Values of at least 50pF are recommended. See Figure 10 for larger capacitors used for EMI filtering, which satisfies this requirement. The analog output is presented differentially across VOUT+ (pin 15) and VOUT- (pin 14). The output voltage range is provided in the Electrical Characteristics table. The analog output is designed to drive a 600 differential load while meeting the published THD+N specifications and typical performance graphs. Note that because the zero crossing detector requires setup, the user should set the ZC bit as a first operation. Subsequent changes in gain occur on the zero crossings provided that the ZC bit setting is maintained. 9 Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): PGA2505 PGA2505 SBOS396B - MARCH 2009 - REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com SERIAL PORT OPERATION The SCLK input is used to clock serial data into the SDI pin and out of the SDO pin. The SDI pin functions as the serial data input, and is used to write the serial port register. The SDO pin is the shift register serial output, and is used for either register read-back or for daisy-chaining multiple PGA2505 devices. Data on SDI are sampled on the rising edge of SCLK, while data are clocked out of SDO on the falling edge of SCLK. The serial port interface for the PGA2505 is comprised of four wires: CS (pin 9), SCLK (pin 10), SDI (pin 8), and SDO (pin 11). Figure 10 illustrates the serial port protocol. The CS input functions as the chip select and word latch clock for the serial port. The CS input must be low in order to clock data into and out of the serial port. The control word is latched on a low-to-high transition of the CS input. The serial port ignores the SCLK and SDI inputs when CS is high, and the SDO output is set to a high impedance state while CS is high. CS SCLK SDI Data Ignored DC CM ZC OR D4 D3 D2 D1 0 0 G5 G4 G3 G2 G1 G0 Data Ignored SDO High Impedance DC CM ZC OR D4 D3 D2 D1 0 0 G5 G4 G3 G2 G1 G0 High Impedance DC Servo Enable (Active Low) CM Servo Enable (Active High) Zero Crossing Detect (Active High) Over-Range Indicator Bit (0 = 5.1VRMS, 1 = 4.0VRMS) Data for GPO4 Preamplifier Gain where N = G[5:0]DEC For N = 0 Gain = 0dB For N = 1 to 17 Gain (dB) = 6 + 3N For N = 18 to 31 Gain = 60dB Data for GPO3 Data for GPO2 Data for GPO1 Figure 10. Serial Port Protocol 10 Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): PGA2505 PGA2505 www.ti.com ......................................................................................................................................................... SBOS396B - MARCH 2009 - REVISED JUNE 2009 DAISY-CHAINING MULTIPLE PGA2505 PREAMPLIFIERS Because the serial port interface may be viewed as a serial in, serial out shift register, multiple PGA2505 preamplifiers may be connected in a cascaded or daisy-chained fashion, as shown in Figure 11. The daisy-chained PGA2505 devices behave as a 16 x N-bit shift register, where N is the number of cascaded PGA2505 devices. VOUT+ To program all of the devices, simply force CS low for 16 x N serial clock periods and clock in 16 x N bits of control data. The CS input is then forced high to latch in the new settings. A timing diagram for the daisy-chain application is shown in Figure 12. SDI DOUT CS CS VOUTPGA2505 #1 SCLK VIN+ DATACLK Microprocessor or DSP DIN SDO VIN- VOUT+ SDI VOUTCS PGA2505 #2 SCLK VIN+ SDO VIN- VOUT+ SDI VOUTCS PGA2505 #N SCLK VIN+ SDO VIN- Figure 11. Daisy-Chain Configuration for Multiple PGA2505 Preamplifiers CS SCLK SDI G0 DC Device #N G0 DC G0 DC Device #2 Device #1 Figure 12. Serial Port Operation for Daisy-Chain Operation 11 Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): PGA2505 PGA2505 SBOS396B - MARCH 2009 - REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com APPLICATION INFORMATION This section provides practical information designing the PGA2505 into end applications. for BASIC CIRCUIT CONFIGURATION A typical application configuration, without the input and output circuitry, is shown in Figure 13. Power-supply bypass and dc servo capacitors are shown with recommended values. All capacitors should be placed as close as possible to the PGA2505 package to limit inductive noise coupling. Surface-mount capacitors are recommended (X7R ceramic for the 0.1F and 1F capacitors, and low ESR tantalum for the 4.7F capacitors). with analog and digital pins separated basically down the center of the package. (Note that AGND is on the opposite side.) However, there must be a low impedance connection between the analog and digital grounds at a common return point. The dc common-mode input, VCOMIN (pin 22), can be connected to analog ground or a dc voltage (such as the reference or common voltage output of an audio ADC). When biasing this input to a dc voltage, keep in mind that both the analog output and input pins will be level-shifted by the value of the bias voltage. The PGA2505 can be placed on a split ground plane, 1 2 3 4 To Relay Drivers and Switches 5 6 7 AGND VIN+ GPO1 VIN- GPO2 VCOMIN GPO3 CS11 GPO4 OVR CS12 DGND CS21 CS22 8 9 To/From MPU, MCU, DSP, or Logic 10 11 VA- SDI CS 24 23 22 21 1mF 20 19 0W 0.1mF 1mF 18 17 0.1mF 4.7mF + PGA2505 SCLK SDO VAVA+ 16 0.1mF 4.7mF + 0.1mF 4.7mF + 12 VDVA+ 0.1mF 13 4.7mF + VA- VOUT+ VOUT- 15 14 10W VA- Figure 13. Basic Circuit Configuration for the PGA2505 12 Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): PGA2505 PGA2505 www.ti.com ......................................................................................................................................................... SBOS396B - MARCH 2009 - REVISED JUNE 2009 INPUT CIRCUIT CONSIDERATIONS The blocking capacitors, along with the PGA2505 input resistance, form a high-pass filter circuit. With the typical input resistance of the PGA2505 specified in the Electrical Characteristics table, the value of the capacitor can be chosen to meet the desired low frequency response for the end application. At the same time, the value should be no greater than required, because larger capacitors store more charge and increase the surge current seen at the preamplifier when a short circuit occurs on the microphone input connector. For proper operation, the input circuit for the PGA2505 must include several items that are common to most microphone preamplifiers. Figure 14 shows a typical input circuit configuration. Other functions, such as input attenuation (pads), filters, and polarity reversal switches are commonly found in preamplifier circuits, but are not shown here in order to focus on the basic input circuit requirements. The microphone input is typically taken from a balanced XLR or TRS input connection (XLR shown). Three 1000pF capacitors provide simple EMI filtering for the circuit. Additional filtering for low- or high-frequency noise may be added, depending on the end application environment. A bridging resistor is shown and may be selected to provide the desired overall input impedance required for a given microphone. This resistance is in parallel with the phantom power bias resistors and the PGA2505 input resistance to set the actual impedance seen by the microphone. To protect the PGA2505 from large surge currents, power Schottky diodes are placed on the input pins to both the VA+ and VA- power supplies. Schottky diodes are used because of the lower turn-on voltage compared to standard rectifier diodes. Power devices are required because the surge currents from a large valued blocking capacitor (47F) can exceed 4.5A for a very short duration of time. It is recommended that the Schottky diode chosen for this application be specified for at least a 10A surge current. The use of a series current-limiting resistor before the protection diodes aids in handling surge currents, although the resistor adds noise to the circuit. Select a current-liming resistor value that is as high as tolerable for the desired noise performance of the preamplifier circuit. Connections for +48V phantom power, required for condenser microphones, are shown in Figure 14. The phantom power requires an On/Off switch, because dynamic microphones do not require phantom power and may be damaged if power is applied. DC-blocking capacitors are required between the phantom power connections and the PGA2505 inputs. The blocking capacitors are selected to have a high working voltage rating, with 50V being the minimum and 63V recommended for long-term reliability. 10mF - 47mF 63WV + (3) VIN+ (2) Mic Input 1 1000pF (4) 6.81kW 0.25W (4) VA- VA+ 1000pF 2 3 (1) 1000pF 6.81kW 0.25W Phantom Power Switch 10mF - 47mF 63WV + (3) (4) (4) VIN- (2) +48V (1) Bridging resistor; used to set the impedance seen by the microphone. (2) NOTES: value is selected based upon the desired low frequency response. The blocking capacitor (3) Current-limiting resistor. Select the highest value tolerable based upon input noise requirements. (4) Schottky diode; selected for fast turn-on and rated for a minimum of a 10A surge current. Recommended device is the MBRA120LT3 from ON Semiconductor. Figure 14. Typical Input Circuit for the PGA2505 13 Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): PGA2505 PGA2505 SBOS396B - MARCH 2009 - REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com OPERATION WITH VCOMIN = +2.5V As a suggested alternative, the PGA2505 analog outputs may be ac-coupled to the ADC inputs, allowing the PGA2505 to operate with VCOMIN = 0V in order to achieve best performance. The ac-coupling capacitors affect the overall low-frequency response of the preamplifier and converter combination, and the user is advised to choose a value that best suits the application requirements. When interfacing the analog outputs of the PGA2505 with audio ADC inputs, the converter may frequently have a common-mode dc output pin. This pin may be connected to the VCOMIN pin of the PGA2505 in order to facilitate a dc-coupled interface between the two devices. The common-mode dc voltage level is typically +2.5V, although some converters may have a slightly lower value, usually between +2.1V and +2.5V. There are several issues that must be considered when operating the PGA2505 in this fashion. Figure 15 illustrates a typical PGA2505 to audio ADC interface using ac-coupling. In addition to the coupling capacitors, a passive RC filter is required as an antialiasing filter for the converter. The vast majority of audio ADCs are of the oversampling delta-sigma variety, with a simple single-pole filter meeting the anti-aliasing requirements for this type of converter. Providing at least 6dB of attenuation also allows the PGA2505 to operate near full signal swing without overdriving the ADC inputs. Both the analog input and output pins of the PGA2505 are level-shifted by the VCOMIN voltage. The analog outputs are shifted to the VCOMIN level, while the analog inputs are shifted to approximately VCOMIN - 0.65V, as a result of the offset that normally exists on the input pins. The level-shifting limits the input and output swing of the PGA2505, reducing the overall signal-to-noise ratio and degrading the THD+N performance. Figure 16 illustrates an application where the VCOMIN pin of the PGA2505 is connected to the common-mode dc output of the audio ADC, with a dc-coupled interface between the PGA2505 analog outputs and the ADC analog inputs. Given VCOMIN = +2.5V and gains of 0dB through 60dB, the output swing is limited to less than one-half that specified in the Electrical Characteristics table. The output hard-clips at approximately a diode drop below the VA+ supply rail and a diode drop above analog ground. To ensure optimal performance, an output buffer to the PGA2505 is recommended. Figure 17 illustrates the use of an OPA1632 as the buffer. Additionally, the feedback circuitry functions as the antialiasing filter shown in Figure 15 and Figure 16. Having a differential buffer with attenuation of 6dB or greater also allows for the PGA2505 to maximize the output signal swing, while ensuring that the input swing does not exceed the full-scale input range of the ADC. An OPA227 is used to drive the output common-mode of the OPA1632. Given VCOMIN = +2.5V and a gain of 0dB, the practical maximum input or output voltage swing is approximately 1.0VRMS differential. Increasing the signal level much beyond this point results in a substantial increase in distortion. Plots of THD+N vs Frequency are shown in the Typical Characteristics section of this data sheet for both VCOMIN = 0V and +2.5V. The performance difference can be seen when comparing the plots. The user must consider whether the difference is acceptable for the end application. Coupling Capacitors PGA2505 VOUT+ CC1 + A/D Converter R 2R PGA + VOUT- VCOMIN (1) CC2 (1) C Serial Data Output PCM or DSD ADC R Attenuation and Antialiasing Filter Recommended devices are the PCM1804, PCM4202, PCM4204, PCM4220, or PCM4222. Figure 15. PGA2505 Analog Output to ADC Analog Input Interface, AC-Coupled 14 Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): PGA2505 PGA2505 www.ti.com ......................................................................................................................................................... SBOS396B - MARCH 2009 - REVISED JUNE 2009 A/D Converter PGA2505 VOUT+ R C PGA VOUT- VCOMIN (1) Serial Data Output PCM or DSD ADC R VCOM Output Antialiasing Filter 0.1mF (1) Recommended devices are the PCM1804, PCM4202, PCM4204, PCM4220, or PCM4222. Figure 16. PGA2505 Analog Output to ADC Analog Input Interface, DC-Coupled +5V 470W 1nF 16 1kW 15 24 3 8 7 40.2W 5 VIN+ + PGA2505 23 22 14 1kW 17 1 2 6 A/D Converter VIN- V 2.7nF OPA1632 4 (1) COM 40.2W 1nF 470W 2 -5V 6 OPA227 1kW 3 0.1mF (1) Recommended devices are the PCM1804, PCM4202, PCM4204, PCM4220, or PCM4222. Figure 17. PGA2505 Using OPA1632 as an Output Buffer REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (May, 2009) to Revision B ..................................................................................................... Page * Changed logo on document .................................................................................................................................................. 1 15 Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): PGA2505 PACKAGE OPTION ADDENDUM www.ti.com 9-Jun-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty PGA2505IDB ACTIVE SSOP DB 24 PGA2505IDBR ACTIVE SSOP DB 24 60 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 9-Jun-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device PGA2505IDBR Package Package Pins Type Drawing SSOP DB 24 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.2 8.8 2.5 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 9-Jun-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PGA2505IDBR SSOP DB 24 2000 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0-8 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. 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