MC74HC4040A 12-Stage Binary Ripple Counter High-Performance Silicon-Gate CMOS The MC74C4040A is identical in pinout to the standard CMOS MC14040. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of 12 master-slave flip-flops. The output of each flip-flop feeds the next and the frequency at each output is half of that of the preceding one. The state counter advances on the negative-going edge of the Clock input. Reset is asynchronous and active-high. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4040A for some designs. * * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance With JEDEC Standard No. 7A Requirements Chip Complexity: 398 FETs or 99.5 Equivalent Gates http://onsemi.com MARKING DIAGRAMS 16 PDIP-16 N SUFFIX CASE 648 16 1 1 16 SO-16 D SUFFIX CASE 751B 16 7 6 5 Clock 3 10 2 4 13 12 14 15 1 Reset VCC 16 11 Q10 Q8 Q9 15 14 13 12 HC40 40A ALYW TSSOP-16 DT SUFFIX CASE 948F 16 1 1 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week FUNCTION TABLE Q2 Q3 Clock Reset Output State X L L H No Charge Advance to Next State All Outputs Are Low Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 ORDERING INFORMATION Q12 Reset Clock 11 1 16 Q1 Device Pin 16 = VCC Pin 8 = GND Q11 HC4040A AWLYWW 1 LOGIC DIAGRAM 9 MC74HC4040AN AWLYYWW 10 Q1 9 Package Shipping MC74HC4040AN PDIP-16 2000 / Box MC74HC4040AD SOIC-16 48 / Rail MC74HC4040ADR2 SOIC-16 2500 / Reel MC74HC4040ADT TSSOP-16 96 / Rail MC74HC4040ADTR2 TSSOP-16 2500 / Reel Pinout: 16-Lead Plastic Package (Top View) 1 2 3 4 5 6 7 8 Q12 Q6 Q5 Q7 Q4 Q3 Q2 GND Semiconductor Components Industries, LLC, 2001 September, 2001 - Rev. 4 1 Publication Order Number: MC74HC4040A/D MC74HC4040A IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIII IIIII III IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III MAXIMUM RATINGS* Symbol VCC Parameter DC Supply Voltage (Referenced to GND) Value Unit - 0.5 to + 7.0 V Vin DC Input Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V Vout DC Output Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V DC Input Current, per Pin 20 mA Iout DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 50 mA PD Power Dissipation in Still Air, 750 500 450 mW Tstg Storage Temperature Range - 65 to + 150 C Iin TL Plastic DIP SOIC Package TSSOP Package This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. C Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package 260 *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: - 7 mW/C from 65 to 125C TSSOP Package: - 6.1 mW/C from 65 to 125C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III III II IIII IIIIIIIIIIIIIII IIIII III RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) Min Max Unit 2.0 6.0 V DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature Range, All Package Types tr, tf Input Rise and Fall Time (Figure 1) 0 VCC V - 55 + 125 C 0 0 0 0 1000 600 500 400 ns VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V DC CHARACTERISTICS (Voltages Referenced to GND) VCC V Guaranteed Limit -55 to 25C 85C 125C Unit VIH Minimum High-Level Input Voltage Vout = 0.1V or VCC -0.1V |Iout| 20A 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 V VIL Maximum Low-Level Input Voltage Vout = 0.1V or VCC - 0.1V |Iout| 20A 2.0 3.0 4.5 6.0 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 V Minimum High-Level Output Voltage Vin = VIH or VIL |Iout| 20A 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 Symbol VOH Parameter Condition |Iout| 2.4mA |Iout| 4.0mA |Iout| 5.2mA Vin =VIH or VIL VOL Maximum Low-Level Output Voltage Vin = VIH or VIL |Iout| 20A http://onsemi.com 2 V MC74HC4040A DC CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Condition |Iout| 2.4mA |Iout| 4.0mA |Iout| 5.2mA Vin = VIH or VIL Iin ICC Guaranteed Limit VCC V -55 to 25C 85C 125C 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 Unit Maximum Input Leakage Current Vin = VCC or GND 6.0 0.1 1.0 1.0 A Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0A 6.0 4 40 160 A NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Symbol Parameter Guaranteed Limit VCC V -55 to 25C 85C 125C Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) 2.0 3.0 4.5 6.0 10 15 30 50 9.0 14 28 45 8.0 12 25 40 MHz tPLH, tPHL Maximum Propagation Delay, Clock to Q1* (Figures 1 and 4) 2.0 3.0 4.5 6.0 96 63 31 25 106 71 36 30 115 88 40 35 ns tPHL Maximum Propagation Delay, Reset to Any Q (Figures 2 and 4) 2.0 3.0 4.5 6.0 45 30 30 26 52 36 35 32 65 40 40 35 ns tPLH, tPHL Maximum Propagation Delay, Qn to Qn+1 (Figures 3 and 4) 2.0 3.0 4.5 6.0 69 40 17 14 80 45 21 15 90 50 28 22 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 4) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 15 110 36 22 19 ns 10 10 10 pF Cin Maximum Input Capacitance NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). * For TA = 25C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations: VCC = 2.0 V: tP = [93.7 + 59.3 (n-1)] ns VCC = 4.5 V: tP = [30.25 + 14.6 (n-1)] ns VCC = 3.0 V: tP = [61.5 + 34.4 (n-1)] ns VCC = 6.0V: tP = [24.4 + 12 (n-1)] ns Typical @ 25C, VCC = 5.0 V 31 pF 2 * Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC . For load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). CPD Power Dissipation Capacitance (Per Package)* http://onsemi.com 3 MC74HC4040A TIMING REQUIREMENTS (Input tr = tf = 6 ns) Guaranteed Limit VCC V -55 to 25C 85C 125C Unit Minimum Recovery Time, Reset Inactive to Clock (Figure 2) 2.0 3.0 4.5 6.0 30 20 5 4 40 25 8 6 50 30 12 9 ns tw Minimum Pulse Width, Clock (Figure 1) 2.0 3.0 4.5 6.0 70 40 15 13 80 45 19 16 90 50 24 20 ns tw Minimum Pulse Width, Reset (Figure 2) 2.0 3.0 4.5 6.0 70 40 15 13 80 45 19 16 90 50 24 20 ns 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns Symbol trec tr, tf Parameter Maximum Input Rise and Fall Times (Figure 1) 2.0 3.0 4.5 6.0 NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). PIN DESCRIPTIONS INPUTS OUTPUTS Q1 thru Q12 (Pins 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1) Clock (Pin 10) Active-high outputs. Each Qn output divides the Clock input frequency by 2N. Negative-edge triggering clock input. A high-to-low transition on this input advances the state of the counter. Reset (Pin 11) Active-high reset. A high level applied to this input asynchronously resets the counter to its zero state, thus forcing all Q outputs low. SWITCHING WAVEFORMS tf tr 90% 50% 10% Clock tw tPLH Q1 50% Clock VCC trec tw GND 1/fMAX Reset tPHL 90% 50% 10% 50% tPHL tTLH Any Q tTHL Figure 1. 50% Figure 2. http://onsemi.com 4 VCC GND VCC GND MC74HC4040A SWITCHING WAVEFORMS (continued) TEST POINT Qn VCC 50% tPLH Qn+1 OUTPUT DEVICE UNDER TEST GND tPHL CL* 50% *Includes all probe and jig capacitance Figure 3. Figure 4. Test Circuit Q1 Q2 9 Clock 10 Q10 6 Q11 14 Q12 15 1 C Q C Q C Q C Q C Q C C Q C Q C Q C Q C Q C R Reset Q3 7 R 11 Q4 = Pin 5 Q5 = Pin 3 Q6 = Pin 2 Q7 = Pin 4 Q8 = Pin 13 Q9 = Pin 12 Figure 5. Expanded Logic Diagram http://onsemi.com 5 VCC = Pin 16 GND = Pin 8 Q MC74HC4040A 1 Clock 2 4 8 16 32 64 128 256 512 1024 2048 4096 Reset Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Figure 6. Timing Diagram APPLICATIONS INFORMATION Time-Base Generator waveform and feeds the HC4040A. Selecting outputs Q5, Q10, Q11, and Q12 causes a reset every 3600 clocks. The HC20 decodes the counter outputs, produces a single (narrow) output pulse, and resets the binary counter. The resulting output frequency is 1.0 pulse/minute. A 60Hz sinewave obtained through a 100 K resistor connected to a 120 Vac power line through a step down transformer is applied to the input of the MC54/74HC14A, Schmitt-trigger inverter. The HC14A squares-up the input VCC 1.0M 120Vac 60Hz HC4040A Clock 20pF Q5 Q10 Q11 Q12 NOTE: 13 12 10 9 Ground MUST be isolated by a transformer or opto-isolator for safety reasons. Figure 7. Time-Base Generator http://onsemi.com 6 1/2 HC20 8 1 2 4 5 1/2 HC20 6 1.0 Pulse/Minute Output MC74HC4040A PACKAGE DIMENSIONS PDIP-16 N SUFFIX CASE 648-08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. -A- 16 9 1 8 B F C DIM A B C D F G H J K L M S L S -T- SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M T A M INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01 SOIC-16 D SUFFIX CASE 751B-05 ISSUE J -A- 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 -B- 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 C -T- SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 7 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 MC74HC4040A PACKAGE DIMENSIONS TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S K EEE CCC CCC EEE K1 2X L/2 16 9 J1 B -U- L SECTION N-N J PIN 1 IDENT. 8 1 N 0.15 (0.006) T U S 0.25 (0.010) A -V- M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. N F DETAIL E -W- C 0.10 (0.004) -T- SEATING PLANE DETAIL E H D DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 G ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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