International Rectifier HEXFET Power MOSFET @ Surface Mount Available in Tape & Reel Dynamic dv/dt Rating Repetitive Avalanche Rated Fast Switching Ease of Paralleling Simple Drive Requirements Description Third Generation HEXFETs from International Rectifier provide the designer with the best combination of fast switching, ruggedized device design, low PD-9.1012 IRF830S on-resistance and cost-effectiveness. The SMD-220 is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on-resistance in any existing surface mount package. The SMD-220 is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. Absolute Maximum Ratings SMD-220 Parameter Max. Units Ip @ Tc = 25C Continuous Drain Current, Ves @ 10 V 45 Ip @ Tc = 100C | Continuous Drain Current, Ves @ 10 V 29 A Ibm Pulsed Drain Current 18 Pp @ Tc=25C_ | Power Dissipation 74 W Pp @ Ta=25C_ | Power Dissipation (PCB Mount)** 3.1 Linear Derating Factor 0.59 wee Linear Derating Factor (PCB Mount)** 0.025 Ves Gate-to-Source Voltage +20 Vv Eas Single Pulse Avalanche Energy @ 280 mJ lar Avalanche Current 45 A Ear Repetitive Avalanche Energy 7.4 mJ dv/dt Peak Diode Recovery dv/dt_ @ 3.5 Vins Tu, Tst6 Junction and Storage Temperature Range ~55 to +150 C Soldering Temperature, for 10 seconds 300 (1.6mm from case) Thermal Resistance Parameter Min. Typ. Max. Units Resc Junction-to-Case _ _ 17 Resa Junction-to-Ambient (PCB mount)** 40 C/W Rea Junction-to-Ambient = _ 62 ** When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994.IRF830S Electrical Characteristics @ Ty = 25C (unless otherwise specified) Parameter Min. | Typ. | Max. | Units Test Conditions Vierypss Drain-to-Source Breakdown Voltage 500 V_ | Vas=0V, Ip= 250A AV erypss/ATy| Breakdown Voltage Temp. Coefficient | 0.61 | | VAC | Reference to 25C, lb= 1mA Rosvon) Static Drain-to-Source On-Resistance = - 1.5 Q | Vas=10V, Ip=2.7A Vasith) Gate Threshold Voltage 2.0 ~ 4.0 V_ | Vps=Ves, Ip= 250A Gis Forward Transconductance 2.5 = _ S| Vps=50V, Ip=2.7A Ipss Drain-to-Source Leakage Current 28 HA Vos=500V, Vase OV = ~ | 250 Vos=400V, Ves=0V, Ty=125C loss Gate-to-Source Forward Leakage _ _ 100 nA Vaes=20V Gate-to-Source Reverse Leakage ~ | -100 Ves=-20V Qg Total Gate Charge _ = 38 Ip=3.1A Qgs Gate-to-Source Charge 5.0 | nC |Vps=400V Qgu Gate-to-Drain ("Miller") Charge _ _ 22 Ves=10V See Fig. 6 and 13 ta(on) Turn-On Delay Time = 8.2 _ Vpo=250V tr Rise Time _ 16 _ ns Ip=3.1A tarot) Turn-Off Delay Time 42 Re=12Q tr Fall Time _ 16 _ Rp=79Q See Figure 10 Lo Internal Drain Inductance _ 4.5 _ amo ead } b nH | from package (ee Ls Internal Source Inductance | 75] and center of die contact s Ciss Input Capacitance _ 610 _ Ves=0V Coss Output Capacitance | 160 | PF | Vps= 25V Crsg Reverse Transfer Capacitance _ 68 _ f=1.0MHz See Figure 5 Source-Drain Ratings and Characteristics Parameter Min. | Typ. | Max. | Units Test Conditions Is Continuous Source Current _ _ 45 MOSFET symbol a (Body Diode) . A showing the ism Pulsed Source Current _ _ 18 integral reverse 6 (Body Diode) p-n junction diode. s Vsp Diode Forward Voltage _ _ 1.6 Vs | Ty=25C, Is=4.5A, Ves=0V ter Reverse Recovery Time | 320 | 640 | ns_ | Ty=25C, Ir=3.1A Qn Reverse Recovery Charge _- 1.0 | 2.0 uG |di/dt=100A/us ton Forward Turn-On Time Intrinsic turn-on time is neglegible (turn-on is dominated by Ls+Lp) h Notes: , ! @ Repetitive rating; pulse width limited by Isps4.5A, di/dt<75A/us, VoD<V(BR}Dss, max. junction temperature (See Figure 11) Tys150C Vpo=50V, starting Ti=25C, L=24mH @ Pulse width < 300 ss; duty cycle <2%. Re=25Q, las=4.5A (See Figure 12)IRF830S [p, Drain Current (Amps) Ip, Drain Current (Amps) 20us PULSE WIDTH 20us PULSE WIDTH To = 25C Te = 150C Vps, Drain-to-Source Voltage (volts) Vps, Drain-to-Source Voltage (volts) Fig 1. Typical Output Characteristics, Fig 2. Typical Output Characteristics, Tco=25C Tco=150C 104 ro co} (Normalized) in Ip, Drain Current (Amps) 3 1 Vpg = SOV Rpscon), Drain-to-Source On Resistance 20us PULSE WIDTH 0 Veg = 10 4 40 =60 -40 - 0 20 40 00 120 140 4 Ves, Gate-to-Source Voltage (volts) Ty, Junction Temperature (C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. TemperatureIRF830S Capacitance (pF) Isp, Reverse Drain Current (Amps) 1500 1250 500 104 Vos, Drain-to-Source Voltage (volts) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage 3 Veg = OV 0.4 0. : 1.0 Vsp, Source-to-Drain Voltage (volts) Fig 7. Typical Source-Drain Diode Forward Voltage 1.2 Vas, Gate-to-Source Voltage (volts) 'p, Drain Current (Amps) 20 on rv re FOR TEST CIACUIT SEE FIGURE 13 0 8 16 24 32 AO Qe, Total Gate Charge (nC) Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 108 5 OPERATION IN THIS AREA LIMITED Y Fos (ON) @ 10 5 2 4 5 2 0.4 5 T cy 2 Ty=150C 0? SINGLE PUL 0.1? 5 4 2? 5 40 2 5 104 Vos, Drain-to-Source Voltage (volts) 5 40225 5 4932 Fig 8. Maximum Safe Operating AreaIp, Drain Current (Amps) "25 50 Tc, Case Temperature (C) Fig 9. Maximum Drain Current Vs. IRF830S Rp Vos D.U.T. K =" Vpp \biov Pulse Width < 1ps Duty Factor < 0.1% iL Fig 10a. Switching Time Test Circuit Vps 90% 10% 75 100 125 150 Ves tafon) tr tayo) Fig 10b. Switching Time Waveforms Case Temperature Thermal Response (Zajc) Fig 11. 10 rut | (THERMAL RESPONSE) biel NOTES: 1. DUTY FACTOR, D=t1/t2 2. PEAK 1y=Pom x Zthjc + Te SINGLE PULSE 105 10-4 10? 10-2 0.4 4 40} t;, Rectangular Pulse Duration (seconds) Maximum Effective Transient Thermal Impedance, Junction-to-CaseIRF830S Vary tp to obtain Vps > required las 500 Ip TOP 2.0A 2.84 =~ 500 TTOM 4,54 s E > fez 400 Do c ud . . Te @ 300 Fig 12a. Unclamped Inductive Test Circuit 3 ao oO D> 200 a g 100 Lu Vos 25 50 75 100 125 150 Starting Ty, Junction Temperature(C) lag wee Fig 12c. Maximum Avalanche Energy Fig 12b. Unclamped Inductive Waveforms Vs. Drain Current Current Regulator vio Se WO ete | + Aes ++- Aap y Ves Vo ama oL Charge > lg = b Current Sampling Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit i Appendix A: Figure 14, Peak Diode Recovery dv/dt Test Circuit Appendix B: Package Outline Mechanical Drawing Appendix C: Part Marking Information . International Appendix D: Tape & Reel information Rectifier