seh ar Inbal Corooraicn sabIn Gecember 1973 Intel shipped the first 8-bit, N-channe! microprocessor, the 8080. Since then it has became the most widely used microprocessor in the industry. Applications of the S080 span from large, intelligent systems terminals to decompression computers for deep sea divers. This 8080 Microcomputer Systems User's Manual presents all of the 8080 system components. Over twenty-five devices are described in detail. These new devices further enhance the 8680 system: 8080A 8-Bit Central Processor Unit Functionally and Eiectrically Compatible with the 8080. TTL Drive Capability. Enhanced Timing. 8224 Clock Generator for 8080A. Single 16 Pin (DIP) Package. Auxiliary Timing Functions. Power-On Reset. 8228 System Controller for BOBGA. Single 28 Pin (DIP) Package. Single interrupt Vector (RST 7). Multi-Byte Interrupt instruction Capability (e.g. CALL. Direct Data and Control Bus Connect to all BOBO System I/O and Memory Components. 8251 Programmable Communication Interface. ASYNC or SYNC (including IBM bi-SYNC1. Single 28 Pin Package. Single +5 Volt Power Supply. 8255 Programmable Peripheral Interface. Three 8-Bit Ports. Rit Set/Reset Capability. interrupt Generation. Single 40 Pin Package. Singie +5 Volt Power Supply. In addition, new memory components include: 8708, 8K Erasable PROM; 8316A, High Density Mask ROM; and $101, Low Power CMOS RAM. intel Microcomputers. First from the beginning.INTROOUCTION General ee ee Advantages of Designing with Microcomputers . . Microcomputer Design Aids Application Example Application Table CHAPTER 1 THE FUNCTIONS OF &4 COMPUTER A Typical Computer System The Architecture of a CPU Computer Operations CHAPTER 2 THE 8080 CENTRAL PROCESSING UNIT General The Processor Cycle Interrupt Sequences Hoid Sequences Halt Sequences 2.0... 2. ee eee Start-up of the 8080 CPU CHAPTER 3 INTERFACING THE 8080 Genera 20 ee ee Basic System Operatian CPU Module Design 2... ee ee Intertacing the 8080 ta Memory and 1/0 Devices CONTENTS iii iii 1-1 1-1 1-3 2-1 22 2-3 2-11 2-12 2-43 2:13 3-1 31 3-2 CHAPTER 4. INSTRUCTION SET General... ee ee Data Transier Group Arithmetic Group Branch Group... 2... ee ees Stack, 1/0 and Machine Controi Group Summary Table CHAPTER 5 8080 MICROCOMPUTER SYSTEM COMPONENTS CPU Group 8224 Ciock Generator Functional Description and System Applications Data Sheet... 0.0... 0. eee ee 8228 System Controller Functional Description and System Appiications Data Sheet 2... 0... eee 80804, Central Processor Data Sheet .. 2... eee B080A-t Central Processor 41.345) Data Sheet... eee et 8080A-2 Central Precessor 41.5ps} Data Sheet... 12. ee eee es M8080A, Central Processor (-55 to +125C} Data Sheet Intel Corporation eeurmes ao responaioility for the wag at any circuitry other than circuitry embodied in an inte Product, No other Crrcun gatent canta are imoiiea,ROMs 87024 Erasable PROM (256 x @} OataSheet..2 2s... 8708/8704 Erasable PROM (1K x 8} Data Sheet. 2.0... 20...0........,,, 8302 Mask ROM (256 x 8) Data Sheet... 8308 Mask ROM (1K x 8} Data Sheet... 82964, Mask ROM (2K x 8} DataSheet 2.0... 2... RAMs 8101-2 Static RAM (256 x 4) DataSheet 6... ....0.0........,,,. 9111-2 Static RAM (256 x 4) Data Sheet... ll, 8102-2 Static RAM (1K x 1) DataSheet.....2 2. ll, 81024-4 Static RAM (1K x 1) DataSheet......20.0.....,......... 810784 Dynamic RAM (4K x 1) DataSheet..........,....,........, 5101 Static CMOS RAM (256 x 4) DataSheet..............,.00......, 8210 Dynamic RAM Driver Data Sheet 8222 Dynamic RAM Refresh Controller New Product Announcement VO 8212 &-Bit 1/0 Port Functional Deseription....2....~00,.... System Appticatians of the 8212 Data Sheet 8255 Programmable Perioherai Interface Basic Functional Description ............ Detaited Operational Description System Applications of the 8255 DataSheet. 2.1... lee, 8251 Programmable Communication intertace Basic Functional Description :......~..... Detailed Operational Description System Applications of the 8257 Data Sheet Peripherals 8205 One of 8 Decoder Functional Description... 2... .020 0. System Applications of the 8205 DataSheet. 2.0.2... el le, $214 Priority Interrupt Controi Unit Interrupts in Microcomputer Systems ..... Functional Description. .... 20... 8216/8226 4-Bit Bi-Directional Bus Driver Functional Description. .......,-...... System Applications of the 8216/8226 ..... DataSheet.........0.............. Coming Soon CHAPTER 6 PACKAGING INFORMATION. ..........,...Since their inception, digital computers have contin- uously become more efficient, expanding into new appli- cations with each major technological improvement. The advant of minicomputers enabled the inclusion of digital computers as a permanent part of various process control systems, Unfortunately, the size and cost of minicomputers in dedicated applications has limited their use. Another approach has been the use of custom built systems made up of random iogic (i.., logic gates, flip-flaps, counters, etc.). However, the huge expense and development time involved in the design and debugging of these systems has restricted their use to large volume applications where the devetop- ment costs could be spread over a jarge number of machines. Today, Intel offers the systems designer a new alter- native ...the microcomputer. Utilizing the technologies and experience gained in becorning the worlds largest supplier of LSI memory components, Intel has made the power of the digital computer available at the integrated circuit level. Using the n-channel silicon gate MOS process, Inte! engi- neers have implemented the fast {2 us. cycle) and powerful (72 basic instructions) 8080 microprocessor on 2 single LS! chip. When this processor is combined with memory and (40 circuits, the computer is complete. intel offers a variety of random-access memory (RAM), read-only memory (ROM} and shift register circuits, that combine with the 8080 pro- cessor to form the MCS-80 microcomputer system, a system that can directly address and retrieve as many as 65,536 bytes stored in the memory devices. The 8080 processor is packaged in a 40-pin cual in-line package (DIP) that allows for remarkably easy interfacing. The 8080 has a 16-bit address bus, a 8-bit bidirectional data bus and fully decoded, TTL-compatible controt outputs. In additian to supporting up to 64K bytes of mixed RAM and ROM memory, the 8080 can address up to 256 input ports and 256 output ports: thus allowing for virtually unlimited system expansion. The 8080 instruction set includes can- ditional oranching, decima! as wetl as binary arithmetic, logical, register-to-register, stack cantrol and memory refer- ence instructions. In fact, the 8080 instruction set is power- ful enough to rival the perfarmance of many of the much higher priced minicomputers, yet the 8080 is upward soft- ware compatible with Intel's earlier 4008 microprocessor {i.e., programs written for the 8008 can be assembled and executed on the 8090). In addition to an extensive instruction set oriented to problem solving, the 8080 has another significant feature SPEED. tn contrast to random logic designs which tend te work in parallel, the microcomputer warks by sequentially executing its program. As a result of this sequential execu- tion, the number of tasks a microcomputer can undertake in a given period of time is directly proportional to the execution speed of the microcomputer. The speed of exe- cution is the limiting factor of the realm of applications of the micrecomputer. The 8080, with instruction times as short as 2 ysec., is an order of magnitude faster than earlier generations of microcomputers, and therefore has an ex- panded field of potential applications. The architecture of the 8680 also shows a significant improvement over earlier microcomputer designs. The 8080 contains a t6-bit stack pointer that controls the addressing of an axternal stack located in memory, The pointer can be initialized via the proper instructions such that any pertion of external memory can be used a5 a last in/first out stack; thus enabling almost unlimited subroutine nesting. The stack pointer allows the contents of the program counter, the ac- cumulater, the condition flags or any of the data registers to be stored in or retrieved from the external stack. In addi- tien, multi-level interrupt processing is possible using the 8080s stack contro} instructions. The status of the pro- cessor can be pushed onto the stack when an interrupt is accepted, then popped off the stack after the interrupt has been serviced, This ability to save the contents of the pro- cessor's registers is possible ever if an interrupt service routine, itself, is interrupted.CONVENTIONAL SYSTEM | PROGRAMMED LOGIC Product definition System and logic design Debug Lab Instrumentation PC card tayout Documentation Cooling and packaging Power distribution Engineering changes Done with conventionai Done with yellow wire Done with togic diagrams Simplified because of ease of Incorporating features Can be programmed with design aids fcompulers, assemblers, eciitors| Software and hardware aids reduce time Fewer cards to layout Less hardware to document Reduced system size and power cansumption eases [ob Less power to distribute Change program Table G-1, The Advantages of Using Microprocessors ADVANTAGES OF DESIGNING WITH MICROCOMPUTERS Microcomputers simplify almost every phase of pro- duct development. The first Step, a8 in any oroduct devei- opment program, is to identify the various functions chat the end system 15 expected ta perform, Instead of realizing these functions with networks of gates and flip-flops, the functions are implemented by encoding suitable sequences of instructions (programs) in the memory elements. Data and certain types of Programs are stored in RAM, while the basic program can be stored in ROM. The Microprocessar performs ail of the system's functions by fetching the in- structions in memary, executing them and communicating the resuits via the microcomputers I/O parts. An 8080 Microprocessor, executing the programmed logic stored in a single 2048-byte ROM element, can perform the same logical functions that might have Previously required up to 1006 logic gates, The benefits of designing a microcomputer inta your system go far beyond the advantages of merely simplifying product development. You will also appreciate the profit- making advantages of using 4 microcomputer in place of custom-designed randam logic. The most apparent advantage is the significant savings in hardware casts, 4 microcomputer chip set repiaces dozens of random logic elements, thus re- ducing the cost as well as the size of your system. In addi- tien, production costs drop as the number of individual components to be handled decreases, and the number of complex printed circuit boards (which are difficult to lay- out, test and correct} is greatly reduced. Probably the most Profitable advantage of a microcomputer is its flexibility for change. To modify your system, you merely re-program the memory elements; you don't have ta redesign the entire system. You can imagine the savings in time and money when you want to upgrade your product. Reliability is another reason to choose the micrecemouter over randam logic. As the number of components decreases, the prob- abitity of a malfunctioning elament likewise decreases. All of the logical contrat functions formerly performed by aumerous hardware components can new be implemented in a few ROM circuits which are non-volatile: that is, tha contents of ROM will never be jost, even in the event of a power failure. Tabla 0-1 summarizes many of the advan- tages of using microcomputers, MICROCOMPUTER DESIGN AIDS if you're used to fogic design and the idea of designing with programmed logic seems like too radical a change, re- gardiess of advantages, there's na need to worry because Intel has already done most of the groundwork for you. The INTELLEC 8 Development Systems provide flexible, in- expensive and simpiified methods for OEM product develop. ment. The INTELLEC 8& provides RAM program storage making pragram loading and modification easier, a display and control console for system monitoring and debugging, a standard TTY interface, a PROM programming capability and a standard software package (System Monitor, Assam- bler and Test Editor}. In addition te the standard software package available with the INTELLEC? 3, Intei ofters a PL/M compiler, a cross-assembler and a simulator written in FORTRAN 1 and designed to run on any large scale cam: puter. These programs may be oracured directly from Intel or from a number of nationwide computer time-sharing services. Intel's Micracomputer Systems Group is always available to provide assistance in every pase of your product development. Intel aiso provides complete documentation on all their hardware and software products. In addition to this User's Manual, there are the: . PL/M Language Reference Manual * 8080 Assembly Language Programming Manual + INTELLEC8/MOD 80 Operator's Manual INTELLEC8/MOD 80 Hardware Reference Manual s 8080 User's Program LibraryAPPLICATIONS EXAMPLE The 8080 can be used as the basis for a wide variety of calcwiation and control systems. The system configura- tions for particular applications will differ in the nature of the peripheral devices used and in the amount and the type of memory required. The applications and solutions de- scribed in this section are presented primarily to show how microcomputers can be used to solve design problems. The BOBO should not be considered limited either in scope or performance to those applications listed here. Consider an 8080 microcomputer used within an auto- matic computing scale for a supermarket. The hasic machine has two input devices: the weighing unit and a keyooard, used for function selection and to enter the price per unit of waight. The only output device is a display showing the total price, although a ticket printer might be added as an optional output device. The control unit must accept weight information from the weighing unit, function and data inputs fram the key- board, and generate the display. The only arithmetic func- tion to be performed is a simple multiplication of weight times rate. The control unit could probably be realized with standard TTL logic. State diagrams for the various portions could oe drawn and a multiplier unit dasigned. The whole design could then be tied together, and eventually reduced to a selection of packages and a printed circuit hoard layout. In effact, when designing with a logic family such as TTL, the designs are customized by the choice of packages and the wiring of the logic. if, however, an 8080 microcomputer is used to realize the control unit (as shown in Figure 0-1), the only custom logic will be that of the interface circuits. These circuits are usually quite simple, providing electrical buffering for the input and output signals. instead of drawing state diagrams leading to logic, the system designer now prepares a flow chart, indicating which input signals must be read, what processing and computa tions are needed, and what output signals must be produced. A program is written from the flow chart, The program is then assembled into bit pattarns which are loaded into the program memory, Thus, this system is customized primarily by the contents of program memory. For this automatic scale, the program would probably reside in read-only memory (ROM), since the micrecom- puter would always execute the same program, the one which implements the scale functions. The processor would constantly monitor the keyboard and weighing unit, and up- date the display whenever necessary. The unit would require very little data memory; it would only be needed for rate storage, intermediate results, and for storing a copy of the display. When the contro! portion of a product is implemented with a microcomputer chip set, functions can be changed and features added merely by altering tha program in mem- ory. With a TTL based system, however, alterations may re- quire extensive rewiring, alteration of PC boards, etc. The number of applications for microcomputers is limited only by the depth of the designers imagination. We have listed a few potential applications in Table 0-2, along with the types of peripheral devices usually associated with each product. KEVEOARD PRINTER | oo o00 | 90 DISPLAY oaa WEIGHING cog, 2? UNIT + oO i aoo | oa F = { | ro--<---- ~ | INPUT INFUT OUTPUT OTT I INTERRACE =1 INTERFACE =2 INTERFACE =1 INTERFACE <2 | . r sey - 7 1 v4] nodD | | i, { if | cP 2 s J 4 BUS CONTROL 14) UNIT : t PROGAAM OATA MEMORY MEMORY FROM) RAMI Figura 0-1. Microcomputer Application Automatic ScalaAPPLICATION PERIPHERAL DEVICES ENCOUNTERED Intelligent Tarminals Cathode Ray Tube Display Printing Units Synchronous and Asynchronous gata lines Cassette Tape Unit Keyboards Gaming Machines Keyboards, pushbuttons and switches Various display davices Cain acceptors Cain dispensers Cash Registers Keyboard or |nout Switch Array Change Dispenser Digital Display Ticket Printer Magnetic Card reader Communication interface Accounting and Billing Machines Keyboard Printer Unit Cassette or other magnetic tape unit Floppy disks Telephone Switching Control Telephone Line Scanner Analog Switching Network Dial Registers Class of Service Parcel Numerically Controlled Machines Magnetic or Paper Tape Reacer Stepper Motors Optical Shaft Encoders Process Control Analogto-Digital Converters Digital-to-Analog Converters Control Switches Displays Table 0-2. Microprocessor ApplicationsThis chapter introduces certain basic computer con- cepts. It provides background information and definitions which will be useful in later chapters of this manual. Those already farniliar with computers may skip this material, at their option. A TYPICAL COMPUTER SYSTEM A typical digital computer consists of: a) A central processor unit (CPU) b) A memory c} Input/output {1/0} ports The memory serves as a place to store Instructions, the coded pieces of information that direct the activities af the CPU, and Data, the coded pieces of information that are processed by the CPU. A group of logically related instruc- tions stored in memory is referred to as 4 Program. The CPU reads" aach instruction from memory in a logically deter- mined sequence, and uses it to initiate processing actions. If the program sequence is coherent and logical, processing the program will produce intelligible and useful results. The memory is also used ta store the data ta be manip- ulated, as well as the instructions that direct that manipu- lation, The program must ba organized such that the CPU does not read a non-instruction word when it expects to see an instruction. The CPU can rapidly access any data stored in memory; but often the memory is not large enough toa store the entire data bank required for a particular appli- cation, The problem can be resolved by providing the com- puter with one or more input Ports. The CPU can address these ports and input the data contained there. The addition of input ports enables the computer ta receive information from external equipment {such as a paper tape reader or floppy disk} at high rates of speed and in large volumes, A comouter also requires one or more Output Ports that permit the CPU to communicate the result of its pro- cessing to the outside world, The output may go to a dis- play, for use by a human operator, to a peripheral device that produces hard-copy, such as a line-printer, to a peripheral storage device, such as a floppy disk unit, or the OUTpUt may constitute process control signals that direct the operations of anather system, such as an automated assembly line. Like input ports, Output ports are addressable. The input and output ports together permit the processor to communicate with the outside worid. The CPU unifies the system. It controls the functions performed by the other components. The CPU must be able to fetch instructions from memory, decode their binary contents and execute them. Ht must also be able to reference memory and (/O ports as necessary in the execution of in- structions, in addition, the CPU should be able to recagnize and respond to certain external control signals, such as INTERRUPT and WAIT requests. The functional units within a CPU that enable it to perform these functions are described below, THE ARCHITECTURE OF A CPU A typical central processor unit (CPU} consists of the following interconnected functional units: Registers Arithmetic/Logic Unit (ALU) Control Circuitry Alegisters are temporary storage units within the CPU, Some registers, such as the program counter and instructian register, have dedicated uses, Other registers, such as the ac- cumulator, are for more general purpose use. Accumulator: The accumulator usually stores one of the operands to be manipulated by the ALU. A typical instructian might direct the ALU to add the contents of same ather register to the contents of the accumulator and store the result in the accumulator itself. In general, the accumulator is both a source (operand) and a destination (result} register. Often a CPU will include a number of adiditional general purpose registers that can be used to store operands or intermediate cata. The availability of general ourposeregisters eliminates the need to shuttle intermediate re- sults back and forth between memory and the accumulator, thus imaroving processing speed and efficiency. Program Counter (Jumps, Subroutines and the Stack): The instructions that make up a program are stored in the system's memory. The central processor references the contents of memory, in order ta determine what action 's appropriate, This means that the processor must know which location contains the next instruction. Each of the locations in memory 1s numbered, to dis- tinguish it from ail other locations in memory, The qumber which identifies a memory location is called its Addrass. The processor maintains a counter which contains the address of the next program instruction. This register is calied the Program Counter. The processor updates the pro- gram caunter by adding "1" to the counter each time it fetches an instruction, so that the program counter is always current (pointing to the next instructions, The programmer therefore stores his instructions in numerically adjacent addresses, so that the lower addresses contain the first instructions to be executed and the higher addresses contain later instructions. The only time the pro- grammer may violate this sequential rule is when an ingtruc- tion in one section of memory is a Jump instruction to another section of memory. 4 jump instruction contains the address of the instruc: tian which is ta follow it. The next instruction may be stored in any memory location, as tong as the programmect jump specifies the correct address. During the execution of ajump instruction, ihe processor replaces the contents of its program counter with the address embodied in the Jump. Thus, the logical cantinuity of the Program is maintained, A special kind of program jump occurs when the stored program Calls a subroutine. In this kind of jug, the pro- cessor is required to remember the contents of the pro- gram counter at the time that the jurnp accurs. This enables the processor ta resume execution of the main program when its finished with the last instruction of the subroutine, 4 Subroutine is a program within a program. Usually it is 4 general-purpose set of instructions that must be exe- cuted repeatedly in the course of a main program, Routines which calculate the square, the sine, or the logarithm of a program variable ars good examples of functions often written as subroutines, Other examples might be programs designed for inputting or outputting data to a particular peripheral device. The processor has a special way of handling sub routines, if order to insure an orderly return to the main Program, When the processor receives a Call instruction, it increments the Program Counter and stores the counter's contents in a reserved memory area known as the Stack. The Stack thus saves the address of the instruction to be executed after the subroutine is completed. Then the pro- cessor loads the address specified in the Cali inte its Pro- gram Counter. The next instruction fetched will therefare be the first step of the subroutine. The last instruction in any subroutine isa Return. Such an instruction need specify mo address. When the processor fetches a Return instruction, it simply replaces the current contents of the Program Counter with the address on the top af the stack, This causes the processor to resume execu- tion of the calling program at the point immediately follaw- ing the original Catl Instruction, Subroutines are often Nested: that is, one subroutine will sometimes call a second subreutine. The second may call a third, and so on. This is perfectly acceptable, as long as the processor has enough capacity to store the necessary return addresses, and the togical provision for doing so. In other words, the maximum depth of nesting is determined by the depth of the stack itself. If the stack has space for storing three return addresses, then three leveis of subrou- tines may be accommodated, Processors have different ways of maintaining stacks, Some have facilities for the storage of return addresses built into the processor itself. Other processors use a reserved area of externa! memory as the stack and simply maintain a Pointer register which contains the address of the most recent stack entry. The external stack allows virtually un- limited subroutine nesting. [n addition, if the processer pro- vides instructions that cause the contents of the accumulator and other general purpose registers to be pushed onto the stack or popped off the stack via the address stored in the stack pointer, muiti-lavel interrupt processing (described later in this chapter} is possible, The status of the processor {i.@., the contents of all the registers} can be saved in the stack when an interrupt is accepted and then restored after the interrupt has been serviced. This ability to save the pro- cessor's status at any given time is possible even if an inter- rUpt service routing, itself, is interrupted, Instruction Register and Decoder: Every computer has a Word Length that is characteris- tic of that machine. A computer's word length is usuaily determined by the size of its internal storage elements and interconnecting paths treferred to as Busses}; for example, a computer whose registers and busses can store and trans- fer 8 bits of information has a characteristic word length af @bits and is referred to as an 8-bit parallel processor, An eight-bit parallel processor generally finds it most efficient to deal with eight-bit binary fields, and the memory asso- ciated with such a processor is therefore organized to store eight bits in each addressable memory location. Data and instructions are stared in memory as eight-bit binary num- bers, or as numbers that are integral multiples of eight bits: 16 bits, 24 bits, and so on, This characteristic eight-bit field is often referred to as a Byte. Each operation that the processor can perform is identified by a unique byte of data known as an InstructionCode or Operation Code, 4n eight-bit word used a5 an in. struction code can distinguish between 256 alternative actions, more than adequate for mast processors. The processor fetches an instruction in tve distinct operations. First, the processor transmits the aadress in its Program Caunter to the memory, Then the memory returns the addressed byte to the processor. The CPU stares this instruction byte in a register known as the Instruction Register and uses it to direct activities during the remainder of the instruction execution. The mechanism by which the pracessor translates an instruction code inta specific processing actions requires more elaboration than we can here afford. The concept, however, should be intuitively clear to any logic designer. The eight bits stored in the instruction register can be de- coded and used to selectively activate ane of a number of output tines, in this case up to 256 tines. Each line repre- sents a set of activities associated with execution of a par- ticular instruction code, The enabied line can be combined with selected timing pulses, to develop electrical signals that can then be used to initiate specific actions, This transla- tion of code into action is performed hy the Instruction Decoder and by the associated control circuitry. An eight-bit instruction code is often sufficient to specify a particular processing action. There are times, haw- ever, when execution of the instruction requires more infor. mation than eight bits can convey, One example of this is when the instruction refer- ences a memory location. The basic instruction code iden- tifies the operation to be perfarmed, but cannot specify the object address as well, In a case like this, a two- or three. byte instruction must be used, Successive instruction bytes are stored in sequentially adjacent memory locatians, and the processor pertarms two or three fetches in succession ta obtain the full instruction, The first byte retrieved from memory is placed in the processers instruction register, and subsequent bytes are placed in temporary storage; the pro- cessor then proceeds with the execution phase. Such an instruction is referred to as Variable Length. Address Register(s): A CPU may use a register or register-pair to hold the address of a memory location that is to be accessed for data. |f the address register is Programmable, {i.., if there are instructions that allow the programmer to alter the contents of the register) the program can build an ad- dress in the address register prior to executing a Memory Reference instruction {i.., an instruction that reads data from memory, writes data to memory or operates on data stored in memory). Arithmetic/Logic Unit (ALU): All processors contain an arithmetic/logic unit, which is often referred to simply as the ALU, The ALU, as its name implies, is that portion of the CPU hardware which performs the arithmetic and logical operations on the binary data. The ALU must contain an Adder which is capable of combining the contents of two registers in accordance with the logic af binary arsthmetic. This pravision permits the processor to perform arithmetic manipulations on the data itabtains from memery and fram its other inputs. Using only the basic adder a capable programmer can write routines which will subtract, multiply and divide, giv- ing the machine complete arithmetic capabilities. In practice, however, most ALUs provide other built-in funetions, in- cluding hardware subtraction, boolean logic operations, and shift capabilities. The ALU contains Flag Bits which specify certain conditions that arise in the course of arithmetic and logical manipulations, Flags typically include Carry, Zero, Sign, and Parity. it is possible to program jumps which are condi- tionally dependent on the status of one or more flags. Thus, for example, the program may be designed to jump to a special routine if the carry bit is set following an addition instruction. Control Circuitry: The control circuitry is the primary functional unit within a CPU, Using clock inputs, the cantrel circuitry maintains the proper sequence of events required for any processing task. After an instruction is fetched and decoded, the control circuitry issues the appropriate signals (to units bath internal and external to the CPU) for initiating the proper processing action, Often the control circuitry will be capable of responding to external signals, such as an inter: rupt or wait request. An Interrupt request will cause the central circuitry to temporarily interrupt main program execution, jump to a special routine to service the interrupt- ing device, then automatically feturn to the main program. & Wait request is often issued by a memory or 1/O element that operates slower than the CPU. The control circuitry willidle the CPU until the memory or (/O port is ready with the data. COMPUTER OPERATIONS There are certain operations that are basic to almost any computer. A sound understanding of these basic opera- tions is a necessary prerequisite ta examining the specific aperatians of a particular computer. Timing: The activities of the central processor are cyclical. The Pracessor fetches an instructian, performs the operations required, fetches the next instruction, and sa on, This orderly sequence of events requires precise timing, and the CPU therefore requires a free running oscillator clock which furnishes the reference for all processer actions. The com- bined fetch and execution of a single instruction is referred to as an Instruction Cycle. The portion of a cycle identifiedwith a clearly defined activity is called a State, And the inter- yal between pulses of the timing oscillator is referred to asa Clock Period, 4s a generat rute, one or more clock periods are necessary for the completion of a state, and there are several states in a cycle. Instruction Fetch: The first stateis) of any instruction cycle will be dedicated to fetching the next instruction. The CPU issues a read signal and the contents of the Progtam counter are sent to memory, which responds by returning the next instruc: tion word, The first byte of the instruction is placed in the instruction register, If the instruction consists of mare than one byte, additionai states are required to fetch each byte of the instruction. When the entire instruction is present in the CPU, the program counter is incremented (in prepara- tion for the next instruction fetch) and the instruction is decoded. The operation specified in the instruction will be executed in the remaining states of the instruction cycle, The instruction may call for a memory read or write, an input of output and/or an internal CPU operation, such as a register: to-register transfer or an add-registers operation, Memory Read: An instruction fetch is merely a special memory read operation that brings the instruction to the CPU's instruc: tion register. The instruction fetched may then call for data to be read from memory into the CPU, The CPU again issues aread signal and sends the proper memory address: memory responds by returning the requested word, The data re- ceived is tiaced in the accumulator or one of the other gen- eral Purpose registers (not the instruction register), Memory Write: A memory write operation is similar to a read except for the direction of data flow. The CPU issues a write signal, sends the proper memory address, then sends the data word to be written mto the addressed memory location, Wait (memory synchronization): As previously stated, the activities of the Processor are timed by a master clock oscillator. The clock periad determines the timing of ail processing activity. The speed of the processing cycle, however, is limited by the memorys Access Time, Once the processor has sent a read address to memory, it cannot proceed until the memory has had time to respond. Mast memories are capable of respanding much faster than the processing cycle requires. A few, however, cannot supply the addressed byte within the minimum time established by the processor's clock. Therefore @ processor should contain a synchroniza- lian provision, which permits the memory to request a Wait stata, When the memory receives a read or write enable sig- nal, it places a request signal on the processor's READY line, causing the CPU ta idle temporarily. After the memary has had time to respond, it frees the processor's READY line, and the instruction cycle proceeds. Input/Output: Input and Output operations are similar to memory read and write operations with the exception that a peri- pheral 1/O device is addressed instead of a memory location, The CPU issues the appropriate input or output control signal, sends the proper device address and either receives the data being input or sends the data to be output. Data can be input/output in either parallel or serial form, All data within a digital computer is represented in binary coded form. A binary data word consists of a group of bits; each bit is either a one or a zero. Parallel 1/0 con- sists of transferring ail bits in the word at the same time, one bit per line, Serial 1/O consists of transferring one bit at @ time on @ single fine. Naturally serial [/Q is much slower, but it requires considerably less hardware than does parallel 1/0, Interrupts: Interrupt provisions are included on many central processors, 38 a means of improving the processor's effi- ciency. Consider the case of a computer that is processing 4 large volume of data, portions of which are to be output to a printer. The CPU can output a byte of data within a single machine cycle but it may take the printer the equiva- lent of many machine cycles to actually print the character specified by the data byte. The CPU could then remain idie waiting until the printer can accept the next data byte, |f an interrupt capability is implemented on the computer, the CPU can output 4 data byte then return to data processing. When-the printer is ready to accept the next data byte, it can request an interrupt. When the CPU acknowledges the interrupt, it suspends main program execution and avto- matically branches to a routine that will output the next data byte. After the byte is output, the CPU continues with main program execution. Note that this is, in principle, quite similar to a subroutine call, except that the jump is initiated externally rather than by the program. More complex interrupt structures are possible, in which several interrupting devices share the same processor but have different priority leveis, Interruptive Processing 1s an important feature that enables maximum untilization of a processor's capacity for high system throughput. Hold: Another important feature that improves the through- put of a processor is the Hold, The hold provision enables Direct Mamory Access (DMA) operations. In ordinary input and output operations, the processor itself supervises the entire data transfer. Information to be placed in memory is transferred from the input device to the processor, and then from the processor to the designated memory jacation, In similar fashion, information that goesfrom memory to output devices goes by way of the processor. Some peripheral devices, however, are capable of transferring infarmation to and from memory much faster than the processor itself can accomplish the transfer. If any appreciable quantity of data must be transferred to ar fram such a device, then system throughput will be increased by having the devica accomplish the transfer directly. The pro- cessor must temporarily suspend its operation during such a transfer, to prevent conflicts that would arise if processor and peripheral device atternpted to access memory simul- taneously. It is for this reason that a hold provision is in- cluded on som processors.The 8080 is a complete 8-bit parallel, central processor unit (CPU) for use in ganeral ourpose digital computer sys- tems, it is fabricated on a single LSI chip (see Figure 31}. using Intel's n-channeai silicon gate MOS process. The 8080 transfers data and internal state information via an 8-bit, bidirectional 3- state Data Bus (Dg-D7}. Memory and peri- pheral device addresses ara transmitted over a separate 16- bit 3-state Address Bus (Ag-A15). Six timing and controt outputs (SYNC, DBIN, WAIT, WR, HLGA and INTE} eman- ate from the 8080, while four control inputs (READY, HOLO, INT and RESET}, four power inputs (+12, +5v, Sv, and GND) and two clock inputs i7 and @3) are ac- cepted by the 8080. Ayn 40 Poet Ay, GNO O-4 2 3a 0 A Dy, oe] a 3B FeO Ata D, Owe 4 37 eo 4,2 Dy Oe] 5 36 [0 Ans D, Owe 6 35 feo Ag D, Ow] 7 34 -eo A, D, OFF 6 INTEL #;-*: Dp, Om a2 -0 Ay Dy Gee] 19 BOBO aL oa 5Y Gee 11 30 -\eo Ay RESET G-w{ 12 23 f*o 4, HOLD Qeq 13 2B eo Hie INT Cand ta 27 bo 4; 2 Oe] 15 26 -eo Ay INTE O=4 16 25 P=0 Ay DBIN O-t 17 24 eo WAIT wa Oe] 19 23 peo AeaDy SYNC G=] 15 neo es av oO] 20 2 Oo HLDA Figure 2-1. $090 Photomicrograph With Pin Designations 2-1ARCHITECTURE OF THE 8080 CPU The 8080 CPU consists of the following functional units: Register array and address logic * Arithmetic and logic unit (ALU) * Instruction register and control section * Bi-directional, 3-state data bus buffer Figure 2-2 illustrates the functional blocks within the BO80 CPU, Registers: The register section consists of a static RAM array Organized into six 16-bit regrsters: * Program counter (PC) Stack pointer {SP} * Six 8-bit general purpose registers arranged in pairs, referred to as B,C: DE: and HL A temporary register pair called WZ The program counter maintains tha memory address of the current program instruction and is incremented auto- matically during every instruction fetch. The stack pointer maintains the address of the next available stack location in memory. The stack pointer can be initialized to use any portion of read-write memory as a stack. The stack pointer is decremented when data is pushed onto the stack and incremented when data is popped off the stack {i.e., the stack grows downward. The six general purpose registers can be used either as single registers (8-bit) ar as ragister pairs (16-bit), The temporary register pair, WZ, is not Program addressable and is oniy used for the internal execution of instructions, Eight-bit data bytes can be transferred between the internal bus and the register array via the register-selact multiplexer. Sixteen-bit transfers can proceed between the tegister array and the address latch or the incrementer/ decrementer circuit. The address atch receives data from any of the three register pairs and drives the 16 address output buffers (Ag-Ay6}, as weil as the incrementer/ decrementer circuit. The incrementer/decrementer circuit receives data fram the address latch and sends it ta the register array. The 16-bit data can be incremented or decremented or simply transferred between registers, BI-DIRECTIONAL DATA BUS 18 BIT] (eat INTERNAL DATA BUS INTERNAL DATA BUS x= __t it ab ACCUMULATOR TEM AEG. INSTRUCTION s HEGISTER 1a) MULTIPLEXER We ir z [tl | F FLAG [Bt TEMP AEG, TEMP REG. i FLIR-ELOPS i ee B un Cc TT} LATCH a i| Ez 2 REG. REG. | INSTALICTION Z Da = DECODER REG, AEG. AND ~ w He a) REGISTER MACHINE & REG. AEG. ARRAY 5 ENCODING a tie! | = STACK POINTER ~. 1] PROGRAM COUNTER DECIMAL INCREMENTEA/OECAEMENTER ADIUST ADDRESS LATCH til a TIMING AND CONTROL POWER | e +12 AODAESS BUFFER ial WRITE CONTROL CONTROL CONTROL CONTROL SYNC CLOCKS! oy wo TE TET TTT A WR BRIN INTE INT HOLD HOLD WalT AC K READ SYNC 1 2) AESET ~ Aig ay ADOCRESS alls Figure 2-2. 8080 cpy Functional Block Diagrarn 2-2Arithmetic and Logic Unit (ALU): The ALU contains the following registers: An 86-bit accumulator e An 8-bit temporary accumulator {ACT} e A 5S-bit flag register: zero, carry, sign, parity and auxiliary carry An&-bit temporary register {TMP} Arithmetic, logical and rotate operations are per- formed in the ALU, The ALU is fed by the temporary register [TMP} and the temporary accumulator {ACT} and carry flip-flop. The result of the operation can be trans- ferred to the internal bus or to the accumulator; the ALU also feeds the flag register. The temporary register {TMP] receives information from the internal bus and can send ail or portians of it to the ALU, the flag register and the internal bus. The accumulator (ACC} can be loaded from the ALU and the internal bus and can transfer data to the temporary accumulator (ACT) and the internal bus. The contents of the accumulator {ACC} and the auxiliary carry flip-flop can be tested for decimal correction during the execution of the DAA instruction (see Chapter 4). instruction Register and Control: During an instruction fetch, the first byte of an in- struction (containing the OP code} is transferred fram the internal bus to the &-bit instruction register, The contents of the instruction register are, in turn, available to the onstructian decoder, The output of the decoder, combined with various timing signals, provides the contral signals for the register array, ALU and gata buffer blocks. In addition, the outputs from the instruction decoder and external control signals feed the timing and state contro! section which generates the state and cycle timing signais. Data Bus Buffer: This S-bit bidirectional 3-state buffer is used to isolate the CPU's internal bus from the external data bus (Dg through D7). In the output mode, the internal bus content is loaded into an &-bit latch that, in turn, drives the data bus output buffers. The output buffers are switched off during input or non-transfer operations. During the input made, data from the external data bus is transferred to the interna! bus. The internal bus is pre- charged at the beginning of each internal state, except for the transter state {7 3described later in this chapter}, 23 THE PROCESSOR CYCLE An instruction cycle is defined as the time required to fetch and execute an instruction. During the fetch, a selected instruction {ane, two or three bytes) is extracted fram memory and deposited in the CPU's instruction regis- ter. During the execution phase, the instruction is decoded and translated into specific processing activities. Every instruction cycle consists of one, two, three, four or five machine cycles. A machine cycle is required each time the CPU accesses memory or an I/O port. The fatch portion of an instruction cycle requires one machine eycte for each byte to be fetched. The duration of the execu tion portion of the instruction cycle depends on the kind of instruction that has been fetched. Some instructions do not require any machine cycles other than those necessary 1o fetch the instruction; other instructions, however, re- quir additional machine cycles to write or read data to/ fram memory or 1/0 devices. The DAD instruction is an exception in that it requires two additional machine cycles to complete an internal register-pair add (see Chapter 4}. Each machine cycle consists of three, four or five states, A state is the smallest unit of processing activity and is defined as the interval between two successive positive- going transitions af the $7 driven clack pulse. The 8080 isdriven by a two-phase clock oscillator, Ail processing activ- ities are referred to the period of this clock. The two non- overlapping clock pulses, jabeled 1 and $9, are furnished by external circuitry, It is the 7 clock pulse which divides each machine cycle into states. Timing logic within the 8080 uses the clack inputs to produce a SYNC pulse, which identifies the beginning of every machine cycle. The SYNC guise is triggered by the low-ta-high transition of 49, as shown in Figure 2-3. ! FIRST STATE OF : *EVERY MACHINE : CYCLE | Of SYNC S/ {| \ SYNC DOES NOT OCCUR IN THE SECOND AND THIRD MACHINE CYCLES OF 4 DAO INSTRUCTION SINCE THESE M&CHINE CYCLES SAE USED FOR 4N INTERNAL REGISTER-PAIR ADD. 2 Figure 2-3.04,9 4nd SYNC Timing There are three exceptions to the defined duration of @ state. They are the WAIT state, the hold (HLDA) state and the halt {HLTA} state, described later in this chapter. Because the WAIT, the HLDA, and the HLTA states depend upon external events, they are by their nature of indeter- minate length. Even these exceptional states, however, mustbe synchronized with the pulses of the driving clock, Thus, the duration of ail states are integral multiplies of the clock period. To summarize then, each clock period marks a state: three ta five states canstitute a machine cycle; and ane to five machine cycles comprise an instruction cycle. A full instruction cycle requires anywhere from four to eight- teen states for its completion, depending on the kind of in- struction involved. Machine Cycle Identification: With the exception of the OAD instruction, there is just one consideration that determines haw many machine cycles are required in any given instruction cycle: the num- ber of times that the processor must reference g memory address or an addressable peripheral device, in order to fetch and execute the instruction. Like many processors, the 8086 is so constructed that it can transmit only ane address per machine cycle. Thus, if the fetch and execution of an instruction requires two memory references, then the instruction cycle associated with that instruction consists of two machine cycles. If five such references are called for, then the instruction cycle contains five machine cycles, Every instruction cycle has at least one reference to memory, during which the instruction is fetched. An in- struction cycle must always have a fetch, even if the execu- tien of the instruction requires mo further references to memory. The first machine cycle in every instruction cycle is therefore # FETCH. Beyond that, there are no fast rules, It depends on the kind of insteuctian that is fetched. Consider some examples. The add-register (ADD r} instruction is an instruction that requires only a single machine cycle (FETCH) for its campietion. in this one-byte instruction, the contents of one of the CPU's six general Purpose registers is added to the existing contents of the accumulator. Since all the information necessary to execute the command is contained in the eight bits of the instruction coda, only one memory reference is necessary. Three states are used to extract the instruction from memery, and one additional state is used to accomplish the dasirect addition. The entire instruction cycle thus requires only one machine eycla that consists of four states, or four periods of the ex- ternal clock. Suppose now, however, that we wish to add the con- tents of a specific memory location to the existing contents of the accumulator (ADD M}. Although this is quite similar in principle to the example just cited, several additional steps witl be used. An extra machine cycle will be used, in order to address the desired memory location. The actual sequence is as follows. First the processor extracts fram memory the one-byte instruction word ad. dressed by its Program counter. This takes three states. The eight-bit instruction word obtained during the FETCH machine cycle is deposited in the CPUs instruction register and used to direct activities during the remainder of the instruction cycle. Next, the processor sends out, as an address, 2-4 the contents of its H and L registers. The eight-bit data word returned during this MEMORY READ machine cycie is placed in a temporary registar inside the BOBO CPU, By now three more clack periods {states} have elapsed, In the seventh and final state, the contents of the temporary regis- ter are added to thase of the accumulator. Two machine cycles, consisting of seven states in ait, complete the ADD M instruction cycle, At the opposite extreme is the save H and L registars (SHLD) instruction, which requires five machine cycles. During an SHLD instruction cycle, the contents of the processors H and L registers are deposited in two sequen- tially adjacent memory locations: the destination is indi- cated by two address bytes which are stored in the two memory locations immediately tollowing the operation code byte. The following sequence of events occurs: {1} A FETCH machine cycle, consisting of four states. During the first three states of this machine cycie, the processor fetches the instruc: tion indicated by its program counter, The pro- gram counter is then incremented. The fourth state is used for internal instruction decoding. A MEMORY READ machine cycle, consisting of three states, During this machine cyele, the byte indicated by the program counter is read from memory and placed in the Processors Z register. The program counter is incremented again. {2} {3} Another MEMORY READ machine cycle, con- sisting of three states, in which the byte indica. ted by the processor's program counter is read from memory and placed in the W register. The program counter is incremented, in anticipation of the next instruction fetch. A MEMORY WRITE machine eycie, of three states, in which the contents of the L register are transferred to the memory location pointed to by the present contents of the W and Z regis- ters. The state following the transfer is used to increment the WZ register pair so that it indi- cates the next memory location to receive data, A MEMORY WRITE machine cycle, of three states, in which the contents of the H register are transferred to the new memory location pointed to by the W,Z register pair, (4) (5) In summary, the SHLD instruction cycle contains five machine cycles and takes 16 states to execute. Most instructions fall somewhere between the ex. tremes typified by the ADD r and the SHLO instruc- tions. The input (INP) and the output (OUT) instructions, for example, require three machine cycles: a FETCH, to obtain the instruction; a MEMORY READ, to obtain the address of the object peripheral: and an iNPUT or an OUT- PUT machine cycle, to complete the transfer.While no one instruction cycle wiil consist of more then five machine cycles, the folowing ten different types ot machine cycles may occur within an instruction cycie: (1) FETCH (M1; (2) MEMORY READ (3) MEMORY WRITE (4) STACK READ (5) STACK WAITE (6) INPUT {7} GUTPUT {8) INTERRUPT (9) HALT {10} HALT INTERRUPT The machine cycles that actually do occur in a par- ticular instruction cycle depend upon the kind of instruc- tion, with the overriding stipulation that the first machine cycle in any instruction cycle is always a FETCH, The processor identifies the machine cycle in prog- ress by transmitting an eight-bit status word during the first state of every machine cycle. Updated status information is presented on the 8080's data tines (Dq-D7l, during the SYNC interval. This data should be saved in latehes, and used to develop control signals for external circuitry. Table 2-1 shows how the positive-true status information is dis- tributed on the processor's data bus, Status signals are provided principally for the cantrol of external circuitry. Simplicity of interface, rather than machine cycle identification, dictates the logical definition of individual status bits. You will therefore observe that certain processor machine cycles are uniquely identified by a single status bit, but that others are not. The My status bit (Dg), for example, unambiguously identifies a FETCH machine cycle. 4 STACK READ, on the other hand, is indicated by the coinciaence of STACK and MEMR sig- nats, Machine cycle identification data is also valuable in the test and debugging phases of system development. Table 2-1 lists the status bit outputs for each type of machine cycle, State Transition Sequence: Every machine cycte within an instruction cycle con- sists of three to five active states (referred to as T4, T2, T3, T4, T5 or Fy). The actual number of states depends upon the instruction being executed, and on the particular ma- chine cycle within the greater instruction cycle. The state transition diagram in Figure 2-4 shows now the 8080 pro- ceeds from state to state in the course of a machine cycle. The diagram also shows how the READY, HOLD, and INTERRUPT lines are sampled during the machine cycle, and hew the conditions on these lines may modify the 25 basic transition sequence, In the present cdiscussian, we are concerned only with the basic sequence and with the AEADY function. The HOLD and INTERRUPT functians will be discussed later, The BOBD CPU does not directly indicate its internal state by transmitting a state control output during aach state: instead, the 8080 supplies direct control output (NTE, HLDA, DBIN, WR and WAIT) for use by external circuitry, Recall that the 8080 passes through at least three states in every machine cycie, with each state defined by successive low-to-high transitions of the @4 clock, Figure 2-5 shows the timing relationships in a typical FETCH machine cycle. Events that occur in each state are referenced to transitions of the 7 and o9 clock pulses. The SYNC signal identifies the first state (T4} in every machine cycle. As shown in Figure 2-5, the SYNC signal is related to the leading ecige of the $2 clock. There is a delay (toc) between the low-to-high transition of 69 and the pasitive-going edge of the SYNC pulse. There also is a corresponding delay {also toc} between the next 92 pulse and the falling edge of the SYNC signal, Status information is displayed on Op-D7 during the same 2 to 2 interval. Switching of the status signals is likewise controlled by $2. The rising edge of 62 during T1 also loads the pro cessors address lines (Ag-A15). These lines become stable within a brief delay (tp a) of the @9 clocking pulse, and they remain stabie until the first @g pulse after state 73. This gives the processor ample time to read the data re- turned from memory. Onee the processor has sent an address to memory, there is an opportunity for the memory to request a WAIT. This it does by pulling the processor's READY line low, prior to the Ready set-up interval itrs} which occurs during the @g pulse within state Tp or Ty. As long as the READY line remains low, the processor will idle, giving the memory time to respond to the addressed data request. Refer to Figure 2-5. The processor responds to a wait request by entering an alternative state (Ty? at the end of Tg, rather than pro- ceeding directly to the T3 state. Entry inte the Tyy state is indicated by a WAIT signal from the processor, acknowledg- ing the memorys request, A low-to-high transition on the WAIT line is triggered by the rising edge of the 47 clock and gcturs within a brief delay (toc of the actual entry inte the Ty state. A wait periad may be of indefinite duration. The pra- cessor remains in the waiting condition until its READY line again goes high. A READY indication must precede the falt- ing edge of the #2 clock hy a specified interval {tag}, in arder to guarantee an exit from the Ty state. The cycle may then proceed, beginning with the rising edge of the next 67 clock. A WAIT interval will therefore consist of an integral number of Ty states and will atways be a multiple of the clock period,Instructions for the 8080 require from one to five machine cycles for complete executian, The 8080 sends out bit of Status information on the data bus at the beginning of each machine cycle {during SYNC timel, The following table defines the status intormatian, STATUS INFORMATION DEFINITION Data Bus Symbots Bit Definition INTA Da = Acknowledge signat for INTERRUPT re. quest, Signal should be used to gate are- start instruction onto the data bus when OBIN is active, WO D, Indicates that the operation in the currant machine cycle will be a WRITE memory or OUTPUT function (WO = 0). Otherwise, a READ memory of INPUT operation will be executed. STACK Bs Indicates that the address bus hotds the pushdown stack address from the Stack Painter. HLTA Da Acknowledge signal for HALT instruction. OUT Dy Indicates that the address bus contains the address of an output device and the data bus will contain the output data when WR is active, My Ds, Provides a signal to indicate that the CPU is in the fetch cycle for the first byte of an instruction. INP* Dg Indicates that the address bus contains the address af an input device and the input data showid be placed on the data bus when DIN is active, MEMR~ By Designates that the data bus wil! be used for mamory read data. Thaw: three status ots can he used to control the How of data onto the BO8O data bus STATUS WORD CHART cLOcK GEN 5 ORMWER STATUS BOBO STATUS LATCH sTatus LATOR 1 By 4 iwta wo 4rack HLTA our MAT IMB MEMR PEIN WN 2 S*NC uyata & = a / & EN ss 3 gs < s/s / / = ONIOHCIIONIGIIGIICSIONONED) Do | INTA 0o/o;}/o};a;o;yo0}]n' 3 [5 1 Dy Wo 1 1 QO 1 0 1 0.1 } 1 D2| Stack | oO; olo[t]sflorpololo oO O03! HLTA o}lo/;/oj}o:iofofle!ot 1 Daf our olor ,olelaloliriafe lo Ds | My tio;ofojaflolotiala 1 | Ds} INP oi/eo/lo!lalojrfo-oy, so 0 Lor | meme [+ fifofailelolotel1 lo Table 2-1. 8080 Status Bit DetinitiansREADY HLTA ES NG Is INTERNAL BOLD FF SET? iNST EXECUTION COMPLETED INT + INTE YES SET INTERNAL edt SET INTERNAL HOLG Fie I Wal | HOLD ' MODE HOLO MODE HOLO HOLD RESET INTERNAL HOLD FF INT INTE SET INTERNAL HOLD f-F HOLD MODE HOLD HOLO RESET INTERNAL HOLD F F a RESET HLTA INT FF Figure 2-4. CPU State Transition Diagram 27 INTE E/F IS RESET IF INTERN SL INT FF 15 SET. WUNTEANAL INT FF 18 RESET If INTE F/F IS BESET. NSEE PAGE 2.12The events that take piace during the T3 state are determined by the kind of machine cycle in progress. [na FETCH machine cycle, the pracessor interprets the data on its data bus as an instruction. During a MEMORY READ or a STACK READ, data on this bus is interpreted as a data word, The processor outputs data on this bus during a MEMORY WRITE machine cycle. During I/O operations, the processor may either transmit or receive data, de- pending on whether an OUTPUT or an INPUT operation is involved. Figure 2-6 ilfustrates the timing that is characteristic of a data input operation, As shown, the low-to-high transi- tion of 92 during Ta clears status information from the pro- cessors data lines, preparing these lines ior the receipt at incoming data, The data presented to the processor must have stabilized prior to both the d1~data set-up interval {tyg7}, that precedes the falling edge of the Gy pulse detin- ing state Ty, and the d9~-data set-up interval! {tosal, that precedes the rising edge of 9 in state T3. This same data must remain stable during the data hold interval (t{OH} that occurs following the rising edge of the o pulse, Data placed on these jines by memory or by other external devices will be sampled during T2. During the input of data to the processor, the 8080 generates a DBIN signal which should be used externally to enabie the transfer. Machine cycles in which DBIN is avail- able include: FETCH, MEMORY READ, STACK READ, and {(NTERRUPT. DBIN is initiated by the rising edge of 9 during state T2 and terminated by the corresponding edge of $2 during Tg. Any Ty phases intervening between T3 and T3 will therefore extend DBIN by one or more clock periods. Figure 2-7 shows the timing af a machine cycle in which the processor outputs data. Output data may be des- tined either for memory or for peripherals. The rising edge of $9 within state T? clears status information from the CPUs data lines, and toads in the data which is to be output to external devices, This substitution takes place within the SYNC READY walt OBiN wa STATUS IM FQ MAT [Cry UNKNOWN TELGATING WRITE MODE READ MODE 4454 SAMPLE READY OPTIONAL MEMORY ADDRESS HOU0 AND HALT | : | HALT VOGEVICE NUMBER ' on Ora MEMOAY i STATUS INFORMATION . ACCESS TIME i Inta oT ADJUST MLTA wo | MEMA My | INP STACK | FETCH DATA OPTIONAL on instaucrion INS TRACT IO EXECUTION WRITE DATA IF HEQUIRED NOTE: (M) Refer to Status Word Chart on Page 2-6. Figure 2-5. Basic 8080 Instruction Cycle 28Mg r ! ty Ts FM Ta Ky Ta Fy PALL | 10 DEVICE NUMBER A 1 T? 3 ASP a2 =--4- Arse BYTE UNKNOWNS BYTE h INPUT DATA TO ONE TWO ACCUMULATOR wee eee r- : ro on | ee a ft PEGATING i tobe i on SYNC {fT | \ ___/ Le 4 : oem | NT READY } Walt . Wa 1 ' | , 1 1 sTaTus INFORMS TION NOTE: ay) Refer to Status Word Chart on Page 2-6. Figure 2-6. Input Instruction Cycle My % Ta ac) Tz "1 Ty 1" AL LAL. LS VS FLOATING: ~ : VO DEVICE : \ j BYTE NUMBER | a i ae i A [accumyiaror } STATUS INFORMATION NOTE. (Nj Reter to Status Word Chart an Page 2-6. Figure 2-7. Output Instruction Cycie 2-4data output delay interval (top) following the 9 clack's leading edge. Data on the bus remains stabie throughout the remainder of the machine cycle, until replaced by up- dated status information in the subsequent Ty state. Observe that a READY signal is necessary for completion of an OUTPUT machine eycle. Unless such an indication is pres- ent, the processor enters the Ty state, following the T2 state, Data on the output lines remains stable in the interim, and the processing cycle will nat proceed until the READY line again goes high. The 8080 CPU generates a WR output for the syn- chronizatian af external transfers, during these machine cycies in which the processor Outputs data. These include MEMORY WRITE, STACK WRITE, and QUTPUT, The negative-going leading edge of WR is referenced to the rising edge of the first $7 clock pulse following T3, and occurs within a brief delay ito) of that event, WR remains low until r-triggered by the leading edge of @, during the state following T3. Note that any Ty states intervening between Tz and T3 of the output machine cycle will neces- sarily extend WR, in much the same way that OBIN is af- fected during data input operations, Ali processor machine cycles consist of at least three states: T4, 7, and T3 as just described. [f the processor has to wait for a response from the peripheral or memory with which it is communicating, then the machine cycle may also contain one or more Tw states. Quring the three basic states, data is transferred to or from the Processor. After the T3 state, however, it becames difficult to generalize. Tq4 and Tg states are available, if the execution of a particular instruction requires them, But nat ail machine cycles make use of these states. It depends upan the kind of instruction being executed, and on the Particular machine cycle within the instruction cycle, The Processor will termi- nate any machine cycle as soon as its processing activities are completed, rather than proceeding through the Tg and Ts states every time. Thus the 8080 may exit a machine cycle following the T3, the Tq, or the Ts state and pro- ceed directly to the T1 state of the next machine cycle, STATE ASSOCIATED ACTIVITIES 4 A memory address or 1/Q device number is placed on the Address Bus (A45.0); status information is piaced on Data Bus iD7.9). T> The CPU samples the READY and HOLD in- puts and checks for halt instruction. Tw Processor enters wait state if READY is iow foptianal) or if HALT instruction has been executed, T3 An instruction byte (FETCH machine cycle}, data byte (MEMORY READ, STACK READ) Of interrupt instruction (INTER RUPT machine cycle} is input to the CPU from the Data Bus: ora data byte (MEMORY WRITE, STACK WRITE or OUTPUT machine cycle) is output onto the data bus, T4 States Tq and T5 ave available if the execu- TS tion of a particular instruction requires them: {optional} if not, the CPU may skip one or both of them, T4 and Ts are only used for internat Processor operations. Table 2-2. State Definitions 2-10INTERRUPT SEQUENCES The 8080 has the built-in capacity to handle external interrupt requests. A peripheral device can initiate an inter- rupt simply by driving the processars interrupt {INT} line high. The interrupt (INT} input fs asynchronous, and a raquest may therefore originate at any time during any instruction cycle, Internal lagic re-clocks the external re- Quest, $0 that a proper correspondence with the driving clock is established, As Figure 2-8 shows, an interrugt request (INT) arriving during the time that the interrupt enable jine {INTE} is high, acts in coincidence with the o9 clock to set the internal interrupt latch, This event takes place during the last state of the instruction cycle in which the request occurs, thus ensuring that any instructian +m progress is completed before the interrupt can be processed, The INTERRUPT machine cycle which follows the arrival of an enabled interrupt request resembles an ordinary FETCH machine cycle in most respects, The My status bit is transmitted as usual during the SYNC interval. It is accompanied, however, by an INTA status bit (Dg) which acknowledges the external request, The contents of the Program counter are latched onto the CPU's address lings during T4, but the counter itself is not incremented during the INTERRUPT machine cycle, as it otherwise would be. in this way, the pre-interrupt status of the program counter is preserved, sa that data in the counter may be restored by the interrupted program after the interrupt request has been processed. The interrupt cycle is otherwise indistingurshable fram an ordinary FETCH machine cycle, The processor itself takes no further special action, It is the responsibility of the peripheral logic to see that an eight-bit interrupt instruction is jammed onto the processor's data bus during state T3. In @ typical system, this means that the data-in bus from memory must be temporarily disconnected fram the pro- cessors main data bus, so that the interrupting device can command the main bus without interference. The 8080's instruction set provides a special ane-byte cail which facilitates the processing of interrupts (the ordi- nary program Call takes three bytes}. This is the RESTART instruction (AST). A variable three-bit field embedded in the eight-bit field of the AST enables the interrupting device to direct a Call to one of eight fixed memory locatians, The decimal addresses of these dedicated locations are: 0, 8, 16, 24, 32, 40, 48, and 56. Any of these addresses may be used ta store the first instructionis) of a routine cesigned to service the requirements af an interrupting device. Since the (RST! is a call, campletion of the instruction also stores the old program counter contents on the STACK. SYNC NBN WR RETURN #4, INTERN AL INTE INT FFF INTERNAL! INHIBIT STORE OF PC+1 INTERNAL STATUS INFORMATION oe NOTE: Reter to Status Word Chart on Page 2-6, Figure 2-8. Interrupt TimingAisa FLOATING bra oe HOLD REQUEST HOLD READY HOLD F/F INTERNAL HLOA : Ta AND Ty OPERATION CAN BE 111 SEE ATTACHED ELECTRICAL CHAAACTERISTICS. ! : DONE INTERNALLY. Figure 2-9. HOLD Operation (Read Mode} om FLOATING Dra Wr HOLD REQUEST HOLG READY HOLG FSF INTERNAL HLOa WRITE BATA . Figura 2-10. HOLD Operation (Write Moda}HOLD SEQUENCES The 80804 CPU cantains provisions for Direct Mem- ory Access (DMAI operations. By applying a HOLD to the appropriate contre! pin on the processor, an external device can cause the CPU to suspend its normal operations and re- linquish control of the address and data busses, The proces- sor responds to a request of this kind by flaating its address to other devices sharing the busses. At the same time, the processor acknowledges the HOLD by placing a high on its HLDA outpin gin, During an acknowledged HOLD, the address and data busses are under control of the peripheral which originated the request, enabling it to conduct mem- ory transfers without processor intervention. Like the interrupt, the HOLD input is synchronized internaily. A HOLD signal must be stable prior to the Hold set-up interval {ty}, that precedes the rising edge of dy. Figures 2-9 and 2-10 illustrate the timing involved in HOLG operations. Note the delay between the asynchronous HOLD REQUEST and the re-clacked HOLD. As shown in the diagram, a coincidence of the READY, the HOLD, and the @3 clocks sets the internal hold latch. Setting the tatch anables the subsequent rising edge of the 7 clock pulse to trigger the HLOA output, Acknowledgement of the HOLD REQUEST precedes slightly the actual floating of the processors address and data lines, The processor acknowledges a HOLD at the begin- ning of T3, f a read or an input machine cycle is in progress tsee Figure 2-3}. Otherwise, acknawledgement is deferred untit the beginning of the state fallowing T3 {see Figure 2-10}. In both cases, however, the HLDA goes high within a specified delay (toc) of the rising edge of the selected 44 clock pulse. Address and data lines are floated within a brief delay after the rising edge of the next o> clack pulse, This relationship is also shown in the diagrams. To all outward appearances, the processor has suspend: ed its operations once the address and data busses are floated. Internally, however, certain functions may continue, If a HOLD REQUEST is acknowledged at T3, and if the pro- cessor is in the middle of a machine cycle which requires four or more states to complete, the CPU proceeds through Tq and Ts before coming to a rest. Not until the end of the machine cycle is reached will processing activities cease. Internal processing is thus permitted to overlap the external OMA transfer, improving both the efficiency and the speed of the entire system. The processor exits the holding state through a sequence similar to that by which it entered. A HOLD REQUEST is terminated asynchronously when the external device has completed its data transfer. The HLDA output 213 returns to a low level following the jeading edge of the next @t clock pulse. Normal processing resumes with the ma- chine cycte faliowing the last cycle that was executed. HALT SEQUENCES When a halt instruction (HLT) is executed, the CPU enters the halt state (Typ) after state T2 of the next ma- chine cycle, as shown in Figure 2-11. There are only three ways in which the 8080 can exit the halt state: e A high an the RESET tine will always reset the 8080 to state T4; RESET also clears the program counter. A HOLD input will cause the 8080 to enter the hold state, as previously described. When the HOLD line goes low, the 8080 re-enters the halt state on the rising edge of the next @7 clack pulse. An interrupt {i.e,, INT goes high while INTE is enabled} will cause the 8080 to exit the Halt state and enter state T4 on the rising edge of the next 4 clock pulse. NOTE: The interrupt enable (INT E} flag must be set when the halt state is entered: otherwise, the 8080 will only be able to exit via a RESET signal. Figure 2-12 illustrates halt sequencing in flow chart form, START-UP OF THE 8080 CPU When power is applied initially to the 8080, the pro- cessor begins operating immediately. The contents of its program counter, stack pointer, and the other working regis- ters are naturally subject to randam factors and cannot be specified, For this reason, it will be necessary to begin the power-up sequence with RESET, An external RESET signal of three clock period dura- tion {minimum} restores the processor's internal program counter to zero, Program execution thus begins with mem- ory location zero, following a RESET. Systems which re- quire the processor to wait for an explicit start-up signal will store a halt instruction (El, HLT} in the first two loca- tions, A manual of an automatic INTERRUPT will be used for starting. In other systems, the processor may begin ex- ecuting its stored program immediately, Note, however, that the RESET has no effect on status flags, or on any of the processor's working registers (accumulator, registers, or stack pointer). The contents of these registers remain inde- terminate, until initialized explicitly by the program,Tete penny pe ee ee hes --4 STATUS i INFORMATION / @ | NOTE i) Fate: to Status Mord Chart on Page 2-6 Figure 2-11. HALT Timing Loi t TO STATE so TwarTy YES HALT STATE TO STATE % | MOLO STATE Figura 2-12. HALT Sequence Flow Chart.Tr Tost {| Tne2 |) Tne BOT et Tas Te | . nih = ee = eee ONG AESET : ttl j ' Np | INTERNAL . zt RESET a syne : 1 f , OBIN 4 { tt STATUS : INFORMATION | ! | . KO WHEN PEEET SIGNAL | ACTIVE. ALL OF CONTROL OUTAUT SIGNALS WILL BE RESET (MMEDIATEL Y OR SOME CLOCK FERIGO$ LATER. THE RESET SIGNAL MUST @ ACTIVE FOR & MINIMUM OF THREE CLOCK CYCLES. IN THE ABOVE DIAGAAM M ANDI MAY BE ANY INTEGER. 1 my OTE: CN pata sa States drora Cars on Pape M6 Figure 2-13. Raset. a % fm ee seggencce--- : ra | __ FOATING . \ FLOATING ~_a= ee See eee = = | SsYxC OBIN HOLD HOLD FF INTERNAL} HLDA INTE INT iN Me IMT FSF (INTERNALS STaTus INFORMATION WOT CW} Rater so Stetan ard Chart on Pape 74 Figure 2-14, Relation between HOLD and INT in the HALT State. 2-15MNEMGANIC i OF CODE wail AZ T vat Dy Dg Og Dg | 930201 0a Ti + plat Ta Ta TE 1 Tigi va HOW F102 100 |osss POOUT | PO=PC +1 |INST~TMPVIR | (SSS1-TMF (TMPI-O0D STATUS | | ! : 7 i | nl : Mow r,M 61BoB'B1d14 1 x HL OUT. DATA DOB I ! sTaTusisl : MOY Mor a1. oes . 1S88)-TMP HL OUT, rupiepata Bus : : STATUSIT . : au SPL ee 1oqg4 : 1HL ___ 45 i | Syl dana i og ODA i orig . : * POOWT 32 ae DD0D | 5TaTUs:6i : MAM, daa oot farig es 420 = FMF . \ LAI en, cana ooAP loood : ! x ' Po-PC-1 32 mer) : LEA adar qqr1i1tigi1a4 : x PO POs 1 32 eZ STA ade oO11 o91 0 : x POH Poet a2 ez LHLO ada goo 1ag 1o136 ; ' x . POs Po+1 22 ee ' : SHLO wder oo1da Bora : x . PC OUT, Poe roel alee STATUSIEl LOAX rplat oo RP '1oda : x rp yt TATA a sTaTusil STAX rpl4 oo AP oo16 : x rpOuUT | 1A) ae DATA BUS sTaTusl7l : xCHG 1116 ronda ' (HL (OE! ADDr 1oo00 os 56 i 1888|TMP Ist {ACTIHITMP A \ lAleaCT : : ADD M 70904 e134 i 1&l-aeT HL QUT. BAT Ante TMP STATUSIS | ADI ana 11a0 O8116 lAl=acT POOUT FC - PoA 1 2] Ge TMP - . STATUSIBl i Apter 1ao0 1s 8 8 i 1 1BSS1+TMP 191 IACTHITAP Aya} i , Ale aoT E OC 100 oO 6b 11 og ' i : Ao Aor HLauT . LAT Arte TP A ! sTaTusiai | t : ACI dara rragjriiia : . al =act PEOUT POPE +1 S28 TMP : i sTaTLsi& | suer toa oss 8 : | 1SSSIt MP fey) 1 SACTIACTMP a | lal+acT : SV M4 toa oi. 6 : : 1 Absa : HL GUT. TATA He TMP : i : . STATUSIB! Sul dana Pro rT: a1 1.98 : . 7 Lab ACT Pc OUT. Poe Po 4 32 ee TMP t sTaTUSIGl SRB r lagi 18 6 8 i {SS5h=-TMP ia (ACTI-ITM PIC YA i : (Al-acT saa M / 4004 trad 1A)+ACT HLOUF 2aT ate TMP . STATUSIEl | SB! dee 1aad1 1 tad : : 141+a0T PC OUT. PO =PO+#1 82 a TMP : sTaTusisl IWF r ooo00.01 a0 . : ID DD TMP aLL-OOo : : : ITMP) #14 IbeFL oo qo.o0)6 : * Ht OUT TAT a ~e TMP : STATUSIBL TM Pel He ALU OCR r ofoo0]b1981 \ (DO0}-TMP ALUODD iTMP)41-4&LU OCR O14 o191 : x HL OUT rata TMP STATUSIE | TP 1 pe LL INX rp oopRe BoO11 : {AP} +1 LAF DOCK og RF ioa4 | IPF 4 pF : L ' DAD rplal 1 oO RF 1oaqa1 I x biJ+acT {LL-TMP, ALLEL, CF : {ACTIHTMP! =a LU aaa attra loris / AANA, FLagglidl ANAT .irorialas ss i iS88K7TMP tal (ACTHY TMP na, + ' t i qa ACT ANAM 1ro1e f B11 90 POOUT | POTD +1 INST+TMPHIR | tAISACT HL OUT DATA TMP i STATUS | sTaTusiGi 2-16Pe OUT a PO-Po +! PO=Po+1 POs ?t+! DATA BUS Pos Po #1 Porc +! DATA BUS + {ACTHITMPI+A TACT H+ TMP, (ACTH TMP Ya, (acTle( TMP Cra, taCT HTTP] +A CACT]-(T MFA {ACT (TMP CA {ACTI-ITMP}-C1a DATA BUS (ACTHCITHPH+A wz QUT SsTATUsIEl WzMNEMONIC OP CODE marl Mz D7 Bg Og Dy | D409) Og nM r2ial a Ta 15 1 ria " 13 ANI date Priayorr POOWT = PC + Pos 1) INSTTMPHIA (A}-8CT POOUT | PC=PC+1 B71. TMF ! STATUE ! STAT Sie xAAT to20lfigs 8 i j (abACT ta] (ACTIFITPA +a : tSS815TMP XA MM 1ou1d tia 1AISACT HL OWT DATA TMP sTATUSIEl APL hate trig rr.a 1 [AleACT ACDUT 1 PC= Poe 82 Ge TMP : STATUE. | OFA; 101 eas 8 lAeacT al ACTH S(T MP} =a IS82"4TMP onAM POrr:+ gta g LAAT HLOUT DATA te TMP STaATuUSIG. | ORL date taidd utido iAisACT POOUT . os PGR POH a2 -te TMP STATUS | CMP r ra. 18 85 tA) -ACT ta * CACTIATMPI. FLAGS 1555|T MP CMP MA pori~prarara lA &OT HL QUT. DATA a TMe i STATUS CPI gata r14 T.taa lab-act POOUT | Por PC+ 62 TMP | STATUSIE: | RL oooo0fo114 (Al-ALU oe tal ALUGA, CF AOTATE . RAC ooao tara (IAL 191 + ALLA, GY ROTATE | RAL ao6o01 ord IAL, CSALU (si ables CF ROTATE j ASA gag. Tri ; Lak, Oy4+AL fal ALLA, OY AOTATE cMA oa1o0 1403 (AA CMe oor1raud di cyocy I STC OO 11%: Dati i+c JAP acer 1100 oo 41 x POOUT . : os PC +1 B22 sTATUS-4 i Jeonmade lM i 11 go, cate : JUBGE CONDITION pcauT | pceege> 32 -teeZ ' sTaTus.6 CALL addr rigayrras SP = SF. 1 POOWT P= pce a2 imz ST aTus.6: Coondacdrl7] | 11 cc ci0o4g JUDGE CONDITION POOuUt | Pee PO+ B2eez IF TAUE, SP = SP = 4 sTaTusil | RET , tog 1ag1 x sPauT = j SP=SF+? DaTaez t ; STATUS: 41 | F cond eddrl 171 r1rect!lcaaga INSTSTMPHIFL JUDGE CONDITICN[4! _ | Sea SP +10 CATAeRZ : STATUS. 131 | AST a 14NN So WT dd ow SP = 5P.4 SF OUT. gP=5P-1 (ACH! ee C8 TA BS INSTT MP/IR sTaTuUs.6. * POHL 1 fio too 4 INST>TMBR | HL} tr PUSH rp ,1.AP: of od i SP = 5P-t SPOUT | 5P+SP-1 (rhl--O4TA BUS ! STATUS. *l PUSH Pow roth; a.o7 ' SP~ SP -1 SPOUT. |, SP-5P-t 14)H DATA BUS | | STATUS. 16 POP iD 111A PFiggat x SPOUT 9: SP=8F+1 DATA-+terl sTaTugs: | POP Poe p1d4 ooo 4 x SPOUT | SP=SP+1 DATA-teFLAGS sTATUSiS! XTHL ti ratopig x of 5@ = SP HT CATA teZ . STATUS."5i | IN poet rig.) todd : x PODUT PC =PE+1 52 ez, W sTatusl | DUT port .104 goats i ! x PC OUT. Po = Po +1 Bg eeZ, Ww tt STATUS i El triad 1a. ' SET NTE F/F oF tadi4 oo11 1 RESET INTE FF : | HLT otit o11o : * Po OUT HALT MODE t t STATUS NOP oon] @o a0 | POOUT : fe-PO+ 1) INST+TMP;IR x aTaTus |Ma tzid (ACT - (TMP, (ACTIAITHP LA (ROTI +1T MPL, (ACTIOTMP) aa AACT TMP TACTI-FT MPL: FLAGS (AGTI(TMPL FLAGS | Po OUT POehce 52 ew a wee me Sebee : : wz OUT WE] +t PC STATUSIEL : . . : vf Fon : STaTusitil PC OUT PO = Pt +4 et Ww se : : aa : on me we gut wzi* 1 PC STATUS! + Sola oe 7 : STATUSIIt 12] PCOUT | Pla PE +1 53 ey ar OUT (PCH TABUS | SPOUT PCL Ie DATA BUS WZ OUT OWE] 41 = 86 STATUS! sTaTusiel | srs.p 1 STAT gi 16] : sTaTusi) POOUT | Po-Fo+4 a3 ew 3 SP OUT {PCH DATA Ls SP OUT IPCLIme DATA BUS wz OUT IZ) +1 6c STaTusi6l sTaTusiG] | space. - STAT US|] STaTusltt.12) $F OUT SP-5P+4 0 DATA ew : ot : w : weve. wz OUT WZ) #1 = PC STATUSIIS) ae vores SO : arene statisti 8? OUT. SP=SP+1 0 CATA mw Ww OUT Wwzl +1 PC STATUSIIS] STATUSI2 421 Sf oyt ITMP = SONNNOOK)) m Zz , . : a7 Jo de Wz OUT WZ +7 = PC STATUSI15] IPCLi~ LATA BUS : thie Soe ep . AES : Loeb sTATUSLIT SPOUT rl) tee TA BIS: sTaTus|'6] : SF OUT FLAGS D474 BUS STATUS|'6! SF QUT SPeSP+100 GATA- seerh sraTuslis! 5? OUT SP2SPs1 DATAeeA STATUSITS! SP OuT OATA t= TA BUS SPOUT ILI DaTa BUS CAE) ee HL STATIS] : STATUSLIEl W2 QUT DATA He A STATUSLIBL : W2 QUT Lal He DATA BUS sTaTUst ! 2-19NOTES: 1, Tha first mamory cycle (M1) is always an instruction fetch; the first for only} byte, containing the op code, is fetched during this cycie. 2. (f the READY input from memory is not high during T2 of each memory cycle, the processor will enter a wait state (TW? until READY is sampied as high. 3. States T4 and T5 are present, a$ required, for opera- tions which are completely internal to the CPU, The con- tents of the internal bus during T4 and TS are available at the data bus; this is designed for testing purposes only. An "%" denotes that the stata is present, but is only used for such internal operations as instruction decoding. 4. Only register pairs rp = B (registers B and C} or ro=O {registers D and ) may be specified. 5. These states are skipped. 6. Memory read sub-cycles; an instruction or data word will be read, 7. Memory write sub-cyele. 8. The READY signal is not required during the second and third sub-cycles (M2 and M3}. The HOLD signal is accepted during M2 and M3. The SYNC signal is not gene- rated during M2 and M3. During the execution of DAD, M2 and M3 are required for an internal register-pair add: memory is not referenced, 9. The results of these arithmetic, logical ar rotate in- structions are not moved inte the accumulator (A) until state T2 of the next instruction cycle, That is, A is loaded while the next instruction is being fetched; this overlapping of operations allows for faster processing. 10. If the value of the least significant 4-bits of the accumu- lator is greater than 9 ar if the auxiliary carry bit is set, 6 is added to the accumulator. If the value of the most signiti- cant 4bits of the accumulator is now greater than 9, or if the carry bit is set, Gis added to the most significant 4-bits of the accumulator. 11. This represents the first sub-cycie {the instruction fetch} of the next instruction cycle. 2-20 12. If the condition was met, the contents of the register pair WZ are output on the address lines (An45} instead of the contents of the program counter (PC), 13. If the condition was not met, sub-cycles M4 and M5 are skipped: the processor instead proceeds immediately to the instruction fetch (M1} of the next instruction cycle. 14, if the condition was not met, sub-cycles MZ and M3 are skipped; the processor instead proceeds immediately to the instruction fetch (M2) of the next instruction cycle. 15. Stack read sub-cycle, 16. Stack write sub-cycie. 17, CONDITION ccc NZ not zero (Z = 0) 000 Z zero (27 = 1} 001 NG no carry (CY =) o10 C carry (CY = 1) OT PQ parity odd {P = 0) 100 PE parity even (P = 1} 101 P olus ($= 9) 110 M minus {$= 1} 111 78, 1/0 sub-cycle: the |/O port's &bit setect code is dupli- cated on address lines 0-7 (Ag7) and &15 (Ag.re). 19. Output sub-cycte. 20, The processor will remain idle in the halt state until an interrupt, a reset or a hold is accepted, When a hold re- quest is accepted, the CPU enters the hold mode: after the held made is terminated, the processor returns to the hait state, After a reset is accepted, the processor begins execu- tion at memory location zero. After an interrupt is accepted, the processor executes the instruction forced onte the data bus (usually a restart instruction), $88 or DDD Value rp Value A 111 B 00 i B ooo Do 01 c a1 H ; 10 cD a10 "sp 11 E Olt H 100 | L 101This chapter will illustrate, in detail, how to interface the BOBO CPU with Memory and 1/0, It will also show the benefits and tradeoffs encountered when using a variety of system architectures to achieve higher throughput, de- creased component count or minimization af memory size. 8080 Microcomputer system design lends itself to a simple, modular approach. Such an approach will yield the designer a reliable, high performance system that contains a minimum component count and is easy te manufacture and maintain, The overall system can be thought af as a simple block diagram, The three (3) blocks in the diagram reore- sent the functions commen to any camputer system. CPU Module* Contains the Central Processing Unit, system timing and interface circuitry to Memory and 1/0 devices. Mamory Cantains Read Only Memory {ROM} and Read/Write Memory {RAM} for program and data storage. iO Contains circuitry that allows the computer system to communicate with devices or structures existing outside of the CPU or Memary array. for example: Paper Tape, etc. Keyboards, Floppy Disks, There are three busses that interconnect these blocks: Date Bust =A bi-directional path on which data can flow between the CPU and Memory or 1/0. Address Bus 4 uni-directional group of lines that identify a particular Memory location or 1/0 device. "Module refers to a functional block, it dogs not ref- erence a printed circuit board manufactured by INTEL. tBus refers to a set of signals grouped together because of the similarity of their functions. 31 Cantral Bus =A. uni-directional set of signals that indicate the type of activity in current process. Type of activities: 1. Memory Read 2. Memory Write 3. 1/0 Read 4. 1/0 Write 5. Interrupt Acknowledge 2 LORESS Bus cP - MOOMLE foo ay NL? r. DATA gus Figure 3-1. Typical Computer Systam Block Giagram Basic System Operation 1. The CPU Module issues an activity command an the Control Bus. z. The CPU Medule issues a binary code on the Address Bus to identify which particular Memory location or |{0 device will be involved in the current process activity. 3. The CPU Module receives or transmits data with the selected Memory location or 1/0 device. 4. The CPU Module returns to a and issues the next activity command. It is easy to see at this point that the CPU module is the central element in any computer system.The foliowing pages will cover the detailed design of the CPU Module with the 6080. The three Busses (Data, Address and Control} will be developed and the intercon- nection to Memory and 1/0 will be shown, Design philosophies and system architectures pre- sented in this manuai are consistent with Product develap- ment programs underway at INTEL for the MCS-80. Thus, the designer who uses this manual as a quide for his total system engineering is assured that ail new develoornents in components and software for MCS-80 from INTEL wiil be the design and ta achieve operationa: characteristics that ara as close as possible to those of the 8224 and 8228. Many auxiliary timing functions and festures of the 8224 and 8228 are toc compiex to practically implement in standard components, so only the basic functions of the 8224 and 8228 are generated. Since significant benefits in system timing and component count reduction can be realized by using the 8224 and 8228, this is thea preferred methed of implementation, compatible with his design approach. 1. 8080 CPU The operation of the 8080 CPL was covered in pre- CPU Module Design vious chapters of this manual, so little reference will be made to it in the design of the Module, The CPU Module contains three major areas: 1, The 8080 Central Processing Unit 2. Clock Ganerator and High Level Driver 2. A Clock Generator and High Levei Driver The BO8O is a dynamic device, meaning that its inter- 3. A bi-directional Data Bus Driver and System Control nal storage elements and logic circuitry require a Logic timing reference (Clock), supptied by external cir- . : . . cuitry, to refresh and provide timing control signals. The following will discuss the design of the three ; ; major areas contained in the CPU) Module. This design is The 8080 requires two (2} such Clocks. Their wave- presented as an alternative to the intel 224 Clock Gener- forms must be non-overlapping, and comply with the ator and Intel 8228 System Controller. By studying the timing and levels specified in the 8080 A.C. and D.C. alternative approach, the designer can mare clearly see the Characteristics, page 5-15. considerations involved in the specification and engineering . af the B224 and 8228. Standard TTL components and Intel Clock Generator Design general purpose peripheral devices are usad te implement The Clock Generator consists of a crystal controlled, GAD ad 8 ad 7 26 1ow " Al 5 + AD pee aA? ia 4 adv -4# BI AT ad pe at as pS} ________+ a5 PB cro ar pe a ag | ay AB ADDRESS BUS SYSTEM OMA AED i HOLD ag p32 ag Ag _ ald All ao ald SYSTEMINT AEG. 4] INT AlZ poe al? Ald poe add 16 34 INT ENABLE ty INTE aia pee ee AT ag Ps, ats wa b 4 ______, oO aTAL opin 2 HLDOA --, | 22 al oo 080 iy 2 pt bee bf ID o2 a fa} CZ 5LOCK 4# 4 wary 03 Bi-DIREC- jy 089 Wall AED A GENERATOR a REAGY oa : sus DerEA ons DATA BUS 7 RESET bs hi OBS 06 fee 4 Cad 3 SMC o7 bee Lefpereeege CE? ce 1 Fo STATUS STAOBE $$ Kant SYSTEM CONTROL ee KEM) CONTROL Bid $e TO 1c Figure 3-2. 8080 CPU Interface 3-2SSCiLLATOR in| 20 MH an LOI 330 330 , T4504 * Osc 74504 OBO RF Tag04 | CLOCK GENERATOR cLK 7486 sane Vee DA oA 0 | <$<$< nt TITTLE Da as 1a163 ry pc ac 7486 GNo> Do _oD 7a400 CLA LB J BIT TL | | = AUXILIARY FUNCTIONS Moe sNC 74400 Taleo Qo STsTe 74574 WAVEFORMS CLK * gla (TTL a LH La OO Sans WAIT REG D O- Aeany 92 250ns ma824 0mm wl be BGs ros als 250ns SYNC OMA REG Go o}* HOLO 14574 Leuk sTsTa@ \ / Figure 3-3. 8080 Clock Generator 20 MHZ oscillator, a four bit counter, and gating circuits, The oscillator provides a 20 MHZ signal to the input of a four (4) bit, presettable, synchronous, binary counter. By presetting the counter as shown in figure 3-3 and clocking it with the 20 MHZ signal, a simpte decoding of the counters outputs using standard TTL gates, provides proper timing for the two (2) 8080 elock inputs. Note that the timing must actually be measured at the output of the High Level Oriver to take into ac- count the added delays and waveform distortions within auch a device. High Level Driver Dasign The voltage level of the clocks for the 8080 is nat TTL compatible like the other signals that input ta the 8080, The voltage swing is from .6 volts (Virc! to 11 volts (Vig) with risetimes and falltimes under 50 ns. The Capacitive Drive is 20 pf {max.j. Thus, a High Level Driver is required to interface the outouts of the Clock Generator (TTL} to the 8080. The two (2) outputs of the Clack Generator are ca pacitivity coupled to a dual- High Level clock driver, The driver must be capable of complying with the 8080 clock input specifications, page 5-15. A driver of this type usually has Httle problem supplying the 3-3 positive transition when biased from the 8080 Vop supply (12) but to achieve the low voltage speciti- cation (Vite! .8 volts Max, the driver is biased to the 8080 Vag supply (-SV}. This allows the driver to swing from GND to Yoo with the aid of a simple resistor divider, A low resistance series network is added between the driver and the 8090 to eliminate any overshoot of the pulsed waveforms, Now a circuit is apparent that can easily comply with the 8080 specifications. In fact ris and failtimes of this design are typically less than 10 ns. +lay fe BED DF > ara ol TT Econ WA sogo PIN 291 R cener a cou 5 a 8 aT fF 4 T mee" 38080 PIN 15h = 15K ay Figure 3-4. High Level DriverAuxiliary Timing Signals and Functions The Clock Generator can also be used to previde other signais that the designer can use to simplify large system timing or the interface to dynamic memearies, Functions such as power-on reset, synchronization of external requests (HOLD, READY, etc.) and single step, could easily be added to the Clock Generator to further enhance its capabilities. For instance, the 20 MHZ signal fram the oscillator can be buffered so that it could provide the basis for communication baud rate generation. The Clock Generator diagram also shows how to gen- erate an advanced timing signal {@1A)} that is handy to use in clocking D" type flipflops to synchronize external requests. It can aiso be used to generate a strobe (STSTB) that is the latching signal for the sta- tus information which is available on the Data Bus at the beginning of each machine cycle. A simple gating of the SYNC signal from the 8080 and the advanced {@1A} will do the job, See Figure 3-3. Bi-Diractional Bus Driver and System Control Logic The system Memory and I/O devices communicate with the CPU over the bi-directional Data Bus. The system Control Bus is used to gate data on and off the Data Bus within the proper timing sequences as dictated by the operation af the 8080 CPU. The data lines of the 8080 CPU, Memory and I/O devices are 3-state in nature, that is, their output drivers have the ability to be forced into a high-impedance mode and are, effectively, removed from the circuit. This 3- state bus technique allows the designer to construct a system around a single, eight (8) bit parallel, bi-direc- tional Data Bus and simply gate the information on or otf this bus by selecting or deselecting (3-stating) Memory and i/O devices with signals from the Con- trol Bus. Bi-Directional Data Bus Drivar Gesign The 8080 Oata Bus {D7-D0) has two (2) major areas of concern for the designer: 1. toput Voltage level (Vi) 3.3 volts minimum, 2. Output Drive Capability (lg_} 3.7 mA maximum, Cec Ost DS? OBI oa4 O85 DBS Oa? a INTA 5 FMT A STACK 10 ALTA 16 OUT TOR Tt? M1 13 INP 21 MEM MEM R Veg now MEM WW Figura 3-5. 8080 System Control 34The input level specitication implies that any semi- conductor memory or I/O device connected to the 8080 Data Bus must be able to provide a minimum of 3.4 volts in its high state. Most semiconductor mem- ories and standard TTL 1/0 devices have an output capability of between 2.0 ang 2.8 volts, obviously a direct connection anto the 8080 Gata Bus would re- quire pullup resistors, whose value should not affect the bus speed or stress the drive capability of the memory or 1/O components, The BOBOA output drive capability (Ip_} 1.9mA max. is sufficient for smail systems where Memory size and 10 raquirements are minimal and the entire system is contained on a single printed circuit board. Mast sys- tems however, take advantage of the high-perfor- mance computing power of the 8080 CPU and thus a more typical system would require some form of buf- fering on the 8080 Data Bus to support a larger array of Memory and 1/0 devices which are likely to be on separate boards. A device specifically designed to do this buffering function is the INTEL 8216, a (4) four bit bi-direc- tional bus driver whose input voltage levelis compat- ible with standara TTL devices and semiconductor memory components, and has ovtput drive capability of 50 mA. At the 8080 side, the 8216 has a high output of 3.65 volts that mot only meets the 8080 input spec but provides the designer with a worse case 350 mV noise margin, 4 pair of 8216's are connected directly to the 8080 Data Bus (07-00) as shown in figure 3-5. Note that the DBIN signal from the 8080 is connected to the direction control input (DIEN) so the carrect flow of data on the bus is maintained. The chip select (C5) of the B216 is connected to BUS ENABLE (BUSEN) to allow for DMA activities by deselecting the Data Bus Buffer and forcing the outputs of the 8216's into their high impedance (3-state] mode. This allows other devices to gain access to the data bus (DMA). System Controi Logic Dasign The Contrei Bus maintains discipline of the bi-direc- tional Data Bus, that is, it determines what type of device will have access to the bus (Memory or |/O} and generates signals to assure that these devices transfer Data with the 8080 CPU within the proper timing windows as dictated by the CPU operational characteristics. As described previously, the 8080 issues Status infor- mation at the beginning of each Machine Cycle on its Data Bus to indicate what operation will take place during that cycle, 4 simple {8} bit latch, like an INTEL 8212, connected directly to the S080 Data Bus (D7-B0) as shown in figure 3-5 will store the 35 Status information, The signal that ioads the data into the Status Latch comes from the Clock Gener- ator, it is Status Strobe {STSTB) and occurs at the start of each Machine Cycle, Note that the Status Latch is connected onto the 8080 Data Bus (07-00) before the Sus Butter. This is to maintain the integrity of the Data Bus and simplify Cantral Bus timing inOMA dependent environments. As shown in the diagram, a simple gating of the out- puts of the Status Latch with the DBIN and Wa signals from the 8080 generate the (4) four Control signals that make up the basic Control Bus. These four signals: 1. Memory Read (MEM R} 2. Memory Write (MEM W} 3. 1/0 Read (170 R) 4.1/0 Write (70 Wi connect directly ta the MCS-80 component "family of ROMs, RAMs and 1/0 devices. A fifth signal, Interrupt Acknowledge (INTAI is added to the Control Bus by gating data off the Status Latch with the DBIN signal from the 8080 CPU. This signal is used to enable the Interrupt Instruction Port which holas the RST instruction onto the Data Bus, Other signais that are part of the Control Bus such as WO. Stack and M7 are present to aid in the testing of the System and also ta simplify interfacing the CPU te dynamic memories or very large systems that re- quire several levels of bus buffering. Address Buffer Design The Address Bus 1A15-A0} of the 800, like the Data Bus, is sufficient to support a small system that has a moderate size Memory and |/O structure, canfined to a single card. To expand the size of the system that the Address Bus can support a simple buffer can be added, as shown in figure 3-6. The INTEL 8212 oF B216 is an excellent device for this function. They provide low input loading (.25 mA}, high output drive and insert a minimal delay in the System Timing. Note that BUS ENABLE (BUSEN) is connected to the buffers sc that they are forced into their high- impedance (3-state) mode during DMA activities so that other devices can gain access to the Adcrass Bus.INTERFACING THE 8680 CPU TO MEMORY AND I/O DEVICES The 8080 interfaces with standard semiconductor Memory companents and |/O devices. (n the previous text the proper control signals and buffering were developed which will produce a simple bus system similar to the basic system example shown at the beginning of this chapter. tn Figure 3-6 a simple, but exact 8080 typical system is shown that can be used as a guide for any 8080 system, regardless of size or complexity. It is a three bus archi- tecture, using the signals developed in the CPU module. Note that Memory and i/O devices interface in the same manner and that ther isolation is oniy a function of the definition of the Read-Write signals on the Control Bus. This allows the 8080 system to be configured so that Mem- ory and (/O are treated as a single array (memory mapped 1/0} for small systems that require high thruput and have less than 32K memory size. This approach will be brought out Jater in the chapter, ROM INTERFACE A ROM 5s a device that stores data in the tarm of Program or other information such as look-up tables and ig only read from, thus the term Read Only Memory. This type of memory is generally non-volatile, meaning that when the power is removed the information is retained. This feature eliminates the need for extra equipment tike tape readers and disks to load programs initially, an im- portant aspect in small system design. Interfacing standard ROMs, such as the devices shown in the diagram is simple and direct. The output Data lines are connected to the bi-directional Data Bus, the Address inputs tie to the Address bus with possible decoding of the Most significant bits as chip selects and the MEMR signal from the Control Bus connected to a chip select or data butter. Basically, the CPU issues an address during the first portion of an instruction or data fetch (T1 & T2). This value on the Address Bus selects a specific tocation within the ROM, than depending on the ROM's delay {access time) the data stored at the addressed location ts present at the Data output lines. At this time (T3) the CPU Data Bus is in the input Mode" and the control logic issues a Memory Read command (MEMR) that gates the addressed data on ta the Data Bus. RAM INTERFACE A RAM is a device that stores data. This data can be program, active look-up tabdles, temporary values or ex: ternal stacks. The difference between RAM and ROM is that data can be written into such devices and are in essence, Read/Write storage elements. RAMs do not hold their data when power is removed so in the case where Pro- gram or look-up tables data is stared a method to ioad STSTE CLOCK 8224 ] GENERATOR | p HOLD AEG AND DRIVER if J SYNC oo? at AESET INT hi AbY a0koa CPL WA 00-07 OBIN HLDA AD ATE ma r 1 1 i l | : 1 ; i. eS H B228 | B21? ADDRESS 4 Baza agaz giar2 aio7A-4 SYSTEM i pops = SUFFERS 5 gaa AQ; aaa B12 RAN BITE CONTROLLER Ul sare wrronaLy | ars aa18A 1022 = s1p1 B22? r p T r | | | DATA BUS 1H) Ab GL] iLife IL eT] CONTROL 85 16 Tr T TT Lf : | jl Li : : ADDAESS BUS 11 Es Ss, J 251 uo Bate COMMUNICATION 8255 INTERFACE a }] B24 resonant ' CE RIPHERAL 8212 eee! INTERRUPT Figure 36. Microcomputer System 34RAM memory must be provided, such as: Floppy Disk, Paper Tape, etc. The CPU treats RAM in exactly the same manner as AOM for addressing data to be read. Writing data is very similar, the RAM is issued an address during the first par- tion of the Memory Write cycle (T1 & 72) in T3 when the data that is ta be written is output by the CPU and is stable on the bus an MEMW cammand is generated. The MEMW signa is connected ta the R/W input of the RAM and strobes the data into the addressed location. In Figure 3-7 a typical Memory system is iHustrated to show how standard semiconductor components interface to the 8080 bus. The memory array shown has BK bytes {2 bits/byte) of ROM storage, using four Intel" 8216As and 512 bytes of RAM storage, using Intel 8111 static RAMs. The basic interface ta the bus structure detailed here is common to almost any size memory. The only ad- dition that might have to be made for larger systems is more buffers (8216/8212} and decoders (8205) for gener- ating chip selects. The memories chosen for this example have an access time of 850 n& (max} to illustrate that slower, ecanamical devices can be easily interfaced to the 8080 with little ef- fect on performance. When the #080 is operated from a clock generator with a tCY of 500 nS the required memory access time is Approx, 450-550 n$. See detailed timing specification Pg. 5-16. Using memory devices of this speed such as Intel8308, 81024, S074, ete. the READY input to the 8080 CPU can remain high because no wait states are required. Note that the bus interface to memory shown in Figure 3-7 remains the same. However, if slower memories are to be used, such as the devices llustrated (83164, 8111} that have access times slower than the min- imum requirement a simple logic cantrel of the READY input te the 8080 CPU wit insert an extra wait state that is equal to one or more clock periods a5 an access time adjustment delay to compensate. The effect of the extra wait state is naturally a slower execution time for the instruction. A single wait changes the basic instruction cyele to 2.5 micraSeconds, 8K + 612 ak o RAM ROM MEMORY MAP ROM RAM ] J Bit git B316A cs3 cs (* RAW OD 101-4 ADA? RAW OO WO14 AAT csi 0108 aaa} Zs eM EMR AO-A? TER Mena | Aba? MEMR agato a DATA BUS 18 4 CONTROL BUS 16) SODAESS BUS (16) Figure 3-7. Typical Memory Interface a71/0 INTERFACE Ganeral Theory As in any computer based system, the 8080 CPU must be able to communicate with devices or structures that exist outside its normal memory array. Devices like keyboards, Paper tape, floppy disks, printers, displays and other control structures are used to input information inte the BOBO CPU and display or store the results of the computational activity. Probably the most important and strongest feature of the 8080 Microcomputer System is the flexibility and power of its I/O structure and the components that support it. There are many ways to structure the iO array so that it will fit the total system environment to maximize efficiency and minimize component count. The basic operation of the 1/0 structure can best be viewed a3 an array of single byte memory locatians that can be Read from or Written into. The BO80 CPU has special in- structions devoted to managing such transfers (IN, OUT). These instructions generally isolate memory and |/O arrays so that memory address space is not effected by the 1/0 structure and the general concept is that of a simple transfer te or from the Accumulator with an addressed PORT. 4n- other method of I/O architecture is to treat the I/O structure as part of the Memory array. This is generally referred to as Memory Mapped (/O" and provides the designer with a powerful new instruction set devoted to 1/0 manipulation, 'SOLATEDIG a 65K 1 1 : MEMORY | | 6 256 | 1 ; oO 1 ' | 2 Pe * | a a2K B5K | | | MEMORY | | SENQRY MAPPED! O Figure 3-8. Memory/t/O Mapping. Isolated 1/0 In Figure 3-9 the system control signals, previously de- tailed in this chapter, are shown, This type of (/O architecture separates the memory address space fram the I/O address space and uses a conceptually simple transfer to or from Ac- cumulator technique. Such an architecture is easy to under- stand because 1/Q communicates only with the Accumulator using the IN or OUT instructions. Also because af the isola- tion of memory and 1/0, the full address space (65K) is un- effected by I/O addressing. 3-4 + DEVICES SYSTEM CONTROL (8228) Figure 3-9. Isolated I/O. Mamory Mapped 1/0 By assigning an area of memory address space as 1/O a powerful architecture can be developed that can manioulate 170 using the same instructions that are used to manipudate memory locations. Thus, a new instruction set is created that is devoted to 1/C handling. As shown in Figure 3-10, new control signals are gene- rated by gating the MEMRA and MEMW signals with A745, the most significant address bit. The new [/C control signals con- nect in exactly the same manner as isolated (/O, thus the system bus characteristics are unchanged. By assigning A715 as the 1/0 "flag", a simple method of \/0 discipline is maintained: If A715 is a zero then Memory is active. If A715 is a one then 1/0 is active. Other address bits can also be used for this function. 475 was chosen because it is the most significant address bit so it is easier to control with software and because it still allows memory addressing of 37K. (40 devices are still considered addressed ports but instead of the Accumulator as the only transfer medium any of the internal registers can be used. Al} instructions that could be used to operate on memory locations can be used in 140, Examples: MOvVr, M {Inout Port to any Register) MOV M,r (Output any Register to Part} MVIM (Output immediate data to Part} LOA {Input te ACC} STA {Gutput from ACC to Part} LHLD (16 Bit Enput} SHLD (16 Bit Output) ADD M {Add Part ta ACC) ANAM ("AND Port with ACC] it is easy to see that from the list of possible new instructions that this type of 1/0 architecture could have a drastic effect on increased system throughput, it is concep- tually more difficult to understand than Isolated I/O and it does limit memory address space, but Memory Mapped 1/0 can mean a significant increase in overall speed and at the same time reducing required program memory area.