LMK00301SQE/NOPB - Texas Instruments

3:1

MUX

SYNC

CLKoutA0

CLKoutA0*

CLKoutA4

CLKoutA4*

CLKin0

CLKin0*

CLKin1

CLKin1*

OSCin

OSCout

REFout_EN

CLKoutA_TYPE[1:0]

CLKin_SEL[1:0]

REFout (LVCMOS)

GND

VCCOA

VCCOC

VCC VCCOA VCCOB VCCOC

Bank A

5 Output Pairs

(LVPECL, LVDS,

HCSL, or Hi-Z)

Universal Inputs

(Differential/

Single-Ended)

Crystal

CLKoutB0

CLKoutB0*

CLKoutB4

CLKoutB4*

VCCOB

CLKoutB_TYPE[1:0] 2

Bank B

5 Output Pairs

(LVPECL, LVDS,

HCSL, or Hi-Z)

LMK00301

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SNAS512G –SEPTEMBER 2011–REVISED MAY 2013

LMK00301 3-GHz 10-Output Differential Clock Buffer/Level Translator

Check for Samples: LMK00301

1FEATURES TARGET APPLICATIONS

2• 3:1 Input Multiplexer • Clock Distribution and Level Translation for

ADCs, DACs, Multi-Gigabit Ethernet, XAUI,

– Two Universal Inputs Operate up to 3.1 GHz Fibre Channel, SATA/SAS, SONET/SDH, CPRI,

and Accept LVPECL, LVDS, CML, SSTL, High-Frequency Backplanes

HSTL, HCSL, or Single-Ended Clocks • Switches, Routers, Line Cards, Timing Cards

– One Crystal Input Accepts 10 to 40 MHz

Crystal or Single-Ended Clock • Servers, Computing, PCI Express (PCIe 3.0)

• Two Banks with 5 Differential Outputs Each • Remote Radio Units and Baseband Units

– LVPECL, LVDS, HCSL, or Hi-Z (Selectable DESCRIPTION

Per Bank) The LMK00301 is a 3-GHz, 10-output differential

– LVPECL Additive Jitter with LMK03806 fanout buffer intended for high-frequency, low-jitter

Clock Source at 156.25 MHz: clock/data distribution and level translation. The input

– 20 fs RMS (10 kHz – 1 MHz) clock can be selected from two universal inputs or

one crystal input. The selected input clock is

– 51 fs RMS (12 kHz – 20 MHz) distributed to two banks of 5 differential outputs and

• High PSRR: -65 / -76 dBc (LVPECL/LVDS) at one LVCMOS output. Both differential output banks

156.25 MHz can be independently configured as LVPECL, LVDS,

• LVCMOS Output with Synchronous Enable or HCSL drivers, or disabled. The LVCMOS output

Input has a synchronous enable input for runt-pulse-free

operation when enabled or disabled. The LMK00301

• Pin-Controlled Configuration operates from a 3.3 V core supply and 3 independent

• VCC Core Supply: 3.3 V ± 5% 3.3 V/2.5 V output supplies.

• 3 Independent VCCO Output Supplies: 3.3 V/2.5 The LMK00301 provides high performance,

V ± 5% versatility, and power efficiency, making it ideal for

• Industrial Temperature Range: -40°C to +85°C replacing fixed-output buffer devices while increasing

• 48-lead WQFN (7 mm x 7 mm) timing margin in the system.

Functional Block Diagram

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

CLKoutA0

CLKoutA0*

CLKoutA1

VCCOA

GND

OSCin

CLKin_SEL0

CLKin_SEL1

CLKoutB4

CLKoutB2*

CLKoutB2

CLKoutB1*

GND

CLKin1*

GND

REFout_EN

CLKoutA1*

VCCOA

CLKoutA2

CLKoutA2*

CLKoutA3

CLKoutA3*

CLKoutA4

CLKoutA4*

CLKoutA_TYPE0

VCC

OSCout

GND

CLKin0

CLKin0*

CLKoutB_TYPE0

GND

CLKoutB4*

CLKoutB3*

CLKoutB3

VCCOB

CLKoutB1

CLKoutB0*

CLKoutB0

CLKoutB_TYPE1

CLKin1

VCC

REFout

VCCOC

CLKoutA_TYPE1

GND

4748 46 45 44 43 42 41 40 39 38 37

1413 15 16 17 18 19 20 21 22 23 24

DAP

Top Down View

LMK00301

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Connection Diagram

Figure 1. 48-Pin

RHS0048A Package

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PIN DESCRIPTIONS(1)

Pin # Pin Name(s) Type Description

DAP DAP GND Die Attach Pad. Connect to the PCB ground plane for heat dissipation.

1, 2 CLKoutA0, CLKoutA0* O Differential clock output A0. Output type set by CLKoutA_TYPE pins.

3, 4 CLKoutA1, CLKoutA1* O Differential clock output A1. Output type set by CLKoutA_TYPE pins.

Power supply for Bank A Output buffers. VCCOA can operate from 3.3 V or

5, 8 VCCOA PWR 2.5 V. The VCCOA pins are internally tied together. Bypass with a 0.1 uF

low-ESR capacitor placed very close to each Vcco pin. (2)

6, 7 CLKoutA2, CLKoutA2* O Differential clock output A2. Output type set by CLKoutA_TYPE pins.

9, 10 CLKoutA3, CLKoutA3* O Differential clock output A3. Output type set by CLKoutA_TYPE pins.

11, 12 CLKoutA4, CLKoutA4* O Differential clock output A4. Output type set by CLKoutA_TYPE pins.

13, 18, 24, GND GND Ground

37, 43, 48

14, 47 CLKoutA_TYPE0, CLKoutA_TYPE1 I Bank A output buffer type selection pins (3)

Power supply for Core and Input Buffer blocks. The Vcc supply operates

15, 42 Vcc PWR from 3.3 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to

each Vcc pin.

Input for crystal. Can also be driven by a XO, TCXO, or other external

16 OSCin I single-ended clock.

Output for crystal. Leave OSCout floating if OSCin is driven by a single-

17 OSCout O ended clock.

19, 22 CLKin_SEL0, CLKin_SEL1 I Clock input selection pins (3)

20, 21 CLKin0, CLKin0* I Universal clock input 0 (differential/single-ended)

23, 39 CLKoutB_TYPE0, CLKoutB_TYPE1 I Bank B output buffer type selection pins (3)

25, 26 CLKoutB4*, CLKoutB4 O Differential clock output B4. Output type set by CLKoutB_TYPE pins.

27, 28 CLKoutB3*, CLKoutB3 O Differential clock output B3. Output type set by CLKoutB_TYPE pins.

Power supply for Bank B Output buffers. VCCOB can operate from 3.3 V or

29, 32 VCCOB PWR 2.5 V. The VCCOB pins are internally tied together. Bypass with a 0.1 uF

low-ESR capacitor placed very close to each Vcco pin. (2)

30, 31 CLKoutB2*, CLKoutB2 O Differential clock output B2. Output type set by CLKoutB_TYPE pins.

33, 34 CLKoutB1*, CLKoutB1 O Differential clock output B1. Output type set by CLKoutB_TYPE pins.

35, 36 CLKoutB0*, CLKoutB0 O Differential clock output B0. Output type set by CLKoutB_TYPE pins.

Not connected internally. Pin may be floated, grounded, or otherwise tied to

38 NC — any potential within the Supply Voltage range stated in Absolute Maximum

Ratings.

40, 41 CLKin1*, CLKin1 I Universal clock input 1 (differential/single-ended)

44 REFout O LVCMOS reference output. Enable output by pulling REFout_EN pin high.

Power supply for REFout Output buffer. VCCOC can operate from 3.3 V or

45 VCCOC PWR 2.5 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to each

Vcco pin. (2)

REFout enable input. Enable signal is internally synchronized to selected

46 REFout_EN I clock input. (3)

(1) Any unused output pin should be left floating with minimum copper length (see note in Clock Outputs), or properly terminated if

connected to a transmission line, or disabled/Hi-Z if possible. See Clock Outputs for output configuration and Termination and Use of

Clock Drivers for output interface and termination techniques.

(2) The output supply voltages or pins (VCCOA, VCCOB, and VCCOC) will be called VCCO in general when no distinction is needed, or when the

output supply can be inferred from the output bank/type.

(3) CMOS control input with internal pull-down resistor.

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Functional Description

The LMK00301 is a 10-output differential clock fanout buffer with low additive jitter that can operate up to 3.1

GHz. It features a 3:1 input multiplexer with an optional crystal oscillator input, two banks of 5 differential outputs

with multi-mode buffers (LVPECL, LVDS, HCSL, or Hi-Z), one LVCMOS output, and 3 independent output buffer

supplies. The input selection and output buffer modes are controlled via pin strapping. The device is offered in a

48-pin WQFN package and leverages much of the high-speed, low-noise circuit design employed in the

LMK04800 family of clock conditioners.

VCC and VCCO Power Supplies

The LMK00301 has separate 3.3 V core (VCC) and 3 independent 3.3 V/2.5 V output power supplies (VCCOA,

VCCOB, VCCOC) supplies. Output supply operation at 2.5 V enables lower power consumption and output-level

compatibility with 2.5 V receiver devices. The output levels for LVPECL (VOH, VOL) and LVCMOS (VOH) are

referenced to its respective Vcco supply, while the output levels for LVDS and HCSL are relatively constant over

the specified Vcco range. Refer to Power Supply and Thermal Considerations for additional supply related

considerations, such as power dissipation, power supply bypassing, and power supply ripple rejection (PSRR).

NOTE

Care should be taken to ensure the Vcco voltages do not exceed the Vcc voltage to

prevent turning-on the internal ESD protection circuitry.

Clock Inputs

The input clock can be selected from CLKin0/CLKin0*, CLKin1/CLKin1*, or OSCin. Clock input selection is

controlled using the CLKin_SEL[1:0] inputs as shown in Table 1. Refer to Driving the Clock Inputs for clock input

requirements. When CLKin0 or CLKin1 is selected, the crystal circuit is powered down. When OSCin is selected,

the crystal oscillator circuit will start-up and its clock will be distributed to all outputs. Refer to Crystal Interface for

more information. Alternatively, OSCin may be driven by a single-ended clock (up to 250 MHz) instead of a

crystal.

Table 1. Input Selection

CLKin_SEL1 CLKin_SEL0 Selected Input

0 0 CLKin0, CLKin0*

0 1 CLKin1, CLKin1*

1 X OSCin

Table 2 shows the output logic state vs. input state when either CLKin0/CLKin0* or CLKin1/CLKin1* is selected.

When OSCin is selected, the output state will be an inverted copy of the OSCin input state.

Table 2. CLKin Input vs. Output States

State of State of

Selected CLKin Enabled Outputs

CLKinX and CLKinX* Logic low

inputs floating

CLKinX and CLKinX* Logic low

inputs shorted together

CLKin logic low Logic low

CLKin logic high Logic high

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Clock Outputs

The differential output buffer type for Bank A and Bank B outputs can be separately configured using the

CLKoutA_TYPE[1:0] and CLKoutB_TYPE[1:0] inputs, respectively, as shown in Table 3. For applications where

all differential outputs are not needed, any unused output pin should be left floating with a minimum copper

length (see note below) to minimize capacitance and potential coupling and reduce power consumption. If an

entire output bank will not be used, it is recommended to disable (Hi-Z) the bank to reduce power. Refer to

Termination and Use of Clock Drivers for more information on output interface and termination techniques.

NOTE

For best soldering practices, the minimum trace length for any unused output pin should

extend to include the pin solder mask. This way during reflow, the solder has the same

copper area as connected pins. This allows for good, uniform fillet solder joints helping to

keep the IC level during reflow.

Table 3. Differential Output Buffer Type Selection

CLKoutX_ CLKoutX_ CLKoutX Buffer Type

TYPE1 TYPE0 (Bank A or B)

0 0 LVPECL

0 1 LVDS

1 0 HCSL

1 1 Disabled (Hi-Z)

Reference Output

The reference output (REFout) provides a LVCMOS copy of the selected input clock. The LVCMOS output high

level is referenced to the Vcco voltage. REFout can be enabled or disabled using the enable input pin,

REFout_EN, as shown in Table 4.

Table 4. Reference Output Enable

REFout_EN REFout State

0 Disabled (Hi-Z)

1 Enabled

The REFout_EN input is internally synchronized with the selected input clock by the SYNC block. This

synchronizing function prevents glitches and runt pulses from occurring on the REFout clock when enabled or

disabled. REFout will be enabled within 3 cycles (tEN) of the input clock after REFout_EN is toggled high. REFout

will be disabled within 3 cycles (tDIS) of the input clock after REFout_EN is toggled low.

When REFout is disabled, the use of a resistive loading can be used to set the output to a predetermined level.

For example, if REFout is configured with a 1 kΩload to ground, then the output will be pulled to low when

disabled.

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings(1)(2)(3)

Parameter Symbol Ratings Units

Supply Voltages VCC, VCCO -0.3 to 3.6 V

Input Voltage VIN -0.3 to (VCC + 0.3) V

Storage Temperature Range TSTG -65 to +150 °C

Lead Temperature (solder 4 s) TL+260 °C

Junction Temperature TJ+150 °C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test

conditions, see Electrical Characteristics. The ensured specifications apply only to the test conditions listed.

(2) This device is a high-performance integrated circuit with an ESD rating up to 2 kV Human Body Model, up to 150 V Machine Model, and

up to 750 V Charged Device Model and is ESD sensitive. Handling and assembly of this device should only be done at ESD-free

workstations.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

Recommended Operating Conditions

Parameter Symbol Min Typ Max Units

Ambient Temperature Range TA-40 25 85 °C

Junction Temperature TJ125 °C

Core Supply Voltage Range VCC 3.15 3.3 3.45 V

3.3 – 5% 3.3 3.3 + 5%

Output Supply Voltage Range (1) (2) VCCO V

2.5 – 5% 2.5 2.5 + 5%

(1) The output supply voltages or pins (VCCOA, VCCOB, and VCCOC) will be called VCCO in general when no distinction is needed, or when the

output supply can be inferred from the output bank/type.

(2) Vcco for any output bank should be less than or equal to Vcc (Vcco ≤Vcc).

Package Thermal Resistance

Package θJA θJC (DAP)

48-Lead WQFN (1) 28.5 °C/W 7.2 °C/W

(1) Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These

vias play a key role in improving the thermal performance of the package. It is recommended that the maximum number of vias be used

in the board layout.

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Electrical Characteristics

Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤TA≤85 °C, CLKin driven

differentially, input slew rate ≥3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, TA

= 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. (1)

Symbol Parameter Conditions Min Typ Max Units

Current Consumption(2)

CLKinX selected 8.5 10.5 mA

Core Supply Current,

ICC_CORE All Outputs Disabled OSCin selected 10 13.5 mA

Additive Core Supply

ICC_PECL Current, Per LVPECL 20 27 mA

Bank Enabled

Additive Core Supply

ICC_LVDS Current, Per LVDS 26 32.5 mA

Bank Enabled

Additive Core Supply

ICC_HCSL Current, Per HCSL 35 42 mA

Bank Enabled

Additive Core Supply

ICC_CMOS Current, LVCMOS 3.5 5.5 mA

Output Enabled

Additive Output Supply Includes Output Bank Bias and Load Currents,

ICCO_PECL Current, Per LVPECL RT= 50 Ωto Vcco - 2V 165 197 mA

Bank Enabled on all outputs in bank

Additive Output Supply

ICCO_LVDS Current, Per LVDS 34 44.5 mA

Bank Enabled

Additive Output Supply Includes Output Bank Bias and Load Currents,

ICCO_HCSL Current, Per HCSL RT= 50 Ω87 104 mA

Bank Enabled on all outputs in bank

Vcco = 9 10 mA

Additive Output Supply 3.3 V ± 5%

200 MHz,

ICCO_CMOS Current, LVCMOS CL= 5 pF Vcco =

Output Enabled 7 8 mA

2.5 V ± 5%

Power Supply Ripple Rejection (PSRR)

Ripple-Induced 156.25 MHz -65

PSRRPECL Phase Spur Level (3) dBc

312.5 MHz -63

Differential LVPECL Output

Ripple-Induced 100 kHz, 100 mVpp 156.25 MHz -76

PSRRHCSL Phase Spur Level (3) Ripple Injected on Vcco, dBc

312.5 MHz -74

Differential HCSL Output Vcco = 2.5 V

Ripple-Induced 156.25 MHz -72

PSRRLVDS Phase Spur Level (3) dBc

312.5 MHz -63

Differential LVDS Output

CMOS Control Inputs (CLKin_SELn, CLKoutX_TYPEn, REFout_EN)

VIH High-Level Input Voltage 1.6 Vcc V

VIL Low-Level Input Voltage GND 0.4 V

IIH High-Level Input Current VIH = Vcc, Internal pull-down resistor 50 µA

IIL Low-Level Input Current VIL = 0 V, Internal pull-down resistor -5 0.1 µA

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(2) See Power Supply and Thermal Considerations for more information on current consumption and power dissipation calculations.

(3) Power supply ripple rejection, or PSRR, is defined as the single-sideband phase spur level (in dBc) modulated onto the clock output

when a single-tone sinusoidal signal (ripple) is injected onto the Vcco supply. Assuming no amplitude modulation effects and small index

modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as

follows: DJ (ps pk-pk) = [ (2 * 10(PSRR / 20))/(π* fCLK) ] * 1E12

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Electrical Characteristics (continued)

Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤TA≤85 °C, CLKin driven

differentially, input slew rate ≥3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, TA

= 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. (1)

Symbol Parameter Conditions Min Typ Max Units

Clock Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*)

Functional up to 3.1 GHz

Output frequency range and timing specified per

fCLKin Input Frequency Range (4) DC 3.1 GHz

output type (refer to LVPECL, LVDS, HCSL,

LVCMOS output specifications)

Differential Input

VIHD Vcc V

High Voltage

Differential Input

VILD CLKin driven differentially GND V

Low Voltage

Differential Input

VID 0.15 1.3 V

Voltage Swing (5)

VID = 150 mV 0.25 Vcc - 1.2

Differential Input

VCMD VID = 350 mV 0.25 Vcc - 1.1 V

Common Mode Voltage VID = 800 mV 0.25 Vcc - 0.9

Single-Ended Input

VIH Vcc V

High Voltage

Single-Ended Input

VIL GND V

CLKinX driven single-ended (AC or DC coupled),

Low Voltage CLKinX* AC coupled to GND or

Single-Ended Input Voltage externally biased within VCM range

VI_SE 0.3 2 Vpp

Swing (6)

Single-Ended Input

VCM 0.25 Vcc - 1.2 V

Common Mode Voltage fCLKin0 = 100 MHz -84

fCLKin0 = 200 MHz -82

Mux Isolation, fOFFSET > 50 kHz,

ISOMUX dBc

CLKin0 to CLKin1 PCLKinX = 0 dBm fCLKin0 = 500 MHz -71

fCLKin0 = 1000 MHz -65

Crystal Interface (OSCin, OSCout)

External Clock OSCin driven single-ended,

FCLK 250 MHz

Frequency Range (4) OSCout floating

Fundamental mode crystal

FXTAL Crystal Frequency Range ESR ≤200 Ω(10 to 30 MHz) 10 40 MHz

ESR ≤125 Ω(30 to 40 MHz)(7)

CIN OSCin Input Capacitance 1 pF

(4) Specification is ensured by characterization and is not tested in production.

(5) See Differential Voltage Measurement Terminology for definition of VID and VOD voltages.

(6) Parameter is specified by design, not tested in production.

(7) The ESR requirements stated must be met to ensure that the oscillator circuitry has no startup issues. However, lower ESR values for

the crystal may be necessary to stay below the maximum power dissipation (drive level) specification of the crystal. Refer to Crystal

Interface for crystal drive level considerations.

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Electrical Characteristics (continued)

Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤TA≤85 °C, CLKin driven

differentially, input slew rate ≥3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, TA

= 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. (1)

Symbol Parameter Conditions Min Typ Max Units

LVPECL Outputs (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)

Vcco = 3.3 V ± 5%, 1.0 1.2

VOD ≥600 mV, RT= 160 Ωto GND

Maximum Output Frequency

fCLKout_FS RL= 100 ΩGHz

Full VOD Swing (8)(9) Vcco = 2.5 V ± 5%,

differential 0.75 1.0

RT= 91 Ωto GND

Vcco = 3.3 V ± 5%, 1.5 3.1

VOD ≥400 mV, RT= 160 Ωto GND

Maximum Output Frequency

fCLKout_RS RL= 100 ΩGHz

Reduced VOD Swing (8)(9) Vcco = 2.5 V ± 5%,

differential 1.5 2.3

RT= 91 Ωto GND

CLKin: 100 MHz, 59

Slew rate ≥3 V/ns

Vcco = 3.3 V,

Additive RMS Jitter RT= 160 Ωto GND, CLKin: 156.25 MHz,

JitterADD Integration Bandwidth 64 fs

RL= 100 ΩSlew rate ≥2.7 V/ns

1 MHz to 20 MHz (10) differential CLKin: 625 MHz, 30

Slew rate ≥3 V/ns

CLKin: 156.25 MHz,

JSOURCE = 190 fs RMS 20

Vcco = 3.3 V,

Additive RMS Jitter with (10 kHz to 1 MHz)

RT= 160 Ωto GND,

JitterADD LVPECL clock source from fs

RL= 100 ΩCLKin: 156.25 MHz,

LMK03806 (10)(11) differential JSOURCE = 195 fs RMS 51

(12 kHz to 20 MHz)

CLKin: 100 MHz, -162.5

Slew rate ≥3 V/ns

Vcco = 3.3 V,

Noise Floor RT= 160 Ωto GND, CLKin: 156.25 MHz,

Noise Floor -158.1 dBc/Hz

fOFFSET ≥10 MHz(12)(13) RL= 100 ΩSlew rate ≥2.7 V/ns

differential CLKin: 625 MHz, -154.4

Slew rate ≥3 V/ns

DUTY Duty Cycle (8) 50% input clock duty cycle 45 55 %

Vcco - Vcco - Vcco -

VOH Output High Voltage V

1.2 0.9 0.7

TA= 25 °C, DC Measurement, Vcco - Vcco - Vcco -

VOL Output Low Voltage RT= 50 Ωto Vcco - 2 V V

2.0 1.75 1.5

VOD Output Voltage Swing (14) 600 830 1000 mV

Output Rise Time

tR175 300 ps

RT= 160 Ωto GND, Uniform transmission line up to

20% to 80%(15) 10 in. with 50-Ωcharacteristic impedance,

Output Fall Time RL= 100 Ωdifferential, CL≤5 pF

tF175 300 ps

80% to 20%(15)

(8) Specification is ensured by characterization and is not tested in production.

(9) See Typical Performance Characteristics for output operation over frequency.

(10) For the 100 MHz and 156.25 MHz clock input conditions, Additive RMS Jitter (JADD) is calculated using Method #1: JADD = SQRT(JOUT2

- JSOURCE2), where JOUT is the total RMS jitter measured at the output driver and JSOURCE is the RMS jitter of the clock source applied to

CLKin. For the 625 MHz clock input condition, Additive RMS Jitter is approximated using Method #2: JADD = SQRT(2*10dBc/10) /

(2*π*fCLK), where dBc is the phase noise power of the Output Noise Floor integrated from 1 to 20 MHz bandwidth. The phase noise

power can be calculated as: dBc = Noise Floor + 10*log10(20 MHz - 1 MHz). The additive RMS jitter was approximated for 625 MHz

using Method #2 because the RMS jitter of the clock source was not sufficiently low enough to allow practical use of Method #1. Refer

to the “Noise Floor vs. CLKin Slew Rate” and “RMS Jitter vs. CLKin Slew Rate” plots in Typical Performance Characteristics.

(11) 156.25 MHz LVPECL clock source from LMK03806 with 20 MHz crystal reference (crystal part number: ECS-200-20-30BU-DU). Typical

JSOURCE = 190 fs RMS (10 kHz to 1 MHz) and 195 fs RMS (12 kHz to 20 MHz). Refer to the LMK03806 datasheet for more information.

(12) The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is ≥10 MHz, but for lower

frequencies this measurement offset can be as low as 5 MHz due to measurement equipment limitations.

(13) Phase noise floor will degrade as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input

(LVPECL, LVDS) will be less susceptible to degradation in noise floor at lower slew rates due to its common mode noise rejection.

However, it is recommended to use the highest possible input slew rate for differential clocks to achieve optimal noise floor performance

at the device outputs.

(14) See Differential Voltage Measurement Terminology for definition of VID and VOD voltages.

(15) Parameter is specified by design, not tested in production.

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Electrical Characteristics (continued)

Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤TA≤85 °C, CLKin driven

differentially, input slew rate ≥3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, TA

= 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. (1)

Symbol Parameter Conditions Min Typ Max Units

LVDS Outputs (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)

Maximum Output Frequency VOD ≥250 mV,

fCLKout_FS 1.0 1.6 GHz

Full VOD Swing (16)(17) RL= 100 Ωdifferential

Maximum Output Frequency VOD ≥200 mV,

fCLKout_RS 1.5 2.1 GHz

Reduced VOD Swing (16)(17) RL= 100 Ωdifferential

CLKin: 100 MHz, 89

Slew rate ≥3 V/ns

Additive RMS Jitter Vcco = 3.3 V, CLKin: 156.25 MHz,

JitterADD Integration Bandwidth RL= 100 Ω77 fs

Slew rate ≥2.7 V/ns

1 MHz to 20 MHz (18) differential CLKin: 625 MHz, 37

Slew rate ≥3 V/ns

CLKin: 100 MHz, -159.5

Slew rate ≥3 V/ns

Vcco = 3.3 V,

Noise Floor CLKin: 156.25 MHz,

Noise Floor RL= 100 Ω-157.0 dBc/Hz

fOFFSET ≥10 MHz(19)(20) Slew rate ≥2.7 V/ns

differential CLKin: 625 MHz, -152.7

Slew rate ≥3 V/ns

DUTY Duty Cycle (16) 50% input clock duty cycle 45 55 %

VOD Output Voltage Swing (21) 250 400 450 mV

Change in Magnitude of VOD

ΔVOD for Complementary -50 50 mV

TA= 25 °C,

Output States DC Measurement,

VOS Output Offset Voltage 1.125 1.25 1.375 V

RL= 100 Ωdifferential

Change in Magnitude of VOS

ΔVOS for Complementary -35 35 mV

Output States

ISA Output Short Circuit Current TA= 25 °C, -24 24 mA

ISB Single Ended Single ended outputs shorted to GND

Output Short Circuit Current

ISAB Complementary outputs tied together -12 12 mA

Differential

Output Rise Time Uniform transmission line up to 10 in.

tR175 300 ps

20% to 80%(22) with 50-Ωcharacteristic impedance,

RL= 100 Ωdifferential,

Output Fall Time

tF175 300 ps

CL≤5 pF

80% to 20%(22)

(16) Specification is ensured by characterization and is not tested in production.

(17) See Typical Performance Characteristics for output operation over frequency.

(18) For the 100 MHz and 156.25 MHz clock input conditions, Additive RMS Jitter (JADD) is calculated using Method #1: JADD = SQRT(JOUT2

- JSOURCE2), where JOUT is the total RMS jitter measured at the output driver and JSOURCE is the RMS jitter of the clock source applied to

CLKin. For the 625 MHz clock input condition, Additive RMS Jitter is approximated using Method #2: JADD = SQRT(2*10dBc/10) /

(2*π*fCLK), where dBc is the phase noise power of the Output Noise Floor integrated from 1 to 20 MHz bandwidth. The phase noise

power can be calculated as: dBc = Noise Floor + 10*log10(20 MHz - 1 MHz). The additive RMS jitter was approximated for 625 MHz

using Method #2 because the RMS jitter of the clock source was not sufficiently low enough to allow practical use of Method #1. Refer

to the “Noise Floor vs. CLKin Slew Rate” and “RMS Jitter vs. CLKin Slew Rate” plots in Typical Performance Characteristics.

(19) The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is ≥10 MHz, but for lower

frequencies this measurement offset can be as low as 5 MHz due to measurement equipment limitations.

(20) Phase noise floor will degrade as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input

(LVPECL, LVDS) will be less susceptible to degradation in noise floor at lower slew rates due to its common mode noise rejection.

However, it is recommended to use the highest possible input slew rate for differential clocks to achieve optimal noise floor performance

at the device outputs.

(21) See Differential Voltage Measurement Terminology for definition of VID and VOD voltages.

(22) Parameter is specified by design, not tested in production.

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SNAS512G –SEPTEMBER 2011–REVISED MAY 2013

Electrical Characteristics (continued)

Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤TA≤85 °C, CLKin driven

differentially, input slew rate ≥3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, TA

= 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. (1)

Symbol Parameter Conditions Min Typ Max Units

HCSL Outputs (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)

fCLKout Output Frequency Range (23) RL= 50 Ωto GND, CL≤5 pF DC 400 MHz

PCIe Gen 3,

Additive RMS Phase Jitter CLKin: 100 MHz,

JitterADD_PCIe PLL BW = 2–5 MHz, 0.03 0.15 ps

for PCIe 3.0 (23) Slew rate ≥0.6 V/ns

CDR = 10 MHz CLKin: 100 MHz, 77

Additive RMS Jitter Slew rate ≥3 V/ns

Vcco = 3.3 V,

JitterADD Integration Bandwidth fs

RT= 50 Ωto GND CLKin: 156.25 MHz,

1 MHz to 20 MHz (24) 86

Slew rate ≥2.7 V/ns

CLKin: 100 MHz, -161.3

Slew rate ≥3 V/ns

Noise Floor Vcco = 3.3 V,

Noise Floor dBc/Hz

fOFFSET ≥10 MHz(25)(26) RT= 50 Ωto GND CLKin: 156.25 MHz, -156.3

Slew rate ≥2.7 V/ns

DUTY Duty Cycle (23) 50% input clock duty cycle 45 55 %

VOH Output High Voltage 520 810 920 mV

TA= 25 °C, DC Measurement,

RT= 50 Ωto GND

VOL Output Low Voltage -150 0.5 150 mV

Absolute Crossing Voltage

VCROSS 160 350 460 mV

(23)(27) RL= 50 Ωto GND,

CL≤5 pF

Total Variation of VCROSS

ΔVCROSS 140 mV

(23)(27)

Output Rise Time 250 MHz,

tR300 500 ps

20% to 80% (27)(28) Uniform transmission line up to 10 in.

with 50-Ωcharacteristic impedance,

Output Fall Time RL= 50 Ωto GND,

tF300 500 ps

80% to 20% (27)(28) CL≤5 pF

(23) Specification is ensured by characterization and is not tested in production.

(24) For the 100 MHz and 156.25 MHz clock input conditions, Additive RMS Jitter (JADD) is calculated using Method #1: JADD = SQRT(JOUT2

- JSOURCE2), where JOUT is the total RMS jitter measured at the output driver and JSOURCE is the RMS jitter of the clock source applied to

CLKin. For the 625 MHz clock input condition, Additive RMS Jitter is approximated using Method #2: JADD = SQRT(2*10dBc/10) /

(2*π*fCLK), where dBc is the phase noise power of the Output Noise Floor integrated from 1 to 20 MHz bandwidth. The phase noise

power can be calculated as: dBc = Noise Floor + 10*log10(20 MHz - 1 MHz). The additive RMS jitter was approximated for 625 MHz

using Method #2 because the RMS jitter of the clock source was not sufficiently low enough to allow practical use of Method #1. Refer

to the “Noise Floor vs. CLKin Slew Rate” and “RMS Jitter vs. CLKin Slew Rate” plots in Typical Performance Characteristics.

(25) The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is ≥10 MHz, but for lower

frequencies this measurement offset can be as low as 5 MHz due to measurement equipment limitations.

(26) Phase noise floor will degrade as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input

(LVPECL, LVDS) will be less susceptible to degradation in noise floor at lower slew rates due to its common mode noise rejection.

However, it is recommended to use the highest possible input slew rate for differential clocks to achieve optimal noise floor performance

at the device outputs.

(27) AC timing parameters for HCSL or CMOS are dependent on output capacitive loading.

(28) Parameter is specified by design, not tested in production.

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Electrical Characteristics (continued)

Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤TA≤85 °C, CLKin driven

differentially, input slew rate ≥3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, TA

= 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. (1)

Symbol Parameter Conditions Min Typ Max Units

LVCMOS Output (REFout)

fCLKout Output Frequency Range (29) CL≤5 pF DC 250 MHz

Additive RMS Jitter Vcco = 3.3 V, 100 MHz, Input Slew

JitterADD Integration Bandwidth 95 fs

CL≤5 pF rate ≥3 V/ns

1 MHz to 20 MHz (30)

Noise Floor Vcco = 3.3 V, 100 MHz, Input Slew

Noise Floor -159.3 dBc/Hz

fOFFSET ≥10 MHz(31)(32) CL≤5 pF rate ≥3 V/ns

DUTY Duty Cycle (29) 50% input clock duty cycle 45 55 %

Vcco -

VOH Output High Voltage V

0.1

1 mA load

VOL Output Low Voltage 0.1 V

Vcco = 3.3 V 28

Output High Current

IOH mA

(Source) Vcco = 2.5 V 20

Vo = Vcco / 2 Vcco = 3.3 V 28

IOL Output Low Current (Sink) mA

Vcco = 2.5 V 20

Output Rise Time 250 MHz,

tR225 400 ps

20% to 80% (33)(34) Uniform transmission line up to 10 in.

with 50-Ωcharacteristic impedance,

Output Fall Time RL= 50 Ωto GND,

tF225 400 ps

80% to 20% (33)(34) CL≤5 pF

tEN Output Enable Time (35) 3 cycles

CL≤5 pF

tDIS Output Disable Time (35) 3 cycles

(29) Specification is ensured by characterization and is not tested in production.

(30) For the 100 MHz and 156.25 MHz clock input conditions, Additive RMS Jitter (JADD) is calculated using Method #1: JADD = SQRT(JOUT2

- JSOURCE2), where JOUT is the total RMS jitter measured at the output driver and JSOURCE is the RMS jitter of the clock source applied to

CLKin. For the 625 MHz clock input condition, Additive RMS Jitter is approximated using Method #2: JADD = SQRT(2*10dBc/10) /

(2*π*fCLK), where dBc is the phase noise power of the Output Noise Floor integrated from 1 to 20 MHz bandwidth. The phase noise

power can be calculated as: dBc = Noise Floor + 10*log10(20 MHz - 1 MHz). The additive RMS jitter was approximated for 625 MHz

using Method #2 because the RMS jitter of the clock source was not sufficiently low enough to allow practical use of Method #1. Refer

to the “Noise Floor vs. CLKin Slew Rate” and “RMS Jitter vs. CLKin Slew Rate” plots in Typical Performance Characteristics.

(31) The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is ≥10 MHz, but for lower

frequencies this measurement offset can be as low as 5 MHz due to measurement equipment limitations.

(32) Phase noise floor will degrade as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input

(LVPECL, LVDS) will be less susceptible to degradation in noise floor at lower slew rates due to its common mode noise rejection.

However, it is recommended to use the highest possible input slew rate for differential clocks to achieve optimal noise floor performance

at the device outputs.

(33) AC timing parameters for HCSL or CMOS are dependent on output capacitive loading.

(34) Parameter is specified by design, not tested in production.

(35) Output Enable Time is the number of input clock cycles it takes for the output to be enabled after REFout_EN is pulled high. Similarly,

Output Disable Time is the number of input clock cycles it takes for the output to be disabled after REFout_EN is pulled low. The

REFout_EN signal should have an edge transition much faster than that of the input clock period for accurate measurement.

Product Folder Links: LMK00301

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SNAS512G –SEPTEMBER 2011–REVISED MAY 2013

Electrical Characteristics (continued)

Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤TA≤85 °C, CLKin driven

differentially, input slew rate ≥3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, TA

= 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. (1)

Symbol Parameter Conditions Min Typ Max Units

Propagation Delay and Output Skew

RT= 160 Ωto GND,

Propagation Delay

tPD_PECL RL= 100 Ωdifferential, 180 360 540 ps

CLKin-to-LVPECL(36) CL≤5 pF

Propagation Delay RL= 100 Ωdifferential,

tPD_LVDS 200 400 600 ps

CLKin-to-LVDS(36) CL≤5 pF

Propagation Delay RT= 50 Ωto GND,

tPD_HCSL 295 590 885 ps

CLKin-to-HCSL (37)(36) CL≤5 pF

Vcco = 3.3 V 900 1475 2300

Propagation Delay

tPD_CMOS CL≤5 pF ps

CLKin-to-LVCMOS (36)(37) Vcco = 2.5 V 1000 1550 2700

Output Skew

tSK(O) LVPECL/LVDS/HCSL 30 50 ps

Skew specified between any two CLKouts with the

(37)(38)(39) same buffer type. Load conditions per output type

Part-to-Part Output Skew are the same as propagation delay specifications.

tSK(PP) LVPECL/LVDS/HCSL 80 120 ps

(36)(37)(39)

(36) Parameter is specified by design, not tested in production.

(37) AC timing parameters for HCSL or CMOS are dependent on output capacitive loading.

(38) Specification is ensured by characterization and is not tested in production.

(39) Output skew is the propagation delay difference between any two outputs with identical output buffer type and equal loading while

operating at the same supply voltage and temperature conditions.

Product Folder Links: LMK00301

VOH

VOL

GND

VOD = | VOH - VOL | VSS = 2·VOD

VOD Definition VSS Definition for Output

Non-Inverting Clock

Inverting Clock

VOD VSS

VOS

VIH

VIL

GND

VID = | VIH ± VIL | VSS = 2·VID

VID Definition VSS Definition for Input

Non-Inverting Clock

Inverting Clock

VID VSS

VCM

LMK00301

SNAS512G –SEPTEMBER 2011–REVISED MAY 2013

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Measurement Definitions

Differential Voltage Measurement Terminology

The differential voltage of a differential signal can be described by two different definitions causing confusion

when reading datasheets or communicating with other engineers. This section will address the measurement and

description of a differential signal so that the reader will be able to understand and discern between the two

different definitions when used.

The first definition used to describe a differential signal is the absolute value of the voltage potential between the

inverting and non-inverting signal. The symbol for this first measurement is typically VID or VOD depending on if

an input or output voltage is being described.

The second definition used to describe a differential signal is to measure the potential of the non-inverting signal

with respect to the inverting signal. The symbol for this second measurement is VSS and is a calculated

parameter. Nowhere in the IC does this signal exist with respect to ground, it only exists in reference to its

differential pair. VSS can be measured directly by oscilloscopes with floating references, otherwise this value can

be calculated as twice the value of VOD as described in the first description.

Figure 2 illustrates the two different definitions side-by-side for inputs and Figure 3 illustrates the two different

definitions side-by-side for outputs. The VID (or VOD) definition show the DC levels, VIH and VOL (or VOH and VOL),

that the non-inverting and inverting signals toggle between with respect to ground. VSS input and output

definitions show that if the inverting signal is considered the voltage potential reference, the non-inverting signal

voltage potential is now increasing and decreasing above and below the non-inverting reference. Thus the peak-

to-peak voltage of the differential signal can be measured.

VID and VOD are often defined as volts (V) and VSS is often defined as volts peak-to-peak (VPP).

Figure 2. Two Different Definitions for Differential Input Signals

Figure 3. Two Different Definitions for Differential Output Signals

Refer to Application Note AN-912 (literature number SNLA036), Common Data Transmission Parameters and

their Definitions, for more information.

Product Folder Links: LMK00301

0.00 0.25 0.50 0.75 1.00

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

OUTPUT SWING (V)

TIME (ns)

0.00 0.25 0.50 0.75 1.00

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

OUTPUT SWING (V)

TIME (ns)

0.0 2.5 5.0 7.5 10.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

OUTPUT SWING (V)

TIME (ns)

0.0 2.5 5.0 7.5 10.0

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

OUTPUT SWING (V)

TIME (ns)

100 1000 10000

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

OUTPUT SWING (V)

FREQUENCY (MHz)

Vcco=2.5 V, Rterm=91 

Vcco=3.3 V, Rterm=160 

100 1000 10000

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

OUTPUT SWING (V)

FREQUENCY (MHz)

LMK00301

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SNAS512G –SEPTEMBER 2011–REVISED MAY 2013

Typical Performance Characteristics

Unless otherwise specified: Vcc = 3.3 V, Vcco = 3.3 V, TA= 25 °C, CLKin driven differentially, input slew rate ≥3 V/ns.

LVPECL Output Swing (VOD) LVDS Output Swing (VOD)

vs. vs.

Frequency Frequency

Figure 4. Figure 5.

LVPECL Output Swing @ 156.25 MHz LVDS Output Swing @ 156.25 MHz

Figure 6. Figure 7.

LVPECL Output Swing @ 1.5 GHz LVDS Output Swing @ 1.5 GHz

Figure 8. Figure 9.

Product Folder Links: LMK00301

0.5 1.0 1.5 2.0 2.5 3.0 3.5

-165

-160

-155

-150

-145

-140

-135

NOISE FLOOR (dBc/Hz)

DIFFERENTIAL INPUT SLEW RATE (V/ns)

Fclk=625 MHz

Foffset=20 MHz

LVPECL

LVDS

CLKin Source

0.5 1.0 1.5 2.0 2.5 3.0 3.5

100

150

200

250

300

350

400

RMS JITTER (fs)

DIFFERENTIAL INPUT SLEW RATE (V/ns)

Fclk=100 MHz

Int. BW=1-20 MHz

LVPECL

LVDS

HCSL

LVCMOS

CLKin Source

0.5 1.0 1.5 2.0 2.5 3.0 3.5

-170

-165

-160

-155

-150

-145

-140

NOISE FLOOR (dBc/Hz)

DIFFERENTIAL INPUT SLEW RATE (V/ns)

Fclk=100 MHz

Foffset=20 MHz

LVPECL

LVDS

HCSL

LVCMOS

CLKin Source

0.5 1.0 1.5 2.0 2.5 3.0 3.5

-165

-160

-155

-150

-145

-140

-135

NOISE FLOOR (dBc/Hz)

DIFFERENTIAL INPUT SLEW RATE (V/ns)

Fclk=156.25 MHz

Foffset=20 MHz

LVPECL

LVDS

HCSL

CLKin Source

012345

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

OUTPUT SWING (V)

TIME (ns)

0123456

-1.00

-0.75

-0.50

-0.25

0.00

0.25

0.50

0.75

1.00

OUTPUT SWING (V)

TIME (ns)

Vcco=3.3 V, AC coupled, 50load

Vcco=2.5 V, AC coupled, 50load

LMK00301

SNAS512G –SEPTEMBER 2011–REVISED MAY 2013

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Typical Performance Characteristics (continued)

Unless otherwise specified: Vcc = 3.3 V, Vcco = 3.3 V, TA= 25 °C, CLKin driven differentially, input slew rate ≥3 V/ns.

HCSL Output Swing @ 250 MHz LVCMOS Output Swing @ 250 MHz

Figure 10. Figure 11.

Noise Floor vs. CLKin Slew Rate @ 100 MHz Noise Floor vs. CLKin Slew Rate @ 156.25 MHz

Figure 12. Figure 13.

Noise Floor vs. CLKin Slew Rate @ 625 MHz RMS Jitter vs. CLKin Slew Rate @ 100 MHz

Figure 14. Figure 15.

Product Folder Links: LMK00301

-50 -25 0 25 50 75 100

250

350

450

550

650

750

850

1350

1450

1550

1650

1750

1850

1950

CLKout PROPAGATION DELAY (ps)

TEMPERATURE (°C)

REFout PROPAGATION DELAY (ps)

Right Y-axis plot

LVPECL (0.35 ps/°C)

LVDS (0.35 ps/°C)

HCSL (0.35 ps/°C)

LVCMOS (2.2 ps/°C)

.1 1 10

-90

-85

-80

-75

-70

-65

-60

-55

-50

RIPPLE INDUCED SPUR LEVEL (dBc)

RIPPLE FREQUENCY (MHz)

Fclk=156.25 MHz

Vcco Ripple=100 mVpp

LVPECL

LVDS

HCSL

.1 1 10

-90

-85

-80

-75

-70

-65

-60

-55

-50

RIPPLE INDUCED SPUR LEVEL (dBc)

RIPPLE FREQUENCY (MHz)

Fclk=312.5 MHz

Vcco Ripple=100 mVpp

LVPECL

LVDS

HCSL

0.5 1.0 1.5 2.0 2.5 3.0 3.5

100

150

200

250

300

350

400

450

500

RMS JITTER (fs)

DIFFERENTIAL INPUT SLEW RATE (V/ns)

Fclk=156.25 MHz

Int. BW=1-20 MHz

LVPECL

LVDS

HCSL

CLKin Source

0.5 1.0 1.5 2.0 2.5 3.0 3.5

100

125

150

175

200

RMS JITTER (fs)

DIFFERENTIAL INPUT SLEW RATE (V/ns)

Fclk=625 MHz

Int. BW=1-20 MHz

LVPECL

LVDS

CLKin Source

LMK00301

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SNAS512G –SEPTEMBER 2011–REVISED MAY 2013

Typical Performance Characteristics (continued)

Unless otherwise specified: Vcc = 3.3 V, Vcco = 3.3 V, TA= 25 °C, CLKin driven differentially, input slew rate ≥3 V/ns.

RMS Jitter vs. CLKin Slew Rate @ 156.25 MHz RMS Jitter vs. CLKin Slew Rate @ 625 MHz

Figure 16. Figure 17.

PSRR vs. Ripple Frequency @ 156.25 MHz PSRR vs. Ripple Frequency @ 312.5 MHz

Figure 18. Figure 19.

Propagation Delay vs. Temperature LVPECL Phase Noise @ 100 MHz

Figure 20. Figure 21.

Product Folder Links: LMK00301

0 500 1k 1.5k 2k 2.5k 3k 3.5k 4k

100

125

150

175

200

CRYSTAL POWER DISSIPATION (W)

RLIM()

20 MHz Crystal

40 MHz Crystal

10 100 1k 10k 100k 1M 10M

-180

-160

-140

-120

-100

-80

-60

PHASE NOISE (dBc/Hz)

OFFSET FREQUENCY (Hz)

20 MHz Crystal, Rlim = 1.5 k

40 MHz Crystal, Rlim = 1.0 k

LMK00301

SNAS512G –SEPTEMBER 2011–REVISED MAY 2013

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Typical Performance Characteristics (continued)

Unless otherwise specified: Vcc = 3.3 V, Vcco = 3.3 V, TA= 25 °C, CLKin driven differentially, input slew rate ≥3 V/ns.

LVDS Phase Noise @ 100 MHz HCSL Phase Noise @ 100 MHz

Figure 22. Figure 23.

Crystal Power Dissipation

vs.

RLIM LVDS Phase Noise in Crystal Mode

Figure 24. Figure 25.

(1) The typical RMS jitter values in the plots show the total output RMS jitter (JOUT) for each output buffer type and the

source clock RMS jitter (JSOURCE). From these values, the Additive RMS Jitter can be calculated as: JADD =

SQRT(JOUT2– JSOURCE2).

(2) 20 MHz crystal characteristics: Abracon ABL series, AT cut, CL= 18 pF , C0= 4.4 pF measured (7 pF max), ESR =

8.5 Ωmeasured (40 Ωmax), and Drive Level = 1 mW max (100 µW typical).

(3) 40 MHz crystal characteristics: Abracon ABLS2 series, AT cut, CL= 18 pF , C0= 5 pF measured (7 pF max), ESR =

5Ωmeasured (40 Ωmax), and Drive Level = 1 mW max (100 µW typical).

Product Folder Links: LMK00301

0.1 PF

50:Trace

CMOS

Driver

VCC RB1

RB2

VCC

LMK

Input

50:

VO,PP VO,PP/2

VBB ~ (VO,PP/2) x 0.5

0.1 PF

50:Trace

50:

LMK

Input

0.1 PF

CMOS

Driver

LMK00301

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SNAS512G –SEPTEMBER 2011–REVISED MAY 2013

APPLICATION INFORMATION

Driving the Clock Inputs

The LMK00301 has two universal inputs (CLKin0/CLKin0* and CLKin1/CLKin1*) that can accept AC- or DC-

coupled 3.3V/2.5V LVPECL, LVDS, CML, SSTL, and other differential and single-ended signals that meet the

input requirements specified in Electrical Characteristics. The device can accept a wide range of signals due to

its wide input common mode voltage range (VCM ) and input voltage swing (VID) / dynamic range. For 50% duty

cycle and DC-balanced signals, AC coupling may also be employed to shift the input signal to within the VCM

range. Refer to Termination and Use of Clock Drivers for signal interfacing and termination techniques.

To achieve the best possible phase noise and jitter performance, it is mandatory for the input to have high slew

rate of 3 V/ns (differential) or higher. Driving the input with a lower slew rate will degrade the noise floor and jitter.

For this reason, a differential signal input is recommended over single-ended because it typically provides higher

slew rate and common-mode-rejection. Refer to the “Noise Floor vs. CLKin Slew Rate” and “RMS Jitter vs. CLKin

Slew Rate” plots in Typical Performance Characteristics.

While it is recommended to drive the CLKin/CLKin* pair with a differential signal input, it is possible to drive it

with a single-ended clock provided it conforms to the Single-Ended Input specifications for CLKin pins listed in

the Electrical Characteristics. For large single-ended input signals, such as 3.3V or 2.5V LVCMOS, a 50 Ωload

resistor should be placed near the input for signal attenuation to prevent input overdrive as well as for line

termination to minimize reflections. Again, the single-ended input slew rate should be as high as possible to

minimize performance degradation. The CLKin input has an internal bias voltage of about 1.4 V, so the input can

be AC coupled as shown in Figure 26. The output impedance of the LVCMOS driver plus Rs should be close to

50 Ωto match the characteristic impedance of the transmission line and load termination.

Figure 26. Single-Ended LVCMOS Input, AC Coupling

A single-ended clock may also be DC coupled to CLKinX as shown in Figure 27. A 50-Ωload resistor should be

placed near the CLKinX input for signal attenuation and line termination. Because half of the single-ended swing

of the driver (VO,PP / 2) drives CLKinX, CLKinX* should be externally biased to the midpoint voltage of the

attenuated input swing ((VO,PP / 2) × 0.5). The external bias voltage should be within the specified input common

voltage (VCM) range. This can be achieved using external biasing resistors in the kΩrange (RB1 and RB2) or

another low-noise voltage reference. This will ensure the input swing crosses the threshold voltage at a point

where the input slew rate is the highest.

Figure 27. Single-Ended LVCMOS Input, DC Coupling

with Common Mode Biasing

Product Folder Links: LMK00301

LMK00301

OSCin

OSCout

XTAL

RLIM

0.1 PF

50:Trace

50:

CMOS

Driver

0.1 PF

LMK00301

OSCin

OSCout

LMK00301

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If the crystal oscillator circuit is not used, it is possible to drive the OSCin input with an single-ended external

clock as shown in Figure 28. The input clock should be AC coupled to the OSCin pin, which has an internally-

generated input bias voltage, and the OSCout pin should be left floating. While OSCin provides an alternative

input to multiplex an external clock, it is recommended to use either universal input (CLKinX) since it offers

higher operating frequency, better common mode and power supply noise rejection, and greater performance

over supply voltage and temperature variations.

Figure 28. Driving OSCin with a Single-Ended Input

Crystal Interface

The LMK00301 has an integrated crystal oscillator circuit that supports a fundamental mode, AT-cut crystal. The

crystal interface is shown in Figure 29.

Figure 29. Crystal Interface

The load capacitance (CL) is specific to the crystal, but usually on the order of 18 - 20 pF. While CLis specified

for the crystal, the OSCin input capacitance (CIN = 1 pF typical) of the device and PCB stray capacitance (CSTRAY

~ 1~3 pF) can affect the discrete load capacitor values, C1and C2.

For the parallel resonant circuit, the discrete capacitor values can be calculated as follows:

CL= (C1* C2) / (C1+ C2) + CIN + CSTRAY (1)

Typically, C1= C2for optimum symmetry, so Equation 1 can be rewritten in terms of C1only:

CL= C12/ (2 * C1) + CIN + CSTRAY (2)

Finally, solve for C1:

C1= (CL– CIN – CSTRAY)*2 (3)

Electrical Characteristics provides crystal interface specifications with conditions that ensure start-up of the

crystal, but it does not specify crystal power dissipation. The designer will need to ensure the crystal power

dissipation does not exceed the maximum drive level specified by the crystal manufacturer. Overdriving the

crystal can cause premature aging, frequency shift, and eventual failure. Drive level should be held at a sufficient

level necessary to start-up and maintain steady-state operation.

The power dissipated in the crystal, PXTAL, can be computed by:

PXTAL = IRMS2* RESR*(1 + C0/CL)2

where

• IRMS is the RMS current through the crystal.

• RESR is the max. equivalent series resistance specified for the crystal

• CLis the load capacitance specified for the crystal

• C0is the min. shunt capacitance specified for the crystal (4)

Product Folder Links: LMK00301

CLKoutX

CLKoutX*

HCSL

Receiver

50:

50:Traces

50:

HCSL

Driver

CLKoutX

CLKoutX*

LVDS

Receiver

100:

100:Trace

(Differential)

LVDS

Driver

LMK00301

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SNAS512G –SEPTEMBER 2011–REVISED MAY 2013

IRMS can be measured using a current probe (e.g. Tektronix CT-6 or equivalent) placed on the leg of the crystal

connected to OSCout with the oscillation circuit active.

As shown in Figure 29, an external resistor, RLIM, can be used to limit the crystal drive level, if necessary. If the

power dissipated in the selected crystal is higher than the drive level specified for the crystal with RLIM shorted,

then a larger resistor value is mandatory to avoid overdriving the crystal. However, if the power dissipated in the

crystal is less than the drive level with RLIM shorted, then a zero value for RLIM can be used. As a starting point, a

suggested value for RLIM is 1.5 kΩ.

Termination and Use of Clock Drivers

When terminating clock drivers keep in mind these guidelines for optimum phase noise and jitter performance:

• Transmission line theory should be followed for good impedance matching to prevent reflections.

• Clock drivers should be presented with the proper loads.

– LVDS outputs are current drivers and require a closed current loop.

– HCSL drivers are switched current outputs and require a DC path to ground via 50 Ωtermination.

– LVPECL outputs are open emitter and require a DC path to ground.

• Receivers should be presented with a signal biased to their specified DC bias level (common mode voltage)

for proper operation. Some receivers have self-biasing inputs that automatically bias to the proper voltage

level; in this case, the signal should normally be AC coupled.

It is possible to drive a non-LVPECL or non-LVDS receiver with a LVDS or LVPECL driver as long as the above

guidelines are followed. Check the datasheet of the receiver or input being driven to determine the best

termination and coupling method to be sure the receiver is biased at the optimum DC voltage (common mode

voltage).

Termination for DC Coupled Differential Operation

For DC coupled operation of an LVDS driver, terminate with 100 Ωas close as possible to the LVDS receiver as

shown in Figure 30.

Figure 30. Differential LVDS Operation, DC Coupling,

No Biasing by the Receiver

For DC coupled operation of an HCSL driver, terminate with 50 Ωto ground near the driver output as shown in

Figure 31. Series resistors, Rs, may be used to limit overshoot due to the fast transient current. Because HCSL

drivers require a DC path to ground, AC coupling is not allowed between the output drivers and the 50 Ω

termination resistors.

Figure 31. HCSL Operation, DC Coupling

Product Folder Links: LMK00301

CLKoutX

CLKoutX*

LVPECL

Receiver

RPU

100:Trace

(Differential)

RPU

Vcco

LVPECL

Driver

RPD

RPU RPD

Vcco VTT

3.3V

2.5V

120:

250:

82:

62.5:

~1.3V

0.5V

CLKoutX

CLKoutX*

LVPECL

Receiver

50:

100:Trace

(Differential)

50:

Vcco - 2V

LVPECL

Driver

LMK00301

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For DC coupled operation of an LVPECL driver, terminate with 50 Ωto Vcco - 2 V as shown in Figure 32.

Alternatively terminate with a Thevenin equivalent circuit as shown in Figure 33 for Vcco (output driver supply

voltage) = 3.3 V and 2.5 V. In the Thevenin equivalent circuit, the resistor dividers set the output termination

voltage (VTT) to Vcco - 2 V.

Figure 32. Differential LVPECL Operation, DC Coupling

Figure 33. Differential LVPECL Operation, DC Coupling, Thevenin Equivalent

Termination for AC Coupled Differential Operation

AC coupling allows for shifting the DC bias level (common mode voltage) when driving different receiver

standards. Since AC coupling prevents the driver from providing a DC bias voltage at the receiver, it is important

to ensure the receiver is biased to its ideal DC level.

When driving differential receivers with an LVDS driver, the signal may be AC coupled by adding DC blocking

capacitors; however the proper DC bias point needs to be established at both the driver side and the receiver

side. The recommended termination scheme depends on whether the differential receiver has integrated

termination resistors or not.

When driving a differential receiver without internal 100 Ωdifferential termination, the AC coupling capacitors

should be placed between the load termination resistor and the receiver to allow a DC path for proper biasing of

the LVDS driver. This is shown in Figure 34(a.) The load termination resistor and AC coupling capacitors should

be placed as close as possible to the receiver inputs to minimize stub length. The receiver can be biased

internally or externally to a reference voltage within the receiver’s common mode input range through resistors in

the kilo-ohm range.

Product Folder Links: LMK00301

LVDS

Driver

CLKoutX

CLKoutX*

0.1 PF

100:Trace

(Differential)

100:

Receiver with internal

termination and biasing

through 50: resistors

50:

Vbias

(b) LVDS DC termination with AC coupling at source and internal termination at load.

Double termination at source and load will reduce swing by half.

Source termination for

proper DC bias of the driver

LVDS

Driver

CLKoutX

CLKoutX*

0.1 PF

100:Trace

(Differential) 100:

Receiver biasing can be

internal or external through

resistors in K: range

(a) LVDS DC termination with AC coupling at load

Vbias

LMK00301

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SNAS512G –SEPTEMBER 2011–REVISED MAY 2013

When driving a differential receiver with internal 100 Ωdifferential termination, a source termination resistor

should be placed before the AC coupling capacitors for proper DC biasing of the driver as shown in Figure 34(b.)

However, with a 100 Ωresistor at the source and the load (i.e. double terminated), the equivalent resistance

seen by the LVDS driver is 50 Ωwhich causes the effective signal swing at the input to be reduced by half. If a

self-terminated receiver requires input swing greater than 250 mVpp (differential) as well as AC coupling to its

inputs, then the LVDS driver with the double-terminated arrangement in Figure 34(b.) may not meet the minimum

input swing requirement; alternatively, the LVPECL or HCSL output driver format with AC coupling is

recommended to meet the minimum input swing required by the self-terminated receiver.

When using AC coupling with LVDS outputs, there may be a startup delay observed in the clock output due to

capacitor charging. The examples in Figure 34 use 0.1 μF capacitors, but this value may be adjusted to meet the

startup requirements for the particular application.

Figure 34. Differential LVDS Operation with AC Coupling to Receivers

(a.) Without Internal 100 ΩTermination

(b.) With Internal 100 ΩTermination

LVPECL drivers require a DC path to ground. When AC coupling an LVPECL signal use 160 Ωemitter resistors

(or 91 Ωfor Vcco = 2.5 V) close to the LVPECL driver to provide a DC path to ground as shown in Figure 38. For

proper receiver operation, the signal should be biased to the DC bias level (common mode voltage) specified by

the receiver. The typical DC bias voltage (common mode voltage) for LVPECL receivers is 2 V. Alternatively, a

Thevenin equivalent circuit forms a valid termination as shown in Figure 35 for Vcco = 3.3 V and 2.5 V. Note: this

Thevenin circuit is different from the DC coupled example in Figure 33, since the voltage divider is setting the

input common mode voltage of the receiver.

Product Folder Links: LMK00301

CLKoutX

CLKoutX*

(unused)

RPD

50:Trace

RPU

Load

Vcco

RPD

RPU

Vcco

LVPECL

Driver

RPU RPD

Vcco VTT

3.3V

2.5V

120:

250:

82:

62.5:

~1.3V

0.5V

CLKoutX

CLKoutX* 50:

50:Trace

50:

Load

Vcco - 2V

LVPECL

Driver

CLKoutX

CLKoutX*

0.1 PF

0.1 PFLVPECL

Reciever

100:Trace

(Differential)

RPU

RPD

Vcco

RPU

RPD

Vcco

LVPECL

Driver

RPU RPD

Vcco VBB

3.3V

2.5V

82:

62.5:

120:

250:

160:

91:

LMK00301

SNAS512G –SEPTEMBER 2011–REVISED MAY 2013

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Figure 35. Differential LVPECL Operation, AC Coupling,

Thevenin Equivalent

Termination for Single-Ended Operation

A balun can be used with either LVDS or LVPECL drivers to convert the balanced, differential signal into an

unbalanced, single-ended signal.

It is possible to use an LVPECL driver as one or two separate 800 mV p-p signals. When DC coupling one of the

LMK00301 LVPECL driver of a CLKoutX/CLKoutX* pair, be sure to properly terminate the unused driver. When

DC coupling on of the LMK00301 LVPECL drivers, the termination should be 50 Ωto Vcco - 2 V as shown in

Figure 36. The Thevenin equivalent circuit is also a valid termination as shown in Figure 37 for Vcco = 3.3 V.

Figure 36. Single-Ended LVPECL Operation, DC Coupling

Figure 37. Single-Ended LVPECL Operation, DC Coupling, Thevenin Equivalent

Product Folder Links: LMK00301

CLKoutX

CLKoutX*

0.1 PF

50:Trace

50:

Load

50:

LVPECL

Driver

Vcco

3.3V

2.5V

160:

91:

LMK00301

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SNAS512G –SEPTEMBER 2011–REVISED MAY 2013

When AC coupling an LVPECL driver use a 160 Ωemitter resistor (or 91 Ωfor Vcco = 2.5 V) to provide a DC

path to ground and ensure a 50 Ωtermination with the proper DC bias level for the receiver. The typical DC bias

voltage for LVPECL receivers is 2 V. If the companion driver is not used, it should be terminated with either a

proper AC or DC termination. This latter example of AC coupling a single-ended LVPECL signal can be used to

measure single-ended LVPECL performance using a spectrum analyzer or phase noise analyzer. When using

most RF test equipment no DC bias point (0 VDC) is required for safe and proper operation. The internal 50 Ω

termination the test equipment correctly terminates the LVPECL driver being measured as shown in Figure 38.

When using only one LVPECL driver of a CLKoutX/CLKoutX* pair, be sure to properly terminated the unused

driver.

Figure 38. Single-Ended LVPECL Operation, AC Coupling

Power Supply and Thermal Considerations

Current Consumption and Power Dissipation Calculations

The current consumption values specified in Electrical Characteristics can be used to calculate the total power

dissipation and IC power dissipation for any device configuration. The total VCC core supply current (ICC_TOTAL)

can be calculated using Equation 5:

ICC_TOTAL = ICC_CORE + ICC_BANK_A + ICC_BANK_B + ICC_CMOS

where

• ICC_CORE is the current for core logic and input blocks and depends on selected input (CLKinX or OSCin).

• ICC_BANK_A is the current for Bank A and depends on output type (ICC_PECL, ICC_LVDS, ICC_HCSL, or 0 mA if

disabled).

• ICC_BANK_B is the current for Bank B and depends on output type (ICC_PECL, ICC_LVDS, ICC_HCSL, or 0 mA if

disabled).

• ICC_CMOS is the current for the LVCMOS output (or 0 mA if REFout is disabled). (5)

Since the output supplies (VCCOA, VCCOB, VCCOC) can be powered from 3 independent voltages, the respective

output supply currents (ICCO_BANK_A, ICCO_BANK_B, ICCO_CMOS) should be calculated separately.

ICCO_BANK for either Bank A or B can be directly taken from the corresponding output supply current specification

(ICCO_PECL, ICCO_LVDS, or ICCO_HCSL)provided the output loading matches the specified conditions. Otherwise,

ICCO_BANK should be calculated as follows:

ICCO_BANK = IBANK_BIAS + (N * IOUT_LOAD)

where

• IBANK_BIAS is the output bank bias current (fixed value).

• IOUT_LOAD is the DC load current per loaded output pair.

• N is the number of loaded output pairs in the bank (N = 0 to 5). (6)

Table 5 shows the typical IBANK_BIAS values and IOUT_LOAD expressions for the 3 differential output types.

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For LVPECL, it is possible to use a larger termination resistor (RT) to ground instead of terminating with 50 Ωto

VTT = Vcco - 2 V; this technique is commonly used to eliminate the extra termination voltage supply (VTT) and

potentially reduce device power dissipation at the expense of lower output swing. For example, when Vcco is 3.3

V, a RTvalue of 160 Ωto ground will eliminate the 1.3 V termination supply without sacrificing much output

swing. In this case, the typical IOUT_LOAD is 25 mA, so ICCO_PECL for a fully-loaded bank reduces to 158 mA (vs.

165 mA with 50 Ωresistors to Vcco - 2 V).

Table 5. Typical Output Bank Bias and Load Currents

Current Parameter LVPECL LVDS HCSL

IBANK_BIAS 33 mA 34 mA 6 mA

IOUT_LOAD (VOH - VTT)/RT+ (VOL - VTT)/RT0 mA (No DC load current) VOH/RT

Once the current consumption is calculated or known for each supply, the total power dissipation (PTOTAL) can be

calculated as:

PTOTAL = (VCC*ICC_TOTAL) + (VCCOA*ICCO_BANK_A) + (VCCOB*ICCO_BANK_B) + (VCCOC*ICCO_CMOS)(7)

If the device configuration has LVPECL or HCSL outputs, then it is also necessary to calculate the power

dissipated in any termination resistors (PRT_ PECL and PRT_HCSL) and in any termination voltages (PVTT). The

external power dissipation values can be calculated as follows:

PRT_PECL (per LVPECL pair) = (VOH - VTT)2/RT+ (VOL - VTT)2/RT(8)

PVTT_PECL (per LVPECL pair) = VTT * [(VOH - VTT)/RT+ (VOL - VTT)/RT](9)

PRT_HCSL (per HCSL pair) = VOH2/ RT(10)

Finally, the IC power dissipation (PDEVICE) can be computed by subtracting the external power dissipation values

from PTOTAL as follows:

PDEVICE = PTOTAL - N1*(PRT_PECL + PVTT_PECL)-N2*PRT_HCSL

where

• N1is the number of LVPECL output pairs with termination resistors to VTT (usually Vcco - 2 V or GND).

• N2is the number of HCSL output pairs with termination resistors to GND. (11)

Power Dissipation Example #1: Separate Vcc and Vcco Supplies with Unused Outputs

This example shows how to calculate IC power dissipation for a configuration with separate VCC and VCCO

supplies and unused outputs. Because some outputs are not used, the ICCO_PECL value specified in Electrical

Characteristics cannot be used directly, and output bank current (ICCO_BANK) should be calculated to accurately

estimate the IC power dissipation.

• VCC = 3.3 V, VCCOA = 3.3 V, VCCOB = 2.5 V. Typical ICC and ICCO values.

• CLKin0/CLKin0* input is selected.

• Bank A is configured for LVPECL: 4 pairs used with RT= 50 Ωto VT= Vcco - 2 V (1 pair unused).

• Bank B is configured for LVDS: 3 pairs used with RL= 100 Ωdifferential (2 pairs unused).

• REFout is disabled.

• TA= 85 °C

Using the current and power calculations from the previous section, we can compute PTOTAL and PDEVICE.

• From Equation 5: ICC_TOTAL =8.5mA+20mA+26mA+0mA=54.5mA

• From Table 5: IOUT_LOAD (LVPECL) = (1.6 V - 0.5 V)/50 Ω+ (0.75 V - 0.5 V)/50 Ω= 27 mA

• From Equation 6: ICCO_BANK_A = 33 mA + (4 * 27 mA) = 141 mA

• From Equation 7: PTOTAL = (3.3 V * 54.5 mA) + (3.3 V * 141 mA) + (2.5 V * 34 mA)] = 730 mW

• From Equation 8: PRT_PECL = ((2.4 V - 1.3 V)2/50 Ω) + ((1.55 V - 1.3 V)2/50 Ω) = 25.5 mW (per output pair)

• From Equation 9: PVTT_PECL = 0.5 V * [ ((2.4 V - 1.3 V) / 50 Ω) + ((1.55 V - 1.3 V) / 50 Ω) ] = 13.5 mW (per

output pair)

• From Equation 10: PRT_HCSL = 0 mW (no HCSL outputs)

• From Equation 11: PDEVICE = 730 mW - (4 * (25.5 mW + 13.5 mW)) - 0 mW = 574 mW

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In this example, the IC device will dissipate about 574 mW or 79% of the total power (730 mW), while the

remaining 21% will be dissipated in the emitter resistors (102 mW for 4 pairs) and termination voltage (54 mW

into Vcco - 2 V).

Based on the thermal resistance junction-to-case (θJA) of 28.5 °C/W, the estimated die junction temperature

would be about 16.4 °C above ambient, or 101.4 °C when TA= 85 °C.

Power Dissipation Example #2: Worst-Case Dissipation

This example shows how to calculate IC power dissipation for a configuration to estimate worst-case power

dissipation. In this case, the maximum supply voltage and supply current values specified in Electrical

Characteristics are used.

• Max VCC = VCCO = 3.465 V. Max ICC and ICCO values.

• CLKin0/CLKin0* input is selected.

• Banks A and B are configured for LVPECL: all outputs terminated with 50 Ωto VT= Vcco - 2 V.

• REFout is enabled with 5 pF load.

• TA= 85 °C

Using the maximum supply current and power calculations from the previous section, we can compute PTOTAL

and PDEVICE.

• From Equation 5: ICC_TOTAL = 10.5 mA + 27 mA + 27 mA + 5.5 mA = 70 mA

• From ICCO_PECL max spec: ICCO_BANK_A = ICCO_BANK_B = 197 mA

• From Equation 7: PTOTAL = 3.465 V * (70 mA + 197 mA + 197 mA + 10 mA) = 1642.4 mW

• From Equation 8: PRT_PECL = ((2.57 V - 1.47 V)2/50 Ω) + ((1.72 V - 1.47 V)2/50 Ω) = 25.5 mW (per output pair)

• From Equation 9: PVTT_PECL = 1.47 V * [ ((2.57 V - 1.47 V) / 50 Ω) + ((1.72 V - 1.47 V) / 50 Ω) ] = 39.5 mW

(per output pair)

• From Equation 10: PRT_HCSL = 0 mW (no HCSL outputs)

• From Equation 11: PDEVICE = 1642.4 mW - (10 * (25.5 mW + 39.5 mW)) - 0 mW = 992.4 mW

In this worst-case example, the IC device will dissipate about 992.4 mW or 60% of the total power (1642.4 mW),

while the remaining 40% will be dissipated in the LVPECL emitter resistors (255 mW for 10 pairs) and

termination voltage (395 mW into Vcco - 2 V).

Based on θJA of 28.5 °C/W, the estimated die junction temperature would be about 28.3 °C above ambient, or

113.3 °C when TA= 85 °C.

Power Supply Bypassing

The Vcc and Vcco power supplies should have a high-frequency bypass capacitor, such as 0.1 uF or 0.01 uF,

placed very close to each supply pin. 1 uF to 10 uF decoupling capacitors should also be placed nearby the

device between the supply and ground planes. All bypass and decoupling capacitors should have short

connections to the supply and ground plane through a short trace or via to minimize series inductance.

Power Supply Ripple Rejection

In practical system applications, power supply noise (ripple) can be generated from switching power supplies,

digital ASICs or FPGAs, etc. While power supply bypassing will help filter out some of this noise, it is important to

understand the effect of power supply ripple on the device performance. When a single-tone sinusoidal signal is

applied to the power supply of a clock distribution device, such as LMK00301, it can produce narrow-band phase

modulation as well as amplitude modulation on the clock output (carrier). In the single-side band phase noise

spectrum, the ripple-induced phase modulation appears as a phase spur level relative to the carrier (measured in

dBc).

For the LMK00301, power supply ripple rejection, or PSRR, was measured as the single-sideband phase spur

level (in dBc) modulated onto the clock output when a ripple signal was injected onto the Vcco supply. The

PSRR test setup is shown in Figure 39.

Product Folder Links: LMK00301

Ripple

Source Bias-Tee Power

Supplies

DUT Board

Limiting

Amp

Scope Phase Noise

Analyzer

Measure 100 mVPP

ripple on Vcco at IC

OUT+

OUT- OUT

Measure single

sideband phase spur

power in dBc

Clock

Source

IN+

IN-

Vcco Vcc

LMK00301

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Figure 39. PSRR Test Setup

A signal generator was used to inject a sinusoidal signal onto the Vcco supply of the DUT board, and the peak-

to-peak ripple amplitude was measured at the Vcco pins of the device. A limiting amplifier was used to remove

amplitude modulation on the differential output clock and convert it to a single-ended signal for the phase noise

analyzer. The phase spur level measurements were taken for clock frequencies of 156.25 MHz and 312.5 MHz

under the following power supply ripple conditions:

• Ripple amplitude: 100 mVpp on Vcco = 2.5 V

• Ripple frequencies: 100 kHz, 1 MHz, and 10 MHz

Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ)

can be calculated using the measured single-sideband phase spur level (PSRR) as follows:

DJ (ps pk-pk) = [(2*10(PSRR / 20)) / (π*fCLK)] * 1012 (12)

The “PSRR vs. Ripple Frequency” plots in Typical Performance Characteristics show the ripple-induced phase

spur levels for the differential output types at 156.25 MHz and 312.5 MHz . The LMK00301 exhibits very good

and well-behaved PSRR characteristics across the ripple frequency range for all differential output types. The

phase spur levels for LVPECL are below -64 dBc at 156.25 MHz and below -62 dBc at 312.5 MHz. Using

Equation 12, these phase spur levels translate to Deterministic Jitter values of 2.57 ps pk-pk at 156.25 MHz and

1.62 ps pk-pk at 312.5 MHz. Testing has shown that the PSRR performance of the device improves for Vcco =

3.3 V under the same ripple amplitude and frequency conditions.

Thermal Management

Power dissipation in the LMK00301 device can be high enough to require attention to thermal management. For

reliability and performance reasons the die temperature should be limited to a maximum of 125 °C. That is, as an

estimate, TA(ambient temperature) plus device power dissipation times θJA should not exceed 125 °C.

The package of the device has an exposed pad that provides the primary heat removal path as well as excellent

electrical grounding to the printed circuit board. To maximize the removal of heat from the package a thermal

land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the

package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package.

A recommended land and via pattern is shown in Figure 40. More information on soldering WQFN packages can

be obtained at: http://www.ti.com/packaging.

Product Folder Links: LMK00301

0.33 mm, typ

1.2 mm, typ

5.0 mm, min

LMK00301

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SNAS512G –SEPTEMBER 2011–REVISED MAY 2013

Figure 40. Recommended Land and Via Pattern

To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground

plane layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite

side of the PCB from the device. This copper area may be plated or solder coated to prevent corrosion but

should not have conformal coating (if possible), which could provide thermal insulation. The vias shown in

Figure 40 should connect these top and bottom copper layers and to the ground layer. These vias act as “heat

pipes” to carry the thermal energy away from the device side of the board to where it can be more effectively

dissipated.

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REVISION HISTORY

Changes from Revision F (February 2013) to Revision G Page

• Changed Target Applications by adding additional applications to the second and third bullets, and removing High-

Speed and Serial Interfaces from first bullet. ........................................................................................................................ 1

• Changed VCM text to condition for VIH to VCM parameters .................................................................................................... 8

• Deleted VIH min value from Electrical Characteristics Table. ............................................................................................... 8

• Deleted VIL max value from Electrical Characteristics table. ................................................................................................ 8

• Added VI_SE parameter and spec limits with corresponding table note to Electrical Characteristics Table. ........................ 8

• Changed third paragraph in Driving the Clock Inputs section to include CLKin* and LVCMOS text. Revised to better

correspond with information in Electrical Characteristics Table. ........................................................................................ 19

• Changed bypass cap text to signal attenuation text of the fourth paragraph in Driving the Clock Inputs section. ............ 19

• Changed Single-Ended LVCMOS Input, DC Coupling with Common Mode Biasing image with revised graphic. ............ 19

• Added text to second paragraph of Termination for AC Coupled Differential Operation to explain graphic update to

Differential LVDS Operation with AC Coupling to Receivers .............................................................................................. 23

• Changed graphic for Differential LVDS Operation, AC Coupling, No Biasing by the Receiver and updated caption. ....... 23

Product Folder Links: LMK00301

PACKAGE OPTION ADDENDUM

www.ti.com 3-May-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Top-Side Markings

(4)

Samples

LMK00301SQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LMK00301

LMK00301SQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LMK00301

LMK00301SQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LMK00301

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LMK00301SQ/NOPB WQFN RHS 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1

LMK00301SQE/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1

LMK00301SQX/NOPB WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 13-May-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMK00301SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0

LMK00301SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0

LMK00301SQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 13-May-2013

Pack Materials-Page 2

MECHANICAL DATA

RHS0048A

www.ti.com

SQA48A (Rev B)

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