EVALUATION KIT AVAILABLE MAX17521 60V, 1A, Dual-Output, High-Efficiency, Synchronous Step-Down DC-DC Converter General Description Benefits and Features The MAX17521 dual-output, high-efficiency, high-voltage, synchronous step-down DC-DC converter with integrated MOSFETs operates over a 4.5V to 60V input. The converter can deliver up to 1A at each output. Each output is programmable from 0.9V to 92%VIN. The feedback voltage regulation accuracy over -40C to +125C is 1.7%. Reduces External Components and Total Cost * No Schottky--Synchronous Operation * All-Ceramic Capacitors, Compact Layout Reduces Number of DC-DC Regulators to Stock * Wide 4.5V to 60V Input * Each Output Adjustable From 0.9V to 92%VIN * Pin-Selectable 560kHz or 300kHz Switching Frequency * Independent Input Voltage Pin for Each Output The MAX17521 uses peak-current-mode control. Each output can be operated in the pulse-width modulation (PWM) or pulse-frequency modulation (PFM) control schemes. Reduces Power Dissipation * Peak Efficiency > 90% * PFM Mode Enables Enhanced Light-Load Efficiency * 1A Shutdown Current The MAX17521 is available in a 24-pin (4mm x 5mm) TQFN package. Simulation models are available. Applications Operates Reliably in Adverse Industrial Environments * Hiccup Mode Overload Protection * Adjustable Soft-Start Pin for Each Output * Built-In Output Voltage Monitoring with RESET for Each Output * Adjustable EN/UVLO Threshold for Each Output * Monotonic Startup Into Prebiased Load * Overtemperature Protection * -40C to +125C Operation Industrial Control Power Supplies CPU, DSP, or FPGA Power Distributed Supply Regulation General-Purpose Point of Load Ordering Information appears at end of data sheet. Typical Application Circuit VIN 7.5V-60V C1 2.2F C2 2.2F PGND1 EN/UVLO1 VIN1 VIN2 EN/UVLO2 PGND2 MODE1 C6 1F MODE2 VCC1 VCC2 C16 1F SGND2 SGND1 MAX17521 RESET1 VOUT1 5V, 1A RESET2 L1 22H LX2 LX1 FB1 SS1 COMP1 FSEL SYNC COMP2 SS2 FB2 C8 3300 pF C7 3300 pF R5 14k C10 33pF C9 2700 pF 19-7479; Rev 0; 3/15 VOUT2 3.3V, 1A R9 54.9k R1 82.5k R2 18.2k L2 15H C4 22F C3 10F C12 22pF R8 19.1k C11 2700 pF R10 20.5k MAX17521 60V, 1A, Dual-Output, High-Efficiency, Synchronous Step-Down DC-DC Converter Absolute Maximum Ratings VIN_ to PGND_.......................................................-0.3V to +65V EN/UVLO_ to SGND_.............................. -0.3V to (VIN_ + 0.3V) LX_ to PGND_......................................... -0.3V to (VIN_ + 0.3V) FB_, RESET_, FSEL, MODE_, COMP_, VCC_, SYNC, SS_ to SGND_...............-0.3V to +6V SGND_ to PGND_................................................-0.3V to +0.3V LX Total RMS Current.........................................................1.6A Continuous Power Dissipation (TA = +70C) (derate 28.6mW/C above +70C) (multilayer board).....................................................2285.7mW Output Short-Circuit Duration.....................................Continuous Operating Temperature Range.......................... -40C to +125C Junction Temperature.......................................................+150C Storage Temperature Range............................. -65C to +160C Lead Temperature (soldering, 10s).................................. +300C Soldering Temperature (reflow)........................................+260C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Thermal Characteristics (Note 1) Junction-to-Ambient Thermal Resistance (JA)...............35C/W Junction-to-Case Thermal Resistance (JC)...................1.8C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Electrical Characteristics (VIN_ = +24V, VSGND_ = VPGND_ = VFSEL = 0V, CIN_ = 2.2F, CVCC_ = 1F, VEN/UVLO_ = 1.5V, CSS_ = 0.01F, FB_ = 0.98 x VFB-REG, COMP_ = unconnected, LX_ = unconnected, RESET_ = unconnected. TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C. All voltages are referenced to SGND_, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 60 V 1 3.5 A 135 260 A INPUT SUPPLY (VIN) Input Voltage Range Input Shutdown Current Input Switching Current VIN_ IIN-SH 4.5 VEN_ = 0V, shutdown mode IQ_PFM_ VMODE_> 2V IQ_PWM_ VMODE_< 0.8V, VCOMP_ = 0.8V VFSEL > 2V 5 VFSEL < 0.8V mA 3.7 ENABLE/UVLO (EN_) EN_ Threshold VEN_R VEN_rising 1.19 1.215 1.24 VEN_F VEN_falling 1.11 1.135 1.16 VEN_TRUESD EN_ Input Leakage Current IEN_ VEN_falling, true shutdown V 0.75 VEN_= VIN = 60V, TA = +25C 300 nA FREQUENCY SELECTOR (FSEL) FSEL Threshold FSEL Input Leakage Current VFSELR VFSEL low level VFSELF VFSEL high level IFSEL VFSEL = VCC, TA = +25C 0.8 2 -2.5 V +2.5 A 1.9 V 300 nA MODE SELECTOR (MODE_) MODE_ Threshold MODE_ Input Leakage Current www.maximintegrated.com VMODE_ R VMODE_ low level VMODE_ F VMODE_ high level IMODE_ VMODE = VCC, TA = +25C 2.5 Maxim Integrated 2 MAX17521 60V, 1A, Dual-Output, High-Efficiency, Synchronous Step-Down DC-DC Converter Electrical Characteristics (continued) (VIN_ = +24V, VSGND_ = VPGND_ = VFSEL = 0V, CIN_ = 2.2F, CVCC_ = 1F, VEN/UVLO_ = 1.5V, CSS_ = 0.01F, FB_ = 0.98 x VFB-REG, COMP_ = unconnected, LX_ = unconnected, RESET_ = unconnected. TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C. All voltages are referenced to SGND_, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 4.65 5 5.35 V VCC_ = 4.3V, VIN_ = 12V 17 40 80 VIN_ = 4.5V, IVCC_ = 5mA 4.1 VVCC_-UVR VCC_ rising 3.85 4 4.15 VCC_ -UVF VCC_ falling 3.55 3.7 3.85 High-Side_ pMOS On-Resistance RDS_ -ONH ILX_ = 0.5A (sourcing) TA = +25C 0.6 0.8 Low-Side_ nMOS On-Resistance RDS_ -ONL ILX_ = 0.5A (sinking) TA = +25C LDO (VCC_) VCC_ Output Voltage Range VCC_ Current Limit VCC_ Dropout VCC_ UVLO VVCC_ IVCC_ -MAX VCC_-DO 6V < VIN_ < 12V, 0mA < IVCC_ < 10mA 12V < VIN_ < 60V, 0mA < IVCC_ < 2mA mA V V POWER MOSFETs LX_ Leakage Current ILX_LKG TA = TJ = +125C (Note 3) 1.2 0.2 TA = TJ = +125C (Note 3) 0.35 0.45 VEN_ = 0V, TA = +25C, VLX_ = (VPGND_ + 1V) to (VIN_ - 1V) 3 A A SOFT-START (SS_) Charging Current_ ISS_ VSS_ = 0.5V 4.7 5 5.3 0.885 0.9 0.915 FEEDBACK (FB) FB Regulation Voltage VFB_REG FB Input Bias Current IFB MODE_ = SGND_ MODE_ = unconnected 0.915 VFB = 0.9V 15 100 V nA OUTPUT VOLTAGE (VOUT) Output Voltage Range VFSEL > 2V; no load (Note 3) 0.92 0.92 x VIN VFSEL < 0.8V; no load (Note 3) 0.92 0.96 x VIN ICOMP_ = 2.5A 510 590 650 S ICOMP_ _SRC 19 33 55 A ICOMP_ 19 33 55 A RCS_ 0.455 0.5 0.545 VOUT V TRANSCONDUCTANCE AMPLIFIER (COMP) Transconductance COMP_ Source Current COMP_ Sink Current Current Sense Transresistance www.maximintegrated.com GM_ _SINK Maxim Integrated 3 MAX17521 60V, 1A, Dual-Output, High-Efficiency, Synchronous Step-Down DC-DC Converter Electrical Characteristics (continued) (VIN_ = +24V, VSGND_ = VPGND_ = VFSEL = 0V, CIN_ = 2.2F, CVCC_ = 1F, VEN/UVLO_ = 1.5V, CSS_ = 0.01F, FB_ = 0.98 x VFB-REG, COMP_ = unconnected, LX_ = unconnected, RESET_ = unconnected. TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C. All voltages are referenced to SGND_, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IPEAK_-LIMIT 1.35 1.6 1.85 A Runaway Current Limit Threshold IRUNAWAY 1.45 1.85 2.05 A Sink Current Limit Threshold ISINK-LIMIT CURRENT LIMIT Peak Current Limit Threshold PFM Peak Current _-LIMIT IPFM_ VMODE_ < 0.8V VMODE_ > 2V VMODE_ > 2V 0.65 A 0 A 0.2 0.3 0.4 VFSEL > 2V 510 560 600 VFSEL < 0.8V 280 300 320 VFSEL > 2V 280 300 320 68.5 70 72.5 A TIMINGS Switching Frequency fSW_ VFB_ > VOUT_-HICF VFB_ <VOUT_-HICF VFB_ Under Voltage Trip Level to Cause HICCUP VOUT_-HICF VSS_ > 0.95V (soft-start is done) HICCUP Timeout Minimum On-Time Maximum Duty Cycle 4096 TON_ _MIN DMAX_ VFB_ = 0.98 x VFB_ -REG % Cycles 85 120 VFSEL > 2V 92 94 96 VFSEL < 0.8V 96 97 98 LX_ Dead Time kHz 5 ns % ns FREQUENCY SYNCHRONIZATIONS (SYNC) SYNC Threshold VSYNC_R VSYNC_F SYNC Input Leakage Current ISYNC SYNC Pulse Duration TSYNC SYNC Frequency 0.8 FSYNC 2 VSYNC = 5V ; TA = +25C 300 50 nA ns 1.1x fSW FSW = 300kHz or 560kHz V 1.4x fSW kHz RESET_ RESET_ Output Level Low IRESET_ = 1mA 0.02 V RESET_ Output Leakage Current High VFB_ = 1.01 x VFB_-REG, TA = 25C 0.5 A VOUT_ Threshold for RESET Falling VOUT_ -OKF VFB_ falling 90.5 92.5 94.5 % VOUT_ Threshold for RESET_ Rising VOUT_-OKR VFB_ rising 93.5 95.5 97.5 % RESET _ Delay After FB_ Reaches 95% Regulation www.maximintegrated.com 1024 Cycles Maxim Integrated 4 MAX17521 60V, 1A, Dual-Output, High-Efficiency, Synchronous Step-Down DC-DC Converter Electrical Characteristics (continued) (VIN_ = +24V, VSGND_ = VPGND_ = VFSEL = 0V, CIN_ = 2.2F, CVCC_ = 1F, VEN/UVLO_ = 1.5V, CSS_ = 0.01F, FB_ = 0.98 x VFB-REG, COMP_ = unconnected, LX_ = unconnected, RESET_ = unconnected. TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C. All voltages are referenced to SGND_, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS THERMAL SHUTDOWN Thermal-Shutdown Threshold Thermal-Shutdown Hysteresis Temperature rising 165 C 10 C Note 2: Limits are 100% tested at TA = +25C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Note 3: Guaranteed by design, not production tested. www.maximintegrated.com Maxim Integrated 5 MAX17521 60V, 1A, Dual-Output, High-Efficiency, Synchronous Step-Down DC-DC Converter Typical Operating Characteristics (VIN_ = 24V, VSGND_ = VPGND_ = 0V, CVIN_ = 2.2F, CVCC = 1F, VEN/UVLO_ = 1.5V, CSS_ = 3300pF, VFB_ = 0.98 x VOUT_, LX_ = unconnected, RESET_ = unconnected, FSEL = unconnected, MODE_ = unconnected, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C. All voltages are referenced to SGND, unless otherwise noted.) OVERALL EFFICIENCY vs. INPUT VOLTAGE IOUT1 = IOUT2 = 750mA 90 88 86 80 80 70 70 60 50 40 IOUT1 = IOUT2 = 1A 8 18 28 38 0 48 5V OUTPUT, LOAD REGULATION 10 100 0 1000 100 1000 TOC05 VIN = 24V, FSEL = OPEN 3.41 PFM MODE 3.39 3.37 3.35 3.33 3.31 3.29 4.95 3.27 PWM MODE 0 200 400 600 800 3.25 1000 PWM MODE 0 LOAD CURRENT (mA) 4.988 TOC06 3.313 OUTPUT VOLTAGE (V) 4.982 4.980 4.978 IOUT1 = 500mA IOUT1 = 250mA 4.974 4.972 18 28 INPUT VOLTAGE (V) www.maximintegrated.com 38 IOUT2 = 1A 3.312 800 1000 TOC07 IOUT2 = 750mA 3.311 3.310 3.309 3.308 IOUT2 = 500mA IOUT2 = 250mA 3.307 3.306 FSEL = OPEN 8 600 3.3V OUTPUT, LINE REGULATION 3.315 IOUT1 = 750mA 4.984 4.976 400 3.314 IOUT1 = 1A 4.986 200 LOAD CURRENT (mA) 5V OUTPUT, LINE REGULATION 4.990 OUTPUT VOLTAGE (V) 10 3.3V OUTPUT, LOAD REGULATION 3.45 3.43 PFM MODE 5.00 4.970 VIN = 24V, FSEL = OPEN 1 LOAD CURRENT (mA) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1 TOC04 5.05 4.90 PWM MODE 10 VIN = 24V, FSEL = OPEN VIN = 24V, FSEL = OPEN 5.10 40 LOAD CURRENT (mA) INPUT VOLTAGE (V) 5.15 50 20 10 FSEL = OPEN 60 30 PWM MODE TOC03 PFM MODE 90 20 82 3.3V OUTPUT, EFFICIENCY vs. LOAD CURRENT 100 80 30 84 TOC02 PFM MODE 90 IOUT1 = IOUT2 = 500mA EFFICIENCY (%) EFFICIENCY (%) 92 5V OUTPUT, EFFICIENCY vs. LOAD CURRENT 100 EFFICIENCY (%) 94 TOC01 48 3.305 FSEL = OPEN 8 18 28 38 48 INPUT VOLTAGE (V) Maxim Integrated 6 MAX17521 60V, 1A, Dual-Output, High-Efficiency, Synchronous Step-Down DC-DC Converter Typical Operating Characteristics (continued) (VIN_ = 24V, VSGND_ = VPGND_ = 0V, CVIN_ = 2.2F, CVCC = 1F, VEN/UVLO_ = 1.5V, CSS_ = 3300pF, VFB_ = 0.98 x VOUT_, LX_ = unconnected, RESET_ = unconnected, FSEL = unconnected, MODE_ = unconnected, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C. All voltages are referenced to SGND, unless otherwise noted.) STARTUP FROM EN/UVLO, 5V OUTPUT, 1A LOAD CURRENT TOC08 STARTUP FROM EN/UVLO, 3.3V OUTPUT, 1A LOAD CURRENT STARTUP FROM VIN, 5V OUTPUT, 1A LOAD CURRENT TOC09 TOC10 10V/div VEN/UVLO1 5V/div VEN/UVLO2 5V/div 2V/div VIN VOUT2 VOUT1 500mA/div 2V/div VOUT1 2V/div IOUT1 IOUT2 500mA/div VRESET1 5V/div 500mA/div 5V/div VRESET2 1ms/div IOUT1 5V/div VRESET1 400s/div 1ms/div STARTUP FROM VIN, 3.3V OUTPUT, 1A LOAD CURRENT STARTUP WITH 2.5V PREBIAS, 5V OUTPUT, NO LOAD TOC11 TOC12 10V/div 2V/div VIN VOUT2 5V/div 2V/div VEN/UVLO1 VOUT1 500mA/div 500mA/div IOUT1 IOUT2 5V/div 5V/div VRESET2 VRESET1 400s/div STARTUP WITH 2V PREBIAS, 3.3V OUTPUT, NO LOAD 400s/div STARTUP IN RATIOMETRIC TRACKING MODE, 1A LOAD ON BOTH OUTPUTS TOC14 TOC13 10V/div 5V/div VEN/UVLO2 1V/div 2V/div VOUT2 VIN 1V/div 500mA/div IOUT2 5V/div VOUT1 VRESET2 VOUT2 400s/div www.maximintegrated.com 400s/div Maxim Integrated 7 MAX17521 60V, 1A, Dual-Output, High-Efficiency, Synchronous Step-Down DC-DC Converter Typical Operating Characteristics (continued) (VIN_ = 24V, VSGND_ = VPGND_ = 0V, CVIN_ = 2.2F, CVCC = 1F, VEN/UVLO_ = 1.5V, CSS_ = 3300pF, VFB_ = 0.98 x VOUT_, LX_ = unconnected, RESET_ = unconnected, FSEL = unconnected, MODE_ = unconnected, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C. All voltages are referenced to SGND, unless otherwise noted.) 5V OUTPUT,PWM MODE, (LOAD CURRENT STEPPED FROM 0.5A--1A) STARTUP IN SEQUENTIAL TRACKING MODE, 1A LOAD ON BOTH OUTPUTS TOC16 STARTUP IN COINCIDENT TRACKING MODE, 1A LOAD ON BOTH OUTPUTS TOC15 TOC17 2V/div 10V/div 1V/div VOUT1 VIN VOUT1 (AC) 100mV/div IOUT 500mA/div 5V/div 1V/div 2V/div 5V/div VOUT2 VOUT1 VOUT2 1ms/div 400s/div 5V OUTPUT, PWM MODE, (LOAD CURRENT STEPPED FROM 0 TO 0.5A) 100s/div 5V OUTPUT, PFM MODE, (LOAD CURRENT STEPPED FROM 5mA--500mA) TOC19 TOC18 VOUT1 (AC) 100mV/div VOUT1 (AC) 200mV/div IOUT1 200mA/div IOUT1 200mA/div 100s/div 10ms/div 3.3V OUTPUT, PWM MODE, (LOAD CURRENT STEPPED FROM 0--0.5A) 3.3V OUTPUT,PWM MODE, (LOAD CURRENT STEPPED FROM 0.5A--1A) TOC21 TOC20 VOUT2 (AC) 100mV/div VOUT2 (AC) 50mV/div 500mA/div IOUT2 IOUT2 100s/div www.maximintegrated.com 200mA/div 100s/div Maxim Integrated 8 MAX17521 60V, 1A, Dual-Output, High-Efficiency, Synchronous Step-Down DC-DC Converter Typical Operating Characteristics (continued) (VIN_ = 24V, VSGND_ = VPGND_ = 0V, CVIN_ = 2.2F, CVCC = 1F, VEN/UVLO_ = 1.5V, CSS_ = 3300pF, VFB_ = 0.98 x VOUT_, LX_ = unconnected, RESET_ = unconnected, FSEL = unconnected, MODE_ = unconnected, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C. All voltages are referenced to SGND, unless otherwise noted.) 3.3V OUTPUT, PFM MODE, (LOAD CURRENT STEPPED FROM 5mA--0.5A) TOC22 VOUT2 (AC) 100mV/div IOUT2 STEADY-STATE SWITCHING WAVEFORMS, 5V OUTPUT, NO LOAD, PWM MODE STEADY-STATE SWITCHING WAVEFORMS, 5V OUTPUT, 1A LOAD TOC23 TOC24 VOUT1 (AC) 20mV/div VOUT1 (AC) VLX1 10V/div VLX1 10V/div 1A/div ILX1 500mA/div 200mA/div ILX1 VIN = 24V, FSEL = OPEN 20mV/div 1s/div 1s/div 1ms/div STEADY-STATE SWITCHING WAVEFORMS, 5V OUTPUT, 5mA LOAD, PFM MODE STEADY-STATE SWITCHING WAVEFORMS, 3.3V OUTPUT, 1A LOAD TOC26 TOC25 100mV/div VOUT1 (AC) 10V/div VLX1 ILX1 200mA/div VOUT2 (AC) 10mV/div VLX2 10V/div ILX2 1A/div VIN = 24V, FSEL = OPEN VIN = 24V, FSEL = OPEN 40s/div 1s/div STEADY-STATE SWITCHING WAVEFORMS, 3.3V OUTPUT, NO LOAD, PWM MODE STEADY-STATE SWITCHING WAVEFORMS, 3.3V OUTPUT, 5mA LOAD, PFM MODE TOC27 VOUT2 (AC) VIN = 24V, FSEL = OPEN VIN = 24V, FSEL = OPEN VLX2 ILX2 TOC28 10mV/div VOUT2 (AC) 10V/div VLX2 500mA/div 100mV/div 10V/div ILX2 200mA/div VIN = 24V, FSEL = OPEN 1s/div www.maximintegrated.com 40s/div Maxim Integrated 9 MAX17521 60V, 1A, Dual-Output, High-Efficiency, Synchronous Step-Down DC-DC Converter Typical Operating Characteristics (continued) (VIN_ = 24V, VSGND_ = VPGND_ = 0V, CVIN_ = 2.2F, CVCC = 1F, VEN/UVLO_ = 1.5V, CSS_ = 3300pF, VFB_ = 0.98 x VOUT_, LX_ = unconnected, RESET_ = unconnected, FSEL = unconnected, MODE_ = unconnected, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C. All voltages are referenced to SGND, unless otherwise noted.) OUTPUT SHORT-CIRCUIT PROTECTION, 5V OUTPUT TOC29 OUTPUT SHORT-CIRCUIT PROTECTION, 3.3V OUTPUT TOC30 VOUT1 500mV/div VOUT2 500mV/div IOUT1 500mA/div IOUT2 500mA/div 2ms/div 5V OUTPUT, 1A LOAD, BODE PLOT 2ms/div 3.3V OUTPUT, 1A LOAD, BODE PLOT TOC31 TOC32 PHASE PHASE VOUT = 5V FCR = 51kHz, Phase Margin = 62.3 PHASE () VOUT = 3.3V GAIN FREQUENCY(Hz) www.maximintegrated.com GAIN GAIN (dB) GAIN (dB) PHASE () GAIN FCR = 51K, Phase Margin = 62.3 GAIN FREQUENCY(Hz) Maxim Integrated 10 MAX17521 60V, 1A, Dual-Output, High-Efficiency, Synchronous Step-Down DC-DC Converter Pin Configuration LX1 MODE1 SYNC MODE2 LX2 TOP VIEW 24 23 22 21 20 + PGND1 1 19 PGND2 VIN1 2 18 VIN2 EN/UVLO1 3 17 EN/UVLO2 VCC1 4 FB1 5 15 FB2 SS1 6 14 SS2 SGND1 7 MAX17521 16 VCC2 10 11 RESET2 13 SGND2 12 COMP2 9 FSEL COMP1 8 RESET1 EP TQFN (4mm x 5mm) Pin Description PIN NAME 1 PGND1 2 VIN1 3 EN/UVLO1 4 VCC1 5 FB1 Feedback Input for Converter 1. Connect FB1 to the center of the resistive divider between VOUT1 and SGND1. See the Adjusting Output Voltage section for more details. 6 SS1 Soft-start Input for Converter 1. Connect a capacitor from SS1 to SGND1 to set the soft-start time for converter 1. 7 SGND1 Analog Ground Connection for Converter 1. 8 COMP1 Loop Compensation Pin for Converter 1. Connect an RC network from COMP1 to SGND1. See the Loop Compensation section for more details. www.maximintegrated.com FUNCTION Power Ground Connection of Converter 1. Connect PGND1 externally to the power ground plane. Connect SGND and PGND pins together at the ground return path of the VCC bypass capacitors. Power-Supply Input of Converter 1. The input supply range is from 4.5V to 60V. Decouple to PGND1 with a 2.2F capacitor; place the capacitor close to the VIN1 and PGND1 pins. Enable/Undervoltage Lockout Input for Converter 1. Drive EN/UVLO1 high to enable converter 1. Connect to the center of the resistive divider between VIN1 and SGND1 to set the input voltage at which the converter 1 turns on. Pull up to VIN1 for always-on operation. 5V LDO Output for Converter 1. Bypass VCC1 with 1F ceramic capacitance to SGND1. Maxim Integrated 11 MAX17521 60V, 1A, Dual-Output, High-Efficiency, Synchronous Step-Down DC-DC Converter Pin Description (continued) PIN NAME 9 RESET1 Open-Drain RESET1 Output. The RESET1 output is driven low if FB1 drops below 92.5% of its set value. RESET1 goes high 1024 clock cycles after FB1 rises above 95.5% of its set value. RESET1 is valid when the device is enabled and VIN is above 4.5V. 10 FSEL Configures the Switching Frequency of the MAX17521. Leaving FSEL unconnected sets the switching frequency of both the converters at 560kHz. Connecting FSEL pin to SGND_ sets the switching frequency of both the converters at 300kHz. 11 RESET2 Open-Drain RESET2 Output. The RESET2 output is driven low if FB2 drops below 92.5% of its set value. RESET2 goes high 1024 clock cycles after FB2 rises above 95.5% of its set value. RESET2 is valid when the device is enabled and VIN is above 4.5V. 12 COMP2 Loop Compensation Pin for Converter 2. Connect an RC network from COMP2 to SGND2. See the Loop Compensation section for more details. 13 SGND2 Analog Ground Connection for Converter 2. 14 SS2 Soft-Start Input for Converter 2. Connect a capacitor from SS2 to SGND2 to set the soft-start time for converter 2. 15 FB2 Feedback Input for Converter 2. Connect FB2 to the center of the resistive divider between VOUT2 and SGND2. See the Adjusting Output Voltage section for more details. 16 VCC2 17 EN/UVLO2 18 VIN2 19 PGND2 20 LX2 21 MODE2 22 SYNC 23 MODE1 24 LX1 Switching Node of Converter 1. Connect LX1 to the switching-side of the inductor. - EP Exposed Pad. Connect to the SGND pins. Connect to a large copper plane below the IC to improve heat dissipation capability. www.maximintegrated.com FUNCTION 5V LDO Output for converter 2. Bypass VCC2 with 1F ceramic capacitance to SGND2. Enable/Undervoltage Lockout Input for Converter 2. Drive EN/UVLO2 high to enable converter 2. Connect to the center of the resistive divider between VIN2 and SGND2 to set the input voltage at which the converter 2 turns on. Pull up to VIN2 for always on operation. Power-Supply Input of Converter 2. The input supply range is from 4.5V to 60V. Decouple to PGND2 with a 2.2F capacitor; place the capacitor close to the VIN2 and PGND2 pins. Power Ground Connection of Converter 2. Connect PGND2 externally to the power ground plane. Connect SGND and PGND pins together at the ground return path of the VCC bypass capacitors. Switching Node of Converter 2. Connect LX2 to the switching side of the inductor. Configures Converter 2 to Operate in PWM or PFM Modes of Operation. Leave MODE2 unconnected for PFM operation (pulse skipping at light loads). Connect MODE2 to SGND2 for constant frequency PWM operation at all loads. See the MODE Setting section for more details. Synchronizes Device to an External Clock. See the External Frequency Synchronization section for more details. Configures Converter 1 to Operate in PWM or PFM Modes of Operation. Leave MODE1 unconnected for PFM operation (pulse skipping at light loads). Connect MODE1 to SGND1 for constant frequency PWM operation at all loads. See the MODE Setting section for more details. Maxim Integrated 12 MAX17521 60V, 1A, Dual-Output, High-Efficiency, Synchronous Step-Down DC-DC Converter Block Diagram VCC LDO SLOPE COMPENSATION CURRENT SENSE + VIN HICCUP P DRIVER PWM COMPARATOR CURRENT SENSE PWM,PFM LOGIC + LX COMP N DRIVER FSEL MODE OSCILLATOR MODE SELECTOR CLK PGND RESET_ PWM/PFM 5A SS VCC EN/UVLO START RESET LOGIC HICCUP FB MAX17521 (Block diagram of only one step-down regulator is shown) www.maximintegrated.com 900mV REFERENCE SWITCHOVER LOGIC GM COMP SGND Maxim Integrated 13 MAX17521 60V, 1A, Dual-Output, High-Efficiency, Synchronous Step-Down DC-DC Converter Detailed Description The MAX17521 dual step-down regulator operates from 4.5V to 60V and delivers up to 1A load current on each output. Feedback voltage regulation accuracy meets 1.7% over load, line and temperature. The device uses a peak-current-mode control scheme. For each output, an internal transconductance error amplifier generates an integrated error voltage. The error voltage sets the duty cycle using a PWM comparator, a high-side current-sense amplifier, and a slope-compensation generator. At each rising edge of the clock, the high-side pMOSFET turns on and remains on until either the appropriate or maximum duty cycle is reached, or the peak current limit is detected. During the high-side MOSFET's on-time, the inductor current ramps up. During the second half of the switching cycle, the high-side MOSFET turns off and the low-side nMOSFET turns on and remains on until either the next rising edge of the clock arrives or sink current limit is detected. The inductor releases the stored energy as its current ramps down, and provides current to the output (the internal low RDSON pMOS/nMOS switches ensure high efficiency at full load). This device also integrates switching frequency selector pin and individual mode of operation selector pins, enable/ undervoltage lockout (EN/UVLO) pins, programmable soft-start pins, and open-drain RESET signals for each output. Mode of Operation Selection The logic state of the MODE pins are latched when VCC and EN/UVLO voltages exceed the respective UVLO rising thresholds and all internal voltages are ready to allow LX switching. If the MODE pin is open at powerup, the corresponding output operates in PFM mode at light loads. If the MODE pin is grounded at power-up, the corresponding output operates in constant-frequency PWM mode at all loads. State changes on the MODE pins are ignored during normal operation. PWM Mode Operation In PWM mode, the inductor current is allowed to go negative. PWM operation provides constant frequency operation at www.maximintegrated.com all loads, and is useful in applications sensitive to switching frequency. However, the PWM mode of operation gives lower efficiency at light loads compared to the PFM mode of operation. PFM Mode Operation PFM mode of operation disables negative inductor current and additionally skips pulses at light loads for high efficiency. In PFM mode, the inductor current is forced to a fixed peak of 300mA every clock cycle until the output rises to 103% of the nominal voltage. Once the output reaches 103% of the nominal voltage, both the high-side and low-side FETs are turned off and the device enters hibernate operation until the load discharges the output to 101% of the nominal voltage. Most of the internal blocks are turned off in hibernate operation to save quiescent current. After the output falls below 101% of the nominal voltage, the device comes out of hibernate operation, turns on all internal blocks and again commences the process of delivering pulses of energy to the output until it reaches 103% of the nominal output voltage. The advantage of the PFM mode is higher efficiency at light loads because of lower quiescent current drawn from supply. The disadvantage is that the output-voltage ripple is higher compared to PWM mode of operation and switching frequency is not constant at light loads. Linear Regulator (VCC) Two internal linear regulators (VCC1, VCC2) provide 5V nominal supplies to power the internal blocks and the low-side MOSFET drivers. The output of the VCC linear regulators should be bypassed with 1F ceramic capacitors to SGND. The device employs two undervoltage-lockout circuits that disable the internal linear regulators when VCC falls below 3.7V (typ). Each of the VCC regulators can source up to 40mA (typ) to supply the device and to power the low-side gate drivers. Switching Frequency Selection The FSEL pin programs the switching frequency of both the converters. If the FSEL pin is open at power-up, both the outputs operate at 560 kHz switching frequency. If the FSEL pin is grounded at power-up, both the outputs operate at 300kHz switching frequency. Maxim Integrated 14 MAX17521 60V, 1A, Dual-Output, High-Efficiency, Synchronous Step-Down DC-DC Converter Operating Input Voltage Range The minimum and maximum operating input voltages for a given output voltage should be calculated as follows: VIN(MIN) = VOUT + (I OUT(MAX) x (R DCR + 0.47)) D MAX +(I OUT(MAX) x 0.73) VIN(MAX) = VOUT f SW(MAX) x t ON(MIN) where VOUT is the steady-state output voltage, IOUT (MAX) is the maximum load current, RDCR is the DC resistance of the inductor, DMAX is the maximum allowable duty ratio, fSW(MAX) is the maximum switching frequency and tON-MIN is the worst-case minimum switch on-time (120ns). The following table lists the fSW(MAX) and DMAX values to be used for calculation for different switching frequency selection FSEL fSW(MAX) (kHz) DMAX OPEN 600 0.92 SGND 320 0.96 External Frequency Synchronization (SYNC) The internal oscillator of the device can be synchronized to an external clock signal on the SYNC pin. The external synchronization clock frequency must be between 1.1 x fSW and 1.4 x fSW, where fSW is the frequency selected by the FSEL pin. The minimum external clock pulse-width high should be greater than 50ns. See the SYNC section in the Electrical Characteristics table for details. current that built up during the on period of the step-down converter. One occurrence of the runaway current limit triggers a hiccup mode. In addition, if due to a fault condition, output voltage drops to 70% (typ) of its nominal value any time after soft-start is complete, hiccup mode is triggered. In hiccup mode, the converter is protected by suspending switching for a hiccup timeout period of 4096 clock cycles. Once the hiccup timeout period expires, soft-start is attempted again. This operation results in minimal power dissipation under overload fault conditions. RESET Output The device includes two RESET comparators to monitor the output voltages. The open-drain RESET outputs require an external pull-up resistor. RESET can sink 2mA of current while low. RESET goes high (high impedance) 1024 switching cycles after the corresponding output voltage increases above 95.5% of the nominal regulated voltage. RESET goes low when the output voltage drops to below 92.5% of the nominal regulated voltage. RESET also goes low during thermal shutdown. RESET is valid when the device is enabled and VIN is above 4.5V. Coincident/Ratiometric Tracking and Output Voltage Sequencing The soft-start pins (SS_) can be used to track the output voltages to that of another power supply at startup. This requires connecting the SS_ pins to an external resistor divider from the supply which needs to be tracked. The following figures (Figure 1 to Figure 3) show the possible ways of configuring the MAX17521 in various tracking modes. The device is provided with a robust overcurrent-protection scheme that protects the device under overload and output short-circuit conditions. A cycle-by-cycle peak current limit turns off the high-side MOSFET whenever the high-side switch current exceeds an internal limit of 1.6A (typ). A runaway current limit on the high-side switch current at 1.85A (typ) protects the device under high input voltage, short-circuit conditions when there is insufficient output voltage available to restore the inductor www.maximintegrated.com SS1 MAX17521 SS2 OUTPUT VOLTAGE Overcurrent Protection/HICCUP Mode TIME INDEPENDENT SOFT-START Figure 1. Independent Soft-Start of Each Output Maxim Integrated 15 MAX17521 60V, 1A, Dual-Output, High-Efficiency, Synchronous Step-Down DC-DC Converter VOUT1 LX1 R1 SS1 VOUT1 VOUT1 MAX17521 OUTPUT VOLTAGE FB1 R2 R5 SS2 R6 VOUT2 LX2 R3 = R5 R4 = R6 VOUT2 TIME COINCIDENT TRACKING R3 FB2 R4 Figure 2. Coincident Tracking of the Outputs VOUT1 LX1 R1 FB1 MAX17521 R2 FB1 SS2 VOUT2 LX2 R3 VOUT1 OUTPUT VOLTAGE SS1 VOUT2 TIME RATIOMETRIC TRACKING FB2 R4 Figure 3. Ratiometric Tracking of the Outputs www.maximintegrated.com Maxim Integrated 16 MAX17521 60V, 1A, Dual-Output, High-Efficiency, Synchronous Step-Down DC-DC Converter EN/UVLO1 VOUT1 LX1 R1 EN/UVLO1 RESET2 VOUT1 FB1 MAX17521 RESET1 = EN/UVLO2 R2 RESET1 EN/UVLO2 VOUT2 LX2 VOUT2 R3 RESET2 FB2 OUTPUT VOLTAGE SEQUENCING R4 Figure 4. Output Voltage Sequencing During power-off, the output voltages discharge to ground at a rate which depends on the respective output capacitor and load. The RESET_ pins and EN/UVLO_ pins can be daisychained to generate power sequencing, as shown in Figure 4. Prebiased Output When the device starts into a prebiased output, both the high-side and low-side switches of the corresponding channel are turned off so that the converter does not sink current from the output. High-side and low-side switches do not start switching until the PWM comparator commands the first PWM pulse, at which point switching commences first with the high-side switch. The output voltage is then smoothly ramped up to the target value in alignment with the internal reference. Thermal-Overload Protection Thermal-overload protection limits total power dissipation in the device. When the junction temperature of the device exceeds +165C, an on-chip thermal sensor shuts down the device, allowing the device to cool. The thermal sensor turns the device on again after the junction temperature cools by 10C. Soft-start resets during www.maximintegrated.com thermal shutdown. Carefully evaluate the total power dissipation (see the Power dissipation section) to avoid unwanted triggering of the thermal-overload protection in normal operation. Applications Information Input Capacitor Selection The input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit's switching. The input capacitor RMS current requirement (IRMS) for a single output is defined by the following equation: = IRMS I OUT(MAX) x VOUT x (VIN - VOUT ) VIN where, IOUT(MAX) is the maximum load current. IRMS has a maximum value when the input voltage equals twice the output voltage (VIN = 2 x VOUT), so IRMS(MAX) = IOUT(MAX)/2 when only one converter is enabled. When both the converters are enabled and are operating outof-phase, the RMS current is shared by both the input capacitors and therefore the maximum RMS current carried by each of the input capacitors is IOUT(MAX)/4. Maxim Integrated 17 MAX17521 60V, 1A, Dual-Output, High-Efficiency, Synchronous Step-Down DC-DC Converter Choose an input capacitor that exhibits less than +10C temperature rise at the RMS input current for optimal longterm reliability. Use low-ESR ceramic capacitors with highripple-current capability at the input. X7R capacitors are recommended in industrial applications for their temperature stability. When both the converters are enabled, calculate the input capacitance using the following equation: C IN = 0.5 x I OUT(MAX) x D x (1 - D) x f SW x VIN where D = VOUT/VIN is the duty ratio of the controller, fSW is the switching frequency, VIN is the allowable input voltage ripple, and is the efficiency. In applications where the source is located distant from the device input, an electrolytic capacitor should be added in parallel to the ceramic capacitor to provide necessary damping for potential oscillations caused by the inductance of the longer input power path and input ceramic capacitor. Inductor Selection Three key inductor parameters must be specified for operation with the device: inductance value (L), inductor saturation current (ISAT) and DC resistance (RDCR). The switching frequency and output voltage determine the inductor value as follows: 2.2 x VOUT L= f SW where VOUT and fSW are nominal values. Select an inductor whose value is nearest to the value calculated by the previous formula. Select a low-loss inductor closest to the calculated value with acceptable dimensions and having the lowest possible DC resistance. The saturation current rating (ISAT) of the inductor must be high enough to ensure that saturation can occur only above the peak current-limit value of 1.85A. Output Capacitor Selection X7R Ceramic Output capacitors are preferred due to their stability over temperature in Industrial applications. The output capacitor is usually sized to support a step load of 50% of the maximum output current in the application, such that the output voltage deviation is contained to 3% www.maximintegrated.com of the output voltage change. The output capacitance may be calculated as follows: C OUT= 1 I STEP x t RESPONSE x 2 VOUT t RESPONSE ( 0.33 1 + ) fC f sw Where ISTEP is the load current step, tRESPONSE is the response time of the controller, VOUT is the allowable output voltage deviation, fC is the target closed-loop crossover frequency and fSW is the switching frequency. fC is generally chosen to be 1/9th of fSW. Soft-Start capacitor selection The device implements adjustable soft-start operation to reduce inrush current. A capacitor connected from the SS pin to SGND programs the soft-start time for the corresponding output voltage. The selected output capacitance (CSEL) and the output voltage (VOUT) determine the minimum required soft-start capacitor as follows: C SS 56 x 10 -6 x C SEL x VOUT The soft-start time (tSS) is related to the capacitor connected at SS (CSS) by the following equation: t SS C SS 5.55 x 10 -6 For example, to program a 1ms soft-start time, a 5.6nF capacitor should be connected from the SS pin to SGND. Adjusting Output Voltage Set the output voltages with resistive voltage-dividers connected from the positive terminal of the output capacitor (VOUT) to SGND (see Figure 1). Connect the centre node of the divider to the FB pin. To optimize efficiency and output accuracy, use the following calculations to choose the resistive divider values: R4 = R5 = 15 x VOUT 0.9 R4 x 0.9 (VOUT - 0.9) where R4 and R5 are in k. Maxim Integrated 18 MAX17521 60V, 1A, Dual-Output, High-Efficiency, Synchronous Step-Down DC-DC Converter Setting the Undervoltage-Lockout Level The device offers an adjustable input undervoltagelockout level for each output. Set the voltage at which each converter turns on with a resistive voltage-divider connected from VIN to SGND (see Figure 2). Connect the center node of the divider to EN/UVLO pin. Choose R1 to be 3.3M, and then calculate R2 as: R2 = R1x 1.218 (VINU - 1.218) control loop. The basic regulator loop is modeled as a power modulator, an output feedback divider, and an error amplifier. The power modulator has DC gain GMOD(dc), with a pole and zero pair. The following equation defines the power modulator DC gain: G MOD(dc) = 2 0.4 (0.5 - D) + + R LOAD VIN f SW x L SEL 1 where VINU is the input voltage at which a particular converter is required to turn on. Where RLOAD = VOUT/IOUT(MAX), fSW is the switching frequency, LSEL is the selected output inductance, D is the duty ratio, D = VOUT/VIN. Loop Compensation for Adjustable Output Version RZ can be calculated as: The MAX17521 uses peak current-mode control scheme and needs only simple RC networks connected from the COMP pins to SGND to have a stable, high-bandwidth VOUT R4 The compensation network is shown in Figure 3. R Z= 6000 x f C x C SEL x VOUT where RZ is in . Choose fC to be 1/9th of the switching frequency. CZ can be calculated as follows: CZ = C SEL x G MOD(dc) 2xRZ FB CP can be calculated as follows: R5 CP = SGND 1 x R Z x f SW Figure 5. Adjusting Output Voltage VIN TO COMP PIN R1 EN/UVLO R2 RZ CZ CP SGND Figure 6. Setting the Undervoltage Lockout Level www.maximintegrated.com Figure 7. Loop Compensation for Adjustable Output Version Maxim Integrated 19 MAX17521 60V, 1A, Dual-Output, High-Efficiency, Synchronous Step-Down DC-DC Converter Power Dissipation The exposed pad of the IC should be properly soldered to the PCB to ensure good thermal contact. Ensure that the junction temperature of the device does not exceed +125C under the operating conditions specified for the power supply. At high ambient temperatures, based on the operating condition, the heat dissipated in the IC might exceed the maximum junction temperature of +125C. Heat sink should be used to reduce JA at such operating conditions. To prevent the part from exceeding 125C junction temperature, users need to do some thermal analysis. At a particular operating condition, the power losses that lead to temperature rise of the device are estimated as follows: ( 1 PLOSS = (POUT x ( - 1)) - I OUT 2 x R DCR P= OUT VOUT x I OUT If the application has a thermal-management system that ensures that the exposed pad of the device is maintained at a given temperature (TEP_MAX) by using proper heat sinks, then the junction temperature of the device can be estimated at any given maximum ambient temperature as: T= J_MAX TEP_MAX + ( JC x PLOSS ) PCB Layout Guidelines Careful PCB layout is critical to achieve low switching losses and stable operation. For a sample layout that ensures first-pass success, refer to the MAX17521 evaluation kit layouts available at www.maximintegrated.com. Follow these guidelines for good PCB layout: * All connections carrying pulsed currents must be very short and as wide as possible. The loop area of these connections must be made very small to reduce stray inductance and radiated EMI. * A ceramic input filter capacitor should be placed close to the VIN pins of the device. The bypass capacitor for the VCC pins should also be placed close to the VCC pins. External compensation components should be placed close to the IC and far from the inductor. The feedback trace should be routed as far as possible from the inductor. * The analog small-signal ground and the power ground for switching currents must be kept separate. They should be connected together at a point where switching activity is at minimum, typically the return terminal of the VCC bypass capacitors. The ground plane should be kept continuous as much as possible. * A number of thermal vias that connect to a large ground plane should be provided under the exposed pad of the device, for efficient heat dissipation. ) where POUT is the output power, is the efficiency of the device and RDCR is the DC resistance of the output inductor (refer to the Typical Operating Characteristics for more information on efficiency at typical operating conditions). The maximum power that can be dissipated in the 24-pin TQFN package is 2285.7mW at +70C temperature. The power dissipation capability should be derated as the temperature goes above +70C at 28.6mW/C. For a typical multilayer board, the thermal performance metrics for the package are given as: JA = 35C / W JC = 1.8C / W The junction temperature of the device can be estimated at any given maximum ambient temperature (TA_MAX) from the following equation: TJ_MAX = T A _MAX + ( JA x PLOSS ) www.maximintegrated.com Maxim Integrated 20 MAX17521 60V, 1A, Dual-Output, High-Efficiency, Synchronous Step-Down DC-DC Converter Ordering Information Package Information PART PIN-PACKAGE PACKAGE-SIZE MAX17521ATG+ 24 TQFN-EP* 4mm x 5mm *EP = Exposed pad. Chip Information PROCESS: BiCMOS www.maximintegrated.com For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 24 TQFN T2445+1C 21-0201 90-0083 Maxim Integrated 21 MAX17521 60V, 1A, Dual-Output, High-Efficiency, Synchronous Step-Down DC-DC Converter Revision History REVISION NUMBER REVISION DATE 0 3/15 DESCRIPTION Initial release PAGES CHANGED -- For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated's website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. 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