General Description
The MAX17521 dual-output, high-efficiency, high-voltage,
synchronous step-down DC-DC converter with integrated
MOSFETs operates over a 4.5V to 60V input. The converter
can deliver up to 1A at each output. Each output is
programmable from 0.9V to 92%VIN. The feedback voltage
regulation accuracy over -40°C to +125°C is ±1.7%.
The MAX17521 uses peak-current-mode control. Each
output can be operated in the pulse-width modulation
(PWM) or pulse-frequency modulation (PFM) control
schemes.
The MAX17521 is available in a 24-pin (4mm x 5mm)
TQFN package. Simulation models are available.
Applications
●Industrial Control Power Supplies
●CPU, DSP, or FPGA Power
●Distributed Supply Regulation
●General-Purpose Point of Load
Benets and Features
●Reduces External Components and Total Cost
• No Schottky—Synchronous Operation
• All-Ceramic Capacitors, Compact Layout
●Reduces Number of DC-DC Regulators to Stock
• Wide 4.5V to 60V Input
• Each Output Adjustable From 0.9V to 92%VIN
• Pin-Selectable 560kHz or 300kHz Switching
Frequency
• Independent Input Voltage Pin for Each Output
●Reduces Power Dissipation
• Peak Efciency > 90%
• PFM Mode Enables Enhanced Light-Load Efciency
• 1μA Shutdown Current
●Operates Reliably in Adverse Industrial Environments
• Hiccup Mode Overload Protection
• Adjustable Soft-Start Pin for Each Output
• Built-In Output Voltage Monitoring with RESET for
Each Output
• Adjustable EN/UVLO Threshold for Each Output
• Monotonic Startup Into Prebiased Load
• Overtemperature Protection
• -40°C to +125°C Operation
Ordering Information appears at end of data sheet.
19-7479; Rev 0; 3/15
Typical Application Circuit
RESET1
EN/UVLO 1 V
IN1
MODE1
V
CC1
SGND1
SS1 FB2
LX2
1μF
MAX17521
V
IN
7.5V–60V
FB1
LX1
V
OUT1
5V, 1A
EN/UVLO 2V
IN2
SS2
RESET2
MODE2
V
CC2
SGND2
1μF
2700pF
COMP1
2700pF
COMP2
FSELSYNC
PGND1 PGND2
R1
82.5kΩ
R2
18.2kΩ
C3
10μF
L1
22μH
C6
C7
3300pF
C10
33pF
C9
R5
14kΩ
C12
22pF
R8
19.1k Ω
C11
C8
3300pF
C1
2.2μF
C2
2.2μF
C16
L2
15μH
C4
22μF
R9
54.9kΩ
R10
20.5kΩ
V
OUT2
3.3V, 1A
MAX17521 60V, 1A, Dual-Output, High-Efciency,
Synchronous Step-Down DC-DC Converter
EVALUATION KIT AVAILABLE
VIN_ to PGND_ ......................................................-0.3V to +65V
EN/UVLO_ to SGND_ ............................. -0.3V to (VIN_ + 0.3V)
LX_ to PGND_......................................... -0.3V to (VIN_ + 0.3V)
FB_, RESET_, FSEL, MODE_,
COMP_, VCC_, SYNC, SS_ to SGND_ ..............-0.3V to +6V
SGND_ to PGND_................................................-0.3V to +0.3V
LX Total RMS Current ........................................................±1.6A
Continuous Power Dissipation (TA = +70°C)
(derate 28.6mW/°C above +70°C)
(multilayer board) ....................................................2285.7mW
Output Short-Circuit Duration .................................... Continuous
Operating Temperature Range ......................... -40°C to +125°C
Junction Temperature ...................................................... +150°C
Storage Temperature Range ............................ -65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) ....................................... +260°C
Junction-to-Ambient Thermal Resistance (θJA) ..............35°C/W
Junction-to-Case Thermal Resistance (θJC) ..................1.8°C/W
(Note 1)
Electrical Characteristics
(VIN_ = +24V, VSGND_ = VPGND_ = VFSEL = 0V, CIN_ = 2.2μF, CVCC_ = 1μF, VEN/UVLO_ = 1.5V, CSS_ = 0.01μF, FB_ = 0.98 x VFB-REG,
COMP_ = unconnected, LX_ = unconnected, RESET_ = unconnected. TA = TJ = -40°C to +125°C, unless otherwise noted. Typical
values are at TA = +25°C. All voltages are referenced to SGND_, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
INPUT SUPPLY (VIN)
Input Voltage Range V IN_ 4.5 60 V
Input Shutdown Current IIN-SH VEN_ = 0V, shutdown mode 1 3.5 µA
Input Switching Current
IQ_PFM_ VMODE_> 2V 135 260 µA
IQ_PWM_
VMODE_< 0.8V,
VCOMP_ = 0.8V
VFSEL > 2V 5mA
VFSEL < 0.8V 3.7
ENABLE/UVLO (EN_)
EN_ Threshold
VEN_R VEN_rising 1.19 1.215 1.24
V
VEN_F VEN_falling 1.11 1.135 1.16
VEN_-
TRUESD
VEN_falling, true shutdown 0.75
EN_ Input Leakage Current IEN_ VEN_= VIN = 60V, TA = +25°C 300 nA
FREQUENCY SELECTOR (FSEL)
FSEL Threshold VFSELR VFSEL low level 0.8 V
VFSELF VFSEL high level 2
FSEL Input Leakage Current IFSEL VFSEL = VCC, TA = +25°C -2.5 +2.5 µA
MODE SELECTOR (MODE_)
MODE_ Threshold VMODE_ R VMODE_ low level 1.9 V
VMODE_ F VMODE_ high level 2.5
MODE_ Input Leakage Current IMODE_ VMODE = VCC, TA = +25°C 300 nA
MAX17521 60V, 1A, Dual-Output, High-Efciency,
Synchronous Step-Down DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
2
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
(VIN_ = +24V, VSGND_ = VPGND_ = VFSEL = 0V, CIN_ = 2.2μF, CVCC_ = 1μF, VEN/UVLO_ = 1.5V, CSS_ = 0.01μF, FB_ = 0.98 x VFB-REG,
COMP_ = unconnected, LX_ = unconnected, RESET_ = unconnected. TA = TJ = -40°C to +125°C, unless otherwise noted. Typical
values are at TA = +25°C. All voltages are referenced to SGND_, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LDO (VCC_)
VCC_ Output Voltage Range VVCC_ 6V < VIN_ < 12V, 0mA < IVCC_ < 10mA
12V < VIN_ < 60V, 0mA < IVCC_ < 2mA 4.65 5 5.35 V
VCC_ Current Limit IVCC_ -MAX VCC_ = 4.3V, VIN_ = 12V 17 40 80 mA
VCC_ Dropout VCC_-DO VIN_ = 4.5V, IVCC_ = 5mA 4.1 V
VCC_ UVLO VVCC_-UVR VCC_ rising 3.85 4 4.15 V
VCC_ -UVF VCC_ falling 3.55 3.7 3.85
POWER MOSFETs
High-Side_ pMOS
On-Resistance RDS_ -ONH ILX_ = 0.5A
(sourcing)
TA = +25°C 0.6 0.8 Ω
TA = TJ = +125°C (Note 3) 1.2
Low-Side_ nMOS
On-Resistance RDS_ -ONL ILX_ = 0.5A
(sinking)
TA = +25°C 0.2 0.35 Ω
TA = TJ = +125°C (Note 3) 0.45
LX_ Leakage Current ILX_LKG VEN_ = 0V, TA = +25°C, VLX_ =
(VPGND_ + 1V) to (VIN_ – 1V) 3μA
SOFT-START (SS_)
Charging Current_ ISS_ VSS_ = 0.5V 4.7 5 5.3 μA
FEEDBACK (FB)
FB Regulation Voltage VFB_REG
MODE_ = SGND_ 0.885 0.9 0.915 V
MODE_ = unconnected 0.915
FB Input Bias Current IFB VFB = 0.9V 15 100 nA
OUTPUT VOLTAGE (VOUT)
Output Voltage Range VOUT
VFSEL > 2V; no load (Note 3) 0.92 0.92 x
VIN V
VFSEL < 0.8V; no load (Note 3) 0.92 0.96 x
VIN
TRANSCONDUCTANCE AMPLIFIER (COMP)
Transconductance GM_ICOMP_ = ±2.5μA 510 590 650 μS
COMP_ Source Current ICOMP_ _SRC 19 33 55 μA
COMP_ Sink Current ICOMP_
_SINK 19 33 55 μA
Current Sense Transresistance RCS_ 0.455 0.5 0.545 Ω
MAX17521 60V, 1A, Dual-Output, High-Efciency,
Synchronous Step-Down DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
3
Electrical Characteristics (continued)
(VIN_ = +24V, VSGND_ = VPGND_ = VFSEL = 0V, CIN_ = 2.2μF, CVCC_ = 1μF, VEN/UVLO_ = 1.5V, CSS_ = 0.01μF, FB_ = 0.98 x VFB-REG,
COMP_ = unconnected, LX_ = unconnected, RESET_ = unconnected. TA = TJ = -40°C to +125°C, unless otherwise noted. Typical
values are at TA = +25°C. All voltages are referenced to SGND_, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CURRENT LIMIT
Peak Current Limit Threshold IPEAK_-LIMIT 1.35 1.6 1.85 A
Runaway Current Limit
Threshold
IRUNAWAY
_-LIMIT 1.45 1.85 2.05 A
Sink Current Limit Threshold ISINK-LIMIT
VMODE_ < 0.8V 0.65 A
VMODE_ > 2V 0 A
PFM Peak Current IPFM_ VMODE_ > 2V 0.2 0.3 0.4 A
TIMINGS
Switching Frequency fSW_
VFB_ > VOUT_-HICF
VFSEL > 2V 510 560 600
kHz
VFSEL < 0.8V 280 300 320
VFB_ <VOUT_-HICF VFSEL > 2V 280 300 320
VFB_ Under Voltage Trip Level
to Cause HICCUP VOUT_-HICF VSS_ > 0.95V (soft-start is done) 68.5 70 72.5 %
HICCUP Timeout 4096 Cycles
Minimum On-Time TON_ _MIN 85 120 ns
Maximum Duty Cycle DMAX_ VFB_ = 0.98 x VFB_ -REG
VFSEL > 2V 92 94 96 %
VFSEL < 0.8V 96 97 98
LX_ Dead Time 5 ns
FREQUENCY SYNCHRONIZATIONS (SYNC)
SYNC Threshold VSYNC_R 0.8 V
VSYNC_F 2
SYNC Input Leakage Current ISYNC VSYNC = 5V ; TA = +25°C 300 nA
SYNC Pulse Duration TSYNC 50 ns
SYNC Frequency FSYNC FSW = 300kHz or 560kHz 1.1x
fSW
1.4x
fSW kHz
RESET_
RESET_ Output Level Low IRESET_ = 1mA 0.02 V
RESET_ Output Leakage
Current High VFB_ = 1.01 x VFB_-REG, TA = 25°C 0.5 μA
VOUT_ Threshold for RESET
Falling VOUT_ -OKF VFB_ falling 90.5 92.5 94.5 %
VOUT_ Threshold for RESET_
Rising VOUT_-OKR VFB_ rising 93.5 95.5 97.5 %
RESET _ Delay After FB_
Reaches 95% Regulation 1024 Cycles
MAX17521 60V, 1A, Dual-Output, High-Efciency,
Synchronous Step-Down DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
4
Electrical Characteristics (continued)
(VIN_ = +24V, VSGND_ = VPGND_ = VFSEL = 0V, CIN_ = 2.2μF, CVCC_ = 1μF, VEN/UVLO_ = 1.5V, CSS_ = 0.01μF, FB_ = 0.98 x VFB-REG,
COMP_ = unconnected, LX_ = unconnected, RESET_ = unconnected. TA = TJ = -40°C to +125°C, unless otherwise noted. Typical
values are at TA = +25°C. All voltages are referenced to SGND_, unless otherwise noted.) (Note 2)
Note 2: Limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage range are
guaranteed by design and characterization.
Note 3: Guaranteed by design, not production tested.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
THERMAL SHUTDOWN
Thermal-Shutdown Threshold Temperature rising 165 °C
Thermal-Shutdown Hysteresis 10 °C
MAX17521 60V, 1A, Dual-Output, High-Efciency,
Synchronous Step-Down DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
5
Electrical Characteristics (continued)
(VIN_ = 24V, VSGND_ = VPGND_ = 0V, CVIN_ = 2.2μF, CVCC = 1μF, VEN/UVLO_ = 1.5V, CSS_ = 3300pF, VFB_ = 0.98 x VOUT_, LX_ =
unconnected, RESET_ = unconnected, FSEL = unconnected, MODE_ = unconnected, TA = TJ = -40°C to +125°C, unless otherwise
noted. Typical values are at TA = +25°C. All voltages are referenced to SGND, unless otherwise noted.)
80
82
84
86
88
90
92
94
8 18 28 38 48
EFFICIENCY (%)
INPUT VOLTAGE (V)
OVERALL EFFICIENCY
vs. INPUT VOLTAGE
IOUT1 = IOUT2 = 1A FSEL = OPEN
IOUT1 = IOUT2 = 750mA
IOUT1 = IOUT2 = 500mA
TOC01
4.970
4.972
4.974
4.976
4.978
4.980
4.982
4.984
4.986
4.988
4.990
8 18 28 38 48
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
5V OUTPUT, LINE REGULATION
IOUT1 =250mA
FSEL = OPEN
IOUT1 = 1A
IOUT1 =500mA
IOUT1 =750mA
TOC06
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
EFFICIENCY (%)
LOAD CURRENT (mA)
5V OUTPUT,
EFFICIENCYvs. LOAD CURRENT
PWM MODE
PFM MODE
VIN =24V, FSEL = OPEN
TOC02
3.305
3.306
3.307
3.308
3.309
3.310
3.311
3.312
3.313
3.314
3.315
8 18 28 38 48
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
3.3V OUTPUT, LINE REGULATION
IOUT2 =250mA
FSEL = OPEN
IOUT2 = 1A
IOUT2 =500mA
IOUT2 =750mA
TOC07
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
EFFICIENCY (%)
LOAD CURRENT (mA)
3.3V OUTPUT,
EFFICIENCYvs. LOAD CURRENT
PWM MODE
PFM MODE
VIN =24V, FSEL = OPEN
TOC03
4.90
4.95
5.00
5.05
5.10
5.15
0 200 400 600 800 1000
OUTPUT VOLTAGE (V)
LOAD CURRENT (mA)
5V OUTPUT, LOAD REGULATION
PWM MODE
PFM MODE
VIN =24V, FSEL = OPEN
TOC04
3.25
3.27
3.29
3.31
3.33
3.35
3.37
3.39
3.41
3.43
3.45
0 200 400 600 800 1000
OUTPUT VOLTAGE (V)
LOAD CURRENT (mA)
3.3V OUTPUT, LOAD REGULATION
PWM MODE
PFM MODE
VIN =24V, FSEL = OPEN
TOC05
Maxim Integrated
│
6
www.maximintegrated.com
MAX17521 60V, 1A, Dual-Output, High-Efciency,
Synchronous Step-Down DC-DC Converter
Typical Operating Characteristics
(VIN_ = 24V, VSGND_ = VPGND_ = 0V, CVIN_ = 2.2μF, CVCC = 1μF, VEN/UVLO_ = 1.5V, CSS_ = 3300pF, VFB_ = 0.98 x VOUT_, LX_ =
unconnected, RESET_ = unconnected, FSEL = unconnected, MODE_ = unconnected, TA = TJ = -40°C to +125°C, unless otherwise
noted. Typical values are at TA = +25°C. All voltages are referenced to SGND, unless otherwise noted.)
1ms/div
5V/div
STARTUP FROM EN/UVLO,
5V OUTPUT, 1A LOAD CURRENT
5V/div
VOUT1
IOUT1
2V/div
VEN/UVLO1
VRESET1
500mA/div
TOC08
1ms/div
5V/div
STARTUP FROM EN/UVLO,
3.3V OUTPUT, 1A LOAD CURRENT
5V/div
VOUT2
IOUT2
2V/div
VE
N/UVLO2
VRESET2
500mA/div
TOC09
500mA/div
400μs/div
VIN
10V/div
STARTUP FROM VIN,
5V OUTPUT, 1A LOAD CURRENT
VOUT1
IOUT1
2V/div
5V/div
VRESET1
TOC10
400µs/div
5V/div
STARTUP WITH 2V PREBIAS,
3.3V OUTPUT, NO LOAD
5V/div
VOUT2
IOUT2
2V/div
VEN/UVLO2
VRESET2
500mA/div
TOC13
400μs/div
10V/div
STARTUP IN RATIOMETRIC TRACKING MODE,
1A LOAD ON BOTH OUTPUTS
VIN
1V/div
VOUT1
VOUT2
1V/div
TOC14
500mA/div
400µs/div
VIN
10V/div
STARTUP FROM VIN,
3.3V OUTPUT, 1A LOAD CURRENT
VOUT2
IOUT2
2V/div
5V/div
VRESET2
TOC11
400µs/div
5V/div
STARTUP WITH 2.5V PREBIAS,
5V OUTPUT, NO LOAD
5V/div
VOUT1
IOUT1
2V/div
VEN/UVLO1
VRESET1
500mA/div
TOC12
Maxim Integrated
│
7
www.maximintegrated.com
MAX17521 60V, 1A, Dual-Output, High-Efciency,
Synchronous Step-Down DC-DC Converter
Typical Operating Characteristics (continued)
(VIN_ = 24V, VSGND_ = VPGND_ = 0V, CVIN_ = 2.2μF, CVCC = 1μF, VEN/UVLO_ = 1.5V, CSS_ = 3300pF, VFB_ = 0.98 x VOUT_, LX_ =
unconnected, RESET_ = unconnected, FSEL = unconnected, MODE_ = unconnected, TA = TJ = -40°C to +125°C, unless otherwise
noted. Typical values are at TA = +25°C. All voltages are referenced to SGND, unless otherwise noted.)
400μs/div
10V/div
STARTUP IN COINCIDENT TRACKING MODE,
1A LOAD ON BOTH OUTPUTS
VIN
1V/div
VOUT1
VOUT2
1V/div
TOC15
1ms/div
2V/div
STARTUP IN SEQUENTIAL TRACKING MODE,
1A LOAD ON BOTH OUTPUTS
VOUT1 5V/div
VOUT2
2V/div
5V/div
TOC16
100μs/div
100mV/div
5V OUTPUT,PWM MODE,
(LOAD CURRENT STEPPED FROM 0.5A—1A)
VOUT1
(AC)
500mA/div
IOUT
TOC17
100μs/div
100mV/div
3.3V OUTPUT,PWM MODE,
(LOAD CURRENT STEPPED FROM 0.5A—1A)
VOUT2
(AC)
500mA/div
IOUT2
TOC20
100μs/div
50mV/div
3.3V OUTPUT, PWM MODE,
(LOAD CURRENT STEPPED FROM 0—0.5A)
VOUT2
(AC)
200mA/div
IOUT2
TOC21
100μs/div
100mV/div
5V OUTPUT, PWM MODE,
(LOAD CURRENT STEPPED
FROM 0 TO 0.5A)
VOUT1
(AC)
200mA/div
IOUT1
TOC18
10ms/div
200mV/div
5V OUTPUT, PFM MODE,
(LOAD CURRENT STEPPED FROM 5mA—500mA)
VOUT1
(AC)
200mA/div
IOUT1
TOC19
Maxim Integrated
│
8
www.maximintegrated.com
MAX17521 60V, 1A, Dual-Output, High-Efciency,
Synchronous Step-Down DC-DC Converter
Typical Operating Characteristics (continued)
(VIN_ = 24V, VSGND_ = VPGND_ = 0V, CVIN_ = 2.2μF, CVCC = 1μF, VEN/UVLO_ = 1.5V, CSS_ = 3300pF, VFB_ = 0.98 x VOUT_, LX_ =
unconnected, RESET_ = unconnected, FSEL = unconnected, MODE_ = unconnected, TA = TJ = -40°C to +125°C, unless otherwise
noted. Typical values are at TA = +25°C. All voltages are referenced to SGND, unless otherwise noted.)
1ms/div
100mV/div
3.3V OUTPUT, PFM MODE,
(LOAD CURRENT STEPPED FROM 5mA—0.5A)
VOUT2
(AC)
200mA/div
IOUT2
TOC22
1µs/div
VLX1
20mV/div
STEADY-STATE SWITCHING WAVEFORMS,
5V OUTPUT, 1A LOAD
VOUT1
(AC)
10V/div
1A/div
ILX1
TOC23
VIN = 24V, FSEL = OPEN
1µs/div
VLX1
20mV/div
STEADY-STATE SWITCHING WAVEFORMS,
5V OUTPUT, NO LOAD, PWM MODE
VOUT1
(AC)
10V/div
500mA/div
ILX1
TOC24
VIN = 24V, FSEL = OPEN
1µs/div
VLX2
10mV/div
STEADY-STATE SWITCHING WAVEFORMS,
3.3V OUTPUT, NO LOAD, PWM MODE
VOUT2
(AC)
10V/div
500mA/div
ILX2
TOC27
VIN = 24V, FSEL = OPEN
40µs/div
VLX2
100mV/div
STEADY-STATE SWITCHING WAVEFORMS,
3.3V OUTPUT, 5mA LOAD, PFM MODE
VOUT2
(AC)
10V/div
200mA/div
ILX2
TOC28
VIN = 24V, FSEL = OPEN
40µs/div
VLX1
100mV/div
STEADY-STATE SWITCHING WAVEFORMS,
5V OUTPUT, 5mA LOAD, PFM MODE
VOUT1
(AC)
10V/div
200mA/div
ILX1
TOC25
VIN = 24V, FSEL = OPEN
1µs/div
VLX2
10mV/div
STEADY-STATE SWITCHING WAVEFORMS,
3.3V OUTPUT, 1A LOAD
VOUT2
(AC)
10V/div
1A/div
ILX2
TOC26
VIN = 24V, FSEL = OPEN
Maxim Integrated
│
9
www.maximintegrated.com
MAX17521 60V, 1A, Dual-Output, High-Efciency,
Synchronous Step-Down DC-DC Converter
Typical Operating Characteristics (continued)
(VIN_ = 24V, VSGND_ = VPGND_ = 0V, CVIN_ = 2.2μF, CVCC = 1μF, VEN/UVLO_ = 1.5V, CSS_ = 3300pF, VFB_ = 0.98 x VOUT_, LX_ =
unconnected, RESET_ = unconnected, FSEL = unconnected, MODE_ = unconnected, TA = TJ = -40°C to +125°C, unless otherwise
noted. Typical values are at TA = +25°C. All voltages are referenced to SGND, unless otherwise noted.)
5V OUTPUT, 1A LOAD, BODE PLOT
GAIN
TOC31
GAIN (dB)
GAIN
PHASE
PHASE (º)
VOUT = 5V
FCR =51kHz,
FREQUENCY(Hz)
Phase Margin = 62.3°
GAIN
3.3V OUTPUT, 1A LOAD, BODE PLOT TOC32
GAIN (dB)
FREQUENCY(Hz)
PHASE (º)
V
OUT
= 3.3V
F
CR
=51K,
GAIN
PHASE
Phase Margin = 62.3°
2ms/div
500mV/div
OUTPUT SHORT-CIRCUIT PROTECTION,
5V OUTPUT
VOUT1
500mA/div
IOUT1
TOC29
2ms/div
500mV/div
OUTPUT SHORT-CIRCUIT PROTECTION,
3.3V OUTPUT
VOUT2
500mA/div
IOUT2
TOC30
Maxim Integrated
│
10
www.maximintegrated.com
MAX17521 60V, 1A, Dual-Output, High-Efciency,
Synchronous Step-Down DC-DC Converter
Typical Operating Characteristics (continued)
PIN NAME FUNCTION
1 PGND1 Power Ground Connection of Converter 1. Connect PGND1 externally to the power ground plane.
Connect SGND and PGND pins together at the ground return path of the VCC bypass capacitors.
2 VIN1 Power-Supply Input of Converter 1. The input supply range is from 4.5V to 60V. Decouple to PGND1
with a 2.2μF capacitor; place the capacitor close to the VIN1 and PGND1 pins.
3 EN/UVLO1
Enable/Undervoltage Lockout Input for Converter 1. Drive EN/UVLO1 high to enable converter 1.
Connect to the center of the resistive divider between VIN1 and SGND1 to set the input voltage at which
the converter 1 turns on. Pull up to VIN1 for always-on operation.
4 VCC1 5V LDO Output for Converter 1. Bypass VCC1 with 1μF ceramic capacitance to SGND1.
5 FB1 Feedback Input for Converter 1. Connect FB1 to the center of the resistive divider between VOUT1 and
SGND1. See the Adjusting Output Voltage section for more details.
6 SS1 Soft-start Input for Converter 1. Connect a capacitor from SS1 to SGND1 to set the soft-start time for
converter 1.
7 SGND1 Analog Ground Connection for Converter 1.
8 COMP1 Loop Compensation Pin for Converter 1. Connect an RC network from COMP1 to SGND1. See the
Loop Compensation section for more details.
TQFN
(4mm × 5mm)
TOP VIEW
MAX17521
1PGND 1
2VIN1
3EN/UVLO1
4VCC1
5FB1
6SS1
7SGND 1
EP
19 PGND 2
18 VIN2
17 EN/UVLO2
16 VCC2
15 FB2
LX1
MODE 1
SYNC
MODE 2
LX2
14 SS2
13 SGND 2
8
COMP 1
9
RESET1
10
FSEL
11
RESET2
12
COMP 2
24 23 22 21 20
+
MAX17521 60V, 1A, Dual-Output, High-Efciency,
Synchronous Step-Down DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
11
Pin Conguration
Pin Description
PIN NAME FUNCTION
9RESET1
Open-Drain RESET1 Output. The RESET1 output is driven low if FB1 drops below 92.5% of its set
value. RESET1 goes high 1024 clock cycles after FB1 rises above 95.5% of its set value. RESET1 is
valid when the device is enabled and VIN is above 4.5V.
10 FSEL
Congures the Switching Frequency of the MAX17521. Leaving FSEL unconnected sets the switching
frequency of both the converters at 560kHz. Connecting FSEL pin to SGND_ sets the switching
frequency of both the converters at 300kHz.
11 RESET2
Open-Drain RESET2 Output. The RESET2 output is driven low if FB2 drops below 92.5% of its set
value. RESET2 goes high 1024 clock cycles after FB2 rises above 95.5% of its set value. RESET2 is
valid when the device is enabled and VIN is above 4.5V.
12 COMP2 Loop Compensation Pin for Converter 2. Connect an RC network from COMP2 to SGND2. See the
Loop Compensation section for more details.
13 SGND2 Analog Ground Connection for Converter 2.
14 SS2 Soft-Start Input for Converter 2. Connect a capacitor from SS2 to SGND2 to set the soft-start time for
converter 2.
15 FB2 Feedback Input for Converter 2. Connect FB2 to the center of the resistive divider between VOUT2 and
SGND2. See the Adjusting Output Voltage section for more details.
16 VCC2 5V LDO Output for converter 2. Bypass VCC2 with 1μF ceramic capacitance to SGND2.
17 EN/UVLO2
Enable/Undervoltage Lockout Input for Converter 2. Drive EN/UVLO2 high to enable converter 2.
Connect to the center of the resistive divider between VIN2 and SGND2 to set the input voltage at which
the converter 2 turns on. Pull up to VIN2 for always on operation.
18 VIN2 Power-Supply Input of Converter 2. The input supply range is from 4.5V to 60V. Decouple to PGND2
with a 2.2μF capacitor; place the capacitor close to the VIN2 and PGND2 pins.
19 PGND2 Power Ground Connection of Converter 2. Connect PGND2 externally to the power ground plane.
Connect SGND and PGND pins together at the ground return path of the VCC bypass capacitors.
20 LX2 Switching Node of Converter 2. Connect LX2 to the switching side of the inductor.
21 MODE2
Congures Converter 2 to Operate in PWM or PFM Modes of Operation. Leave MODE2 unconnected
for PFM operation (pulse skipping at light loads). Connect MODE2 to SGND2 for constant frequency
PWM operation at all loads. See the MODE Setting section for more details.
22 SYNC Synchronizes Device to an External Clock. See the External Frequency Synchronization section for
more details.
23 MODE1
Congures Converter 1 to Operate in PWM or PFM Modes of Operation. Leave MODE1 unconnected
for PFM operation (pulse skipping at light loads). Connect MODE1 to SGND1 for constant frequency
PWM operation at all loads. See the MODE Setting section for more details.
24 LX1 Switching Node of Converter 1. Connect LX1 to the switching-side of the inductor.
– EP Exposed Pad. Connect to the SGND pins. Connect to a large copper plane below the IC to improve
heat dissipation capability.
MAX17521 60V, 1A, Dual-Output, High-Efciency,
Synchronous Step-Down DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
12
Pin Description (continued)
Block Diagram
EN/UVLO
FB
RESET_
START RESET
LOGIC
SGND
HICCUP
MAX17521
VCC
COMP
PGND
VIN
LX
PDRIVER
NDRIVER
5μA
HICCUP
SS
LDO
VCC
PWM,PFM
LOGIC
SLOPE
COMPENSATION
CURRENT
SENSE
CURRENT
SENSE
OSCILLATOR CLK
FSEL
MODE SELECTOR PWM/PFM
MODE
900mV
REFERENCE
SWITCHOVER
LOGIC
G
M
COMP
PWM
COMPARATOR
++
(Block diagram of only one step-down regulator is shown)
MAX17521 60V, 1A, Dual-Output, High-Efciency,
Synchronous Step-Down DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
13
Detailed Description
The MAX17521 dual step-down regulator operates from
4.5V to 60V and delivers up to 1A load current on each
output. Feedback voltage regulation accuracy meets
±1.7% over load, line and temperature.
The device uses a peak-current-mode control scheme.
For each output, an internal transconductance error
amplifier generates an integrated error voltage. The error
voltage sets the duty cycle using a PWM comparator, a
high-side current-sense amplifier, and a slope-compensation
generator. At each rising edge of the clock, the high-side
pMOSFET turns on and remains on until either the appro-
priate or maximum duty cycle is reached, or the peak
current limit is detected.
During the high-side MOSFET’s on-time, the inductor
current ramps up. During the second half of the switching
cycle, the high-side MOSFET turns off and the low-side
nMOSFET turns on and remains on until either the next
rising edge of the clock arrives or sink current limit is
detected. The inductor releases the stored energy as its
current ramps down, and provides current to the output
(the internal low RDSON pMOS/nMOS switches ensure
high efficiency at full load).
This device also integrates switching frequency selector pin
and individual mode of operation selector pins, enable/
undervoltage lockout (EN/UVLO) pins, programmable
soft-start pins, and open-drain RESET signals for each
output.
Mode of Operation Selection
The logic state of the MODE pins are latched when VCC
and EN/UVLO voltages exceed the respective UVLO
rising thresholds and all internal voltages are ready to
allow LX switching. If the MODE pin is open at power-
up, the corresponding output operates in PFM mode at
light loads. If the MODE pin is grounded at power-up, the
corresponding output operates in constant-frequency
PWM mode at all loads. State changes on the MODE pins
are ignored during normal operation.
PWM Mode Operation
In PWM mode, the inductor current is allowed to go negative.
PWM operation provides constant frequency operation at
all loads, and is useful in applications sensitive to switching
frequency. However, the PWM mode of operation gives
lower efficiency at light loads compared to the PFM mode
of operation.
PFM Mode Operation
PFM mode of operation disables negative inductor
current and additionally skips pulses at light loads for high
efficiency. In PFM mode, the inductor current is forced to
a fixed peak of 300mA every clock cycle until the output
rises to 103% of the nominal voltage. Once the output
reaches 103% of the nominal voltage, both the high-side
and low-side FETs are turned off and the device enters
hibernate operation until the load discharges the output to
101% of the nominal voltage. Most of the internal blocks
are turned off in hibernate operation to save quiescent
current. After the output falls below 101% of the nominal
voltage, the device comes out of hibernate operation,
turns on all internal blocks and again commences the
process of delivering pulses of energy to the output until it
reaches 103% of the nominal output voltage.
The advantage of the PFM mode is higher efficiency at
light loads because of lower quiescent current drawn
from supply. The disadvantage is that the output-voltage
ripple is higher compared to PWM mode of operation and
switching frequency is not constant at light loads.
Linear Regulator (VCC)
Two internal linear regulators (VCC1, VCC2) provide 5V
nominal supplies to power the internal blocks and the
low-side MOSFET drivers. The output of the VCC linear
regulators should be bypassed with 1μF ceramic capacitors
to SGND. The device employs two undervoltage-lockout
circuits that disable the internal linear regulators when
VCC falls below 3.7V (typ). Each of the VCC regulators
can source up to 40mA (typ) to supply the device and to
power the low-side gate drivers.
Switching Frequency Selection
The FSEL pin programs the switching frequency of both
the converters. If the FSEL pin is open at power-up, both
the outputs operate at 560 kHz switching frequency. If the
FSEL pin is grounded at power-up, both the outputs operate
at 300kHz switching frequency.
MAX17521 60V, 1A, Dual-Output, High-Efciency,
Synchronous Step-Down DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
14
Operating Input Voltage Range
The minimum and maximum operating input voltages for
a given output voltage should be calculated as follows:
OUT OUT(MAX) DCR
IN(MIN) MAX
OUT(MAX)
V (I (R 0.47))
VD
(I 0.73)
+ ×+
=
+×
OUT
IN(MAX)
SW(MAX) ON(MIN)
V
Vft
=×
where VOUT is the steady-state output voltage, IOUT
(MAX) is the maximum load current, RDCR is the DC resis-
tance of the inductor, DMAX is the maximum allowable
duty ratio, fSW(MAX) is the maximum switching frequency
and tON-MIN is the worst-case minimum switch on-time
(120ns). The following table lists the fSW(MAX) and DMAX
values to be used for calculation for different switching
frequency selection
FSEL fSW(MAX) (kHz) DMAX
OPEN 600 0.92
SGND 320 0.96
External Frequency Synchronization (SYNC)
The internal oscillator of the device can be synchronized
to an external clock signal on the SYNC pin. The external
synchronization clock frequency must be between 1.1 x fSW
and 1.4 x fSW, where fSW is the frequency selected by the
FSEL pin. The minimum external clock pulse-width high
should be greater than 50ns. See the SYNC section in the
Electrical Characteristics table for details.
Overcurrent Protection/HICCUP Mode
The device is provided with a robust overcurrent-pro-
tection scheme that protects the device under overload
and output short-circuit conditions. A cycle-by-cycle peak
current limit turns off the high-side MOSFET whenever
the high-side switch current exceeds an internal limit
of 1.6A (typ). A runaway current limit on the high-side
switch current at 1.85A (typ) protects the device under
high input voltage, short-circuit conditions when there is
insufficient output voltage available to restore the inductor
current that built up during the on period of the step-down
converter. One occurrence of the runaway current limit
triggers a hiccup mode. In addition, if due to a fault
condition, output voltage drops to 70% (typ) of its nominal
value any time after soft-start is complete, hiccup mode
is triggered.
In hiccup mode, the converter is protected by suspending
switching for a hiccup timeout period of 4096 clock cycles.
Once the hiccup timeout period expires, soft-start is
attempted again. This operation results in minimal power
dissipation under overload fault conditions.
RESET Output
The device includes two RESET comparators to moni-
tor the output voltages. The open-drain RESET outputs
require an external pull-up resistor. RESET can sink 2mA
of current while low. RESET goes high (high impedance)
1024 switching cycles after the corresponding output voltage
increases above 95.5% of the nominal regulated voltage.
RESET goes low when the output voltage drops to below
92.5% of the nominal regulated voltage. RESET also
goes low during thermal shutdown. RESET is valid when
the device is enabled and VIN is above 4.5V.
Coincident/Ratiometric Tracking and
Output Voltage Sequencing
The soft-start pins (SS_) can be used to track the output
voltages to that of another power supply at startup. This
requires connecting the SS_ pins to an external resistor
divider from the supply which needs to be tracked. The
following figures (Figure 1 to Figure 3) show the possible
ways of configuring the MAX17521 in various tracking
modes.
Figure 1. Independent Soft-Start of Each Output
SS1
SS2
MAX17521
INDEPENDENT SOFT-START
OUTPUT VOLTAGE
TIME
MAX17521 60V, 1A, Dual-Output, High-Efciency,
Synchronous Step-Down DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
15
Figure 2. Coincident Tracking of the Outputs
Figure 3. Ratiometric Tracking of the Outputs
LX1 VOUT1
SS1
SS2
VOUT1
MAX17521
COINCIDENT TRACKING
VOUT1
VOUT2
TIME
OUTPUT VOLTAGE
LX2
R3 = R5
R4 = R6
R5
R6
R1
R2
FB1
R3
R4
FB2
VOUT2
RATIOMETRIC TRACKING
VOUT1
VOUT2
TIME
OUTPUT VOLTAGE
SS1
SS2
MAX17521
FB1
FB1
R2
R1
VOUT1
LX1
FB2
R4
R3
VOUT2
LX2
MAX17521 60V, 1A, Dual-Output, High-Efciency,
Synchronous Step-Down DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
16
During power-off, the output voltages discharge to ground
at a rate which depends on the respective output capacitor
and load.
The RESET_ pins and EN/UVLO_ pins can be daisy-
chained to generate power sequencing, as shown in
Figure 4.
Prebiased Output
When the device starts into a prebiased output, both
the high-side and low-side switches of the corresponding
channel are turned off so that the converter does not
sink current from the output. High-side and low-side
switches do not start switching until the PWM comparator
commands the first PWM pulse, at which point switching
commences first with the high-side switch. The output
voltage is then smoothly ramped up to the target value in
alignment with the internal reference.
Thermal-Overload Protection
Thermal-overload protection limits total power dissipa-
tion in the device. When the junction temperature of the
device exceeds +165°C, an on-chip thermal sensor shuts
down the device, allowing the device to cool. The ther-
mal sensor turns the device on again after the junction
temperature cools by 10°C. Soft-start resets during
thermal shutdown. Carefully evaluate the total power
dissipation (see the Power dissipation section) to avoid
unwanted triggering of the thermal-overload protection in
normal operation.
Applications Information
Input Capacitor Selection
The input filter capacitor reduces peak currents drawn
from the power source and reduces noise and voltage
ripple on the input caused by the circuit’s switching. The
input capacitor RMS current requirement (IRMS) for a
single output is defined by the following equation:
OUT IN OUT
RMS OUT(MAX) IN
V (V V )
II V
×−
= ×
where, IOUT(MAX) is the maximum load current. IRMS has
a maximum value when the input voltage equals twice
the output voltage (VIN = 2 x VOUT), so IRMS(MAX) =
IOUT(MAX)/2 when only one converter is enabled. When
both the converters are enabled and are operating out-
of-phase, the RMS current is shared by both the input
capacitors and therefore the maximum RMS current
carried by each of the input capacitors is IOUT(MAX)/4.
Figure 4. Output Voltage Sequencing
OUTPUT VOLTAGE SEQUENCING
EN/UVLO1
EN/UVLO2
FB1
MAX17521
EN/UVLO1
RESET2
RESET1
R2
R1
VOUT 1
LX1
FB2
R4
R3
VOUT 2
LX2
VOUT1
RESET1 =EN/UVLO 2
VOUT2
RESET2
MAX17521 60V, 1A, Dual-Output, High-Efciency,
Synchronous Step-Down DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
17
Choose an input capacitor that exhibits less than +10°C
temperature rise at the RMS input current for optimal long-
term reliability. Use low-ESR ceramic capacitors with high-
ripple-current capability at the input. X7R capacitors are
recommended in industrial applications for their temperature
stability. When both the converters are enabled, calculate
the input capacitance using the following equation:
OUT(MAX)
IN
SW IN
0.5 I D (1 D)
CfV
× ××−
=η× ×∆
where D = VOUT/VIN is the duty ratio of the controller,
fSW is the switching frequency, ΔVIN is the allowable input
voltage ripple, and η is the efficiency.
In applications where the source is located distant from
the device input, an electrolytic capacitor should be added
in parallel to the ceramic capacitor to provide necessary
damping for potential oscillations caused by the induc-
tance of the longer input power path and input ceramic
capacitor.
Inductor Selection
Three key inductor parameters must be specified for
operation with the device: inductance value (L), inductor
saturation current (ISAT) and DC resistance (RDCR). The
switching frequency and output voltage determine the
inductor value as follows:
OUT
SW
2.2 V
Lf
×
=
where VOUT and fSW are nominal values. Select an
inductor whose value is nearest to the value calculated by
the previous formula.
Select a low-loss inductor closest to the calculated value
with acceptable dimensions and having the lowest pos-
sible DC resistance. The saturation current rating (ISAT)
of the inductor must be high enough to ensure that satu-
ration can occur only above the peak current-limit value
of 1.85A.
Output Capacitor Selection
X7R Ceramic Output capacitors are preferred due to their
stability over temperature in Industrial applications. The
output capacitor is usually sized to support a step load
of 50% of the maximum output current in the application,
such that the output voltage deviation is contained to 3%
of the output voltage change. The output capacitance
may be calculated as follows:
STEP RESPONSE
OUT
OUT
It
1
C2V
×
= × ∆
RESPONSE
C sw
0.33 1
t ()
ff
≅+
Where ISTEP is the load current step, tRESPONSE is the
response time of the controller, ΔVOUT is the allowable
output voltage deviation, fC is the target closed-loop
crossover frequency and fSW is the switching frequency.
fC is generally chosen to be 1/9th of fSW.
Soft-Start capacitor selection
The device implements adjustable soft-start operation
to reduce inrush current. A capacitor connected from
the SS pin to SGND programs the soft-start time for the
corresponding output voltage. The selected output
capacitance (CSEL) and the output voltage (VOUT) determine
the minimum required soft-start capacitor as follows:
6
SS SEL OUT
C 56 10 C V
−
≥× × ×
The soft-start time (tSS) is related to the capacitor
connected at SS (CSS) by the following equation:
SS
SS 6
C
t
5.55 10
−
≥
×
For example, to program a 1ms soft-start time, a 5.6nF
capacitor should be connected from the SS pin to SGND.
Adjusting Output Voltage
Set the output voltages with resistive voltage-dividers
connected from the positive terminal of the output capacitor
(VOUT) to SGND (see Figure 1). Connect the centre node
of the divider to the FB pin. To optimize efficiency and
output accuracy, use the following calculations to choose
the resistive divider values:
OUT
15 V
R4
0.9
×
=
OUT
R4 0.9
R5 (V 0.9)
×
=−
where R4 and R5 are in kΩ.
MAX17521 60V, 1A, Dual-Output, High-Efciency,
Synchronous Step-Down DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
18
Setting the Undervoltage-Lockout Level
The device offers an adjustable input undervoltage-
lockout level for each output. Set the voltage at which
each converter turns on with a resistive voltage-divider
connected from VIN to SGND (see Figure 2). Connect the
center node of the divider to EN/UVLO pin.
Choose R1 to be 3.3MΩ, and then calculate R2 as:
INU
R1 1.218
R2 (V 1.218)
×
=−
where VINU is the input voltage at which a particular
converter is required to turn on.
Loop Compensation for Adjustable
Output Version
The MAX17521 uses peak current-mode control scheme
and needs only simple RC networks connected from the
COMP pins to SGND to have a stable, high-bandwidth
control loop. The basic regulator loop is modeled as a
power modulator, an output feedback divider, and an error
amplifier. The power modulator has DC gain GMOD(dc),
with a pole and zero pair. The following equation defines
the power modulator DC gain:
MOD(dc)
LOAD IN SW SEL
2
G1 0.4 (0.5 D)
R Vf L
=−
++ ×
Where RLOAD = VOUT/IOUT(MAX), fSW is the switching
frequency, LSEL is the selected output inductance, D is
the duty ratio, D = VOUT/VIN.
The compensation network is shown in Figure 3.
RZ can be calculated as:
Z C SEL OUT
R 6000 f C V= ×× ×
where RZ is in Ω. Choose fC to be 1/9th of the switching
frequency.
CZ can be calculated as follows:
SEL MOD(dc)
Z
Z
CG
C2R
×
=×
CP can be calculated as follows:
P
Z SW
1
CRf
=π× ×
Figure 5. Adjusting Output Voltage
Figure 6. Setting the Undervoltage Lockout Level Figure 7. Loop Compensation for Adjustable Output Version
SGND
VOUT
FB
R4
R5
SGND
VIN
EN/UVLO
R1
R2
R
Z
CZCP
TO COMP PIN
MAX17521 60V, 1A, Dual-Output, High-Efciency,
Synchronous Step-Down DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
19
Power Dissipation
The exposed pad of the IC should be properly soldered
to the PCB to ensure good thermal contact. Ensure that
the junction temperature of the device does not exceed
+125°C under the operating conditions specified for the
power supply.
At high ambient temperatures, based on the operating
condition, the heat dissipated in the IC might exceed
the maximum junction temperature of +125°C. Heat sink
should be used to reduce θ
JA
at such operating conditions.
To prevent the part from exceeding 125°C junction
temperature, users need to do some thermal analysis.
At a particular operating condition, the power losses that
lead to temperature rise of the device are estimated as
follows:
()
2
LOSS OUT DCR
OUT
OUT OUT OUT
1
P (P ( 1) ) I R
P VI
= ×−− ×
η
= ×
where POUT is the output power, η is the efficiency of the
device and RDCR is the DC resistance of the output inductor
(refer to the Typical Operating Characteristics for more
information on efficiency at typical operating conditions).
The maximum power that can be dissipated in the 24-pin
TQFN package is 2285.7mW at +70°C temperature. The
power dissipation capability should be derated as the
temperature goes above +70°C at 28.6mW/°C. For a typical
multilayer board, the thermal performance metrics for the
package are given as:
JA
JC
35 C / W
1.8 C / W
θ=°
θ=°
The junction temperature of the device can be estimated
at any given maximum ambient temperature (TA_MAX)
from the following equation:
( )
J_MAX A _MAX JA LOSS
TT P= +θ ×
If the application has a thermal-management system that
ensures that the exposed pad of the device is maintained
at a given temperature (T
EP_MAX
) by using proper heat
sinks, then the junction temperature of the device can be
estimated at any given maximum ambient temperature as:
( )
J_MAX EP_MAX JC LOSS
TT P= +θ ×
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching loss-
es and stable operation. For a sample layout that ensures
first-pass success, refer to the MAX17521 evaluation kit
layouts available at www.maximintegrated.com. Follow
these guidelines for good PCB layout:
• All connections carrying pulsed currents must be very
short and as wide as possible. The loop area of these
connections must be made very small to reduce stray
inductance and radiated EMI.
• A ceramic input filter capacitor should be placed close
to the VIN pins of the device. The bypass capaci-
tor for the VCC pins should also be placed close to
the VCC pins. External compensation components
should be placed close to the IC and far from the
inductor. The feedback trace should be routed as far
as possible from the inductor.
• The analog small-signal ground and the power
ground for switching currents must be kept separate.
They should be connected together at a point where
switching activity is at minimum, typically the return
terminal of the VCC bypass capacitors. The ground
plane should be kept continuous as much as pos-
sible.
• A number of thermal vias that connect to a large
ground plane should be provided under the exposed
pad of the device, for efficient heat dissipation.
MAX17521 60V, 1A, Dual-Output, High-Efciency,
Synchronous Step-Down DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
20
PART PIN-PACKAGE PACKAGE-SIZE
MAX17521ATG+ 24 TQFN-EP* 4mm x 5mm
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
24 TQFN T2445+1C 21-0201 90-0083
*EP = Exposed pad.
MAX17521 60V, 1A, Dual-Output, High-Efciency,
Synchronous Step-Down DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
21
Ordering Information
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 3/15 Initial release —
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2015 Maxim Integrated Products, Inc.
│
22
MAX17521 60V, 1A, Dual-Output, High-Efciency,
Synchronous Step-Down DC-DC Converter
Revision History
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
