1
Copyright
Cirrus Logic, Inc. 2003
(All Rights Reserved)
http://www.cirrus.com
CDB4351
Evaluation Board for CS4351
Features
Demonstrates recommended layout and
grounding arrangements
CS8416 receives S/PDIF, & EIAJ-340
compatible digital audio
Headers for external PCM audio and Control
input
Requires only a digital signal source and
power supplies for a complete Digital-to-
Analog-Converter system
Description
The CDB4351 evaluation board is an excellent means
for quickly evaluating the CS4351 24-bit, high perfor-
mance stereo D/A converter. Evaluation requires an
analog signal analyzer, a digital signal source, a PC for
controlling the CS4351 (stand alone operation is also
available) and a power supply. Analog line level outputs
are provided via RCA phono jacks.
The CS8416 digital audio receiver I.C. provides the sys-
tem timing necessary to operate the Digital-to-Analog
converter and will accept S/PDIF, and EIAJ-340-compat-
ible audio data. The evaluation board may also be
configured to accept external timing and data signals for
operation in a user application during system
development.
ORDERING INFORMATION
CDB4351 Evaluation Board
CS4351
Analog Outputs
and Muting
Control
Port
Inputs for Clocks
and Data
CS8416
Digital Audio
Interface
Nov ‘03
DS566DB1
CDB4351
2DS566DB2
TABLE OF CONTENTS
1. CS4351 DIGITAL TO ANALOG CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. CS8416 DIGITAL AUDIO RECEIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. INPUT FOR CLOCKS AND DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4. POWER SUPPLY CIRCUITRY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5. GROUNDING AND POWER SUPPLY DECOUPLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6. CONTROL PORT SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7. ANALOG OUTPUT FILTERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
8. ERRATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
LIST OF FIGURES
Figure 1. System Block Diagram and Signal Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. CS4351 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. PCM Input Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. CS8416 S/PDIF Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 6. Control Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 7. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Silkscreen Top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Top Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Bottom Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CDB4351
DS566DB2 3
CDB4351 SYSTEM OVERVIEW
The CDB4351 evaluation board is an excellent means of quickly evaluating the CS4351. The
CS8416 digital audio interface receiver provides an easy interface to digital audio signal sources
including the majority of digital audio test equipment. The evaluation board also allows the user
to supply external PCM clocks and data through a header for system development.
The CDB4351 schematic has been partitioned into 6 schematics shown in Figures 2 through 7.
Each partitioned schematic is represented in the system diagram shown in Figure 1. Notice that
the system diagram also includes the interconnections between the partitioned schematics.
1. CS4351 DIGITAL TO ANALOG CONVERTER
A description of the CS4351 is included in the CS4351 datasheet.
2. CS8416 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard S/PDIF data format using a CS8416 Digital Au-
dio Receiver, Figure 5. The outputs of the CS8416 include a serial bit clock, serial data, left-right
clock, and a 128/256 Fs master clock. The CS8416 data format is selected by switch S1. The
operation of the CS8416 and a discussion of the digital audio interface is included in the CS8416
datasheet.
The evaluation board has been designed such that the input can be either optical or coax, see
Figure 5. However, both inputs cannot be driven simultaneously.
Positions 1 and 2 of S1 set the serial format for the CS8416. These should match the settings of
the CS4351 (default is both set to I2S). Position 3 of S1 sets the output MCLK to LRCK ratio of
the CS8416. This switch should be set to 256 (LO) for input Fs<=48kHz and can be either 256
(LO) or 128 (HI) for Fs>48kHz
3. INPUT FOR CLOCKS AND DATA
The evaluation board has been designed to allow interfacing to external systems via the header
J9. Header J9 allows the evaluation board to accept externally generated PCM clocks and data.
The schematic for the clock/data input is shown in Figure 4. Switch position 4 of S1 selects the
source as either CS8416 or header J9.
Please see the CS4351 datasheet for more information.
4. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by six binding posts (GND, +5 V, VL, VD, VA, and
VA_H), see Figure 7. The VD, VL, and VA supplies can be jumpered to a +3.3 V regulator and
the +5 V binding post can be jumpered to a 5 V regulator thus requiring only VA_H and GND for
ease of use. VD, VL, VA and VA_H should be set to the recommended values stated in the
CS4351 datasheet.
WARNING: Refer to the CS4351 datasheet for maximum allowable voltages levels. Operation
outside of this range can cause permanent damage to the device.
CDB4351
4DS566DB2
5. GROUNDING AND POWER SUPPLY DECOUPLING
As with any high performance converter, the CS4351 requires careful attention to power supply
and grounding arrangements to optimize performance. Figure 2 details the connections to the
CS4351 and Figures 8, 9, and 10 show the component placement and top and bottom layout.
The decoupling capacitors are located as close to the CS4351 as possible. Extensive use of
ground plane fill in the evaluation board yields large reductions in radiated noise.
6. CONTROL PORT SOFTWARE
The CDB4351 is shipped with Windows 95/98/ME based software as well as Windows
NT/2000/XP drivers for interfacing with the CS4351 control port via the DB25 connector, J16.
The software can be used to communicate with the CS4351 in either SPI or I2C mode. See the
readme.txt for more information.
7. ANALOG OUTPUT FILTERING
The analog output on the CDB4351 has been designed according to the CS4351 datasheet. This
output circuit includes an AC coupling cap, the FET mute circuit, and a single pole R and C. An
additional load resistance of 5.1 kΩ can be jumpered in (J15 and J24) to test the CS4351’s load
driving capability. The FET muting circuit may be bypassed by placing a shunt on J13 and J21.
Table 1. System Connections
CONNECTOR INPUT/OUTPUT SIGNAL PRESENT
+5V Input + 5 V power
VD Input + 3.3 V power for the CS4351 digital supply
VL Input + 1.8 V to +3.3 V power for the CS4351 serial interface
VA Input + 3.3 V power for the CS4351 low voltage analog
VA_H Input +9 V to +12 V positive supply for the CS4351 high voltage analog
GND Input Ground connection from power supply
SPDIF INPUT - J11 Input Digital audio interface input via coax
SPDIF INPUT - OPT1 Input Digital audio interface input via optical
PCM INPUT - J9 Input Input for master, serial, left/right clocks and serial data
PC Port Input/Output Parallel connection to PC for SPI / I2C control port signals
EXT CTRL I/O Input/Output I/O for SPI / I2C control port signals
AOUTA and AOUTB Output RCA line level analog outputs
CDB4351
DS566DB2 5
Table 2. CDB4351 Jumper Settings
*Default Factory Settings.
The S/C column denotes standard jumper settings for either stand-alone (S) or control port (C) operation.
8. ERRATA
CDB4351 Revision A.0
The FET muting circuit must be bypassed by placing a shunt on J13 and J21, otherwise unwant-
ed noise will occur while muted.
JUMPER /
SWITCH PURPOSE POSITION S/C FUNCTION SELECTED
J5 Selects source of voltage
for the +5V supplies
+5 V
*+5V_REG
Voltage source is +5 V binding post
Voltage source is +5 V regulator
J6 Selects source of voltage
for the VD supplies
VD
*+3.3V REG
Voltage source is VD binding post
Voltage source is +3.3 V regulator
J7 Selects source of voltage
for the VL supply
VL
*+3.3V REG
Voltage source is VL binding post
Voltage source is +3.3 V regulator
J10 Selects source of voltage
for the VA supply
VA
*+3.3V REG
Voltage source is VA binding post
Voltage source is +3.3 V regulator
S1 Sets Mode of CS8416 and
clock source
*1 = open
*2, 3, 4 = closed
Default setting is I2S mode from CS8416
See CS8416 datasheet for details
J20 Stand-Alone/Control Port
Select
DIS
*EN
S
C
Stand-Alone Mode (No PC required)
Control Port Mode (PC required)
J17 DEM(AD0/CS) HI
*LO
-
SC
See CS4351 datasheet for details
J18 DIF0(SDA/CDIN) *HI
LO
C
S
See CS4351 datasheet for details
J19 DIF1(SCL/CCLK) *HI
LO
C
S
See CS4351 datasheet for details
J15
J24
LOAD select SHUNTED
*OPEN
Adds resistor for max loading
Normal output circuit
J13
J21
Mute Disable *SHUNTED
OPEN
Bypasses FET muting
Normal output circuit
CDB4351
DS566DB2 7
Figure 2. CS4351
CDB4351
8DS566DB2
Figure 3. Analog Outputs
CDB4351
DS566DB2 9
Figure 4. PCM Input Headers
CDB4351
10 DS566DB2
Figure 5. CS8416 S/PDIF Input
CDB4351
DS566DB2 11
Figure 6. Control Port Interface
CDB4351
12 DS566DB2
Figure 7. Power Supply Connections
CDB4351
DS566DB2 13
Figure 8. Silkscreen Top
CDB4351
14 DS566DB2
Figure 9. Top Side
CDB4351
DS566DB2 15
Figure 10. Bottom Side
CDB4351
16 DS566DB2
REVISION HISTORY
Release Date Changes
DB1 18-Nov-2003 Initial Release
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is sub-
ject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised t o obtain the latest version of
relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and con-
ditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsi-
bility is assumed by Cirrus for the use of this information, including us e of this information as the basis for manufacture or sale of any items, or for infringement
of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied
under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns th e copyrights associated with the
information contained herein and gives consent for copies to be made of the information only for use within your organization wi th respect to Cirrus integrated
circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes,
or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this ma-
terial and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign
Trade Law and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED
FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS
OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE
SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOM-
ER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF
THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER
AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM
ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade-
marks or service marks of their respective owners.
I
2
C is a registered trademark of Philips Semiconductor. Purchase of I
2
C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies
conveys a license under the Philips I
2
C Patent Rights to use those components in a standard I
2
C system.
