NVM Serial Test Interface
USER MANUAL
i
Table of Contents
Section 1
Introduction ........................................................................................... 1-1
1.1 Functional Overview .................................................................................1-2
1.2 External Signals ........................................................................................1-3
1.3 Test Register.............................................................................................1-4
1.4 Address Register ......................................................................................1-4
1.5 Data Register ............................................................................................1-4
Section 2
Write Mode and Write Burst Mode........................................................ 2-1
2.1 Write and Write Burst Mode......................................................................2-1
2.1.1 Write Mode .........................................................................................2-1
2.1.2 Write Burst Mode................................................................................2-2
2.2 Loading a Page in Write Mode or Write Burst Mode.................................2-4
2.3 Finishing a Write Mode or Write Burst Mode ............................................2-6
Section 3
Read Mode and Read Burst Mode ....................................................... 3-1
3.1 Read Mode and Read Burst Mode ...........................................................3-1
3.1.1 Read Mode .........................................................................................3-1
3.1.2 Read Burst Mode................................................................................3-2
3.2 Finishing a Read Mode or Read Burst Mode............................................3-3
Section 4
Chip Write Mode ................................................................................... 4-1
Section 5
Chip Erase Mode .................................................................................. 5-1
Section 6
Write Lock Bit Mode.............................................................................. 6-1
Section 7
Read Lock Bit Mode ............................................................................. 7-1
Section 8
Partial Programming Mode ................................................................... 8-1
Table of Contents
ii
NVM Serial Test Interface User Manual 1-1
Section 1
Introduction
The Nonvolatile Memory Serial Test Interface (NVMSTI) is an interface for foundry test
purposes. It is a logic block composed of:
■Three shift registers
- Test register
- Address register
- Data register
■A decoder
■A finite state machine
It should be instanced in designs containing embedded NVM (Flash or EEPROM)
elements.
Figure 1-1. NVM Serial Test Interface Schematic
E2_TEST
E2_WE
E2_CLOCK
E2_RESET
E2_ShandLoadb
E2_SDI
E2_SDO
Test
Mux
Control
Add & Data
Test
E2_TEST
TEST_WE
TEST_CE
TEST_PAGEL
TEST_PAGEM
TEST_RSTT
TEST_TM0
TEST_TM1
TEST_TM2
TEST_TM3
TEST_TM4
TEST
_ADD<X:0>
TEST
_DI<Y:0>
functional CE_
functional WE_
functional PAGEM
functional PAGEL
functional ADD<X:0>
functional DI<Y:0>
stuck at 0 or 1
stuck at 0 or 1
stuck at 0 or 1
stuck at 0 or 1
stuck at 0 or 1
CE_
WE_
PAGEM
PAGEL
ADD<X:0>
DI<Y:0>
RSTT
TM0
TM1
TM2
TM3
TM4
RDYBSY
DO<Y:0>
RDYBSY
DO<Y:0>
E2_MGM
RDYBSY
DO<Y:0>
NVM Serial Test Interface Nonvolatile Memory
Introduction
1-2 NVM Serial Test Interface User Manual
Figure 1-2. NVMSTI Functional Block Diagram
1.1 Functional
Overview
The NVM Serial Test Interface is a finite state machine with three states:
■Test register state
■Address register state
■Data register state
At initialization, the test register is accessed. It is loaded when E2_ShandLoadb is high
by shifting the data through E2_SDI (6 clock cycles).
At the next falling edge of E2_ShandLoadb, the address register is accessed. It is
loaded when E2_ShandLoadb is high by shifting the data through E2_SDI (X clock
cycles).
At the next falling edge of E2_ShandLoadb, the data register is accessed. It is loaded
when E2_ShandLoadb is high by shifting the data through E2_SDI (Y clock cycles).
At the next falling edge of E2_ShandLoadb, the NVMSTI returns to the test register
access. Refer to Figure 1-3.
Finite
State
Machine
E2_CLOCK
E2_TEST
E2_ShandLoadb
E2_SDI
E2_RESET
RDYBSY
DO<Y:0>
Address
Chain
Data
Chain
Test Chain
(6 bits)
Decoder
E2_WE
TEST_WE
TEST_CE
TEST_PAGEL
TEST_PAGEM
TEST_RSTT
TEST_TM0
TEST_TM1
TEST_TM2
TEST_TM3
TEST_TM4
E2_SDO
TEST_DI<Y:0>
TEST_ADD<X:0>
Introduction
NVM Serial Test Interface User Manual 1-3
Figure 1-3. NVMSTI Programming Cycle
It is important to note the following:
■The clock is stopped throughout the serial interface when E2_TEST = 0.
■The MSB bit is always loaded first during the load of registers via E2_SDI.
■The LSB bit is always loaded last during a read of registers via E2_SDO.
■The test signals to the memory are generated by the decoder from the data written in
the test register.
For read, write and partial programming modes, more complex procedures are neces-
sary. These are described in the sections that follow.
1.2 External Signals The following test signals can be multiplexed with functional signals. Note that they must
be externally accessible.
Table 1-1. Test Signals Description
Signal Type Description
E2_RESET I Reset Signal
E2_TEST I Test Signal
E2_CLOCK I Clock Signal
E2_SDI I Input Signal
Introduction
1-4 NVM Serial Test Interface User Manual
1.3 Test Register The size of the test register is fixed at six bits. From the value contained in this register,
the NVMSTI generates the control signals (RSTT, CE, TM) to test the memory, depend-
ing on the mode selected.
Note that:
■These signals are loaded on the falling edge of E2_ShandLoadb.
■The Write Enable signal (E2_WE) is accessible externally to control the write pulse.
■The signals TEST_PAGEM and TEST_PAGEL are generated in a special way
because they require a pulse.
In the netlist delivered to the user, the test modes are coded as in Table 1-2 below.
Depending on the NVM used, other test modes may exist. For this reason, the test reg-
ister is fixed at six bits (64 possibilities).
1.4 Address Register The size of the address register can be parametrized and depends on memory size.
Note that addresses are loaded on the falling edge of E2_ShandLoadb.
1.5 Data Register The size of the data register can be parametrized and depends on memory size.
Note that the signal E2_SDO is equal to the signal RDYBSY if the NVMSTI is not in read
mode.
E2_SDO O Output Signal
E2_ShandLoadb I Shift and Load Signal to shift E2_SDI in the registers
E2_WE I Write Enable Signal to write in the memory (active
low)
E2_MGM I Analog Input for Margin Mode
Table 1-1. Test Signals Description (Continued)
Signal Type Description
Table 1-2. Test Mode Codes
Test Mode Code
Chip Erase 0
Chip Write 1
Write Code 2
Read Code 3
Partial Prg 4
Margin Mode 5
Read Lock Bit 6
Write Lock Bit 7
HTRB Mode 8
NVM Serial Test Interface User Manual 2-1
Section 2
Write Mode and Write Burst Mode
When writing a page, it is not necessary to fill in all addresses if the locations are contig-
uous. Only the first address is significant, as the others can be calculated from this one.
The procedure for writing a page is based on the use of the rising edge of the clock
when the NVMSTI is in write mode and in data access cycle.
The initial address is written during the address cycle and is incremented after each ris-
ing edge of the clock during a data access cycle with E2_ShandLoadb low. The
addresses that follow are loaded by staying in write mode during the address cycle or by
continuing to increment the counter.
The test codes for Write Mode and Write Burst Mode are the same.
2.1 Write and Write
Burst Mode
To write a page either Write Mode or Write Burst Mode may be chosen. The procedures
for both modes are described below.
2.1.1 Write Mode The procedure for Write Mode is:
■Enter the test mode (write code 000010) during the test register state.
■Give a rising edge of clock when E2_ShandLoadb is low to enable the TEST_PAGEM
signal during the address register state.
■Enter the address value when E2_ShandLoadb is high during the address register
state.
■Enter the data value when E2_ShandLoadb is high during the data register state.
■Give a rising edge of clock when E2_ShandLoadb is low to generate the pulse
TEST_PAGEL during the next test register state.
Refer to Figure 2-1 below.
Write Mode and Write Burst Mode
2-2 NVM Serial Test Interface User Manual
Figure 2-1. Write Mode
2.1.2 Write Burst Mode The procedure for Write Burst Mode is:
■Enter the test mode (write code 000010) during the test register state.
■Give a rising edge of clock when E2_ShandLoadb is low to enable the TEST_PAGEM
signal during the address register state.
■Enter the (address - 1) value in the address register when E2_ShandLoadb is high
during the address register state.
■Give a rising edge of clock when E2_ShandLoadb is low to increment the address
value by one during the data register state.
■Enter the data value in the data register when E2_ShandLoadb is high during the data
register state.
Refer to Figure 2-2.
Continue as follows:
■Give a rising edge of clock when E2_ShandLoadb is low to generate the pulse
TEST_PAGEL during the test register state. The data is written.
■Do nothing in the next address register state.
■Give a rising edge of clock when E2_ShandLoadb is low to increment the address
value during the next data register state.
Write Mode and Write Burst Mode
NVM Serial Test Interface User Manual 2-3
■Enter the data value in the data register when E2_ShandLoadb is high during the data
register state.
Refer to Figure 2-3.
Repeat the last four steps of the procedure until completion.
Note: In Write Burst Mode, the maximum number of data items that can be loaded is
equal to the number of words per page.
Figure 2-2. Write Burst Mode
Write Mode and Write Burst Mode
2-4 NVM Serial Test Interface User Manual
Figure 2-3. Write Burst Mode
2.2 Loading a Page
in Write Mode or
Write Burst Mode
The procedure for loading data into a page is:
■Enable the Write Enable signal (E2_WE (active low)) during the test register state (the
signal can be found at the beginning of the second test register state in Figure 2-5).
■Wait for the rising edge of RDYBSY. Refer to Figure 2-4.
■Give two rising edges of clock when E2_ShandLoadb is low to disable and enable
again the TEST_PAGEM signal during the address register state.
■Keep in memory the previous addresses or enter a new (address - 1) when
E2_ShandLoadb is high during the address cycle.
■Give a rising edge of clock when E2_ShandLoadb is low to increment the address
value by one during the data register state.
■Enter the data value in the data register when E2_ShandLoadb is high during the data
register state.
Now refer to Figure 2-5:
■Give a rising edge of clock when E2_ShandLoadb is low to generate the pulse
TEST_PAGEL during the test register state. The data is written.
Write Mode and Write Burst Mode
NVM Serial Test Interface User Manual 2-5
■Do nothing in the next address register state.
■Give a rising edge of clock when E2_ShandLoadb is low to increment the address
value by one during the data register state.
■Enter the data value in the data register when E2_ShandLoadb is high during the data
register state.
Repeat the last four steps of the procedure until completion.
Figure 2-4. Loading a Page (1)
Write Mode and Write Burst Mode
2-6 NVM Serial Test Interface User Manual
Figure 2-5. Loading a Page (2)
2.3 Finishing a Write
Mode or Write
Burst Mode
The last value is loaded after test cycle and generation of the pulse TEST_PAGEL. The
procedure for finishing is:
■Enable the signal E2_WE (active low) when E2_ShandLoadb is high during the test
register state and wait until the signal RDYBSY is disabled by stopping the clock.
■Give a rising edge of clock when E2_ShandLoadb is low to disable the TEST_PAGEM
signal during the address register state.
■Start another test sequence, if necessary.
NVM Serial Test Interface User Manual 3-1
Section 3
Read Mode and Read Burst Mode
When reading a page, it is not necessary to fill in all addresses if the locations are con-
tiguous. Only the first address is significant, as the others can be calculated from this
one.
The procedure for reading a page is based on the use of the rising edge of clock when
the NVMSTI is in Read Mode and in address cycle.
The initial address is written during the address cycle and it is incremented after each
rising edge of clock during an address access with E2_ShandLoadb low. The addresses
that follow are loaded by staying in Read Mode during an address cycle or by continuing
to increment the counter.
The test codes for Read Mode and Read Burst Mode are the same.
3.1 Read Mode and
Read Burst Mode
To read a page, either Read Mode or Read Burst Mode may be chosen. The procedures
for both modes are described below.
3.1.1 Read Mode The procedure for Read Mode is:
■Enter the test mode (read code 000011) in the test register during the test register
state.
■Enter the address value in the address register when E2_ShandLoadb is high during
the address register state.
■Give a rising edge of clock when E2_ShandLoadb is low to load the output of memory
into the data register during the data register state.
■Shift the data value in the data register when E2_ShandLoadb is high during the data
register state.
Note: Read access time is measured between the falling edge of E2_ShandLoadb
and the rising edge of the clock to load the output of memory into the data regis-
ter during the data register state.
Refer to Figure 3-1 below.
Read Mode and Read Burst Mode
3-2 NVM Serial Test Interface User Manual
Figure 3-1. Read Mode
3.1.2 Read Burst Mode The procedure for Read Burst Mode is:
■Enter the test mode (read code 000011) in the test register during the test register
state.
■Enter the address value in the address register when E2_ShandLoadb is high during
the address register state.
■Give a rising edge of clock when E2_ShandLoadb is low to load the output of memory
into the data register during the data register state.
■Shift the data value in the data register when E2_ShandLoadb is high during the data
register state.
■Do nothing in test register state.
■Give a rising edge of clock when E2_ShandLoadb is low to increment the address
during the address register state.
■Give a rising edge of clock when E2_ShandLoadb is low to load the output of memory
into the data register during the data register state.
■Shift the data value in the data register when E2_ShandLoadb is high during the data
register state. The data is output on E2_SDO.
Repeat the last four steps of the procedure until completion.
Refer to Figure 3-2 below.
Read Mode and Read Burst Mode
NVM Serial Test Interface User Manual 3-3
Figure 3-2. Read Burst Mode
3.2 Finishing a Read
Mode or Read
Burst Mode
During the test register state, load a different code.
Read Mode and Read Burst Mode
3-4 NVM Serial Test Interface User Manual
NVM Serial Test Interface User Manual 4-1
Section 4
Chip Write Mode
Start of the sequence:
■Enter the test mode (chip write code 000001) during the test register state.
■No address value is needed.
■Enter the data value (00...) when E2_ShandLoadb is high during the data register
state.
■Enable the E2_WE signal (active low) when E2_ShandLoadb is low during the next
test register state.
Figure 4-1. Chip Write Mode – Start of Sequence
NVM Serial Test Interface User Manual 5-1
Section 5
Chip Erase Mode
Start of the sequence:
■Enter the test mode (chip erase code 000000) during the test chain access.
■No address value is needed.
■Enter the data value (FF...) when E2_ShandLoadb is high during the data chain
access.
■Enable the E2_WE signal (active low) when E2_ShandLoadb is low during the next
test register state.
Figure 5-1. Chip Erase Mode – Start of Sequence
NVM Serial Test Interface User Manual 6-1
Section 6
Write Lock Bit Mode
Start of the sequence:
■Enter the test mode (write lock bit code 000111) during the test register state.
■Enter the address value when E2_ShandLoadb is high during the address register
state.
■Enter the data value when E2_ShandLoadb is high during the data register state.
Figure 6-1. Write Lock Bit Mode – Start of Sequence
Write Lock Bit Mode
6-2 NVM Serial Test Interface User Manual
End of the sequence:
■Enable the signal E2_WE when E2_ShandLoadb is high during the test register state
and wait until the signal RDYBSY is disabled by stopping the clock.
See Figure 6-2 below.
Figure 6-2. Write Lock Bit Mode – End of Sequence
NVM Serial Test Interface User Manual 7-1
Section 7
Read Lock Bit Mode
Start of the sequence:
■Enter the test mode (read lock bit code 000110) during the test register state.
■No address value is needed.
■Give a rising edge of clock when E2_ShandLoadb is low to load the output of memory
into the data register during the data register state.
■Shift the data register out when E2_ShandLoadb is high during the same data
register state.
Figure 7-1. Read Lock Bit Mode – Start of Sequence
Finishing the sequence:
■During the test register state, load a different code.
Read Lock Bit Mode
7-2 NVM Serial Test Interface User Manual
NVM Serial Test Interface User Manual 8-1
Section 8
Partial Programming Mode
The sequence is the same as Write or Write Burst Mode.
Start of the sequence:
■Enter the test mode (partial programming code 000100) during the test register state.
■Give a rising edge of clock when E2_ShandLoadb is low to enable the TEST_PAGEM
signal during the address register state.
■Enter the (address value - 1) when E2_ShandLoadb is high during the address
register state.
■Give a rising edge of clock when E2_ShandLoadb is low to increment the address
value by one during the data register state.
■Enter the data value when E2_ShandLoadb is high during the data register state.
■Give a rising edge of clock when E2_ShandLoadb is low to generate the pulse
TEST_PAGEL during the test register state.
■Do nothing in address register state.
■Give a rising edge of clock when E2_ShandLoadb is low to increment the address
value by one during the data register state.
■Enter the data value in the data register when E2_ShandLoadb is high during the data
register state.
Repeat the last four steps of the procedure until completion. Refer to Figure 8-1 and
Figure 8-2.
To write the data after the sequence data register state:
■Enable the signal E2_WE (active low) during the test register state.
■Wait for the rising edge of RDYBSY.
■To continue the sequence, give two rising edges of clock when E2_ShandLoadb is
low to disable and enable the TEST_PAGEM signal during the address register state.
Refer to Figure 8-3.
Return to the third step (“Enter the (address value - 1) when E2_ShandLoadb is high...”)
and repeat the sequence until completion.
■To finish the sequence, give a rising edge of clock when E2_ShandLoadb is low to
disable the TEST_PAGEM signal during the address register state. Refer to
Figure 8-4.
Partial Programming Mode
8-2 NVM Serial Test Interface User Manual
Figure 8-1. Partial Programming Mode – Start of Sequence (1)
Partial Programming Mode
NVM Serial Test Interface User Manual 8-3
Figure 8-2. Partial Programming Mode – Start of Sequence (2)
Partial Programming Mode
8-4 NVM Serial Test Interface User Manual
Figure 8-3. Partial Programming Mode – Continuation of Sequence (1)
Partial Programming Mode
NVM Serial Test Interface User Manual 8-5
Figure 8-4. Partial Programming Mode – End of Sequence (2)
Partial Programming Mode
8-6 NVM Serial Test Interface User Manual
Enter Title of Manual -1
Document Details
Title: NVM Serial Test Interface User Manual
Literature Number: 1311B
Status: Revision B
Publication Date: November 1999
Revision Notes
Revision A: First issue.
Revision B: E2_ShandLoad changed to E2_ShandLoadb
Published by:
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