INTEGRATED CIRC ihn DATA Slr S =| 74LVC163 Presettable synchronous 4-bit binary counter; synchronous reset Product specification Supersedes data of 1996 Aug 23 IC24 Data Handbook Philips Semiconductors 1998 May 20 PHILIPSPhilips Semiconductors Presettable synchronous 4-bit binary counter; synchronous reset Product specification 74LVC163 eee eee reer eee eee rere ee eS FEATURES Wide supply voltage range of 1.2 V to 3.6 V In accordance with JEDEC standard no. 8-1A Inputs accept voltages up 10 5.5 V CMOS low power consumption Direct interface with TTL levels Synchronous reset Synchronous counting and loading @ Two count enable inputs for nbit cascading Positive edgetriggered clock DESCRIPTION The 74LVC163 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC163 is a synchronous presettable binary counter which features an intemal look~head carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Qo to Qs) of the counters may be preset to a HIGH or LOW level. A LOW fevel at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (Dg to D3) to be loaded into the counter on the positive-going edge of the clock (provided that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET). A iow level at the master reset input (MR) sets all four outputs of the flip-flops (Q> to Qs5) to LOW level after the next positive-going transition on the clock (CP) input (provided that the set-up and hald time requirements for PE are met). This action occurs regardless of the ievels at CP, PE, CET and CEP inputs This synchronous reset feature enables the designer to modify the maximum count with only one extemal NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Qo. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: ' tpmax) (CP to TC) + tgy (CEP to CP) frmax = QUICK REFERENCE DATA GND = OV; Tamp = 25C; Ta = Tr < 2.5ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT Propagation delay C, = 50 pF CP to Q, Voc = 3.3V 49 teyeteLy CP toTC 5.7 ns CET to TC 4.5 tax maximum clock frequency 200 MHz CG, input capacitance 5.0 pF Cpp power dissipation capacitance per gate notes 1 and 2 39 pF NOTES: 1. Cpp is used to determine the dynamic power dissipation (Pp in nW) Pp = Cpp x Voc? x f, +2 (CL x Ver? x fp) where: f, = input frequency in MHz; GC, = output k fo = output frequency in MHz; Vec = supply voltage in V; Z(C_ x Voc? X fy) = sum of the outputs 2. The condition is V; = GND to Voc joad capacity in pF; ORDERING INFORMATION PACKAGES TEMPERATURE RANGE | OUTSIDE NORTH AMERICA | NORTH AMERICA | DWG NUMBER 16-Pin Plastic SO 40C to +85C 74LVC163 D 74LVC163 D SOT109-1 16-Pin Plastic SSOP Type II ~40C to +85C 74LVC163 DB 74LVC163 DB SOT338-1 16-Pin Plastic TSSOP Type | ~40C to +85C 74LVC163 PW 74LVC163PW DH SOT403-1 853-1865 19421 1998 May 20Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; FALVC163 synchronous reset PIN CONFIGURATION PIN DESCRIPTION VS PIN NUMBER SYMBOL FUNCTION mm [TH 18} Voc 1 MR asynchronous master cp [2] 15] TC reset (active LOW) bo [3] fia] co 9 cp clock input (LOW-to-HIGH, pt [4] ig] a1 edge-triggered) p2 [5] 12} a2 3,4,5,6 Do to Dg data inputs pa [6 ii} a3 7 CEP count enable inputs cep [7 Fig] CET 8 GND ground (OV) np [8] P39] PE 9 PE parallel enable input {active LOW) SF00656 10 CET count enable carry input 14,13,12,11 Qo to Qg flip-flop outputs LOGIC SYMBOL 15 TC terminal count output 16 Vee positive supply voltage * LOGIC SYMBOL (IEEE/EC) To CTR4 3 d, Q|- 44 Mt 4_1D, Q; 13 63 5 _1 De Q2 fF 12 G4 6 ] Ds Qsfp 1 C2/1,9,4+ 9 d PE CEP CET CP MR | ? 10 Voc = Pin 16 GND = Pin 8 | 2 1 SY0006S SY00066 1998 May 20Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; 7ALVC163 synchronous reset FUNCTIONAL DIAGRAM FUNCTION TABLE OPERATING INPUTS OUTPUTS one le MODES [wR] cp |cep|cer|PE}pn| an [tc Reset (clear) | 1 | T X x x | xX L L Do [P [Oe | Ps nitix {x fi yee fe S|PE A Parallel load nf t Xx x ; h H . PARALLEL LOAD CIRCUITRY Count h |t h h hn | X | count | * Hold h | X | x h | X dn * 10 | CET (do nothing) | h | X X | h | X an L NOTES: tl ee Tes * = The TC output is High when CET is High and the counter aa is at Terminal Count (HHHH) H = __ High voltage level BINARY h = _ High voltage level one setup time prior to the Low-to-High 2t cp COUNTER clock transition L = Low voltage level | = Low voltage level one setup time prior to the Low-to-High |WR_ ig clock transition q = _ Lower case letters indicate the state of the referenced Q 1, Qe, |[Q output one setup time prior to the Low-to-High clock transition X = Don'tcare 4 lta fre In T = Low-to-High clock transition syoo06a TYPICAL TIMING SEQUENCE WR STATE DIAGRAM PE Do pI D2 D3 cP ceEP CET Qo re OV. a2 a3 Te 1415 0 1 3 COUNT e INHIBIT SF00664 S00089 1998 May 20 Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one, and two; inhibitPhilips Semiconductors . Product specification Presettable synchronous 4-bit binary counter; synchronous reset 74LVC163 LOGIC DIAGRAM DO Dt D2 D3 CET Ba CEP ? G PE RA FFO FFI FF2 FF oD ar D oT D er D a op _o 44 cr op o cp 5 i al_| ' . ; | Qo Qi a2 Q3 tc SY00074 1998 May 20 5Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; 74LVC163 synchronous reset RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER CONDITIONS MIN MAX UNIT V DC supply voltage (for max. speed performance) 2.7 3.6 Vv ce DC supply voltage {for low-voltage applications) 1.2 3.6 Vi DC input voltage range 0 5.5 Vv Vo DC output voltage range 0 Voc v Tamb Operating free-air temperature range ~40 +85 C . Veo = 1.2 to 2.7V 0 20 tr Input rise and fall times Veo = 2.7 to 3.6V 0 { 10 ns/V ABSOLUTE MAXIMUM RATINGS! In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL PARAMETER CONDITIONS RATING UNIT Vec DC supply voltage 0.5 to +6.5 Vv lik DC input diode current V; <0 -50 mA Vv DC input voltage Note 2 ~0.5 to 45.5 V lox DC output diode current Vo >Vec or Vo < 0 +50 mA Vo DC output voltage Note 2 ~0.5 to Ver +0.5 Vv lo DC output source or sink current Vo =0to Voc +50 mA leno. icc DC Voc or GND current +100 mA Trig Storage temperature range ~65 to +150 a 07 Power dissipation per package Prot ~ plastic mini-pack (SO) above +70C derate linearly with 8 mW/K 500 Toso) shrink mini-pack (SSOP and | a hove 460C derate linearly with 5.5 mW/K 500 mw NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 May 20Philips Semiconductors - Product specification Presettable synchronous 4-bit binary counter; 74LVC163 synchronous reset DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions voltages are referenced to.GND (ground = OV) : LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C. | UNIT MIN TYP! | MAX Voc = 1.2V Vo Vin HIGH level input voltage < Vv Voc = 2.7 to 3.6V 2.0 Voc = 1.2V GND Vie LOW level Input voltage Vv Voc = 2.7 to 3.6V 0.8 Voc = 2.7V; V= Vay or Vics lo =-12mnA Voc -0.5 Voc = 3.0V; Vj = Vix oF Vip; lo = -100pA Vec-0.2 | Vec Vou HIGH level output voltage Vv Vee = 3.0V; V) = Vig or Vit; lo =~12mA Voco-0.6 Veo = 3.0V; Vi = Vin or Vit: lo = -24mA Veco - 1.0 Veco = 2.7V; Vi = Vy or Vy; lo = T2MA 0.40 Vor LOW level output voltage Voo =3.0Vi Vi = Ving or Viti lg = 100pA GND | 0.20 Vv Veco = 3.0V; Vj = Vin or ViL; lo = 24mA 0.55 if Input leakage current Voc = 3.6V; V; = 5.5V or GND 0.1 +5 BA lec Quiescent supply current Voc = 3.6V; Vi = Voc or GND; Ig = 0 0.1 10 pA Alec eeut pine quiescent supply currentper |v. - 2. 7V to 3.6V; Vi = Voc -0.6V; Io = 0 5 | 500 | pA NOTES: 1. All typical values are at Voc = 3.3V and Tamp = 25C. AC CHARACTERISTICS GND = 0 V; tp = t < 2.5 ns; C, = 50 pF; Ry = 5000; Tym = 40C to 485C LIMITS SYMBOL PARAMETER WAVEFORM Voc = 3.3V +0.3V Vee = 2.7V Vee = 1.2V UNIT MIN TYP! MAX MIN MAX TYP tpHe Propagation delay _ _ tPLH CP to On 1 49 8.0 9.0 24 ns tpHL Propagation delay _ _ tei CP to TC 1 5.7 9.5 1 28 ns teu Propagation delay _ _ tin CET to TC 2 45 7.8 3.8 19 ns Clock pulse width _ _ _ tw HIGH or LOW 1 4.0 1.2 5.0 ns Set-up time _ _ _ teu D, toCP 3,4 25 1.0 3.0 ns Set-up time _ - ~ teu WR. PE to cP 4 3.0 1.2 3.5 ns Set-up tine _ - ~- ty CEP, CET to CP 5 5.0 2.1 5.5 ns Hold time - _ - ~ th Dp, PE, CEP, CET, MRitocp | 9 4:and5 Ww ns Maximum clock _ . _ MH frax pulse frequency 1 125 200 110 2 NOTE: 1. These typical values are at Voc = 3.3V and Tamp = 25C. 1998 May 20 7Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; synchronous reset 74LVC163 AC WAVEFORMS Vu = 1.5 VatVoc = 2.7V y Vu =0.5* Voc at Voc < 2.7 V bas PE INPUT Voy and Vor are the typical output voltage drop that occur with the output load. GND vi CP INPUT Ve - - cs GND - - - CP INPUT VM cun___/, vi Dy INPUT 3 Vou GND Qn, TC OUTPUT The shaded areas indicate when the input is permitted Voo -- - ee eee ee . to change for predictable output performance. . SC00137_ Waveform 4, Setup and hold times for the input (D,,) and parallel enable input (PE). SyY00071 Waveform 1. Clock (CP) to outputs (Q,, TC) propagation delays, the clock pulse width and the maximum clock frequency. vy, CEP, CET INPUT GND vi CET INPUT Vv GN CP INPUT Vou GND TC OUTPUT Vou NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. syoo072 sco013e Waveform 5. CEP and CET setup and hold times. Waveform 2. Input (CET) to output (TC) propagation delays. TEST CIRCUIT Si Veo 2* Voc Vv; O Open wR o GND INPUT 5002 GND vi Vo PULSE y GENERATOR DLT. : 50pF CP INPUT Ry CLs 5008 eno Lit tl Lt 2 SWITCH POSITION SC0013 TEST Sy Vee Mi Waveform 3. Master reset (MF) pulse width, the master reset teuitpa Open <27 Voc to output (Q,, TC) propagation delays and the master reset to clock (CP) removal times. 2.7-3.6V 2.7N Svo0go3 Waveform 6. Load circuitry for switching times. 1998 May 20 8Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; 4 synchronous reset 7ALVC163 $016: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D on Cy | h aA AIR A to ee oO geo op C by detail X o a 25 5mm scale DIMENSIONS {inch dimensions are derived from the original mm dimensions) UNIT me Ay | Az | Ag | dp ce | DM] EM) e He L Lp a v w y z) | 6 mm | 175] O40 | 125 | 25 | ose} oro | o@ | aa | 27] sa || o | 06 | 25/025] 1 | o9 | ge inches | 0.060, oee| o.9| | ors nours| ae | ors {29%] se {2041 | go%s [ose] 01 | at | oone | 9028] Note 1, Plastic or metal protrusions of 0.15 mm maximum per side are not included. REPERENCES VERSION = DEE [EUROPEAN | esue DATE SOT109-1 076E07S MS-012AC &-} pebeuied 1998 May 20 9Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; ALC synchronous reset rd 163 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 D ~ + ___>{a] | 71 a eer eee | / iy \ CUREEERE J [| Ss a He "7 Brom 5 { [ iyie | | Ay YI (As) A pin 1 index t | Cl keer nut i _ Go 2.5 5mm bt scale DIMENSIONS (mm are the original dimensions) A UNIT | a | Ar | Az | As | bp [| ce | OM] EM] e | He | L | uy | @ v w y | 2M] 6 0.21 | 1.80 0.38 | 0.20) 64 | 54 7.9 1.03 | 0.9 1.00 | 8 mm |) 2.0 | oo5 | 1.65 | 975 | 025 | 009] 60 | 52 | 8] 76 | 175 | oes] o7 | 9% | 9] Ot | oss] oe Note +, Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC EIAJ PROJECTION SOT338-1 MO-150AC i ore an 1998 May 20 10Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; synchronous reset 74LVC163 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 Sede r T ay LS 7. | CY | a 1 j 7 | a Lp OYTO. _ 0 25 Simm Po DIMENSIONS (mm are the. original dimensions) unit | A | ar | Az | As | bp | OM] e@] e fre | [up] atv | wl y | 2M] o om | +30 | 888 [eas [ome | BLS? [$5 | GE ows] SF [ae [2] 85 | oe [ow] o [BTS Notes 1, Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION EC JEDEC BIAJ PROJECTION s0T403-1 MO-153 E+ orones ISSUE DATE 1998 May 20 11Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; synchronous reset 74LVC163 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specttication Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications May change in ary manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Preliminary Specification Preproduction Product Semiconductors reserves the right to make changes at any time without notice in order to improve dasign and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes Product Specification Putt ton at any time without notica, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard. cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLIGATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors. and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnity Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors Philips Semiconductors and Philips Electronics North America Corporation 811 East Arques Avenue register eligible circuits under the Semiconductor Chip Protection Act. P.O. Box 3409 Copyright Philips Electronics North America Corporation 1998 Sunnyvale, California 94088-3409 All rights reserved. Printed in U.S.A. Telephone 800-234-7381 print code Date of release: 05-96 Document order number: 9397-750-04497 Philips Semiconductors