3.3V 1K/4K/16K x36 Unidirectional Synchronous
FIFO with Bus Matching
CY7C43663AV
CY7C43643AV
CY7C43683AV
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06024 Rev. *C Revised December 26, 2002
Features
• High-speed, low-power, unidirectional, First-In
First-Out (FIFO) memories with bus-matching capabil-
ities
• 1K × 36 (CY7C43643AV)
• 4K × 36 (CY7C43663AV)
• 16K × 36 (CY7C43683AV)
• 0.25-micron CMOS for optimum speed/power
• High-speed 133-MHz operation (7.5-ns Read/Write
cycle times)
• Low power
—ICC = 60 mA
—ISB = 10 mA
• Fully asynchrono us and s imult aneous Read and Write
operation permitted
• Mailbox bypass register for each FIFO
• Parallel and serial programmable Almost Full and
Almost Empty flags
• Retransmit function
• Standard or FWFT user selectable mode
• Partial reset
• Big or Little Endian format for word or byte bus sizes
• 128-pin TQFP packaging
• Easily expandable in width and depth
Logic Block Diagram
Port A
Control
Logic Port B
Control
Logic
Mail1
Register
Input
Register
Output
Register
Write
Pointer Read
Pointer
Status
Flag Logic
Programmable
Flag Offset Timing
Mode
1K/4K/16K
× 36
Dual Ported
Memory
Mail2
Register
FIFO,
Mail1
CLKA
CSA
W/RA
ENA
MBA
RT
MRS1
PRS
FF/IR
AF
SPM
FS0/SD
FS1/SEN
A0–35
MBF2
BE/FWFT
B0–35
CLKB
CSB
W/RB
ENB
MBB
BM
SIZE
EF/OR
AE
MBF1
Mail2
Reset
Logic
Bus Matching
36
36
MRS2
Registers
CY7C43663AV
CY7C43643AV
CY7C43683AV
Document #: 38-06024 Rev. *C Page 2 of 28
Pin Configuration[1]
Note:
1. Pin-compatible to IDT723623/33/43 family.
CY7C43643AV
CY7C43663AV
CY7C43683AV
TQFP
Top View
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
FS0/SD
MRS2
FS1/SEN
GND
NC
MRS1
MBA
MBF2
NC
AF
VCC
PRS
FF/IR
CSA
ENB
W/RB
CSB
GND
NC
EF/OR
NC
AE
VCC
MBF1
MBB
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
B30
B26
B27
B28
B29
B31
NC
GND
B32
B33
B34
B35
VCC
NC
CLKB
GND
SIZE
B16
B17
B18
B19
B20
B21
B22
B23
GND
BM
B24
B25
RT
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
A2
B0
GND
A0
A1
VCC
SPM
A3
A4
A5
GND
A6
A7
A8
A9
B9
B8
B7
VCC
B6
GND
B5
B4
B3
B2
B1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
VCC
A29
GND
A30
A31
A32
A34
A35
GND
CLKA
ENA
W/RA
A12
A20
GND
A18
A19
A21
VCC
A22
GND
BE/FWFT
A23
A24
A25
A26
A27
A28
A33
72
71
70
69
68
67
66
65
B12
B10
B11
GND
B13
B14
B15
VCC
30
31
32
33
34
35
36
37
38
NC
A10
A11
GND
A13
A14
A15
A16
A17
NC
CY7C43663AV
CY7C43643AV
CY7C43683AV
Document #: 38-06024 Rev. *C Page 3 of 28
Functional Description
The CY7C436X3AV is a monolithic, high-speed, low-power,
CMOS Unidirectional Synchronous FIFO memory which
supports clock frequencies up to 133 MHz and has Read
access times as fast as 6 ns.
The CY7C436X3AV is a synchronous (clocked) FIFO,
meani ng eac h port em pl oys a synchro nou s interface. All dat a
transfers through a port are gated to the LOW-to-HIGH
transition of a port clock by enable signals. T he clocks for each
port are independent of one another and can be asynchronous
or coincident. The enables for each port are arranged to
provide a simple unidirectional interface between micropro-
cessors and/or buses with synchronous control.
Comm unicati on between ea ch port may bypas s the FIFO s via
two mailbox registers. The mailbox registers’ width matches
the sele cted Port B bus width. Each mailbox register has a flag
(MBF1 and MBF2) to signal when new mail has been stored.
T wo kinds of reset are available on the CY7C436X3A V: Master
Reset and Partial Reset . Master Reset initializes t he Read and
Write pointers to the first location of the memory array,
configures the FIFO for Big or Little Endian byte arrangement,
and selects serial flag programming, parallel flag
programming, or one of the three possible default flag offset
settings, 8, 16, or 64. The FIFO also has two Master Reset
pins , MRS1 and MRS2.
Partia l Reset also s et s the R ead an d W rite po inters to the fi rst
location of the memory. Unlike Master Reset, any settings
existing prior to Partial Reset (i.e., programming method and
parti al flag defa ult of fs ets) are r etained. Partial Re se t is useful
since it permits flushing of the FIFO memory without changing
any co nfigura tion settin gs. The FIFO ha s it s own indepe ndent
Partial Reset pin, PRS.
The CY7C436X3AV have two modes of operation: In the CY
Standard mode, the first word written to an empty FIFO is
deposited into the memory array . A Read operation is required
to access that word (along with all other words residing in
memory). In the First-Word Fall-Through Mode (FWFT), the
first l ong-word (36-bit -wide ) written to a n emp ty FIFO appea rs
automatically on the outputs, no Read operation required
(neverth eless , acc essin g subs equen t words d oes ne cess ita te
a formal Read request). The state of the FWFT/STAN pin
during FIFO operation determines the mode in use.
The FIFO has a combined Empty/Output Ready flag (EF/OR)
and a co mb ined F ull/Inp ut Ready flag (F F/IR). T he EF and FF
functio ns are s electe d in the CY S tand ard mode. EF indicate s
wheth er the memory i s empty or not. FF indic ates whether the
memory is full. The IR and OR functions are selected in the
First-W ord Fall-Th rough Mode. IR indicates whether or not the
FIFO has avai lab le memory loca tion s. O R s how s whether t he
FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
The FI FO has a prog ram ma ble Alm ost Empt y fl ag (AE ) an d a
programmable Almost Full flag (AF). AE indicates when a
selected number of words written to FIFO memory achieve a
predetermined “almost empty state.” AF indicates when a
selected number of words written to the memory achieve a
predetermined “almost full state.”[2]
FF/IR and AF are synchronized to the port clock that writes
data into its array. EF/OR and AE are s ynchronized to the port
clock that reads data from its array. Programmable offset for
AE and AF are loaded in parallel using Port A or in serial via
the SD input. Three default offset settings are also provided.
The AE th reshol d c an be set at 8, 16, o r 64 lo ca tio ns from t he
empty boundary and AF threshold can be set at 8, 16, or 64
locations from the full boundary. All these choices are made
using the FS0 and FS1 inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths.
The CY7C436X3AV are characterized for operation from
0°C– 70°C commercial and from –40°C – 85°C industrial.
Input ESD protection is greater than 2001V, and latch-up is
prevented by the use of guard rings.
Selection Guide
CY7C43643/63/83AV
–7CY7C43643/63/83AV
–10 CY7C43643/63/83AV
–15 Unit
Maximum Frequency 133 100 66.7 MHz
Maximum Access Time 6 8 10 ns
Minimum Cycle Time 7.5 10 15 ns
Minimum Data or Enable Set-Up 3 4 5 ns
Minimum Data or Enable Hold 0 0 0 ns
Maximum Flag Delay 6 8 10 ns
Active Power Supply
Current (ICC1)Commercial 60 60 60 mA
Industrial 60
CY7C43643AV CY7C43663AV CY7C43683AV
Density 1K × 36 4K × 36 16K × 36
Package 128 TQFP 128 TQFP 1 28 TQFP
Note:
2. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to two clock cycles for flag deassertion, but the flag will always
be asserted exactly when the FIFO content reaches the programmed value. Use the assertion edge for trigger if flag accuracy is required. Refer to Cypress’s
application note entitled “Designing with CY7C436xx Synchronous FIFOs” for more details on flag uncertainties.
CY7C43663AV
CY7C43643AV
CY7C43683AV
Document #: 38-06024 Rev. *C Page 4 of 28
Pin Definitions
Signal Name Description I/O Function
A0–35 Port A Data I36-bit unidirectional data port for side A.
AE Almost Empty
Flag (Port B) OProgrammable Almost Empty flag synchronized to CLKB. It is LOW when the
number of words in the FIFO is less than or equal to the value in the Almost Empty offset
register, X.[2]
AF Almost Full Flag OProgrammable Almost Full flag synchronized to CLKA. It is L OW when the number
of empty loc ations in the FIFO is les s than or equal to the valu e in the Almost Full of fset
register, Y.[2]
B0–35 Port B Data O36-bit unidirectional data port for side B.
BE/FWFT Big
Endian/First-Wor
d Fall-Through
Select
IThis is a dual-purpos e pin. During M aster Reset, a HIGH on BE will sele ct Big Endi an
operation . In this case, de pending on the bus size, th e most sig nificant byte or word on
Port A is transferre d to Po rt B firs t. A LO W on BE will s ele ct L ittle Endian operati on. In
this case , the leas t significa nt byte or word on Port A is transferred to Port B first. After
Master Rese t, t his p in s elect s the ti ming mode. A H IGH on FW FT selec ts CY S t and ard
mode, a LOW select s First-Word Fal l-Throug h Mode. On ce the timi ng mode has been
selected, the level on FWFT must be static throughout device operation.
BM Bus Match
Select (Port B) IA HIGH on this pin enables either byte or word bus wid th on Port B, depend ing on
the sta t e of SIZE. A LO W sele cts lo ng-wo rd op era tion. BM works with SI ZE and BE to
select the bus size and endi an arrang em ent for Port B. The lev el of BM must be s t ati c
throughout device operation.
CLKA Port A Clock ICLKA is a continuous clock that synchronizes all data transfers through Port A
and can be as ynchrono us or coinc ident to CL KB. FF/IR and AF are all synchronized to
the LOW-to-HIGH transition of CLKA.
CLKB Port B Clock ICLKB is a continuous clock that synchronizes all data transfers through Port B
and can be asynchronous or coincide nt to CLKA. EF/OR and AE are synchronized to
the LOW-to-HIGH transition of CLKB.
CSA Port A Chip
Select ICSA must be LOW to enable a LOW -to HIGH transition of CLKA to read (from Mail2
register) or write on Port A. The A0–35 outputs are in the high-imped ance state when
CSA is HIGH.
CSB Port B Chip
Select ICSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write
(into Mail 2 register) on Por t B. The B0–35 outputs are in the high-im pedance st ate when
CSB is HIGH.
EF/OR Empty/Output
Ready Flag (Port
B)
OThis is a dual-fun ction pin. In the C Y S tand ard mode, the EF fun ction is se lected. EF
indicates whether or not the FIFO memory is empty . In the FWFT mode, the OR function
is selected. OR indicate s the presence o f valid data on B0–35 outputs, ava ilable for
reading. EF/OR is synchronized to the LOW-to-HIGH transition of CLKB.
ENA Port A Enable IENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read (from Mail2
register) or write data on Port A.
ENB Port B Enable IENB must be HIGH to en able a LOW-to-HIGH transition of CLKB to read or write (to
Mail2 register) data on Port B.
FF/IR Port B Full/Inpu t
Ready Flag OThis is a dual- functi on pin. I n the CY S t and ard mo de, the FF func tion is select ed. FF
indicate s wheth er or not the FIFO mem ory is full. In the FWFT mo de, the IR fu nction is
selected. IR indicates whether or not there is space available for writing to the FIFO
memory. FF/IR is synchronized to the LOW-to-HIGH transition of CLKA.
FS1/SEN Flag Offset
Select 1/Serial
Enable
IFS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register
programming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select
the flag offset programming method. Three offset register programming methods are
available: automatically load one of three preset values (8, 16, or 64), parallel load from
Port A, and serial load. When serial load is selected for flag offset register programming,
FS1/SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA.
When FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into
the X and Y regist ers. The nu mber o f bit wr ites req uired t o pr ogram t he of fse t regis ters
is 20 for the CY7C43643AV, 24 for the CY7C43663AV, and 28 for the CY7C43683AV.
The first bit Write store s the Y-register MSB and the la st bi t W ri te sto r es the X-register
LSB.
FS0/SD Flag Offs et
Select 0/Serial
Data
I
CY7C43663AV
CY7C43643AV
CY7C43683AV
Document #: 38-06024 Rev. *C Page 5 of 28
MBA Port A Mailbox
Select IA HIGH level on MBA chooses a mailbox register for a Port A Read or Write
operation. When a Write operation is performed on Port A, a HIGH on MBA will write
the data into Mail1 register, a low on MBA will write the data into the FIFO memory.
MBB Port B Mailbox
Select IA HIGH level on MBB chooses a mailbox register for a Port B Read or Write
operation. When a Read operation is performed on Port B, a HIGH level on MBB selects
data from the Mail1 register for output and a LOW level selects FIFO output register
data for ou tput. Data can only be w ritten into Mail2 regis ter through Port B (MBB HIGH)
and not into the FIFO memory.
MBF1 Mail1 Register
Flag OMBF1 is set LOW by a LOW -to-HIGH transition of CLKA that writ es data to the Mail1
register . Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH
by a LOW-to-HIGH transition of CLKB when a Port B Read is selected and MBB is HIGH.
MBF1 is set HIGH following either a Master or Partial Reset.
MBF2 Mail2 Register
Flag OMBF2 is set LOW by a LOW -to-HIGH transition of CLKB that writ es data to the Mail2
register . Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH
by a LOW-to-HIGH transition of CLKA when a Port A Read is selected and MBA is HIGH.
MBF2 is set HIGH following either a Master or Partial Reset.
MRS1 Master Reset IA LOW on this pin initia liz es the F IFO Rea d and W ri t e po inters to t he f irs t lo ca tion
of memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1
selects the programming method (serial or parallel) and one of three programmable flag
default offsets. It also configures Port B for bus size and endian arrangement. Four
LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must
occur while MRS1 is LOW.
MRS2 Master Reset IA LOW on this pin initializes the Mail2 Register.
PRS Par tial Reset IA LOW on this pin initia liz es the F IFO Rea d and W ri t e po inters to t he f irs t lo ca tion
of memory and sets the Port B output register to all zeroes. During Partial Reset, the
currently selected bus size, endian arrangement, programming method (serial or
parallel), and programmable flag settings are all retained.
RT Retransmit IA LOW strobe on this pin will retransmit the data in the FIFO. This is achieved by
bringing t he Read poi nter back to l ocation zero. Th e user will sti ll need to pre form Read
operations to retransmit the data. Retransmit function applies to CY standard mode only .
SIZE Bus Size Select IA HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW
on this pin when BM is HIGH sel ec t s word (18-b it) bus size. SIZE works with BM and
BE to selec t the bus si ze and endia n arrangement for P ort B. The level of SIZE must be
static throughout device operation.
SPM Serial
Programming IA LOW on this pin selects serial programming of partial flag offsets. A HIGH on
this pin selects parallel programming or default offsets (8, 16, or 64).
W/RA Port A
Write/Read
Select
IA HIGH s elec ts a W r ite operation and a LOW selects a Read op er atio n on Por t A
for a LOW-to-HIGH transition of CLKA. The A0–35 outputs are in the high-impedance
st ate when W/RA is HIGH.
W/RB Port B
Write/Read
Select
IA LOW selects a Write ope ration and a HIGH selec ts a Re ad operation on Port B
for a LOW-to-HIGH transition of CLKB. The B0–35 outputs are in the high-impedance
st ate when W/RB is LOW.
Pin Definitions (continue d)
Signal Name Description I/O Function
CY7C43663AV
CY7C43643AV
CY7C43683AV
Document #: 38-06024 Rev. *C Page 6 of 28
Signal Description
Master Reset (MRS1, MRS2)
The FIFO memory of the CY7C436X3AV undergoes a
complete reset by taking its associa ted Master Reset (MRS1 ,
MRS2) input LOW for at least four Port A clock (CLKA) and
four Port B clock (CLKB) LOW-to-HIGH transitions. The
Master Reset input can switch asynchronously to the clocks.
A Maste r Reset initi alizes the in ternal Read a nd Write po inters
and forces the Full/Input Ready flag (FF/IR) LOW, the
Empty/Output Ready flag (EF/OR) LOW, the Almost Empty
fla g ( AE ) LO W, an d the Al mo st Ful l f la g ( AF ) H I GH . A Ma s t e r
Reset also forces the Mailbox flag (MBF1, MBF2) of the
parallel mailbox register HIGH. After a Master Reset, the
FIFO’s Fu ll/Input Ready flag is set HIGH after two clock cy cles
to begin no rmal operation . A Mast er Reset must be perform ed
on the FIFO after power up, before data is written to its
memory.
A LOW-to-HIGH transition on a FIFO Master Reset (MRS1,
MRS2) input latches the value of the Big Endian (BE) input,
determining the order by which bytes are transferred through
Port B.
A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2)
input latches the values of the Flag Select (FS0, FS1) and
Serial Programming Mode (SPM) inputs for choosing the
Almost Full and Almost Empty offset programming method
(see Almost Empty and Almost Full flag offset programming
below).
Partial Reset (PRS)
The FIFO memory of the CY7C436X3AV undergoes a limited
reset by takin g its asso ciate d Parti al Rese t (PRS) input LOW
for at least four Port A clock (CLKA) and four Port B clock
(CLKB) LOW-to-HIGH transitions. The Partial Reset inputs
can switch asynchronously to the clocks. A Partial Reset
initializes the internal Read and Write pointers and forces the
Full/Input Ready flag (FF/IR) LOW, the Empty/Output Ready
flag (EF/OR) LOW, the Almost Empty flag (AE) LOW, and the
Almost Full flag (AF) HIGH. A Partial Reset also forces the
Mailbox flag (MBF1, MBF2) of the parallel mailbox register
HIGH. After a Partial Reset, the FIFO’s Full/Input Ready flag
is set HIGH after two clock cycles to begin normal operation.
Whatever flag offsets, programming method (parallel or
serial), and timing mode (FWFT or CY Standard mode) are
currentl y selecte d at the time a Partial Res et is initiate d, those
settings will remain unchanged upon completion of the reset
operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Master Reset would be
inconvenient.
Big Endian/First-Word Fall-Through (BE/FWFT)
This i s a dual-purpo se pin. At the time of Master Reset, the BE
select function is active, permitting a choice of Big or Little
Endian byte arrangement for data written to or Read from
Port B. This sel ectio n dete rmines the o rder by which bytes (or
words) of data are transferred through this port. For the
following illustrations, assume that a byte (or word) bus size
has been selected for Port B.
A HIGH on the BE/FWFT input when the Master Reset (MRS1,
MRS2) inputs go from LOW to HIGH will select a Big Endian
arrangement. When data is moving in the direction from Port
A to Port B, the most significant byte (word) of the long-word
written to Port A will be transferred to Port B first; the least
signif icant byte (wor d) of the long-w ord written to Po rt A will be
transferred to Port B last.
A LOW on the BE/FWFT input when the Ma ster Reset (MRS1,
MRS2) input s go from LOW to HIGH will s elec t a Litt le Endi an
arrangement. When data is moving in the direction from Port
A to Port B, the least significant byte (word) of the long-word
written to Port A will be transferred to Port B first; the most
signif icant byte (wor d) of the long-w ord written to Po rt A will be
transferred to Port B last.
After Master Reset, the FWFT select function is active,
permitting a choice between two possible timing modes: CY
Standard mode or First-Word Fall-Through (FWFT) Mode.
Once the Ma ster R eset ( MRS1 , MRS2) input is HIG H, a HIGH
on the BE/FWFT input at the second LOW-to-HIGH transition
of CLKA will select CY Standard mode. This mode uses the
Empty F l ag f u nc ti o n (E F) to indicate whether or not there are
any words present in the FIFO memory. It uses the Full Flag
functio n (F F) to in dic ate whe the r or n ot the FIFO memory ha s
any free space for writing. In CY Standard mode, every word
read from the FIFO, including the first, must be requested
using a formal Read operation.
Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW
on the BE/FWFT input of the second LOW-to-HIGH transition
of CLKA will sel ect FWF T Mode. Th is mode uses the Ou tput
Ready function (OR) to indicate whether or not there is valid
data at the data outputs (B0–35). It also uses the Input Ready
(IR) function to indicate whether or not the FIFO memory has
any free space for writing. In the FWFT mode, the first word
written to an empty FIFO goes directly to data outputs, no
Read request necessary. Subsequent words must be
acce ssed by performing a f ormal Read oper ation .
Following Master Reset, the level applied to the BE/FWFT
input to choose the desired timing mode must remain static
throughout the FIFO operation.
Programming the Almost Empty and Almost Full Flags
T wo re gisters in the CY7C436X3AV are used t o hold the o ffset
values for th e Almo st Emp ty and Almost Full flags. Th e Port B
Almost Empty flag (AE ) offs et register is l abeled X. The Port A
Almost Full flag (AF) offset register is labeled Y. The index of
each register name corresponds with preset values during the
reset o f a FIF O, pro gram m ed in p a rall el us in g the FIFO ’s Port
A data inputs, or programmed in serial using the Serial Data
(SD) input (see Table 1).
To load a FIFO’s Almost Emp ty flag and Al most Full fl ag of fset
registers with one of the three preset values listed in Table 1,
the Serial Program Mode (SPM) and at least one of the
flag-select inputs must be HIGH during the LOW-to-HIGH
transition of its Master Reset input (MRS1, MRS2). For
example, to load the preset value of 64 into X and Y, SPM, FS0
and FS1 must be HIGH when the FIFO reset (MRS1, MRS2 )
returns HIGH. When using on e of the preset values for the flag
offsets, the FIFO can be reset simultaneously or at different
times.
To program the X and Y registers from Port A, perform a
Master Reset on both FIFOs simultaneously with SPM HIGH
and FS0 and FS 1 LO W du ring the LO W-to-HI GH tra nsi tio n of
MRS1, MRS2 . After this reset is complete, the first two writes
to the FIFO do not store data in RAM but load the offset
registers in the order Y and X. The Port A data inputs used by
the offset registers are (A0–9), (A0–11), or (A0–13), for the
CY7C43663AV
CY7C43643AV
CY7C43683AV
Document #: 38-06024 Rev. *C Page 7 of 28
CY7C436X3AV, respectively. The highest numbered input is
used as the most significant bit of the binary number in each
case. Valid programming values for the registers range from
0–1023 for the CY7C43643AV, 0 –4095 for the
CY7C43663AV, and 0 –16383 for the CY7C43683AV.[2]
Before programming the offset registers, FF/IR is set HIGH.
FIFOs begin normal operation after programming is complete.
To program the X and Y registers serially, initiate a Master
Reset with SPM LOW, FS0/SD LOW, and FS1/SEN HIGH
during th e LOW- to-HIGH transitio n of MRS1, MRS2. After thi s
reset is complete, the X and Y register values are loaded
bit-wise through the FS0/SD input on each LOW-to-HIGH
transition of CLKA that the FS1/SEN input is LOW. Twenty,
twenty - four, or twent y-e ight bi t writes are ne eded t o com plete
the programming for the CY7C436X3AV , respectively . The two
registers are written in the order Y then finally X. The first-bit
Write stores the most significant bit of the Y register and the
last-bit Write stores the least significant bit of the X register.
Each register value can be programmed from 0 – 1023
(CY7C43643AV), 0 – 4095 (CY7C43663AV), and 0 – 16383
(CY7C43683AV).
When the option to program the offset registers serially is
chosen, th e Port A Full/Input Re ady (FF/IR) flag remains LOW
until all register bits are written. FF/IR is set HIGH by the
LOW -to -H IGH trans iti on of CLKA after th e las t bi t is lo ade d to
allow normal FIFO operation.
SPM, FS0/SD, and FS1/SEN function the same way in both
CY St a nd ard and FWFT mode s.
FIFO Write/Read Operation
The state of the Port A data (A0–35) lines is controlled by Port
A Chip Select (CSA) and Port A Write/Read Select (W/RA).
The A0–35 lines are in the high-impedance state when either
CSA or W/RA is HIGH. The A0–35 lines are active mail2
register outputs when both CSA and W/RA are LOW.
Data is loaded into the FIFO from the A0–35 inputs on a
LOW -to-HIGH tran sition of CLKA whe n CSA is LOW, W/RA is
HIGH, ENA is HIGH, MBA is LOW, and FF/IR is HIGH (see
Table 2). FIFO writes on Port A are independent of any
concurrent Port B operation.
The P ort B c on trol si gna ls are i den tic al to th os e o f Port A with
the exception that the Port B Write/Read select (W/RB) is the
inverse of the Port A Write/Read select (W/RA). The state o f
the Port B data (B0–35) lines is controlled by the Port B Chip
Select (CSB) and Port B Write /Read select (W/RB). The B0–35
lines are in the high-impedance state when either CSB is HIGH
or W/RB is LOW. The B0–35 lines are active out puts when CSB
is LOW and W/RB is HIGH.
Data is read from the FIFO to the B0–35 outputs by a
LOW -to-HIGH tran sition of CLKB whe n CSB is LOW, W/RB is
HIGH, ENB is HIGH, MBB is LOW, and EF/OR is HIGH (see
Table 3). FIFO reads and writes on Port B are independent of
any concurrent Port A operation.
The set-u p and hold time constraint s to the po rt cl ock s for the
port Chip Selects and Write/Read Selects are only for enabling
Write and Read operations and are not related to
high-im pe dan ce contro l of the dat a outputs. If a p ort e nable is
LOW during a clock cycle, the port’s Chip Select and
Write/Read Select may change states during the set-up and
hold time window of the cycle.
When operating the FIFO in FWFT Mode with the Output
Ready flag LOW, the ne xt word w ritten is automati cally s ent to
the FIFO’s output register by the LOW-to-HIGH transition of
the port clock that sets the Output Ready flag HIGH, data
residing in the FIFO’s memory array is clocked to the output
register only when a Read is selected using the port’s Chip
Select, Write/Read Select, Enable, and Mailbox Select.
When op erating the FIFO in CY S ta ndard mod e, regardle ss of
whether the Empty Flag is LOW or HIGH, data residing in the
FIFO’s memory array is clocked to the output register only
when a Read is selected using the port’s Chip Select,
Write/Read Select, Enable, and Mailbox Select.
Synchronized FI FO Flags
Each FIFO is synchronized to its port clock through at least two
flip-flop stages. This is don e to improve flag-signal reliability by
reducing the probability of the metastable events when CLKA
and CLKB operate asynchronously to one another . EF/OR and
AE are synchronized to CLKB. FF/IR and AF are synchronized
to CLKA. Table 4 shows the relationship of each port flag to
the FIFO.
Empty/Output Ready Flags (EF/OR)
These a r e du al-p urpo se fla gs. In the FWFT Mo de, t he O utp ut
Ready (O R) fu nctio n is sel ected . When the Outpu t Re ady fl ag
is HIGH, new data is present in the FIFO output register . When
the Output Rea dy flag is LOW , the previous data word remains
in the FIFO output register and any FIFO reads are ignored.
In the CY Standard mode, the Empty Flag (EF) function is
selected. When the Empty Flag is HIGH, data is available in
the FIFO’s RAM memory for reading to the output register.
When Empty Flag is LOW, the previous data word remains in
the FIFO output register and any FIFO reads are ignored.
The Empty/Output Ready flag of a FIFO is synchronized to
CLKB. Fo r both the FWFT an d CY Standard modes, th e FIF O
Read poi nte r is incremente d each ti me a n ew w ord is c loc k ed
to its output register . The state machine that controls an Output
Ready flag monitors a Write pointer and Read pointer
comparator that indicates when the FIFO SRAM status is
empty, em pty + 1, or empty + 2.
In FWFT Mode, from the time a word is written to a FIFO, it
can be shifted to the FIFO output register in a minimum of
three cycles of the Output Ready flag synchronizing clock.
Therefore, an Output Ready flag is LOW if a word in memory
is the next data to be sent to the FIFO output register and three
cycl es have not elapse d sinc e th e ti me the w ord was wri tt en.
The Output Ready flag of the FIFO remains LOW until the third
LOW-to-HIGH transition of the synchronizing clock occurs,
simultaneously forcing the Output Ready flag HIGH and
shifting the word to the FIFO output register.
In the CY Standard mode, from the time a word is written to a
FIFO, the Empty flag will indicate the presence of data
available for reading in a minimum of two cycles of the Empty
flag synchron izing cloc k. Ther efore , an Emp ty fla g is LO W if a
word in memory is the next data to be sent to the FIFO output
register and two cycles have not elapsed since the time the
word was written. The Empty flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing
clock o ccurs , f orc ing th e Empty fl ag HIG H ; o nly t hen c an da t a
be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag
synch ronizi ng cloc k begin s the first sy nchro nizat ion cycle of a
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Document #: 38-06024 Rev. *C Page 8 of 28
Write if the clock transition occurs at time tSKEW1 or greater
after the Write. Otherwise, the subsequent clock cycle will be
the first synchronization cycle.
Full/Input Ready Flags (FF/IR)
This is a dual-purpose flag. In FWFT Mode, the Input Ready
(IR) function is selected. In CY Standard mode, the Full Flag
(FF) function is selected. For both timing modes, when the
Full/In put Rea dy fl ag i s HIGH, a mem ory loc ation is free in the
SRAM to receive new data. No memory locations are free
when the Full/Input Ready flag is LOW and any writes to the
FIFO are ignored.
The Full /Input Ready f lag of a FIF O is sy nc hro niz ed to CLKA.
For both FWF T and CY St an dard modes , eac h tim e a word is
written to a FIFO, its Write pointer is incremented. The state
machi ne that contro ls a Full/Inpu t Ready flag mon itors a Wri te
pointer and Read pointer comparator that indicates when the
FIFO SRAM status is full, full – 1, or full – 2. From the time a
word is read from a FIFO, its previous memory location is
ready to be written to in a minimum of two cycles of the
Full/Input Ready flag synchronizing clock. Therefore, a
Full/Input Ready flag is LOW if less than two cycles of the
Full/Input Ready flag synchronizing clock have elapsed since
the next memory Write location has been read. The second
LOW -to-H IGH tran sition on the Full/In put R eady fl ag sy nchro-
nizing clock after the Read sets the Full/Input Ready flag
HIGH.
A L OW- to-HIG H tr ansition on a Fu ll/Inp ut R eady f lag sync hro-
nizing cl ock be gin s th e firs t sy nc hro niz ati on cyc le of a R ea d if
the clock transition occurs at time tSKEW1 or greater after the
Read. Otherwise, the subsequent clock cycle can be the first
synchronization cycle.
Almost Empty Flags (AE)
The Almost Empty flag of the FIFO is synchronized to port B
clock. The state machine that controls an Almost Empty flag
monitors a Write pointer and Read pointer comparator that
indicates when the FIFO SRAM status is almost empty , almost
empty + 1, or almost empty + 2. The Almost Empty state is
defined by the contents of register X for AE. These registers
are loaded with preset values during a FIFO reset,
programmed from Port A, or programmed serially (see Almost
Empty flag and Almost Full flag offset programming above). An
Almost Empty flag is LOW when its FIFO contains X or less
words and is HIGH when its FIFO contains (X + 2) or more
words.[2]
The Almost Empty flag is set HIGH by the first CLKB rising
edge after two FIFO writes that fills memory to the (X + 2) level.
A LOW -to-H IGH trans ition o f CLKB begin s the firs t synchro ni-
zation cycle if it occurs at time tSKEW2 or greater after the Write
that fills the FIFO to (X + 2) words. O therwise, the subsequ ent
synchronizing clock cycle will be the first synchronization
cycle.
Almost Full Flags (AF)
The Almost Full flag of the FIFO is synchronized to port A
clock. The state machine that controls an Almost Full flag
monitors a Write pointer and Read pointer comparator that
indicates when the FIFO SRAM status is almost full, almost
full –1, or almost full – 2. The Almost Full state is defined by
the contents of register Y for AF. These registers are loaded
with preset values during a FIFO reset, programmed fro m Port
A, or programme d seri ally ( see Almos t Empt y flag and Al most
Full flag offset programming above). An Almost Full flag is
LOW when the number of words in its FIFO is greater than or
equal to (1024 – Y), (4096 – Y), or (16384 – Y), for the
CY7C436X3A V respectively . An Almost Full flag is HIGH when
the number of words in its FIFO is less than or equal to
[1024 –(Y + 2)], [4096 – (Y + 2)], or [16384 – (Y + 2)], for the
CY7C436X3AV respectively.
The Almo st Full flag i s s et HIG H by th e fi rst C L KA ris ing ed ge
after two FIFO reads that reduces the number of words in
memory to [1024/4096/16384 – (Y + 2)]. A LOW-to-HIGH
transition of CLKA begins the first synchronization cycle if it
occurs at time tSKEW2 or greater after the Read that reduces
the number of words in memory to [1024/4096/16384 –
(Y + 2)]. O therwise , the subs equent sy nchroniz ing clock cy cle
will be the firs t synchr onization cyc le.
Mailbox Registers
Each FI FO has a 36- bit byp ass regis ter to p ass command and
control information between Port A and Port B without putting
it in queue. The Mailbox Select (MBA, MBB) inputs choose
between a mail register and a FIFO for a port data transfer
operation. The usable width of both the Mail1 and Mail2
registers matches the selected bus size of Port B.
A LOW-to-HIGH transition on CLKA writes A0-35 data to the
Mail1 Regi ster when a Port A Write is selected by CSA, W/RA,
and ENA with MBA HIGH. If the selected Port A bus size is
also 36 bits, then the usable width of the Mail1 Register
empl oys da ta li ne s A 0-35. If the selected Port A bus size is 18
bit s, then th e u sa ble w idth of t he Mail1 Reg is ter employs da ta
lines A0-17. (In this case, A18-35 are don’t care inputs.) If the
selec ted Po rt A bus si ze is 9 bit s , the n th e us abl e width of the
Mail1 Register employs data lines A0–8. (In this case, A9-35 are
“Don’t Care” inputs.)
A LOW-to-HIGH transition on CLKB writes B0-35 data to the
Mail2 Regi ster when a Port B Write is selected by CSB, W/RB,
and ENB with MBB HIGH. If the selected Port B bus size is
also 36 bits, then the usable width of the Mail2 Register
employ s dat a lines B 0–35. If the s ele cte d Port B bus size is 18
bit s, then th e u sa ble w idth of t he Mail2 Reg is ter employs da ta
lines B0–17. (In this case, B18–35 are don’t care inputs.) If the
selec ted Po rt B bus si ze is 9 bit s , the n th e us abl e width of the
Mail2 R egister emp loys data lines B0-8. (In t his case, B9-35 are
“Don’t Care” inputs.)
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LOW . Attemp ted writes to a mail reg ister are
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the F IFO o utput re giste r if th e port Mail box Se lect
input is LOW and from the mail register if the port Mailbox
Select input is H IGH.
The Mail1 Register flag (MBF1) is set HIGH by a
LOW-to-HIGH transition on CLKB when a Port B Read is
selec ted by CSB, W/RB, and ENB with MBB HIGH.
The Mail2 Register flag (MBF2) is set HIGH by a
LOW-to-HIGH transition on CLKA when a Port A Read is
selec ted by CSA, W/RA, and ENA with MBA HIGH.
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the mailbox data.
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Bus Sizing
The Port B bu s can b e confi gured in a 36-bit long-word , 18-b it
word, or 9-bit byte format for data read from FIFO. The levels
applied to the Port B Bus Size Select (SIZE) and the Bus
Match Select (BM) determine t he Port B bus size. These levels
should be static throughout FIFO operation. Both bus size
selections are implemented at the completion of Master Reset,
by the time the Full/Input Ready flag is set HIGH.
Two different methods for sequencing data transfer are
available for Port B when the bus-size selection is either byte
or word size. They are referred to as Big Endian ( most signif-
icant byte first) and Little Endian (least significant byte first).
The level applied to the Big Endian Select (BE) input during
the LOW-to-HIGH transition of MRS1/MRS2 selects the
endian method t hat will b e active du ring FIFO operation . BE is
a don’t care input when the bus size selected for Port B is
long-word. The endian method is implemented at the
completion of Master Reset, by the time the Full/Input Ready
flag is set HIGH.
Only 36-bit long-word data is written to the FIFO memory on
the CY7C436X3AV. Bus-matching operations are done after
data is read from the FIFO. These bus-matching operations
are no t availab le wh en trans ferring d ata via mai lbox regi ster s.
Furtherm ore, both the word- and byte-size b us selectio ns limit
the width of the data bus that can be used for mail register
operations. In this case, only those byte lanes belonging to the
selected word- or byte-size bus can carry mailbox data. The
remaining data outputs will be indeterminate. The remaining
data inputs will be don’t care inputs. For example, when a
word-size bus is selected, then mailbox data can be trans-
mitted only between A 0–17 and B0–17. When a b yte-size bus is
selected, then mailbox data can be transmitted only between
A0–8 and B0–8.
Bus-Matching FIFO Reads
Data is read from the FIFO RAM in 36-bit long-word incre-
ment s. If a long-word bu s size is impl emented, the entir e long-
word immediately shifts to the FIFO output register. If byte or
word size is implemented on Port B, only the first one or two
bytes appear on the selected portion of the FIFO output
register, with the rest of the long-word stored in auxiliary
registe rs. In thi s case, subs equent FIFO reads out put the rest
of the long-word to the FIFO output register.
When reading data from the FIFO in the byte or word format,
the unused B9–35 or B18–35 outputs are indeterminate.
Retransmit (RT)
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. Retransmit
function applies to CY standard mode only.
The number of 36-/18-/9-bit words written into the FIFO should
be less than full depth min us 2/4/8 word s betwe en the rese t of
the FIFO (master or partial) and Retransmit setup. A LOW
pulse on RT resets the internal Read pointer to the first phys-
ical location of the FIF O. CLKA and CLKB may be free running
but ENB mus t be disab led during and tRTR after the re transmit
pulse. With every vali d Read cycle after retra nsmit, p reviou sly
accessed data is read and the Read pointer is incremented
until it is equa l to the Writ e po int er. Flags are gover ned by the
relative locations of the Read and Write pointers and are up-
dated du rin g a retra nsm it cy cl e. Da ta written to the FIFO a fter
activation of RT are transmitted also. The full depth of the FIFO
can be repeatedly retransmitted.
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Document #: 38-06024 Rev. *C Page 10 of 28
A
A27–35
B
A18–26
C
A9–17
D
A0–8
A
B27–35
B
B18–26
C
B9–17
D
B0–8
AB
CD
CD
AB
A
B
C
D
(a) L ONG WORD SI ZE
(b) WORD SIZE – BIG ENDIAN
(c) WORD SIZE – LITTLE ENDIAN
(d) BYTE SIZE – BIG ENDIAN
BE BM SIZE
XLX
BE BM SIZE
HHL
BE BM SIZE
LHL
BE BM SIZE
HHH
Write to FIFO
Read from FIFO
1st: Read from FIFO
2nd: Read from FIFO
1st: Read from FIFO
2nd: Read from FIFO
1st: Read from FIFO
2nd: Read from FIFO
3rd: Read from FIFO
4th: Read from FIFO
BYTE ORDER ON PORT A:
D
C
B
A
(e) BYTE SIZE – LITT LE ENDIAN
BE BM SIZE
LHH
1st: Read from FIFO
2nd: Read from FIFO
3rd: Read from FIFO
4th: Read from FIFO
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
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Table 1. Flag Program ming
SPM FS1/SEN FS0/SD MRS1/MRS2 X and Y Registers[3]
H H H ↑64
H H L ↑16
H L H ↑8
H L L ↑Parallel programming via Port A
L H L ↑Serial programming via SD
L H H ↑Reserved
L L H ↑Reserved
L L L ↑Reserved
Table 2. Port A Enable Function
CSA W/RA ENA MBA CLKA A0–35 Port Function
H X X X X In high-impedance state None
L H L X X In high-impedance state None
L H H L ↑In high-impedance state FIFO Write
L H H H ↑In high-impedance state Mail1 Write
L L L L X Active, Mail2 register None
L L H L ↑Active, Mail2 register None
L L L H X Active, Mail2 register None
L L H H ↑Active, Mail2 register Mail2 Read (set MBF2 HIGH)
Table 3. Port B Enable Function
CSB W/RB ENB MBB CLKB B0–35 Port Function
H X X X X In high-impedance state None
L L L X X In high-imp edance state None
L L H L ↑In high-impedance state None
L L H H ↑In high -impedance state Ma il2 Write
L H L L X Active, FIFO output register None
L H H L ↑Active, FIFO output register FIFO Read
L H L H X Active, Mail1 regis ter None
L H H H ↑Active, Mail1 regist er Mail1 Read (set MBF1 HIGH)
Note:
3. X register holds the offset for AE; Y register holds the offset for AF.
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Document #: 38-06024 Rev. *C Page 12 of 28
Table 4. FIFO Flag Operation (CY Standard and FWFT Modes)
Number of Words in FIFO Memory[2, 4, 5, 6, 7] Synchronized to CLKB Synchronized to CLKA
CY7C43643AV CY7C43663AV CY7C43683AV EF/OR AE AF FF/IR
0 0 0 L L H H
1 – X 1 – X 1 – X H L H H
(X + 1) to [1024 –
(Y + 1)] (X + 1) to [4096 –
(Y + 1)] (X + 1) to [1638 4 –
(Y + 1)] H H H H
(1024 – Y) to 1023 (4096 – Y) to 4095 (16384 – Y) to
16383 H H L H
1024 4096 16384 H H L L
Table 5. Data Size for FIFO Long-Word Reads
Size Mode[8] Data Written to FIFO Data Read From FIFO
BM SIZE BE A27–35 A18–26 A9–17 A0–8B27–35 B18–26 B9–17 B0–8
L X X A B C D A B C D
Table 6. Data Size for Word Reads
Size Mode[8] Data Written to FIFO Read No. Dat a Read From FIFO
BM SIZE BE A27–35 A18–26 A9–17 A0–8B9–17 B0–8
H L H A B C D 1 A B
2 C D
H L L A B C D 1 C D
2 A B
Table 7. Data Size for Byte Reads from FIFO
Size Mode[8] Data Written to FIFO Read No. Dat a Read From
FIFO
BM SIZE BE A27–35 A18–26 A9–17 A0–8B0–8
HHHABCD1 A
2B
3C
4D
HHLABCD1 D
2C
3B
4A
Notes:
4. X is the Almost Empty offset for FI FO used by AE. Y is the Almost Full offset for FIFO used by AF. Both X and Y are selected during a FIFO reset or Port A
programming.
5. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
6. Data in the output register does not count as a “word in FIFO memory”. Since in FWFT Mode, the first word written to an empty FIFO goes unrequested to
the output register (no Read operation necessary), it is not included in the FIFO memory count.
7. The OR and IR functions are active during FWFT mode; the EF and FF functions are active in CY Standard mode.
8. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.
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Document #: 38-06024 Rev. *C Page 13 of 28
Maximum Ratings[9,11]
(Abov e wh ic h th e us eful life ma y be imp aire d. For user gui de-
lines, not tested.)
Storage Te mperature ...................................–65°C to +150°C
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Supply Voltage to Ground Potential...............–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[10].....................................–0.5V to VCC+0.5V
DC Input Volta ge[10] .................................–0.5V to VCC+0.5V
Output Current into Outpu t s (LO W)..................... ..... ...20 mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current....................................................> 200 mA
Operating Range
Range Ambient Temperature VCC[12]
Commercial 0°C to +70°C 3.3V ± 10%
Industrial –40°C to +85°C 3.3V ± 10%
Electri cal Characteristics Over the Operating Range
Parameter Description Test Conditions
CY7C43643/63/83AV
UnitMin. Max.
VOH Output HIGH Voltage VCC = 3.0V , IOH = –2.0 mA 2.4 V
VOL Output LOW Vo ltage VCC = 3.0V , IOL = 8.0 mA 0.5 V
VIH Input HIGH Voltage 2.0 VCC V
VIL Input LOW Voltage –0.5 0.8 V
IIX Input Leaka ge Cu rren t VCC = Max. –10 +10 µA
IOZL
IOZH Output OFF, High Z
Current VSS < VO< VCC –10 +10 µA
ICC1[13] Active Power Supply
Current Commercial 60 mA
Industrial 60 mA
ISB[14] Avera ge Standby Curren t Commercial 10 mA
Industrial 10 mA
Capacitance[15]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V 4pF
COUT Output Capacitance 8pF
Notes:
9. Stresses beyond those listed under “Abso lu t e Ma xi mu m Rat in gs ” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
10. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
11. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
12. Operating VCC Range for –7 spee d is 3.3 V ± 5%.
13. Input signals switch from 0V – 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs
are unloaded.
14. All inputs = VCC – 0.2V, except CLKA and CLKB (which are at frequency = 0 MHz). All outputs are unloaded.
15. Tested initially and after any design or process changes that may affect these parameters.
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AC Test Loads and Waveforms (–10, –15)
AC Test Loads and Waveforms (–7)
Switching Characteristics Over the Operating Range
Parameter Description
CY7C43643/63/
83AV
–7
CY7C43643/
63/83AV
–10
CY7C43643/
63/83AV
–15
UnitMin. Max. Min. Max. Min. Max.
fSClock Frequency, CLKA or CLKB 133 100 67 MHz
tCLK Clock Cycle Time, CLKA or CLKB 7.5 10 15 ns
tCLKH Pulse Duration, CLKA or CLKB HIGH 3.5 4 6 ns
tCLKL Pulse Duration, CLKA or CLKB LOW 3.5 4 6 ns
tDS Set-Up T ime, A0–35 bef ore CLKA↑ and B0–35 before
CLKB↑3 4 5 ns
tENS Set-Up Time, CSA, W/RA, ENA, and MBA before
CLKA↑; CSB, W/RB, ENB, and MBB before CLKB↑3 4 5 ns
tRSTS Set-Up Time, MRS1/MRS2, PRS, RT LOW before
CLKA↑ or CLKB↑[17] 2.5 4 5 ns
tFSS Set-Up Time, FS0 and FS1 before MRS1/MRS2
HIGH 5 7 7.5 ns
tBES Set-Up Time, BE/FWFT before MRS1/MRS2 HIGH 5 7 7.5 ns
tSPMS Set-Up Ti me, SPM before MRS1/MRS2 HI GH 5 7 7.5 ns
tSDS Set-Up Time, FS0/SD before CLKA↑3 4 5 ns
tSENS Set-Up Time, FS1/SEN before CLKA↑3 4 5 ns
tFWS Set-Up Time, FWFT before CLKA↑0 0 0 ns
tDH Hold Time, A0–35 after CLKA↑ and B0–35 after
CLKB↑0 0 0 ns
tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑;
CSB, W/RB, ENB, and MBB after CLKB↑0 0 0 ns
Note:
16. CL = 5 pF for tDIS.
17. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3.0V
3.3V
OUTPUT
R2 = 680ΩCL = 30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤3ns ≤3ns
ALL INPUT PULSES
R1 = 330Ω
[16]
3.0V
GND
90%
10%
90%
10%
≤3ns ≤3ns
ALL INPUT PULSES
I/O
50Ω
V
CC
/2
Z0 = 50Ω
CY7C43663AV
CY7C43643AV
CY7C43683AV
Document #: 38-06024 Rev. *C Page 15 of 28
tRSTH Hold Time, MRS1/MRS2, PRS, RT LOW after
CLKA↑ or CLKB↑[17] 1 2 2 ns
tFSH Hold Time, FS0 and FS1 after MRS1/MRS2 HIGH 1 1 2 ns
tBEH Hold Time, BE/FWFT after MRS1/MRS2 HIGH 1 1 2 ns
tSPMH Hold Time, SPM after MRS1/MRS2 HIGH 1 1 2 ns
tSDH Hold Time, FS0/SD after CLKA↑0 0 0 ns
tSENH Hold Time, FS1/SEN after CLKA↑0 0 0 ns
tSPH Hold T ime, FS1/SEN HIGH after MRS1/MRS2 HIGH 1 1 2 ns
tSKEW1[18] Skew Time betwee n CLKA↑ and CLKB↑ for EF/OR
and FF/IR 5 5 7.5 ns
tSKEW2[18] Skew Time between CLKA↑ and CLKB↑ for AE and
AF 7 8 12 ns
tAAccess Time, CLKA↑ to A0–35 and CLKB↑ to B0–35 1 6 1 8 3 10 ns
tWFF Propagation Delay Time, CLKA↑ to FF/IR 1 6 1 8 2 10 ns
tREF Propagation Delay Time, CLKB↑ to EF/OR 1 6 1 8 2 10 ns
tPAE Propagation Delay Time, CLKB↑ to AE 1 6 1 8 1 10 ns
tPAF Propagation Delay Time, CLKA↑ to AF 1 6 1 8 1 10 ns
tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW or
MBF2 HIGH and CLKB↑ to MBF2 LOW or MBF1
HIGH
0 6 0 8 0 12 ns
tPMR Propagation Delay Time, CLKA↑ to B0–35[19] and
CLKB↑ to A0–35[20] 1 7 2 11 312 ns
tMDV Propagation Delay Time, MBA to A0–35 Valid and
MBB to B0–35 Valid 1 6 2 9 3 11 ns
tRSF Propaga tion Delay T ime, MRS1/MRS2 or PRS LOW
to AE LOW , AF HIGH,FF/ IR LOW , EF/ OR LOW and
MBF1/MBF2 HIGH
1 6 1 10 115 ns
tEN Enable Time, CSA or W/RA LOW to A0–35 Active and
CSB LOW and W/RB HIGH to B0–35 Active 1 6 2 8 2 10 ns
tDIS Disable Time, CSA or W/RA HIGH to A0–35 at High
Impedance and CSB HIGH or W/RB LOW to B0–35
at High Imped anc e
1 5 1 6 1 8 ns
tRTR Retransmit Recovery Time 90 90 90 ns
Notes:
18. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB
cycle.
19. Writing data to the Mail1 register when the B0–35 outputs are active and MBB is HIGH.
20. Writing data to the Mail2 register when the A0–35 outputs are active and MBA is HIGH.
Switching Characteristics Over the Operating Range (continued)
Parameter Description
CY7C43643/63/
83AV
–7
CY7C43643/
63/83AV
–10
CY7C43643/
63/83AV
–15
UnitMin. Max. Min. Max. Min. Max.
CY7C43663AV
CY7C43643AV
CY7C43683AV
Document #: 38-06024 Rev. *C Page 16 of 28
Switching Waveforms
Note:
21. PRS must be HIGH during Master Reset.
Master Reset Loading X and Y with a Preset Value of Eight
CLKA
tRSF
tRSF
tRSF
tWFF
tFSS tFSH
tSPMS tSPMH
tBES tBEH
tRSTH
tRSTS
tFWS
CLKB
MRS1,
MRS2
BE/FWFT
SPM
FS1/SEN,
FS0/SD
FF/IR
EF/OR
AE
AF
MBF1
[21]
tRSF
tRSF
CY7C43663AV
CY7C43643AV
CY7C43683AV
Document #: 38-06024 Rev. *C Page 17 of 28
Notes:
22. MRS1/MRS2 must be HIGH during Partial Reset.
23. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles. FIFO can only be programmed in
parallel when FF/IR is HIGH.
24. tSKEW1 is the minimum time betwee n the rising CLKA edge and a rising CLKB for FF/IR to transition HIGH in the next cycle. If the time between the rising
edge of CLKA and rising edge of CLKB is less than tSKEW1, then FF/IR may transition HIGH one cycle later than shown.
Switching Waveforms (continued)
Partial Reset (CY Standard and FWFT Modes)
tRSF
tRSF
tRSF
tRSTS tRSTH
CLKA
CLKB
PRS
FF/IR
EF/OR
AE
AF
MBF1
[22]
tWFF
tRSF
tRSF
Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(CY Standard and FWFT Modes)
tWFF
tFSS
tDS
tFSS tFSH
tFSH
tENS tENH
tDH
tSKEW1[24]
AF Of fset (Y) First Wo rd to FIFO
CLKA
MRS1,
MRS2
SPM
FS1/SEN,
FS0/SD
FF/IR
ENA
A0−35
[23]
AE Offset (X)
CY7C43663AV
CY7C43643AV
CY7C43683AV
Document #: 38-06024 Rev. *C Page 18 of 28
Notes:
25. It is not necessary to program offset register bits on consecutive clock cycles. FIFO Write attempts into the memory are ignor ed until FF/IR is set HIGH.
26. Programmable offsets are written serially to the SD input in the order AF offset (Y) then AE offset (X).
27. Read Fr om FIF O.
28. If W/RB switches from Read to Write before the assertion of CSB, tENS = tDIS + tENS.
Switching Waveforms (continued)
Serial Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values (CY Standard and FWFT Modes)
tFSS tSPH tSENS tSENH tSENH
tSENS
tSDH
tSDS tSDH
tSDS
tWFF
AF Offset (Y) MSB
tFSS tFSH
CLKA
MRS1,
MRS2
SPM
FF/IR
FS1/SEN
[25, 26]
FS0/SD [26]
AE Offset ( X) LSB
tFSS tFSH
OR
tCLKH tCLKL
tENS
tDIS
tENS tENH
tCLK
tDIS
tENH
tENS tENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV
W1[27] W2[27]
W1[27] W2[27]
W3[27]
Previous Data
No Operation
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B0–35
(Standard Mode)
B0–35
(FWFT Mode)
Port B Long-Word Read Cycle Timing for FIFO (CY Standard and FWFT Modes)
HIGH
[28]
CY7C43663AV
CY7C43643AV
CY7C43683AV
Document #: 38-06024 Rev. *C Page 19 of 28
Notes:
29. Unused bytes B18–35 contains all zeroes for wo rd-size reads.
30. Unused bytes B9–17, B18–26, and B27–35 contain all zeroes for byte-size reads.
Switching Waveforms (continued)
OR
tDIS
tENS tENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV tDIS
Previous
Read 1
Read 1
Rea d 2
Read 2
Read 3
No Operati on
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B0–17
(Standard Mode)
B0–17
(FWFT Mode)
Port B Word Read Cycle Timing for FIFO (CY Standard and FWFT Modes)[29]
HIGH
[28]
tDIS
tENStENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV tDIS
tA
tA
tA
tA
Previous
Read 1
Read 1
Read 2
Read 2
Read 3
Read 3
Read 4
Read 4
Read 5
No Operation
HIGH
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B0–8
(Standard Mode)
B0–8
(FWFT Mode)
Port B Byte Read Cycle Timing for FIFO (CY Standard and FWFT Modes)[30]
OR
[28]
CY7C43663AV
CY7C43643AV
CY7C43683AV
Document #: 38-06024 Rev. *C Page 20 of 28
Notes:
31. If Port B size is word or byte, EF is set LOW by the last word or byte Read from the FIFO, respectively.
32. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output
register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of OR HIGH and load
of the first word to the output register may occur one CLKB cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENS
tCLK
tENH
tENS
tENH
tA
tDS
W1
LOW
tDH
HIGH
HIGH
FIFO Emp ty
LOW
HIGH
LOW
Old Data in FIFO Outp ut Register W1
tENStENH
tREF tREF
tCLKH tCLKL
tCLK
tSKEW1[32]
CLKA
CSA
W/RA
MBA
ENA
FF/IR
A0–35
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B0–35
OR Flag Timing and First Data Word Fall Through whe n FIFO is Empty (FWFT Mode) [31]
CY7C43663AV
CY7C43643AV
CY7C43683AV
Document #: 38-06024 Rev. *C Page 21 of 28
Note:
33. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENS
tENH
tENS
tENH
tA
tDS
W1
LOW
tDH
HIGH
HIGH
FIFO Empty
LOW
HIGH
LOW
W1
tENS tENH
tREF tREF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[33]
CLKA
CSA
W/RA
MBA
ENA
FF/IR
A0–35
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B0–35
EF Flag Timing and First Data Read Fall Through when FIFO is Empty (CY Standard Mode) [31]
CY7C43663AV
CY7C43643AV
CY7C43683AV
Document #: 38-06024 Rev. *C Page 22 of 28
Notes:
34. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte Write of the long-word, respectively.
35. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENS tENH
tA
LOW
HIGH
HIGH
FIFO Full
LOW
HIGH
tENS tENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[35]
tDH
tDS
tENH
tENS
Previous Word in FIFO
Output Register Next W ord From FIFO
To FIFO
CLKB
CSB
W/RB
MBB
ENB
EF/OR
B0–35
CLKA
FF/IR
CSA
W/RA
MBA
ENA
A0–35
IR Flag Timing and First Available Write when FIFO is Full (FWFT Mode) [34]
LOW
CY7C43663AV
CY7C43643AV
CY7C43683AV
Document #: 38-06024 Rev. *C Page 23 of 28
Note:
36. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FF HIGH may occur one CLKA cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENS tENH
tA
LOW
HIGH
HIGH
FIFO Full
LOW
HIGH
tENS tENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[36]
tDH
tDS
tENH
tENS
Previous Word in FIFO
Output Register Next W ord Fr om FIFO
CLKB
CSB
W/RB
MBB
ENB
EF/OR
B0–35
CLKA
FF/IR
CSA
W/RA
MBA
ENA
A0−35
FF Flag Timing and First Available Write when FIFO is Full (CY Standard Mode)[34]
LOW
CY7C43663AV
CY7C43643AV
CY7C43683AV
Document #: 38-06024 Rev. *C Page 24 of 28
Notes:
37. Port A Write (CSA = LOW , W/RA = HIGH, MBA = LO W), Port B Read ( CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been
read from the FIFO.
38. D = Maximum FIFO Depth = 1K for the CY7C43643AV, 4K for the 43663AV, and 16K for the CY7C43683AV.
39. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
40. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKB cycle later than shown.
41. Port A Write (CSA = LOW , W/RA = HIGH, MBA = LO W), Port B Read ( CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been
read from the FIFO.
42. If Port B size is word or byte, AE is set LOW by the last word or byte Read from FIFO, respectively.
43. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
Switching Waveforms (continued)
Tim ing for AF when FIFO is Almost Full (CY Standard and FWFT Modes)
tENH
tENS
tPAF
tENS tENH
[D – (Y + 1)] W ord s in FIFO (D – Y ) Wor ds i n FIFO
CLKA
ENA
AF
CLKB
ENB
[2, 37, 38, 39]
[D – (Y + 2)] Wor ds in
FIFO
tSKEW2[40]
tPAF
tENS tENH
CLKA
ENA
CLKB
AE
ENB
Timing for AE when FIFO is Almost Empty (CY Standard and FWFT Modes)[ 2, 41, 42]
tENS tENH
X Word in FIFO
tENH
tENS
tSKEW2[43]
tPAE
tPAE
tENS tENH
(X+2)Words in FIFO
tENH
tENS
X Wor ds in FI FO
(X + 1) Words in FIFO (X + 2) Words in FIFO
CY7C43663AV
CY7C43643AV
CY7C43683AV
Document #: 38-06024 Rev. *C Page 25 of 28
Notes:
44. If Port B is configured for word size, data can be written to the Mail1 register using A0–17 (A18–35 are “Don’t Care” inputs). In this first case B0–17 will have
valid data (B18–35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0–8 (A9–35 are “Don’t Care”
inputs). In this second case, B0–8 will have valid data (B9–35 will be indeterminate).
45. If W/RA switches from Read to Write before the assertion of CSA, tENS = tDIS + tENS.
Switching Waveforms (continued)
tENH
tENS
tENH
tENS
tENH
tENS
tENH
tENS
tDH
tDS
W1
tPMF tPMF
tEN tMDV tPMR
tENS tENH
tDIS
FIFO Output
Register W1 (Remains valid in Mail1 Register after Read)
CLKA
CSA
W/RA
MBA
ENA
A0–35
CLKB
MBF1
CSB
W/RB
MBB
ENB
Timing for Mail1 Register and MBF1 Flag (CY Standard and FWFT Modes)[44]
B0−35
[45]
[28]
CY7C43663AV
CY7C43643AV
CY7C43683AV
Document #: 38-06024 Rev. *C Page 26 of 28
Notes:
46. If Port B is configured for word size, data can be written to the Mail2 register using B0–17 (B18–35 are don’t care inputs). In this first case A0–17 will have valid
dat a (A18–35 will b e indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0–8 (B9–35 are “Don’t Car e” inputs).
In this second case, A0–8 will have valid data (A9–35 will be indeterminate).
47. Clocks are free-running in this case. CY standard mode only. Write operation should be prohibited one Write clock cycle before the falling edge of RT, and
during the retransmit operation, i.e, when RT is LOW and tRTR after the RT ri sing edge.
48. The Empty and Full flags may change state during Retransmit as a result of the offset of the Read and Write pointers, but the Empty and Full flags will be
valid at tRTR.
49. For the AE and AF flags, two clock cycles are necessary after tRTR to update these flags.
50. The number of 36-/18-/9-bit words written into the FIFO should be less than full depth minus 2/4/8 words between the reset of the FIFO (master or partial)
and the Retr ans mit s etup .
Switching Waveforms (continued)
tENH
tENS
tENH
tENS
tENH
tENS
tENH
tENS
tDH
tDS
W1
tPMF tPMF
tEN tMDV tPMR
tENS tENH
tDIS
FIFO2 Out put
Register W1 (Remains valid in Mail2 Register after Read)
CLKB
CSB
W/RB
MBB
ENB
B0–35
CLKA
MBF2
CSA
W/RA
MBA
ENA
A0−35
Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes)[46]
[28]
[45]
FIFO Retransmit Timing
ENB
RT
t
RTR
EFB/FFA
[46, 47, 48, 49, 50]
tRSTS tRSTH
CLKA
CLKB
CY7C43663AV
CY7C43643AV
CY7C43683AV
Document #: 38-06024 Rev. *C Page 27 of 28
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. Cy press Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
All product and company names mentioned in this document are the trademarks of their respective holders.
3.3V 1K × 36 Unidirectional Synchronous FIFO with Bus Matching
Speed (ns) Ordering Code Package Name Package Type Operating Range
7CY7C43643AV-7AC A128 128-lead Thin Quad Flat Package Commercial
10 CY7C43643AV-10AC A128 128-lead Thin Quad Flat Package Commercial
15 CY7C43643AV-15AC A128 128-lead Thin Quad Flat Package Commercial
3.3V 4K × 36 Unidirectional Synchronous FIFO with Bus Matching
Speed (ns) Ordering Code Package Name Package Type Operating Range
7 CY7C43663AV-7AC A128 128-lead Thin Quad Flat Package Commercial
10 CY7C43663AV-10AC A128 128-lead Thin Quad Flat Package Commercial
15 CY7C43663AV-15AC A128 128-lead Thin Quad Flat Package Commercial
3.3V 16K × 36 Unidirectional Synchronous FIFO with Bus Matching
Speed (ns) Ordering Code Package Name PackageType OperatingRange
7 CY7C43683AV-7AC A128 128-lead Thin Quad Flat Package Commercial
10 CY7C43683AV-10AC A128 128-lead Thin Quad Flat Package Commercial
15 CY7C43683AV-15AC A128 128-lead Thin Quad Flat Package Commercial
10 CY7C43683AV-10AI A128 128-lead Thin Quad Flat Package Industrial
Package Diagram
128-lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128
51-85101-B
CY7C43663AV
CY7C43643AV
CY7C43683AV
Document #: 38-06024 Rev. *C Page 28 of 28
Document Title: CY7C43643AV/CY7C43663AV/CY7C43683AV 3.3V 1K/4K/16K x36 Unidirectional Synchronous FIFO
with Bus Matching
Document Number: 38-06024
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 107253 05/23/01 SZV Change from Spec 38-00776 to 38-06024
*A 109944 01/10/02 FSG Preliminary to final
*B 117210 08/26/02 OOR Added footnote to retransmit timing
Added note to retransmit section
*C 122276 12/26/02 RBI Power up requirements added to Maximum Ratings Information
