723614L15PFG - Integrated Device Technology

JANUARY 2009

CMOS SyncBiFIFOTM WITH

BUS-MATCHING AND BYTE SWAPPING

64 x 36 x 2

IDT723614

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBIFIFO is a trademark of Integrated Device Technology, Inc.

DSC-3146/3

FEATURES:

••

•Free-running CLKA and CLKB can be asynchronous or

coincident (simultaneous reading and writing of data on a

single clock edge is permitted)

••

•Two independent clocked FIFOs (64 x 36 storage capacity each)

buffering data in opposite directions

••

•Mailbox bypass Register for each FIFO

••

•Dynamic Port B bus sizing of 36 bits (long word), 18 bits (word),

and 9 bits (byte)

••

•Selection of Big- or Little-Endian format for word and byte bus

sizes

••

•Three modes of byte-order swapping on port B

••

•Programmable Almost-Full and Almost-Empty flags

••

•Microprocessor interface control logic

••

•EFA, FFA, AEA, and AFA flags synchronized by CLKA

••

•EFB, FFB, AEB, and AFB flags synchronized by CLKB

••

•Passive parity checking on each port

••

•Parity generation can be selected for each port

••

•Supports clock frequencies up to 67 MHz

••

•Fast access times of 10 ns

••

•Available in 132-pin plastic quad flat package (PQF) or space-

saving 120-pin thin quad flat package (TQFP)

••

•Industrial temperature range (–40°°

°°

°C to +85°°

°°

°C) is available

••

•Green parts available, see ordering information

FUNCTIONAL BLOCK DIAGRAM

Mail 1

Input

Output

CLKA

CSA

W/RA

ENA

MBA

Port-A

Control

Logic

Device

Control

RST

CLKB

CSB

W/RB

ENB

Port-B

Control

Logic

MBF1

3146 drw01

Mail 2

Write

Pointer

Read

Pointer

Status Flag

Logic

Parity

Gen/Check

- A

RAM

ARRAY

64 x 36

Parity

Generation

Parity

Gen/Check

Programmable Flag

Offset Register

Status Flag

Logic

Input

Output

RAM

ARRAY

64 x 36

Parity

Generation

Read

Pointer

PEFB

PGB

EFB

AEB

FFB

AFB

ODD/

EVEN

FFA

AFA

FS0

FS1

EFA

AEA

PGA

PEFA

MBF2

Write

Pointer

FIFO2

FIFO1

SIZ0

SIZ1

SW0

SW1

Bus Matching &

Byte Swapping

-B

Byte Matching &

Byte Swapping

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

JANUARY 14, 2009

DESCRIPTION:

The IDT723614 is a monolithic, high-speed, low-power CMOS bidirectional

clocked FIFO memory. It supports clock frequencies up to 67MHz and has read

access times as fast as 10ns. Two independent 64 x 36 dual-port SRAM FIFOs

on board the chip buffer data in opposite directions. Each FIFO has flags to

indicate empty and full conditions and two programmable flags (Almost-Full and

Almost-Empty) to indicate when a selected number of words is stored in memory.

FIFO data on port B can be input and output in 36-bit, 18-bit, and 9-bit formats

PIN CONFIGURATIONS

with a choice of big- or little-endian configurations. Three modes of byte-order

swapping are possible with any bus size selection. Communication between

each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox

passively on each port and may be ignored if not desired. Parity generation

can be selected for data read from each port. Two or more devices can be used

in parallel to create wider data paths.

NOTES:

1. Electrical pin 1 in center of beveled edge.

2. Uses Yamaichi socket IC51-1324-828.

GND

AEB

EFB

GND

AEA

EFA

GND

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

3146 drw02

117

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

GND

83 AFB

AFA

FFA

CSA

ENA

CLKA

W/RA

PGA

ODD/EVEN

PEFA

MBF2

RST

GND

SW1

SW0

SIZ1

MBF1

GND

PEFB

W/RB

CLKB

ENB

CSB

FFB

GND

MBA

SIZ0

PGB

PQFP (PQ132-1, ORDER CODE: PQF)

TOP VIEW

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IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

JANUARY 14, 2009

TQFP (PN120-1, ORDER CODE: PF)

TOP VIEW

PIN CONFIGURATIONS (CONTINUED)

This device is a clocked FIFO, which means each port employs a synchro-

nous interface. All data transfers through a port are gated to the LOW-to-HIGH

transition of a continuous (free-running) port clock by enable signals. The clocks

for each port are independent of one another and can be asynchronous or

coincident. The enables for each port are arranged to provide a simple

bidirectional interface between microprocessors and/or buses controlled by a

synchronous interface.

B22

B21

GND

B20

B19

B18

B17

B16

B15

B14

B13

B12

B11

B10

GND

VCC

GND

EFB

AEB

AFB

A23

A22

A21

GND

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

GND

VCC

GND

EFA

AEA

3146 drw03

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

AFA

FFA

CSA

ENA

CLKA

W/RA

VCC

PGA

PEFA

MBF2

MBA

FS1

FS0

ODD/EVEN

RST

GND

SW1

SW0

SIZ1

SIZ0

MBF1

PEFB

PGB

VCC

W/RB

CLKB

ENB

CSB

FFB

60 B23

A24

A25

A26

VCC

A27

A28

A29

GND

A30

A31

A34

A35

B35

GND

B34

B33

B32

B30

B31

GND

B29

B28

B27

VCC

B26

B25

B24

A32

A33

The Full Flag (FFA, FFB) and Almost-Full flag (AFA, AFB) of a FIFO are

two-stage synchronized to the port clock that writes data to its array. The Empty

Flag (EFA, EFB) and Almost-Empty (AEA, AEB) flag of a FIFO are two stage

synchronized to the port clock that reads data from its array.

The IDT723614 is characterized for operation from 0°C to 70°C.

NOTE:

1. Pin 1 identifier in corner.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

JANUARY 14, 2009

Symbol Name I/O Description

A0-A35 Port A Data I/O 36-bit bidirectional data port for side A.

AEA Port A Almost-Empty O Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of 36-bit

Flag (Port A) words in FIFO2 is less than or equal to the value in the offset register, X.

AEB Port B Almost-Empty O

Programmable Almost-Empty flag synchronized to CLKB. It is LOW when

the number of 36-bit

Flag (Port B) words in FIFO1 is less than or equal to the value in the offset register, X.

AFA Port A Almost-Full O Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of 36-bit empty

Flag (Port A) locations in FIFO1 is less than or equal to the value in the offset register, X.

AFB Port B Almost-Full O Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of 36-bit empty

Flag (Port B) locations in FIFO2 is less than or equal to the value in the offset register, X.

B0-B35 Port B Data I/O 36-bit bidirectional data port for side B.

BE Big-endian select I Selects the bytes on port B used during byte or word data transfer. A LOW on BE selects the most

most significant bytes on B0-B35 for use, and a HIGH selects the least significant bytes.

CLKA Port A Clock I

CLKA is a continuous clock that synchronizes all data transfers through port

A and can be

asynchronous or coincident to CLKB. EFA, FFA, AFA, and AEA are synchronized to the

LOW-to-HIGH transition of CLKA.

CLKB Port B Clock I

CLKB is a continuous clock that synchronizes all data transfers through port

B and can be

asynchronous or coincident to CLKA. Port B byte swapping and data port sizing operations are

also synchronous to the LOW-to-HIGH transi

tion of CLKB. EFB, FFB, AFB, and AEB are synchro-

nized to the LOW-to-

HIGH transition of CLKB.

CSA Port A Chip Select I CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.

The A0-A35 outputs are in the high-impedance state when CSA is HIGH.

CSB Port B Chip Select I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.

The B0-B35 outputs are in the high-impedance state when CSB is HIGH.

EFA Port A Empty Flag O EFA is synchronized to the LOW-to-HIGH transition of CLKA. When EFA is LOW, FIFO2 is

(Port A) empty, and reads from its memory are disabled. Data can be read from FIFO2 to the output

the second LOW-to-HIGH transition of CLKA after data is loaded into empty FIFO2 memory.

EFB Port B Empty Flag O EFB is synchronized to the LOW-to-HIGH transition of CLKB. When EFB is LOW, the FIFO1 is

(Port B) empty, and reads from its memory are disabled. Data can be read from FIFO1 to the output

second LOW-to-HIGH transition of CLKB after data is loaded into empty FIFO1 memory.

ENA Port A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.

ENB Port B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.

FFA Port A Full Flag O FFA is synchronized to the LOW-to-HIGH transition of CLKA. When FFA is

LOW, FIFO1

is full,

(Port A)

and writes to its memory are disabled. FFA is forced

LOW when the device is reset and is set

HIGH by the second LOW-to-HIGH transition of CLKA after reset.

FFB Port B Full Flag O FFB is synchronized to the LOW-to-HIGH transition of CLKB. When FFB is

LOW, FIFO2 is full,

(Port B)

and writes to its memory are disabled. FFB is forced

LOW when the device is reset and is set

HIGH by the second LOW-to-HIGH transition of CLKB after reset.

FS1, FS0 Flag-Offset Selects I The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which

selects one of

four preset values for the Almost-Full flag and Almost-Empty

flag offset.

M BA Port A Mailbox I A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the

Select A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register foroutput,

and a LOW level selects FIFO2 output register data for output.

MBF1 Mail1 Register Flag O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the

mail1 register.

Writes to the mail1 register are inhibited while MBF1 is set

LOW. MBF1 is set HIGH by aLOW-to-

HIGH transition of CLKB when a port B read is

selected and both SIZ1 and SIZ0 are HIGH.

MBF1 is set HIGH when the

device is reset.

MBF2 Mail2 Register Flag O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the

mail2 register.

Writes to the mail2 register are inhibited while MBF2 is set

LOW. MBF2 is set HIGH by a LOW-to-

HIGH transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is set HIGH

when the device is reset.

PIN DESCRIPTION

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

JANUARY 14, 2009

PIN DESCRIPTION (CONTINUED)

Symbol Nam e I/O Description

ODD/ Odd/Even Parity I

Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity

is checked when

EVEN Select ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity

generation is enabled for a read operation.

PEFA Port A Parity Error O

When any byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes

are organized as

Flag (Port A) A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the

parity bit. The type of parity checked is determined by the state of the ODD/EVEN input.

The parity trees used to check the A0-A35 inputs are s

hared by the mail2 register to generate

parity if parity generation is selected by PGA. Therefore, if a mail2 read parity generation is setup

by having W/RA LOW, MBA HIGH, and PGA HIGH, the PEFA flag is forced HIGH regardless of the

A0-A35 inputs.

PEFB Port B Parity Error O

When any valid byte applied to terminals B0-B35 fails parity, PEFB is LOW.

Bytes

are organized

Flag (Port B)

as B0-B8, B9-B17, B18-B26, B27-B35 with the most significant

bit of each byte serving as the parity

bit. A byte is valid when it is used by the bus

size selected for Port B. The type of parity checked is

determined by the state of the ODD/EVEN input.

The parity trees used to check the B0-B35 inputs are shared by the mail 1 register to generate parity if

parity generation is selected by PGB. Therefore, if a mail1

read

with parity generation is setup by

having W/RB LOW, SIZ1 and SIZ0 HIGH,

and PGB HIGH, the PEFB flag is forced HIGH regardless

of the state of the B0-B35 inputs.

P GA Port A Parity I Parity is generated for data reads from port A when PGA is HIGH. The type of parity generated is

Generation selected by the state of the ODD/EVEN input. Bytes are organized as A0-A8, A9-A17, A18-A26,

and A27-A35. The generated parity bits are output in the most significant bit of each byte.

P GB Port B Parity I Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is

Generation selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26,

and B27-B35. The generated parity bits are output in the most significant bit of each byte.

RST Reset I To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of

CLKB must occur while RST is LOW. This sets the AFA, AFB, MBF1, and MBF2 flags HIGH and

the EFA, EFB, AEA, AEB, FFA, and FFB flags LOW. The LOW-to-HIGH transition of RST latches

the status of the FS1 and FS0 inputs to select Almost-Full and Almost-Empty flag offsets.

SI Z0, SIZ 1 Port B Bus Size I

A LOW-to-HIGH transition of CLKB latches the states of SIZ0, SIZ1, and BE,

and the following

Selects (Port B)

LOW-to-HIGH transition of CLKB implements the latched states as a port B bus size. Port B bus sizes

can be long word, word, or byte. A high on both SIZ0 and SIZ1 accesses the mailbox registers for

a port B 36-bit write or read.

SW0, SW1 Port B byte Swap I

At the beginning of each long word transfer, one of four modes of byte-order swapping is selected by

Select (Port B)

SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-

order swapping is possible with any bus-size selection.

W/RA Port A Write/Read I A HIGH selects a write operation and a LOW selects a read operation on for a LOW-to-HIGH port A

Select transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is HIGH.

W/RB Port B Write/Read I A HIGH selects a write operation and a LOW selects a read operation on for a LOW-to-HIGH port B

Select B transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is HIGH.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

JANUARY 14, 2009

ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE

RANGE (UNLESS OTHERWISE NOTED)(1)

Symbol Rating Commercial Unit

VCC Supply Voltage Range –0.5 to 7 V

VI(2) Input Voltage Range –0.5 to VCC+0.5 V

VO(2) Output Voltage Range –0.5 to VCC+0.5 V

IIK Input Clamp Current, (VI < 0 or VI > VCC) ±20 mA

IOK Output Clamp Current, (VO < 0 or VO > VCC) ±50 mA

IOUT Continuous Output Current, (VO = 0 to VCC) ±50 mA

ICC Continuous Current Through VCC or GND ±500 mA

TSTG Storage Temperature Range –65 to 150 °C

NOTES:

1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device

at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended

periods may affect device reliability.

2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 4.5 5.5 V

VIH HIGH Level Input Voltage 2 – V

VIL LOW-Level Input Voltage – 0.8 V

IOH HIGH-Level Output Current – – 4 mA

IOL LOW-Level Output Current – 8 mA

TAOperating Free-air Temperature 0 70 °C

RECOMMENDED OPERATING

CONDITIONS

ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING

FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)

Parameter Test Conditions Min. Typ.(1) Max. Unit

VOH VCC = 4.5V, IOH = –4 mA 2.4 V

VOL VCC = 4.5 V, IOL = 8 mA 0.5 V

IIVCC = 5.5 V, VI = VCC or 0 ±50 µA

IOZ VCC = 5.5 V, VO = VCC or 0 ±50 µA

ICC(2) VCC = 5.5 V, IO = 0 mA, VI = VCC or GND 1 mA

CIN VI = 0, f = 1 MHz 4 pF

COUT VO = 0, f = 1 MHZ 8 pF

NOTES:

1 . All typical values are at VCC = 5 V, TA = 25°C.

2. For additional ICC information, see the following page.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

JANUARY 14, 2009

CALCULATING POWER DISSIPATION

The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT723614 with CLKA and CLKB set

to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to

normalize the graph to a zero-capacitance load. Once the capacitive lead per data-output channel is known, the power dissipation can be calculated with

the equation below.

With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of the IDT723614 can be calculated by:

PT = VCC x ICC(f) + Σ(CL x VOH2 x fo)

where:

CL= output capacitance load

fo= switching frequency of an output

VOH = output high level voltage

When no reads or writes are occurring on the IDT723614, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fs is

calculated by: PT=VCC x fS x 0.290 mA/MHz

010 20 30 40 50 60 70

100

150

200

250

300

350

400

fs ⎯ Clock Frequency ⎯ MHz

I CC(f) Supply Current mA

VCC = 5.5V

3146 drw04

VCC = 5V

VCC = 4.5V

fdata = 1/2 fs

= 25° C

= 0 pF

Figure 1. Typical Characteristics: Supply Current vs Clock Frequency

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

JANUARY 14, 2009

DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF

SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE

Commercial Com'l & Ind'l(1)

IDT723614L15 IDT723614L20

Symbol Parameter Min. Max. Min. Max. Unit

fSClock Frequency, CLKA or CLKB – 66.7 – 50 MHz

tCLK Clock Cycle Time, CLKA or CLKB 15 – 20 – n s

tCLKH Pulse Duration, CLKA and CLKB HIGH 6 – 8 – ns

tCLKL Pulse Duration, CLKA and CLKB LOW 6 – 8 – ns

tDS Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑4–5–ns

tENS Setup Time, CSA, W/RA, ENA and MBA before CLKA↑; CSB, W/RB and ENB 5 – 5 – ns

before CLKB↑

tSZS Setup Time, SIZ0, SIZ1, and BE before CLKB↑4–5–ns

tSWS Setup Time, SW0 and SW1 before CLKB↑5–7–ns

tPGS Setup Time, ODD/EVEN and PGA before CLKA↑; ODD/EVEN and PGB before 4 – 5 – ns

CLKB↑(2)

tRSTS Setup Time, RST LOW before CLKA↑ or CLKB↑(3) 5–6–ns

tFSS Setup Time, FS0 and FS1 before RST HIGH 5 – 6 – n s

tDH Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑1–1–ns

tENH Hold Time, CSA, W/RA, ENA and MBA after CLKA↑; CSB, W/RB, and ENB 1 – 1 – ns

after CLKB↑

tSZH Hold Time, SIZ0, SIZ1, and BE after CLKB↑2–2–ns

tSWH Hold Time, SW0 and SW1 after CLKB↑0–0–ns

tPGH Hold Time, ODD/EVEN and PGA after CLKA↑; ODD/EVEN and PGB after 0 – 0 – ns

CLKB↑(2)

tRSTH Hold Time, RST LOW after CLKA↑ or CLKB↑(3) 5–6–ns

tFSH Hold Time, FS0 and FS1 after RST HIGH 4 – 4 – ns

tSKEW1(4) Skew Time, between CLKA↑ and CLKB↑ for EFA, EFB, FFA, and FFB 8–8–ns

tSKEW2(4) Skew Time, between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB 14 – 16 – ns

NOTES:

1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.

2. Only applies for a clock edge that does a FIFO read.

3. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

4. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.

(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V ± 10%,TA = 40°C to +85°C)

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

JANUARY 14, 2009

Commercial Com'l & Ind'l(1)

IDT723614L15 IDT723614L20

Symbol Parameter Min. Max. Min. Max. Unit

tAAccess Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35 2 10 2 12 ns

tWFF Propagation Delay Time, CLKA↑ to FFA and CLKB↑ to FFB 210212ns

tREF Propagation Delay Time, CLKA↑ to EFA and CLKB↑ to EFB 210212ns

tPAE Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB 210212ns

tPAF Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to AFB 210212ns

tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH and CLKB↑ to 1 9 1 12 n s

MBF2 LOW or MBF1 HIGH

tPMR Propagation Delay Time, CLKA↑ to B0-B35(2) and CLKB↑ to A0-A35(3) 311313ns

tPPE(4) Propagation delay time, CLKB↑ to PEFB 211212ns

tMDV Propagation Delay Time, MBA to A0-A35 valid and SIZ1, SIZ0 to B0-B35 valid 1 1 1 1 11. 5 n s

tPDPE Propagation Delay Time, A0-A35 valid to PEFA valid; B0-B35 valid to PEFB valid 3 10 3 11 ns

tPOPE Propagation Delay Time, ODD/EVEN to PEFA and PEFB 311312ns

tPOPB(5) Propagation Delay Time, ODD/EVEN to parity bits (A8, A17, A26, A35) and 2 11 2 12 ns

(B8, B17, B26, B35)

tPEPE Propagation Delay Time, CSA, ENA, W/RA, MBA, or PGA to PEFA; CSB, ENB, 1 11 1 12 n s

W/RB, SIZ1, SIZ0, or PGB to PEFB

tPEPB(5) Propagation Delay Time, CSA, ENA, W/RA, MBA, or PGA to parity bits (A8, A17, 3 12 3 13 n s

A26, A35); CSB, ENB, W/RB, SIZ1, SIZ0, or PGB to parity bits (B8, B17, B26, B35)

tRSF Propagation Delay Time, RST to (MBF1, MBF2) HIGH 1 15 1 20 n s

tEN Enable Time, CSA and W/RA LOW to A0-A35 active and CSB LOW and W/RB210212ns

HIGH to B0-B35 active

tDIS Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance and CSB HIGH or 1 8 1 9 n s

W/RB LOW to B0-B35 at high-impedance

SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF

SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30PF

NOTES:

1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.

2. Writing data to the mail1 register when the B0-B35 outputs are active and SIZ1, SIZ0 are HIGH.

3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.

4. Only applies when a new port B bus size is implemented by the rising CLKB edge.

5. Only applies when reading data from a mail register.

(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V ± 10%,TA = 40°C to +85°C)

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

JANUARY 14, 2009

B, EFB is set LOW when the fourth byte or second word of the last long word

is read.

The read pointer of a FIFO is incremented each time a new word is

clocked to the output register. The state machine that controls an Empty

Flag monitors a write-pointer and read-pointer comparator that indicates

when the FIFO SRAM status is empty, empty+1, or empty+2. A word written

to a FIFO can be read to the FIFO output register in a minimum of three

cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag is

LOW if a word in memory is the next data to be sent to the FIFO output

not elapsed since the time the word was written. The Empty Flag of the FIFO

is set HIGH by the second LOW-to-HIGH transition of the synchronizing

clock, and the new data word can be read to the FIFO output register in the

following cycle.

A LOW-to-HIGH transition on an Empty Flag synchronizing clock begins

the first synchronization cycle of a write if the clock transition occurs at time tSKEW1

or greater after the write. Otherwise, the subsequent clock cycle can be the first

synchronization cycle (see Figure 14 and 15).

FULL FLAG (FFA, FFB)

The Full Flag of a FIFO is synchronized to the port clock that writes data

to its array. When the Full Flag is HIGH, a memory location is free in the

SRAM to receive new data. No memory locations are free when the full flag

is LOW and attempted writes to the FIFO are ignored.

Each time a word is written to a FIFO, the write pointer is incremented.

The state machine that controls a Full Flag monitors a write-pointer and

read-pointer comparator that indicates when the FIFO SRAM status is full,

full-1, or full-2. From the time a word is read from a FIFO, the previous

memory location is ready to be written in a minimum of three cycles of the

Full Flag synchronizing clock. Therefore, a Full Flag is LOW if less than two

cycles of the Full Flag synchronizing clock have elapsed since the next

memory write location has been read. The second LOW-to-HIGH transition

on the Full Flag synchronization clock after the read sets the Full Flag HIGH and

the data can be written in the following clock cycle.

A LOW-to-HIGH transition on a Full Flag synchronizing clock begins the

first synchronization cycle of a read if the clock transition occurs at time

tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can

be the first synchronization cycle (see Figure 16 and 17).

ALMOST-EMPTY FLAGS (AEA, AEB)

The Almost-Empty flag of a FIFO is synchronized to the port clock that

reads data from its array. The state machine that controls an Almost-Empty

flag monitors a write-pointer and a read-pointer comparator that indicates

when the FIFO SRAM status is almost-empty, almost-empty+1, or almost-

empty+2. The almost-empty state is defined by the value of the Almost-Full

and Almost-Empty Offset register (X). This register is loaded with one of

four preset values during a device reset (see Reset above). An Almost-

Empty flag is LOW when the FIFO contains X or less long words in memory

and is HIGH when the FIFO contains (X+1) or more long words.

Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing

clock are required after a FIFO write for the Almost-Empty flag to reflect the

new level of fill. Therefore, the Almost-Empty flag of a FIFO containing

(X+1) or more long words remains LOW if two cycles of the synchronizing

clock have not elapsed since the write that filled the memory to the (X+1)

level. An Almost-Empty flag is set HIGH by the second LOW-to-HIGH

transition of the synchronizing clock after the FIFO write that fills memory

to the (X+1) level. A LOW-to-HIGH transition of an Almost-Empty flag

synchronizing clock begins the first synchronization cycle if it occurs at time

SIGNAL DESCRIPTIONS

RESET

The IDT723614 is reset by taking the Reset (RST) input LOW for at least

four port A clock (CLKA) and four port B clock (CLKB) LOW-to-HIGH

transitions. The Reset input can switch asynchronously to the clocks. A

device reset initializes the internal read and write pointers of each FIFO and

forces the Full Flags (FFA, FFB) LOW, the Empty Flags (EFA, EFB) LOW,

the Almost-Empty flags (AEA, AEB) LOW and the Almost-Full flags (AFA,

AFB) HIGH. A reset also forces the Mailbox Flags (MBF1, MBF2) HIGH.

After a reset, FFA is set HIGH after two LOW-to-HIGH transitions of CLKA

and FFB is set HIGH after two LOW-to-HIGH transitions of CLKB. The

device must be reset after power up before data is written to its memory.

A LOW-to-HIGH transition on the RST input loads the Almost-Full and

Almost-Empty Offset register (X) with the values selected by the Flag Select

(FS0, FS1) inputs. The values that can be loaded into the registers are

shown in Table 1.

FIFO WRITE/READ OPERATION

The state of port A data A0-A35 outputs is controlled by the port A Chip

Select (CSA) and the port A Write/Read select (W/RA). The A0-A35 outputs

are in the high-impedance state when either CSA or W/RA is HIGH. The A0-

A35 outputs are active when both CSA and W/RA are LOW. Data is loaded

into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA

when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and FFA

is HIGH. Data is read from FIFO2 to the A0-A35 outputs by a LOW-to-HIGH

transition of CLKA when CSA is LOW, W/RA is LOW, ENA is HIGH, MBA

is LOW, and EFA is HIGH (see Table 2).

The port B control signals are identical to those of port A. The state of the

port B data (B0-B35) outputs is controlled by the port B Chip Select (CSB)

and the port B Write/Read select (W/RB). The B0-B35 outputs are in the high-

impedance state when either CSB or W/RB is HIGH. The B0-B35 outputs are

active when both CSB and W/RB are LOW. Data is loaded into FIFO2 from the

B0-B35 inputs on a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB

is HIGH, ENB is HIGH, EFB is HIGH, and either SIZ0 or SIZ1 is LOW. Data

is read from FIFO1 to the B0-B35 outputs by a LOW-to-HIGH transition of CLKB

when CSB is LOW, W/RB is LOW, ENB is HIGH, EFB is HIGH, and either SIZ0

or SIZ1 is LOW (see Table 3).

The setup and hold time constraints to the port clocks for the port Chip

Selects (CSA, CSB) and Write/Read selects (W/RA, W/RB) are only for

enabling write and read operations and are not related to high-impedance

control of the data outputs. If a port enable is LOW during a clock cycle, the

port Chip Select and Write/Read select can change states during the setup

and hold time window of the cycle.

SYNCHRONIZED FIFO FLAGS

Each FIFO is synchronized to its port clock through two flip-flop stages.

This is done to improve flag reliability by reducing the probability of

metastable events on the output when CLKA and CLKB operate asynchro-

nously to one another. EFA, AEA, FFA, and AFA are synchronized to CLKA.

EFB, AEB, FFB, and AFB are synchronized to CLKB. Tables 4 and 5 show

the relationship of each port flag to FIFO1 and FIFO2.

EMPTY FLAGS (EFA, EFB)

The Empty Flag of a FIFO is synchronized to the port clock that reads data

from its array. When the Empty Flag is HIGH, new data can be read to the FIFO

output register. When the Empty Flag is LOW, the FIFO is empty and attempted

FIFO reads are ignored. When reading FIFO1 with a byte or word size on port

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

JANUARY 14, 2009

tSKEW2 or greater after the write that fills the FIFO to (X+1) long words.

Otherwise, the subsequent synchronizing clock cycle can be the first

synchronization cycle (see Figure 18 and 19).

ALMOST FULL FLAGS (AFA, AFB)

The Almost-Full flag of a FIFO is synchronized to the port clock that writes

data to its array. The state machine that controls an Almost-Full flag

monitors a write-pointer and read-pointer comparator that indicates when

the FIFO SRAM status is almost full, almost full-1, or almost full-2. The

almost-full state is defined by the value of the Almost-Full and Almost-Empty

Offset register (X). This register is loaded with one of four preset values

during a device reset (see Reset above). An Almost-Full flag is LOW when

the FIFO contains (64-X) or more long words in memory and is HIGH when

the FIFO contains [64-(X+1)] or less long words.

Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock

are required after a FIFO read for the Almost-Full flag to reflect the new level

of fill. Therefore, the Almost-Full flag of a FIFO containing [64-(X+1)] or less

words remains LOW if two cycles of the synchronizing clock have not

elapsed since the read that reduced the number of long words in memory

to [64-(X+1)]. An Almost-Full flag is set HIGH by the second LOW-to-HIGH

transition of the synchronizing clock after the FIFO read that reduces the

number of long words in memory to [64-(X+1)]. A LOW-to-HIGH transition

of an Almost-Full flag synchronizing clock begins the first synchronization

cycle if it occurs at time tSKEW2 or greater after the read that reduces the number

of long words in memory to [64-(X+1)]. Otherwise, the subsequent synchro-

nizing clock cycle can be the first synchronization cycle (see Figure 20 and 21).

MAILBOX REGISTERS

Each FIFO has a 36-bit bypass register to pass command and control

information between port A and port B without putting it in queue. The

Mailbox-Select (MBA, MBB) inputs choose between a mail register and a

FIFO for a port data transfer operation. A LOW-to-HIGH transition on CLKA

writes A0-A35 data to the mail1 register when a port A write is selected by

CSA, W/RA, and ENA with MBA HIGH. A LOW-to-HIGH transition on CLKB

writes B0-B35 data to the mail2 register when a port B write is selected by

CSB, W/RB, and ENB with both SIZ1 and SIZ0 HIGH. Writing data to a mail

writes to a mail register are ignored while the mail flag is LOW.

When the port A data outputs (A0-A35) are active, the data on the bus

comes from the FIFO2 output register when MBA is LOW and from the mail2

active, the data on the bus comes from the FIFO1 output register when

either one or both SIZ1 and SIZ0 are LOW and from the mail2 register when

both SIZ1 and SIZ0 are HIGH. The Mail1 Register Flag (MBF1) is set HIGH

CSB W/RB ENB SIZ1, SIZ0 CLKB B0-B35 Outputs Port Functions

H X X X X In High-Impedance State None

L H L X X In High-Impedance State None

L H H One, both LOW ↑In High-Impedance State FIFO2 Write

L H H Both HIGH ↑In High-Impedance State Mail2 Write

L L L One, both LOW X Active, FIFO1 Output Register None

L L H One, both LOW ↑Active, FIFO1 Output Register FIFO1 read

L L L Both HIGH X Active, Mail1 Register None

L L H Both HIGH ↑Active, Mail1 Register Mail1 Read (Set MBF1 HIGH)

TABLE 3 — PORT-B ENABLE FUNCTION TABLE

CSA W/RA ENA MBA CLKA A0-A35 Outputs Port Functions

HXXXX In High-Impedance State None

L H L X X In High-Impedance State None

LHHL↑In High-Impedance State FIFO1 Write

LHHH↑In High-Impedance State Mail1 Write

LLLLX Active, FIFO2 Output Register None

LLHL↑Active, FIFO2 Output Register FIFO2 Read

L L L H X Active, Mail2 Register None

LLHH↑Active, Mail2 Register Mail2 Read (Set MBF2 HIGH)

TABLE 2 — PORT-A ENABLE FUNCTION TABLE

ALMOST-FULL AND

FS1 FS0 RST ALMOST-EMPTY FLAG

OFFSET REGISTER (X)

HH↑16

HL↑12

LH↑8

LL↑4

TABLE 1 — FLAG PROGRAMMING

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

JANUARY 14, 2009

DYNAMIC BUS SIZING

The port B bus can be configured in a 36-bit long word, 18-bit word, or 9-

bit byte format for data read from FIFO1 or written to FIFO2. Word- and byte-

size bus selections can utilize the most significant bytes of the bus (Big-

Endian) or least significant bytes of the bus (Little-Endian). Port B bus size

can be changed dynamically and synchronous to CLKB to communicate

with peripherals of various bus widths.

The levels applied to the port B bus Size select (SIZ0, SIZ1) inputs and

the Big-Endian select (BE) input are stored on each CLKB LOW-to-HIGH

transition. The stored port B bus size selection is implemented by the next

rising edge on CLKB according to Figure 2.

Only 36-bit long-word data is written to or read from the two FIFO

memories on the IDT723614. Bus-matching operations are done after data

is read from the FIFO1 RAM and before data is written to the FIFO2 RAM.

Port B bus sizing does not apply to mail register operations.

BUS-MATCHING FIFO1 READS

Data is read from the FIFO1 RAM in 36-bit long word increments. If a long

word bus size is implemented, the entire long word immediately shifts to the

FIFO1 output register. If byte or word size is implemented on port B, only

the first one or two bytes appear on the selected portion of the FIFO1 output

subsequent FIFO1 reads with the same bus-size implementation output the rest

of the long word to the FIFO1 output register in the order shown by Figure 2.

Each FIFO1 read with a new bus-size implementation automatically unloads

data from the FIFO1 RAM to its output register and auxiliary registers. Therefore,

implementing a new port B bus size and performing a FIFO1 read before all bytes

or words stored in the auxiliary registers have been read results in a loss of the

unread long word data.

When reading data from FIFO1 in byte or word format, the unused B0-

B35 outputs remain inactive but static, with the unused FIFO1 output

BUS-MATCHING FIFO2 WRITES

Data is written to the FIFO2 RAM in 36-bit long word increments. FIFO2

writes, with a long-word bus size, immediately store each long word in

FIFO2 RAM. Data written to FIFO2 with a byte or word bus size stores the

initial bytes or words in auxiliary registers. The CLKB rising edge that writes

the fourth byte or the second word of long word to FIFO2 also stores the

entire long word in FIFO2 RAM. The bytes are arranged in the manner

shown in Figure 2.

Each FIFO2 write with a new bus-size implementation resets the state

machine that controls the data flow from the auxiliary registers to the FIFO2

RAM. Therefore, implementing a new bus size and performing a FIFO2

write before bytes or words stored in the auxiliary registers have been

loaded to FIFO2 RAM results in a loss of data.

PORT-B MAIL REGISTER ACCESS

In addition to selecting port-B bus sizes for FIFO reads and writes, the

port B bus Size select (SIZ0, SIZ1) inputs also access the mail registers.

When both SIZ0 and SIZ1 are HIGH, the mail1 register is accessed for a port

B long word read and the mail2 register is accessed for a port B long word

write. The mail register is accessed immediately and any bus-sizing

operation that may be underway is unaffected by the mail register access.

After the mail register access is complete, the previous FIFO access can

resume in the next CLKB cycle. The logic diagram in Figure 3 shows the

previous bus-size selection is preserved when the mail registers are

accessed from port B. A port B bus size is implemented on each rising CLKB

edge according to the states of SIZ0_Q, SIZ1_Q, and BE_Q.

BYTE SWAPPING

The byte-order arrangement of data read from FIFO1 or data written to

FIFO2 can be changed synchronous to the rising edge of CLKB. Byte-order

swapping is not available for mail register data. Four modes of byte-order

swapping (including no swap) can be done with any data port size selection.

The order of the bytes are rearranged within the long word, but the bit order

within the bytes remains constant.

Byte arrangement is chosen by the port B Swap select (SW0, SW1)

inputs on a CLKB rising edge that reads a new long word from FIFO1 or

writes a new long word to FIFO2. The byte order chosen on the first byte or

first word of a new long word read from FIFO1 or written to FIFO2 is

maintained until the entire long word is transferred, regardless of the SW0

and SW1 states during subsequent writes or reads. Figure 4 is an example

of the byte-order swapping available for long words. Performing a byte swap

and bus size simultaneously for a FIFO1 read first rearranges the bytes as

shown in Figure 4, then outputs the bytes as shown in Figure 2. Simulta-

neous bus-sizing and byte-swapping operations for FIFO2 writes, first loads

the data according to Figure 2, then swaps the bytes as shown in Figure 4 when

the long word is loaded to FIFO2 RAM.

by a rising CLKB edge when a port B read is selected by CSB, W/RB, and ENB

with both SIZ1 and SIZ0 HIGH. The Mail2 Register Flag (MBF2) is set HIGH

by a LOW-to-HIGH transition on CLKA when port A read is selected by CSA,

W/RA, and ENA and MBA is HIGH. The data in the mail register remains intact

after it is read and changes only when new data is written to the register.

Synchronized Synchronized

Number of 36-Bit to CLKB to CLKA

Words in the FIFO1(1)

EFB AEB AFA FFA

0LLHH

1 to X H L H H

(X+1) to [64-(X+1)] H H H H

(64-X) to 63 H H L H

64 H H L L

TABLE 4 — FIFO1 FLAG OPERA TION

Synchronized Synchronized

Number of 36-Bit to CLKA to CLKB

Words in the FIFO2(1)

EFA AEA AFB FFB

0LLHH

1 to X H L H H

(X+1) to [64-(X+1)] H H H H

(64-X) to 63 H H L H

64 H H L L

TABLE 5 — FIFO2 FLAG OPERA TION

NOTE:

1. X is the value in the Almost-Empty flag and Almost-Full flag Offset register.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

JANUARY 14, 2009

Figure 2. Dynamic Bus Sizing

B8⎯B0

(a) LONG WORD SIZE

(b) WORD SIZE

⎯

BIG-ENDIAN

⎯

LITTLE-ENDIAN

(d) BYTE SIZE

⎯

BIG-ENDIAN

Write to FIFO1/

Read From FIFO2

Read from FIFO1/

Write to FIFO2

1st: Read from FIFO1/

Write to FIFO2

2nd: Read from FIFO1/

Write to FIFO2

1st: Read from FIFO1/

Write to FIFO2

2nd: Read from FIFO1/

Write to FIFO2

1st: Read from FIFO1/

Write to FIFO2

2nd: Read from FIFO1/

Write to FIFO2

3rd: Read from FIFO1/

Write to FIFO2

4th: Read from FIFO1/

Write to FIFO2

BE SIZ1 SIZ0

L L H

H L H

L H L

X L L

BYTE ORDER ON PORT A:

3146 fig 01

B8⎯B0

ABCD

C D

A35⎯A27 A26⎯A18 A17⎯A9 A8⎯A0

B35⎯B27 B26⎯B18 B17⎯B9

B8⎯B0

(d) BYTE SIZE

⎯

LITTLE-ENDIAN

1st: Read from FIFO1/

Write to FIFO2

2nd: Read from FIFO1/

Write to FIFO2

3rd: Read from FIFO1/

Write to FIFO2

4th: Read from FIFO1/

Write to FIFO2

BE SIZ1 SIZ0

H H L

B8⎯B0

B35⎯B27 B26⎯B18 B17⎯B9

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

JANUARY 14, 2009

PARITY CHECKING

The port A inputs (A0-A35) and port B inputs (B0-B35) each have four

parity trees to check the parity of incoming (or outgoing) data. A parity failure

on one or more bytes of the port A data bus is reported by a LOW level on

the port Parity Error Flag (PEFA). A parity failure on one or more bytes of

the port B data input that are valid for the bus-size implementation is

reported by a LOW level on the port B Parity Error Flag (PEFB). Odd or Even

parity checking can be selected, and the Parity Error Flags can be ignored

if this feature is not desired.

Parity status is checked on each input bus according to the level of the

Odd/Even parity (ODD/EVEN) select input. A parity error on one or more

valid bytes of a port is reported by a LOW level on the corresponding port

Parity Error Flag (PEFA, PEFB) output. Port A bytes are arranged as A0-

A8, A9-A17, A18-A26, and A27-A35. Port B bytes are arranged as B0-B8,

B9-B17, B18-B26, and B27-B35, and its valid bytes are those used in a port

B bus-size implementation. When Odd/Even parity is selected, a port Parity

Error Flag (PEFA, PEFB) is LOW if any byte on the port has an odd/even

number of LOW levels applied to the bits.

The four parity trees used to check the A0-A35 inputs are shared by the mail2

When a port A read from the mail2 register with parity generation is selected with

CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA HIGH, the port A

Parity Error Flag (PEFA) is held HIGH regardless of the levels applied to the

A0-A35 inputs. Likewise, the parity trees used to check the B0-B35 inputs are

shared by the mail1 register when parity generation is selected for port B reads

(PGB = HIGH). When a port B read from the mail1 register with parity generation

is selected with CSB LOW, ENB HIGH, W/RB LOW, both SIZ0 and SIZ1 HIGH,

and PGB HIGH, the port B Parity Error Flag (PEFB) is held HIGH regardless

of the levels applied to the B0-B35 inputs.

PARITY GENERATION

A HIGH level on the port A Parity Generate select (PGA) or port B Parity

Generate select (PGB) enables the IDT723614 to generate parity bits for port

reads from a FIFO or mailbox register. Port A bytes are arranged as A0-A8,

A9-A17, A18-26, and A27-A35, with the most significant bit of each byte used

as the parity bit. Port B bytes are arranged as B0-B8, B9-B17, B18-B26, and

B27-B35, with the most significant bit of each byte used as the parity bit. A write

to a FIFO or mail register stores the levels applied to all nine inputs of a byte

regardless of the state of the Parity Generate select (PGA, PGB) inputs. When

data is read from a port with parity generation selected, the lower eight bits of

each byte are used to generate a parity bit according to the level on the ODD/

EVEN select. The generated parity bits are substituted for the levels originally

written to the most significant bits of each byte as the word is read to the data

outputs.

Parity bits for FIFO data are generated after the data is read from SRAM

and before the data is written to the output register. Therefore, the port A

Parity Generate select (PGA) and Odd/Even parity select (ODD/EVEN) have

setup and hold time constraints to the port A Clock (CLKA) and the port B Parity

Generate select (PGB) and ODD/EVEN have setup and hold-time constraints

to the port B Clock (CLKB). These timing constraints only apply for a rising clock

edge used to read a new long word to the FIFO output register.

The circuit used to generate parity for the mail1 data is shared by the port B

bus (B0-B35) to check parity and the circuit used to generate parity for the mail2

data is shared by the port A bus (A0-A35) to check parity. The shared parity

trees of a port are used to generate parity bits for the data in a mail register when

the port Chip Select (CSA, CSB) is LOW, Enable (ENA, ENB) is HIGH, Write/

Read select (W/RA, W/RB) input is LOW, the Mail register is selected (MBA is

HIGH for port A; both SIZ0 and SIZ1 are HIGH for port B), and port Parity

Generate select (PGA, PGB) is HIGH. Generating parity for mail register data

does not change the contents of the register.

Figure 3. Logic Diagrams for SIZ0, SIZ1, and

BEBE

MUX

D Q

SIZ0 Q

SIZ1 Q

BE Q

•

SIZ0

SIZ1

CLKB

3146 fi

••

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

JANUARY 14, 2009

B8⎯B0

(a) NO SWAP

(b) BYTE SWAP

(d) BYTE-WORD SWAP

L L

SW1 SW0

L L

L H

H L

H H

3146 fi

A8⎯A0

B8⎯B0

A8⎯A0

B8⎯B0

A35⎯A27 A26⎯A18 A17⎯A9

B35⎯B27 B26⎯B18 B17⎯B9

A35⎯A27 A26⎯A18 A17⎯A9

B35⎯B27 B26⎯B18 B17⎯B9

A35⎯A27 A26⎯A18 A17⎯A9

B35⎯B27 B26⎯B18 B17⎯B9

A35⎯A27 A26⎯A18 A17⎯A9

B35⎯B27 B26⎯B18 B17⎯B9

Figure 4. Byte Swapping (Long Word Size Example)

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

JANUARY 14, 2009

Figure 5. Device Reset Loading the X Register with the Value of Eight

CLKA

RST

FFA

FFB

EFB

AEA

CLKB

EFA

FS1,FS0

3146 drw05

RSTS

RSTH

FSH

FSS

WFF

0,1

AFA

MBF1,

MBF2

WFF

AEB

AFB

WFF

REF

WFF

REF

RSF

PAE

PAF

PAE

PAF

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

JANUARY 14, 2009

NOTE:

1. SIZ0 = HIGH and SIZ1 = HIGH writes data to the mail2 register

CLKB

ENB

SW1,

SW0

FFB

W/RB

B0-B35

PEFB

ODD/

EVEN

HIGH

3146 drw 07

t ENS

tENH

CSB

SIZ1,

SIZ0

VALID

tPDPE

NOT (1,1) (1)

(0,0)

tDH

tSZH

tENS tENH

tPPE

(0,0)

tSWS tSWH

tSZS

tDS

DATA SWAP TABLE FOR LONG-WORD WRITES TO FIFO2

Figure 7. Port-B Long-Word Write Cycle Timing for FIFO2

3146 drw06

CLKA

FFA

ENA

A0 - A35

MBA

CSA

W/RA

tENS

tDS

tENH

tDH

(1)

tENS tENH tENH

tENS

No Operation

ODD/

EVEN

PEFA Valid Valid

tPDPE

HIGH

tCLK

tCLKH tCLKL

NOTE:

1. Written to FIFO1. Figure 6. Port-A Write Cycle Timing for FIFO1

SWAP MODE DATA WRITTEN TO FIFO2 DATA READ FROM FIFO2

SW1 SW0 B35-27 B26-18 B17-B9 B8-B0 A35-27 A26-A18 A17-A9 A8-A0

LLABCDABCD

LHDCBAABCD

HLCDABABCD

HHBADCABCD

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

JANUARY 14, 2009

CLKB

SW1, SW0

ENB

FFB

W/RB

HIGH

3146 drw08

PEFB

ODD/EVEN

Big-

Endian B18-B35

Little-

Endian B0-B17

SIZ1, SIZ0

CSB

(0, 1) NOT (1,1)

(1)

ENH

SWH

SZH

SZS

VALID

PDPE

SZH

SWS

(0, 1)

ENS

PPE

NOTES:

1. SIZ0 = HIGH and SIZ1 = HIGH writes data to the mail2 register.

2. PEFB indicates parity error for the following bytes: B35-B27 and B26-B18 for Big-Endian bus, and B17-B9 and B8-B0 for Little-Endian bus.

Figure 8. Port-B Word Write Cycle Timing for FIFO2

DATA SWAP TABLE FOR WORD WRITES TO FIFO2

DATA WRITTEN TO FIFO2

MODE NO. BIG-ENDIAN LITTLE-ENDIAN

SW1 SW0 B35-27 B26-18 B17-B9 B8-B0 A35-27 A26-A18 A17-A9 A8-A0

LL 1 A B C D A B C D

2C D A B

LH 1 D C B A A B C D

2B A D C

HL 1 C D A B A B C D

2A B C D

HH 1 B A D C A B C D

2D C B A

DATA READ FROM FIFO2

SWAP W RITE

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TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

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FFB

CSB

W/RB

SIZ1,

SIZ0

CLKB

3146 drw09

HIGH

SW1,

SW0

ODD/EVEN

B0-

(1,0) (1,0)

Not (1,1)(1)

tENS

tENH

tSWS

tSZH

tSZHtSZS

ENB

Little-

Endian

ValidValidValid

Valid

Big-

Endian B27-

B35

PEFB

tPPE tPDPE tPDPE tPDPE

tDS

tDH

tENS

tSZH

tSZS

tSZH

tENH

tENHtENS

tENH

(1,0)

NOTES:

1. SIZ0 = HIGH and SIZ1 = HIGH writes data to the mail2 register.

2. PEFB indicates parity error for the following bytes: B35—B27 for Big-Endian bus and B17—B9 for Little-Endian bus.

DATA SWAP TABLE FOR BYTE WRITES TO FIFO2

Figure 9. Port-B Byte Write Cycle Timing for FIFO2

DATA READ FROM FIFO2

SWAP W RITE DATA WRITTEN TO FIFO2

MODE NO. BIG-ENDIAN LITTLE-ENDIAN

SW1 SW0 B35-27 B8-B0 A35-27 A26-A18 A17-A9 A8-A0

1A D

2B C

3C B

4D A

1D A

2C B

3B C

4A D

1C B

2D A

3A D

4B C

1B C

2A D

3D A

4C B

L L

L H

H L

H H

A B C D

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TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

JANUARY 14, 2009

NOTES:

1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35.

2. Data read from FIFO1.

CLKB

ENB

SW1,

SW0

EFB

W/RB

PGB,

ODD/

EVEN

HIGH

3146 drw10

CSB

SIZ1,

SIZ0 NOT (1,1)

(1)

PGH

PGS

SZH

ENH

(0,0)

SWS

B0-B35

NOT (1,1)

(1)

Previous Data W1

(2)

DIS

ENS

ENH

SWH

ENS

No Operation

(0,0)

SZS

DATA SW AP TABLE FOR FIFO LONG-WORD READS FROM FIFO1

Figure 10. Port-B Long-Word Read Cycle Timing for FIFO1

DATA WRITTEN TO FIFO1 SWAP MODE DATA READ FROM FIFO1

A35-27 A26-A18 A17-A9 A8-A0 SW1 SW0 B35-27 B26-18 B17-B9 B8-B0

AB C D L L A B C D

AB C D L H D C B A

AB C D H L C D A B

AB C D H H B A D C

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

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CLKB

ENB

SW1,

SW0

EFB

W/RB

PGB,

ODD/

EVEN

HIGH

3146 drw11

CSB

SIZ1,

SIZ0 NOT (1,1)

(1)

tPGHtPGS

tSZH

(0,1)

tSWS

B0-B17

NOT (1,1)

(1)

Previous Data

tENS tENH

tSWH No Operation

Previous DataB18-B35

Little-

Endian

Big-

Endian

(0,1)

(2)

tSZS

tEN tA

tDIS

NOTES:

1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35.

2. Unused word B0-B17 or B18-B35 holds last FIFO1 output register data for word-size reads.

DATA SWAP TABLE FOR WORD READS FROM FIFO1

Figure 11. Port-B Word Read Cycle Timing for FIFO1

DATA WRITTEN TO FIFO1 SWAP MODE READ

NO. BIG-ENDIAN LITTLE-ENDIAN

A35-A27 A26-A18 A17-A9 A8-A0 SW 1 SW 0 B35-B27 B26-B18 B17-B9 B8-B0

1A B CD

ABCD L L2CDAB

1D C BA

ABCD L H2BADC

1C D AB

ABCD H L2ABCD

1B A DC

ABCD H H2D CBA

DATA READ FROM FIFO1

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TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

JANUARY 14, 2009

NOTES:

1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35.

2. Unused bytes hold last FIFO1 output register data for byte-size reads.

EFB

CSB

W/RB

SIZ1,

SIZ0

ENB

CLKB

3146 drw12

HIGH

SW1,

SW0

PGB,

ODD/

EVEN

B0-B8

B27-B35 Read 4Read 1 Read 2

Read 4Read 1 Read 3

Read 3Previous Data

Previous Data Read 2

(1,0) (1,0) (1,0) Not (1,1) (1)

No Operation

tDIS

tEN

tPGH

tPGS

Not (1,1)

(1)

Not (1,1)

(1)

Not (1,1)

(1)

(1,0)

tENH

tSWH

tSZH

tSZS

tENS

tSWS

DATA SWAP TABLE FOR BYTE READS FROM FIFO1

Figure 12. Port-B Byte Read Cycle Timing for FIFO1

1A D

2B C

ABC DLL3 C B

4D A

1D A

2C B

ABC DLH3 B C

4A D

1C B

2D A

ABC DHL3 A D

4B C

1B C

2A D

ABC DHH3 D A

4C B

DATA WRITTEN TO FIFO 1 SWAP MODE READ BIG- LITTLE-

NO. ENDIAN ENDIAN

A35-A27 A26-A18 A17-A9 A8-A0 SW1 SW0 B35-B27 B8-B0

DATA READ FROM FIFO 1

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TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

JANUARY 14, 2009

3146 drw13

CLKA

EFA

ENA

A0 - A35

MBA

CSA

W/RA

ENH

Previous Data Word 1 Word 2

(1) (1)

ENH

No Operation

PGA,

ODD/

EVEN

HIGH

PGH

CLK

CLKH

CLKL

ENS

PGS

ENS

DIS

MDV

NOTE:

1. Read from FIFO2. Figure 13. Port-A Read Cycle Timing for FIFO2

NOTES:

1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA

edge and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.

2. Port-B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port-B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1,

respectively. Figure 14.

EFBEFB

EFB

Flag Timing and First Data Read when FIFO1 is Empty

CSA

WRA

MBA

FFA

A0 - A35

CLKB

EFB

CSB

W/RB

SIZ1,

SIZ0

ENA

ENB

B0 -B35

CLKA

3146 drw14

ENS

ENH

ENS

ENH

FIFO1 Empty

LOW

HIGH

LOW

HIGH

CLK

CLKH

CLKL

SKEW1(1)

CLKH

CLK

CLKL

REF

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TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

JANUARY 14, 2009

CSB

W/RB

SIZ1,

SIZ0

FFB

B0 - B35

CLKA

EFA

CSA

W/RA

MBA

ENB

ENA

A0 -A35

CLKB

3146 drw15

tENS

tENH

tDS tDH

tENS tENH

FIFO2 Empty

LOW

HIGH

LOW

HIGH

tCLK

tCLKH

tSKEW1(1) tCLKH

tCLK

tREF tREF

tCLKL

NOTES:

1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB

edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.

2. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte tSKEW1 is referenced to the rising CLKB edge that writes the

last word or byte of the long word, respectively.

Figure 15.

EFAEFA

EFA

Flag Timing and First Data Read when FIFO2 is Empty

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TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

JANUARY 14, 2009

CSB

EFB

SIZ1,

SIZ0

ENB

B0 - B35

CLKB

FFA

CLKA

CSA

3146 drw16

WRA

A0 - A35

MBA

ENA

tENS tENH

tENS

tDS

tENH

tDH

To FIFO1

Previous Word in FIFO1 Output Register Next Word From FIFO1

LOW

W/RBLOW

LOW

HIGH

LOW

HIGH

FIFO1 Full

tCLK

tCLKH tCLKL

tSKEW1(1) tCLK

tCLKH tCLKL

tWFF tWFF

NOTES:

1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and

rising CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.

2. Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last

word or byte of the long word, respectively.

Figure 16.

FFAFFA

FFA

Flag Timing and First Available Write when FIFO1 is Full.

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TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

JANUARY 14, 2009

NOTES:

1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA

edge and rising CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown.

2. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, FFB is set LOW by the last word or byte write of the long

word, respectively. Figure 17.

FFBFFB

FFB

Flag Timing and First Available Write when FIFO2 is Full

NOTES:

1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA

edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.

2 . FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW).

3. Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, AEB is set LOW by the last word or byte read of the long

word, respectively. Figure 18. Timing for

AEBAEB

AEB

when FIFO1 is Almost-Empty

CSA

EFA

MBA

ENA

A0 - A35

CLKA

FFB

CLKB

CSB

3146 drw17

W/RB

B0 - B35

SIZ1,

SIZ0

ENB

tENS tENH

tENS

tDS

tENH

tDH

To FIFO2

Previous Word in FIFO2 Output Register Next Word From FIFO2

LOW

W/RALOW

LOW

HIGH

LOW

HIGH

FIFO2 Full

tCLK

tCLKH tCLKL

tSKEW1(1) tCLK

tCLKH tCLKL

tWFF tWFF

AEB

CLKA

ENB

3146 drw18

ENA

CLKB 2

ENS

ENH

ENS

ENH

X Long Word in FIFO1 (X+1) Long Words in FIFO1

SKEW2(1)

PAE

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TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

JANUARY 14, 2009

AEA

CLKB

ENA

3146 drw19

ENB

CLKA 2

ENS

ENH

ENS

ENH

(X+1) Long Words in FIFO2

X Long Words in FIFO2

SKEW2(1)

PAE

NOTES:

1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising

CLKB edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.

2 . FIFO2 Write (CSB = LOW, W/RB = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW).

3. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW2 is referenced from the rising CLKB edge that

writes the last word or byte of the long word, respectively.

Figure 19. Timing for

AEAAEA

AEA

when FIFO2 is Almost-Empty

AFA

CLKA

ENB

3146 drw20

ENA

CLKB

ENS

ENH

ENS

ENH

[64-(X+1)] Long Words in FIFO1 (64-X) Long Words in FIFO1

SKEW2(1)

PAF

NOTES:

1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising

CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKB cycle later than shown.

2 . FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW).

3. Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW2 is referenced from the last word or byte read of

the long word, respectively.

Figure 20. Timing for

AFAAFA

AFA

when FIFO1 is Almost-Full

AFB

CLKB

ENA

3146 drw21

ENB

CLKA

ENS

ENH

ENS

ENH

[64-(X+1)] Long Words in FIFO2 (64-X) Long Words in FIFO2

SKEW2(1)

PAF

NOTES:

1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising

CLKB edge and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKA cycle later than shown.

2 . FIFO2 Write (CSB = LOW, W/RB = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW).

3. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, AFB is set LOW by the last word or byte read of

the long word, respectively. Figure 21. Timing for

AFBAFB

AFB

when FIFO2 is Almost-Full

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

JANUARY 14, 2009

NOTE:

1. Port B Parity Generation off (PGB = LOW).

Figure 22. Timing for Mail1 Register and

MBF1MBF1

MBF1

Flag

3146 drw22

CLKA

ENA

A0 - A35

MBA

CSA

W/RA

CLKB

MBF1

CSB

SIZ1,

SIZ0

ENB

B0 - B35

W/RB

ENS

ENH

W1 (Remains valid in Mail1 Register after read)

FIFO1 Output Register

PMF

ENS

MDV

PMR

DIS

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

JANUARY 14, 2009

NOTE:

1. Port-A Parity Generation off (PGA = LOW).

Figure 24. ODD/

EVENEVEN

EVEN

. W/

A, MBA, and PGA to

PEFAPEFA

PEFA

Timing

Figure 23. Timing for Mail2 Register and

MBF2MBF2

MBF2

Flag

3146 drw24

ODD/

EVEN

PEFA

PGA

MBA

W/RA

Valid Valid Valid Valid

POPE

PEPE

POPE

PEPE

3146 drw23

CLKB

ENB

B0 - B35

SIZ1,

SIZ0

CSB

W/RB

CLKA

MBF2

CSA

MBA

ENA

A0 - A35

W/RA

tENH

tDH

tENH

tEN

FIFO2 Output Register

W1 (Remains valid in Mail2 Register after read)

tSZH

tENS

tSZS

tDS

tPMF tPMF

tENS

tPMR

tMDV tDIS

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

JANUARY 14, 2009

3146 drw25

ODD/

EVEN

PEFB

PGB

SIZ1,

SIZ0

W/RB

Valid Valid Valid Valid

POPE

PEPE

POPE

PEPE

Figure 25. ODD/

EVENEVEN

EVEN

. W/

B, SIZ1, SIZ0, and PGB to

PEFBPEFB

PEFB

Timing

Figure 27. Parity Generation Timing when Reading from the Mail1 Register

3146 drw27

ODD/

EVEN

B8, B17,

B26, B35

PGB

SIZ1,

SIZ0

W/RB

Mail1

Data

Generated Parity Generated Parity Mail1 Data

CSB LOW

tEN tMDV

tPEPB tPOPB tPEPB

Figure 26. Parity Generation Timing when Reading from the Mail2 Register

3146 drw26

ODD/

EVEN

A8, A17,

A26, A35

PGA

MBA

W/RA

Mail2

Data

Generated Parity Generated Parity Mail2 Data

CSA LOW

tEN

tPEPB

tMDV

tPOPB tPEPB

NOTE:

1. ENA is HIGH.

NOTE:

1. ENB is HIGH.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723614 CMOS SYNCBIFIFO™™

™™

™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

JANUARY 14, 2009

NOTE:

1. Includes probe and jig capacitance.

Figure 28. Load Circuit and Voltage Waveforms

3146 drw28

From Output

Under Test

30 pF

1.1 kΩ

5 V

680Ω

LOAD CIRCUIT

3 V

GND

Timing

Input

Data,

Enable

Input

GND

3 V

1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES VOLTAGE WAVEFORMS

PULSE DURATIONS

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

3 V

GND

3 V

1.5 V

Output

Enable

Low-Level

Output

High-Level

Output

3 V

VOL

GND

≈3 V

1.5 V 1.5 V

1.5 V

VOH

≈OV

GND

VOH

VOL

1.5 V 1.5 V

Input

In-Phase

Output

High-Level

Input

Low-Level

Input

1.5 V

3 V

PLZ

PHZ

PZL

PZH

(1)

CORPORATE HEADQUARTERS for SALES: for TECH SUPPORT:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1753

San Jose, Ca 95138 fax: 408-284-2775 FIFOhelp@idt.com

www.idt.com

NOTES:

1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.

2. Green parts are available. For specific speeds and packages contact your sales office.

ORDERING INFORMATION

3146 drw29

723614 64 x 36 x 2 SyncBiFIFO™

Device Type

X XX X X

Power Speed Package

Clock Cycle Time (t CLK)

Speed in Nanoseconds

Process/

Temperature

Range

BLANK

(1)

PQF

Commercial (0°C to +70°C)

Industrial (40°C to +85°C)

Thin Quad Flat Pack (TQFP, PN120-1)

Plastic Quad Flat Pack (PQFP, PQ132-1)

Commercial Only

Com'l & Ind'l

Low Power

GGreen

XXXXXX

DATASHEET DOCUMENT HISTORY

03/05/2002 pgs. 1, 8, 9 and 32.

06/06/2005 pgs. 1, 2, 3 and 32.

01/14/2009 pg. 32.