24 GHz VCO and PGA
with 2-Channel PA Output
Data Sheet
ADF5901
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2017 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
24 GHz to 24.25 GHz voltage controlled oscillator (VCO)
2-channel 24 GHz power amplifier (PA) with 8 dBm output
Single-ended outputs
2-channel muxed outputs with mute function
Programmable output power
N divider output (frequency discriminator)
24 GHz local oscillator (LO) output buffer
250 MHz signal bandwidth
Power control detector
Auxiliary 8-bit ADC
±5°C temperature sensor
4-wire serial peripheral interface (SPI)
Electrostatic discharge (ESD) performance
Human body model (HBM): 2000 V
Charged device model (CDM): 250 V
Qualified for automotive applications
APPLICATIONS
Automotive radars
Industrial radars
Microwave radar sensors
Industrial sensors
Precision instrumentation
Tank level sensors
Smart sensors
Door opening
Energy saving
Commercial sensors: object detection and tracking
Cars, boats, aircraft, and UAVs (drones): collision avoidance
Intelligent transportation systems: intelligent traffic
monitoring and control
Surveillance and security
GENERAL DESCRIPTION
The ADF5901 is a 24 GHz Tx monolithic microwave integrated
circuit (MMIC) with an on-chip, 24 GHz VCO with PGA and
dual Tx channels for radar systems. The on-chip, 24 GHz VCO
generates the 24 GHz signal for the two Tx channels and the LO
output. Each Tx channel contains a power control circuit. There
is also an on-chip temperature sensor.
Control of all the on-chip registers is through a simple 4-wire
interface.
The ADF5901 comes in a compact 32-lead, 5 mm × 5 mm
LFCSP package.
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
TXOUT1
TXOUT2
LOOUT
VTUNE
RSET
GND
TX_AHI
ATEST
RF_AHI AHI DVDD
VREG C1 C2
MUXOUT
AUX AUX
VCO_AHI
REFIN
N-DIVIDER
VCO
CAL
R-DIVIDER
TEMPERATURE
SENSOR
ADC
32-BIT
DATA
REGISTER
DOUT
LE
DATA
CLK
CE
÷2
÷2
REFERENCE
REGULATOR
ADC
ADC
ADF5901
13336-001
ADF5901 Data Sheet
Rev. B | Page 2 of 26
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 11
Reference Input Section ............................................................. 11
RF INT Divider ........................................................................... 11
INT, FRAC, and R Relationship ............................................... 11
R Counter .................................................................................... 11
Input Shift Register..................................................................... 11
Program Modes .......................................................................... 11
Register Maps .................................................................................. 13
Register 0 ..................................................................................... 15
Register 1 ..................................................................................... 16
Register 2 ..................................................................................... 17
Register 3 ..................................................................................... 18
Register 4 ..................................................................................... 19
Register 5 ..................................................................................... 20
Register 6 ..................................................................................... 20
Register 7 ..................................................................................... 21
Register 8 ..................................................................................... 22
Register 9 ..................................................................................... 22
Register 10 ................................................................................... 23
Register 11 ................................................................................... 23
Initialization Sequence .............................................................. 23
Recalibration Sequence ............................................................. 23
Temperature Sensor ................................................................... 24
RF Synthesis: a Worked Example ............................................. 24
Applications Information .............................................................. 25
Application of the ADF5901 in FMCW Radar ...................... 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
Automotive Products ................................................................. 26
REVISION HISTORY
8/2017—Rev. A to Rev. B
Changes to Figure 17 ...................................................................... 13
Changes to Figure 20 ...................................................................... 17
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 27
7/2016—Rev. 0 to Rev. A
Changes to Applications Section .................................................... 1
Changes to Initialization Sequence Section and Recalibration
Sequence Section ............................................................................ 23
12/2015—Revision 0: Initial Version
Data Sheet ADF5901
Rev. B | Page 3 of 26
SPECIFICATIONS
AHI = TX_AHI = RF_AHI = VCO_AHI = DVDD = 3.3 V ± 5%, AGND = 0 V, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise
noted. Operating temperature range is −40°C to +105°C.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
OPERATING CONDITIONS
RF Frequency Range 24 24.25 GHz
VCO CHARACTERISITICS
VTUNE 1 2.8 V
VTUNE Impedance 100 kΩ
VCO Phase Noise Performance
At 100 kHz Offset −88 dBc/Hz
At 1 MHz Offset
−108
At 10 MHz Offset −128 dBc/Hz
Amplitude Noise −150 dBc/Hz At 1 MHz offset
Static Pulling fVCO Change vs. Load ±2 MHz Open-loop into 2:1 voltage standing wave ratio
(VSWR) load
Dynamic Pulling Tx On/Off Switch Change ±10 MHz Open-loop
Dynamic Pulling Tx to Tx Switch Change
±5
Open-loop
Pushing fVCO Change vs. AHI Change ±5 MHz/V Open-loop
Spurious Level Harmonics −30 dBc
Spurious Level Nonharmonics <−70 dBc
POWER SUPPLIES
AHI, TX_AHI, RF_AHI, VCO_AHI, DVDD 3.135 3.3 3.465 V
Total Current, ITOTA L 1 170 mA
Software Power-Down Mode 500 µA
Hardware Power-Down Mode
200
Tx OUTPUT
Output Power 2 8 10 dBm
Output Impedance
50
On/Off Isolation 30 dB Single Tx output switched on/off
Tx to Tx Isolation 25 dB
Power-Up/Power-Down Time 200 ns
LO OUTPUT
Output Power −7 −1 +5 dBm
Output Impedance 50 Ω
On/Off Isolation 30 dB
AUX PIN OUTPUT
Output Power −9 −5 0 dBm Single-ended
Output Frequency
Divide by 2 Output 12 12.125 GHz
Divide by 4 Output 6 6.0625 GHz
Output Impedance 200 Ω Differential
On/Off Isolation 30 dB
AUX to LO Isolation 30 dB
TEMPERATURE SENSOR
Analog Accuracy ±5 °C Following one-point calibration
Digital Accuracy ±5 °C Following one-point calibration
Sensitivity
6.4
ADF5901 Data Sheet
Rev. B | Page 4 of 26
Parameter
Min
Typ
Max
Test Conditions/Comments
ADC
Resolution 8 Bits
Integral Nonlinearity (INL) ±1 LSB
Differential Nonlinearity (DNL) ±1 LSB
Least Significant Bit (LSB) 7.4 mV
REFIN CHARACTERISITICS
REFIN Input Frequency 10 260 MHz −5 dBm minimum to +9 dBm maximum biased
at AHI/2 (ac coupling ensures 1.8/2 bias); for
frequencies < 10 MHz, use a dc-coupled, CMOS-
compatible square wave with a slew rate >
25 V/µs
REFIN Input Capacitance 1.2 pF
REF
IN
Input Current
±100
LOGIC INPUTS
Input Voltage
High (VIH) 1.4 V
Low (VIL) 0.6 V
Input Current (IINH, IINL) ±1 µA
Input Capacitance (CIN) 10 pF
LOGIC OUTPUTS
Output Voltage
High (VOH)2 VDD −
0.4
V
Low (V
OL
)
0.4
Output Current
High (IOH) 500 µA
Low (IOL) 500 µA
1 TA = 25°C; AHI = 3.3 V; fREFIN = 100 MHz; RF = 24.125 GHz following initialization sequence in the Initialization Sequence section.
2 VDD selected from IO level bit (DB11 in Register 3).
TIMING SPECIFICATIONS
AHI = TX_AHI = RF_AHI = VCO_AHI = DVDD = 3.3 V ± 5%, AGND = 0 V, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise
noted. Operating temperature range is −40°C to +105°C.
Table 2. Write Timing
Parameter Limit at TMIN to TMAX Unit Description
t1 20 ns min LE setup time
t
2
10
ns min
DATA to CLK setup time
t3 10 ns min DATA to CLK hold time
t4 25 ns min CLK high duration
t5 25 ns min CLK low duration
t6 10 ns min CLK to LE setup time
t7 20 ns min LE pulse width
t8 10 ns max LE setup time to DOUT
t9 15 ns max CLK setup time to DOUT
Data Sheet ADF5901
Rev. B | Page 5 of 26
Write Timing Diagram
Figure 2. Write Timing Diagram
Figure 3. Load Circuit for DOUT/MUXOUT Timing, CL = 10 pF
CLK
DATA
LE
DB30 DB1
(CO NTROL BI T C2)
DB2
(CO NTROL BI T C3) DB0 (L S B)
(CONTRO
L
BIT C1)
t
1
t
2
t
3
t
4
t
5
t
7
t
6
DB31 (MS B)
DB0DB1
t
8
t
9
DB31
(MSB) DB30
DOUT
13336-002
500µA I
OL
500µA I
OH
V
DD
/2
TO DOUT AND
MUXOUT P INS C
L
10pF
13336-003
ADF5901 Data Sheet
Rev. B | Page 6 of 26
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
AHI to GND −0.3 V to +3.9 V
AHI to TX_AHI
−0.3 V to +0.3 V
AHI to RF_AHI −0.3 V to +0.3 V
AHI to VCO_AHI −0.3 V to +0.3 V
AHI to DVDD −0.3 V to +0.3 V
VTUNE to GND −0.3 V to +3.6 V
Digital Input/Output Voltage to GND −0.3 V to DVDD + 0.3 V
Operating Temperature Range
−40°C to +105°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
θJA Thermal Impedance1 (Paddle
Soldered)
40.83 °C/W
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 40 sec
Transistor Count
CMOS 177,381
Bipolar 2315
ESD
Charged Device Model 250 V
Human Body Model 2000 V
1 Two signal planes (that is, on top and bottom surfaces of the board), two
buried planes, and nine vias.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Data Sheet ADF5901
Rev. B | Page 7 of 26
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1, 3, 6, 8,
10, 12, 13,
19
GND RF Ground. Tie all ground pins together.
2 TXOUT1 24 GHz Tx Output 1.
4, 5 TX_AHI Voltage Supply for the Tx Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the ground plane
as close as possible to this pin. TX_AHI must be the same value as AHI.
7 TXOUT2 24 GHz Tx Output 2.
9 ATEST Analog Test Pin.
11 LOOUT LO Output.
14 RF_AHI Voltage Supply for the RF Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the ground plane
as close as possible to this pin. RF_AHI must be the same value as AHI.
15 REFIN Reference Input. This pin is a CMOS input with a nominal threshold of DVDD/2 and a dc equivalent input
resistance of 100 kΩ. See Figure 14. This input can be driven from a TTL or CMOS crystal oscillator, or it can be
ac-coupled.
16 AHI Voltage Supply for the Analog Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the ground
plane as close as possible to this pin.
17 DVDD Digital Power Supply. This supply may range from 3.135 V to 3.465 V. Place decoupling capacitors (0.1 μF, 1 nF,
and 10 pF) to the ground plane as close as possible to this pin. DVDD must be the same value as AHI.
18 VREG Internal 1.8 V Regulator Output. Connect a 220 nF capacitor to ground as close as possible to this pin.
20 CE Chip Enable. A logic low on this pin powers down the device. Taking the pin high powers up the device,
depending on the status of the power-down bit, PD1.
21
CLK
Serial Clock Input. This serial clock input clocks in the serial data to the registers. The data is latched into the
32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
22 DATA Serial Data Input. The serial data is loaded MSB first with the four LSBs as the control bits. This input is a high
impedance CMOS input.
23 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
16 latches with the latch selected via the control bits.
24 DOUT Serial Data Output.
25 MUXOUT Multiplexer Output. This multiplexer output allows either the scaled RF or the scaled reference frequency to be
accessed externally.
26 RSET Resistor Setting Pin. Connecting a 5.1 kΩ resistor between this pin and GND sets an internal current. The
nominal voltage potential at the RSET pin is 0.62 V.
27
AUX
Auxiliary Output. The VCO/2 output or VCO/4 is available.
28 AUX Complementary Auxiliary Output. The VCO/2 output or VCO/4 is available.
GND
NOTES
1. THE LFCSP HAS AN EXPOSED PAD
THAT MUS T BE CONNECTED TO GND.
TX
OUT
1
GND
TX_AHI
TX_AHI
GND
TX
OUT
2
GND
DOUT
LE
DATA
CLK
CE
GND
VREG
DVDD
ATEST
GND
LO
OUT
GND
GND
RF_AHI
REF
IN
AHI
C2
C1
VCO_AHI
V
TUNE
AUX
AUX
R
SET
MUXOUT
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
ADF5901
TOP VIEW
(No t t o Scal e)
13336-004
ADF5901 Data Sheet
Rev. B | Page 8 of 26
Pin No.
Mnemonic
Description
29 VTUNE Control Input to the VCO. This voltage determines the output.
30 VCO_AHI Voltage Supply for the VCO Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the ground
plane as close as possible to this pin. VCO_AHI must be the same value as AHI.
31
C1
Decoupling Capacitor 1. Place a 47 nF capacitor to ground as close as possible to this pin.
32 C2 Decoupling Capacitor 2. Place a 220 nF capacitor to ground as close as possible to this pin.
EP Exposed Pad. The LFCSP has an exposed pad that must be connected to GND.
Data Sheet ADF5901
Rev. B | Page 9 of 26
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 5. Tx Output Power vs. Output Frequency
Figure 6. Transmitter 1 (Tx1) Output Power Variation with Temperature and
Supply vs. Output Frequency
Figure 7. Tx Output Power vs. Tx Amplitude Calibration Reference Code
Figure 8. LO Output Power vs. Output Frequency
Figure 9. AUX/AUX Output Power vs. Output Frequency with Divide by 2
Selected
Figure 10. AUX/AUX Output Power vs. Output Frequency with Divide by 4
Selected
0
2
4
6
8
10
12
23.95 24.00 24.05 24.10 24.15 24.20 24.25 24.30
OUTPUT P OW E R ( dBm)
OUTPUT FREQUENCY (GHz)
–40°C
+25°C
+105°C
Tx1
Tx2
13336-005
OUTSIDE OF SPECIFIED RANGE
0
2
4
6
8
10
12
23.95 24.00 24.05 24.10 24.15 24.20 24.25 24.30
OUTPUT P OW E R ( dBm)
OUTPUT FREQUENCY (GHz)
–40°C
+25°C
+105°C
3.300V
3.465V
3.135V
13336-006
OUTSIDE OF SPECIFIED RANGE
–20
–15
–10
–5
0
5
10
15
010 20 30 40 50 60 70 80 90 100
OUTPUT P OW E R ( dBm)
Tx AMPLITUDE CALI BR ATIO N RE FERENCE CODE
–40°C
+25°C
+105°C
13336-007
–8
–6
–4
–2
0
4
2
6
23.95 24.00 24.05 24.10 24.15 24.20 24.25 24.30
OUTPUT P OW E R ( dBm)
OUTPUT FREQUENCY (GHz)
–40°C
+25°C
+105°C
OUTSIDE OF SPECIFIED RANGE
13336-008
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
11.99 12.01 12.03 12.05 12.07 12.09 12.11 12.13
OUTPUT P OW E R ( dBm)
OUTPUT FREQUENCY (GHz)
–40°C
+25°C
+105°C
AUX
AUX
OUTSIDE OF SPECIFIED RANGE
13336-009
–5
–4
–3
–2
–1
0
1
2
3
4
5
5.99 6.00 6.01 6.02 6.03 6.04 6.05 6.06 6.07
OUTPUT P OW E R ( dBm)
–40°C
+25°C
+105°C
AUX
AUX
OUTSIDE OF SPECIFIED RANGE
OUTPUT FREQUENCY (GHz)
13336-010
ADF5901 Data Sheet
Rev. B | Page 10 of 26
Figure 11. VTUNE Frequency Range
Figure 12. Open-Loop Phase Noise on Tx1 Output at 24.125 GHz
Figure 13. ATEST Voltage and ADC Code vs. Temperature
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
23.75 23.88 24.10 24.13 24.25 24.38 24.50
V
TUNE
(V)
OUTPUT FREQUENCY (GHz)
13336-011
–40°C
+25°C
+105°C
OUTSIDE OF SPECIFIED RANGE
–150
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
1k 10k 100k 1M 10M
PHASE NOISE (dBc/Hz)
FREQUENCY OFF SET (Hz)
13336-012
0
50
100
150
200
250
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
100
110
120
ADC CODE (Coun t )
AT EST (V)
TEMPERATURE ( ºC)
13336-013
Data Sheet ADF5901
Rev. B | Page 11 of 26
THEORY OF OPERATION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 14. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This configuration ensures that there is no loading of
the REFIN pin on power-down.
Figure 14. Reference Input Stage
RF INT DIVIDER
The RF INT counter allows a division ratio in the RF feedback
counter. Division ratios from 75 to 4095 are allowed.
INT, FRAC, AND R RELATIONSHIP
Generate the RF VCO frequency (RFOUT) using the INT and
FRAC values in conjunction with the R counter, as follows:
RFOUT = fREF × (INT + (FRAC/225)) × 2 (1)
where:
RFOUT is the output frequency of internal VCO.
fREF is the internal reference frequency.
INT is the preset divide ratio of the binary 12-bit counter
(75 to 4095).
FRAC is the numerator of the fractional division (0 to 225 − 1).
fREF = REFIN × ((1 + D)/(R × (1 + T))) (2)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit (0 or 1).
R is the preset divide ratio of the binary, 5-bit, programmable
reference counter (1 to 32).
T is the REFIN divide by 2 bit (0 or 1).
Figure 15. RF N Divider
Figure 16. Reference Divider
R COUNTER
The 5-bit R counter allows the input reference frequency (REFIN)
to be divided down to supply the reference clock to the VCO
calibration block. Division ratios from 1 to 32 are allowed.
INPUT SHIFT REGISTER
The ADF5901 digital section includes a 5-bit RF R counter,
a 12-bit RF N counter, and a 25-bit FRAC counter. Data is
clocked into the 32-bit input shift register on each rising edge of
CLK. The data is clocked in MSB first. Data is transferred from
the input shift register to one of 12 latches on the rising edge of
LE. The destination latch is determined by the state of the five
control bits (C5, C4, C3, C2, and C1) in the input shift register.
These are the five LSBs (DB4, DB3, DB2, DB1, and DB0,
respectively), as shown in Figure 2. Table 5 shows the truth
table for these bits. Figure 17 and Figure 18 show a summary of
how the latches are programmed.
PROGRAM MODES
Table 5 and Figure 19 through Figure 30 show how to set up the
program modes in the ADF5901.
Several settings in the ADF5901 are double buffered. These
include the LSB fractional value, R counter value (R divider),
reference doubler, clock divider, RDIV2, and MUXOUT. This
means that two events must occur before the device uses a new
value for any of the double-buffered settings. First, the new
value is latched into the device by writing to the appropriate
register. Second, a new write must be performed on Register R5.
For example, updating the fractional value can involve a write to
the 13 LSB bits in Register R6 and the 12 MSB bits in Register R5.
Write to Register R6 first, followed by the write to Register R5.
The frequency change begins after the write to Register R0.
Double buffering ensures that the bits written to in Register R6
do not take effect until after the write to Register R5.
BUFFER TO R COUNTER
REF
IN
100kΩ
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
13336-014
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRAC
VALUE
INT
REG
RF N DIVI DE R
N = INT + FRAC/2
25
FROM RF
INPUT STAGE TO CAL
BLOCK
N COUNTER
13336-015
×2
DOUBLER 5-BIT
R COUNTER ÷2
DIVIDER
TO CAL
BLOCK
REFIN
R DIVIDER
13336-016
ADF5901 Data Sheet
Rev. B | Page 12 of 26
Table 5. C5, C4, C3, C2, and C1 Truth Table
Control Bits
C5 (DB4) C4 (DB3) C3 (DB2) C2 (DB1) C1 (DB0) Register
0 0 0 0 0 R0
0 0 0 0 1 R1
0 0 0 1 0 R2
0 0 0 1 1 R3
0 0 1 0 0 R4
0 0 1 0 1 R5
0 0 1 1 0 R6
0 0 1 1 1 R7
0 1 0 0 0 R8
0 1 0 0 1 R9
0 1 0 1 0 R10
0 1 0 1 1 R11
Data Sheet ADF5901
Rev. B | Page 13 of 26
REGISTER MAPS
Figure 17. Register Summary (Register 0 to Register 6)
1
DBR = DOUBLE BUFF E RE D RE G ISTER— BUFFE RE D BY THE WRI TE T O REGIS TER 5.
REGIST ER 0 (R0)
REGIST ER 1 (R1)
REGIST ER 3 (R3)
REGIST ER 4 (R4)
REGIST ER 2 (R2)
REGIST ER 5 (R5)
REGIST ER 6 (R6)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
10 0 0 0 0 0 0
CONTROL
BITS
AG2 AG1 AG0 AD 1 1 1 1 PRC PNC 1Tx2C Tx1C PVCO VCAL PADC PTx2 PTx1 PLO C4(0) C3(0) C2(0) C1(0)
C5(0)
PUP LO
PUP Tx1
PUP Tx2
PUP ADC
VCO CAL
PUP VCO
Tx1 AMP CAL
Tx2 AMP CAL
PUP NCNTR
PUP RCNTR
AUX DIV
RESERVED AUX BUFFER
GAIN RESERVED
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 1 1 1 1 1 1 1
CONTROL
BITS
1 1 1 1 0 1 1 1 1 1 1 C4(0) C3(0) C2(0) C1(1)
Tx AM P CAL REF CODE
C5(0)TAR7 TAR6 TAR5 TAR4 TAR3 TAR2 TAR1 TAR0
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0
CONTROL
BITS
0 0 0 0 0 1 0 AS AA0 AA0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C4(0) C3(0) C2(1) C1(0)
RESERVED ADC CLOCK DIVIDER
ADC
AVERAGE
ADC START
C5(0)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 M3 M2 M1 M0 IOL RC5 RC4 RC3 RC2 RC1 RC0 C4(0) C3(0) C2(1) C1(1)
CONTROL
BITS
MUXOUTRESERVED
C5(0)
READBACK CONT ROL
IO LEVEL
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 AB9 AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0 C4(0) C3(1) C2(0) C1(0)
CONTROL
BITS
RESERVED RESERVED
TEST BUS
TO PIN
0 0 NDM 0 0 0 0 TBA TBP
ANALO G TEST BUS
C5(0)
TEST BUS
TO ADC
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 C4(0) C3(1) C2(0) C1(1)
CONTROL
BITS
RESERVED FRAC MSB W ORDINT EGER W ORD
C5(0)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 C4(0) C3(1) C2(1) C1(0)
CONTROL
BITS
FRAC LSB W ORD
C5(0)
DBR
1
RESERVED
RESERVED
DBR
1
13336-017
N DIV TO
MUXOUT EN
ADF5901 Data Sheet
Rev. B | Page 14 of 26
Figure 18. Register Summary (Register 7 to Register 11)
1
DBR = DOUBLE BUFF E RE D RE GI S TER— BUFFE RE D BY THE WRITETO REGISTER 5.
REGIST ER 7 (R7)
REGIST ER 8 (R8)
REGISTER 10 (R10)
REGISTER 9 (R9)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00 0 0 0 0 MR 1
CONTROL
BITS
RD2 RD R4 R3 R2 R1 R0 C4(0) C3(1) C2(1) C1(1)
C5(0)
REF DO UBLE R
RDIV2
RESERVED
MASTER
RESET
R DIVIDER DBR
1
DBR
1
DBR
1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 1 00 0 00 0
CONTROL
BITS
0 0 0 0 0 0 0 0 0 FC9 FC8 FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 C4(1) C3(0) C2(0) C1(0)
FREQENCY CA L DI VIDER
C5(0)
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 1 0 1 0 1 0 0
CONTROL
BITS
0 1 0 0 0 0 0 1 0 1 1 1 0 0 1 0 0 1 C4(1) C3(0) C2(0) C1(1)
C5(0)
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 1 1 1 0 1 0 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 1 0C4(1) C3(0) C2(1) C1(0)
CONTROL
BITS
RESERVED
C5(0)
CLO CK DIVIDER
C1D11C1D10 C1D9 C1D8 C1D7 C1D6 C1D5 C1D4 C1D3 C1D2 C1D1 C1D0
DBR
1
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CR C4(1) C3(0) C2(1) C1(1)
CONTROL
BITS
RESERVED
C5(0)
REGISTER 11 (R11)
CNTR
RESET
13336-018
Data Sheet ADF5901
Rev. B | Page 15 of 26
Figure 19. Register 0 (R0)
REGISTER 0
Control Bits
With Bits[C5:C1] set to 00000, Register R0 is programmed.
Figure 19 shows the input data format for programming this
register.
Auxiliary Buffer Gain
Bits[DB23:DB21] set the auxiliary output buffer gain (see
Figure 19).
Auxiliary Divide by 2
Bit DB20 selects the auxiliary output divider. Setting this bit to 0
selects divide by 2 (6 GHz output). Setting the bit to 1 selects
divide by 1 (12 GHz output).
Power-Up R Counter
Bit DB15 provides the power-up bit for the R counter block.
Setting this bit to 0 performs a power-down of the counter block.
Setting this bit to 1 returns the counter block to normal
operation.
Power-Up N Counter
Bit DB14 provides the power-up bit for the N counter block.
Setting this bit to 0 performs a power-down of the counter
block. Setting this bit to 1 returns the counter block to normal
operation.
Tx2 Amplitude Calibration
Bit DB12 provides the control bit for amplitude calibration of
the Transmitter 2 (Tx2) output. Set this bit to 0 for normal
operation. Setting this bit to 1 performs an amplitude
calibration of the Tx2 output.
Tx1 Amplitude Calibration
Bit DB11 provides the control bit for amplitude calibration of
the Tx1 output. Set this bit to 0 for normal operation. Setting
this bit to 1 performs an amplitude calibration of the Tx1
output.
Power-Up VCO
Bit DB10 provides the power-up bit for the VCO. Setting this bit
to 0 performs a power-down of the VCO. Setting this bit to 1
performs a power-up of the VCO.
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
10 0 0 0 0 0 0
CONTROL
BITS
AG2 AG1 AG0 AD 1 1 1 1 PRC PNC 1Tx2C Tx1C PVCO VCAL
PADC
PTx2 PTx1 PLO C4(0) C3(0) C2(0) C1(0)
C5(0)
PUP LO
PUP Tx1
PUP Tx2
PUP ADC
VCO CAL
PUP VCO
Tx1 AMP CAL
Tx2 AMP CAL
PUP NCNTR
PUP RCNTR
AUX DIV
RESERVED AUX BUFFER
GAIN
PLO
0
1
PUP LO
POW ER UP LO
POWER DOWN LO
PTx1
0
1
PUP Tx1
POW ER UP Tx1
POWER DOWN Tx1
PTx2
0
1
PUP Tx2
POW ER UP Tx2
POWER DOWN Tx2
PADC
0
1
PUP ADC
POWER UP ADC
POWER DOWN ADC
VCAL
0
1
VCO CAL
VCO F ULL CAL
NORMAL OPERATION
PVCO
0
1
PUP VCO
POW ER UP VCO
POWER DOWN VCO
Tx1C
0
1
Tx1 AMP CAL
Tx1 AMP CAL
NORMAL OPERATION
Tx2C
0
1
Tx2 AMP CAL
Tx2 AMP CAL
NORMAL OPERATION
AD
0
1
AUX DIV
DIV 1
DIV 2
PNC
0
1
PUP NCNTR
POWER UP NCNTR
POWER DOWN NCNTR
PNC
0
1
PUP RCNTR
POWER UP RCNTR
POWER DOWN RCNTR
AG2
AG1
AG0 AUX BUF FE R GAI N
0 0 0 BUFFER DI SABL ED
0 0 1 GAIN SETTING 1
0 1 0 GAIN SETTING 2
0 1 1 GAIN SETTING 3
1 0 0 GAIN SETTING 4
1 0 1 GAIN SETTING 5
1 1 0 GAIN SETTING 6
1 1 1 GAIN SETTING 7
RESERVED
RESERVED
13336-019
ADF5901 Data Sheet
Rev. B | Page 16 of 26
VCO Calibration
Bit DB9 provides the control bit for frequency calibration of the
VCO. Set this bit to 0 for normal operation. Setting this bit to 1
performs a VCO frequency and amplitude calibration.
Power-Up ADC
Bit DB8 provides the power-up bit for the ADC. Setting this bit to
0 performs a power-down of the ADC. Setting this bit to 1
performs a power-up of the ADC.
Power-Up Tx2 Output
Bit DB7 provides the power-up bit for the Tx2 output. Setting
this bit to 0 performs a power-down of the Tx2 output. Setting
this bit to 1 performs a power-up of the Tx2 output. Only one
Tx output can be powered up at any time, either Tx1 (DB6) or
Tx2 (DB7).
Power-Up Tx1 Output
Bit DB6 provides the power-up bit for the Tx1 output. Setting
this bit to 0 performs a power-down of the Tx1 output. Setting
this bit to 1 performs a power-up of the Tx1 output. Only one
Tx output can be powered up at any time, either Tx1 (DB6) or
Tx2 (DB7).
Power-Up LO Output
Bit DB5 provides the power-up bit for the LO output. Setting
this bit to 0 performs a power-down of the LO output. Setting
this bit to 1 performs a power-up of the LO output.
REGISTER 1
Control Bits
With Bits[C5:C1] set to 00001, Register R1 is programmed.
Figure 20 shows the input data format for programming this
register.
Tx Amplitude Calibration Reference Code
Bits[DB12:DB5] set the Tx amplitude calibration reference code
(see Figure 20) for the two Tx outputs during calibration.
Calibrate the output power on the Tx outputs from −20 dBm to
8 dBm by setting the Tx amplitude calibration reference code
(see Figure 7).
Figure 20. Register 1 (R1)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 1 1 1 1 1 1 1
CONTROL
BITS
1 1 1 1 0 1 1 1 1 1 1 C4(0) C3(0) C2(0) C1(1)
Tx AMP CAL REF CO DE
C5(0)TAR7 TAR6 TAR5 TAR4 TAR3 TAR2 TAR1 TAR0
TAR7 TAR6 .......... TAR1 TAR0
0 0 .......... 0 0 0
0 0 .......... 0 1 1
0 0 .......... 1 0 2
0 0 .......... 1 1 3
. . .......... . . .
. . .......... . . .
. . .......... . . .
11.......... 0 0 252
1 1 .......... 01253
1 1 .......... 1 0 254
1 1 ......... 1 1 255
Tx AMP CAL REF CO DE
RESERVED
13336-020
Data Sheet ADF5901
Rev. B | Page 17 of 26
Figure 21. Register 2 (R2)
REGISTER 2
Control Bits
With Bits[C5:C1] set to 00010, Register R2 is programmed.
Figure 21 shows the input data format for programming this
register.
ADC Start
Bit DB15 starts the ADC conversion. Setting this bit to 1 starts
an ADC conversion.
ADC Average
Bits[DB14:DB13] program the ADC average, which is the
number of averages of the ADC output (see Figure 21).
ADC Clock Divider
Bits[DB12:DB5] program the clock divider, which is used as the
sampling clock for the ADC (see Figure 21). The output of the
R divider block clocks the ADC clock divider. Program a
divider value to ensure the ADC sampling clock is 1 MHz.
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0
CONTROL
BITS
0 0 0 0 0 1 0 AS AA0 AA0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C4(0) C3(0) C2(1) C1(0)
RESERVED ADC CLO CK DIVI DE R
ADC
AVERAGE
ADC S TART
C5(0)
AC7 AC6 AC1 AC0
ADC CLOCK DIVIDER
0 0 0 1 1
0 0 1 0 2
. . . . .
. . . . .
. . . . .
1 1 0 0 124
1 1 0 1 125
1 1 1 0 126
1 1 1 1 127
.
.
.
.
.
.
.
.
.
.
AS
0
1
ADC S TART
START ADC CO NV ERSION
NORMAL OPERAT IO N
AA1 AA0 ADC AVERAGE
0 0 1
0 1 2
1 0 3
1 1 4
13336-021
ADF5901 Data Sheet
Rev. B | Page 18 of 26
Figure 22. Register 3 (R3)
REGISTER 3
Control Bits
With Bits[C5:C1] set to 00011, Register R3 is programmed.
Figure 22 shows the input data format for programming this
register.
MUXOUT Control
Bits[DB15:DB12] control the on-chip multiplexer of the
ADF5901. See Figure 22 for the truth table.
Input/Output (IO) Level
Bit DB11 controls the DOUT logic levels. Setting this bit to 0 sets
the DOUT logic level to 1.8 V. Setting this bit to 1 sets the DOUT
logic level to 3.3 V.
Readback Control
Bits[DB10:DB5] control the readback data to DOUT on the
ADF5901. See Figure 22 for the truth table.
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00 0 0 0 0 0 11 0 00 1 0 0 1M3 M2 M1 M0 IOLRC5 RC4 RC3 RC2 RC1 RC0 C4(0) C3(0) C2(1) C1(1)
CONTROL
BITS
RESERVED
C5(0)
READBACK CONT RO L
IO LEVEL
RC3 RC2 RC1 RC0 READBACK CONTRO L
0 0 00NONE
0 0 0 1 REGI STER 0
00 1 0REGISTER 1
001 1 REG ISTER 2
010 0 REG ISTER 3
01 0 1REGISTER 4
0 1 1 0 REGSI TER 5
01 1 1REGISTER 6
1 0 00REGISTER 7
10 0 1REGISTER 8
10 1 0REGISTER 9
1 0 1 1 REGISTER 10
11 0 0REGISTER11
. . . . RESERVED
01 0 1RESERVED
0 1 1 0 ADC READBACK
RC4
0
0
0
0
0
0
0
0
0
0
0
0
0
.
1
101 1 1RESERVED
.. . .RESERVED
. . . .RESERVED
1 1 1 1 RESERVED
1
.
.
1
M3 M2
M1
M0 MUXOUT
0 0 0 0 TRISTATE O UTPUT
0 0 01LOGIC HIGH
0 0 1 0LOGIC LOW
0 0 1 1 R-DI V IDER O UT PUT
0 1 0 0 N-DI V IDER O UT PUT
0 1 01RESERVED
01 1 0RESERVED
011 1 CAL BUSY
1 0 0 0 RESERVED
1 0 01RESERVED
10 1 0RESERVED
1 0 1 1 R-DIVIDER/2
11 0 0N-DIVIDER/2
110 1 RESERVED
1 1 1 0 RESERVED
11 1 1RESERVED
RC5
0
0
0
0
0
0
0
0
0
0
0
0
0
.
0
0
0
.
.
1
IOL
0
1
IO LEVEL
3.3V LOGIC OUTPUTS
1.8V LOGIC OUTPUTS
1
DBR = DOUBLE-BUFF ERED REGISTER.
MUXOUT DBR
1
10849-022
Data Sheet ADF5901
Rev. B | Page 19 of 26
Figure 23. Register 4 (R4)
Figure 24. Register 5 (R5)
REGISTER 4
Control Bits
With Bits[C5:C1] set to 00100, Register R4 is programmed.
Figure 23 shows the input data format for programming this
register.
N Divider to MUXOUT Enable
Bit DB21 controls the internal N divider signal for MUXOUT.
Setting this bit to 0 enables the internal N divider signal to
MUXOUT. Setting this bit to 1 returns the device to normal
operation.
Test Bus to ADC
Bit DB16 controls the ATEST pin. Set this bit to 0 for normal
operation. Setting this bit to 1 connects the analog test bus to
the ADC input.
Test Bus to Pin
Bit DB15 controls the ATEST pin. Setting this bit to 0 sets the
ATEST pin to high impedance. Setting this bit to 1 connects the
analog test bus to the ATEST pin.
Analog Test Bus
Bits[DB14:DB5] control the analog test bus. This analog test bus
allows access to internal test signals for the temperature sensor.
See Figure 23 for the truth table.
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0
AB9
AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0 C4(0) C3(1) C2(0) C1(0)
CONTROL
BITS
RESERVED RESERVED
TEST BUS
TO PIN
0 0 NDM 000 0 TBATBP
ANALO G TEST BUS
C5(0)
TEST BUS
TO ADC
TBP
0
1
TEST BUS TO PIN
TEST BUS TO PIN
NORMAL OPERAT IO N
NDM
0
1
N DIV TO M UX OUT EN
NORMAL OPERAT IO N
ENABLE NDI V T O M UXOUT
TBA
0
1
TEST BUS TO ADC
TEST BUS TO ADC
NORMAL OPERAT IO N AB3 AB2 AB1 AB0
0 0 0 0
00 1 1
ANALO G TEST BUSAB7 AB6 AB5 AB4
0 0 0 0
0 0 0 0
AB9 AB8
0 0
0 1
0
259
NONE
TEMPERATURE SENSO R
13336-023
N DIV TO
MUXOUT E N
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 C4(0) C3(1) C2(0) C1(1)
CONTROL
BITS
RESERVED FRAC MS B W ORDINT EGER W ORD
C5(0)
N11 N10 ... N4 N3 N2 N1 N0
0 0 ... 0 0 0 0 0 NOT ALLOWED
0 0 ... 0 0 0 0 1 NOT ALLOWED
0 0 ... 0 0 0 1 0 NOT ALLOWED
. . ... . . . . . ...
0 0 ... 0 1 0 1 0 NOT ALLOWED
0 0 ... 01011 75
0 0 ... 01100 76
. . ... . . . . . ...
1 1 ... 11101 4093
1 1 ... 11110 4094
1 1 ... 11111 4095
F24 F23 .......... F14 F13 (FRAC)*
0 0 .......... 0 0 0
0 0 .......... 0 1 1
0 0 .......... 1 0 2
0 0 .......... 1 1 3
. . .......... . . .
. . .......... . . .
. . .......... . . .
1 1 .......... 0 0 4092
1 1 .......... 0 1 4093
1 1 .......... 1 0 4094
1 1 ......... 1 1 4095
*THE F RAC VAL UE IS MADE UP OF THE 1 2 -BI T M S B STORED IN
REGIST ER R5 , AND THE 1 3-BIT LS B REGI S TER S TORED IN
REGIST ER R6 . FRAC VAL UE = 1 3 -BI T LS B + 1 2 - BIT M S B × 2
13
.
INT EGER W ORD F RAC M S B W ORD
13336-024
ADF5901 Data Sheet
Rev. B | Page 20 of 26
REGISTER 5
Control Bits
With Bits[C5:C1] set to 00101, Register R5 is programmed.
Figure 24 shows the input data format for programming this
register.
12-Bit Integer Value (INT)
These 12 bits (Bits[DB28:DB17]) set the INT value, which
determines the integer part of the RF division factor. This INT
value is used in Equation 5. See the RF Synthesis: a Worked
Example section for more information. All integer values from
75 to 4095 are allowed.
12-Bit MSB Fractional Value (FRAC)
These 12 bits (Bits[DB16:DB5]), together with Bits[DB17:DB5]
(FRAC LSB word) in Register R6, control what is loaded as the
FRAC value into the fractional interpolator. This FRAC value
partially determines the overall RF division factor. It is also used
in Equation 1. These 12 bits are the most significant bits (MSB)
of the 25-bit FRAC value, and Bits[DB17:DB5] (FRAC LSB
word) in Register R6 are the least significant bits (LSB). See the
RF Synthesis: a Worked Example section for more information.
REGISTER 6
Control Bits
With Bits[C5:C1] set to 00110, Register R6 is programmed.
Figure 25 shows the input data format for programming
this register.
13-Bit LSB FRAC Value
These 13 bits (Bits[DB17:DB5]), together with Bits[DB16:DB5]
(FRAC MSB word) in Register R5, control what is loaded as the
FRAC value into the fractional interpolator. This FRAC value
partially determines the overall RF division factor. It is also used
in Equation 1. These 13 bits are the least significant bits (LSB)
of the 25-bit FRAC value, and Bits[DB14:DB3] (FRAC MSB
word) in Register R5 are the most significant bits (MSB). See
the RF Synthesis: a Worked Example section for more
information.
Figure 25. Register 6 (R6)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 0 0
0
F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 C4(0) C3(1) C2(1) C1(0)
CONTROL
BITS
FRAC LSB W ORD
C5(0)
F12 F11 .......... F1 F0 (FRAC)*
0 0 .......... 0 0 0
0 0 .......... 0 1 1
0 0 .......... 1 0 2
0 0 .......... 1 1 3
. . .......... . . .
. . .......... . . .
. . .......... . . .
1 1 .......... 0 0 8188
1 1 .......... 0 1 8189
1 1 .......... 1 0 8190
1 1 ......... 1 1 8191
1DBR = DOUBLE-BUFF ERED REGISTER.
*THE F RAC VAL UE IS MADE UP OF THE 1 2 -BI T M S B STORED IN
REGIST ER R5 , AND THE 1 3-BIT LS B REGI S TER S TORED IN
REGIST ER R6 . FRAC VAL UE = 1 3 -BI T LS B + 1 2 - BIT M S B × 213.
FRAC LSB W ORD
DBR1
RESERVED
13336-025
Data Sheet ADF5901
Rev. B | Page 21 of 26
Figure 26. Register 7 (R7)
REGISTER 7
Control Bits
With Bits[C5:C1] set to 00111, Register R7 is programmed.
Figure 26 shows the input data format for programming
this register.
Master Reset
Bit DB25 provides a master reset bit for the device. Setting this
bit to 1 performs a reset of the device and all register maps.
Setting this bit to 0 returns the device to normal operation.
Clock Divider
Bits[DB23:DB12] set a divider for the VCO frequency calibration.
Load the divider such that the time base is 10 µs (see Figure 26).
Divide by 2 (RDIV2)
Setting the DB11 bit to 1 inserts a divide by 2 toggle flip flop
between the R counter and VCO calibration block.
Reference Doubler
Setting DB10 to 0 feeds the REFIN signal directly to the 5-bit
R counter, disabling the doubler. Setting this bit to 1 multiplies
the REFIN frequency by a factor of 2 before the REFIN signal is
fed into the 5-bit R counter.
The maximum allowable REFIN frequency when the doubler is
enabled is 50 MHz.
5-Bit R Divider
The 5-bit R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the VCO calibration block. Division ratios from 1 to 31 are
allowed.
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00 0 0 0 0 MR 1
CONTROL
BITS
RD2 RD R4 R3 R2 R1 R0 C4(0) C3(1) C2(1) C1(1)
C5(0)
REF DO UBLE R
RDIV2
RESERVED
MASTER
RESET
R DIVIDER
R4 R3 R1 R0 R DI VIDER (R)
0 0 0 1 1
0 0 1 0 2
. . . . .
. . . . .
. . . . .
1 1 0 0 28
1 1 0 1 29
1 1 1 0 30
1 1 1 1 31
RD DOUBLER
0 DISABLED
1 ENABLED
RD2
0 DISABLED
1 ENABLED
R2
0
0
.
.
.
1
1
1
1
REF
RDIV2
MR
0
1
MASTER RESET
ENABLED
DISABLED
DBR1
DBR1
DBR1
CLO CK DIVIDER
C1D11 C1D10 .......... C1D2 C1D0
0 0 .......... 0 0 0
0 0 .......... 0 1 1
0 0 .......... 1 0 2
0 0 .......... 1 1 3
. . .......... . . .
. . .......... . . .
. . .......... . . .
1 1 .......... 0 0 4092
1 1 .......... 0 1 4093
1 1 .......... 1 0 4094
1 1 ......... 1 1 4095
C1D11C1D10 C1D9 C1D8 C1D7 C1D6 C1D5 C1D4 C1D3 C1D2 C1D1 C1D0
DBR1
CLO CK DIVIDER
RESERVED
13336-026
1DBR = DOUBLE-BUFF ERED REGISTER.
ADF5901 Data Sheet
Rev. B | Page 22 of 26
Figure 27. Register 8 (R8)
Figure 28. Register 9 (R9)
REGISTER 8
Control Bits
With Bits[C5:C1] set to 01000, Register R8 is programmed.
Figure 27 shows the input data format for programming this
register.
Frequency Calibration Clock
Bits[DB14:DB5] set a divider for the VCO frequency calibration
clock. Load the divider such that the time base is 10 µs (see
Figure 27).
REGISTER 9
Control Bits
With Bits[C5:C1] set to 01001, Register R9 is programmed.
Figure 28 shows the input data format for programming this
register.
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 1 0 0 0 0 0 0
CONTROL
BITS
0 0 0 0 0 0 0 0 0 FC9 FC8 FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 C4(1) C3(0) C2(0) C1(0)
FREQENCY CA L DI VIDER
C5(0)
RESERVED
FC9 FC8 ... FC4 FC3
FC2
FC1 FC0
0 0 ... 0 0 0 0 0
0 0 ... 0 0 0 0 1
0 0 ... 0 0 0 1 0
. . ... . . . . .
1
2
..... . . . . .
...
1 1 ... 1 1 1 0 1 1021
1 1 ... 1 1 1 1 0 1023
1 1 ... 1 1 1 1 1 1024
FREQUENCY CAL
DIVIDER
...
0
13336-027
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 1 0 1 0 1 0 0
CONTROL
BITS
0 1 0 0 0 0 0 1 0 1 1 1 0 0 1 0 0 1 C4(1) C3(0) C2(0) C1(1)
C5(0)
RESERVED
13336-028
Data Sheet ADF5901
Rev. B | Page 23 of 26
Figure 29. Register 10 (R10)
Figure 30. Register 11 (R11)
REGISTER 10
Control Bits
With Bits[C5:C1] set to 01010, Register R10 is programmed.
Figure 29 shows the input data format for programming this
register.
REGISTER 11
Control Bits
With Bits[C5:C1] set to 01011, Register R11 is programmed.
Figure 30 shows the input data format for programming this
register.
Counter Reset
Bit DB5 provides a counter reset bit for the counters. Setting
this bit to 1 performs a counter reset of the device counters.
Setting this bit to 0 returns the device to normal operation.
INITIALIZATION SEQUENCE
After powering up the device, administer the following
programming sequence. The following sequence locks the VCO
to 24.125 GHz with a 100 MHz reference and a 50 MHz
reference divider frequency:
1. Write 0x02000007 to Register R7 to perform a master reset.
2. Write 0x0000002B to Register R11 to reset the counters.
3. Write 0x0000000B to Register R11 to enable the counters.
4. Write 0x1D32A64A to Register R10.
5. Write 0x2A20B929 to Register R9.
6. Write 0x40003E88 to Register R8 to set the frequency
calibration divider clock to 100 kHz.
7. Write 0x809FE520 to Register R0 to power up the device
and LO (10 µs).
8. Write 0x011F4827 to Register R7 to set the R counter clock
to 50 MHz and the calibration clock to 100 kHz.
9. Write 0x00000006 to Register R6 to set the LSB FRAC = 0.
10. Write 0x01E28005 to Register R5 to set INT = 241 and
MSB FRAC = 1024. Therefore, N = 240.25.
11. Write 0x00200004 to Register R4 to set the ATEST pin to
high impedance.
12. Write 0x01890803 to Register R3 to set the IO level to
VDD = 3.3 V.
13. Write 0x00020642 to Register R2 to set the ADC clock to
1 MHz.
14. Write 0xFFF7FFE1 to Register R1 to set the Tx amplitude
level.
15. Write 0x809FE720 to Register R0 to set the VCO frequency
calibration (800 µs).
16. Write 0x809FE560 to Register R0 to power Tx1 on, Tx2 off,
and LO on.
17. Write 0x809FED60 to Register R0 to set the Tx1 amplitude
calibration (400 µs).
18. Write 0x809FE5A0 to Register R0 to turn Tx1 off, Tx2 on,
and LO on.
19. Write 0x809FF5A0 to Register R0 to set the Tx2 amplitude
calibration (400 µs).
20. Write 0x2800B929 to Register R9.
21. Write 0x809F25A0 to Register R0 to disable the R and N
counters.
RECALIBRATION SEQUENCE
The ADF5901 can be recalibrated after the initialization
sequence is complete and the device is powered up. The
recalibration sequence must be run for every 10°C temperature
change; the temperature can be monitored using the
temperature sensor (see the Temperature Sensor section).
1. Write 0x809FE520 to Register R0 to enable the counters.
Tx1 and Tx2 are off, and LO is on.
2. Write 0x2A20B929 to Register R9.
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
000 1 1 1 0 1 0 0 1 1 0 0 10 1 0 1 00 1 1 0 01 0 C4(1) C3(0) C2(1) C1(0)
CONTROL
BITS
RESERVED
C5(0)
13336-029
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CR C4(1) C3(0) C2(1) C1(1)
CONTROL
BITS
RESERVED
C5(0)
CNTR
RESET
13336-030
CR
0DISABLED
1ENABLED
CNTR RESET
ADF5901 Data Sheet
Rev. B | Page 24 of 26
3. Write 0xFFF7FFE1 to Register R1 to set the Tx amplitude
level.
4. Write 0x809FE720 to Register R0 to set the VCO frequency
calibration (800 µs).
5. Write 0x809FE560 to Register R0 to power Tx1 on, Tx2 off,
and LO on.
6. Write 0x809FED60 to Register R0 to set the Tx1 amplitude
calibration (400 µs).
7. Write 0x89FE5A0 to Register R0 to power Tx1 off, Tx2 on,
and LO on.
8. Write 0x809FF5A0 to Register R0 to set the Tx2 amplitude
calibration (400 µs).
9. Write 0x2800B929 to Register R9.
10. Write 0x809F25A0 to Register R0 to disable the R and N
counters.
TEMPERATURE SENSOR
The ADF5901 has an on-chip temperature sensor that can be
accessed on the ATEST pin or as a digital word on DOUT
following an ADC conversion. The temperature sensor operates
over the full operating temperature range of −40°C to +105°C.
The accuracy can be improved by performing a one-point
calibration at room temperature and storing the result in
memory.
With the temperature sensor on the analog test bus and test bus
connected to the ATEST pin (Register 4 set to 0x0000A064) the
ATEST voltage can be converted to temperature with the
following equation:
( )
GAIN
OFF
ATEST
V
VV
eTemperatur −
=C)(
(3)
where:
VATEST is the voltage on the ATEST pin.
VOFF = 0.699 V, the offset voltage.
VGAIN = 6.4 × 10−3, the voltage gain.
The temperature sensor result can be converted to a digital
word with the ADC and readback on DOUT with the following
sequence:
1. Write 0x809FA5A0 to Register R0 to enable the counters.
2. Write 0x00012064 to Register R4 to connect the analog test
bus to the ADC and VTEMP to the analog test bus.
3. Write 0x00028C82 to Register R2 to start the ADC
conversion.
4. Write 0x018902C3 to Register R3 to set the output ADC
data to DOUT.
5. Read back DOUT.
6. Write 0x809F25A0 to Register R0 to disable R and N
counters.
Convert the DOUT word to temperature with the following
equation:
( )( )
GAIN
OFFLSB
V
VVADC
eTemperatur −×
=C)(
(4)
where:
ADC is the ADC code read back on DOUT.
VLSB = 7.33 mV, the ADC LSB voltage.
VOFF = 0.699 V, the offset voltage.
VGAIN = 6.4 × 10−3, the voltage gain.
RF SYNTHESIS: A WORKED EXAMPLE
The following equation governs how to program the ADF5901:
RFOUT = (INT + (FRAC/225)) × (fREF) × 2 (5)
where:
RFOUT is the RF frequency output.
INT is the integer division factor.
FRAC is the fractionality.
fREF = REFIN × ((1 + D)/(R × (1 + T))) (6)
where:
REFIN is the reference frequency input.
D is the reference doubler bit, DB10 in Register R7 (0 or 1).
R is the reference division factor.
T is the reference divide by 2 bit, DB11 in Register R7 (0 or 1).
For example, in a system where a 24.125 GHz RF frequency
output (RFOUT) is required and a 100 MHz reference frequency
input (REFIN) is available, fREF is set to 50 MHz.
From Equation 6,
fREF = (100 MHz × (1 + 0)/(1 × (1 + 1)) = 50 MHz
From Equation 5,
24.125 GHz = 50 MHz × (N + FRAC/225) × 2
Calculating the N and FRAC values,
N = int(RFOUT/(fREF × 2)) = 241
FRAC = FMSB × 213 + FLSB
FMSB = int(((RFOUT/(fREF × 2)) − N) × 212) = 1024
FLSB = int(((((RFOUT/(fREF × 2)) − N) × 212) − FMSB) × 213) = 0
where:
FMSB is the 12-bit MSB FRAC value in Register R5.
FLSB is the 13-bit LSB FRAC value in Register R6.
int() makes an integer of the argument in parentheses.
Data Sheet ADF5901
Rev. B | Page 25 of 26
APPLICATIONS INFORMATION
APPLICATION OF THE ADF5901 IN FMCW RADAR
Figure 31 shows the application of the ADF5901 in a frequency
modulated continuous wave (FMCW) radar system.
In the FMCW radar system, the ADF4159 generates the
sawtooth or triangle ramps necessary for this type of radar to
operate.
The ADF4159 controls the VTUNE pin on the ADF5901 (Tx)
MMIC and thus the frequency of the VCO and the Tx output
signal on TXOUT1 or TXOUT2. The LO signal from the ADF5901
is fed to the LO input on the ADF5904.
The ADF5904 downconverts the signal from the four receiver
antennas to baseband with the LO signal from the Tx MMIC.
The downconverted baseband signals from the four receiver
channels on the ADF5904 are fed to the ADAR7251 4-channel,
continuous time, Σ-Δ analog-to-digital converter (ADC).
A digital signal processor (DSP) follows the ADC to handle the
target information processing.
Figure 31. FMCW Radar with ADF5901
ADF5901
ADF5904
ADF4159
TXOUT1
TXOUT2
RX3_RF
RX2_RF
RX1_RF
RX4_RF
LO_IN
LOOUT
RFINA
RFINB
AUX
AUX
ADAR7251
DSP
RX BASEBAND
VTUNE
CP
LOOP
FILTER
13336-031
ADF5901 Data Sheet
Rev. B | Page 26 of 26
OUTLINE DIMENSIONS
Figure 32. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-12)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADF5901ACPZ −40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-12
ADF5901ACPZ-RL7 −40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-12
ADF5901WCCPZ −40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-12
ADF5901WCCPZ-RL7
−40°C to +105°C
32-Lead Lead Frame Chip Scale Package [LFCSP]
CP-32-12
EV-ADF5901SD2Z Evaluation Board
1 Z = RoHS Compliant Part.
AUTOMOTIVE PRODUCTS
The ADF5901W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
0.50
0.40
0.30
01-26-2016-B
1
0.50
BSC
BOTTOM VIEWTOP VIEW
PIN 1
INDICATOR
32
9
16
17
2425
8
EXPOSED
PAD
PIN 1
INDICATOR
SEATING
PLANE
0.05 M AX
0.02 NO M
0.20 REF
COPLANARITY
0.08
0.30
0.25
0.18
5.10
5.00 SQ
4.90
0.80
0.75
0.70
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE PIN CO NFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
0.25 M IN
3.75
3.60 SQ
3.55
COM P LIANT T O JEDE C S TANDARDS M O-220-WHHD-5.
PKG-004570
©2015–2017 Analog Devices, Inc. All rights reserved. Trademarks
and
registered trademarks are the property of their respective
owners. D13336-0-8/17(B)