ANALOG DEVICES Octal 8-Bit CMOS D/A Converter FEATURES ee ee ee ee APPLICATIONS * Voltage Set Point Control * Digital Offset & Gain Adjustment * Microprocessor Controlled Calibration * General Purpose Trimming Adjustments FUNCTIONAL DIAGRAM +1/2 LSB Total Unadjusted Error 2us Settling Time Serial Data Input +Full-Scale Output Set by V,_-H and V,_,L Unipolar and Bipolar Operation TTL Input Compatible 20-Pin DIP or SOL Package Low Cost Yoo Vacrea Yaerh, oO 7 1 2 Daca 3 DECORED DACA PO Vou ADDRESS 4 a 8 axa a PO Your & L : 5 a Oy c .13 DUT LO Logic L pac D 0 Voy, 0 D ADORESS 4 4 c DATA ! A ' E a oa 6G $ 15 DACE =O Vout E oft] _seriat E rt SDI REGISTER A . Hey LF a, . our : 7 ~~ . PP Vout & ed 4 18 ; CLK OF DAC H SO Vous H I oo aK OY a i J 42 | 30 4 2 oO GND Ys CLR Yretlo rests REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed hy Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tai: 617/329-4700 Telex: 924491 DAC8800 GENERAL DESCRIPTION The DAC-8800 TrimDAC is designed to be a general purpose digitally controlled voltage adjustment device. The output valtage range can be independently set for each set of four D/A converters. fn addition, bath unipolar and bipolar output voltage ranges are easy to establish by external reference input high and law terminals. The digitally-programmed output valtages are ideal for op amp trimming, voltage-controlled amplifier gain setting and any general purpose trimming tasks. A three-wire serial digital interface loads the contents of eight internal DAC registers which establish the output valtage levels. An asynchronous Ciear (CLR) input places all DACs in a zero code output condition, very handy for system power-up. An internal regulator provides TTL input compatibility aver a wide range of V,,., supply voliages. Single supply operation is available by connecting V,.. to GND. ORDERING INFORMATION ' PACKAGE OPERATING CERDIP PLASTIC 590 TEMPERATURE 20-PIN 20-PIN 20-PIN RANGE DAC#800BR* - - 58C to 4125C DACS800FR DACSa00FP DACBSOOFS" 40C to +85C * For devices processed in total compliance to MIL-STD-883, add /8B3 alter part number. Consull factory for 883 data sheet. {1 Burn-in is available on commercial and industrial temperature range parts in CerDIP and plastic DIP packages. tt For availability and burn-in information on SQ package, contact your local sales office. PIN CONNECTIONS Vererhy Voce, [2] 20-PIN CERDIP Vour = {R-Suffix) ee te 20-PIN SOL Yourd La (5-Suffix) Yoo 20-PIN EPOXY DIP sora (P-Suffix) CLK [9 | cL [iol One Technology Way, P.G. Box 9106, Norwood, MA 02062-5106, U.S.A. Fax: 617/326-8703 Twx: 710/394-6577 Cable: ANALOG NORWOODMASSDAC8800 ELECTRICAL CHARACTERISTICS: (Note 1) Uniess otherwise nated, SINGLE SUPPLY: V,,, = +12V, Vs = OV. V__EH = +8V, Vag = OV; or DUAL SUPPLY: V,,, = 412V, Vo, =~5V, Voge = +2.5V, V__-L = 2.5V; F GRADE: -40C < T, = +85C; B GRADE: -55C s T, = +125C. DAC-8800 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY All specifications apply far DACs A, 8, C,D,E,F,G,H Resaiution N 4 - - Bits notea Errar TUE _ _ 21/2 LSB Differential Nonlinearity DNL _ _ #1 LSB (Note 3} Full Scale Error Gese - - 21/2 LSB Zero Code Exror Vase - - 21/2 LSB DAC Output Resistance Rout a 12 16 wa DAC Output Resistance Match ARoytRaur - 0.5 - % REFERENCE [INPUT . . Voltage Range (Note 5) ageH Pins 2 &19 pert - Mop- 4) v gert Pins 1& 20 Ves - Vege Input Resistance VerrH Digital Inputs = 55,, 2 3 - kQ Input Resistance Match ARG eFd/AQ_-H Digital Inputs = 55,, - 0.5 = % Reference Input c Digital Inputs All Zeros ~ 5a 75 oF Capacitance (Note 4) REF Digital Inputs All Ones - 75 100 DIGITAL INPUTS Logic High INH 24 - - v Logic Low INL - - 0.8 v Input Current Vw Vin = OV ar +5V - - +1 BA Input Capacitance (Note 4} Cn - 4 a pF Input Coding BINARY POWER SUPPLIES (Nate 6) Positive Supply Current lop Dual Supply eos - o2 on mA Negative Supply Current leg Oual Supply - 0.01 o2 mA Power Dissipation Poigs Dus Supply Operation - to oe mW Newelon ato PSR AV p =25% - 0.001 0.01 %1% DYNAMIC PERFORMANCE (Note 4) Vou, Selilling Time tg 21/2 LSB Error Band - 0.8 2 us Cwoeetalk Nate 7) CT Measured Between Adjacent DAC Outputs - a0 - nvs 2- REV. ADAC8800 ELECTRICAL CHARACTERISTICS: (Note 1) Unless otherwise noted, SINGLE SUPPLY: V,,, = +12V, Veq = OV, Var cH =45V, Vaggl = OV; or DUAL SUPPLY: V_5 =+12V, Veg =5V, Vag gH = +2.5V, Viel =-2.5V; F GRADE: 40C < T, < 485C: B GRADE: ~5C - ns Load Edge tc Next Clock i 50 _ _ ns Edge Time LDcK NOTES: 1. Tasting performed in SINGLE SUPPLY mode, except lop: leg. and PSRA 6. Digital Input voltages Vi Mie OF Mi yy for TTL condition; V,. =OV or +5 for which are tesled in DUAL SUPPLY mode. CMOS condition. DAC outputs unloaded. Poigg/8 calculated fram (1, 4x Yop! 2. Includes Full Scale Error, Relative Accuracy, and Zero Code Error. + (leg x Vg g)- a. Alldevices guaranteed monolonic over the full operating temperature range. 7. Measured ala yppin where an adjacant Vour pin is making a full-scale yolt 4. Guaranteed by desiga and not subject to production test. age change. 5. Vo) 4 volts is the maximum reference voltage for the above specifications. 8. See timing diagram for location af measured values. L Also Voerile Veer . DETAILED DAC-8800 BLOCK DIAGRAM Voo WreeHy Vaerhy Veer Hy Varrls ? 2 1 9 2 DAC A-D DAC E-H REGULATOR 4 45 FOR INTERNAL LOGIC 13 - Lo G {>eo ) cK DACA -, 4 REGISTER ; DAGA PS Yourd Tt c CLR 6. - LLLLLL Za OK ADDRESS } DA Pp GECODE REoieeA Daca to YourB D sOFLR re Youre a, } re? Vour? LLLLL LLL " : : Youre oe ns noe * e 16 Az Ay Bq D7 Dg Dy Dy Dy Dy Dg Dy 2 * mad YourF 11-817 SERIAL INPUT cK bacn 9 Yona a , spl Oy cK EGISTER ; DAG H PES Your 9 > GA cLKO 7 exo NEGATIVE SUPPLY qn Js 12 GND Ves O CLA (CLEAR) REV. ADAC8800 DICE CHARACTERISTICS yi Tt as LS WAT SS nel eS 1 i La ae == t I _ r = rT hen ee DIE SIZE 0.151 0.130 Inch, 19,830 sq. mils (3.8354 = 3.3033 mm, 12.664 sq. mm} Bm ek keke Seen ee N ae Pon Pw Pon a WAFER TEST LIMITS at Vpp = +12V, Ves = OV, VaerH = +5V, Veeck = OV; Ta = +25C unless otherwise nated. DAC-8800G PAAAMETER SYMBOL CONDITIONS LIMIT UNITS Total Unadjusted Error FUE tua LSB MAX Differential Nonlinearity BNL #1 LSB MAX Full Scala Error Grse 212 LSB MAX Zero Code Error Voce +1/2 LSB MAX DAC Qutput Resistance Reut . o ax Reference input Resistance RaerH Gigital Inputs = 55H 2 ka MIN Digital Inputs High VINH 24 V MIN Odgital Inputs Low VINE 0.8 VMAX Digital Input Current lin Vin = OY or +5V H1 pA MAX Positive Supply Current lap Vsg=-5 ouos Os mA MAX Negative Supply Current Iss Veg = -5V 0.2 mA MAX "Reoetion wee PSRA AVpp = 45% 0.01 %i% MAX NOTE: Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield lass, yield after packaging is not guaranteed for standard product dics. Consult factary to negotiate specifications based on dice lot qualiflcations through sample lot assembly and testing. REV. ADAC8800 ABSOLUTE MAXIMUM RATINGS (T, = +25C, unless otherwise noted} Vij BO Vig g wececcsceeeeenseesesstsenseicesesennesessesessenensencnsens OV, +20V Voy 10 GND ooo. ceeceseestesetenesensavassnecuecearcereeeeceeerteeees OV, +20V Vg 1OGND oo. cece teense tnestne sees coceesseneaecesneteneteseeeatans -20V, OV Digital Input Voitage to GND ............. GND ~ 0.3V, V,) + 0.3V Vag eeh to GND wetter eerste: Waeely Vip Voepl te GND .... wee Veg: Vacs Vous tO GND oer tna teeneatinensenieeecsneeteneeee Vorrl: VacrH Operating Temperature Range Military, DAC-8800BR ......... eee $5C to +125G Extended Industrial, DAC-8800FR,FP,FS ...-40C to +85C Maximum Junction Temperature (T, Max) 00.0... +150C Storage TEMPerature..... ees BOO to +150C Lead Temperature {Saldaring, 10 sec}... $900C Package Power Dissipation .....0000.0.0..c.e T, Max T,VOiy TABLE 1: PIN Function Description PACKAGE TYPE 8, a (Note 4) Ac UNITS 20-Pin Hermetic DIP (A) 76 11 cc 20-Pin Plastic DIP (P} 69 2? oC AN 20-Pin SO (S) 86 25 AC AY NOTE: 1. @, 15 specified for worst case mounting conditions, ie, ,, i8 specified for dvice in socket for CerDIP, and P-DIP packages; 8, 4 (8 Specified for device soldered to printed circuit board for SO package. CAUTION: 1. Donotapply voltages higher than Vapor fess than Ves potantial on any termi- nal. 2. The digital control inputs are zener-protected; however, permanent damage May occur on unprotected units from high-energy electrostatic fields. Keep units in conductive foam at all times until ready to use, 3. Do notinsert this device into powered sockets; remove power before insertion or remeaval. 4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to davice. PIN MNEMONIC DESCRIPTION 1 Verkhy External DAC voltage reference input shared by DAC A,B,C, D. Vag, determines the lowest negative DAC output voltage. Vagpl, must be equal to or more positive than Vag: 2 VoreH, External DAC voltage reference input shared by DAC A, B, , D. Voge, determines the highast positive DAC output voltage. 3 Vour# DAC A Output 4 VayrB DAC B Output Output voltage determinad by external V._-H, and V_--L.. 5 Voure DAC C Output ut voltag y REF} REP 6 Vout DAC D Output ? Vop Positive supply, allowable input voltage range +4.5V to +16. 8 S01 Serial Data Input 9 CLK Serial Clock Input, positive edge triggered TTL Input Compatible 10 CLK Clock Enable or Serial Clock Input, negative edge triggered 11 GND Ground 12 cLR Clear Input (Active Low), Asynchronous TTL compatible input that resets all DAC registers to zero code. 13 LD Load DAC Register Strobe, TTL compatible input that transfers data bits from serial input register into the decoded DAC register, See Table 2. 14 Veg Negative Supply, allowable input voltage range OV to -12V. 15 VourE DAC E Output 16 Vourk DAG F Output Output voltage determined by external V,_-H, and ,_-L,. 7 Vey DAC G Output P REF 2 REF? 18 VoutH DAC H Qutpur 19 VaerHe External DAC voltage reference inpul shared by DAC E, F, G, H. Veep, determines the highest positive DAC output voltage. 20 Vacebs Extarnal DAC voltage reference input shared by DAC E, F, G, H. Vaerle, determines the lowest negative DAG output voltage. Vagpbs must be equal to or more positive than Vv, 5 REV. ADAC8800 TERE AERA AULA s! Lr DAC REGISTER LOAGED a5v Your \ ov DETAIL SERIAL DATA INPUT TIMING (CLK = 0) CLEAR OPERATION 1 Sol (DATA IN) X A GF Dy 4 x ten ths *p fon 1 CLK av 41/2 LS ERROA BAND Li L3H ERROR BAAD CLK INPUT {PIN 10) TIMIMG IS EXACTLY INVERTED FROM CLK WPT {PIN 9) FIGU RE1: Timing Diagrams TABLE 2: Serial input Decode Tabla LAST f-FIRST LSB MSB] LSB MSE Dy B, D, Dy DB, Bs BD, DB, Ay A, A, v v MSB LSS L fm) A, | A, | A, | DAC UPDATED MSB Ls DAC OUTPUT YOLTAGE oc 8 DACA Dy | Dg | Bs | By | Ds | D2] Dy | Da | Ko VpeeH -VaerL} oo 1 DAC B G 1 Q DAG G ob G@ O@ 6 68 0 48 Vaeect 0.14 DAC D o 89 0 O 6 08 8 1 (1/256) x K+ Vpgeel 1 0 2 DACE $ 1 ao f DAG F 1 4 a DACG ao. 86106061 1 1 4 4 {127/256} x K + Viel 4 44 DAC H 1 oo Oo 9 0 O | (128/258) % K+ Vaerb + O@ O B @ DOD 8 1 | (129/256) % K+ Veeck 5 a 1 ot fF 4 4 4 1 14 | (258256) x K+ Vee el TABLE 3: Logic Central Input Truth Tabla CLK CLK INPUT SHIFT REGISTER OPERATON t L Shift Data H + Shift Data L x No Operation x H No Operation -6- REV. ADAC8800 TYPICAL PERFORMANCE CHARACTERISTICS TOTAL UNADJUSTED ERROR vs DIGITAL INPUT CODE SUPPLY CURRENT vs TEMPERATURE 2.0 Vpp a +124 nie Vinn = 2.4 $ ' 18 5 E i 12 woe Be SUPE osee E tw Z +e ae Z 7 ; a a4 ae DACS E, Fg, M SUPERIMPOSED o ba 128 194 256 oO 500 =25 a 25 50 TS 10600 (425 DIGITALINPLIT GODE (DECIMAL) TEMPERATURE (C) DAC OUTPUT SETTLING TIME EXPANDED DAC OUTPUT POSITIVE & NEGATIVE SETTLING TIME POSITIVE TRANSITIONS TRANSITION ae _ i fl ; j j 7 rst UPPER TRACE: 1, ) INPUT (5/DIV) LOWER TRACE: Vout (2V/DIV) CONDITIONS: = ,,,= +12, Veer, = +5, Vaeply =O. Ven = OV, REF 14 RL = 1M, or = 3.4pF DAC OUTPUT CHANNEL-TO- CHANNEL CROSSTALK BOTH TRANSITIONS ae UPPER TRACE: V,,,,4 0 TO +5V CHANGE LOWER TRACE: V,,,,,8 (1V/DIV) CONDITIONS: V4, = +12V, VaegH, = +5, Vaerey = OV. Veg = OV, A, = 14Q, C, = 3.4pF REV. A UPPER TRAGE: t_,, INPUT (5v/DIV) LOWER TRACE: V,,,,4 (1/DIV) CONDITIONS: V,,,,= +12, Vag eH, = +5, Vaggly = OV. Veg = OV, A, = 1MQ, C, = 3.4pF DOD EXPANDED DAC OUTPUT CHANNEL-TO-CHANNEL CROSS- TALK NEGATIVE TRANSITION ee CONDITIONS: V,,,,= +f2V, Vac pH, = +8V, Vaerty = OV, Veg = OV, R, = 1M2,C, = 3.4pF POWER SUPPLY REJECTION RATIO (dB) POWER SUPPLY REJECTION RATIO vs FREQUENCY OTs me ve Sey 100 i 5 avons Wop MS BO fs ae ae eo T DI; 40 20 | o 1 100 dk 10k 100k FREQUENCY jHz} EXPANDED DAC OUTPUT SETTLING TIME NEGATIVE TRANSITION Eu aS ce UPPER TRACE: tio INPUT (5/DIV} LOWER TRACE: Your avon CONDITIONS: Vy,= +124, Vaegh, = +5, Veer; = OV, Veg = OV, R, = 1MQ, G, = 3.4pF EXPANDED DAC OUTPUT CHANNEL-TO-CHANNEL CROSS- TALK POSITIVE TRANSITION ee. , i: a UPPER TRACE: V,,,,40TO +5 CHANGE LOWER TRACE: V,,,,8 (toomv/DIV) CONDITIONS: V,,,)= +12V, VaegH, = +5, Vagerly = OV. Vag = OV, RL = 1Kii, c = 3.4pFDAC8800 CIRCUIT OPERATION The DAC-8800 provides a programmable voltage output adjust- ment capability. Changing the pragrammed autput voltage of each DAC is accomplished by clocking in an 11-bit serial data word into pin SDI (Serial Data Input}. The format of this data word is three address bits, MSB first, followed by 8 data bits, MSB first. Table 2 provides the serial input decode table fordata loading. DAC outputs can be changed one at a time in random sequence. The fast serial-data clocking of 6.4MHz makes it possible ta load all 8 DACs in as little time as 14 microseconds. The exact timing requirements are provided in Figure 4. Aclear (CLR) input pin allows the circuit to be pawered-up inthe all zero state of a systam reset pulse connected to CLR can asynchronausly clear all data registers. 4-CH aA VageH G-__-4 Vout" Four CONETANT R iNDEPENDENT OF DIGITAL D INPUT COCE 7 Lf q oe | ,|iLT REGISTER a ~ A re L4 2R +__ LI 2A Vaerl O44 DB our = 25g * MaceH -Vaerl] + Vaerl FIGURE 2: DAC-8800 TrimDAC Equivalent DAC Circuit The output voltage range is determined by the external input voltages applied to V,_-H and VL. See Figure 2 for a simpli- fied equivalent DAC circuit. If a negative supply is used on V.. then V.--L may be set negative resulting in a programmable bipolar output voltage swing. The actual output voltaga, Vout depends on V,,,.-H and Voepl as follows: Voy7(D) = Dx (Vpe pH Vee ph/256 + Vaget where Dis a whela number binary digital input ward loaded into the DAC register. Far example, when V,--H =+5V and VL = OV unipolar output aperation results with the following binary digital inputs: D VourtD) VagsH = +5-00V; Vocel = OV 285 408V Full-Scale 128 2.50 Half-Scale 1 0,02V 1 LSB 6 0.06V Zero-Scale also generated When CLR Input Activated Bipolar output operation is achieved when V__-H = +2.5V and Vacpl =2.5V, also note V., must be equal to or more negative than V.pfl. Veg = SV is a good choice for this example. Tha following example lists the actual bipolar output voltages pro- duced by the binary digital input which would now be considered offset-binary coded: D VoutD) Vier = +2.50V; Veet =-2.50V 255 2.48V Positive Full-Scale 129 O0.C2Vv Positive 1 LSB 128 0.00 Bipolar Zero-Scale 127 ~0.02V Negative 1 LSB 0 2.50V Negative Full-Scale REFERENCE INPUTS (V,--H,, Voce, Veer hes Vaertol The external valtages connected to the V___ input pins deter- mine the programmable output voltage ranges of the two sets of four DACs in the DAC-8800. Specifically, V,_-H, and V,--L, are connected to DACs, A, B, C, D, and V,,_,H, and V,--L, are connected to DACs E, F, G, H. Inspection of the DAC-8800 equivalent DAC circuit (Figure 2} shows the external V,--H and V,_-L inputs connected to the intarnal DAC switches. During updating, the DAC switches pro- duce transient current fiowing from V,,--Hto Vi, -L. Itis recom- mended to place 0.01,F bypass capacitors across the V,_-H and V._-t inputs to minimize the voltage transients. REV. ADAC8800 Awide range of external voltage references can be used subject to the reference input valtage range boundary conditions. First V,erH should always be more positive than V,,-1. DC voltages are recommended. V__-L can be equal to the negative power supply V... This feature results in single supply aperation when Ve, is al ground. V__--H should not be closer than four volts to Von: This is due to the DAC-8800 NMOS only DAC switches which will no longer operate properly if V.--H is claser to V_, than four velts. Total unadjusted error degrades when (V,,, Var) is less than four valts as shown in Figure 3. TOTAL UNADJUSTED ERROR VS (Vop VaerH) Ta = +256 cov TOTAL UNADJUSTED ERROR (LSB) 9 4 4 You Veerd (YOLTS) 12 FIGURES: Effect on TUE Operating Beyond Von Veet > 4V Limit RECOMMENDED OPERATING POWER SUPPLY VOLTAGE RANGES Although the DAC-8800 is thoroughly specifiad for operation with V,,=+12V and V.. =O0Vor-5Y, it will still function with the fallawing recommended baundary canditians: (Yop - Veg) < 18V 45V Vip < 16V OV > Veg> -12V In ail cases the referance voltage boundary conditions still ap- ply. The boundary conditions described hera make it possible to use DAC-8800 with a wide variety of readily availabie supply voltages. Same choices include, but are nat limited ta: Von! Vag = +15 V/OV; +12V/0V; +12V/-5V; +5V/-5V; +5VH12V REV. A ~9- DAC OUTPUTS (V,,,,, A, B, C, D, E, F, G, H} The eight D/A converter voltage outputs have a constant output resistance independent af digital input cade. The distribution of Royr frem DAC to DAC within the DAC-8800 typically matches by 0.5%. Device to device R,,,,, matching is process-lot ta prac- ass-lot dependent having a +20% variation. The change in Rour With temperature is very small as a result of PMIs low temperature coefficient SiCr thin-film resistor process. The nominal DAC output capacitance measuras threa picofar- ads and has little variation with temperature. One aspect of the nominal 12.542 DAC output resistance is channel-to-channel crosstalk. Under a werst case condition of adjacent DAC outputs when DAC A makes a five volt output voltage change DAC B exhibits a 300mYV voltage transient. See photograph in typical characteristics section of data sheet. The channel-te-channel crosstalk is due te the G.15pF inter-pin package capacitance. A FET probe with 3.4pF input capaci- tance was used to measure the DAC output channel-to-channel! crosstalk characteristics shown. In voltage transient sensitive applications, minimization of crosstalk can be accomplished by placing ground traces between adjacent DAG oviput pins. DAC output bypass capacitors will also minimize voltage transients. Output sattling time has a dominant pole rasponse as the photo- graph in the typical characteristics section shows. The output settling time characteristic consists of an 80 nanasecond propa- gation delay fallowed by a singla RO decay waveform deter- mined by the nominal R,,,,, of 12.52 times C,,,, plus which includes the oscilloscope probe. Thea digital feedthrough from the serial data inputs (CLK, and $BI) to the DAG outputs measures lass than 20mV. LoaD DIGITAL INTERFACING The DAC-8890 contains a siandard three-wire serial input con- trotinterface. The three inputs are clack (CLK), load (LD), and serial data input (SDI). A CLK input pin is available for negative edge triggered data loading. The edge sensitive clock input pin requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families wark well. If mechanical switches are used far product evaluation they should be debounced by a flip-fiop or other suitable means. The logic control input truth table (Table 3} defines operation of the serial data input register. The GLK input is used ta place data in the serial data input reg- ister. The unused clock input (CLK or CLK) shauld be tied to the active state (CLK = 1 or CLK =O for active). The load strobe (LD) which must follow the eleventh activa CLK edge transfers theDAC8&800 LOAD STAOBE SEALAL DATA x x - x x DAC-3Bo0 FOF SDI a x a _- FIGURE 4: Three-Wire Serial interface Connections 40 > 1 cs, cs, }- Stns * 54 [sons] ae SERIAL DATA xX x x x +) al a Ll, Ff / a TA LOAD STAOBE DEGORE FIGURE 5a: Decoding Multiple DAC-8800s data from the serial data input register ta the DAC register de- coded from the first three address bits clocked into the input reg- ister. Any extra CLK edges after the eleventh edge looses the first bits shifted in. Sae Table 2 for a complete description. See Figure 4 for an example using the CLK input pin to clock data inta the SDI. ~10- The unused clock input of Figure 4 can be used to provide achip selact (CS) feature for applications using mare than one DAC- &800. Figure 5a shows the proper connaction and timing of the CLK inputs which assures that the CLK acting as a chip select (CS) is taken to the active low state selecting the desired DAC- 8800. REV. ADAC8800 Another method of decoding multiple DAC-8800s is shown in Figure Sb. Here all the DAC serial input registers receive the same input data; however, only ane of DAC's LD input is acti- vated to transfer its serial input register contents inta the desti- nation DAC register. In this circuit the LD timing generated by the address decoder should follow the DAC-8800 standard tim- ing requirements. Note the address decoder should not be acti- vated by its WH input while the coded address inputs are chang- ing. Lo pac CLK BAO clock > SDI n Data O Lo DAG o aporess F CLK Ba00 DECOGE CODED oo spl #2 ADDRESS oH EN Lb OAC CLK = BBO SDI "a wa O_ LD DAG SLK 4800 spt iad FIGURE Sb: Decoding Multiple DAC-8800s Lising the LD input Pin APPLICATIONS DIGITALLY PROGRAMMABLE AUDIO AMPLIFIER The DAC-8800 is well suited to digitally contral the gain or at- tenuation settings of eight voltage controlled amplifiers (VCAs}. In professional audio mixing consoles, music synthesizers and other audio processor's VCAs, such as the SSM-2014, adjust audio channel gain and attenuation from front panel potenti- ometers. The VCA provides a clean gain transition cantrol of audio level when the slew rate of the analog input control volt- age (V,} is properly chosen. Taking advantage of the 12.5kQ nominal output resistance af the DAC-8800 it is very aasy to control the slew rate of Vout by appropriate selection of Cour Figure 6 shows one channel of a digitally programmable audio amplifier. The reference high (V,,_-H) and reference low (V,--L) input voltages of the DAG-8800 provide a digitally programmable output voltage of 1.2V to +1.2V which is connected to the con- tral valtage (V,.) input terminal of the SSM-2014 VCA. The gain ofthe SSM-2014 is quaranteed to change from 15dB to + 15dB for 1.2 to -1.2V input V,, voltage. AC, of O.1nF provides a comtrol voltage transition time of 1.2ms which generates a click free change in audio channel gain. REV. A OV AUDIG OUTPUT Vier Yoo F 70 DAC BOT 124 5 e5 41.2 +1.24 G4 Cour TL WIyF Vorb Vag GAIN (dB) va - 12 a a1? Ye (VOLTS) FIGURE 6: Digitally Programmable Amplifier BUFFERING THE DAC-8800 OUTPUT External op amps can be used to buffer the output of tha DAC- 8800's nominal 12.5kQ qutput resistance. In Figure 7 a variety of possibilities are shown. The quad low power OP-420 is used as asimp'e buffer to reduce the output resistance of DACA. The OP-420 was chosen for its wide oparating supply range, both sing!e and dual, low power consumption, and low cost. The next two DACs, B and C, are configured in a summing ar- rangement where DAC C provides the course output voltage setting and DAC B can be used for fine adjustment. The inser- tion of R, in series with DAC B attenuates its contribution to the voltage sum node at the DAC C output. DAC D in Figure 7 is in a noninverting gain of two configuration increasing the available qutput swing to 10V. Appropriate choice of external op amp gain can achieve output voltage swings beyond the range of the DAC-8800 if the external op amp power supply voltages are sufficiently high. In addition, the op amp feedback network termination could be a bias valtage which would provide an offset to the output signal swing. SETTING COMPARATOR TRIP POINTS The DAC-8800 is ideal to provide setpcints for voltage input comparators. In Figure 8 the very low power CMP-404 detects whether input voltage (V,,) is higher or lower than the pro- grammed limit values providing TTL compatible output signals. The compaciness of the DAC-8800 makes it ideal for high den- sity testing applications found in pin head electronics.DAC8800 +120 T Yoo VaerH; 2 Fo Ya Rout Vout YL Vreely 1 av R eH OUT Vour ee ME a Four Your eo / Bac-ss00 Ll] vy Rout Your? Is yw YL 14 / Ves Ww GNO A, = 100KQ, Fy = 1022 J DIGITAL INTERFACING OMITTED FOR CLARITY. AAA SIMPLE BUFFER P O TO s SUMMER CIRCUIT WITH FINE TRIM ADJUSTMENT pio ov TOEY INCREASE GUTPLT SWING pO OV TO WY FIGURE 7: Suffering the DAC-8800 Output +12 M +12 i Yoo Yoo Vruzty o + DACA a + Vaert ao! / pac-se00 CMP-404 + \ paca 14 - pacc / 5 + 14] Veg - HIGH LIMIT Low LIMIT VARIABLE LIMIT FIGURE &: Setting the Comparator Trip Points 1?2- REV. ADAC8800 CURRENT SUMMING OUTPUT OPERATIONS Since the DAC-8800 has a constant output resistance regard- less of digital input code, it can be used in a current summing application. Figure 9 depicts the DAC output connected to the inverting input of an OP-20 law power consumpticn ap amp. An external feedback resistor sets the output signal swing accord- ing to the formula given. The gain accuracy af this circuit has a wide variation due to the 30% output tolerance of the DAC-8800 Royz Specification. A second DAC in the DAC-8800 could be used with an external resistor summed inte the OP-20 current summing node to digitally adjust the full-scale swing. OPTICALLY ISOLATED TWO-WIRE INTERFACE Tweo-wire signal interfacing is often found in process control applicatians where electrical isolation of hazardous environ- ments and minimization of wiring is necessary, Isolation trans- formers or optocouplars provide the high valtage isolation. Normally the DAC-8800 requires a three-wire interface to up- date the DAC contents. One technique which translates a two- wire interface into the three-wire signal contro! required by the +54 Or -R oO - Re. . 0%: RE { wee tov) sv WHERE 0 = DECIMAL CODE INPUT SETWEEN 0 AND 255 -oO4 av FIGURE 9: Current Summing Output Operation DAG-8800 is shown in Figure 10. Asingle package CMOS-lagic dual-retriggerable one-shot MC14538 provides the salution. At rest the optaccuplers are both OFF allowing the pull-up resis- tors to sit at lagic high. No undefined transients should occur on the control input line V,, to avaid inadvertently clocking incorrect data into the DAC-8800 serial input register. When it is time ta update one of tha DAC-8800 DAGs, the CONTROL line will go HIGH VOLTAGE __ ISOLATION MC 14538 3-WIRE INTERFACE SIGNAL 1 a, | 0 Pst uA si 1 AN - u 1 o (CLK) wean XE KAKA KENEX FIGURE 10: fsolated Two-Wire Signal interface for Serial input DAC REV. ADAC8800 low, triggering the first one-shot (Q,). At this time valid data should alsa be applied tothe DATA input optocoupler. Sufficiant time must be allowed before the contro! (V,) input returns to logic high to make sure the DAC-8800 input data is stabilized. When V,. changes to logic high, the first DATA bit shifts into the DAC-8800 serial data input register. The time constant of the first one-shot established by R, and , should be at least twice as long as the basic CONTROL input clock period. This will prevent the Q, output from returning to the high state. The next control input negative edge retriggars tha first one-shot and sets up the DAC-8800 clock for the next DATAbit. Alleleven positive clock edges will fill the DAC-8800 serial input register and each negative clock edge will retrigger the first one shot. As soon as the CONTROL line returns ie the passive state, the firstone shot will time out, triggering the second one shot (Q,), which will pro- duce the required load LD pulse tor the DAG-8800 ta transfer its serial input register contents to the internal DAG register com- pleting the DAC update. The R,C, andRC,, times need to be designed based on the system's CONTAOL-input clock rate, The optocoupler clocking rate must also be considered in set- ling the system clack rate. 14- BURN-IN CIRCUIT Ma Vrcrl: Yaerle a 2 VaceHs YacrHs P2# Your Your [2 Your Yours - Your YourF - +10 > "oo Wes CLK CLA Pe 190k GND REV. A-15-L6/eL-S-LLglo ST NI OF1.NIdd -16-