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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

SLASE23E –JANUARY 2015–REVISED AUGUST 2018

MSP430FR697x(1), MSP430FR687x(1), MSP430FR692x(1), MSP430FR682x(1)

Mixed‑‑Signal Microcontrollers

1 Device Overview

1.1 Features

(1) The RTC is clocked by a 3.7-pF crystal.

• Embedded Microcontroller

– 16-Bit RISC Architecture up to 16-MHz Clock

– Wide Supply Voltage Range From 3.6 V Down

to 1.8 V (Minimum Supply Voltage is Restricted

by SVS Levels, See the SVS Specifications)

• Optimized Ultra-Low-Power Modes

– Active Mode: Approximately 100 µA/MHz

– Standby (LPM3 With VLO): 0.4 µA (Typical)

– Real-Time Clock (RTC) (LPM3.5):

0.35 µA (Typical) (1)

– Shutdown (LPM4.5): 0.04 µA (Typical)

• Ultra-Low-Power Ferroelectric RAM (FRAM)

– Up to 64KB of Nonvolatile Memory

– Ultra-Low-Power Writes

– Fast Write at 125 ns per Word (64KB in 4 ms)

– Unified Memory = Program, Data, and Storage

in One Single Space

– 1015 Write Cycle Endurance

– Radiation Resistant and Nonmagnetic

• Intelligent Digital Peripherals

– 32-Bit Hardware Multiplier (MPY)

– Three-Channel Internal Direct Memory Access

(DMA)

– RTC With Calendar and Alarm Functions

– Five 16-Bit Timers With up to Seven

Capture/Compare Registers

– 16-Bit and 32-Bit Cyclic Redundancy Checker

(CRC16, CRC32)

• High-Performance Analog

– Up to 8-Channel Analog Comparator

– 12-Bit Analog-to-Digital Converter (ADC) With

Internal Reference and Sample-and-Hold and

up to 8 External Input Channels

– Integrated 116-Segment LCD Driver With

Contrast Control

• Code Security and Encryption

– 128-Bit or 256-Bit AES Security Encryption and

Decryption Coprocessor (MSP430FR69xx(1)

Only)

– True Random Number Seed for Random

Number Generation Algorithm

– Lockable Memory Segments for IP

Encapsulation and Secure Storage

• Multifunction Input/Output Ports

– All I/O Pins Support Capacitive Touch Capability

Without Need for External Components

– Accessible Bit-, Byte- and Word-Wise (in Pairs)

– Edge-Selectable Wakeup From LPM on Ports

P1 to P4

– Programmable Pullup and Pulldown on All Ports

• Enhanced Serial Communication

– eUSCI_A0 and eUSCI_A1 Support:

– UART With Automatic Baud-Rate Detection

– IrDA Encode and Decode

– SPI at Rates up to 10 Mbps

– eUSCI_B0 and eUSCI_B1 Support:

– I2C With Multiple-Slave Addressing

– SPI at Rates up to 10 Mbps

• Flexible Clock System

– Fixed-Frequency DCO With 10 Selectable

Factory-Trimmed Frequencies

– Low-Power Low-Frequency Internal Clock

Source (VLO)

– 32-kHz Crystals (LFXT)

– High-Frequency Crystals (HFXT)

• Development Tools and Software

– Free Professional Development Environments

With EnergyTrace++™ Technology for Power

Profiling and Debugging

– Microcontroller Development Boards Available

• Family Members

–Device Comparison Summarizes the Available

Variants and Packages

• For Complete Module Descriptions, See the

MSP430FR58xx, MSP430FR59xx, and

MSP430FR6xx Family User's Guide

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

SLASE23E –JANUARY 2015–REVISED AUGUST 2018

www.ti.com

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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721

MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

1.2 Applications

• Heat Cost Allocators

• Utility Meters – Electricity, Water, and Gas

• Thermostats

• Portable Medical Equipment

• Sensor Management

• Weigh Scales

1.3 Description

This ultra-low-power MSP430FRxx FRAM microcontroller family consists of several devices featuring

embedded nonvolatile FRAM, a 16-bit CPU, and different sets of peripherals targeted for various

applications. The architecture, FRAM, and peripherals, combined with seven low-power modes, are

optimized to achieve extended battery life in portable and wireless sensing applications. FRAM is a new

nonvolatile memory that combines the speed, flexibility, and endurance of SRAM with the stability and

reliability of flash, all at lower total power consumption.

(1) For the most current part, package, and ordering information for all available devices, see the Package

Option Addendum in Section 9, or see the TI website at www.ti.com.

(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the

Mechanical Data in Section 9.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE(2)

MSP430FR6972IPMR LQFP (64) 10 mm × 10 mm

MSP430FR6972IRGC VQFN (64) 9 mm × 9 mm

MSP430FR6922IG56 TSSOP (56) 6.1 mm × 14 mm

EEM

(S: 3+1)

Comp_E

(up to 16

inputs)

FRAM

64KB

32KB

RAM

2KB

Power

Mgmt

LDO

SVS

Brownout

SMCLK

ACLK

MDB

MAB

HFXOUT

HFXIN

Spy-Bi-

Wire

CRC32

CRC-32-

ISO-3309

CRC16

CRC-16-

CCITT

Bus

Control

Logic

MAB

MDB

MAB

MDB

MCLK

MPY32

AES256

Security

En-/De-

cryption

(128/256)

ADC12_B

(up to 16

std. inputs,

up to 8

diff. inputs)

Clock

System

CPUXV2

incl. 16

Registers

JTAG

Interface

DMA

Controller

3Channel

REF_A

Voltage

Reference

MPU

IP Encap

TB0

Timer_B

7 CC

Registers

(int./ext.)

TA0

Timer_A

3 CC

Registers

(int./ext.)

TA1

Timer_A

3 CC

Registers

(int./ext.)

RTC_C

Calendar

and

Counter

Mode

LCD_C

(up to

116 seg;

static,

2 to 4 mux)

eUSCI_A0

eUSCI_A1

(UART,

IrDA,

SPI)

eUSCI_B0

eUSCI_B1

(I C,

SPI)

LPM3.5 Domain

P1.x,P2.x

I/O Port

P5, P6

2x8 I/Os

1x16 I/Os

I/O Port

1x8 I/Os

I/O Port

1x8 I/Os

I/O Port

1x8 I/Os

I/O Ports

P3, P4

2x8 I/Os

1x16 I/Os

I/O Ports

P1, P2

2x8 I/Os

1x16 I/Os

P9.x

up to

1x8

PJ.x

Watchdog

TA2

Timer_A

2 CC

Registers

(int. only)

TA 3

Timer_A

5 CC

Registers

Capacitive Touch IO 0, Capacitive Touch IO 1

P7.x

up to

1x8

up to

1x8

up to

2x8

up to

2x8

up to

2x8

P3.x,P4.x P5.x,P6.x

LFXOUT,

LFXIN,

Tiny RAM

26B

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

www.ti.com

SLASE23E –JANUARY 2015–REVISED AUGUST 2018

Submit Documentation Feedback

Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721

MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram.

NOTE: AES256 is not implemented in the MSP430FR682x, MSP430FR687x, MSP430FR682x1, and MSP430FR687x1

devices.

NOTE: HFXIN and HFOUT are not implemented in the MSP430FR692x, MSP430FR682x, MSP430FR692x1, and

MSP430FR682x1 devices.

Figure 1-1. Functional Block Diagram

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

SLASE23E –JANUARY 2015–REVISED AUGUST 2018

www.ti.com

Submit Documentation Feedback

Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721

MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

Table of Contents

1 Device Overview ......................................... 1

1.1 Features .............................................. 1

1.2 Applications........................................... 2

1.3 Description............................................ 2

1.4 Functional Block Diagram ............................ 3

2 Revision History ......................................... 5

3 Device Comparison ..................................... 6

3.1 Related Products ..................................... 8

4 Terminal Configuration and Functions.............. 9

4.1 Pin Diagrams ......................................... 9

4.2 Pin Attributes........................................ 12

4.3 Signal Descriptions.................................. 18

4.4 Pin Multiplexing ..................................... 26

4.5 Buffer Type.......................................... 26

4.6 Connection of Unused Pins......................... 26

5 Specifications........................................... 27

5.1 Absolute Maximum Ratings......................... 27

5.2 ESD Ratings ........................................ 27

5.3 Recommended Operating Conditions............... 27

5.4 Active Mode Supply Current Into VCC Excluding

External Current .................................... 28

5.5 Typical Characteristics - Active Mode Supply

Currents ............................................. 29

5.6 Low-Power Mode (LPM0, LPM1) Supply Currents

Into VCC Excluding External Current................ 29

5.7 Low-Power Mode LPM2, LPM3, LPM4 Supply

Currents (Into VCC) Excluding External Current .... 30

5.8 Low-Power Mode With LCD Supply Currents (Into

VCC) Excluding External Current.................... 32

5.9 Low-Power Mode LPMx.5 Supply Currents (Into

VCC) Excluding External Current.................... 33

5.10 Typical Characteristics, Low-Power Mode Supply

Currents ............................................. 34

5.11 Typical Characteristics, Current Consumption per

Module .............................................. 35

5.12 Thermal Resistance Characteristics ................ 35

5.13 Timing and Switching Characteristics............... 36

6 Detailed Description ................................... 64

6.1 Overview ............................................ 64

6.2 CPU ................................................. 64

6.3 Operating Modes.................................... 65

6.4 Interrupt Vector Table and Signatures.............. 67

6.5 Bootloader (BSL).................................... 70

6.6 JTAG Operation..................................... 70

6.7 FRAM................................................ 71

6.8 RAM ................................................. 71

6.9 Tiny RAM............................................ 71

6.10 Memory Protection Unit (MPU) Including IP

Encapsulation ....................................... 71

6.11 Peripherals .......................................... 72

6.12 Device Descriptors (TLV).......................... 109

6.13 Memory ............................................ 112

6.14 Identification........................................ 128

7 Applications, Implementation, and Layout...... 129

7.1 Device Connection and Layout Fundamentals .... 129

7.2 Peripheral- and Interface-Specific Design

Information ......................................... 133

8 Device and Documentation Support.............. 136

8.1 Getting Started and Next Steps ................... 136

8.2 Device Nomenclature.............................. 136

8.3 Tools and Software ................................ 137

8.4 Documentation Support............................ 139

8.5 Related Links ...................................... 140

8.6 Community Resources............................. 140

8.7 Trademarks ........................................ 141

8.8 Electrostatic Discharge Caution ................... 141

8.9 Export Control Notice.............................. 141

8.10 Glossary............................................ 141

9 Mechanical, Packaging, and Orderable

Information............................................. 142

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

www.ti.com

SLASE23E –JANUARY 2015–REVISED AUGUST 2018

Submit Documentation Feedback

Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721

MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from January 25, 2017 to August 30, 2018 Page

• Updated Section 3.1,Related Products ........................................................................................... 8

• Added note (1) to Table 5-2,SVS................................................................................................. 36

• Changed capacitor value from 4.7 µF to 470 nF in Figure 7-5,ADC12_B Grounding and Noise Considerations ... 133

• Changed capacitor value from 4.7 µF to 470 nF in the last paragraph of Section 7.2.1.2,Design Requirements .. 134

• Updated text and figure in Section 8.2,Device Nomenclature .............................................................. 136

Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721

MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

SLASE23E –JANUARY 2015–REVISED AUGUST 2018

www.ti.com

3 Device Comparison

Table 3-1 and Table 3-2 summarize the available family members.

(1) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a

number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output

generators, respectively.

(2) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a

number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output

generators, respectively.

(3) eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.

(4) eUSCI_B supports I2C with multiple slave addresses and SPI.

(5) Timer_A TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.

(6) Timer_A TA2 provides only internal capture/compare inputs and only internal PWM outputs (if any).

(7) Timer_A TA3 provides only internal capture/compare inputs and only internal PWM outputs (if any) for FR692x(1) and FR682x(1) with RGC and PM packages. For FR692x(1) and

FR682x(1) with DGG package and all other devices, Timer_A TA3 provides internal, external capture/compare inputs and internal, external PWM outputs (if any).

Table 3-1. Device Comparison – Family Members With UART BSL

DEVICE FRAM

(KB) SRAM

(KB) CLOCK

SYSTEM Timer_A(1) Timer_B(2) eUSCI AES ADC12_B LCD_C I/O PACKAGE

A(3) B(4)

MSP430FR6972 64 2 DCO

HFXT

LFXT

3, 3(5)

2, 5 (6)(7) 7 2 2 yes 8 ext 112 seg 51 64 PM

64 RGC

MSP430FR6872 64 2 DCO

HFXT

LFXT

3, 3(5)

2, 5 (6)(7) 7 2 2 no 8 ext 112 seg 51 64 PM

64 RGC

MSP430FR6970 32 2 DCO

HFXT

LFXT

3, 3(5)

2, 5 (6)(7) 7 2 2 yes 8 ext 112 seg 51 64 PM

64 RGC

MSP430FR6870 32 2 DCO

HFXT

LFXT

3, 3(5)

2, 5 (6)(7) 7 2 2 no 8 ext 112 seg 51 64 PM

64 RGC

MSP430FR6922 64 2 DCO

LFXT 3, 3(5)

2, 5 (6)(7) 7 2 2 yes 8 ext 116 seg

100 seg

(DGG) 52

46 (DGG) 64 PM

64 RGC

56 DGG

MSP430FR6822 64 2 DCO

LFXT 3, 3(5)

2, 5 (6)(7) 7 2 2 no 8 ext 116 seg

100 seg

(DGG) 52

46 (DGG) 64 PM

64 RGC

56 DGG

MSP430FR6920 32 2 DCO

LFXT 3, 3(5)

2, 5 (6)(7) 7 2 2 yes 8 ext 116 seg

100 seg

(DGG) 52

46 (DGG) 64 PM

64 RGC

56 DGG

MSP430FR6820 32 2 DCO

LFXT 3, 3(5)

2, 5 (6)(7) 7 2 2 no 8 ext 116 seg

100 seg

(DGG) 52

46 (DGG) 64 PM

64 RGC

56 DGG

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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721

MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

www.ti.com

SLASE23E –JANUARY 2015–REVISED AUGUST 2018

(1) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a

number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output

generators, respectively.

(2) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a

number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output

generators, respectively.

(3) eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.

(4) eUSCI_B supports I2C with multiple slave addresses and SPI.

(5) Timer_A TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.

(6) Timer_A TA2 provides only internal capture/compare inputs and only internal PWM outputs (if any).

(7) Timer_A TA3 provides only internal capture/compare inputs and only internal PWM outputs (if any) for FR692x(1) and FR682x(1) with RGC and PM packages. For FR692x(1) and

FR682x(1) with DGG package and all other devices, Timer_A TA3 provides internal, external capture/compare inputs and internal, external PWM outputs (if any).

Table 3-2. Device Comparison – Family Members With I2C BSL

DEVICE FRAM

(KB) SRAM

(KB) CLOCK

SYSTEM Timer_A(1) Timer_B(2) eUSCI AES ADC12_B LCD_C I/O PACKAGE

A(3) B(4)

MSP430FR69721 64 2 DCO

HFXT

LFXT

3, 3(5)

2, 5 (6)(7) 7 2 2 yes 8 ext 112 seg 51 64 PM

64 RGC

MSP430FR68721 64 2 DCO

HFXT

LFXT

3, 3(5)

2, 5 (6)(7) 7 2 2 no 8 ext 112 seg 51 64 PM

64 RGC

MSP430FR69221 64 2 DCO

LFXT 3, 3(5)

2, 5 (6)(7) 7 2 2 yes 8 ext 116 seg

100 seg

(DGG) 52

46 (DGG) 64 PM

64 RGC

56 DGG

MSP430FR68221 64 2 DCO

LFXT 3, 3(5)

2, 5 (6)(7) 7 2 2 no 8 ext 116 seg

100 seg

(DGG) 52

46 (DGG) 64 PM

64 RGC

56 DGG

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

SLASE23E –JANUARY 2015–REVISED AUGUST 2018

www.ti.com

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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721

MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

TI 16-bit and 32-bit microcontrollers High-performance, low-power solutions to enable the autonomous

future

Products for MSP430 ultra-low-power sensing and measurement microcontrollers One platform.

One ecosystem. Endless possibilities.

Products for MSP430 ultrasonic and performance sensing microcontrollers Ultra-low-power single-

chip MCUs with integrated sensing peripherals

Companion Products for MSP430FR6972 Review products that are frequently purchased or used with

this product.

Reference Designs for MSP430FR6972 The TI Designs Reference Design Library is a robust reference

design library that spans analog, embedded processor, and connectivity. Created by TI

experts to help you jump start your system design, all TI Designs include schematic or block

diagrams, BOMs, and design files to speed your time to market. Search and download

designs at ti.com/tidesigns.

P4.3/UCA0SOMI/UCA0RXD/UCB1STE

2P1.4/UCB0CLK/UCA0STE/TA1.0/S3

3P1.5/UCB0STE/UCA0CLK/TA0.0/S2

4P1.6/ TA0.1/S1UCB0SIMO/UCB0SDA/

5P1.7/ TA0.2/S0UCB0SOMI/UCB0SCL/

6R33/LCDCAP

7P6.0/R23

8P6.1/R13/LCDREF

9P6.2/COUT/R03

10P6.3/COM0

11P6.4/TB0.0/COM1/S31

12P6.5/TB0.1/COM2/S30

13P6.6/TB0.2/COM3/S29

14P3.0/UCB1CLK/S28

15P3.1/ S27UCB1SIMO/UCB1SDA/

16P3.2/ S26UCB1SOMI/UCB1SCL/

DVSS1

DVCC1

TEST/SBWTCK

RST/NMI/SBWTDIO

PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1

PJ.1/TDI/TCLK/MCLK/SRSCG0

PJ.2/TMS/ACLK/SROSCOFF

PJ.3/TCK/COUT/SRCPUOFF

P3.3/TA1.1/TB0CLK/S25

P3.4/UCA1SIMO/UCA1TXD/TB0.0/S24

P3.5/UCA1SOMI/UCA1RXD/TB0.1/S23

P3.6/UCA1CLK/TB0.2/S22

P3.7/UCA1STE/TB0.3/S21

P2.3/UCA0STE/TB0OUTH/S20

P2.2/UCA0CLK/TB0.4/RTCCLK/S19

P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0/S18

33 P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK/S17

34 P7.0/TA0CLK/S16

35 P7.1/TA0.0/ACLK/S15

36 P7.2/TA0.1/S14

37 P7.3/TA0.2/S13

38 P7.4/SMCLK/S12

39 DVSS2

40 DVCC2

41 P1.3/TA1.2/A3/C3

42 P1.2/TA1.1/TA0CLK/COUT/A2/C2

43 P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+

44 P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-

45 P9.4/A12/C12

46 P9.5/A13/C13

47 P9.6/A14/C14

48 P9.7/A15/C15

AVCC1

AVSS1

PJ.4/LFXIN

PJ.5/LFXOUT

AVSS2

P5.4/UCA1SIMO/UCA1TXD/S11

P5.5/UCA1SOMI/UCA1RXD/S10

P5.6/UCA1CLK/S9

P5.7/UCA1STE/TB0CLK/S8

P4.4/UCB1STE/TA1CLK/S7

P4.5/UCB1CLK/TA1.0/S6

P4.6/ TA1.1/S5UCB1SIMO/UCB1SDA/

P4.7/ TA1.2/S4UCB1SOMI/UCB1SCL/

DVSS3

DVCC3

P4.2/UCA0SIMO/UCA0TXD/UCB1CLK

MSP430FR692x

MSP430FR682x

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

www.ti.com

SLASE23E –JANUARY 2015–REVISED AUGUST 2018

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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721

MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

4 Terminal Configuration and Functions

4.1 Pin Diagrams

Figure 4-1 show the pinout for the 64-pin PM and RGC packages of the MSP430FR692x(1) and

MSP430FR682x(1) MCUs.

On devices with UART BSL: P2.0: BSL_TX; P2.1: BSL_RX

On devices with I2C BSL: P1.6: BSL_DAT; P1.7: BSL_CLK

NOTE: TI recommends connecting the RGC package thermal pad to VSS.

Figure 4-1. 64-Pin PM and RGC Packages (Top View), MSP430FR692x(1) MSP430FR682x(1)

P4.3/UCA0SOMI/UCA0RXD/UCB1STE/S4

2P1.4/UCB0CLK/UCA0STE/TA1.0/S3

3P1.5/UCB0STE/UCA0CLK/TA0.0/S2

4P1.6/ TA0.1/S1UCB0SIMO/UCB0SDA/

5P1.7/ TA0.2/S0UCB0SOMI/UCB0SCL/

6R33/LCDCAP

7P6.0/R23

8P6.1/R13/LCDREF

9P6.2/COUT/R03

10P6.3/COM0

11P6.4/TB0.0/COM1/S30

12P6.5/TB0.1/COM2/S29

13P6.6/TB0.2/COM3/S28

14P3.0/UCB1CLK/TA3.2/S27

15P3.1/ S26UCB1SIMO/UCB1SDA/TA3.3/

16P3.2/ S25UCB1SOMI/UCB1SCL/TA3.4/

DVSS1

DVCC1

TEST/SBWTCK

RST/NMI/SBWTDIO

PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1

PJ.1/TDI/TCLK/MCLK/SRSCG0

PJ.2/TMS/ACLK/SROSCOFF

PJ.3/TCK/COUT/SRCPUOFF

P3.3/TA1.1/TB0CLK/S24

P3.4/UCA1SIMO/UCA1TXD/TB0.0/S23

P3.5/UCA1SOMI/UCA1RXD/TB0.1/S22

P3.6/UCA1CLK/TB0.2/S21

P3.7/UCA1STE/TB0.3/S20

P2.3/UCA0STE/TB0OUTH/S19

P2.2/UCA0CLK/TB0.4/RTCCLK/S18

P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0/S17

33 P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK/S16

34 P7.0/TA0CLK/S15

35 P7.1/TA0.0/ACLK/S14

36 P7.2/TA0.1/S13

37 P7.3/TA0.2/S12

38 P7.4/SMCLK/S11

39 DVSS2

40 DVCC2

41 P1.3/TA1.2/A3/C3

42 P1.2/TA1.1/TA0CLK/COUT/A2/C2

43 P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+

44 P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-

45 P9.4/A12/C12

46 P9.5/A13/C13

47 P9.6/A14/C14

48 P9.7/A15/C15

AVCC1

AVSS1

PJ.4/LFXIN

PJ.5/LFXOUT

AVSS2

54555657

P5.7/UCA1STE/TB0CLK/S10

P4.4/UCB1STE/TA1CLK/S9

P4.5/UCB1CLK/TA1.0/S8

P4.6/ TA1.1/S7UCB1SIMO/UCB1SDA/

P4.7/ TA1.2/S6UCB1SOMI/UCB1SCL/

DVSS3

DVCC3

P4.2/UCA0SIMO/UCA0TXD/UCB1CLK/S5

MSP430FR697x

MSP430FR687x

AVSS3

PJ.7/HFXOUT

PJ.6/HFXIN

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

Figure 4-2 shows the pinout for the 64-pin PM and RGC packages of the MSP430FR697x(1) and

MSP430FR687x(1) MCUs.

On devices with UART BSL: P2.0: BSL_TX; P2.1: BSL_RX

On devices with I2C BSL: P1.6: BSL_DAT; P1.7: BSL_CLK

NOTE: TI recommends connecting the RGC package thermal pad to VSS.

Figure 4-2. 64-Pin PM and RGC Packages (Top View) – MSP430FR697x(1), MSP430FR687x(1)

MSP430FR692x

MSP430FR682x

P1.4/UCB0CLK/UCA0STE/TA1.0/S3

P1.5/UCB0STE/UCA0CLK/TA0.0/S2

P1.6/UCB0SIMO/UCB0SDA/TA0.1/S1

P1.7/UCB0SOMI/UCB0SCL/TA0.2/S0

R33/LCDCAP

P6.0/R23

P6.1/R13/LCDREF

P6.2/COUT/R03

P6.3/COM0

P6.4/TB0.0/COM1/S27

P6.5/TB0.1/COM2/S26

P6.6/TB0.2/COM3/S25

P3.0/UCB1CLK/TA3.2/S24

P3.1/UCB1SIMO/UCB1SDA/TA3.3/S23

P3.2/UCB1SOMI/UCB1SCL/TA3.4/S22

DVSS2

DVCC2

TEST/SBWTCK

RST /NMI/SBWTDIO

PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1

PJ.1/TDI/TCLK/MCLK/SRSCG0

PJ.2/TMS/ACLK/SROSCOFF

PJ.3/TCK/COUT/SRCPUOFF

P3.3/TA1.1/TB0CLK/S21 P3.4/UCA1SIMO/UCA1TXD/TB0.0/S20

P3.5/UCA1SOMI/UCA1RXD/TB0.1/S19

P3.6/UCA1CLK/TB0.2/S18

P3.7/UCA1STE/TB0.3/S17

P2.3/UCA0STE/TB0OUTH/S16

P2.2/UCA0CLK/TB0.4/RTCCLK/S15

P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0/S14

P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK/S13

P7.0/TA0CLK/S12

P7.1/TA0.0/ACLK/S11

P7.2/TA0.1/S10

P7.3/TA0.2/S9

P7.4/SMCLK/S8

DVSS3

DVCC3

P1.3/TA1.2/A3/C3

P1.2/TA1.1/TA0CLK/COUT/A2/C2

P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+

P1.0/TA0.1/RTCCLK/DMAE0/A0/C0/VREF-/VeREF-

AVCC1

AVSS1

PJ.4/LFXIN

PJ.5/LFXOUT

AVSS2

P4.4/UCB1STE/TA1CLK/S7

P4.5/UCB1CLK/TA1.0/S6

P4.6/UCB1SIMO/UCB1SDA/TA1.1/S5

P4.7/UCB1SOMI/UCB1SCL/TA1.2/S4

P9.4/A12/C12

P9.5/A13/C13

P9.6/A14/C14

P9.7/A15/C15

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

Figure 4-3 shows the pinout for the 56-pin DGG package of the MSP430FR692x(1) and

MSP430FR682x(1) MCUs.

On devices with UART BSL: P2.0: BSL_TX; P2.1: BSL_RX

On devices with I2C BSL: P1.6: BSL_DAT; P1.7: BSL_CLK

Figure 4-3. 56-Pin DGG Package (Top View) – MSP430FR692x(1), MSP430FR682x(1)

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

(1) Signals names with (RD) denote the reset default pin name.

(2) To determine the pin mux encodings for each pin, see the Port I/O Diagrams section.

(3) Sz = The LCD segment that is assigned to each pin can vary by package – see the "LCD SEG" columns for the assignment on this pin.

(4) Signal Types: I = Input, O = Output, I/O = Input or Output.

(5) Buffer Types: LVCMOS, Analog, or Power (see Table 4-3 for details)

(6) Reset States:

OFF = High impedance with Schmitt-trigger inputs and pullup or pulldown (if available) disabled

N/A = Not applicable

4.2 Pin Attributes

Table 4-1 lists the attributes of each pin.

Table 4-1. Pin Attributes

FR692x(1), FR682x(1) FR697x(1),

FR687x(1) SIGNAL NAME(1)

(2) (3) SIGNAL

TYPE(4) BUFFER

TYPE(5) POWER

SOURCE

RESET

STATE

AFTER

BOR(6)

PM, RGC DGG PM, RGC

NO. LCD

SEG PIN

NO. LCD

SEG PIN

NO. LCD

SEG

1 1 S4

P4.3 (RD) I/O LVCMOS DVCC OFF

UCA0SOMI I/O LVCMOS DVCC –

UCA0RXD I LVCMOS DVCC –

UCB1STE I/O LVCMOS DVCC –

Sz O Analog DVCC –

2 S3 7 S3 2 S3

P1.4 (RD) I/O LVCMOS DVCC OFF

UCB0CLK I/O LVCMOS DVCC –

UCA0STE I/O LVCMOS DVCC –

TA1.0 I/O LVCMOS DVCC –

Sz O Analog DVCC –

3 S2 8 S2 3 S2

P1.5 (RD) I/O LVCMOS DVCC OFF

UCB0STE I/O LVCMOS DVCC –

UCA0CLK I/O LVCMOS DVCC –

TA0.0 I/O LVCMOS DVCC –

Sz O Analog DVCC –

4 S1 9 S1 4 S1

P1.6 (RD) I/O LVCMOS DVCC OFF

UCB0SIMO I/O LVCMOS DVCC –

UCB0SDA I/O LVCMOS DVCC –

BSL_DAT I LVCMOS DVCC –

TA0.1 I/O LVCMOS DVCC –

Sz O Analog DVCC –

5 S0 10 S0 5 S0

P1.7 (RD) I/O LVCMOS DVCC OFF

UCB0SOMI I/O LVCMOS DVCC –

UCB0SCL I/O LVCMOS DVCC –

BSL_CLK I LVCMOS DVCC –

TA0.2 I/O LVCMOS DVCC –

Sz O Analog DVCC –

6 11 6 R33 I/O Analog DVCC –

LCDCAP I/O Analog DVCC –

7 12 7 P6.0 (RD) I/O LVCMOS DVCC OFF

R23 I/O Analog DVCC –

8 13 8 P6.1 (RD) I/O LVCMOS DVCC OFF

R13 I/O Analog DVCC –

LCDREF I Analog – –

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 4-1. Pin Attributes (continued)

FR692x(1), FR682x(1) FR697x(1),

FR687x(1) SIGNAL NAME(1)

(2) (3) SIGNAL

TYPE(4) BUFFER

TYPE(5) POWER

SOURCE

RESET

STATE

AFTER

BOR(6)

PM, RGC DGG PM, RGC

NO. LCD

SEG PIN

NO. LCD

SEG PIN

NO. LCD

SEG

9 14 9 P6.2 (RD) I/O LVCMOS DVCC OFF

COUT O LVCMOS DVCC –

R03 I/O Analog DVCC –

10 15 10 P6.3 (RD) I/O LVCMOS DVCC OFF

COM0 O Analog DVCC –

11 S31 16 S27 11 S30

P6.4 (RD) I/O LVCMOS DVCC OFF

TB0.0 I/O LVCMOS DVCC –

COM1 O Analog DVCC –

Sz O Analog DVCC –

12 S30 17 S26 12 S29

P6.5 (RD) I/O LVCMOS DVCC OFF

TB0.1 I/O LVCMOS DVCC –

COM2 O Analog DVCC –

Sz O Analog DVCC –

13 S29 18 S25 13 S28

P6.6 (RD) I/O LVCMOS DVCC OFF

TB0.2 I/O LVCMOS DVCC –

COM3 O Analog DVCC –

Sz O Analog DVCC –

14 S28 19 S24 14 S27

P3.0 (RD) I/O LVCMOS DVCC OFF

UCB1CLK I/O LVCMOS DVCC –

TA3.2 I/O LVCMOS DVCC –

Sz O Analog DVCC –

15 S27 20 S23 15 S26

P3.1 (RD) I/O LVCMOS DVCC OFF

UCB1SIMO I/O LVCMOS DVCC –

UCB1SDA I/O LVCMOS DVCC –

TA3.3 I/O LVCMOS DVCC –

Sz O Analog DVCC –

16 S26 21 S22 16 S25

P3.2 (RD) I/O LVCMOS DVCC OFF

UCB1SOMI I/O LVCMOS DVCC –

UCB1SCL I/O LVCMOS DVCC –

TA3.4 I/O LVCMOS DVCC –

Sz O Analog DVCC –

17 17 DVSS1 P Power – N/A

18 18 DVCC1 P Power – N/A

19 22 19 TEST I LVCMOS DVCC OFF

SBWTCK I LVCMOS DVCC –

20 23 20 RST I LVCMOS DVCC OFF

NMI I LVCMOS DVCC –

SBWTDIO I/O LVCMOS DVCC –

21 24 21

PJ.0 (RD) I/O LVCMOS DVCC OFF

TDO O LVCMOS DVCC –

TB0OUTH I LVCMOS DVCC –

SMCLK O LVCMOS DVCC –

SRSCG1 O LVCMOS DVCC –

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 4-1. Pin Attributes (continued)

FR692x(1), FR682x(1) FR697x(1),

FR687x(1) SIGNAL NAME(1)

(2) (3) SIGNAL

TYPE(4) BUFFER

TYPE(5) POWER

SOURCE

RESET

STATE

AFTER

BOR(6)

PM, RGC DGG PM, RGC

NO. LCD

SEG PIN

NO. LCD

SEG PIN

NO. LCD

SEG

22 25 22

PJ.1 (RD) I/O LVCMOS DVCC OFF

TDI I LVCMOS DVCC –

TCLK I LVCMOS DVCC –

MCLK O LVCMOS DVCC –

SRSCG0 O LVCMOS DVCC –

23 26 23

PJ.2 (RD) I/O LVCMOS DVCC OFF

TMS I LVCMOS DVCC –

ACLK O LVCMOS DVCC –

SROSCOFF O LVCMOS DVCC –

24 27 24

PJ.3 (RD) I/O LVCMOS DVCC OFF

TCK I LVCMOS DVCC –

COUT O LVCMOS DVCC –

SRCPUOFF O LVCMOS DVCC –

25 S25 28 S21 25 S24

P3.3 (RD) I/O LVCMOS DVCC OFF

TA1.1 I/O LVCMOS DVCC –

TB0CLK I LVCMOS DVCC –

Sz O Analog DVCC –

26 S24 29 S20 26 S23

P3.4 (RD) I/O LVCMOS DVCC OFF

UCA1SIMO I/O LVCMOS DVCC –

UCA1TXD O LVCMOS DVCC –

TB0.0 I/O LVCMOS DVCC –

Sz O Analog DVCC –

27 S23 30 S19 27 S22

P3.5 (RD) I/O LVCMOS DVCC OFF

UCA1SOMI I/O LVCMOS DVCC –

UCA1RXD I LVCMOS DVCC –

TB0.1 I/O LVCMOS DVCC –

Sz O Analog DVCC –

28 S22 31 S18 28 S21

P3.6 (RD) I/O LVCMOS DVCC OFF

UCA1CLK I/O LVCMOS DVCC –

TB0.2 I/O LVCMOS DVCC –

Sz O Analog DVCC –

29 S21 32 S17 29 S20

P3.7 (RD) I/O LVCMOS DVCC OFF

UCA1STE I/O LVCMOS DVCC –

TB0.3 I/O LVCMOS DVCC –

Sz O Analog DVCC –

30 S20 33 S16 30 S19

P2.3 (RD) I/O LVCMOS DVCC OFF

UCA0STE I/O LVCMOS DVCC –

TB0OUTH I LVCMOS DVCC –

Sz O Analog DVCC –

31 S19 34 S15 31 S18

P2.2 (RD) I/O LVCMOS DVCC OFF

UCA0CLK I/O LVCMOS DVCC –

TB0.4 I/O LVCMOS DVCC –

RTCCLK O LVCMOS DVCC –

Sz O Analog DVCC –

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 4-1. Pin Attributes (continued)

FR692x(1), FR682x(1) FR697x(1),

FR687x(1) SIGNAL NAME(1)

(2) (3) SIGNAL

TYPE(4) BUFFER

TYPE(5) POWER

SOURCE

RESET

STATE

AFTER

BOR(6)

PM, RGC DGG PM, RGC

NO. LCD

SEG PIN

NO. LCD

SEG PIN

NO. LCD

SEG

32 S18 35 S14 32 S17

P2.1 (RD) I/O LVCMOS DVCC OFF

UCA0SOMI I/O LVCMOS DVCC –

UCA0RXD I LVCMOS DVCC –

BSL_RX I LVCMOS DVCC –

TB0.5 I/O LVCMOS DVCC –

DMAE0 I LVCMOS DVCC –

Sz O Analog DVCC –

33 S17 36 S13 33 S16

P2.0 (RD) I/O LVCMOS DVCC OFF

UCA0SIMO I/O LVCMOS DVCC –

UCA0TXD O LVCMOS DVCC –

BSL_TX O LVCMOS DVCC –

TB0.6 I/O LVCMOS DVCC –

TB0CLK I LVCMOS DVCC –

Sz O Analog DVCC –

34 S16 37 S12 34 S15 P7.0 (RD) I/O LVCMOS DVCC OFF

TA0CLK I LVCMOS DVCC –

Sz O Analog DVCC –

35 S15 38 S11 35 S14

P7.1 (RD) I/O LVCMOS DVCC OFF

TA0.0 I/O LVCMOS DVCC –

ACLK O LVCMOS DVCC –

Sz O Analog DVCC –

36 S14 39 S10 36 S13 P7.2 (RD) I/O LVCMOS DVCC OFF

TA0.1 I/O LVCMOS DVCC –

Sz O Analog DVCC –

37 S13 40 S9 37 S12 P7.3 (RD) I/O LVCMOS DVCC OFF

TA0.2 I/O LVCMOS DVCC –

Sz O Analog DVCC –

38 S12 41 S8 38 S11 P7.4 (RD) I/O LVCMOS DVCC OFF

SMCLK O LVCMOS DVCC –

Sz O Analog DVCC –

39 42 39 DVSS2 P Power – N/A

40 43 40 DVCC2 P Power – N/A

41 44 41

P1.3 (RD) I/O LVCMOS DVCC OFF

TA1.2 I/O LVCMOS DVCC –

A3 I Analog AVCC –

C3 I Analog AVCC –

42 45 42

P1.2 (RD) I/O LVCMOS DVCC OFF

TA1.1 I/O LVCMOS DVCC –

TA0CLK I LVCMOS DVCC –

COUT O LVCMOS DVCC –

A2 I Analog AVCC –

C2 I Analog AVCC –

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 4-1. Pin Attributes (continued)

FR692x(1), FR682x(1) FR697x(1),

FR687x(1) SIGNAL NAME(1)

(2) (3) SIGNAL

TYPE(4) BUFFER

TYPE(5) POWER

SOURCE

RESET

STATE

AFTER

BOR(6)

PM, RGC DGG PM, RGC

NO. LCD

SEG PIN

NO. LCD

SEG PIN

NO. LCD

SEG

43 46 43

P1.1 (RD) I/O LVCMOS DVCC OFF

TA0.2 I/O LVCMOS DVCC –

TA1CLK I LVCMOS DVCC –

COUT O LVCMOS DVCC –

A1 I Analog AVCC –

C1 I Analog AVCC –

VREF+ O Analog AVCC –

VeREF+ I Analog – –

44 47 44

P1.0 (RD) I/O LVCMOS DVCC OFF

TA0.1 I/O LVCMOS DVCC –

DMAE0 I LVCMOS DVCC –

RTCCLK O LVCMOS DVCC –

A0 I Analog AVCC –

C0 I Analog AVCC –

VREF- O Analog AVCC –

VeREF- I Analog – –

45 48 45 P9.4 (RD) I/O LVCMOS DVCC OFF

A12 I Analog AVCC –

C12 I Analog AVCC –

46 49 46 P9.5 (RD) I/O LVCMOS DVCC OFF

A13 I Analog AVCC –

C13 I Analog AVCC –

47 50 47 P9.6 (RD) I/O LVCMOS DVCC OFF

A14 I Analog AVCC –

C14 I Analog AVCC –

48 51 48 P9.7 (RD) I/O LVCMOS DVCC OFF

A15 I Analog AVCC –

C15 I Analog AVCC –

49 52 49 AVCC1 P Power – N/A

50 53 50 AVSS1 P Power – N/A

51 54 51 PJ.4 (RD) I/O LVCMOS DVCC OFF

LFXIN I Analog AVCC –

52 55 52 PJ.5 (RD) I/O LVCMOS DVCC OFF

LFXOUT O Analog AVCC –

53 56 53 AVSS2 P Power – N/A

54 PJ.7 (RD) I/O LVCMOS DVCC OFF

HFXOUT O Analog AVCC –

55 PJ.6 (RD) I/O LVCMOS DVCC OFF

HFXIN I Analog AVCC –

56 AVSS3 P Power – N/A

54 S11

P5.4 (RD) I/O LVCMOS DVCC OFF

UCA1SIMO I/O LVCMOS DVCC –

UCA1TXD O LVCMOS DVCC –

Sz O Analog DVCC –

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

Table 4-1. Pin Attributes (continued)

FR692x(1), FR682x(1) FR697x(1),

FR687x(1) SIGNAL NAME(1)

(2) (3) SIGNAL

TYPE(4) BUFFER

TYPE(5) POWER

SOURCE

RESET

STATE

AFTER

BOR(6)

PM, RGC DGG PM, RGC

NO. LCD

SEG PIN

NO. LCD

SEG PIN

NO. LCD

SEG

55 S10

P5.5 (RD) I/O LVCMOS DVCC OFF

UCA1SOMI I/O LVCMOS DVCC –

UCA1RXD I LVCMOS DVCC –

Sz O Analog DVCC –

56 S9 P5.6 (RD) I/O LVCMOS DVCC OFF

UCA1CLK I/O LVCMOS DVCC –

Sz O Analog DVCC –

57 S8 57 S10

P5.7 (RD) I/O LVCMOS DVCC OFF

UCA1STE I/O LVCMOS DVCC –

TB0CLK I LVCMOS DVCC –

Sz O Analog DVCC –

58 S7 1 S7 58 S9

P4.4 (RD) I/O LVCMOS DVCC OFF

UCB1STE I/O LVCMOS DVCC –

TA1CLK I LVCMOS DVCC –

Sz O Analog DVCC –

59 S6 2 S6 59 S8

P4.5 (RD) I/O LVCMOS DVCC OFF

UCB1CLK I/O LVCMOS DVCC –

TA1.0 I/O LVCMOS DVCC –

Sz O Analog DVCC –

60 S5 3 S5 60 S7

P4.6 (RD) I/O LVCMOS DVCC OFF

UCB1SIMO I/O LVCMOS DVCC –

UCB1SDA I/O LVCMOS DVCC –

TA1.1 I/O LVCMOS DVCC –

Sz O Analog DVCC –

61 S4 4 S4 61 S6

P4.7 (RD) I/O LVCMOS DVCC OFF

UCB1SOMI I/O LVCMOS DVCC –

UCB1SCL I/O LVCMOS DVCC –

TA1.2 I/O LVCMOS DVCC –

Sz O Analog DVCC –

62 5 62 DVSS3 P Power – N/A

63 6 63 DVCC3 P Power – N/A

64 64 S5

P4.2 (RD) I/O LVCMOS DVCC OFF

UCA0SIMO I/O LVCMOS DVCC –

UCA0TXD O LVCMOS DVCC –

UCB1CLK I/O LVCMOS DVCC –

Sz O Analog DVCC –

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

4.3 Signal Descriptions

Table 4-2 describes the signals.

Table 4-2. Signal Descriptions

FUNCTION SIGNAL

NAME

FR692x(1), FR682x(1) FR697x(1),

FR687x(1) SIGNAL

TYPE DESCRIPTIONPM, RGC DGG PM, RGC

NO. LCD

SEG PIN

NO. LCD

SEG PIN

NO. LCD

SEG

ADC

A0 44 47 44 I Analog input A0

A1 43 46 43 I Analog input A1

A2 42 45 42 I Analog input A2

A3 41 44 41 I Analog input A3

A12 45 48 45 I Analog input A12

A13 46 49 46 I Analog input A13

A14 47 50 47 I Analog input A14

A15 48 51 48 I Analog input A15

VREF+ 43 46 43 O Output of positive reference voltage

VREF- 44 47 44 O Output of negative reference voltage

VeREF+ 43 46 43 I Input for an external positive reference

voltage to the ADC

VeREF- 44 47 44 I Input for an external negative reference

voltage to the ADC

BSL (I2C) BSL_CLK 5 10 5 I BSL clock (I2C BSL)

BSL_DAT 4 9 4 I/O BSL data (I2C BSL)

BSL (UART) BSL_RX 32 35 32 I BSL receive (UART BSL)

BSL_TX 33 36 33 O BSL transmit (UART BSL)

Clock

ACLK 23

35 26

38 23

35 O ACLK output

HFXIN 55 I Input terminal of crystal oscillator XT2

HFXOUT 54 O Output terminal for crystal oscillator XT2

LFXIN 51 54 51 I Input terminal for crystal oscillator XT1

LFXOUT 52 55 52 O Output terminal of crystal oscillator XT1

MCLK 22 25 22 O MCLK output

RTCCLK 31

44 34

47 31

44 O RTC clock output for calibration

SMCLK 21

38 24

41 21

38 O SMCLK output

Comparator

C0 44 47 44 I Comparator input C0

C1 43 46 43 I Comparator input C1

C2 42 45 42 I Comparator input C2

C3 41 44 41 I Comparator input C3

C12 45 48 45 I Comparator input C12

C13 46 49 46 I Comparator input C13

C14 47 50 47 I Comparator input C14

C15 48 51 48 I Comparator input C15

COUT 9

43 O Comparator output

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 4-2. Signal Descriptions (continued)

FUNCTION SIGNAL

NAME

FR692x(1), FR682x(1) FR697x(1),

FR687x(1) SIGNAL

TYPE DESCRIPTIONPM, RGC DGG PM, RGC

NO. LCD

SEG PIN

NO. LCD

SEG PIN

NO. LCD

SEG

Debug

SBWTCK 19 22 19 I Spy-Bi-Wire input clock

SBWTDIO 20 23 20 I/O Spy-Bi-Wire data input/output

SRCPUOFF 24 27 24 O Low-power debug: CPU status register

CPUOFF

SROSCOFF 23 26 23 O Low-power debug: CPU status register

OSCOFF

SRSCG0 22 25 22 O Low-power debug: CPU status register

SCG0

SRSCG1 21 24 21 O Low-power debug: CPU status register

SCG1

TCK 24 27 24 I Test clock

TCLK 22 25 22 I Test clock input

TDI 22 25 22 I Test data input

TDO 21 24 21 O Test data output port

TEST 19 22 19 I Test mode pin - select digital I/O on JTAG

pins

TMS 23 26 23 I Test mode select

DMA DMAE0 32

44 35

47 32

44 I DMA external trigger input

GPIO

P1.0 44 47 44 I/O General-purpose digital I/O

P1.1 43 46 43 I/O General-purpose digital I/O

P1.2 42 45 42 I/O General-purpose digital I/O

P1.3 41 44 41 I/O General-purpose digital I/O

P1.4 2 7 2 I/O General-purpose digital I/O

P1.5 3 8 3 I/O General-purpose digital I/O

P1.6 4 9 4 I/O General-purpose digital I/O

P1.7 5 10 5 I/O General-purpose digital I/O

P2.0 33 36 33 I/O General-purpose digital I/O

P2.1 32 35 32 I/O General-purpose digital I/O

P2.2 31 34 31 I/O General-purpose digital I/O

P2.3 30 33 30 I/O General-purpose digital I/O

P3.0 14 19 14 I/O General-purpose digital I/O

P3.1 15 20 15 I/O General-purpose digital I/O

P3.2 16 21 16 I/O General-purpose digital I/O

P3.3 25 28 25 I/O General-purpose digital I/O

P3.4 26 29 26 I/O General-purpose digital I/O

P3.5 27 30 27 I/O General-purpose digital I/O

P3.6 28 31 28 I/O General-purpose digital I/O

P3.7 29 32 29 I/O General-purpose digital I/O

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 4-2. Signal Descriptions (continued)

FUNCTION SIGNAL

NAME

FR692x(1), FR682x(1) FR697x(1),

FR687x(1) SIGNAL

TYPE DESCRIPTIONPM, RGC DGG PM, RGC

NO. LCD

SEG PIN

NO. LCD

SEG PIN

NO. LCD

SEG

GPIO

P4.2 64 64 I/O General-purpose digital I/O

P4.3 1 1 I/O General-purpose digital I/O

P4.4 58 1 58 I/O General-purpose digital I/O

P4.5 59 2 59 I/O General-purpose digital I/O

P4.6 60 3 60 I/O General-purpose digital I/O

P4.7 61 4 61 I/O General-purpose digital I/O

P5.4 54 I/O General-purpose digital I/O

P5.5 55 I/O General-purpose digital I/O

P5.6 56 I/O General-purpose digital I/O

P5.7 57 57 I/O General-purpose digital I/O

P6.0 7 12 7 I/O General-purpose digital I/O

P6.1 8 13 8 I/O General-purpose digital I/O

P6.2 9 14 9 I/O General-purpose digital I/O

P6.3 10 15 10 I/O General-purpose digital I/O

P6.4 11 16 11 I/O General-purpose digital I/O

P6.5 12 17 12 I/O General-purpose digital I/O

P6.6 13 18 13 I/O General-purpose digital I/O

P7.0 34 37 34 I/O General-purpose digital I/O

P7.1 35 38 35 I/O General-purpose digital I/O

P7.2 36 39 36 I/O General-purpose digital I/O

P7.3 37 40 37 I/O General-purpose digital I/O

P7.4 38 41 38 I/O General-purpose digital I/O

P9.4 45 48 45 I/O General-purpose digital I/O

P9.5 46 49 46 I/O General-purpose digital I/O

P9.6 47 50 47 I/O General-purpose digital I/O

P9.7 48 51 48 I/O General-purpose digital I/O

PJ.0 21 24 21 I/O General-purpose digital I/O

PJ.1 22 25 22 I/O General-purpose digital I/O

PJ.2 23 26 23 I/O General-purpose digital I/O

PJ.3 24 27 24 I/O General-purpose digital I/O

PJ.4 51 54 51 I/O General-purpose digital I/O

PJ.5 52 55 52 I/O General-purpose digital I/O

PJ.6 55 I/O General-purpose digital I/O

PJ.7 54 I/O General-purpose digital I/O

I2C

UCB0SCL 5 10 5 I/O USCI_B0: I2C clock (I2C mode)

UCB0SDA 4 9 4 I/O USCI_B0: I2C data (I2C mode)

UCB1SCL 16

61 21

416

61 I/O USCI_B1: I2C clock (I2C mode)

UCB1SDA 15

60 20

315

60 I/O USCI_B1: I2C data (I2C mode)

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 4-2. Signal Descriptions (continued)

FUNCTION SIGNAL

NAME

FR692x(1), FR682x(1) FR697x(1),

FR687x(1) SIGNAL

TYPE DESCRIPTIONPM, RGC DGG PM, RGC

NO. LCD

SEG PIN

NO. LCD

SEG PIN

NO. LCD

SEG

LCD

COM0 10 15 10 O LCD common output COM0 for LCD

backplane

COM1 11 16 11 O LCD common output COM1 for LCD

backplane

COM2 12 17 12 O LCD common output COM2 for LCD

backplane

COM3 13 18 13 O LCD common output COM3 for LCD

backplane

LCDCAP 6 11 6 I LCD capacitor connection

LCDREF 8 13 8 I External reference voltage input for

regulated LCD voltage

R03 9 14 9 I/O Input/output port of lowest analog LCD

voltage (V5)

R13 8 13 8 I/O Input/output port of third most positive

analog LCD voltage (V3 or V4)

R23 7 12 7 I/O Input/output port of second most positive

analog LCD voltage (V2)

R33 6 11 6 I/O Input/output port of most positive analog

LCD voltage (V1)

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 4-2. Signal Descriptions (continued)

FUNCTION SIGNAL

NAME

FR692x(1), FR682x(1) FR697x(1),

FR687x(1) SIGNAL

TYPE DESCRIPTIONPM, RGC DGG PM, RGC

NO. LCD

SEG PIN

NO. LCD

SEG PIN

NO. LCD

SEG

LCD Sz

1 S4 O

LCD segment output (package specific)

64 S5 O

5 S0 10 S0 5 S0 O

4 S1 9 S1 4 S1 O

3 S2 8 S2 3 S2 O

2 S3 7 S3 2 S3 O

61 S4 4 S4 61 S6 O

60 S5 3 S5 60 S7 O

59 S6 2 S6 59 S8 O

58 S7 1 S7 58 S9 O

57 S8 57 S10 O

56 S9 O

55 S10 O

54 S11 O

38 S12 41 S8 38 S11 O

37 S13 40 S9 37 S12 O

36 S14 39 S10 36 S13 O

35 S15 38 S11 35 S14 O

34 S16 37 S12 34 S15 O

33 S17 36 S13 33 S16 O

32 S18 35 S14 32 S17 O

31 S19 34 S15 31 S18 O

30 S20 33 S16 30 S19 O

29 S21 32 S17 29 S20 O

28 S22 31 S18 28 S21 O

27 S23 30 S19 27 S22 O

26 S24 29 S20 26 S23 O

25 S25 28 S21 25 S24 O

16 S26 21 S22 16 S25 O

15 S27 20 S23 15 S26 O

14 S28 19 S24 14 S27 O

13 S29 18 S25 13 S28 O

12 S30 17 S26 12 S29 O

11 S31 16 S27 11 S30 O

Power

AVCC1 49 52 49 P Analog power supply

AVSS1 50 53 50 P Analog ground supply

AVSS2 53 56 53 P Analog ground supply

AVSS3 56 P Analog ground supply

DVCC1 18 18 P Digital power supply

DVCC2 40 43 40 P Digital power supply

DVCC3 63 6 63 P Digital power supply

DVSS1 17 17 P Digital ground supply

DVSS2 39 42 39 P Digital ground supply

DVSS3 62 5 62 P Digital ground supply

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 4-2. Signal Descriptions (continued)

FUNCTION SIGNAL

NAME

FR692x(1), FR682x(1) FR697x(1),

FR687x(1) SIGNAL

TYPE DESCRIPTIONPM, RGC DGG PM, RGC

NO. LCD

SEG PIN

NO. LCD

SEG PIN

NO. LCD

SEG

SPI

UCA0CLK 3

31 8

34 3

31 I/O USCI_A0: Clock signal input (SPI slave

mode), Clock signal output (SPI master

mode)

UCA0SIMO 33

64 36 33

64 I/O USCI_A0: Slave in, master out (SPI mode)

UCA0SOMI 1

32 35 1

32 I/O USCI_A0: Slave out, master in (SPI mode)

UCA0STE 2

30 7

33 2

30 I/O USCI_A0: Slave transmit enable (SPI

mode)

UCA1CLK 28

56 31 28 I/O USCI_A1: Clock signal input (SPI slave

mode), Clock signal output (SPI master

mode)

UCA1SIMO 26

54 29 26 I/O USCI_A1: Slave in, master out (SPI mode)

UCA1SOMI 27

55 30 27 I/O USCI_A1: Slave out, master in (SPI mode)

UCA1STE 29

57 32 29

57 I/O USCI_A1: Slave transmit enable (SPI

mode)

UCB0CLK 2 7 2 I/O USCI_B0: Clock signal input (SPI slave

mode), Clock signal output (SPI master

mode)

UCB0SIMO 4 9 4 I/O USCI_B0: Slave in, master out (SPI mode)

UCB0SOMI 5 10 5 I/O USCI_B0: Slave out, master in (SPI mode)

UCB0STE 3 8 3 I/O USCI_B0: Slave transmit enable (SPI

mode)

UCB1CLK 14

64 19

214

64 I/O USCI_B1: Clock signal input (SPI slave

mode), Clock signal output (SPI master

mode)

UCB1SIMO 60

15 3

20 60

15 I/O USCI_B1: Slave in, master out (SPI mode)

UCB1SOMI 16

61 21

416

61 I/O USCI_B1: Slave out, master in (SPI mode)

UCB1STE 1

58 11

58 I/O USCI_B1: Slave transmit enable (SPI

mode)

System NMI 20 23 20 I Nonmaskable interrupt input

RST 20 23 20 I Reset input active low

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 4-2. Signal Descriptions (continued)

FUNCTION SIGNAL

NAME

FR692x(1), FR682x(1) FR697x(1),

FR687x(1) SIGNAL

TYPE DESCRIPTIONPM, RGC DGG PM, RGC

NO. LCD

SEG PIN

NO. LCD

SEG PIN

NO. LCD

SEG

Timer_A

TA0.0 3

35 8

38 3

35 I/O Timer_A TA0 CCR0 capture: CCI0A input,

compare: Out0 output

TA0.1 4

44 I/O Timer_A TA0 CCR1 capture: CCI1A input,

compare: Out1 output

TA0.2 5

43 I/O Timer_A TA0 CCR2 capture: CCI2A input,

compare: Out2 output

TA0CLK 34

42 37

45 34

42 I Timer_A TA0 clock signal TA0CLK input

TA1.0 2

59 7

59 I/O Timer_A TA1 CCR0 capture: CCI0A input,

compare: Out0 output

TA1.1 25

60 I/O Timer_A TA1 CCR1 capture: CCI1A input,

compare: Out1 output

TA1.2 41

61 44

441

61 I/O Timer_A TA1 CCR2 capture: CCI2A input,

compare: Out2 output

TA1CLK 43

58 46

143

58 I Timer_A TA1 clock signal TA1CLK input

TA3.2 19 14 I/O

Timer_A TA3 CCR2 capture: CCI2B input,

compare: Out2 output

(Note: Not available for FR692x and

FR682x 64-pin package. Internally tied to

DVSS when TA3 is selected)

TA3.3 20 15 I/O

Timer_A TA3 CCR3 capture: CCI3B input,

compare: Out3 output

(Note: Not available for FR692x and

FR682x 64-pin package. Internally tied to

DVSS when TA3 is selected)

TA3.4 21 16 I/O

Timer_A TA3 CCR4 capture: CCI4B input,

compare: Out4 output

(Note: Not available for FR692x and

FR682x 64-pin package. Internally tied to

DVSS when TA3 is selected)

Timer_B

TB0.0 11

26 16

29 11

26 I/O Timer_B TB0 CCR0 capture: CCI0B input,

compare: Out0 output

TB0.1 12

27 17

30 12

27 I/O Timer_B TB0 CCR1 capture: CCI1A input,

compare: Out1 output

TB0.2 13

28 18

31 13

28 I/O Timer_B TB0 CCR2 capture: CCI2A input,

compare: Out2 output

TB0.3 29 32 29 I/O Timer_B TB0 CCR3 capture: CCI3B input,

compare: Out3 output

TB0.4 31 34 31 I/O Timer_B TB0 CCR4 capture: CCI4B input,

compare: Out4 output

TB0.5 32 35 32 I/O Timer_B TB0 CCR5 capture: CCI5B input,

compare: Out5 output

TB0.6 33 36 33 I/O Timer_B TB0 CCR6 capture: CCI6B input,

compare: Out6 output

TB0CLK 25

57 28

36 25

57 I Timer_B TB0 clock signal TB0CLK input

TB0OUTH 21

30 24

33 21

30 ISwitch all PWM outputs high impedance

input - Timer_B TB0

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 4-2. Signal Descriptions (continued)

FUNCTION SIGNAL

NAME

FR692x(1), FR682x(1) FR697x(1),

FR687x(1) SIGNAL

TYPE DESCRIPTIONPM, RGC DGG PM, RGC

NO. LCD

SEG PIN

NO. LCD

SEG PIN

NO. LCD

SEG

UART

UCA0RXD 1

32 35 1

32 I USCI_A0: Receive data (UART mode)

UCA0TXD 33

64 36 33

64 O USCI_A0: Transmit data (UART mode)

UCA1RXD 27

55 30 27 I USCI_A1: Receive data (UART mode)

UCA1TXD 26

54 29 26 O USCI_A1: Transmit data (UART mode)

Thermal Pad RGC package only. VQFN package

exposed thermal pad. TI recommends

connection to VSS.

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

4.4 Pin Multiplexing

Pin multiplexing for these devices is controlled by both register settings and operating modes (for

example, if the device is in test mode). For details of the settings for each pin and schematics of the

multiplexed ports, see Section 6.11.23.

4.5 Buffer Type

Table 4-3 describes the buffer types that are referenced in Section 4.2.

(1) Only for Input pins.

Table 4-3. Buffer Type

BUFFER TYPE

(STANDARD) NOMINAL

VOLTAGE HYSTERESIS PU OR PD

NOMINAL

PU OR PD

STRENGTH

(µA)

OUTPUT

DRIVE

STRENGTH

(mA)

OTHER

CHARACTERISTICS

LVCMOS 3.0 V Y(1) Programmable See Table 5-11 See

Section 5.13.5.1

Analog 3.0 V N N/A N/A N/A See analog modules in

Section 5 for details

Power (DVCC) 3.0 V N N/A N/A N/A SVS enables hysteresis on

DVCC

Power (AVCC) 3.0 V N N/A N/A N/A

(1) Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection

guidelines.

(2) The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG

mode with TI tools like FET interfaces or GANG programmers.

4.6 Connection of Unused Pins

Table 4-4 lists the correct termination of all unused pins.

Table 4-4. Connection of Unused Pins(1)

PIN POTENTIAL COMMENT

AVCC DVCC

AVSS DVSS

Px.0 to Px.7 Open Switched to port function, output direction (PxDIR.n = 1)

R33/LCDCAP DVSS or DVCC If not used, the pin can be tied to either supply.

RST/NMI DVCC or VCC 47-kΩpullup or internal pullup selected with 10-nF (2.2 nF(2)) pulldown

PJ.0/TDO

PJ.1/TDI

PJ.2/TMS

PJ.3/TCK Open The JTAG pins are shared with general-purpose I/O function (PJ.x). If these pins are not used, they

should be set to port function and output direction. When used as JTAG pins, these pins should

remain open.

TEST Open This pin always has an internal pulldown enabled.

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Voltage differences between DVCC and AVCC exceeding the specified limits may cause malfunction of the device including erroneous

writes to RAM and FRAM.

(3) All voltages referenced to VSS.

(4) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

5 Specifications

5.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT

Voltage applied at DVCC and AVCC pins to VSS –0.3 4.1 V

Voltage difference between DVCC and AVCC pins(2) ±0.3 V

Voltage applied to any pin (3) –0.3 VCC + 0.3

(4.1 Maximum) V

Diode current at any device pin ±2 mA

Storage temperature, Tstg(4) –40 125 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as

±1000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V

may actually have higher performance.

5.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V

Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250

(1) TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up, power down, and device

operation, the voltage difference between AVCC and DVCC must not exceed the limits specified in Absolute Maximum Ratings.

Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.

(2) Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR

resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation for

capacitor CDVCC should limit the slopes accordingly.

(3) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.

(4) The minimum supply voltage is defined by the supervisor SVS levels. See the PMM SVS threshold parameters in Table 5-2 for the exact

values.

(5) As decoupling capacitor for each supply pin pair (DVCC and DVSS, AVCC and AVSS), a low-ESR ceramic capacitor of 100 nF

(minimum) should be placed as close as possible (within a few millimeters) to the respective pin pairs.

(6) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

(7) DCO settings and HF cyrstals with a typical value less than or equal to the specified MAX value are permitted.

(8) Wait states only occur on actual FRAM accesses; that is, on FRAM cache misses. RAM and peripheral accesses are always excecuted

without wait states.

(9) DCO settings and HF cyrstals with a typical value less than or equal to the specified MAX value are permitted. If a clock source with a

higher typical value is used, the clock must be divided in the clock system.

5.3 Recommended Operating Conditions

Typical data are based on VCC = 3.0 V, TA= 25°C (unless otherwise noted) MIN NOM MAX UNIT

VCC Supply voltage applied at all DVCC and AVCC pins(1) (2) (3) 1.8(4) 3.6 V

VSS Supply voltage applied at all DVSS and AVSS pins 0 V

TAOperating free-air temperature –40 85 °C

TJOperating junction temperature –40 85 °C

CDVCC Capacitor value at DVCC(5) 1–20% µF

fSYSTEM Processor frequency (maximum MCLK

frequency)(6) No FRAM wait states (NWAITSx = 0) 0 8(7) MHz

With FRAM wait states (NWAITSx = 1)(8) 0 16(9)

fACLK Maximum ACLK frequency 50 kHz

fSMCLK Maximum SMCLK frequency 16(9) MHz

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(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.

(2) Characterized with program executing typical data processing.

fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency, except for 12 MHz. For 12 MHz, fDCO= 24 MHz and

fMCLK = fSMCLK = fDCO/2.

At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency

(fMCLK,eff) decreases. The effective MCLK frequency also depends on the cache hit ratio. SMCLK is not affected by the number of wait

states or the cache hit ratio.

The following equation can be used to compute fMCLK,eff:

fMCLK,eff = fMCLK / [wait states × (1 - cache hit ratio) + 1]

For example, with 1 wait state and 75% cache hit ratio fMCKL,eff = fMCLK / [1 × (1 - 0.75) + 1] = fMCLK / 1.25.

(3) Represents typical program execution. Program and data reside entirely in FRAM. All execution is from FRAM.

(4) Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit

ratio represents number cache accesess divided by the total number of FRAM accesses. For example, a 75% ratio implies three of

every four accesses is from cache, and the remaining are FRAM accesses.

(5) See Figure 5-1 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best

linear fit using the typical data shown in Section 5.4.

(6) Program and data reside entirely in RAM. All execution is from RAM.

(7) Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.

5.4 Active Mode Supply Current Into VCC Excluding External Current

over recommended operating free-air temperature (unless otherwise noted)(1) (2)

PARAMETER EXECUTION

MEMORY VCC

FREQUENCY (fMCLK = fSMCLK)

UNIT

1 MHz

0 WAIT

STATES

(NWAITSx = 0)

4 MHz

0 WAIT

STATES

(NWAITSx = 0)

8 MHz

0 WAIT

STATES

(NWAITSx = 0)

12 MHz

1 WAIT

STATES

(NWAITSx = 1)

16 MHz

1 WAIT

STATES

(NWAITSx = 1)

TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX

IAM, FRAM_UNI

(Unified memory)(3) FRAM 3.0 V 210 640 1220 1475 1845 µA

IAM, FRAM(0%)(4) (5) FRAM

0% cache hit

ratio 3.0 V 370 1280 2510 2080 2650 µA

IAM, FRAM(50%)(4) (5) FRAM

50% cache hit

ratio 3.0 V 240 745 1440 1575 1990 µA

IAM, FRAM(66%)(4) (5) FRAM

66% cache hit

ratio 3.0 V 200 560 1070 1300 1620 µA

IAM, FRAM(75%)(4) (5) FRAM

75% cache hit

ratio 3.0 V 170 255 480 890 1085 1155 1310 1420 1620 µA

IAM, FRAM(100%(4) (5) FRAM

100% cache hit

ratio 3.0 V 110 235 420 640 730 µA

IAM, RAM (6) (5) RAM 3.0 V 130 320 585 890 1070 µA

IAM, RAM only (7) (5) RAM 3.0 V 100 180 290 555 860 1040 1300 µA

500

1000

1500

2000

2500

3000

0 1 2 3 4 5 6 7 8 9

Active Mode Current [µA]

MCLK Frequency [MHz]

I(AM,0%)

I(AM,50%)

I(AM,66%)

I(AM,75%)

I(AM,100%)

I(AM,RAMonly)

C001

I(AM,75%)[uA] = 103*f[MHz] + 68

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5.5 Typical Characteristics - Active Mode Supply Currents

NOTE: I(AM, cache hit ratio): Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with

cache hit-to-miss ratio as specified. Cache hit ratio represents number cache accesses divided by the total number of

FRAM accesses. For example, a 75% ratio implies three of every four accesses is from cache, and the remaining are

FRAM accesses.

NOTE: I(AM, RAMonly): Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.

Figure 5-1. Typical Active Mode Supply Currents, No Wait States

(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.

(2) Current for watchdog timer clocked by SMCLK included.

fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO at specified frequency - except for 12 MHz: here fDCO=24MHz and fSMCLK = fDCO/2.

5.6 Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current

over recommended operating free-air temperature (unless otherwise noted)(1) (2)

PARAMETER VCC

FREQUENCY (fSMCLK)

UNIT1 MHz 4 MHz 8 MHz 12 MHz 16 MHz

TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX

ILPM0 2.2 V 75 105 165 250 230 µA

3.0 V 80 120 115 175 260 240 275

ILPM1 2.2 V 40 65 130 215 195 µA

3.0 V 40 65 65 130 215 195 220

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(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.

(2) Not applicable for devices with HF crystal oscillator only.

(3) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are

chosen to closely match the required 12.5 pF load.

(4) Low-power mode 2, crystal oscillator test conditions:

Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included.

CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),

fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz

(5) Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are

chosen to closely match the required 3.7-pF load.

(6) Low-power mode 2, VLO test conditions:

Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). Current for brownout and SVS included.

CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),

fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz

(7) Low-power mode 3, 12-pF crystal, includes SVS test conditions:

Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),

fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz

Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional

idle current. See the idle currents specified for the respective peripheral groups.

(8) Low-power mode 3, 3.7-pF crystal, excludes SVS test conditions:

Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE =

0).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),

fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz

Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional

idle current. See the idle currents specified for the respective peripheral groups.

(9) Low-power mode 3, VLO, excludes SVS test conditions:

Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). Current for brownout included. SVS disabled

(SVSHE = 0).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),

fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz

Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional

idle current. See the idle currents specified for the respective peripheral groups.

(10) Low-power mode 3, VLO, excludes SVS, RAM powered down completely test conditions:

Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). Current for brownout included. SVS disabled

(SVSHE = 0). RAM disabled (RCCTL0 = 5A55h).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),

fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz

Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional

idle current. See the idle currents specified for the respective peripheral groups.

5.7 Low-Power Mode LPM2, LPM3, LPM4 Supply Currents (Into VCC) Excluding External

Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)

PARAMETER VCC –40°C 25°C 60°C 85°C UNIT

TYP MAX TYP MAX TYP MAX TYP MAX

ILPM2,XT12 Low-power mode 2, 12-pF

crystal(2) (3) (4) 2.2 V 0.8 1.2 3.1 8.8 μA

3.0 V 0.8 1.2 2.2 3.1 8.8 17

ILPM2,XT3.7 Low-power mode 2, 3.7-pF

crystal(2) (5) (4) 2.2 V 0.7 1.1 3.0 8.7 μA

3.0 V 0.7 1.1 3.0 8.7

ILPM2,VLO Low-power mode 2, VLO,

includes SVS(6) 2.2 V 0.5 0.9 2.8 8.5 μA

3.0 V 0.5 0.9 2.0 2.8 8.5 16.7

ILPM3,XT12 Low-power mode 3, 12-pF

crystal, includes SVS(2) (3) (7) 2.2 V 0.7 0.9 1.2 2.5 μA

3.0 V 0.7 0.9 1.2 1.2 2.5 6.4

ILPM3,XT3.7 Low-power mode 3, 3.7-pF

crystal, excludes SVS(2) (5) (8)

(also see Figure 5-2)

2.2 V 0.6 0.7 1.1 2.4 μA

3.0 V 0.6 0.7 1.1 2.4

ILPM3,VLO Low-power mode 3,

VLO, excludes SVS(9) 2.2 V 0.35 0.4 0.9 1.8 μA

3.0 V 0.35 0.4 0.8 0.9 1.8 6.1

ILPM3,VLO,

RAMoff

Low-power mode 3,

VLO, excludes SVS, RAM

powered down completely(10)

2.2 V 0.35 0.4 0.8 1.7 μA

3.0 V 0.35 0.4 0.7 0.8 1.7 5.2

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Low-Power Mode LPM2, LPM3, LPM4 Supply Currents (Into VCC) Excluding External

Current (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)

PARAMETER VCC –40°C 25°C 60°C 85°C UNIT

TYP MAX TYP MAX TYP MAX TYP MAX

(11) Low-power mode 4, includes SVS test conditions:

Current for brownout and SVS included (SVSHE = 1).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),

fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz

Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional

idle current. See the idle currents specified for the respective peripheral groups.

(12) Low-power mode 4, excludes SVS test conditions:

Current for brownout included. SVS disabled (SVSHE = 0).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),

fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz

Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional

idle current. See the idle currents specified for the respective peripheral groups.

(13) Low-power mode 4, excludes SVS, RAM powered down completely test conditions:

Current for brownout included. SVS disabled (SVSHE = 0). RAM disabled (RCCTL0 = 5A55h).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),

fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz

Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional

idle current. See the idle currents specified for the respective peripheral groups.

ILPM4,SVS Low-power mode 4, includes

SVS(11) 2.2 V 0.45 0.55 0.9 1.8 μA

3.0 V 0.45 0.55 0.8 0.9 1.8 6.2

ILPM4 Low-power mode 4, excludes

SVS(12) 2.2 V 0.25 0.4 0.7 1.6 μA

3.0 V 0.25 0.4 0.65 0.7 1.6 4.6

ILPM4,RAMoff Low-power mode 4, excludes

SVS, RAM powered down

completely(13)

2.2 V 0.25 0.4 0.7 1.4 μA

3.0 V 0.25 0.4 0.65 0.7 1.4 4.6

IIDLE,GroupA

Additional idle current if one or

more modules from Group A

(see Section 6.3.2) are

activated in LPM3 or LPM4

3.0 V 0.02 0.4 1.0 μA

IIDLE,GroupB

Additional idle current if one or

more modules from Group B

(see Section 6.3.2) are

activated in LPM3 or LPM4

3.0 V 0.02 0.4 1.0 μA

IIDLE,GroupC

Additional idle current if one or

more modules from Group C

(see Section 6.3.2) are

activated in LPM3 or LPM4

3.0 V 0.02 0.3 0.8 μA

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(1) Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled

(SVSHE = 0).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),

fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz

Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional

idle current (idle current of Group containing LCD module already included). See the idle currents specified for the respective peripheral

groups.

(2) LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump

disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)

Current through external resistors not included (voltage levels are supplied by test equipment).

Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.

(3) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump

disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)

Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.

(4) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump

enabled), VLCDx = 1000 (VLCD= 3 V typ.), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)

Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load. CLCDCAP = 10 µF

5.8 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER VCC

TEMPERATURE (TA)

UNIT–40°C 25°C 60°C 85°C

TYP MAX TYP MAX TYP MAX TYP MAX

ILPM3,XT12

LCD,

ext. bias

Low-power mode 3 (LPM3)

current,12-pF crystal, LCD 4-

mux mode, external biasing,

excludes SVS(1) (2) 3.0 V 0.8 1.0 1.5 3.1 µA

ILPM3,XT12

LCD,

int. bias

Low-power mode 3 (LPM3)

current, 12-pF crystal, LCD 4-

mux mode, internal biasing,

charge pump disabled,

excludes SVS(1) (3)

3.0 V 2.5 2.7 3.4 2.8 4.4 9.3 µA

ILPM3,XT12

LCD,CP

Low-power mode 3 (LPM3)

current,12-pF crystal, LCD 4-

mux mode, internal biasing,

charge pump enabled, 1/3 bias,

excludes SVS(1) (4)

2.2 V 6.2 6.4 7.0 8.0 µA

3.0 V 5.8 6.0 6.8 7.5 µA

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(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.

(2) Not applicable for devices with HF crystal oscillator only.

(3) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are

chosen to closely match the required 12.5 pF load.

(4) Low-power mode 3.5, 1-pF crystal including SVS test conditions:

Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz

(5) Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are

chosen to closely match the required 3.7-pF load.

(6) Low-power mode 3.5, 3.7-pF crystal excluding SVS test conditions:

Current for RTC clocked by XT1 included.Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz

(7) Low-power mode 4.5 including SVS test conditions:

Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz

(8) Low-power mode 4.5 excluding SVS test conditions:

Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz

5.9 Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)

PARAMETER VCC –40°C 25°C 60°C 85°C UNIT

TYP MAX TYP MAX TYP MAX TYP MAX

ILPM3.5,XT12 Low-power mode 3.5, 12-pF

crystal including SVS(2) (3) (4) 2.2 V 0.45 0.5 0.6 0.75 μA

3.0 V 0.45 0.5 0.75 0.6 0.75 1.4

ILPM3.5,XT3.7 Low-power mode 3.5, 3.7-pF

crystal excluding SVS(2) (5) (6) 2.2 V 0.3 0.35 0.4 0.65 μA

3.0 V 0.3 0.35 0.4 0.65

ILPM4.5,SVS Low-power mode 4.5, including

SVS(7) 2.2 V 0.2 0.3 0.35 0.4 μA

3.0 V 0.2 0.3 0.5 0.35 0.4 0.7

ILPM4.5 Low-power mode 4.5,

excluding SVS(8) 2.2 V 0.03 0.04 0.06 0.14 μA

3.0 V 0.03 0.04 0.06 0.14 0.5

0.2

0.3

0.4

0.5

0.6

0.7

-50.00 -25.00 0.00 25.00 50.00 75.00 100.00

LPM3.5 Supply Current [A]

Temperature [ƒC]

@ 3.0V, SVS off

@ 2.2V, SVS off

C003

0.00E+00

1.00E-01

2.00E-01

3.00E-01

4.00E-01

5.00E-01

6.00E-01

7.00E-01

-50 -25 0 25 50 75 100

LPM.54 Supply Current [A]

Temperature [ƒC]

@ 3.0V, SVS off

@ 2.2V, SVS off

@ 3.0V, SVS on

@ 2.2V, SVS on

C004

0.5

1.5

2.5

-50 -25 0 25 50 75 100

LPM3 Supply Current [A]

Temperature [ƒC]

@ 3.0V, SVS off

@ 2.2V, SVS off

@ 3.0V, SVS on

@ 2.2V, SVS on

C003

0.5

1.5

2.5

-50 -25 0 25 50 75 100

LPM4 Supply Current [A]

Temperature [ƒC]

@ 3.0V, SVS off

@ 2.2V, SVS off

@ 3.0V, SVS on

@ 2.2V, SVS on

C001

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5.10 Typical Characteristics, Low-Power Mode Supply Currents

Figure 5-2. LPM3 Supply Current vs Temperature (LPM3,XT3.7) Figure 5-3. LPM4 Supply Current vs Temperature (LPM4,SVS)

Figure 5-4. LPM3.5 Supply Current vs Temperature

(LPM3.5,XT3.7) Figure 5-5. LPM4.5 Supply Current vs Temperature (LPM4.5)

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(1) LCD_C: See Section 5.8. For other module currents not listed here, see the module specific parameter sections.

5.11 Typical Characteristics, Current Consumption per Module(1)

MODULE TEST CONDITIONS REFERENCE CLOCK MIN TYP MAX UNIT

Timer_A Module input clock 3 μA/MHz

Timer_B Module input clock 5 μA/MHz

eUSCI_A UART mode Module input clock 5.5 μA/MHz

eUSCI_A SPI mode Module input clock 3.5 μA/MHz

eUSCI_B SPI mode Module input clock 3.5 μA/MHz

eUSCI_B I2C mode, 100 kbaud Module input clock 3.5 μA/MHz

RTC_C 32 kHz 100 nA

MPY Only from start to end of operation MCLK 25 μA/MHz

AES Only from start to end of operation MCLK 21 μA/MHz

CRC16 Only from start to end of operation MCLK 2.5 μA/MHz

CRC32 Only from start to end of operation MCLK 2.5 μA/MHz

(1) N/A = not applicable

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

5.12 Thermal Resistance Characteristics(1)

PARAMETER PACKAGE VALUE(1) UNIT

θJA Junction-to-ambient thermal resistance, still air(2)

TSSOP-56 (DGG)

57.7 °C/W

θJC(TOP) Junction-to-case (top) thermal resistance(3) 15.1 °C/W

θJB Junction-to-board thermal resistance(4) 26.5 °C/W

ΨJB Junction-to-board thermal characterization parameter 26.2 °C/W

ΨJT Junction-to-top thermal characterization parameter 0.5 °C/W

θJC(BOTTOM) Junction-to-case (bottom) thermal resistance(5) N/A °C/W

θJA Junction-to-ambient thermal resistance, still air(2)

QFP-64 (PN)

59.3 °C/W

θJC(TOP) Junction-to-case (top) thermal resistance(3) 19.5 °C/W

θJB Junction-to-board thermal resistance(4) 30.8 °C/W

ΨJB Junction-to-board thermal characterization parameter 30.5 °C/W

ΨJT Junction-to-top thermal characterization parameter 1.0 °C/W

θJC(BOTTOM) Junction-to-case (bottom) thermal resistance(5) N/A °C/W

θJA Junction-to-ambient thermal resistance, still air(2)

QFN-64 (RGC)

29.6 °C/W

θJC(TOP) Junction-to-case (top) thermal resistance(3) 15.8 °C/W

θJB Junction-to-board thermal resistance(4) 8.5 °C/W

ΨJB Junction-to-board thermal characterization parameter 8.5 °C/W

ΨJT Junction-to-top thermal characterization parameter 0.2 °C/W

θJC(BOTTOM) Junction-to-case (bottom) thermal resistance(5) 1.2 °C/W

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5.13 Timing and Switching Characteristics

5.13.1 Power Supply Sequencing

TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up,

power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the

limits specified in Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the

device including erroneous writes to RAM and FRAM.

Table 5-1 lists the reset power ramp requirements.

(1) Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR

resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation for

capacitor CDVCC should limit the slopes accordingly.

(2) The brownout levels are measured with a slowly changing supply.

Table 5-1. Brownout and Device Reset Power Ramp Requirements

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

VVCC_BOR– Brownout power-down level(1) | dDVCC/dt| < 3 V/s(2) 0.73 1.66 V

VVCC_BOR+ Brownout power-up level(1) | dDVCC/dt| < 3 V/s(2) 0.79 1.68 V

Table 5-2 lists the characteristics of the SVS.

(1) For additional information, see the Dynamic Voltage Scaling Power Solution for MSP430 Devices With Single-Channel LDO Reference

Design.

Table 5-2. SVS

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ISVSH,LPM SVSHcurrent consumption, low power modes 170 300 nA

VSVSH- SVSHpower-down level(1) 1.75 1.80 1.85 V

VSVSH+ SVSHpower-up level(1) 1.77 1.88 1.99 V

VSVSH_hys SVSHhysteresis 40 120 mV

tPD,SVSH, AM SVSHpropagation delay, active mode dVVcc/dt = –10 mV/µs 10 µs

5.13.2 Reset Timing

Table 5-11 lists the required reset input timing.

(1) Not applicable if the RST/NMI pin is configured as NMI.

Table 5-3. Reset Input

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER VCC MIN MAX UNIT

t(RST) External reset pulse duration on RST(1) 2.2 V, 3.0 V 2 µs

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5.13.3 Clock Specifications

Table 5-4 lists the characteristics of the LFXT.

(1) To improve EMI on the LFXT oscillator, the following guidelines should be observed.

• Keep the trace between the device and the crystal as short as possible.

• Design a good ground plane around the oscillator pins.

• Prevent crosstalk from other clock or data lines into oscillator pins LFXIN and LFXOUT.

• Avoid running PCB traces underneath or adjacent to the LFXIN and LFXOUT pins.

• Use assembly materials and processes that avoid any parasitic load on the oscillator LFXIN and LFXOUT pins.

• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.

(2) When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics

defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW.

(3) Maximum frequency of operation of the entire device cannot be exceeded.

(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the

LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following

guidelines, but should be evaluated based on the actual crystal selected for the application:

• For LFXTDRIVE = {0}, CL,eff = 3.7 pF

• For LFXTDRIVE = {1}, CL,eff = 6 pF

• For LFXTDRIVE = {2}, 6 pF ≤CL,eff ≤9 pF

• For LFXTDRIVE = {3}, 9 pF ≤CL,eff ≤12.5 pF

(5) This represents all the parasitic capacitance present at the LFXIN and LFXOUT terminals, respectively, including parasitic bond and

package capacitance. The effective load capacitance, CL,eff can be computed as CIN x COUT / (CIN + COUT), where CIN and COUT is the

total capacitance at the LFXIN and LFXOUT terminals, respectively.

(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Recommended values supported are 3.7

pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF. The PCB adds additional capacitance, so it must also be

considered in the overall capacitance. Verify that the recommended effective load capacitance of the selected crystal is met.

Table 5-4. Low-Frequency Crystal Oscillator, LFXT(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

IVCC.LFXT Current consumption

fOSC = 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {0},

TA= 25°C, CL,eff = 3.7 pF, ESR ≈44 kΩ

3.0 V

180

fOSC = 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {1},

TA= 25°C, CL,eff = 6 pF, ESR ≈40 kΩ185

fOSC = 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {2},

TA= 25°C, CL,eff = 9 pF, ESR ≈40 kΩ225

fOSC = 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {3},

TA= 25°C, CL,eff = 12.5 pF, ESR ≈

40 kΩ

330

fLFXT LFXT oscillator crystal

frequency LFXTBYPASS = 0 32768 Hz

DCLFXT LFXT oscillator duty cycle Measured at ACLK,

fLFXT = 32768 Hz 30% 70%

fLFXT,SW LFXT oscillator logic-level

square-wave input frequency LFXTBYPASS = 1(2) (3) 10.5 32.768 50 kHz

DCLFXT, SW LFXT oscillator logic-level

square-wave input duty cycle LFXTBYPASS = 1 30% 70%

OALFXT Oscillation allowance for

LF crystals(4)

LFXTBYPASS = 0, LFXTDRIVE = {1},

fLFXT = 32768 Hz, CL,eff = 6 pF 210 kΩ

LFXTBYPASS = 0, LFXTDRIVE = {3},

fLFXT = 32768 Hz, CL,eff = 12.5 pF 300

CLFXIN Integrated load capacitance at

LFXIN terminal(5) (6) 2 pF

CLFXOUT Integrated load capacitance at

LFXOUT terminal(5) (6) 2 pF

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Table 5-4. Low-Frequency Crystal Oscillator, LFXT(1) (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

(7) Includes start-up counter of 1024 clock cycles.

(8) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specification may set the

flag. A static condition or stuck at fault condition will set the flag.

(9) Measured with logic-level input frequency but also applies to operation with crystals.

tSTART,LFXT Start-up time(7)

fOSC = 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {0},

TA= 25°C, CL,eff = 3.7 pF 3.0 V 800

fOSC = 32768 Hz

LFXTBYPASS = 0, LFXTDRIVE = {3},

TA= 25°C, CL,eff = 12.5 pF 3.0 V 1000

fFault,LFXT Oscillator fault frequency(8) (9) 0 3500 Hz

Table 5-5 lists the characteristics of the HFXT.

(1) To improve EMI on the HFXT oscillator the following guidelines should be observed.

• Keep the traces between the device and the crystal as short as possible.

• Design a good ground plane around the oscillator pins.

• Prevent crosstalk from other clock or data lines into oscillator pins HFXIN and HFXOUT.

• Avoid running PCB traces underneath or adjacent to the HFXIN and HFXOUT pins.

• Use assembly materials and processes that avoid any parasitic load on the oscillator HFXIN and HFXOUT pins.

• If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

(2) HFFREQ = {0} is not supported for HFXT crystal mode of operation.

(3) Maximum frequency of operation of the entire device cannot be exceeded.

Table 5-5. High-Frequency Crystal Oscillator, HFXT(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

IDVCC.HFXT HFXT oscillator crystal current HF

mode at typical ESR

fOSC = 4 MHz,

HFXTBYPASS = 0, HFXTDRIVE = 0,

HFFREQ = 1(2),

TA= 25°C,

CL,eff = 18 pF, typical ESR, Cshunt

3.0 V

μA

fOSC = 8 MHz,

HFXTBYPASS = 0, HFXTDRIVE = 1,

HFFREQ = 1

TA= 25°C,

CL,eff = 18 pF, typical ESR, Cshunt

120

fOSC = 16 MHz,

HFXTBYPASS = 0, HFXTDRIVE = 2,

HFFREQ = 2,

TA= 25°C,

CL,eff = 18 pF, typical ESR, Cshunt

190

fOSC = 24 MHz

HFXTBYPASS = 0, HFXTDRIVE = 3,

HFFREQ = 3,

TA= 25°C,

CL,eff = 18 pF, typical ESR, Cshunt

250

fHFXT HFXT oscillator crystal frequency,

crystal mode

HFXTBYPASS = 0, HFFREQ = 1 (2)

(3) 4 8 MHz

HFXTBYPASS = 0, HFFREQ = 2 (3) 8.01 16

HFXTBYPASS = 0, HFFREQ = 3 (3) 16.01 24

DCHFXT HFXT oscillator duty cycle Measured at SMCLK,

fHFXT = 16 MHz 40% 50% 60%

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Table 5-5. High-Frequency Crystal Oscillator, HFXT(1) (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

(4) When HFXTBYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics

defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCHFXT, SW.

(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.

(6) Includes start-up counter of 1024 clock cycles.

(7) This represents all the parasitic capacitance present at the HFXIN and HFXOUT terminals, respectively, including parasitic bond and

package capacitance. The effective load capacitance, CL,eff can be computed as CIN x COUT / (CIN + COUT), where CIN and COUT is the

total capacitance at the HFXIN and HFXOUT terminals, respectively.

(8) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Recommended values supported are

14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF. The PCB adds additional capacitance, so it must also be considered in

the overall capacitance. Verify that the recommended effective load capacitance of the selected crystal is met.

(9) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX might set the flag. A static

condition or stuck at fault condition will set the flag.

(10) Measured with logic-level input frequency but also applies to operation with crystals.

fHFXT,SW HFXT oscillator logic-level

square-wave input frequency,

bypass mode

HFXTBYPASS = 1, HFFREQ = 0(4)

(3) 0.9 4

MHz

HFXTBYPASS = 1, HFFREQ = 1(4)

(3) 4.01 8

HFXTBYPASS = 1, HFFREQ = 2(4)

(3) 8.01 16

HFXTBYPASS = 1, HFFREQ = 3(4)

(3) 16.01 24

DCHFXT,

SW HFXT oscillator logic-level

square-wave input duty cycle HFXTBYPASS = 1 40% 60%

OAHFXT Oscillation allowance for

HFXT crystals(5)

HFXTBYPASS = 0,

HFXTDRIVE = 0, HFFREQ = 1(2),

fHFXT,HF = 4 MHz, CL,eff = 16 pF 450

Ω

HFXTBYPASS = 0,

HFXTDRIVE = 1, HFFREQ = 1,

fHFXT,HF = 8 MHz, CL,eff = 16 pF 320

HFXTBYPASS = 0,

HFXTDRIVE = 2, HFFREQ = 2,

fHFXT,HF = 16 MHz, CL,eff = 16 pF 200

HFXTBYPASS = 0,

HFXTDRIVE = 3, HFFREQ = 3,

fHFXT,HF = 24 MHz, CL,eff = 16 pF 200

tSTART,HFXT Start-up time(6)

fOSC = 4 MHz,

HFXTBYPASS = 0, HFXTDRIVE = 0,

HFFREQ = 1,

TA= 25°C, CL,eff = 16 pF 3.0 V 1.6

fOSC = 24 MHz,

HFXTBYPASS = 0, HFXTDRIVE = 3,

HFFREQ = 3,

TA= 25°C, CL,eff = 16 pF 3.0 V 0.6

CHFXIN Integrated load capacitance at

HFXIN terminaI(7) (8) 2 pF

CHFXOUT Integrated load capacitance at

HFXOUT terminaI(7) (8) 2 pF

fFault,HFXT Oscillator fault frequency(9) (10) 0 800 kHz

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Table 5-6 lists the characteristics of the DCO.

(1) After a wakeup from LPM1, LPM2, LPM3 or LPM4, the DCO frequency fDCO might exceed the specified frequency range for a few

clocks cycles by up to 5% before settling into the specified steady state frequency range.

(2) Calculated using the box method: (MAX(–40°C to 85ºC) – MIN(–40°C to 85ºC)) / MIN(–40°C to 85ºC) / (85ºC – (–40ºC))

Table 5-6. DCO

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

fDCO1 DCO frequency range 1 MHz,

trimmed Measured at SMCLK, divide by 1,

DCORSEL = 0, DCOFSEL = 0

DCORSEL = 1, DCOFSEL = 0 1 ±3.5% MHz

fDCO2.7 DCO frequency range 2.7 MHz,

trimmed Measured at SMCLK, divide by 1,

DCORSEL = 0, DCOFSEL = 1 2.667 ±3.5% MHz

fDCO3.5 DCO frequency range 3.5 MHz,

trimmed Measured at SMCLK, divide by 1,

DCORSEL = 0, DCOFSEL = 2 3.5 ±3.5% MHz

fDCO4 DCO frequency range 4 MHz,

trimmed Measured at SMCLK, divide by 1,

DCORSEL = 0, DCOFSEL = 3 4 ±3.5% MHz

fDCO5.3 DCO frequency range 5.3 MHz,

trimmed Measured at SMCLK, divide by 1,

DCORSEL = 0, DCOFSEL = 4

DCORSEL = 1, DCOFSEL = 1 5.333 ±3.5% MHz

fDCO7 DCO frequency range 7 MHz,

trimmed Measured at SMCLK, divide by 1,

DCORSEL = 0, DCOFSEL = 5

DCORSEL = 1, DCOFSEL = 2 7 ±3.5% MHz

fDCO8 DCO frequency range 8 MHz,

trimmed Measured at SMCLK, divide by 1,

DCORSEL = 0, DCOFSEL = 6

DCORSEL = 1, DCOFSEL = 3 8 ±3.5% MHz

fDCO16 DCO frequency range 16 MHz,

trimmed Measured at SMCLK, divide by 1,

DCORSEL = 1, DCOFSEL = 4 16 ±3.5%(1) MHz

fDCO21 DCO frequency range 21 MHz,

trimmed Measured at SMCLK, divide by 2,

DCORSEL = 1, DCOFSEL = 5 21 ±3.5%(1) MHz

fDCO24 DCO frequency range 24 MHz,

trimmed Measured at SMCLK, divide by 2,

DCORSEL = 1, DCOFSEL = 6 24 ±3.5%(1) MHz

fDCO,DC Duty cycle

Measured at SMCLK, divide by 1,

No external divide, all DCORSEL and

DCOFSEL settings except DCORSEL

= 1, DCOFSEL = 5 and DCORSEL =

1, DCOFSEL = 6

48% 50% 52%

tDCO,

JITTER DCO jitter

Based on fsignal = 10 kHz and DCO

used for 12-bit SAR ADC sampling

source. This achieves >74-dB SNR

due to jitter; that is, it is limited by

ADC performance.

2 3 ns

dfDCO/dT DCO temperature drift(2) 3.0 V 0.01 %/ºC

Table 5-7 lists the characteristics of the VLO.

(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))

(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

Table 5-7. Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

IVLO Current consumption 100 nA

fVLO VLO frequency Measured at ACLK 6 9.4 14 kHz

dfVLO/dTVLO frequency temperature drift Measured at ACLK(1) 0.2 %/°C

dfVLO/dVCC VLO frequency supply voltage drift Measured at ACLK(2) 0.7 %/V

fVLO,DC Duty cycle Measured at ACLK 40% 50% 60%

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Table 5-8 lists the characteristics of the MODOSC.

(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))

(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

Table 5-8. Module Oscillator (MODOSC)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IMODOSC Current consumption Enabled 25 μA

fMODOSC MODOSC frequency 4.0 4.8 5.4 MHz

fMODOSC/dT MODOSC frequency temperature drift(1) 0.08 %/℃

fMODOSC/dVCC MODOSC frequency supply voltage

drift(2) 1.4 %/V

DCMODOSC Duty cycle Measured at SMCLK, divide by 1 40% 50% 60%

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MSP430FR6922

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5.13.4 Wake-up Characteristics

Table 5-9 lists the device wake-up times.

(1) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first

externally observable MCLK clock edge with MCLKREQEN = 1. This time includes the activation of the FRAM during wakeup.

(2) With MCLKREQEN = 0, the MCLK is gated one additoinal one clock cycle (wake from LPM0, LPM1, LPM2, LPM3, and LPM4). The

device wake-up time is not affected by the status of the MCLKREQEN bit.

(3) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first

instruction of the user program is executed.

Table 5-9. Wake-up Times From Low-Power Modes and Reset

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST

CONDITIONS VCC MIN TYP MAX UNIT

tWAKE-UP FRAM

Additional wake-up time to activate the FRAM

in AM if previously disabled by the FRAM

controller or from an LPM if immediate

activation is selected 6 10 μs

tWAKE-UP LPM0 Wake-up time from LPM0 to active mode

MCLKREQEN = 1

(1) 2.2 V, 3.0 V 400 ns +

1.5 / fDCO

MCLKREQEN = 0

(1)(2) 2.2 V, 3.0 V 400 ns +

2.5 / fDCO

tWAKE-UP LPM1 Wake-up time from LPM1 to active mode(1) 2.2 V, 3.0 V 6 μs

tWAKE-UP LPM2 Wake-up time from LPM2 to active mode(1) 2.2 V, 3.0 V 6 μs

tWAKE-UP LPM3 Wake-up time from LPM3 to active mode(1) 2.2 V, 3.0 V 7 10 μs

tWAKE-UP LPM4 Wake-up time from LPM4 to active mode(1) 2.2 V, 3.0 V 7 10 μs

tWAKE-UP LPM3.5 Wake-up time from LPM3.5 to active mode(3) 2.2 V, 3.0 V 250 350 μs

tWAKE-UP LPM4.5 Wake-up time from LPM4.5 to active mode(3) SVSHE = 1 2.2 V, 3.0 V 250 350 μs

SVSHE = 0 2.2 V, 3.0 V 0.4 0.8 ms

tWAKE-UP-RST Wake-up time from a RST pin triggered reset to

active mode(3) 2.2 V, 3.0 V 250 350 μs

tWAKE-UP-BOR Wake-up time from power-up to active mode (3) 2.2 V, 3.0 V 0.5 1.0 ms

Table 5-10 lists the typical charge required for wakeup.

(1) Charge used during the wake-up time from a given low-power mode to active mode. This does not include the energy required in active

mode (for example, for an interrupt service routine).

(2) Charge required until start of user code. This does not include the energy required to reconfigure the device.

Table 5-10. Typical Wake-up Charge(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

QWAKE-UP FRAM Charge used for activating the FRAM in AM or during wakeup

from LPM0 if previously disabled by the FRAM controller. 15.1 nAs

QWAKE-UP LPM0 Charge used to wake up from LPM0 to active mode (with FRAM

active) 4.4 nAs

QWAKE-UP LPM1 Charge used to wake up from LPM1 to active mode (with FRAM

active) 15.1 nAs

QWAKE-UP LPM2 Charge used to wake up from LPM2 to active mode (with FRAM

active) 15.3 nAs

QWAKE-UP LPM3 Charge used to wake up from LPM3 to active mode (with FRAM

active) 16.5 nAs

QWAKE-UP LPM4 Charge used to wake up from LPM4 to active mode (with FRAM

active) 16.5 nAs

QWAKE-UP LPM3.5 Charge used to wake up from LPM3.5 to active mode(2) 76 nAs

QWAKE-UP LPM4.5 Charge used to wake up from LPM4.5 to active mode(2) SVSHE = 1 77 nAs

SVSHE = 0 77.5

QWAKE-UP-RESET Charge used for reset from RST or BOR event to active mode(2) 75 nAs

0.10

1.00

10.00

100.00

1000.00

10000.00

0.001 0.01 0.1 1 10 100 1000 10000 100000

Average Wake-up Current (µA)

Wake-up Frequency (Hz)

LPM0

LPM1

LPM2,XT12

LPM3,XT12

LPM3.5,XT12

0.10

1.00

10.00

100.00

1000.00

10000.00

0.001 0.01 0.1 1 10 100 1000 10000 100000

Average Wake-up Current (µA)

Wake-up Frequency (Hz)

LPM0

LPM1

LPM2,XT12

LPM3,XT12

LPM3.5,XT12

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5.13.4.1 Typical Characteristics, Average LPM Currents vs Wake-up Frequency

NOTE: The average wake-up current does not include the energy required in active mode; for example, for an interrupt

service routine or to reconfigure the device.

Figure 5-6. Average LPM Currents vs Wake-up Frequency at 25°C

NOTE: The average wake-up current does not include the energy required in active mode; for example, for an interrupt

service routine or to reconfigure the device.

Figure 5-7. Average LPM Currents vs Wake-up Frequency at 85°C

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5.13.5 Digital I/Os

Table 5-11 lists the characteristics of the digital inputs.

(1) If the port pins PJ.4/LFXIN and PJ.5/LFXOUT are used as digital I/Os, they are connected by a 4-pF capacitor and a 35-MΩresistor in

series. At frequencies of approximately 1 kHz and lower, the 4-pF capacitor can add to the pin capacitance of PJ.4/LFXIN and

PJ.5/LFXOUT.

(2) The input leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.

(3) The input leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is

disabled.

(4) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals

shorter than t(int).

(5) Not applicable if the RST/NMI pin is configured as NMI.

Table 5-11. Digital Inputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

VIT+ Positive-going input threshold voltage 2.2 V 1.2 1.65 V

3.0 V 1.65 2.25

VIT– Negative-going input threshold voltage 2.2 V 0.55 1.00 V

3.0 V 0.75 1.35

Vhys Input voltage hysteresis (VIT+ – VIT–)2.2 V 0.44 0.98 V

3.0 V 0.60 1.30

RPull Pullup or pulldown resistor For pullup: VIN = VSS

For pulldown: VIN = VCC 20 35 50 kΩ

CI,dig Input capacitance, digital only port pins VIN = VSS or VCC 3 pF

CI,ana Input capacitance, port pins with shared analog

functions(1) VIN = VSS or VCC 5 pF

Ilkg(Px.y) High-impedance input leakage current See (2)(3) 2.2 V,

3.0 V –20 +20 nA

t(int) External interrupt timing (external trigger pulse

duration to set interrupt flag)(4)

Ports with interrupt capability

(see block diagram and

terminal function

descriptions).

2.2 V,

3.0 V 20 ns

t(RST) External reset pulse duration on RST(5) 2.2 V,

3.0 V 2 µs

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MSP430FR69721

MSP430FR6970

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MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

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Table 5-12 lists the characteristics of the digital outputs.

(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop

specified.

(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage

drop specified.

(3) The port can output frequencies at least up to the specified limit. It might support higher frequencies.

(4) A resistive divider with 2 × R1 and R1 = 1.6 kΩbetween VCC and VSS is used as load. The output is connected to the center tap of the

divider. CL= 20 pF is connected from the output to VSS.

(5) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.

Table 5-12. Digital Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

VOH High-level output voltage

I(OHmax) = –1 mA(1)

2.2 V

VCC –

0.25 VCC

I(OHmax) = –3 mA(2) VCC –

0.60 VCC

I(OHmax) = –2 mA(1)

3.0 V

VCC –

0.25 VCC

I(OHmax) = –6 mA(2) VCC –

0.60 VCC

VOL Low-level output voltage

I(OLmax) = 1 mA(1)

2.2 V VSS VSS +

0.25

I(OLmax) = 3 mA(2) VSS VSS +

0.60

I(OLmax) = 2 mA(1)

3.0 V VSS VSS +

0.25

I(OLmax) = 6 mA(2) VSS VSS +

0.60

fPx.y Port output frequency (with load)(3) CL= 20 pF, RL(4) (5) 2.2 V 16 MHz

3.0 V 16

fPort_CLK Clock output frequency(3) ACLK, MCLK, or SMCLK at

configured output port

CL= 20 pF(5)

2.2 V 16 MHz

3.0 V 16

trise,dig Port output rise time, digital only port pins CL= 20 pF 2.2 V 4 15 ns

3.0 V 3 15

tfall,dig Port output fall time, digital only port pins CL= 20 pF 2.2 V 4 15 ns

3.0 V 3 15

trise,ana Port output rise time, port pins with shared

analog functions CL= 20 pF 2.2 V 6 15 ns

3.0 V 4 15

tfall,ana Port output fall time, port pins with shared

analog functions CL= 20 pF 2.2 V 6 15 ns

3.0 V 4 15

-15

-10

-5

0 0.5 1 1.5 2

High-Level Output Current (mA)

High-Level Output Voltage (V)

25°C

85°C

C001

P1.1

-30

-20

-10

0 0.5 1 1.5 2 2.5 3

High-Level Output Current (mA)

High-Level Output Voltage (V)

25°C

85°C

C001

P1.1

0 0.5 1 1.5 2

Low-Level Output Current (mA)

Low-Level Output Voltage (V)

25°C

85°C

C001

P1.1

0 0.5 1 1.5 2 2.5 3

Low-Level Output Current (mA)

Low-Level Output Voltage (V)

25°C

85°C

C001

P1.1

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5.13.5.1 Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V

VCC = 2.2 V

Figure 5-8. Typical Low-Level Output Current vs Low-Level

Output Voltage

VCC = 3.0 V

Figure 5-9. Typical Low-Level Output Current vs Low-Level

Output Voltage

VCC = 2.2 V

Figure 5-10. Typical High-Level Output Current vs High-Level

Output Voltage

VCC = 3.0 V

Figure 5-11. Typical High-Level Output Current vs High-Level

Output Voltage

100

1000

10 100

Pin Oscillator Frequency [kHz]

External Load Capacitance (incl. board etc.) [pF]

fitted

25°C

85°C

C002

100

1000

10 100

Pin Oscillator Frequency [kHz]

External Load Capacitance (incl. board etc.) [pF]

fitted

25°C

85°C

C002

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Table 5-13 lists the characteristics of the pin oscillator.

(1) CLis the external load capacitance connected from the output to VSS and includes all parasitic effects such as PCB traces.

Table 5-13. Pin-Oscillator Frequency, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

foPx.y Pin-oscillator frequency Px.y, CL= 10 pF(1) 3.0 V 1200 kHz

Px.y, CL= 20 pF(1) 3.0 V 650 kHz

5.13.5.2 Typical Characteristics, Pin-Oscillator Frequency

VCC = 2.2 V One output active at a time.

Figure 5-12. Typical Oscillation Frequency vs Load Capacitance

VCC = 3.0 V One output active at a time.

Figure 5-13. Typical Oscillation Frequency vs Load Capacitance

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5.13.6 Timer_A and Timer_B

Table 5-14 lists the characteristics of the Timer_A.

Table 5-14. Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

fTA Timer_A input clock frequency Internal: SMCLK or ACLK,

External: TACLK,

Duty cycle = 50% ±10% 2.2 V,

3.0 V 16 MHz

tTA,cap Timer_A capture timing All capture inputs, minimum pulse

duration required for capture 2.2 V,

3.0 V 20 ns

Table 5-15 lists the characteristics of the Timer_B.

Table 5-15. Timer_B

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

fTB Timer_B input clock frequency Internal: SMCLK or ACLK,

External: TBCLK,

Duty cycle = 50% ±10% 2.2 V,

3.0 V 16 MHz

tTB,cap Timer_B capture timing All capture inputs, minimum pulse

duration required for capture 2.2 V,

3.0 V 20 ns

5.13.7 eUSCI

Table 5-16 lists the supported clock frequencies for the eUSCI in UART mode.

Table 5-16. eUSCI (UART Mode) Clock Frequency

PARAMETER CONDITIONS VCC MIN MAX UNIT

feUSCI eUSCI input clock frequency Internal: SMCLK, ACLK

External: UCLK

Duty cycle = 50% ±10% 16 MHz

fBITCLK BITCLK clock frequency

(equals baud rate in MBaud) 4 MHz

Table 5-17 lists the characteristics of the eUSCI in UART mode.

(1) Pulses on the UART receive input (UCxRX) that are shorter than the UART receive deglitch time are suppressed. Thus the selected

deglitch time can limit the maximum usable baud rate. To make sure that pulses are correctly recognized, their duration should exceed

the maximum specification of the deglitch time.

Table 5-17. eUSCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

ttUART receive deglitch time(1)

UCGLITx = 0

2.2 V,

3.0 V

5 30

UCGLITx = 1 20 90

UCGLITx = 2 35 160

UCGLITx = 3 50 220

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Table 5-18 lists the supported clock frequencies for the eUSCI in SPI master mode.

Table 5-18. eUSCI (SPI Master Mode) Clock Frequency

PARAMETER CONDITIONS VCC MIN MAX UNIT

feUSCI eUSCI input clock frequency Internal: SMCLK, ACLK

Duty cycle = 50% ±10% 16 MHz

Table 5-19 lists the characteristics of the eUSCI in SPI master mode.

(1) fUCxCLK = 1 / 2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).

For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams

in Figure 5-14 and Figure 5-15.

(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data

on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-

14 and Figure 5-15.

Table 5-19. eUSCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

tSTE,LEAD STE lead time, STE active to clock UCSTEM = 1, UCMODEx = 01 or 10 1 UCxCLK

cycles

tSTE,LAG STE lag time, last clock to STE

inactive UCSTEM = 1, UCMODEx = 01 or 10 1

tSTE,ACC STE access time, STE active to

SIMO data out UCSTEM = 0, UCMODEx = 01 or 10 2.2 V,

3.0 V 60 ns

tSTE,DIS STE disable time, STE inactive to

SOMI high impedance UCSTEM = 0, UCMODEx = 01 or 10 2.2 V,

3.0 V 80 ns

tSU,MI SOMI input data setup time 2.2 V 40 ns

3.0 V 40

tHD,MI SOMI input data hold time 2.2 V 0 ns

3.0 V 0

tVALID,MO SIMO output data valid time(2) UCLK edge to SIMO valid,

CL= 20 pF 2.2 V 10 ns

3.0 V 10

tHD,MO SIMO output data hold time(3) CL= 20 pF 2.2 V 0 ns

3.0 V 0

tSU,MI

tHD,MI

UCLK

SOMI

SIMO

tVALID,MO

CKPL = 0

CKPL = 1

tLOW/HIGH tLOW/HIGH

1/fUCxCLK

tSTE,LEAD tSTE,LAG

tSTE,ACC

UCMODEx = 01

UCMODEx = 10

STE

tHD,MO

tSTE,DIS

tSU,MI

tHD,MI

UCLK

SOMI

SIMO

tVALID,MO

CKPL = 0

CKPL = 1

tLOW/HIGH tLOW/HIGH

1/fUCxCLK

STE tSTE,LEAD tSTE,LAG

UCMODEx = 01

UCMODEx = 10

tHD,MO

tSTE,ACC tSTE,DIS

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Figure 5-14. SPI Master Mode, CKPH = 0

Figure 5-15. SPI Master Mode, CKPH = 1

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Table 5-20 lists the characteristics of the eUSCI in SPI slave mode.

(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)).

For the master parameters tSU,MI(Master) and tVALID,MO(Master) see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams

in Figure 5-16 and Figure 5-17.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-16

and Figure 5-17.

Table 5-20. eUSCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

tSTE,LEAD STE lead time, STE active to clock 2.2 V 50 ns

3.0 V 40

tSTE,LAG STE lag time, last clock to STE inactive 2.2 V 2 ns

3.0 V 3

tSTE,ACC STE access time, STE active to SOMI data out 2.2 V 50 ns

3.0 V 40

tSTE,DIS STE disable time, STE inactive to SOMI high

impedance 2.2 V 50 ns

3.0 V 45

tSU,SI SIMO input data setup time 2.2 V 4 ns

3.0 V 4

tHD,SI SIMO input data hold time 2.2 V 7 ns

3.0 V 7

tVALID,SO SOMI output data valid time(2) UCLK edge to SOMI valid,

CL= 20 pF 2.2 V 35 ns

3.0 V 35

tHD,SO SOMI output data hold time(3) CL= 20 pF 2.2 V 0 ns

3.0 V 0

UCLK

CKPL = 0

CKPL = 1

SOMI

SIMO

tSU,SI

tHD,SI

tVALID,SO

tHD,SO

tLOW/HIGH

1/fUCxCLK

tLOW/HIGH

tSTE,DIS

tSTE,ACC

STE tSTE,LEAD tSTE,LAG

UCMODEx = 01

UCMODEx = 10

UCLK

CKPL = 0

CKPL = 1

SOMI

SIMO

tSU,SI

tHD,SI

tVALID,SO

tLOW/HIGH

1/fUCxCLK

tLOW/HIGH

tSTE,DIS

tSTE,ACC

STE tSTE,LEAD tSTE,LAG

UCMODEx = 01

UCMODEx = 10

tHD,SO

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Figure 5-16. SPI Slave Mode, CKPH = 0

Figure 5-17. SPI Slave Mode, CKPH = 1

SDA

SCL

tHD,DAT

tSU,DAT

tHD,STA

tHIGH

tLOW

tBUF

tHD,STA

tSU,STA

tSP

tSU,STO

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Table 5-21 lists the characteristics of the eUSCI in I2C mode.

Table 5-21. eUSCI (I2C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-18)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

feUSCI eUSCI input clock frequency Internal: SMCLK, ACLK

External: UCLK

Duty cycle = 50% ±10% 16 MHz

fSCL SCL clock frequency 2.2 V, 3.0 V 0 400 kHz

tHD,STA Hold time (repeated) START fSCL = 100 kHz 2.2 V, 3.0 V 4.0 µs

fSCL > 100 kHz 0.6

tSU,STA Setup time for a repeated START fSCL = 100 kHz 2.2 V, 3.0 V 4.7 µs

fSCL > 100 kHz 0.6

tHD,DAT Data hold time 2.2 V, 3.0 V 0 ns

tSU,DAT Data setup time 2.2 V, 3.0 V 100 ns

tSU,STO Setup time for STOP fSCL = 100 kHz 2.2 V, 3.0 V 4.0 µs

fSCL > 100 kHz 0.6

tBUF Bus free time between a STOP and

START condition fSCL = 100 kHz 4.7 us

fSCL > 100 kHz 1.3

tSP Pulse duration of spikes suppressed by

input filter

UCGLITx = 0

2.2 V, 3.0 V

50 250

UCGLITx = 1 25 125

UCGLITx = 2 12.5 62.5

UCGLITx = 3 6.3 31.5

tTIMEOUT Clock low time-out UCCLTOx = 1 2.2 V, 3.0 V 27 msUCCLTOx = 2 30

UCCLTOx = 3 33

Figure 5-18. I2C Mode Timing

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5.13.8 Segment LCD Controller

Table 5-22 lists the operating conditions of the LCD.

Table 5-22. LCD_C Recommended Operating Conditions

PARAMETER CONDITIONS MIN NOM MAX UNIT

VCC,LCD_C,CP en,3.6 Supply voltage range, charge

pump enabled, VLCD ≤3.6 V LCDCPEN = 1, 0000b < VLCDx ≤1111b

(charge pump enabled, VLCD ≤3.6 V) 2.2 3.6 V

VCC,LCD_C,CP en,3.3 Supply voltage range, charge

pump enabled, VLCD ≤3.3 V LCDCPEN = 1, 0000b < VLCDx ≤1100b

(charge pump enabled, VLCD ≤3.3 V) 2.0 3.6 V

VCC,LCD_C,int. bias Supply voltage range, internal

biasing, charge pump disabled LCDCPEN = 0, VLCDEXT = 0 2.4 3.6 V

VCC,LCD_C,ext. bias Supply voltage range, external

biasing, charge pump disabled LCDCPEN = 0, VLCDEXT = 0 2.4 3.6 V

VCC,LCD_C,VLCDEXT Supply voltage range, external

LCD voltage, internal or external

biasing, charge pump disabled LCDCPEN = 0, VLCDEXT = 1 2.0 3.6 V

VLCDCAP External LCD voltage at

LCDCAP, internal or external

biasing, charge pump disabled LCDCPEN = 0, VLCDEXT = 1 2.4 3.6 V

CLCDCAP Capacitor value on LCDCAP

when charge pump enabled LCDCPEN = 1, VLCDx > 0000b (charge

pump enabled) 4.7–20% 4.7 10+20% µF

fACLK,in ACLK input frequency range 30 32.768 40 kHz

fLCD LCD frequency range fFRAME = (1 / (2 × mux)) × fLCD with mux

= 1 (static) to 8 0 1024 Hz

fFRAME,4mux LCD frame frequency range fFRAME,4mux(MAX) = (1 / (2 × 4)) ×

fLCD(MAX)

= (1 / (2 × 4)) × 1024 Hz 128 Hz

CPanel Panel capacitance fLCD = 1024 Hz,

all common lines equally loaded 10000 pF

VR33 Analog input voltage at R33 LCDCPEN = 0, VLCDEXT = 1 2.4 VCC + 0.2 V

VR23,1/3bias Analog input voltage at R23 LCDREXT = 1, LCDEXTBIAS = 1,

LCD2B = 0 VR13

VR03 +

2/3 ×

(VR33 –

VR03)VR33 V

VR13,1/3bias Analog input voltage at R13 with

1/3 biasing LCDREXT = 1, LCDEXTBIAS = 1,

LCD2B = 0 VR03

VR03 +

1/3 ×

(VR33 –

VR03)VR23 V

VR13,1/2bias Analog input voltage at R13 with

1/2 biasing LCDREXT = 1, LCDEXTBIAS = 1,

LCD2B = 1 VR03

VR03 +

1/2 ×

(VR33 –

VR03)VR33 V

VR03 Analog input voltage at R03 R0EXT = 1 VSS V

VLCD-VR03 Voltage difference between

VLCD and R03 LCDCPEN = 0, R0EXT = 1 2.4 VCC + 0.2 V

VLCDREF External LCD reference voltage

applied at LCDREF VLCDREFx = 01 0.8 1.0 1.2 V

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Table 5-23 lists the characteristics of the LCD.

Table 5-23. LCD_C Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

VLCD,0

LCD voltage

VLCDx = 0000, VLCDEXT = 0 2.4 V to 3.6 V VCC

VLCD,1 LCDCPEN = 1, VLCDx = 0001b 2 V to 3.6 V 2.49 2.60 2.72

VLCD,2 LCDCPEN = 1, VLCDx = 0010b 2 V to 3.6 V 2.66

VLCD,3 LCDCPEN = 1, VLCDx = 0011b 2 V to 3.6 V 2.72

VLCD,4 LCDCPEN = 1, VLCDx = 0100b 2 V to 3.6 V 2.78

VLCD,5 LCDCPEN = 1, VLCDx = 0101b 2 V to 3.6 V 2.84

VLCD,6 LCDCPEN = 1, VLCDx = 0110b 2 V to 3.6 V 2.90

VLCD,7 LCDCPEN = 1, VLCDx = 0111b 2 V to 3.6 V 2.96

VLCD,8 LCDCPEN = 1, VLCDx = 1000b 2 V to 3.6 V 3.02

VLCD,9 LCDCPEN = 1, VLCDx = 1001b 2 V to 3.6 V 3.08

VLCD,10 LCDCPEN = 1, VLCDx = 1010b 2 V to 3.6 V 3.14

VLCD,11 LCDCPEN = 1, VLCDx = 1011b 2 V to 3.6 V 3.20

VLCD,12 LCDCPEN = 1, VLCDx = 1100b 2 V to 3.6 V 3.26

VLCD,13 LCDCPEN = 1, VLCDx = 1101b 2.2 V to 3.6 V 3.32

VLCD,14 LCDCPEN = 1, VLCDx = 1110b 2.2 V to 3.6 V 3.38

VLCD,15 LCDCPEN = 1, VLCDx = 1111b 2.2 V to 3.6 V 3.32 3.44 3.6

VLCD,7,0.8 LCD voltage with external

reference of 0.8 V LCDCPEN = 1, VLCDx = 0111b,

VLCDREFx = 01b, VLCDREF = 0.8 V 2 V to 3.6 V 2.96 ×

0.8 V V

VLCD,7,1.0 LCD voltage with external

reference of 1.0 V LCDCPEN = 1, VLCDx = 0111b,

VLCDREFx = 01b, VLCDREF = 1.0 V 2 V to 3.6 V 2.96 ×

1.0 V V

VLCD,7,1.2 LCD voltage with external

reference of 1.2 V LCDCPEN = 1, VLCDx = 0111b,

VLCDREFx = 01b, VLCDREF = 1.2 V 2.2 V to 3.6 V 2.96 ×

1.2 V V

ΔVLCD Voltage difference between

consecutive VLCDx settings ΔVLCD = VLCD,x - VLCD,x–1

with x = 0010b to 1111b 40 60 80 mV

ICC,Peak,CP Peak supply currents due to

charge pump activities LCDCPEN = 1, VLCDx = 1111b

external, with decoupling capacitor on

DVCC supply ≥1 µF

2.2 V 600 µA

tLCD,CP,on Time to charge CLCD when

discharged CLCD = 4.7 µF, LCDCPEN = 0→1,

VLCDx = 1111b 2.2 V 100 500 ms

ICP,Load Maximum charge pump load

current LCDCPEN = 1, VLCDx = 1111b 2.2 V 50 µA

RLCD,Seg LCD driver output impedance,

segment lines LCDCPEN = 0, ILOAD = ±10 µA 2.2 V 10 kΩ

RLCD,COM LCD driver output impedance,

common lines LCDCPEN = 0, ILOAD = ±10 µA 2.2 V 10 kΩ

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5.13.9 ADC12

Table 5-24 lists the power supply and input range conditions for the ADC.

(1) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.

(2) The internal reference supply current is not included in current consumption parameter I(ADC12_B).

(3) Typically about 60% of the total current into the AVCC and DVCC terminal is from AVCC.

Table 5-24. 12-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT

V(Ax) Analog input voltage(1) All ADC12 analog input pins Ax 0 AVCC V

I(ADC12_B)

single-

ended mode Operating supply current into

AVCC plus DVCC terminal(2) (3)

fADC12CLK = MODCLK, ADC12ON = 1,

ADC12PWRMD = 0, ADC12DIF = 0

REFON = 0, ADC12SHTx = 0,

ADC12DIV = 0

3.0 V 145 199 µA

2.2 V 140 190

I(ADC12_B)

differential

mode Operating supply current into

AVCC and DVCC terminals(2) (3)

fADC12CLK = MODCLK, ADC12ON = 1,

ADC12PWRMD = 0, ADC12DIF = 1

REFON = 0, ADC12SHTx = 0,

ADC12DIV = 0

3.0 V 175 245 µA

2.2 V 170 230

CIInput capacitance Only one terminal Ax can be selected

at one time 2.2 V 10 15 pF

RIInput MUX ON resistance 0 V ≤V(Ax) ≤AVCC >2 V 0.5 4 kΩ

<2 V 1 10

Table 5-25 lists the timing parameter for the ADC.

(1) The ADC12OSC is sourced directly from MODOSC inside the UCS.

(2) 14 × 1 / fADC12CLK. If ADC12WINC = 1, then 15 × 1 / fADC12CLK

(3) The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signals are already

settled.

Table 5-25. 12-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

fADC12CLK Specified performance For specified performance of ADC12 linearity parameters

with ADC12PWRMD = 0,

If ADC12PWRMD = 1, the maximum is 1/4 of the value

shown here 0.45 5.4 MHz

fADC12CLK Reduced performance Linearity parameters have reduced performance 32.768 kHz

fADC12OSC Internal oscillator(1) ADC12DIV = 0, fADC12CLK = fADC12OSC from MODCLK 4 4.8 5.4 MHz

tCONVERT Conversion time

REFON = 0, Internal oscillator,

fADC12CLK = fADC12OSC from MODCLK,

ADC12WINC = 0 2.6 3.5 µs

External fADC12CLK from ACLK, MCLK, or SMCLK,

ADC12SSEL ≠0(2)

tADC12ON Turnon settling time of

the ADC See (3) 100 ns

tADC12OFF Time ADC must be off

before can be turned

on again tADC12OFF must be met to make sure tADC12ON time holds 100 ns

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Table 5-25. 12-Bit ADC, Timing Parameters (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(4) Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB: tsample = ln(2n+2) × (RS+ RI) × (CI+ Cpext), RS< 10 kΩ,

where n = ADC resolution = 12, RS= external source resistance, Cpext = external parasitic capacitance.

(5) 6 × (1 / fADC12CLK)

tSample Sampling time RS= 400 Ω, RI= 4 kΩ,

CI= 15 pF, Cpext= 8 pF(4)

All pulse sample mode

(ADC12SHP = 1) and

extended sample mode

(ADC12SHP = 0) with

buffered reference (ADC12

VRSEL = 0x1, 0x3, 0x5, 0x7,

0x9, 0xB, 0xD, 0xF)

1 µs

Extended sample mode

(ADC12SHP = 0) with

unbuffered reference

(ADC12 VRSEL= 0x0, 0x2,

0x4, 0x6, 0xC, 0xE)

(5) µs

Table 5-26 lists the linearity parameters of the ADC when using an external reference.

(1) See Table 5-28 and Table 5-34 for more information on internal reference performance and see Designing With the MSP430FR58xx,

FR59xx, FR68xx, and FR69xx ADC for details on optimizing ADC performance for your application with the choice of internal versus

external reference.

(2) Offset is measured as the input voltage (at which ADC output transitions from 0 to 1) minus 0.5 LSB.

(3) Offset increases as IRdrop increases when VR– is AVSS.

(4) For details, see the device descriptor table section in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.

Table 5-26. 12-Bit ADC, Linearity Parameters With External Reference(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution Number of no missing code

output-code bits 12 bits

EIIntegral linearity error (INL)

for differential input 1.2 V ≤VR+ – VR–≤AVCC ±1.8 LSB

EIIntegral linearity error (INL)

for single ended inputs 1.2 V ≤VR+ – VR–≤AVCC ±2.2 LSB

EDDifferential linearity error

(DNL) –0.99 +1.0 LSB

EOOffset error(2) (3) ADC12 VRSEL = 0x2 or 0x4 without TLV calibration,

TLV calibration data can be used to improve the parameter(4) ±0.5 ±1.5 mV

EG,ext Gain error

With external voltage reference without internal buffer

(ADC12 VRSEL = 0x2 or 0x4) without TLV calibration,

TLV calibration data can be used to improve the parameter(4),

VR+ = 2.5 V, VR– = AVSS ±0.8 ±2.5

LSB

With external voltage reference with internal buffer (ADC12

VRSEL = 0x3),

VR+ = 2.5 V, VR– = AVSS ±1 ±20

ET,ext Total unadjusted error

With external voltage reference without internal buffer

(ADC12 VRSEL = 0x2 or 0x4) without TLV calibration,

TLV calibration data can be used to improve the parameter(4),

VR+ = 2.5 V, VR– = AVSS ±1.4 ±3.5

LSB

With external voltage reference with internal buffer (ADC12

VRSEL = 0x3),

VR+ = 2.5 V, VR– = AVSS ±1.4 ±21.0

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Table 5-27 lists the differential dynamic performance characteristics of the ADC with an external

reference.

(1) See Table 5-28 and Table 5-34 for more information on internal reference performance and see Designing With the MSP430FR58xx,

FR59xx, FR68xx, and FR69xx ADC for details on optimizing ADC performance for your application with the choice of internal versus

external reference.

(2) ENOB = (SINAD – 1.76) / 6.02

Table 5-27. 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SNR Signal-to-noise ratio VR+ = 2.5 V, VR– = AVSS 68 71 dB

ENOB Effective number of bits(2) VR+ = 2.5 V, VR– = AVSS 10.7 11.2 bits

Table 5-28 lists the differential dynamic performance characteristics of the ADC with an internal reference.

(1) See Table 5-34 for more information on internal reference performance and see Designing With the MSP430FR58xx, FR59xx, FR68xx,

and FR69xx ADC for details on optimizing ADC performance for your application with the choice of internal versus external reference.

(2) ENOB = (SINAD – 1.76) / 6.02

Table 5-28. 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ENOB Effective number of bits(2) VR+ = 2.5V, VR– = AVSS 10.3 10.7 Bits

Table 5-29 lists the single-ended dynamic performance characteristics of the ADC with an external

reference.

(1) See Table 5-30 and Table 5-34 for more information on internal reference performance and see Designing With the MSP430FR58xx,

FR59xx, FR68xx, and FR69xx ADC for details on optimizing ADC performance for your application with the choice of internal versus

external reference.

(2) ENOB = (SINAD – 1.76) / 6.02

Table 5-29. 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SNR Signal-to-noise ratio VR+ = 2.5 V, VR– = AVSS 64 68 dB

ENOB Effective number of bits(2) VR+ = 2.5 V, VR– = AVSS 10.2 10.7 bits

Table 5-30 lists the single-ended dynamic performance characteristics of the ADC with an internal

reference.

(1) See Table 5-34 for more information on internal reference performance and see Designing With the MSP430FR58xx, FR59xx, FR68xx,

and FR69xx ADC for details on optimizing ADC performance for your application with the choice of internal versus external reference.

(2) ENOB = (SINAD – 1.76) / 6.02

Table 5-30. 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ENOB Effective number of bits(2) VR+ = 2.5 V, VR– = AVSS 9.4 10.4 bits

Table 5-31 lists the dynamic performance characteristics of the ADC with using a 32.768-kHz clock.

(1) ENOB = (SINAD – 1.76) / 6.02

Table 5-31. 12-Bit ADC, Dynamic Performance With 32.768-kHz Clock

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ENOB Effective number of bits(1) Reduced performance with fADC12CLK from ACLK LFXT

at 32.768 kHz, VR+ = 2.5 V, VR– = AVSS 10 bits

500

550

600

650

700

750

800

850

900

950

–40 –20 0 20 40 60 80

Typical Temperature Sensor Voltage (mV)

Ambient Temperature (°C)

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Table 5-32 lists the temperature sensor and built-in V1/2 characteristics.

(1) The temperature sensor offset can be as much as ±30°C. TI recommends a single-point calibration to minimize the offset error of the

built-in temperature sensor.

(2) The device descriptor structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference voltage

levels. The sensor voltage can be computed as VSENSE = TCSENSOR * (Temperature, °C) + VSENSOR, where TCSENSOR and VSENSOR can

be computed from the calibration values for higher accuracy.

(3) The typical equivalent impedance of the sensor is 250 kΩ. The sample time required includes the sensor on-time tSENSOR(on).

(4) The on-time tV 1/2(on) is included in the sampling time tV 1/2 (sample); no additional on time is needed.

Table 5-32. 12-Bit ADC, Temperature Sensor and Built-In V1/2

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

VSENSOR See (1) (2) ADC12ON = 1, ADC12TCMAP = 1,

TA= 0°C (see Figure 5-19)700 mV

TCSENSOR See (2) ADC12ON = 1, ADC12TCMAP = 1 2.5 mV/°C

tSENSOR(sample) Sample time required if

ADCTCMAP = 1 and channel

(MAX – 1) is selected(3) ADC12ON = 1, ADC12TCMAP = 1,

Error of conversion result ≤1 LSB 30 µs

V1/2 AVCC voltage divider for

ADC12BATMAP = 1 on MAX input

channel ADC12ON = 1, ADC12BATMAP = 1 47.5% 50% 52.5%

IV 1/2 current for battery monitor during

sample time ADC12ON = 1, ADC12BATMAP = 1 38 72 µA

tV 1/2 (sample) Sample time required if

ADC12BATMAP = 1 and channel

MAX is selected(4) ADC12ON = 1, ADC12BATMAP = 1 1.7 µs

Figure 5-19. Typical Temperature Sensor Voltage

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Table 5-33 lists the external reference characteristics of the ADC.

(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also

the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the

recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.

(2) Two decoupling capacitors, 10 µF and 470 nF, should be connected to VeREF to decouple the dynamic current required for an external

reference source if it is used for the ADC12_B. See also the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's

Guide.

Table 5-33. 12-Bit ADC, External Reference(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

VR+ Positive external reference voltage input

VeREF+ or VeREF- based on ADC12 VRSEL bit VR+ > VR– 1.2 AVCC V

VR– Negative external reference voltage input

VeREF+ or VeREF- based on ADC12 VRSEL bit VR+ > VR– 0 1.2 V

(VR+ – VR–) Differential external reference voltage input VR+ > VR– 1.2 AVCC V

IVeREF+

IVeREF- Static input current singled ended input mode

1.2 V ≤VeREF+≤VAVCC, VeREF– = 0 V

fADC12CLK = 5 MHz, ADC12SHTx = 1h,

ADC12DIF = 0, ADC12PWRMD = 0 ±10

µA

1.2 V ≤VeREF+≤VAVCC , VeREF– = 0 V

fADC12CLK = 5 MHz, ADC12SHTx = 8h,

ADC12DIF = 0, ADC12PWRMD = 01 ±2.5

IVeREF+

IVeREF- Static input current differential input mode

1.2 V ≤VeREF+≤VAVCC, VeREF– = 0 V

fADC12CLK = 5 MHz, ADC12SHTx = 1h,

ADC12DIF = 1, ADC12PWRMD = 0 ±20

1.2 V ≤VeREF+≤VAVCC , VeREF– = 0 V

fADC12CLK = 5 MHz, ADC12SHTx = 8h,

ADC12DIF = 1, ADC12PWRMD = 1 ±5

IVeREF+ Peak input current with single ended input 0 V ≤VeREF+ ≤VAVCC, ADC12DIF = 0 1.5 mA

IVeREF+ Peak input current with differential input 0 V ≤VeREF+ ≤VAVCC, ADC12DIF = 1 3 mA

CVeREF+/- Capacitance at VeREF+ or VeREF- terminal See (2) 10 µF

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5.13.10 REF Module

Table 5-34 lists the characteristics of the built-in voltage reference.

(1) Internal reference noise affects ADC performance when ADC uses internal reference. See Designing With the MSP430FR59xx and

MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal versus external

reference.

(2) Buffer offset affects ADC gain error and thus total unadjusted error.

(3) The internal reference current is supplied through the AVCC terminal.

(4) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).

(5) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.

Table 5-34. REF, Built-In Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

VREF+ Positive built-in reference

voltage output

REFVSEL = {2} for 2.5 V, REFON = 1 2.7 V 2.5 ±1.5% VREFVSEL = {1} for 2.0 V, REFON = 1 2.2 V 2.0 ±1.5%

REFVSEL = {0} for 1.2 V, REFON = 1 1.8 V 1.2 ±1.8%

Noise RMS noise at VREF(1) From 0.1 Hz to 10 Hz, REFVSEL = {0} 110 600 µV

VOS_BUF_INT VREF ADC BUF_INT buffer

offset(2) TA= 25°C , ADC ON, REFVSEL = {0},

REFON = 1, REFOUT = 0 –12 +12 mV

VOS_BUF_EXT VREF ADC BUF_EXT

buffer offset(2) TA= 25°C, REFVSEL = {0} , REFOUT = 1,

REFON = 1 or ADC ON –12 +12 mV

AVCC(min) AVCC minimum voltage,

Positive built-in reference

active

REFVSEL = {0} for 1.2 V 1.8 VREFVSEL = {1} for 2.0 V 2.2

REFVSEL = {2} for 2.5 V 2.7

IREF+ Operating supply current

into AVCC terminal(3) REFON = 1 3 V 8 15 µA

IREF+_ADC_BUF Operating supply current

into AVCC terminal(3)

ADC ON, REFOUT = 0, REFVSEL = {0, 1, 2},

ADC12PWRMD = 0,

3 V

225 355

µA

ADC ON, REFOUT = 1, REFVSEL = {0, 1, 2},

ADC12PWRMD = 0 1030 1660

ADC ON, REFOUT = 0, REFVSEL = {0, 1, 2},

ADC12PWRMD = 1 120 185

ADC ON, REFOUT = 1, REFVSEL = {0, 1, 2},

ADC12PWRMD = 1 545 895

ADC OFF, REFON = 1, REFOUT = 1,

REFVSEL = {0, 1, 2} 1085 1780

IO(VREF+) VREF maximum load

current, VREF+ terminal REFVSEL = {0, 1, 2}, AVCC = AVCC(min) for

each reference level,

REFON = REFOUT = 1 –1000 +10 µA

ΔVout/ΔIo

(VREF+) Load-current regulation,

VREF+ terminal

REFVSEL = {0, 1, 2},

IO(VREF+) = +10 µA or –1000 µA,

AVCC = AVCC(min) for each reference level,

REFON = REFOUT = 1 2500 µV/mA

CVREF+/- Capacitance at VREF+ and

VREF- terminals REFON = REFOUT = 1 0 100 pF

TCREF+ Temperature coefficient of

built-in reference REFVSEL = {0, 1, 2}, REFON = REFOUT = 1,

TA= –40°C to 85°C(4) 18 50 ppm/K

PSRR_DC Power supply rejection ratio

(DC) AVCC = AVCC(min) to AVCC(max), TA= 25°C,

REFVSEL = {0, 1, 2}, REFON = REFOUT = 1 120 400 µV/V

PSRR_AC Power supply rejection ratio

(AC) dAVCC= 0.1 V at 1 kHz 3.0 mV/V

tSETTLE Settling time of reference

voltage(5) AVCC = AVCC (min) to AVCC(max),

REFVSEL = {0, 1, 2}, REFON = 0 →175 80 µs

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5.13.11 Comparator

Table 5-35 lists the characteristics of the comparator.

Table 5-35. Comparator_E

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

IAVCC_COMP Comparator operating supply

current into AVCC, excludes

reference resistor ladder

CEPWRMD = 00, CEON = 1,

CERSx = 00 (fast)

2.2 V,

3.0 V

11 20

µA

CEPWRMD = 01, CEON = 1,

CERSx = 00 (medium) 9 17

CEPWRMD = 10, CEON = 1,

CERSx = 00 (slow), TA= 30°C 0.5

CEPWRMD = 10, CEON = 1,

CERSx = 00 (slow), TA= 85°C 1.3

IAVCC_REF Quiescent current of resistor

ladder into AVCC, including

REF module current

CEREFLx = 01, CERSx = 10, REFON = 0,

CEON = 0, CEREFACC = 0 2.2 V,

3.0 V

12 15 µA

CEREFLx = 01, CERSx = 10, REFON = 0,

CEON = 0, CEREFACC = 1 5 7

VREF Reference voltage level

CERSx = 11, CEREFLx = 01, CEREFACC = 0 1.8 V 1.17 1.2 1.23

CERSx = 11, CEREFLx = 10, CEREFACC = 0 2.2 V 1.92 2.0 2.08

CERSx = 11, CEREFLx = 11, CEREFACC = 0 2.7 V 2.40 2.5 2.60

CERSx = 11, CEREFLx = 01, CEREFACC = 1 1.8 V 1.10 1.2 1.245

CERSx = 11, CEREFLx = 10, CEREFACC = 1 2.2 V 1.90 2.0 2.08

CERSx = 11, CEREFLx = 11, CEREFACC = 1 2.7 V 2.35 2.5 2.60

VIC Common-mode input range 0 VCC – 1 V

VOFFSET Input offset voltage

CEPWRMD = 00 –32 32

mVCEPWRMD = 01 –32 32

CEPWRMD = 10 –30 30

CIN Input capacitance CEPWRMD = 00 or CEPWRMD = 01 9 pF

CEPWRMD = 10 9

RSIN Series input resistance On (switch closed) 1 3 kΩ

Off (switch open) 50 MΩ

tPD Propagation delay, response

time

CEPWRMD = 00, CEF = 0, Overdrive ≥20 mV 260 330 ns

CEPWRMD = 01, CEF = 0, Overdrive ≥20 mV 350 460

CEPWRMD = 10, CEF = 0, Overdrive ≥20 mV 15 µs

tPD,filter Propagation delay with filter

active

CEPWRMD = 00 or 01, CEF = 1,

Overdrive ≥20 mV, CEFDLY = 00 700 1000 ns

CEPWRMD = 00 or 01, CEF = 1,

Overdrive ≥20 mV, CEFDLY = 01 1.0 1.8

µs

CEPWRMD = 00 or 01, CEF = 1,

Overdrive ≥20 mV, CEFDLY = 10 2.0 3.5

CEPWRMD = 00 or 01, CEF = 1,

Overdrive ≥20 mV, CEFDLY = 11 4.0 7.0

tEN_CMP Comparator enable time

CEON = 0 →1, VIN+, VIN- from pins,

Overdrive ≥20 mV, CEPWRMD = 00 0.9 1.5

µs

CEON = 0 →1, VIN+, VIN- from pins,

Overdrive ≥20 mV, CEPWRMD = 01 0.9 1.5

CEON = 0 →1, VIN+, VIN- from pins,

Overdrive ≥20 mV, CEPWRMD = 10 15 100

tEN_CMP_VREF Comparator and reference

ladder and reference voltage

enable time

CEON = 0 →1, CEREFLX = 10, CERSx = 10 or 11,

CEREF0 = CEREF1 = 0x0F,

Overdrive ≥20 mV 350 1500 µs

VCE_REF Reference voltage for a

given tap VIN = reference into resistor ladder,

n = 0 to 31

VIN ×

(n + 0.5)

/ 32

VIN ×

(n + 1)

/ 32

VIN ×

(n + 1.5)

/ 32 V

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5.13.12 FRAM Controller

Table 5-36 lists the characteristics of the FRAM.

(1) Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read

current IREAD is included in the active mode current consumption numbers IAM,FRAM.

(2) N/A = not applicable. FRAM does not require a special erase sequence.

(3) Writing into FRAM is as fast as reading.

(4) The maximum read (and write) speed is specified by fSYSTEM using the appropriate wait state settings (NWAITSx).

Table 5-36. FRAM

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST

CONDITIONS MIN TYP MAX UNIT

Read and write endurance 1015 cycles

tRetention Data retention duration TJ= 25°C 100 yearsTJ= 70°C 40

TJ= 85°C 10

IWRITE Current to write into FRAM IREAD(1) nA

IERASE Erase current N/A(2) nA

tWRITE Write time tREAD(3) ns

tREAD Read time, NWAITSx = 0 1 / fSYSTEM(4) ns

Read time, NWAITSx = 1 2 / fSYSTEM(4)

5.13.13 Emulation and Debug

Table 5-37 lists the characteristics of the JTAG and Spy-Bi-Wire interface.

(1) Tools that access the Spy-Bi-Wire and BSL interfaces must wait for the tSBW,En time after the first transition of the TEST/SBWTCK pin

(low to high), before the second transition of the pin (high to low) during the entry sequence.

(2) fTCK may be restricted to meet the timing requirements of the module selected.

Table 5-37. JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST

CONDITIONS MIN TYP MAX UNIT

IJTAG Supply current adder when JTAG active (but not clocked) 2.2 V, 3.0 V 40 100 μA

fSBW Spy-Bi-Wire input frequency 2.2 V, 3.0 V 0 10 MHz

tSBW,Low Spy-Bi-Wire low clock pulse duration 2.2 V, 3.0 V 0.04 15 μs

tSBW, En Spy-Bi-Wire enable time (TEST high to acceptance of first clock

edge)(1) 2.2 V, 3.0 V 110 μs

tSBW,Rst Spy-Bi-Wire return to normal operation time 15 100 μs

fTCK TCK input frequency, 4-wire JTAG(2) 2.2 V 0 16 MHz

3.0 V 0 16 MHz

Rinternal Internal pulldown resistance on TEST 2.2 V, 3.0 V 20 35 50 kΩ

fTCLK TCLK/MCLK frequency during JTAG access, no FRAM access

(limited by fSYSTEM)16 MHz

tTCLK,Low/High TCLK low or high clock pulse duration, no FRAM access 25 ns

fTCLK,FRAM TCLK/MCLK frequency during JTAG access, including FRAM access

(limited by fSYSTEM with no FRAM wait states) 4 MHz

tTCLK,FRAM,Low/High TCLK low or high clock pulse duration, including FRAM accesses 100 ns

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6 Detailed Description

6.1 Overview

The Texas Instruments MSP430FR697x(1), MSP430FR687x(1), MSP430FR692x(1), and

MSP430FR682x(1) family of ultra-low-power microcontrollers consists of several devices featuring

different sets of peripherals. The architecture, combined with seven low-power modes is optimized to

achieve extended battery life for example in portable measurement applications. The devices features a

powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code

efficiency. The devices are microcontroller configurations with up to five 16-bit timers, a comparator,

eUSCIs that support UART, SPI, and I2C, a hardware multiplier, an AES accelerator, DMA, an RTC

module with alarm capabilities, up to 52 I/O pins, and a high-performance 12-bit ADC. The

MSP430FR6xxx(1) devices also include an LCD module with contrast control for displays with up to 116

segments.

6.2 CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All

operations, other than program-flow instructions, are performed as register operations in conjunction with

seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and

constant generator, respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all

instructions.

The instruction set consists of the original 51 instructions with three formats and seven address modes

and additional instructions for the expanded address range. Each instruction can operate on word and

byte data. CPUxV2 can also operate on address-word data (20-bit).

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6.3 Operating Modes

The device has one active mode and seven software selectable low-power modes of operation (see Table 6-1). An interrupt event can wake up the

device from low-power modes LPM0 to LPM4, service the request, and restore back to the low-power mode on return from the interrupt program.

Low-power modes LPM3.5 and LPM4.5 disable the core supply to minimize power consumption.

(1) FRAM disabled in FRAM controller

(2) Disabling the FRAM through the FRAM controller decreases the LPM current consumption, but the wake-up time can increase. If the wakeup is for FRAM access (for example, to fetch an

interrupt vector), wake-up time is increased. If the wakeup is for an operation that does not access FRAM (for example, DMA transfer to RAM), wake-up time is not increased.

(3) All clocks disabled

(4) See Section 6.3.2, which describes the use of peripherals in LPM3 and LPM4.

(5) "Unclocked peripherals" are peripherals that do not require a clock source to operate; for example, the comparator and REF, or the eUSCI when operated as an SPI slave.

(6) Controlled by SMCLKOFF

(7) Using the RAM Controller, the RAM can be completely powered down to save leakage; however, all data is lost.

(8) Activated SVS (SVSHE = 1) results in higher current consumption. SVS not included in typical current consumption.

(9) SVSHE = 1

(10) SVSHE = 0

Table 6-1. Operating Modes

MODE AM LPM0 LPM1 LPM2 LPM3 LPM4 LPM3.5 LPM4.5

Active Active,

FRAM Off

(1) CPU Off (2) CPU Off Standby Standby Off RTC Only Shutdown

With SVS Shutdown

Without

SVS

Maximum system clock 16 MHz 16 MHz 16 MHz 50 kHz 50 kHz 0 (3) 50 kHz 0 (3)

Typical current consumption,

25°C 103

µA/MHz 65 µA/MHz 75 µA at

1 MHz 40 µA at

1 MHz 0.9 µA 0.4 µA 0.3 µA 0.35 µA 0.2 µA 0.02 µA

Typical wake-up time N/A instant. 6 µs 6 µs 7 µs 7 µs 250 µs 250 µs 1000 µs

Wake-up events N/A all all LF

RTC

I/O

Comp

RTC

I/O

Comp

I/O

Comp RTC

I/O _

I/O

CPU on off off off off off reset reset

FRAM on off(1) standby (or off

(1))off off off off off off

High-frequency peripherals available available available off off off reset reset

Low-frequency peripherals available available available available available (4) off RTC reset

Unclocked peripherals(5) available available available available available (4) available (4) reset reset

MCLK on off off off off off off off

SMCLK opt. (6) opt. (6) opt. (6) off off off off off

ACLK on on on on on off off off

Full retention yes yes yes yes yes (7) yes (7) no no

SVS always always always optional(8) optional(8) optional(8) optional(8) on (9) off (10)

Brownout always always always always always always always always

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6.3.1 Peripherals in Low-Power Modes

Peripherals can be in different states that affect which power mode the device can enter. The states

depend on the operational modes of the peripherals (see Table 6-2). The states are:

• A peripheral is in a "high-frequency state" if it requires or uses a clock with a "high" frequency of more

than 50 kHz.

• A peripheral is in a "low-frequency state" if it requires or uses a clock with a "low" frequency of 50 kHz

or less.

• A peripheral is in an "unclocked state" if it does not require or use an internal clock.

If the CPU requests a power mode that does not support the current state of all active peripherals, the

device does not enter the requested power mode. The device instead enters a power mode that still

supports the current state of the peripherals, except if an external clock is used. If an external clock is

used, the application must use the correct frequency range for the requested power mode.

(1) Peripherals are in a state that requires or uses a clock with a "high" frequency of more than 50 kHz.

(2) Peripherals are in a state that requires or uses a clock with a "low" frequency of 50 kHz or less.

(3) Peripherals are in a state that does not require or does not use an internal clock.

(4) The DMA always transfers data in active mode but can wait for a trigger in any low-power mode. A DMA trigger during a low-power

mode causes a temporary transition into active mode for the time of the transfer.

(5) This peripheral operates during active mode only and delays the transition into a low-power mode until its operation is completed.

Table 6-2. Peripheral States

PERIPHERAL IN HIGH-FREQUENCY STATE(1) IN LOW-FREQUENCY STATE(2) IN UNCLOCKED STATE(3)

WDT Clocked by SMCLK Clocked by ACLK Not applicable

DMA(4) Not applicable Not applicable Waiting for a trigger

RTC_C Not applicable Clocked by LFXT Not applicable

LCD_C Not applicable Clocked by ACLK or VLOCLK Not applicable

Timer_A TAx Clocked by SMCLK or

clocked by external clock >50 kHz Clocked by ACLK or

clocked by external clock ≤50 kHz Clocked by external clock ≤50 kHz

Timer_B TBx Clocked by SMCLK or

clocked by external clock >50 kHz Clocked by ACLK or

clocked by external clock ≤50 kHz Clocked by external clock ≤50 kHz

eUSCI_Ax in

UART mode Clocked by SMCLK Clocked by ACLK Waiting for first edge of START bit.

eUSCI_Ax in SPI

master mode Clocked by SMCLK Clocked by ACLK Not applicable

eUSCI_Ax in SPI

slave mode Clocked by external clock >50 kHz Clocked by external clock ≤50 kHz Clocked by external clock ≤50 kHz

eUSCI_Bx in I2C

master mode Clocked by SMCLK or

clocked by external clock >50 kHz Clocked by ACLK or

clocked by external clock ≤50 kHz Not applicable

eUSCI_Bx in I2C

slave mode Clocked by external clock >50 kHz Clocked by external clock ≤50 kHz Waiting for START condition or

clocked by external clock ≤50 kHz

eUSCI_Bx in SPI

master mode Clocked by SMCLK Clocked by ACLK Not applicable

eUSCI_Bx in SPI

slave mode Clocked by external clock >50 kHz Clocked by external clock ≤50 kHz Clocked by external clock ≤50 kHz

ADC12_B Clocked by SMCLK or by MODOSC Clocked by ACLK Waiting for a trigger

REF_A Not applicable Not applicable Always

COMP_E Not applicable Not applicable Always

CRC(5) Not applicable Not applicable Not applicable

MPY(5) Not applicable Not applicable Not applicable

AES(5) Not applicable Not applicable Not applicable

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6.3.2 Idle Currents of Peripherals in LPM3 and LPM4

Most peripherals can be activated to be operational in LPM3 if clocked by ACLK. Some modules are even

operational in LPM4 because they do not require a clock to operate (for example, the comparator).

Activating a peripheral in LPM3 or LPM4 increases the current consumption due to its active supply

current contribution but also due to an additional idle current. To limit the idle current adder, certain

peripherals are group together. To achieve optimal current consumption, try to use modules within one

group and to limit the number of groups with active modules. Table 6-3 lists the grouping. Modules not

listed in this table are either already included in the standard LPM3 current consumption specifications or

cannot be used in LPM3 or LPM4.

The idle current adder is very small at room temperature (25°C) but increases at high temperatures

(85°C); see the IIDLE current parameters in Section 5.7 for details.

Table 6-3. Peripheral Groups

Group A Group B Group C

Timer TA0 Timer TA2 Timer TA3

Timer TA1 Timer B0 eUSCI_A1

Comparator eUSCI_A0 LCD_C

ADC12_B eUSCI_B0

REF_A eUSCI_B1

6.4 Interrupt Vector Table and Signatures

The interrupt vectors, the power-up start address, and signatures are in the address range 0FFFFh to

0FF80h. Table 6-4 summarizes the content of this address range.

The power-up start address or reset vector is at 0FFFFh to 0FFFEh. It contains the 16-bit address pointing

to the start address of the application program.

The interrupt vectors start at 0FFFDh extending to lower addresses. Each vector contains the 16-bit

address of the appropriate interrupt-handler instruction sequence.

The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as BSL password (if

enabled by the corresponding signature)

The signatures are at 0FF80h extending to higher addresses. Signatures are evaluated during device

start-up. Starting from address 0FF88h extending to higher addresses a JTAG password can

programmed. The password can extend into the interrupt vector locations using the interrupt vector

addresses as additional bits for the password.

See the chapter System Resets, Interrupts, and Operating Modes, System Control Module (SYS) in the

MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide for details.

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(1) Multiple source flags

(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space

(3) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

(4) Only on devices with ADC, otherwise reserved.

Table 6-4. Interrupt Sources, Flags, Vectors, and Signatures

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM

INTERRUPT WORD

ADDRESS PRIORITY

System Reset

Power-up, Brownout, Supply

Supervisor

External Reset RST

Watchdog time-out (watchdog

mode)

WDT, FRCTL MPU, CS, PMM

password violation

FRAM uncorrectable bit error

detection

FRAM access time error

MPU segment violation

Software POR, BOR

SVSHIFG

PMMRSTIFG

WDTIFG

WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW

UBDIFG

ACCTEIFG

MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,

MPUSEG3IFG

PMMPORIFG, PMMBORIFG

(SYSRSTIV) (1) (2)

Reset 0FFFEh Highest

System NMI

Vacant memory access

JTAG mailbox

FRAM bit error detection

MPU segment violation

VMAIFG

JMBNIFG, JMBOUTIFG

CBDIFG, UBDIFG

MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,

MPUSEG3IFG

(SYSSNIV) (1) (3)

(Non)maskable 0FFFCh

User NMI

External NMI

Oscillator Fault NMIIFG, OFIFG

(SYSUNIV) (1) (3) (Non)maskable 0FFFAh

Comparator_E Comparator_E interrupt flags

(CEIV) (1) Maskable 0FFF8h

Timer_B TB0 TB0CCR0.CCIFG Maskable 0FFF6h

Timer_B TB0 TB0CCR1.CCIFG to TB0CCR6.CCIFG,

TB0CTL.TBIFG

(TB0IV)(1) Maskable 0FFF4h

Watchdog Timer

(Interval Timer Mode) WDTIFG Maskable 0FFF2h

Reserved Reserved Maskable 0FFF0h

eUSCI_A0 Receive or Transmit UCA0IFG: UCRXIFG, UCTXIFG (SPI mode)

UCA0IFG:UCSTTIFG, UCTXCPTIFG, UCRXIFG,

UCTXIFG (UART mode)

(UCA0IV)(1) Maskable 0FFEEh

eUSCI_B0 Receive or Transmit

UCB0IFG: UCRXIFG, UCTXIFG (SPI mode)

UCB0IFG: UCALIFG, UCNACKIFG, UCSTTIFG,

UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1,

UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3,

UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)

(UCB0IV)(1)

Maskable 0FFECh

ADC12_B ADC12IFG0 to ADC12IFG31

ADC12LOIFG, ADC12INIFG, ADC12HIIFG,

ADC12RDYIFG, ADC12OVIFG, ADC12TOVIFG

(ADC12IV) (1) (4) Maskable 0FFEAh

Timer_A TA0 TA0CCR0.CCIFG Maskable 0FFE8h

Timer_A TA0 TA0CCR1.CCIFG to TA0CCR2.CCIFG,

TA0CTL.TAIFG

(TA0IV)(1) Maskable 0FFE6h

eUSCI_A1 receive or transmit UCA1IFG:UCRXIFG, UCTXIFG (SPI mode)

UCA1IFG:UCSTTIFG, UCTXCPTIFG, UCRXIFG,

UCTXIFG (UART mode)

(UCA1IV)(1) Maskable 0FFE4h

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Table 6-4. Interrupt Sources, Flags, Vectors, and Signatures (continued)

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM

INTERRUPT WORD

ADDRESS PRIORITY

(5) May contain a JTAG password required to enable JTAG access to the device.

(6) Signatures are evaluated during device start-up. See the System Resets, Interrupts, and Operating Modes, System Control Module

(SYS) chapter in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide for details.

(7) Must not contain 0AAAAh if used as JTAG password.

eUSCI_B1 receive or transmit

(Reserved on MSP430FR692x)

UCB1IFG: UCRXIFG, UCTXIFG (SPI mode)

UCB1IFG: UCALIFG, UCNACKIFG, UCSTTIFG,

UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1,

UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3,

UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)

(UCB1IV)(1)

Maskable 0FFE2h

DMA DMA0CTL.DMAIFG, DMA1CTL.DMAIFG,

DMA2CTL.DMAIFG

(DMAIV)(1) Maskable 0FFE0h

Timer_A TA1 TA1CCR0.CCIFG Maskable 0FFDEh

Timer_A TA1 TA1CCR1.CCIFG to TA1CCR2.CCIFG,

TA1CTL.TAIFG

(TA1IV)(1) Maskable 0FFDCh

I/O Port P1 P1IFG.0 to P1IFG.7

(P1IV)(1) Maskable 0FFDAh

Timer_A TA2 TA2CCR0.CCIFG Maskable 0FFD8h

Timer_A TA2 TA2CCR1.CCIFG

TA2CTL.TAIFG

(TA2IV)(1) Maskable 0FFD6h

I/O Port P2 P2IFG.0 to P2IFG.3

(P2IV) (1) Maskable 0FFD4h

Timer_A TA3 TA3CCR0.CCIFG Maskable 0FFD2h

Timer_A TA3 TA3CCR1.CCIFG

TA3CTL.TAIFG

(TA3IV)(1) Maskable 0FFD0h

I/O Port P3 P3IFG.0 to P3IFG.7

(P3IV) (1) Maskable 0FFCEh

I/O Port P4 P4IFG.2 to P4IFG.7

(P4IV) (1) Maskable 0FFCCh

LCD_C LCD_C Interrupt Flags (LCDCIV) (1) Maskable 0FFCAh

RTC_C RTCRDYIFG, RTCTEVIFG, RTCAIFG,

RT0PSIFG, RT1PSIFG, RTCOFIFG

(RTCIV) (1) Maskable 0FFC8h

AES AESRDYIFG Maskable 0FFC6h Lowest

Reserved Reserved (5) 0FFC4h

⋮

0FF8Ch

Signatures (6)

IP Encapsulation Signature2 (5) 0FF8Ah

IP Encapsulation Signature1 (5) (7) 0FF88h

BSL Signature2 0FF86h

BSL Signature1 0FF84h

JTAG Signature2 0FF82h

JTAG Signature1 0FF80h

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6.5 Bootloader (BSL)

The BSL enables programming of the FRAM or RAM using a UART serial interface (FRxxxx devices) or

an I2C interface (FRxxxx1 devices). Access to the device memory through the BSL is protected by an

user-defined password. Use of the BSL requires four pins as shown in Table 6-5. BSL entry requires a

specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For complete description of

the features of the BSL and its implementation, see MSP430 FRAM Device Bootloader (BSL) User's

Guide

Table 6-5. BSL Pin Requirements and Functions

DEVICE SIGNAL BSL FUNCTION

RST/NMI/SBWTDIO Entry sequence signal

TEST/SBWTCK Entry sequence signal

BSL_TX Devices with UART BSL (FRxxxx): Data transmit

BSL_RX Devices with UART BSL (FRxxxx): Data receive

BSL_DAT Devices with I2C BSL (FRxxxx1): Data

BSL_CLK Devices with I2C BSL (FRxxxx1): Clock

VCC Power supply

VSS Ground supply

6.6 JTAG Operation

6.6.1 JTAG Standard Interface

The MSP430 family supports the standard JTAG interface, which requires four signals for sending and

receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to

enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with

MSP430 development tools and device programmers. Table 6-6 lists the JTAG pin requirements. For

further details on interfacing to development tools and device programmers, see the MSP430 Hardware

Tools User's Guide. For a complete description of the features of the JTAG interface and its

implementation, see MSP430 Programming With the JTAG Interface.

Table 6-6. JTAG Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION

PJ.3/TCK IN JTAG clock input

PJ.2/TMS IN JTAG state control

PJ.1/TDI/TCLK IN JTAG data input, TCLK input

PJ.0/TDO OUT JTAG data output

TEST/SBWTCK IN Enable JTAG pins

RST/NMI/SBWTDIO IN External reset

VCC Power supply

VSS Ground supply

6.6.2 Spy-Bi-Wire Interface

In addition to the standard JTAG interface, the MSP430 family supports the 2-wire Spy-Bi-Wire interface.

Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. Table 6-7

lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and

device programmers, see the MSP430 Hardware Tools User's Guide.

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Table 6-7. Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION

TEST/SBWTCK IN Spy-Bi-Wire clock input

RST/NMI/SBWTDIO IN, OUT Spy-Bi-Wire data input/output

VCC Power supply

VSS Ground supply

6.7 FRAM

The FRAM can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the

CPU. Features of the FRAM include:

• Ultra-low-power ultra-fast-write nonvolatile memory

• Byte and word access capability

• Programmable and automated wait-state generation

• Error correction coding (ECC)

NOTE

Wait States

For MCLK frequencies > 8 MHz, wait states must be configured following the flow described

in the "Wait State Control" section of the "FRAM Controller (FRCTRL)" chapter in the

MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.

For important software design information regarding FRAM including but not limited to partitioning the

memory layout according to application-specific code, constant, and data space requirements, the use of

FRAM to optimize application energy consumption, and the use of the Memory Protection Unit (MPU) to

maximize application robustness by protecting the program code against unintended write accesses, see

MSP430™ FRAM Technology – How To and Best Practices

6.8 RAM

The RAM is made up of one sector. The sector can be completely powered down in LPM3 and LPM4 to

save leakage; however, all data is lost during shutdown.

6.9 Tiny RAM

Twenty-six bytes of Tiny RAM are provided in addition to the complete RAM (see Table 6-37). This

memory is always available even in LPM3 and LPM4, while the complete RAM can be powered down in

LPM3 and LPM4. Tiny RAM can be used to hold data or a very small stack when the complete RAM is

powered down in LPM3 and LPM4. Tiny RAM is not available in LPMx.5.

6.10 Memory Protection Unit (MPU) Including IP Encapsulation

The FRAM can be protected by the MPU from inadvertent CPU execution and read or write access.

Features of the MPU include:

• IP encapsulation with programmable boundaries (prevents reads from "outside" like JTAG or non-IP

software) in steps of 1KB.

• Main memory partitioning that can be configured in up to three segments in steps of 1KB.

• The access rights for each main and information memory segment can be individually selected.

• Access violation flags with interrupt capability for easy servicing of access violations.

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6.11 Peripherals

Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be

managed using all instructions. For complete module descriptions, see the MSP430FR58xx,

MSP430FR59xx, and MSP430FR6xx Family User's Guide.

6.11.1 Digital I/O

There are up to nine 8-bit I/O ports implemented:

• All individual I/O bits are independently programmable.

• Any combination of input, output, and interrupt conditions is possible.

• Programmable pullup or pulldown on all ports.

• Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for all pins of

ports P1 to P4.

• Read and write access to port control registers is supported by all instructions.

• Ports can be accessed byte-wise or word-wise in pairs.

• Capacitive touch functionality is supported on all pins of ports P1 to P7, P9, and PJ.

NOTE

Configuration of Digital I/Os After BOR Reset

To prevent any cross-currents during start-up of the device, all port pins are high-impedance

with Schmitt triggers and their module functions disabled. To enable the I/O functionality after

a BOR reset, the ports must be configured first and then the LOCKLPM5 bit must be cleared.

For details see the "Digital I/O" chapter, section "Configuration After Reset" in the

MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.

6.11.2 Oscillator and Clock System (CS)

The clock system includes support for a 32-kHz watch-crystal oscillator XT1 (LF), an internal very-low-

power low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a

high-frequency crystal oscillator XT2 (HF). The clock system module is designed to meet the requirements

of both low system cost and low power consumption. A fail-safe mechanism exists for all crystal sources.

The clock system module provides the following clock signals:

• Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (LFXT1), the internal low-frequency

oscillator (VLO), or a digital external low frequency (<50 kHz) clock source.

• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced from a high-frequency

crystal (HFXT2), the internal DCO, a 32-kHz watch crystal (LFXT1), the internal VLO, or a digital

external clock source.

• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be

sourced by same sources made available to MCLK.

6.11.3 Power-Management Module (PMM)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device . The PMM

also includes the supply voltage supervisor (SVS) and brownout protection. The brownout circuit is

implemented to provide the proper internal reset signal to the device during power on and power off. The

SVS circuitry detects if the supply voltage drops below a safe level. SVS circuitry is available on the

primary and core supplies.

6.11.4 Hardware Multiplier

The multiplication operation is supported by a dedicated peripheral module. The module performs

operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication

as well as signed and unsigned multiply-and-accumulate operations.

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6.11.5 Real-Time Clock (RTC_C)

The RTC_C module contains an integrated real-time clock (RTC) with the following features implemented:

• Calendar mode with leap year correction

• General-purpose counter mode

The internal calendar compensates for months with fewer than 31 days and includes leap year correction.

The RTC_C also supports flexible alarm functions and offset-calibration hardware. RTC operation is

available in LPM3.5 modes to minimize power consumption.

6.11.6 Watchdog Timer (WDT_A)

The primary function of the WDT_A module is to perform a controlled system restart after a software

problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function

is not needed in an application, the module can be configured as an interval timer and can generate

interrupts at selected time intervals. Table 6-8 lists the clocks that the WDT_A module can use.

Table 6-8. WDT_A Clocks

WDTSSEL NORMAL OPERATION

(WATCHDOG AND INTERVAL TIMER MODE)

00 SMCLK

01 ACLK

10 VLOCLK

11 LFMODOSC

6.11.7 System Module (SYS)

The SYS module handles many of the system functions within the device. These system functions include

power-on reset and power-up clear handling, NMI source selection and management, reset interrupt

vector generators, bootloader entry mechanisms, and configuration management (device descriptors).

Also included is a data exchange mechanism using JTAG called a JTAG mailbox that can be used in the

application. Table 6-9 lists the SYS module interrupt vector registers.

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Table 6-9. System Module Interrupt Vector Registers

INTERRUPT VECTOR

SYSRSTIV, System Reset 019Eh

No interrupt pending 00h

Brownout (BOR) 02h Highest

RSTIFG RST/NMI (BOR) 04h

PMMSWBOR software BOR (BOR) 06h

LPMx.5 wakeup (BOR) 08h

Security violation (BOR) 0Ah

Reserved 0Ch

SVSHIFG SVSH event (BOR) 0Eh

Reserved 10h

Reserved 12h

PMMSWPOR software POR (POR) 14h

WDTIFG watchdog time-out (PUC) 16h

WDTPW password violation (PUC) 18h

FRCTLPW password violation (PUC) 1Ah

Uncorrectable FRAM bit error detection (PUC) 1Ch

Peripheral area fetch (PUC) 1Eh

PMMPW PMM password violation (PUC) 20h

MPUPW MPU password violation (PUC) 22h

CSPW CS password violation (PUC) 24h

MPUSEGPIFG encapsulated IP memory segment violation

(PUC) 26h

MPUSEGIIFG information memory segment violation (PUC) 28h

MPUSEG1IFG segment 1 memory violation (PUC) 2Ah

MPUSEG2IFG segment 2 memory violation (PUC) 2Ch

MPUSEG3IFG segment 3 memory violation (PUC) 2Eh

ACCTEIFG access time error (PUC) 30h

Reserved 32h to 3Eh Lowest

SYSSNIV, System NMI 019Ch

No interrupt pending 00h

Reserved 02h Highest

Uncorrectable FRAM bit error detection 04h

Reserved 06h

MPUSEGPIFG encapsulated IP memory segment violation 08h

MPUSEGIIFG information memory segment violation 0Ah

MPUSEG1IFG segment 1 memory violation 0Ch

MPUSEG2IFG segment 2 memory violation 0Eh

MPUSEG3IFG segment 3 memory violation 10h

VMAIFG vacant memory access 12h

JMBINIFG JTAG mailbox input 14h

JMBOUTIFG JTAG mailbox output 16h

Correctable FRAM bit error detection 18h

Reserved 1Ah to 1Eh Lowest

SYSUNIV, User NMI 019Ah

No interrupt pending 00h

NMIIFG NMI pin 02h Highest

OFIFG oscillator fault 04h

Reserved 06h

Reserved 08h

Reserved 0Ah to 1Eh Lowest

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6.11.8 DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU

intervention. For example, the DMA controller can be used to move data from the ADC12_B conversion

memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA

controller reduces system power consumption by allowing the CPU to remain in sleep mode, without

having to awaken to move data to or from a peripheral. Table 6-10 lists the available DMA triggers.

(1) If a reserved trigger source is selected, no trigger is generated.

(2) Only on devices with AES. Reserved on devices without AES.

(3) Only on devices with ADC. Reserved on devices without ADC.

Table 6-10. DMA Trigger Assignments (1)

TRIGGER CHANNEL 0 CHANNEL 1 CHANNEL 2

0 DMAREQ DMAREQ DMAREQ

1 TA0CCR0 CCIFG TA0CCR0 CCIFG TA0CCR0 CCIFG

2 TA0CCR2 CCIFG TA0CCR2 CCIFG TA0CCR2 CCIFG

3 TA1CCR0 CCIFG TA1CCR0 CCIFG TA1CCR0 CCIFG

4 TA1CCR2 CCIFG TA1CCR2 CCIFG TA1CCR2 CCIFG

5 TA2 CCR0 CCIFG TA2 CCR0 CCIFG TA2 CCR0 CCIFG

6 TA3 CCR0 CCIFG TA3 CCR0 CCIFG TA3 CCR0 CCIFG

7 TB0CCR0 CCIFG TB0CCR0 CCIFG TB0CCR0 CCIFG

8 TB0CCR2 CCIFG TB0CCR2 CCIFG TB0CCR2 CCIFG

9 Reserved Reserved Reserved

10 Reserved Reserved Reserved

11 AES Trigger 0(2) AES Trigger 0(2) AES Trigger 0(2)

12 AES Trigger 1(2) AES Trigger 1(2) AES Trigger 1(2)

13 AES Trigger 2(2) AES Trigger 2(2) AES Trigger 2(2)

14 UCA0RXIFG UCA0RXIFG UCA0RXIFG

15 UCA0TXIFG UCA0TXIFG UCA0TXIFG

16 UCA1RXIFG UCA1RXIFG UCA1RXIFG

17 UCA1TXIFG UCA1TXIFG UCA1TXIFG

18 UCB0RXIFG (SPI)

UCB0RXIFG0 (I2C) UCB0RXIFG (SPI)

UCB0RXIFG0 (I2C)

19 UCB0TXIFG (SPI)

UCB0TXIFG0 (I2C) UCB0TXIFG (SPI)

UCB0TXIFG0 (I2C)

20 UCB0RXIFG1 (I2C) UCB0RXIFG1 (I2C) UCB0RXIFG1 (I2C)

21 UCB0TXIFG1 (I2C) UCB0TXIFG1 (I2C) UCB0TXIFG1 (I2C)

22 UCB0RXIFG2 (I2C) UCB0RXIFG2 (I2C) UCB0RXIFG2 (I2C)

23 UCB0TXIFG2 (I2C) UCB0TXIFG2 (I2C) UCB0TXIFG2 (I2C)

24 UCB1RXIFG (SPI)

UCB1RXIFG0 (I2C) UCB1RXIFG (SPI)

UCB1RXIFG0 (I2C)

25 UCB1TXIFG (SPI)

UCB1TXIFG0 (I2C) UCB1TXIFG (SPI)

UCB1TXIFG0 (I2C)

26 ADC12 end of conversion(3) ADC12 end of conversion(3) ADC12 end of

conversion(3)

27 Reserved Reserved Reserved

28 Reserved Reserved Reserved

29 MPY ready MPY ready MPY ready

30 DMA2IFG DMA0IFG DMA1IFG

31 DMAE0 DMAE0 DMAE0

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

(1) Only on devices with ADC

6.11.9 Enhanced Universal Serial Communication Interface (eUSCI)

The eUSCI modules are used for serial data communication. The eUSCI module supports synchronous

communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols

such as UART, enhanced UART with automatic baud-rate detection, and IrDA.

The eUSCI_An module provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.

The eUSCI_Bn module provides support for SPI (3 or 4 pin) and I2C.

Two eUSCI_A modules and two eUSCI_B modules are implemented.

6.11.10 Timer_A TA0, Timer_A TA1

TA0 and TA1 are 16-bit timers/counters (Timer_A type) with three capture/compare registers each. TA0

and TA1 can support multiple capture/compares, PWM outputs, and interval timing (see Table 6-11 and

Table 6-12). TA0 and TA1 have extensive interrupt capabilities. Interrupts may be generated from the

counter on overflow conditions and from each of the capture/compare registers.

Table 6-11. Timer_A TA0 Signal Connections

INPUT PORT PIN DEVICE INPUT

SIGNAL MODULE INPUT

SIGNAL MODULE

BLOCK

MODULE

OUTPUT

SIGNAL

DEVICE OUTPUT

SIGNAL OUTPUT PORT PIN

P1.2 or P7.0 TA0CLK TACLK

Timer N/A N/A

ACLK (internal) ACLK

SMCLK (internal) SMCLK

P1.2 or P7.0 TA0CLK INCLK

P1.5 TA0.0 CCI0A

CCR0 TA0 TA0.0

P1.5

P7.1 TA0.0 CCI0B P7.1

DVSS GND

DVCC VCC

P1.0 or P1.6 or

P7.2 TA0.1 CCI1A

CCR1 TA1 TA0.1

P1.0

P1.6

COUT (internal) CCI1B P7.2

DVSS GND ADC12 (internal) (1)

ADC12SHSx = {1}

DVCC VCC

P1.1 or P1.7 or

P7.3 TA0.2 CCI2A

CCR2 TA2 TA0.2

P1.1

ACLK (internal) CCI2B P1.7

DVSS GND P7.3

DVCC VCC

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

(1) Only on devices with ADC

Table 6-12. Timer_A TA1 Signal Connections

INPUT PORT PIN DEVICE INPUT

SIGNAL MODULE INPUT

SIGNAL MODULE

BLOCK

MODULE

OUTPUT

SIGNAL

DEVICE OUTPUT

SIGNAL OUTPUT PORT PIN

P1.1 or P4.4 TA1CLK TACLK

Timer N/A N/A

ACLK (internal) ACLK

SMCLK (internal) SMCLK

P1.1 or P4.4 TA1CLK INCLK

P1.4 or P4.5 TA1.0 CCI0A

CCR0 TA0 TA1.0

P1.4

DVSS CCI0B P4.5

DVSS GND

DVCC VCC

P1.2 or P3.3 or

P4.6 TA1.1 CCI1A

CCR1 TA1 TA1.1

P1.2

P4.6

COUT (internal) CCI1B P3.3

DVSS GND ADC12 (internal) (1)

ADC12SHSx = {4}

DVCC VCC

P1.3 or P4.7 TA1.2 CCI2A

CCR2 TA2 TA1.2

P1.3

ACLK (internal) CCI2B P4.7

DVSS GND

DVCC VCC

(1) Only on devices with ADC

6.11.11 Timer_A TA2

TA2 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers each and with internal

connections only. TA2 can support multiple capture/compares, PWM outputs, and interval timing (see

Table 6-13). TA2 has extensive interrupt capabilities. Interrupts may be generated from the counter on

overflow conditions and from each of the capture/compare registers.

Table 6-13. Timer_A TA2 Signal Connections

DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT

SIGNAL DEVICE OUTPUT SIGNAL

COUT (internal) TACLK

Timer N/A

ACLK (internal) ACLK

SMCLK (internal) SMCLK

From Capacitive Touch

I/O 0 (internal) INCLK

TA3 CCR0 output

(internal) CCI0A

CCR0 TA0

TA3 CCI0A input

ACLK (internal) CCI0B

DVSS GND

DVCC VCC

From Capacitive Touch

I/O 0 (internal) CCI1A

CCR1 TA1

ADC12 (internal) (1)

ADC12SHSx = {5}

COUT (internal) CCI1B

DVSS GND

DVCC VCC

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

(1) Only on devices with ADC.

6.11.12 Timer_A TA3

TA3 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers each and with internal

connections only. TA3 can support multiple capture/compares, PWM outputs, and interval timing (see

Table 6-14). TA3 has extensive interrupt capabilities. Interrupts may be generated from the counter on

overflow conditions and from each of the capture/compare registers.

Table 6-14. Timer_A TA3 Signal Connections

DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT

SIGNAL DEVICE OUTPUT SIGNAL

COUT (internal) TACLK

Timer N/A

ACLK (internal) ACLK

SMCLK (internal) SMCLK

From Capacitive Touch

I/O 1 (internal) INCLK

TA2 CCR0 output

(internal) CCI0A

CCR0 TA0

TA2 CCI0A input

ACLK (internal) CCI0B

DVSS GND

DVCC VCC

From Capacitive Touch

I/O 1 (internal) CCI1A

CCR1 TA1

ADC12 (internal) (1)

ADC12SHSx = {6}

COUT (internal) CCI1B

DVSS GND

DVCC VCC

DVSS CCI2A

CCR2 TA2

P3.0

DVSS (FR692x(1) and

FR682x(1) 64‑pin

package) CCI2B P3.0 (Note: Not available for

FR692x(1) and FR682x(1)

64-pin package devices)

DVSS GND

DVCC VCC

DVSS CCI3A

CCR3 TA3

P3.1

DVSS (FR692x(1) and

FR682x(1) 64‑pin

package) CCI3B P3.1 (Note: Not available for

FR692x(1) and FR682x(1)

64-pin package devices)

DVSS GND

DVCC VCC

DVSS CCI4A

CCR4 TA4

P3.2

DVSS (FR692x(1) and

FR682x(1) 64‑pin

package) CCI4B P3.2 (Note: Not available for

FR692x(1) and FR682x(1)

64-pin package devices)

DVSS GND

DVCC VCC

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

(1) Only on devices with ADC

6.11.13 Timer_B TB0

TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers each. TB0 can support

multiple capture/compares, PWM outputs, and interval timing (see Table 6-15). TB0 has extensive

interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each

of the capture/compare registers.

Table 6-15. Timer_B TB0 Signal Connections

INPUT PORT PIN DEVICE INPUT

SIGNAL MODULE INPUT

SIGNAL MODULE

BLOCK

MODULE

OUTPUT

SIGNAL

DEVICE OUTPUT

SIGNAL OUTPUT PORT PIN

P2.0 or P3.3 or

P5.7 TB0CLK TBCLK

Timer N/A N/A

ACLK (internal) ACLK

SMCLK (internal) SMCLK

P2.0 or P3.3 or

P5.7 TB0CLK INCLK

P3.4 TB0.0 CCI0A

CCR0 TB0 TB0.0

P3.4

P6.4 TB0.0 CCI0B P6.4

DVSS GND ADC12 (internal) (1)

ADC12SHSx = {2}

DVCC VCC

P3.5 or P6.5 TB0.1 CCI1A

CCR1 TB1 TB0.1

P3.5

COUT (internal) CCI1B P6.5

DVSS GND ADC12 (internal) (1)

ADC12SHSx = {3}

DVCC VCC

P3.6 or P6.6 TB0.2 CCI2A

CCR2 TB2 TB0.2

P3.6

ACLK (internal) CCI2B P6.6

DVSS GND

DVCC VCC

DVSS CCI3A

CCR3 TB3 TB0.3

P3.7 TB0.3 CCI3B P3.7

DVSS GND

DVCC VCC

DVSS CCI4A

CCR4 TB4 TB0.4

P2.2 TB0.4 CCI4B P2.2

DVSS GND

DVCC VCC

DVSS CCI5A

CCR5 TB5 TB0.5

P2.1 TB0.5 CCI5B P2.1

DVSS GND

DVCC VCC

DVSS CCI6A

CCR6 TB6 TB0.6

P2.0 TB0.6 CCI6B P2.0

DVSS GND

DVCC VCC

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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6.11.14 ADC12_B

The ADC12_B module supports fast 12-bit analog-to-digital conversions with differential and single-ended

inputs. The module implements a 12-bit SAR core, sample select control, reference generator and a

conversion result buffer. A window comparator with a lower and upper limits allows CPU-independent

result monitoring with three window comparator interrupt flags.

Table 6-16 summarizes the available external trigger sources.

Table 6-17 lists the available multiplexing between internal and external analog inputs.

Table 6-16. ADC12_B Trigger Signal Connections

ADC12SHSx CONNECTED TRIGGER

SOURCE

BINARY DECIMAL

000 0 Software (ADC12SC)

001 1 Timer_A TA0 CCR1 output

010 2 Timer_B TB0 CCR0 output

011 3 Timer_B TB0 CCR1 output

100 4 Timer_A TA1 CCR1 output

101 5 Timer_A TA2 CCR1 output

110 6 Timer_A TA3 CCR1 output

111 7 Reserved (DVSS)

(1) N/A: No internal signal available on this device.

Table 6-17. ADC12_B External and Internal Signal Mapping

CONTROL BIT EXTERNAL

(CONTROL BIT = 0) INTERNAL

(CONTROL BIT = 1)

ADC12BATMAP A31 Battery monitor

ADC12TCMAP A30 Temperature sensor

ADC12CH0MAP A29 N/A(1)

ADC12CH1MAP A28 N/A(1)

ADC12CH2MAP A27 N/A(1)

ADC12CH3MAP A26 N/A(1)

6.11.15 Comparator_E

The primary function of the Comparator_E module is to support precision slope analog-to-digital

conversions, battery voltage supervision, and monitoring of external analog signals.

6.11.16 CRC16

The CRC16 module produces a signature based on a sequence of entered data values and can be used

for data checking purposes. The CRC16 signature is based on the CRC-CCITT standard.

6.11.17 CRC32

The CRC32 module produces a signature based on a sequence of entered data values and can be used

for data checking purposes. The CRC32 signature is based on the ISO 3309 standard.

6.11.18 AES256 Accelerator

The AES accelerator module performs encryption and decryption of 128-bit data with 128-, 192-, or 256-

bit keys according to the advanced encryption standard (AES) (FIPS PUB 197) in hardware.

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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6.11.19 True Random Seed

The Device Descriptor Info (TLV) (see Section 6.12) contains a 128-bit true random seed that can be used

to implement a deterministic random-number generator.

6.11.20 Shared Reference (REF_A)

The REF_A module is responsible for generation of all critical reference voltages that can be used by the

various analog peripherals in the device.

6.11.21 LCD_C

The LCD_C driver generates the segment and common signals required to drive a liquid crystal display

(LCD). The LCD_C controller has dedicated data memories to hold segment drive information. Common

and segment signals are generated as defined by the mode. Static, and 2-mux up to 4-mux LCDs are

supported. The module can provide an LCD voltage independent of the supply voltage with its integrated

charge pump. It is possible to control the level of the LCD voltage and thus contrast by software. The

module also provides an automatic blinking capability for individual segments in static, 2-mux, 3-mux, and

4-mux modes.

To reduce system noise the charge pump can be temporarily disabled. Table 6-18 lists the available

automatic charge pump disable options.

Table 6-18. LCD Automatic Charge Pump Disable Bits (LCDCPDISx)

CONTROL BIT DESCRIPTION

LCDCPDIS0 LCD charge pump disable during ADC12 conversion.

0b = LCD charge pump not automatically disabled during conversion

1b = LCD charge pump automatically disabled during conversion

LCDCPDIS1 to LCDCPDIS7 No functionality

6.11.22 Embedded Emulation

6.11.22.1 Embedded Emulation Module (EEM)

The EEM supports real-time in-system debugging. The S version of the EEM has the following features:

• Three hardware triggers or breakpoints on memory access

• One hardware trigger or breakpoint on CPU register write access

• Up to four hardware triggers that can be combined to form complex triggers or breakpoints

• One cycle counter

• Clock control on module level

6.11.22.2 EnergyTrace++ Technology

The devices implement circuitry to support EnergyTrace++ technology. The EnergyTrace++ technology

lets you observe information about the internal states of the microcontroller. These states include the CPU

Program Counter (PC), the ON or OFF status of the peripherals and the system clocks (regardless of the

clock source), and the low-power mode currently in use. These states can always be read by a debug

tool, even when the microcontroller sleeps in LPMx.5 modes.

The activity of the following modules can be observed:

• MPY is calculating.

• WDT is counting.

• RTC is counting.

• ADC: a sequence, sample, or conversion is active.

• REF: REFBG or REFGEN active and BG in static mode.

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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• COMP is on.

• AES is encrypting or decrypting.

• eUSCI_A0 is transferring (receiving or transmitting) data.

• eUSCI_A1 is transferring (receiving or transmitting) data.

• eUSCI_B0 is transferring (receiving or transmitting) data.

• eUSCI_B1 is transferring (receiving or transmitting) data.

• TB0 is counting.

• TA0 is counting.

• TA1 is counting.

• TA2 is counting.

• TA3 is counting.

• LCD timing generator is active.

Px.y/Mod1/Mod2/Mod3/Sz

PxSEL1.y

PxDIR.y

PxIN.y

To module 1(A)

To module 2(A)

To module 3(A)

From module 1

PxOUT.y

DVSS

DVCC 1

Pad Logic

Direction

0: Input

1: Output

PxREN.y

0 1

0 0

1 0

1 1

PxSEL0.y

0 1

0 0

1 0

1 1

From module 2

From module 2(B)

From module 1(B)

From module 3(B)

From module 3

LCDSz

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

6.11.23 Input/Output Diagrams

6.11.23.1 Digital I/O Functionality Port P1 to P7 and P9

The port pins provide the following features:

• Interrupt and wakeup from LPMx.5 capability for ports P1 to P4

• Capacitive touch functionality (see Section 6.11.23.2)

• Up to three digital module input and/or output functions

• LCD segment functionality (not all pins, package dependent)

Figure 6-1 shows the features and the corresponding control logic (besides the Capacitive Touch logic).

Figure 6-1 is applicable for all port pins P1.0 to P9.7, unless a dedicated diagram is available in the

following sections. The module functions provided per pin and whether the direction is controlled by the

module or by the port direction register for the selected secondary function are described in the following

pin function tables.

A. The direction is either controlled by connected module or by the corresponding PxDIR.y bit. See pin function tables.

B. The inputs from several pins towards a module are ORed together.

NOTE: Functional representation only.

Figure 6-1. General Port Pin Diagram

PxREN.y

PxOUT.y

Direction Control

Analog Enable

Capacitive Touch Enable 0

Output Signal

DVSS

DVCC

Input Signal

Px.y

Capacitive Touch Signal 0

Capacitive Touch Signal 1

Capacitive Touch Enable 1

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

6.11.23.2 Capacitive Touch Functionality on Port P1 to P7, P9, and PJ

Figure 6-2 shows the the capacitive touch functionality that is available on all port pins. The capacitive

touch functionality is controlled using the capacitive touch I/O control registers CAPTIO0CTL and

CAPTIO1CTL as described in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and

MSP430FR69xx Family User's Guide. The capacitive touch functionality is not shown in the other pin

diagrams.

NOTE: Functional representation only.

Figure 6-2. Capacitive Touch I/O Functionality

P1.0/TA0.1/DMAE0/RTCCLK/

A0/C0/VREF-/VeREF-

P1.1/TA0.2/TA1CLK/COUT/

A1/C1/VREF+/VeREF+

P1.2/TA1.1/TA0CLK/COUT/A2/C2

P1.3/TA1.2/A3/C3

P1SEL1.x

P1DIR.x

P1IN.x

DVSS

P1OUT.x

DVSS

DVCC 1

To Comparator

From Comparator

Pad Logic

To ADC

From ADC

Bus

Keeper

Direction

0: Input

1: Output

CEPD.x

P1REN.x

0 1

0 0

1 0

1 1

P1SEL0.x

0 1

0 0

1 0

1 1

DVSS

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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6.11.23.3 Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger

Figure 6-3 shows the port diagram. Table 6-19 summarizes the selection of the pin functions.

NOTE: Functional representation only.

Figure 6-3. Port P1 (P1.0 to P1.3) Diagram

MSP430FR6972

MSP430FR69721

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MSP430FR6872

MSP430FR68721

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MSP430FR6922

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(1) X = Don't care

(2) Do not use this pin as RTCCLK output if the DMAE0 functionality is used on any other pin. Select an alternative RTCCLK output pin.

(3) Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

(4) Setting the CEPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module

automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPD.x bit.

(5) Do not use this pin as COUT output if the TA1CLK functionality is used on any other pin. Select an alternative COUT output pin.

Table 6-19. Port P1 (P1.0 to P1.3) Pin Functions

PIN NAME (P1.x) x FUNCTION CONTROL BITS OR SIGNALS (1)

P1DIR.x P1SEL1.x P1SEL0.x

P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/

VREF-/VeREF- 0 P1.0 (I/O) I: 0; O: 1 0 0

TA0.CCI1A 0 0 1

TA0.1 1

DMAE0 0 1 0

RTCCLK(2) 1

A0, C0, VREF-, VeREF- (3) (4) X 1 1

P1.1/TA0.2/TA1CLK/COUT/A1/C1/

VREF+/VeREF+ 1 P1.1 (I/O) I: 0; O: 1 0 0

TA0.CCI2A 0 0 1

TA0.2 1

TA1CLK 0 1 0

COUT(5) 1

A1, C1, VREF+, VeREF+ (3) (4) X 1 1

P1.2/TA1.1/TA0CLK/COUT/A2/C2 2 P1.2 (I/O) I: 0; O: 1 0 0

TA1.CCI1A 0 0 1

TA1.1 1

TA0CLK 0 1 0

COUT(5) 1

A2, C2 (3) (4) X 1 1

P1.3/TA1.2/A3/C3 3 P1.3 (I/O) I: 0; O: 1 0 0

TA1.CCI2A 0 0 1

TA1.2 1

N/A 0 1 0

Internally tied to DVSS 1

A3, C3 (3) (4) X 1 1

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

(1) X = Don't care

(2) Direction controlled by eUSCI_B0 module.

(3) Direction controlled by eUSCI_A0 module.

(4) Associated LCD segment is package dependent. See the pin diagrams and signal descriptions in Section 4.

6.11.23.4 Port P1 (P1.4 to P1.7) Input/Output With Schmitt Trigger

For the port diagram, see Figure 6-1.Table 6-20 summarizes the selection of the pin functions.

Table 6-20. Port P1 (P1.4 to P1.7) Pin Functions

PIN NAME (P1.x) x FUNCTION CONTROL BITS OR SIGNALS (1)

P1DIR.x P1SEL1.x P1SEL0.x LCDSz

P1.4/UCB0CLK/UCA0STE/TA1.0/Sz 4 P1.4 (I/O) I: 0; O: 1 0 0 0

UCB0CLK X (2) 010

UCA0STE X (3) 100

TA1.CCI0A 0 110

TA1.0 1

Sz (4) X X X 1

P1.5/UCB0STE/UCA0CLK/TA0.0/Sz 5 P1.5 (I/O) I: 0; O: 1 0 0 0

UCB0STE X (2) 010

UCA0CLK X (3) 100

TA0.CCI0A 0 110

TA0.0 1

Sz (4) X X X 1

P1.6/UCB0SIMO/UCB0SDA/TA0.1/

Sz 6 P1.6 (I/O) I: 0; O: 1 0 0 0

UCB0SIMO/UCB0SDA X (2) 010

N/A 0 100

Internally tied to DVSS 1

TA0.CCI1A 0 110

TA0.1 1

Sz (4) X X X 1

P1.7/UCB0SOMI/UCB0SCL/TA0.2/

Sz 7 P1.7 (I/O) I: 0; O: 1 0 0 0

UCB0SOMI/UCB0SCL X (2) 010

N/A 0 100

Internally tied to DVSS 1

TA0.CCI2A 0 110

TA0.2 1

Sz (4) X X X 1

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

(1) X = Don't care

(2) Direction controlled by eUSCI_A0 module.

(3) Associated LCD segment is package dependent. See the pin diagrams and signal descriptions in Section 4.

6.11.23.5 Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger

For the port diagram, see Figure 6-1.Table 6-21 summarizes the selection of the pin functions.

Table 6-21. Port P2 (P2.0 to P2.3) Pin Functions

PIN NAME (P2.x) x FUNCTION CONTROL BITS OR SIGNALS (1)

P2DIR.x P2SEL1.x P2SEL0.x LCDSz

P2.0/UCA0SIMO/UCA0TXD/TB0.6/

TB0CLK/Sz 0 P2.0 (I/O) I: 0; O: 1 0 0 0

UCA0SIMO/UCA0TXD X (2) 010

TB0.CCI6B 0 100

TB0.6 1

TB0CLK 0 110

Internally tied to DVSS 1

Sz (3) X X X 1

P2.1/UCA0SOMI/UCA0RXD/TB0.5/

DMAE0/Sz 1 P2.1 (I/O) I: 0; O: 1 0 0 0

UCA0SOMI/UCA0RXD X (2) 010

TB0.CCI5B 0 100

TB0.5 1

DMA0E 0 110

Internally tied to DVSS 1

Sz (3) X X X 1

P2.2/UCA0CLK/TB0.4/RTCCLK/Sz 2 P2.2 (I/O) I: 0; O: 1 0 0 0

UCA0CLK X (2) 010

TB0.CCI4B 0 100

TB0.4 1

N/A 0 110

RTCCLK 1

Sz (3) X X X 1

P2.3/UCA0STE/TB0OUTH/Sz 3 P2.3 (I/O) I: 0; O: 1 0 0 0

UCA0STE X (2) 010

TB0OUTH 0 100

Internally tied to DVSS 1

N/A 0 110

Internally tied to DVSS 1

Sz (3) X X X 1

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

(1) X = Don't care

(2) Direction controlled by eUSCI_B1 module.

(3) Associated LCD segment is package dependent. See the pin diagrams and signal descriptions in Section 4.

6.11.23.6 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger

For the port diagram, see Figure 6-1.Table 6-22 and Table 6-23 summarize the selection of the pin

functions.

Table 6-22. Port P3 (P3.0 to P3.3) Pin Functions

PIN NAME (P3.x) x FUNCTION CONTROL BITS OR SIGNALS (1)

P3DIR.x P3SEL1.x P3SEL0.x LCDSz

P3.0/UCB1CLK/Sz 0 P3.0 (I/O) I: 0; O: 1 0 0 0

UCB1CLK X (2) 010

TA3.CCI2B (Note: not available for

FR692x(1) and FR682x(1) 64-pin

package devices) 0

100

TA3.2

Internally tied to DVSS (for FR692x(1)

and FR682x(1) 64-pin package devices) 1

N/A 0 110

Internally tied to DVSS 1

Sz (3) X X X 1

P3.1/UCB1SIMO/UCB1SDA/Sz 1 P3.1 (I/O) I: 0; O: 1 0 0 0

UCB1SIMO/UCB1SDA X (2) 010

TA3.CCI3B (Note: not available for

FR692x(1) and FR682x(1) 64-pin

package devices) 0

100

TA3.3

Internally tied to DVSS (for FR692x(1)

and FR682x(1) 64-pin package devices) 1

N/A 0 110

Internally tied to DVSS 1

Sz (3) X X X 1

P3.2/UCB1SOMI/UCB1SCL/Sz 2 P3.2 (I/O) I: 0; O: 1 0 0 0

UCB1SOMI/UCB1SCL X (2) 010

TA3.CCI4B (Note: not available for

FR692x(1) and FR682x(1) 64-pin

package devices) 0

100

TA3.4

Internally tied to DVSS (for FR692x(1)

and FR682x(1) 64-pin package devices) 1

0110

Sz (3) X X X 1

P3.3/TA1.1/TB0CLK/Sz 3 P3.3 (I/O) I: 0; O: 1 0 0 0

N/A 0 010

Internally tied to DVSS 1

TA1.CCI1A 0 100

TA1.1 1

TB0CLK 0 110

Internally tied to DVSS 1

Sz (3) X X X 1

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

(1) X = Don't care

(2) Direction controlled by eUSCI_A1 module.

(3) Associated LCD segment is package dependent. See the pin diagrams and signal descriptions in Section 4.

Table 6-23. Port P3 (P3.4 to P3.7) Pin Functions

PIN NAME (P3.x) x FUNCTION CONTROL BITS OR SIGNALS (1)

P3DIR.x P3SEL1.x P3SEL0.x LCDSz

P3.4/UCA1SIMO/UCA1TXD/TB0.0/

Sz 4 P3.4 (I/O) I: 0; O: 1 0 0 0

UCA1SIMO/UCA1TXD X (2) 010

TB0CCI0A 0 100

TB0.0 1

N/A 0 110

Internally tied to DVSS 1

Sz (3) X X X 1

P3.5/UCA1SOMI/UCA1RXD/TB0.1/

Sz 5 P3.5 (I/O) I: 0; O: 1 0 0 0

UCA1SOMI/UCA1RXD X (2) 010

TB0CCI1A 0 100

TB0.1 1

N/A 0 110

Internally tied to DVSS 1

Sz (3) X X X 1

P3.6/UCA1CLK/TB0.2/Sz 6 P3.6 (I/O) I: 0; O: 1 0 0 0

UCA1CLK X (2) 010

TB0CCI2A 0 100

TB0.2 1

N/A 0 110

Internally tied to DVSS 1

Sz (3) X X X 1

P3.7/UCA1STE/TB0.3/Sz 7 P3.7 (I/O) I: 0; O: 1 0 0 0

UCA1STE X (2) 010

TB0CCI3B 0 100

TB0.3 1

N/A 0 110

Internally tied to DVSS 1

Sz (3) X X X 1

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

(1) X = Don't care

(2) Direction controlled by eUSCI_A0 module.

(3) Direction controlled by eUSCI_B1 module.

(4) Associated LCD segment is package dependent. See the pin diagrams and signal descriptions in Section 4.

6.11.23.7 Port P4 (P4.2 to P4.7) Input/Output With Schmitt Trigger

For the port diagram, see Figure 6-1.Table 6-24 and Table 6-25 summarize the selection of the pin

functions.

Table 6-24. Port P4 (P4.2 and P4.3) Pin Functions

PIN NAME (P4.x) x FUNCTION CONTROL BITS OR SIGNALS (1)

P4DIR.x P4SEL1.x P4SEL0.x LCDSz

P4.2/UCA0SIMO/UCA0TXD/

UCB1CLK/Sz 2 P4.2 (I/O) I: 0; O: 1 0 0 0

UCA0SIMO/UCA0TXD X (2) 010

UCB1CLK X (3) 100

N/A 0 110

Internally tied to DVSS 1

Sz (4) X X X 1

P4.3/UCA0SOMI/UCA0RXD/

UCB1STE/Sz 3 P4.3 (I/O) I: 0; O: 1 0 0 0

UCA0SOMI/UCA0RXD X (2) 010

UCB1STE X (3) 100

N/A 0 110

Internally tied to DVSS 1

Sz (4) X X X 1

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

(1) X = Don't care

(2) Direction controlled by eUSCI_B1 module.

(3) Associated LCD segment is package dependent. See the pin diagrams and signal descriptions in Section 4.

Table 6-25. Port P4 (P4.4 to P4.7) Pin Functions

PIN NAME (P4.x) x FUNCTION CONTROL BITS OR SIGNALS (1)

P4DIR.x P4SEL1.x P4SEL0.x LCDSz

P4.4/UCB1STE/TA1CLK/Sz 4 P4.4 (I/O) I: 0; O: 1 0 0 0

N/A 0 010

Internally tied to DVSS 1

UCB1STE X (2) 100

TA1CLK 0 110

Internally tied to DVSS 1

Sz (3) X X X 1

P4.5/UCB1CLK/TA1.0/Sz 5 P4.5 (I/O) I: 0; O: 1 0 0 0

N/A 0 010

Internally tied to DVSS 1

UCB1CLK X (2) 100

TA1CCI0A 0 110

TA1.0 1

Sz (3) X X X 1

P4.6/UCB1SIMO/UCB1SDA/TA1.1/

Sz 6 P4.6 (I/O) I: 0; O: 1 0 0 0

N/A 0 010

Internally tied to DVSS 1

UCB1SIMO/UCB1SDA X (2) 100

TA1CCI1A 0 110

TA1.1 1

Sz (3) X X X 1

P4.7/UCB1SOMI/UCB1SCL/TA1.2/

Sz 7 P4.7 (I/O) I: 0; O: 1 0 0 0

N/A 0 010

Internally tied to DVSS 1

UCB1SOMI/UCB1SCL X (2) 100

TA1CCI2A 0 110

TA1.2 1

Sz (3) X X X 1

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

(1) X = Don't care

(2) Direction controlled by eUSCI_A1 module.

(3) Associated LCD segment is package dependent. See the pin diagrams and signal descriptions in Section 4.

6.11.23.8 Port P5 (P5.4 to P5.7) Input/Output With Schmitt Trigger

For the port diagram, see Figure 6-1.Table 6-26 summarizes the selection of the pin functions.

Table 6-26. Port P5 (P5.4 to P5.7) Pin Functions

PIN NAME (P5.x) x FUNCTION CONTROL BITS OR SIGNALS (1)

P5DIR.x P5SEL1.x P5SEL0.x LCDSz

P5.4/UCA1SIMO/UCA1TXD/Sz 4 P5.4 (I/O) I: 0; O: 1 0 0 0

UCA1SIMO/UCA1TXD X (2) 010

N/A 0 100

Internally tied to DVSS 1

N/A 0 110

Internally tied to DVSS 1

Sz (3) X X X 1

P5.5/UCA1SOMI/UCA1RXD/Sz 5 P5.5 (I/O) I: 0; O: 1 0 0 0

UCA1SOMI/UCA1RXD X (2) 010

N/A 0 100

Internally tied to DVSS 1

N/A 0 110

Internally tied to DVSS 1

Sz (3) X X X 1

P5.6/UCA1CLK/Sz 6 P5.6 (I/O) I: 0; O: 1 0 0 0

UCA1CLK X (2) 010

N/A 0 100

Internally tied to DVSS 1

N/A 0 110

Internally tied to DVSS 1

Sz (3) X X X 1

P5.7/UCA1STE/TB0CLK/Sz 7 P5.7 (I/O) I: 0; O: 1 0 0 0

UCA1STE X (2) 010

N/A 0 100

Internally tied to DVSS 1

TB0CLK 0 110

Internally tied to DVSS 1

Sz (3) X X X 1

P6.0/R23

P6.1/R13/LCDREF

P6.2/COUT/R03

P6.3/COM0

P6.4/TB0.0/COM1

P6.5/TB0.1/COM2

P6.6/TB0.2/COM3

P6SEL1.x

P6DIR.x

P6IN.x

From module 1

P6OUT.x

DVSS

DVCC 1

To/From

LCD module

Pad Logic

Bus

Keeper

Direction

0: Input

1: Output

P6REN.x

0 1

0 0

1 0

1 1

P6SEL0.x

0 1

0 0

1 0

1 1

From module 2

DVSS

To module 1(A)

To module 2(A)

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

6.11.23.9 Port P6 (P6.0 to P6.6) Input/Output With Schmitt Trigger

Figure 6-4 shows the port diagram. Table 6-27 and Table 6-28 summarize the selection of the pin

functions.

NOTE: Functional representation only.

Figure 6-4. Port P6 (P6.0 to P6.6) Diagram

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721

MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

(1) X = Don't care

(2) Setting P6SEL1.x and P6SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

Table 6-27. Port P6 (P6.0 to P6.2) Pin Functions

PIN NAME (P6.x) x FUNCTION CONTROL BITS OR SIGNALS (1)

P6DIR.x P6SEL1.x P6SEL0.x

P6.0/R23 0 P6.0 (I/O) I: 0; O: 1 0 0

N/A 0 0 1

Internally tied to DVSS 1

N/A 0 1 0

Internally tied to DVSS 1

R23 (2) X 1 1

P6.1/R13/LCDREF 1 P6.1 (I/O) I: 0; O: 1 0 0

N/A 0 0 1

Internally tied to DVSS 1

N/A 0 1 0

Internally tied to DVSS 1

R13/LCDREF (2) X 1 1

P6.2/COUT/R03 2 P6.2 (I/O) I: 0; O: 1 0 0

N/A 0 0 1

COUT 1

N/A 0 1 0

Internally tied to DVSS 1

R03 (2) X 1 1

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

(1) X = Don't care

(2) Setting P6SEL1.x and P6SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

Table 6-28. Port P6 (P6.3 to P6.6) Pin Functions

PIN NAME (P6.x) x FUNCTION CONTROL BITS OR SIGNALS (1)

P6DIR.x P6SEL1.x P6SEL0.x

P6.3/COM0 3 P6.3 (I/O) I: 0; O: 1 0 0

N/A 0 0 1

Internally tied to DVSS 1

N/A 0 1 0

Internally tied to DVSS 1

COM0(2) X 1 1

P6.4/TB0.0/COM1 4 P6.4 (I/O) I: 0; O: 1 0 0

TB0CCI0B 0 0 1

TB0.0 1

N/A 0 1 0

Internally tied to DVSS 1

COM1(2) X 1 1

P6.5/TB0.1/COM2 5 P6.5 (I/O) I: 0; O: 1 0 0

TB0CCI1A 0 0 1

TB0.1 1

N/A 0 1 0

Internally tied to DVSS 1

COM2(2) X 1 1

P6.6/TB0.2/COM3 6 P6.6 (I/O) I: 0; O: 1 0 0

TB0CCI2A 0 0 1

TB0.2 1

N/A 0 1 0

Internally tied to DVSS 1

COM3(2) X 1 1

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

(1) X = Don't care

(2) Associated LCD segment is package dependent. See the pin diagrams and signal descriptions in Section 4.

6.11.23.10 Port P7 (P7.0 to P7.4) Input/Output With Schmitt Trigger

For the port diagram, see Figure 6-1.Table 6-29 and Table 6-30 summarize the selection of the pin

functions.

Table 6-29. Port P7 (P7.0 to P7.3) Pin Functions

PIN NAME (P7.x) x FUNCTION CONTROL BITS OR SIGNALS (1)

P7DIR.x P7SEL1.x P7SEL0.x LCDSz

P7.0/TA0CLK/Sz 0 P7.0 (I/O) I: 0; O: 1 0 0 0

TA0CLK 0 010

Internally tied to DVSS 1

N/A 0 100

Internally tied to DVSS 1

N/A 0 110

Internally tied to DVSS 1

Sz (2) X X X 1

P7.1/TA0.0/ACLK/Sz 1 P7.1 (I/O) I: 0; O: 1 0 0 0

TA0CCI0B 0 010

TA0.0 1

N/A 0 100

Internally tied to DVSS 1

N/A 0 110

ACLK 1

Sz (2) X X X 1

P7.2/TA0.1/Sz 2 P7.2 (I/O) I: 0; O: 1 0 0 0

TA0CCI1A 0 010

TA0.1 1

N/A 0 100

Internally tied to DVSS 1

N/A 0 110

N/A 1

Sz (2) X X X 1

P7.3/TA0.2/Sz 3 P7.3 (I/O) I: 0; O: 1 0 0 0

TA0CCI2A 0 010

TA0.2 1

N/A 0 100

Internally tied to DVSS 1

N/A 0 110

Internally tied to DVSS 1

Sz (2) X X X 1

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

(1) X = Don't care

(2) Associated LCD segment is package dependent. See the pin diagrams and signal descriptions in Section 4.

Table 6-30. Port P7 (P7.4) Pin Functions

PIN NAME (P7.x) x FUNCTION CONTROL BITS OR SIGNALS (1)

P7DIR.x P7SEL1.x P7SEL0.x LCDSz

P7.4/SMCLK/Sz 4 P7.4 (I/O) I: 0; O: 1 0 0 0

N/A 0 010

Internally tied to DVSS 1

N/A 0 100

Internally tied to DVSS 1

N/A 0 110

SMCLK 1

Sz (2) X X X 1

P9.4/A12/C12

P9.5/A13/C13

P9.6/A14/C14

P9.7/A15/C15

P9SEL1.x

P9DIR.x

P9IN.x

DVSS

P9OUT.x

DVSS

DVCC 1

To Comparator

From Comparator

Pad Logic

To ADC

From ADC

Bus

Keeper

Direction

0: Input

1: Output

CEPD.x

P9REN.x

0 1

0 0

1 0

1 1

P9SEL0.x

0 1

0 0

1 0

1 1

DVSS

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

6.11.23.11 Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger

Figure 6-5 shows the port diagram. Table 6-31 summarizes the selection of the pin functions.

NOTE: Functional representation only.

Figure 6-5. Port P9 (P9.4 to P9.7) Diagram

100

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

(1) X = Don't care

(2) Setting P9SEL1.x and P9SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

(3) Setting the CEPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module

automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPD.x bit.

Table 6-31. Port P9 (P9.4 to P9.7) Pin Functions

PIN NAME (P9.x) x FUNCTION CONTROL BITS OR SIGNALS (1)

P9DIR.x P9SEL1.x P9SEL0.x

P9.4/A12/C12 4 P9.4 (I/O) I: 0; O: 1 0 0

N/A 0 0 1

Internally tied to DVSS 1

N/A 0 1 0

Internally tied to DVSS 1

A12/C12 (2) (3) X 1 1

P9.5/A13/C13 5 P9.5 (I/O) I: 0; O: 1 0 0

N/A 0 0 1

Internally tied to DVSS 1

N/A 0 1 0

Internally tied to DVSS 1

A13/C13 (2) (3) X 1 1

P9.6/A14/C14 6 P9.6 (I/O) I: 0; O: 1 0 0

N/A 0 0 1

Internally tied to DVSS 1

N/A 0 1 0

Internally tied to DVSS 1

A14/C14 (2) (3) X 1 1

P9.7/A15/C15 7 P9.7 (I/O) I: 0; O: 1 0 0

N/A 0 0 1

Internally tied to DVSS 1

N/A 0 1 0

Internally tied to DVSS 1

A15/C15 (2) (3) X 1 1

PJ.4/LFXIN

PJSEL1.4

PJDIR.4

PJIN.4

To modules

DVSS

PJOUT.4

DVSS

DVCC 1

To LFXT XIN

Pad Logic

Bus

Keeper

Direction

0: Input

1: Output

PJREN.4

0 1

0 0

1 0

1 1

PJSEL0.4

0 1

0 0

1 0

1 1

DVSS

101

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

6.11.23.12 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger

Figure 6-6 and Figure 6-7 show the port diagrams. Table 6-32 summarizes the selection of the pin

functions.

NOTE: Functional representation only.

Figure 6-6. Port PJ (PJ.4) Diagram

PJ.5/LFXOUT

PJSEL1.5

PJDIR.5

PJIN.5

To modules

DVSS

PJOUT.5

DVSS

DVCC 1

To LFXT XOUT

Pad Logic

Bus

Keeper

Direction

0: Input

1: Output

PJREN.5

0 1

0 0

1 0

1 1

PJSEL0.5

0 1

0 0

1 0

1 1

DVSS

PJSEL1.4

PJSEL0.4

LFXTBYPASS

102

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

NOTE: Functional representation only.

Figure 6-7. Port PJ (PJ.5) Diagram

103

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

(1) X = Don't care

(2) Setting PJSEL1.4 = 0 and PJSEL0.4 = 1 causes the general-purpose I/O to be disabled. When LFXTBYPASS = 0, PJ.4 and PJ.5 are

configured for crystal operation and PJSEL1.5 and PJSEL0.5 are don't care. When LFXTBYPASS = 1, PJ.4 is configured for bypass

operation and PJ.5 is configured as general-purpose I/O.

(3) When PJ.4 is configured in bypass mode, PJ.5 is configured as general-purpose I/O.

(4) With PJSEL0.5 = 1 or PJSEL1.5 =1 the general-purpose I/O functionality is disabled. No input function is available. Configured as

output, the pin is actively pulled to zero.

Table 6-32. Port PJ (PJ.4 and PJ.5) Pin Functions

PIN NAME (PJ.x) x FUNCTION CONTROL BITS OR SIGNALS (1)

PJDIR.x PJSEL1.5 PJSEL0.5 PJSEL1.4 PJSEL0.4 LFXTBYPASS

PJ.4/LFXIN 4 PJ.4 (I/O) I: 0; O: 1 X X 0 0 X

N/A 0 X X 1 X X

Internally tied to DVSS 1

LFXIN crystal mode (2) X X X 0 1 0

LFXIN bypass mode (2) X X X 0 1 1

PJ.5/LFXOUT 5 PJ.5 (I/O) I: 0; O: 1 0 0 0 0 0

1 X

X X 1(3)

N/A 0 See (4) See (4) 0 0 0

1 X

X X 1(3)

Internally tied to DVSS 1 See (4) See (4) 0 0 0

1 X

X X 1(3)

LFXOUT crystal mode

(2) X X X 0 1 0

PJ.6/HFXIN

PJSEL1.6

PJDIR.6

PJIN.6

To modules

DVSS

PJOUT.6

DVSS

DVCC 1

To HFXT XIN

Pad Logic

Bus

Keeper

Direction

0: Input

1: Output

PJREN.6

0 1

0 0

1 0

1 1

PJSEL0.6

0 1

0 0

1 0

1 1

DVSS

104

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

6.11.23.13 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger

Figure 6-8 and Figure 6-9 show the port diagrams. Table 6-33 summarizes the selection of the pin

functions.

NOTE: Functional representation only.

Figure 6-8. Port PJ (PJ.6) Diagram

PJ.7/HFXOUT

PJSEL1.7

PJDIR.7

PJIN.7

To modules

DVSS

PJOUT.7

DVSS

DVCC 1

To HFXT XOUT

Pad Logic

Bus

Keeper

Direction

0: Input

1: Output

PJREN.7

0 1

0 0

1 0

1 1

PJSEL0.7

0 1

0 0

1 0

1 1

DVSS

PJSEL1.6

HFXTBYPASS

PJSEL0.6

105

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

NOTE: Functional representation only.

Figure 6-9. Port PJ (PJ.7) Diagram

106

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

(1) X = Don't care

(2) Setting PJSEL1.6 = 0 and PJSEL0.6 = 1 causes the general-purpose I/O to be disabled. When HFXTBYPASS = 0, PJ.6 and PJ.7 are

configured for crystal operation and PJSEL1.6 and PJSEL0.7 are don't care. When HFXTBYPASS = 1, PJ.6 is configured for bypass

operation and PJ.7 is configured as general-purpose I/O.

(3) When PJ.6 is configured in bypass mode, PJ.7 is configured as general-purpose I/O.

(4) With PJSEL0.7 = 1 or PJSEL1.7 = 1 the general-purpose I/O functionality is disabled. No input function is available. Configured as

output, the pin is actively pulled to zero.

Table 6-33. Port PJ (PJ.6 and PJ.7) Pin Functions

PIN NAME (PJ.x) x FUNCTION CONTROL BITS OR SIGNALS (1)

PJDIR.x PJSEL1.7 PJSEL0.7 PJSEL1.6 PJSEL0.6 HFXTBYPASS

PJ.6/HFXIN 6 PJ.6 (I/O) I: 0; O: 1 X X 0 0 X

N/A 0 X X 1 X X

Internally tied to DVSS 1

HFXIN crystal mode(2) X X X 0 1 0

HFXIN bypass mode(2) X X X 0 1 1

PJ.7/HFXOUT 7 PJ.7 (I/O) I: 0; O: 1 0 0 0 0 0

1 X

X X 1(3)

N/A 0 See (4) See (4) 0 0 0

1 X

X X 1(3)

Internally tied to DVSS 1 See (4) See (4) 0 0 0

1 X

X X 1(3)

HFXOUT crystal mode(2) X X X 0 1 0

PJ.0/TDO/TB0OUTH/

SMCLK SRSCG1

PJ.1/TDI/TCLK/MCLK/

SRSCG0

PJ.2/TMS/ACLK/

SROSCOFF

PJ.3/TCK/COUT/

SRCPUOFF

PJSEL1.x

PJDIR.x

PJIN.x

To modules

and JTAG

From module 1

PJOUT.x

DVSS

DVCC 1

Pad Logic

Bus

Keeper

Direction

0: Input

1: Output

PJREN.x

0 1

0 0

1 0

1 1

PJSEL0.x

0 1

0 0

1 0

1 1

From Status Register (SR)

DVSS

JTAG enable

From JTAG

107

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

6.11.23.14 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt

Trigger

Figure 6-10 shows the port diagram. Table 6-34 summarizes the selection of the pin functions.

NOTE: Functional representation only.

Figure 6-10. Port PJ (PJ.0 to PJ.3) Diagram

108

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

(1) X = Don't care

(2) Default condition

(3) The pin direction is controlled by the JTAG module. JTAG mode selection is made by the SYS module or by the Spy-Bi-Wire 4-wire

entry sequence. Neither PJSEL1.x and PJSEL0.x nor CEPD.x bits have an effect in these cases.

(4) Do not use this pin as SMCLK output if the TB0OUTH functionality is used on any other pin. Select an alternative SMCLK output pin.

(5) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.

Table 6-34. Port PJ (PJ.0 to PJ.3) Pin Functions

PIN NAME (PJ.x) x FUNCTION CONTROL BITS OR SIGNALS (1)

PJDIR.x PJSEL1.x PJSEL0.x

PJ.0/TDO/TB0OUTH/

SMCLK/SRSCG1 0 PJ.0 (I/O) (2) I: 0; O: 1 0 0

TDO (3) XXX

TB0OUTH 0 0 1

SMCLK(4) 1

N/A 0 1 0

CPU Status Register Bit SCG1 1

N/A 0 1 1

Internally tied to DVSS 1

PJ.1/TDI/TCLK/MCLK/

SRSCG0 1 PJ.1 (I/O) (2) I: 0; O: 1 0 0

TDI/TCLK (3) (5) XXX

N/A 0 0 1

MCLK 1

N/A 0 1 0

CPU Status Register Bit SCG0 1

N/A 0 1 1

Internally tied to DVSS 1

PJ.2/TMS/ACLK/

SROSCOFF 2 PJ.2 (I/O) (2) I: 0; O: 1 0 0

TMS (3) (5) XXX

N/A 0 0 1

ACLK 1

N/A 0 1 0

CPU Status Register Bit OSCOFF 1

N/A 0 1 1

Internally tied to DVSS 1

PJ.3/TCK/COUT/

SRCPUOFF 3 PJ.3 (I/O) (2) I: 0; O: 1 0 0

TCK (3) (5) XXX

N/A 0 0 1

COUT 1

N/A 0 1 0

CPU Status Register Bit CPUOFF 1

N/A 0 1 1

Internally tied to DVSS 1

109

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

6.12 Device Descriptors (TLV)

Table 6-35 summarizes the Device IDs. Table 6-36 list the contents of the device descriptor tag-length-

value (TLV) structure.

Table 6-35. Device ID

DEVICE PACKAGE DEVICE ID

At 01A05h At 01A04h

MSP430FR6970 PM and RGC 82h 49h

MSP430FR6972(1) PM and RGC 82h 4Bh

MSP430FR6870 PM and RGC 82h 4Ch

MSP430FR6872(1) PM and RGC 82h 4Eh

MSP430FR6920 DGG 82h 4Fh

PM and RGC 82h 50h

MSP430FR6922(1) DGG 82h 53h

PM and RGC 82h 54h

MSP430FR6820 DGG 82h 55h

PM and RGC 82h 56h

MSP430FR6822(1) DGG 82h 59h

PM and RGC 82h 5Ah

(1) NA = Not applicable, Per unit = content can differ from device to device

Table 6-36. Device Descriptor Table (1)

DESCRIPTION MSP430FRxxxx (UART BSL) MSP430FRxxxx1 (I2C BSL)

ADDRESS VALUE ADDRESS VALUE

Info Block

Info length 01A00h 06h 01A00h 06h

CRC length 01A01h 06h 01A01h 06h

CRC value 01A02h Per unit 01A02h Per unit

01A03h Per unit 01A03h Per unit

Device ID 01A04h See Table 6-35.01A04h See Table 6-35.

Device ID 01A05h 01A05h

Hardware revision 01A06h Per unit 01A06h Per unit

Firmware revision 01A07h Per unit 01A07h Per unit

Die Record

Die record tag 01A08h 08h 01A08h 08h

Die record length 01A09h 0Ah 01A09h 0Ah

Lot/wafer ID

01A0Ah Per unit 01A0Ah Per unit

01A0Bh Per unit 01A0Bh Per unit

01A0Ch Per unit 01A0Ch Per unit

01A0Dh Per unit 01A0Dh Per unit

Die X position 01A0Eh Per unit 01A0Eh Per unit

01A0Fh Per unit 01A0Fh Per unit

Die Y position 01A10h Per unit 01A10h Per unit

01A11h Per unit 01A11h Per unit

Test results 01A12h Per unit 01A12h Per unit

01A13h Per unit 01A13h Per unit

110

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 6-36. Device Descriptor Table (1) (continued)

DESCRIPTION MSP430FRxxxx (UART BSL) MSP430FRxxxx1 (I2C BSL)

ADDRESS VALUE ADDRESS VALUE

(2) ADC gain: The gain correction factor is measured using the internal voltage reference with REFOUT = 0. Other settings (for example,

with REFOUT = 1) can result in different correction factors.

(3) ADC offset: The offset correction factor is measured using the internal 2.5-V reference.

ADC12B

Calibration

ADC12B calibration tag 01A14h 11h 01A14h 11h

ADC12B calibration length 01A15h 10h 01A15h 10h

ADC gain factor(2) 01A16h Per unit 01A16h Per unit

01A17h Per unit 01A17h Per unit

ADC offset(3) 01A18h Per unit 01A18h Per unit

01A19h Per unit 01A19h Per unit

ADC 1.2-V reference

Temperature sensor 30°C 01A1Ah Per unit 01A1Ah Per unit

01A1Bh Per unit 01A1Bh Per unit

ADC 1.2-V reference

Temperature sensor 85°C 01A1Ch Per unit 01A1Ch Per unit

01A1Dh Per unit 01A1Dh Per unit

ADC 2.0-V reference

Temperature sensor 30°C 01A1Eh Per unit 01A1Eh Per unit

01A1Fh Per unit 01A1Fh Per unit

ADC 2.0-V reference

Temperature sensor 85°C 01A20h Per unit 01A20h Per unit

01A21h Per unit 01A21h Per unit

ADC 2.5-V reference

Temperature sensor 30°C 01A22h Per unit 01A22h Per unit

01A23h Per unit 01A23h Per unit

ADC 2.5-V reference

Temperature sensor 85°C 01A24h Per unit 01A24h Per unit

01A25h Per unit 01A25h Per unit

REF Calibration

REF calibration tag 01A26h 12h 01A26h 12h

REF calibration length 01A27h 06h 01A27h 06h

REF 1.2-V reference 01A28h Per unit 01A28h Per unit

01A29h Per unit 01A29h Per unit

REF 2.0-V reference 01A2Ah Per unit 01A2Ah Per unit

01A2Bh Per unit 01A2Bh Per unit

REF 2.5-V reference 01A2Ch Per unit 01A2Ch Per unit

01A2Dh Per unit 01A2Dh Per unit

111

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 6-36. Device Descriptor Table (1) (continued)

DESCRIPTION MSP430FRxxxx (UART BSL) MSP430FRxxxx1 (I2C BSL)

ADDRESS VALUE ADDRESS VALUE

(4) 128-bit random number: The random number is generated during production test using the CryptGenRandom() function from Microsoft®.

Random Number

128-bit random number tag 01A2Eh 15h 01A2Eh 15h

Random number length 01A2Fh 10h 01A2Fh 10h

128-bit random number(4)

01A30h Per unit 01A30h Per unit

01A31h Per unit 01A31h Per unit

01A32h Per unit 01A32h Per unit

01A33h Per unit 01A33h Per unit

01A34h Per unit 01A34h Per unit

01A35h Per unit 01A35h Per unit

01A36h Per unit 01A36h Per unit

01A37h Per unit 01A37h Per unit

01A38h Per unit 01A38h Per unit

01A39h Per unit 01A39h Per unit

01A3Ah Per unit 01A3Ah Per unit

01A3Bh Per unit 01A3Bh Per unit

01A3Ch Per unit 01A3Ch Per unit

01A3Dh Per unit 01A3Dh Per unit

01A3Eh Per unit 01A3Eh Per unit

01A3Fh Per unit 01A3Fh Per unit

BSL Configuration

BSL tag 01A40h 1Ch 01A40h 1Ch

BSL length 01A41h 02h 01A41h 02h

BSL interface 01A42h 00h 01A42h 01h

BSL interface configuration 01A43h 00h 01A43h 48h

112

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

(1) All address space not listed is considered vacant memory.

(2) Read as: D032h at 00h (Opcode: BIS.W LPM4, SR), 00F0h at 02h (Opcode: BIS.W LPM4, SR), 3FFFh at 04h (Opcode: JMP$)

6.13 Memory

Table 6-37 summarizes the memory map for all devices.

Table 6-37. Memory Organization(1)

MSP430FR69x2(1)

MSP430FR68x2(1) MSP430FR69x0

MSP430FR68x0

Memory (FRAM)

Main: interrupt vectors and

signatures

Main: code memory Total Size 63KB

00FFFFh to 00FF80h

013FFFh to 004400h

32KB

00FFFFh to 00FF80h

00FF7Fh to 008000h

RAM Sect 1 2KB

0023FFh to 001C00h 2KB

0023FFh to 001C00h

Device Descriptor Info (TLV)

(FRAM) 256 bytes

001AFFh to 001A00h 256 bytes

001AFFh to 001A00h

Information memory (FRAM)

Info A 128 bytes

0019FFh to 001980h 128 bytes

0019FFh to 001980h

Info B 128 bytes

00197Fh to 001900h 128 bytes

00197Fh to 001900h

Info C 128 bytes

0018FFh to 001880h 128 bytes

0018FFh to 001880h

Info D 128 bytes

00187Fh to 001800h 128 bytes

00187Fh to 001800h

Bootloader (BSL) memory (ROM)

BSL 3 512 bytes

0017FFh to 001600h 512 bytes

0017FFh to 001600h

BSL 2 512 bytes

0015FFh to 001400h 512 bytes

0015FFh to 001400h

BSL 1 512 bytes

0013FFh to 001200h 512 bytes

0013FFh to 001200h

BSL 0 512 bytes

0011FFh to 001000h 512 bytes

0011FFh to 001000h

Peripherals Size 4KB

000FFFh to 000020h 4KB

000FFFh to 000020h

Tiny RAM Size 26 bytes

000001Fh to 000006h 26 bytes

000001Fh to 000006h

Reserved

(Read Only)(2) Size 6 bytes

000005h to 000000h 6 bytes

000005h to 000000h

113

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

6.13.1 Peripheral File Map

Table 6-38 lists the base address and offset range for the registers of supported peripheral modules.

Table 6-38. Peripherals

MODULE NAME BASE ADDRESS OFFSET ADDRESS

RANGE

Special Functions (see Table 6-39) 0100h 000h to 01Fh

PMM (see Table 6-40) 0120h 000h to 01Fh

FRAM Control (see Table 6-41) 0140h 000h to 00Fh

CRC16 (see Table 6-42) 0150h 000h to 007h

RAM Controller (see Table 6-43) 0158h 000h to 001h

Watchdog (see Table 6-44) 015Ch 000h to 001h

CS (see Table 6-45) 0160h 000h to 00Fh

SYS (see Table 6-46) 0180h 000h to 01Fh

Shared Reference (see Table 6-47) 01B0h 000h to 001h

Port P1, P2 (see Table 6-48) 0200h 000h to 01Fh

Port P3, P4 (see Table 6-49) 0220h 000h to 01Fh

Port P5, P6 (see Table 6-50) 0240h 000h to 01Fh

Port P7 (see Table 6-51) 0260h 000h to 01Fh

Port P9 (see Table 6-52) 0280h 000h to 01Fh

Port PJ (see Table 6-53) 0320h 000h to 01Fh

Timer_A TA0 (see Table 6-54) 0340h 000h to 02Fh

Timer_A TA1 (see Table 6-55) 0380h 000h to 02Fh

Timer_B TB0 (see Table 6-56) 03C0h 000h to 02Fh

Timer_A TA2 (see Table 6-57) 0400h 000h to 02Fh

Capacitive Touch I/O 0 (see Table 6-58) 0430h 000h to 00Fh

Timer_A TA3 (see Table 6-59) 0440h 000h to 02Fh

Capacitive Touch I/O 1 (see Table 6-60) 0470h 000h to 00Fh

Real-Time Clock (RTC_C) (see Table 6-61) 04A0h 000h to 01Fh

32-Bit Hardware Multiplier (see Table 6-62) 04C0h 000h to 02Fh

DMA General Control (see Table 6-63) 0500h 000h to 00Fh

DMA Channel 0 (see Table 6-63) 0510h 000h to 00Fh

DMA Channel 1 (see Table 6-63) 0520h 000h to 00Fh

DMA Channel 2 (see Table 6-63) 0530h 000h to 00Fh

MPU Control (see Table 6-64) 05A0h 000h to 00Fh

eUSCI_A0 (see Table 6-65) 05C0h 000h to 01Fh

eUSCI_A1 (see Table 6-66) 05E0h 000h to 01Fh

eUSCI_B0 (see Table 6-67) 0640h 000h to 02Fh

eUSCI_B1 (see Table 6-68) 0680h 000h to 02Fh

ADC12_B (see Table 6-69) 0800h 000h to 09Fh

Comparator_E (see Table 6-70) 08C0h 000h to 00Fh

CRC32 (see Table 6-71) 0980h 000h to 02Fh

AES (see Table 6-72) 09C0h 000h to 00Fh

LCD_C (see Table 6-73) 0A00h 000h to 05Fh

114

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 6-39. Special Function Registers (Base Address: 0100h)

SFR interrupt enable SFRIE1 00h

SFR interrupt flag SFRIFG1 02h

SFR reset pin control SFRRPCR 04h

Table 6-40. PMM Registers (Base Address: 0120h)

PMM control 0 PMMCTL0 00h

PMM interrupt flags PMMIFG 0Ah

PM5 control 0 PM5CTL0 10h

Table 6-41. FRAM Control Registers (Base Address: 0140h)

FRAM control 0 FRCTL0 00h

General control 0 GCCTL0 04h

General control 1 GCCTL1 06h

Table 6-42. CRC16 Registers (Base Address: 0150h)

CRC data input CRCDI 00h

CRC data input reverse byte CRCDIRB 02h

CRC initialization and result CRCINIRES 04h

CRC result reverse byte CRCRESR 06h

Table 6-43. RAM Controller Registers (Base Address: 0158h)

RAM controller control 0 RCCTL0 00h

Table 6-44. Watchdog Registers (Base Address: 015Ch)

Watchdog timer control WDTCTL 00h

Table 6-45. CS Registers (Base Address: 0160h)

CS control 0 CSCTL0 00h

CS control 1 CSCTL1 02h

CS control 2 CSCTL2 04h

CS control 3 CSCTL3 06h

CS control 4 CSCTL4 08h

CS control 5 CSCTL5 0Ah

CS control 6 CSCTL6 0Ch

Table 6-46. SYS Registers (Base Address: 0180h)

System control SYSCTL 00h

JTAG mailbox control SYSJMBC 06h

115

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 6-46. SYS Registers (Base Address: 0180h) (continued)

JTAG mailbox input 0 SYSJMBI0 08h

JTAG mailbox input 1 SYSJMBI1 0Ah

JTAG mailbox output 0 SYSJMBO0 0Ch

JTAG mailbox output 1 SYSJMBO1 0Eh

User NMI vector generator SYSUNIV 1Ah

System NMI vector generator SYSSNIV 1Ch

Reset vector generator SYSRSTIV 1Eh

Table 6-47. Shared Reference Registers (Base Address: 01B0h)

Shared reference control REFCTL 00h

Table 6-48. Port P1, P2 Registers (Base Address: 0200h)

Port P1 input P1IN 00h

Port P1 output P1OUT 02h

Port P1 direction P1DIR 04h

Port P1 resistor enable P1REN 06h

Port P1 selection 0 P1SEL0 0Ah

Port P1 selection 1 P1SEL1 0Ch

Port P1 interrupt vector word P1IV 0Eh

Port P1 complement selection P1SELC 16h

Port P1 interrupt edge select P1IES 18h

Port P1 interrupt enable P1IE 1Ah

Port P1 interrupt flag P1IFG 1Ch

Port P2 input P2IN 01h

Port P2 output P2OUT 03h

Port P2 direction P2DIR 05h

Port P2 resistor enable P2REN 07h

Port P2 selection 0 P2SEL0 0Bh

Port P2 selection 1 P2SEL1 0Dh

Port P2 complement selection P2SELC 17h

Port P2 interrupt vector word P2IV 1Eh

Port P2 interrupt edge select P2IES 19h

Port P2 interrupt enable P2IE 1Bh

Port P2 interrupt flag P2IFG 1Dh

Table 6-49. Port P3, P4 Registers (Base Address: 0220h)

Port P3 input P3IN 00h

Port P3 output P3OUT 02h

Port P3 direction P3DIR 04h

Port P3 resistor enable P3REN 06h

Port P3 selection 0 P3SEL0 0Ah

Port P3 selection 1 P3SEL1 0Ch

Port P3 interrupt vector word P3IV 0Eh

116

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 6-49. Port P3, P4 Registers (Base Address: 0220h) (continued)

Port P3 complement selection P3SELC 16h

Port P3 interrupt edge select P3IES 18h

Port P3 interrupt enable P3IE 1Ah

Port P3 interrupt flag P3IFG 1Ch

Port P4 input P4IN 01h

Port P4 output P4OUT 03h

Port P4 direction P4DIR 05h

Port P4 resistor enable P4REN 07h

Port P4 selection 0 P4SEL0 0Bh

Port P4 selection 1 P4SEL1 0Dh

Port P4 complement selection P4SELC 17h

Port P4 interrupt vector word P4IV 1Eh

Port P4 interrupt edge select P4IES 19h

Port P4 interrupt enable P4IE 1Bh

Port P4 interrupt flag P4IFG 1Dh

Table 6-50. Port P5, P6 Registers (Base Address: 0240h)

Port P5 input P5IN 00h

Port P5 output P5OUT 02h

Port P5 direction P5DIR 04h

Port P5 resistor enable P5REN 06h

Port P5 selection 0 P5SEL0 0Ah

Port P5 selection 1 P5SEL1 0Ch

Reserved 0Eh

Port P5 complement selection P5SELC 16h

Reserved 18h

Reserved 1Ah

Reserved 1Ch

Port P6 input P6IN 01h

Port P6 output P6OUT 03h

Port P6 direction P6DIR 05h

Port P6 resistor enable P6REN 07h

Port P6 selection 0 P6SEL0 0Bh

Port P6 selection 1 P6SEL1 0Dh

Port P6 complement selection P6SELC 17h

Reserved 1Eh

Reserved 19h

Reserved 1Bh

Reserved 1Dh

Table 6-51. Port P7 Registers (Base Address: 0260h)

Port P7 input P7IN 00h

Port P7 output P7OUT 02h

Port P7 direction P7DIR 04h

Port P7 resistor enable P7REN 06h

117

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 6-51. Port P7 Registers (Base Address: 0260h) (continued)

Port P7 selection 0 P7SEL0 0Ah

Port P7 selection 1 P7SEL1 0Ch

Reserved 0Eh

Port P7 complement selection P7SELC 16h

Reserved 18h

Reserved 1Ah

Reserved 1Ch

Table 6-52. Port P9 Registers (Base Address: 0280h)

Port P9 input P9IN 00h

Port P9 output P9OUT 02h

Port P9 direction P9DIR 04h

Port P9 resistor enable P9REN 06h

Port P9 selection 0 P9SEL0 0Ah

Port P9 selection 1 P9SEL1 0Ch

Reserved 0Eh

Port P9 complement selection P9SELC 16h

Reserved 18h

Reserved 1Ah

Reserved 1Ch

Table 6-53. Port J Registers (Base Address: 0320h)

Port PJ input PJIN 00h

Port PJ output PJOUT 02h

Port PJ direction PJDIR 04h

Port PJ resistor enable PJREN 06h

Port PJ selection 0 PJSEL0 0Ah

Port PJ selection 1 PJSEL1 0Ch

Port PJ complement selection PJSELC 16h

Table 6-54. Timer_A TA0 Registers (Base Address: 0340h)

TA0 control TA0CTL 00h

Capture/compare control 0 TA0CCTL0 02h

Capture/compare control 1 TA0CCTL1 04h

Capture/compare control 2 TA0CCTL2 06h

TA0 counter TA0R 10h

Capture/compare 0 TA0CCR0 12h

Capture/compare 1 TA0CCR1 14h

Capture/compare 2 TA0CCR2 16h

TA0 expansion 0 TA0EX0 20h

TA0 interrupt vector TA0IV 2Eh

118

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 6-55. Timer_A TA1 Registers (Base Address: 0380h)

TA1 control TA1CTL 00h

Capture/compare control 0 TA1CCTL0 02h

Capture/compare control 1 TA1CCTL1 04h

Capture/compare control 2 TA1CCTL2 06h

TA1 counter TA1R 10h

Capture/compare 0 TA1CCR0 12h

Capture/compare 1 TA1CCR1 14h

Capture/compare 2 TA1CCR2 16h

TA1 expansion 0 TA1EX0 20h

TA1 interrupt vector TA1IV 2Eh

Table 6-56. Timer_B TB0 Registers (Base Address: 03C0h)

TB0 control TB0CTL 00h

Capture/compare control 0 TB0CCTL0 02h

Capture/compare control 1 TB0CCTL1 04h

Capture/compare control 2 TB0CCTL2 06h

Capture/compare control 3 TB0CCTL3 08h

Capture/compare control 4 TB0CCTL4 0Ah

Capture/compare control 5 TB0CCTL5 0Ch

Capture/compare control 6 TB0CCTL6 0Eh

TB0 counter TB0R 10h

Capture/compare 0 TB0CCR0 12h

Capture/compare 1 TB0CCR1 14h

Capture/compare 2 TB0CCR2 16h

Capture/compare 3 TB0CCR3 18h

Capture/compare 4 TB0CCR4 1Ah

Capture/compare 5 TB0CCR5 1Ch

Capture/compare 6 TB0CCR6 1Eh

TB0 expansion 0 TB0EX0 20h

TB0 interrupt vector TB0IV 2Eh

Table 6-57. Timer_A TA2 Registers (Base Address: 0400h)

TA2 control TA2CTL 00h

Capture/compare control 0 TA2CCTL0 02h

Capture/compare control 1 TA2CCTL1 04h

TA2 counter TA2R 10h

Capture/compare 0 TA2CCR0 12h

Capture/compare 1 TA2CCR1 14h

TA2 expansion 0 TA2EX0 20h

TA2 interrupt vector TA2IV 2Eh

Table 6-58. Capacitive Touch I/O 0 Registers (Base Address: 0430h)

Capacitive touch I/O 0 control CAPTIO0CTL 0Eh

119

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 6-59. Timer_A TA3 Registers (Base Address: 0440h)

TA3 control TA3CTL 00h

Capture/compare control 0 TA3CCTL0 02h

Capture/compare control 1 TA3CCTL1 04h

Capture/compare control 2 TA3CCTL2 06h

Capture/compare control 3 TA3CCTL3 08h

Capture/compare control 4 TA3CCTL4 0Ah

TA3 counter TA3R 10h

Capture/compare 0 TA3CCR0 12h

Capture/compare 1 TA3CCR1 14h

Capture/compare 2 TA3CCR2 16h

Capture/compare 3 TA3CCR3 18h

Capture/compare 4 TA3CCR4 1Ah

TA3 expansion 0 TA3EX0 20h

TA3 interrupt vector TA3IV 2Eh

Table 6-60. Capacitive Touch I/O 1 Registers (Base Address: 0470h)

Capacitive touch I/O 1 control CAPTIO1CTL 0Eh

Table 6-61. RTC_C Registers (Base Address: 04A0h)

RTC control 0 RTCCTL0 00h

RTC password RTCPWD 01h

RTC control 1 RTCCTL1 02h

RTC control 3 RTCCTL3 03h

RTC offset calibration RTCOCAL 04h

RTC temperature compensation RTCTCMP 06h

RTC prescaler 0 control RTCPS0CTL 08h

RTC prescaler 1 control RTCPS1CTL 0Ah

RTC prescaler 0 RTCPS0 0Ch

RTC prescaler 1 RTCPS1 0Dh

RTC interrupt vector word RTCIV 0Eh

RTC seconds/counter 1 RTCSEC/RTCNT1 10h

RTC minutes/counter 2 RTCMIN/RTCNT2 11h

RTC hours/counter 3 RTCHOUR/RTCNT3 12h

RTC day of week/counter 4 RTCDOW/RTCNT4 13h

RTC days RTCDAY 14h

RTC month RTCMON 15h

RTC year RTCYEAR 16h

RTC alarm minutes RTCAMIN 18h

RTC alarm hours RTCAHOUR 19h

RTC alarm day of week RTCADOW 1Ah

RTC alarm days RTCADAY 1Bh

Binary-to-BCD conversion BIN2BCD 1Ch

BCD-to-binary conversion BCD2BIN 1Eh

120

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 6-62. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)

16-bit operand 1 – multiply MPY 00h

16-bit operand 1 – signed multiply MPYS 02h

16-bit operand 1 – multiply accumulate MAC 04h

16-bit operand 1 – signed multiply accumulate MACS 06h

16-bit operand 2 OP2 08h

16 × 16 result low word RESLO 0Ah

16 × 16 result high word RESHI 0Ch

16 × 16 sum extension SUMEXT 0Eh

32-bit operand 1 – multiply low word MPY32L 10h

32-bit operand 1 – multiply high word MPY32H 12h

32-bit operand 1 – signed multiply low word MPYS32L 14h

32-bit operand 1 – signed multiply high word MPYS32H 16h

32-bit operand 1 – multiply accumulate low word MAC32L 18h

32-bit operand 1 – multiply accumulate high word MAC32H 1Ah

32-bit operand 1 – signed multiply accumulate low word MACS32L 1Ch

32-bit operand 1 – signed multiply accumulate high word MACS32H 1Eh

32-bit operand 2 – low word OP2L 20h

32-bit operand 2 – high word OP2H 22h

32 × 32 result 0 – least significant word RES0 24h

32 × 32 result 1 RES1 26h

32 × 32 result 2 RES2 28h

32 × 32 result 3 – most significant word RES3 2Ah

MPY32 control 0 MPY32CTL0 2Ch

Table 6-63. DMA Registers (Base Address DMA General Control: 0500h,

DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)

DMA channel 0 control DMA0CTL 00h

DMA channel 0 source address low DMA0SAL 02h

DMA channel 0 source address high DMA0SAH 04h

DMA channel 0 destination address low DMA0DAL 06h

DMA channel 0 destination address high DMA0DAH 08h

DMA channel 0 transfer size DMA0SZ 0Ah

DMA channel 1 control DMA1CTL 00h

DMA channel 1 source address low DMA1SAL 02h

DMA channel 1 source address high DMA1SAH 04h

DMA channel 1 destination address low DMA1DAL 06h

DMA channel 1 destination address high DMA1DAH 08h

DMA channel 1 transfer size DMA1SZ 0Ah

DMA channel 2 control DMA2CTL 00h

DMA channel 2 source address low DMA2SAL 02h

DMA channel 2 source address high DMA2SAH 04h

DMA channel 2 destination address low DMA2DAL 06h

DMA channel 2 destination address high DMA2DAH 08h

DMA channel 2 transfer size DMA2SZ 0Ah

DMA module control 0 DMACTL0 00h

DMA module control 1 DMACTL1 02h

121

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 6-63. DMA Registers (Base Address DMA General Control: 0500h,

DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h) (continued)

DMA module control 2 DMACTL2 04h

DMA module control 3 DMACTL3 06h

DMA module control 4 DMACTL4 08h

DMA interrupt vector DMAIV 0Eh

Table 6-64. MPU Control Registers (Base Address: 05A0h)

MPU control 0 MPUCTL0 00h

MPU control 1 MPUCTL1 02h

MPU Segmentation Border 2 MPUSEGB2 04h

MPU Segmentation Border 1 MPUSEGB1 06h

MPU access management MPUSAM 08h

MPU IP control 0 MPUIPC0 0Ah

MPU IP Encapsulation Segment Border 2 MPUIPSEGB2 0Ch

MPU IP Encapsulation Segment Border 1 MPUIPSEGB1 0Eh

Table 6-65. eUSCI_A0 Registers (Base Address: 05C0h)

eUSCI_A control word 0 UCA0CTLW0 00h

eUSCI _A control word 1 UCA0CTLW1 02h

eUSCI_A baud rate 0 UCA0BR0 06h

eUSCI_A baud rate 1 UCA0BR1 07h

eUSCI_A modulation control UCA0MCTLW 08h

eUSCI_A status word UCA0STATW 0Ah

eUSCI_A receive buffer UCA0RXBUF 0Ch

eUSCI_A transmit buffer UCA0TXBUF 0Eh

eUSCI_A LIN control UCA0ABCTL 10h

eUSCI_A IrDA transmit control UCA0IRTCTL 12h

eUSCI_A IrDA receive control UCA0IRRCTL 13h

eUSCI_A interrupt enable UCA0IE 1Ah

eUSCI_A interrupt flags UCA0IFG 1Ch

eUSCI_A interrupt vector word UCA0IV 1Eh

Table 6-66. eUSCI_A1 Registers (Base Address:05E0h)

eUSCI_A control word 0 UCA1CTLW0 00h

eUSCI _A control word 1 UCA1CTLW1 02h

eUSCI_A baud rate 0 UCA1BR0 06h

eUSCI_A baud rate 1 UCA1BR1 07h

eUSCI_A modulation control UCA1MCTLW 08h

eUSCI_A status word UCA1STATW 0Ah

eUSCI_A receive buffer UCA1RXBUF 0Ch

eUSCI_A transmit buffer UCA1TXBUF 0Eh

eUSCI_A LIN control UCA1ABCTL 10h

eUSCI_A IrDA transmit control UCA1IRTCTL 12h

122

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 6-66. eUSCI_A1 Registers (Base Address:05E0h) (continued)

eUSCI_A IrDA receive control UCA1IRRCTL 13h

eUSCI_A interrupt enable UCA1IE 1Ah

eUSCI_A interrupt flags UCA1IFG 1Ch

eUSCI_A interrupt vector word UCA1IV 1Eh

Table 6-67. eUSCI_B0 Registers (Base Address: 0640h)

eUSCI_B control word 0 UCB0CTLW0 00h

eUSCI_B control word 1 UCB0CTLW1 02h

eUSCI_B bit rate 0 UCB0BR0 06h

eUSCI_B bit rate 1 UCB0BR1 07h

eUSCI_B status word UCB0STATW 08h

eUSCI_B byte counter threshold UCB0TBCNT 0Ah

eUSCI_B receive buffer UCB0RXBUF 0Ch

eUSCI_B transmit buffer UCB0TXBUF 0Eh

eUSCI_B I2C own address 0 UCB0I2COA0 14h

eUSCI_B I2C own address 1 UCB0I2COA1 16h

eUSCI_B I2C own address 2 UCB0I2COA2 18h

eUSCI_B I2C own address 3 UCB0I2COA3 1Ah

eUSCI_B received address UCB0ADDRX 1Ch

eUSCI_B address mask UCB0ADDMASK 1Eh

eUSCI_B I2C slave address UCB0I2CSA 20h

eUSCI_B interrupt enable UCB0IE 2Ah

eUSCI_B interrupt flags UCB0IFG 2Ch

eUSCI_B interrupt vector word UCB0IV 2Eh

Table 6-68. eUSCI_B1 Registers (Base Address: 0680h)

eUSCI_B control word 0 UCB1CTLW0 00h

eUSCI_B control word 1 UCB1CTLW1 02h

eUSCI_B bit rate 0 UCB1BR0 06h

eUSCI_B bit rate 1 UCB1BR1 07h

eUSCI_B status word UCB1STATW 08h

eUSCI_B byte counter threshold UCB1TBCNT 0Ah

eUSCI_B receive buffer UCB1RXBUF 0Ch

eUSCI_B transmit buffer UCB1TXBUF 0Eh

eUSCI_B I2C own address 0 UCB1I2COA0 14h

eUSCI_B I2C own address 1 UCB1I2COA1 16h

eUSCI_B I2C own address 2 UCB1I2COA2 18h

eUSCI_B I2C own address 3 UCB1I2COA3 1Ah

eUSCI_B received address UCB1ADDRX 1Ch

eUSCI_B address mask UCB1ADDMASK 1Eh

eUSCI_B I2C slave address UCB1I2CSA 20h

eUSCI_B interrupt enable UCB1IE 2Ah

eUSCI_B interrupt flags UCB1IFG 2Ch

eUSCI_B interrupt vector word UCB1IV 2Eh

123

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 6-69. ADC12_B Registers (Base Address: 0800h)

ADC12_B control 0 ADC12CTL0 00h

ADC12_B control 1 ADC12CTL1 02h

ADC12_B control 2 ADC12CTL2 04h

ADC12_B control 3 ADC12CTL3 06h

ADC12_B window comparator low threshold ADC12LO 08h

ADC12_B window comparator high threshold ADC12HI 0Ah

ADC12_B interrupt flag 0 ADC12IFGR0 0Ch

ADC12_B interrupt flag 1 ADC12IFGR1 0Eh

ADC12_B interrupt flag 2 ADC12IFGR2 10h

ADC12_B interrupt enable 0 ADC12IER0 12h

ADC12_B Interrupt Enable 1 ADC12IER1 14h

ADC12_B interrupt enable 2 ADC12IER2 16h

ADC12_B interrupt vector ADC12IV 18h

ADC12_B memory control 0 ADC12MCTL0 20h

ADC12_B memory control 1 ADC12MCTL1 22h

ADC12_B memory control 2 ADC12MCTL2 24h

ADC12_B memory control 3 ADC12MCTL3 26h

ADC12_B memory control 4 ADC12MCTL4 28h

ADC12_B memory control 5 ADC12MCTL5 2Ah

ADC12_B memory control 6 ADC12MCTL6 2Ch

ADC12_B memory control 7 ADC12MCTL7 2Eh

ADC12_B memory control 8 ADC12MCTL8 30h

ADC12_B memory control 9 ADC12MCTL9 32h

ADC12_B memory control 10 ADC12MCTL10 34h

ADC12_B memory control 11 ADC12MCTL11 36h

ADC12_B memory control 12 ADC12MCTL12 38h

ADC12_B memory control 13 ADC12MCTL13 3Ah

ADC12_B memory control 14 ADC12MCTL14 3Ch

ADC12_B memory control 15 ADC12MCTL15 3Eh

ADC12_B memory control 16 ADC12MCTL16 40h

ADC12_B memory control 17 ADC12MCTL17 42h

ADC12_B memory control 18 ADC12MCTL18 44h

ADC12_B memory control 19 ADC12MCTL19 46h

ADC12_B memory control 20 ADC12MCTL20 48h

ADC12_B memory control 21 ADC12MCTL21 4Ah

ADC12_B memory control 22 ADC12MCTL22 4Ch

ADC12_B memory control 23 ADC12MCTL23 4Eh

ADC12_B memory control 24 ADC12MCTL24 50h

ADC12_B memory control 25 ADC12MCTL25 52h

ADC12_B memory control 26 ADC12MCTL26 54h

ADC12_B memory control 27 ADC12MCTL27 56h

ADC12_B memory control 28 ADC12MCTL28 58h

ADC12_B memory control 29 ADC12MCTL29 5Ah

ADC12_B memory control 30 ADC12MCTL30 5Ch

ADC12_B memory control 31 ADC12MCTL31 5Eh

ADC12_B memory 0 ADC12MEM0 60h

ADC12_B memory 1 ADC12MEM1 62h

124

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 6-69. ADC12_B Registers (Base Address: 0800h) (continued)

ADC12_B memory 2 ADC12MEM2 64h

ADC12_B memory 3 ADC12MEM3 66h

ADC12_B memory 4 ADC12MEM4 68h

ADC12_B memory 5 ADC12MEM5 6Ah

ADC12_B memory 6 ADC12MEM6 6Ch

ADC12_B memory 7 ADC12MEM7 6Eh

ADC12_B memory 8 ADC12MEM8 70h

ADC12_B memory 9 ADC12MEM9 72h

ADC12_B memory 10 ADC12MEM10 74h

ADC12_B memory 11 ADC12MEM11 76h

ADC12_B memory 12 ADC12MEM12 78h

ADC12_B memory 13 ADC12MEM13 7Ah

ADC12_B memory 14 ADC12MEM14 7Ch

ADC12_B memory 15 ADC12MEM15 7Eh

ADC12_B memory 16 ADC12MEM16 80h

ADC12_B memory 17 ADC12MEM17 82h

ADC12_B memory 18 ADC12MEM18 84h

ADC12_B memory 19 ADC12MEM19 86h

ADC12_B memory 20 ADC12MEM20 88h

ADC12_B memory 21 ADC12MEM21 8Ah

ADC12_B memory 22 ADC12MEM22 8Ch

ADC12_B memory 23 ADC12MEM23 8Eh

ADC12_B memory 24 ADC12MEM24 90h

ADC12_B memory 25 ADC12MEM25 92h

ADC12_B memory 26 ADC12MEM26 94h

ADC12_B memory 27 ADC12MEM27 96h

ADC12_B memory 28 ADC12MEM28 98h

ADC12_B memory 29 ADC12MEM29 9Ah

ADC12_B memory 30 ADC12MEM30 9Ch

ADC12_B memory 31 ADC12MEM31 9Eh

Table 6-70. Comparator_E Registers (Base Address: 08C0h)

Comparator control 0 CECTL0 00h

Comparator control 1 CECTL1 02h

Comparator control 2 CECTL2 04h

Comparator control 3 CECTL3 06h

Comparator interrupt CEINT 0Ch

Comparator interrupt vector word CEIV 0Eh

Table 6-71. CRC32 Registers (Base Address: 0980h)

CRC32 data input CRC32DIW0 00h

Reserved 02h

Reserved 04h

CRC32 data input reverse CRC32DIRBW0 06h

CRC32 initialization and result word 0 CRC32INIRESW0 08h

125

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 6-71. CRC32 Registers (Base Address: 0980h) (continued)

CRC32 initialization and result word 1 CRC32INIRESW1 0Ah

CRC32 result reverse word 1 CRC32RESRW1 0Ch

CRC32 result reverse word 0 CRC32RESRW1 0Eh

CRC16 data input CRC16DIW0 10h

Reserved 12h

Reserved 14h

CRC16 data input reverse CRC16DIRBW0 16h

CRC16 initialization and result word 0 CRC16INIRESW0 18h

Reserved 1Ah

Reserved 1Ch

CRC16 result reverse word 0 CRC16RESRW1 1Eh

Reserved 20h

Reserved 22h

Reserved 24h

Reserved 26h

Reserved 28h

Reserved 2Ah

Reserved 2Ch

Reserved 2Eh

Table 6-72. AES Accelerator Registers (Base Address: 09C0h)

AES accelerator control 0 AESACTL0 00h

Reserved 02h

AES accelerator status AESASTAT 04h

AES accelerator key AESAKEY 06h

AES accelerator data in AESADIN 008h

AES accelerator data out AESADOUT 00Ah

AES accelerator XORed data in AESAXDIN 00Ch

AES accelerator XORed data in (no trigger) AESAXIN 00Eh

Table 6-73. LCD_C Registers (Base Address: 0A00h)

LCD_C control 0 LCDCCTL0 000h

LCD_C control 1 LCDCCTL1 002h

LCD_C blinking control LCDCBLKCTL 004h

LCD_C memory control LCDCMEMCTL 006h

LCD_C voltage control LCDCVCTL 008h

LCD_C port control 0 LCDCPCTL0 00Ah

LCD_C port control 1 LCDCPCTL1 00Ch

LCD_C port control 2 LCDCPCTL2 00Eh

LCD_C charge pump control LCDCCPCTL 012h

LCD_C interrupt vector LCDCIV 01Eh

Static and 2 to 4 mux modes

LCD_C memory 1 LCDM1 020h

LCD_C memory 2 LCDM2 021h

LCD_C memory 3 LCDM3 022h

126

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 6-73. LCD_C Registers (Base Address: 0A00h) (continued)

LCD_C memory 4 LCDM4 023h

LCD_C memory 5 LCDM5 024h

LCD_C memory 6 LCDM6 025h

LCD_C memory 7 LCDM7 026h

LCD_C memory 8 LCDM8 027h

LCD_C memory 9 LCDM9 028h

LCD_C memory 10 LCDM10 029h

LCD_C memory 11 LCDM11 02Ah

LCD_C memory 12 LCDM12 02Bh

LCD_C memory 13 LCDM13 02Ch

LCD_C memory 14 LCDM14 02Dh

LCD_C memory 15 LCDM15 02Eh

LCD_C memory 16 LCDM16 02Fh

LCD_C memory 17 LCDM17 030h

LCD_C memory 18 LCDM18 031h

LCD_C memory 19 LCDM19 032h

LCD_C memory 20 LCDM20 033h

LCD_C memory 21 LCDM21 034h

LCD_C memory 22 LCDM22 035h

Reserved 036h

Reserved 037h

LCD_C blinking memory 1 LCDBM1 040h

LCD_C blinking memory 2 LCDBM2 041h

LCD_C blinking memory 3 LCDBM3 042h

LCD_C blinking memory 4 LCDBM4 043h

LCD_C blinking memory 5 LCDBM5 044h

LCD_C blinking memory 6 LCDBM6 045h

LCD_C blinking memory 7 LCDBM7 046h

LCD_C blinking memory 8 LCDBM8 047h

LCD_C blinking memory 9 LCDBM9 048h

LCD_C blinking memory 10 LCDBM10 049h

LCD_C blinking memory 11 LCDBM11 04Ah

LCD_C blinking memory 12 LCDBM12 04Bh

LCD_C blinking memory 13 LCDBM13 04Ch

LCD_C blinking memory 14 LCDBM14 04Dh

LCD_C blinking memory 15 LCDBM15 04Eh

LCD_C blinking memory 16 LCDBM16 04Fh

LCD_C blinking memory 17 LCDBM17 050h

LCD_C blinking memory 18 LCDBM18 051h

LCD_C blinking memory 19 LCDBM19 052h

LCD_C blinking memory 20 LCDBM20 053h

LCD_C blinking memory 21 LCDBM21 054h

LCD_C blinking memory 22 LCDBM22 055h

Reserved 056h

Reserved 057h

5 to 8 mux modes

LCD_C memory 1 LCDM1 020h

127

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Table 6-73. LCD_C Registers (Base Address: 0A00h) (continued)

LCD_C memory 2 LCDM2 021h

LCD_C memory 3 LCDM3 022h

LCD_C memory 4 LCDM4 023h

LCD_C memory 5 LCDM5 024h

LCD_C memory 6 LCDM6 025h

LCD_C memory 7 LCDM7 026h

LCD_C memory 8 LCDM8 027h

LCD_C memory 9 LCDM9 028h

LCD_C memory 10 LCDM10 029h

LCD_C memory 11 LCDM11 02Ah

LCD_C memory 12 LCDM12 02Bh

LCD_C memory 13 LCDM13 02Ch

LCD_C memory 14 LCDM14 02Dh

LCD_C memory 15 LCDM15 02Eh

LCD_C memory 16 LCDM16 02Fh

LCD_C memory 17 LCDM17 030h

LCD_C memory 18 LCDM18 031h

LCD_C memory 19 LCDM19 032h

LCD_C memory 20 LCDM20 033h

LCD_C memory 21 LCDM21 034h

LCD_C memory 22 LCDM22 035h

LCD_C memory 23 LCDM23 036h

LCD_C memory 24 LCDM24 037h

LCD_C memory 25 LCDM25 038h

LCD_C memory 26 LCDM26 039h

LCD_C memory 27 LCDM27 03Ah

LCD_C memory 28 LCDM28 03Bh

LCD_C memory 29 LCDM29 03Ch

LCD_C memory 30 LCDM30 03Dh

LCD_C memory 31 LCDM31 03Eh

LCD_C memory 32 LCDM32 03Fh

LCD_C memory 33 LCDM33 040h

LCD_C memory 34 LCDM34 041h

LCD_C memory 35 LCDM35 042h

LCD_C memory 36 LCDM36 043h

LCD_C memory 37 LCDM37 044h

LCD_C memory 38 LCDM38 045h

LCD_C memory 39 LCDM39 046h

LCD_C memory 40 LCDM40 047h

LCD_C memory 41 LCDM41 048h

LCD_C memory 42 LCDM42 049h

LCD_C memory 43 LCDM43 04Ah

128

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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6.14 Identification

6.14.1 Revision Identification

The device revision information is shown as part of the top-side marking on the device package. The

device-specific errata sheet describes these markings. For links to the errata sheets for the devices in this

data sheet, see Section 8.4.

The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For

details on this value, see the "Hardware Revision" entries in Section 6.12.

6.14.2 Device Identification

The device type can be identified from the top-side marking on the device package. The device-specific

errata sheet describes these markings. For links to the errata sheets for the devices in this data sheet, see

Section 8.4.

A device identification value is also stored in the Device Descriptor structure in the Info Block section. For

details on this value, see the "Device ID" entries in Section 6.12.

6.14.3 JTAG Identification

Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in

detail in MSP430 Programming With the JTAG Interface.

Digital

Power Supply

Decoupling

100 nF1 Fµ

Analog

Power Supply

Decoupling

DVCC

DVSS

AVCC

AVSS

+100 nF1 Fµ

129

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

7 Applications, Implementation, and Layout

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

7.1 Device Connection and Layout Fundamentals

This section describes the recommended guidelines when designing with the MSP430. These guidelines

are to make sure that the device has proper connections for powering, programming, debugging, and

optimum analog performance.

7.1.1 Power Supply Decoupling and Bulk Capacitors

TI recommends connecting a combination of a 1-µF plus a 100-nF low-ESR ceramic decoupling capacitor

to each AVCC and DVCC pin. Higher-value capacitors may be used but can impact supply rail ramp-up

time. Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a

few millimeters). Additionally, TI recommends separated grounds with a single-point connection for better

noise isolation from digital to analog circuits on the board and to achieve high analog accuracy.

Figure 7-1. Power Supply Decoupling

7.1.2 External Oscillator

Depending on the device variant (see Section 3), the device can support a low-frequency crystal (32 kHz)

on the LFXT pins, a high-frequency crystal on the HFXT pins, or both. External bypass capacitors for the

crystal oscillator pins are required.

It is also possible to apply digital clock signals to the LFXIN and HFXIN input pins that meet the

specifications of the respective oscillator if the appropriate LFXTBYPASS or HFXTBYPASS mode is

selected. In this case, the associated LFXOUT and HFXOUT pins can be used for other purposes. If they

are left unused, they must be terminated according to Section 4.6.

Figure 7-2 shows a typical connection diagram.

CL1 CL2

LFXIN

HFXIN

LFXOUT

HFXOUT

130

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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MSP430FR6820

Figure 7-2. Typical Crystal Connection

See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal

oscillator with the MSP430 devices.

7.1.3 JTAG

With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or

MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the

connections also support the MSP-GANG production programmers, thus providing an easy way to

program prototype boards, if desired. Figure 7-3 shows the connections between the 14-pin JTAG

connector and the target device required to support in-system programming and debugging for 4-wire

JTAG communication. Figure 7-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).

The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are

identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSP-

FET430UIF interface modules and MSP-GANG have a VCC-sense feature that, if used, requires an

alternate connection (pin 4 instead of pin 2). The VCC-sense feature senses the local VCC present on the

target board (that is, a battery or other local power supply) and adjusts the output signals accordingly.

Figure 7-3 and Figure 7-4 show a jumper block that supports both scenarios of supplying VCC to the target

board. If this flexibility is not required, the desired VCC connections may be hard-wired to eliminate the

jumper block. Pins 2 and 4 must not be connected at the same time.

For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User's

Guide.

TDO/TDI

TDI

TMS

TCK

GND

TEST

JTAG

VCC TOOL

VCC TARGET

J1 (see Note A)

J2 (see Note A)

VCC

47 kW

AV /DVCCCC

RST/NMI/SBWTDIO

TDO/TDI

TDI

TMS

TCK

TEST/SBWTCK

AV /DVSS SS

MSP430FRxxx

2.2 nF

(see Note B)

RST

Important to connect

131

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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A. If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,

make connection J2.

B. The upper limit for C1 is 2.2 nF when using current TI tools.

Figure 7-3. Signal Connections for 4-Wire JTAG Communication

TEST/SBWTCK

MSP430FRxxx

RST/NMI/SBWTDIO

TDO/TDI

TCK

GND

JTAG

47 kΩ

(See Note B)

VCC TOOL

VCC TARGET

2.2 nF

(See Note B)

J1 (see Note A)

J2 (see Note A)

Important to connect

AV /DVCCCC

AV /DVSS SS

VCC

132

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

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A. Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the

debug or programming adapter.

B. The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during

JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with

the device. The upper limit for C1 is 2.2 nF when using current TI tools.

Figure 7-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)

7.1.4 Reset

The reset pin can be configured as a reset function (default) or as an NMI function in the special function

In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing

specifications generates a BOR-type device reset.

Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is

edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the

external NMI. When an external NMI event occurs, the NMIIFG is set.

The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either

pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.

If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an

external 47-kΩpullup resistor to the RST/NMI pin with a 10-nF pulldown capacitor. The pulldown capacitor

should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire

JTAG mode with TI tools like FET interfaces or GANG programmers.

See the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide for more information

on the referenced control registers and bits.

7.1.5 Unused Pins

For details on the connection of unused pins, see Section 4.6.

Using an

External

Positive

Reference

Using an

External

Negative

Reference

VEREF-

VREF+/VEREF+

470 nF

10 µF

470 nF10 µF

AVSS

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7.1.6 General Layout Recommendations

• Proper grounding and short traces for external crystal to reduce parasitic capacitance. See MSP430

32-kHz Crystal Oscillators for recommended layout guidelines.

• Proper bypass capacitors on DVCC, AVCC, and reference pins if used.

• Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital

switching signals such as PWM or JTAG signals away from the oscillator circuit.

• Proper ESD level protection should be considered to protect the device from unintended high-voltage

electrostatic discharge. See MSP430 System-Level ESD Considerations for guidelines.

7.1.7 Do's and Don'ts

TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up,

power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the

limits specified in Section 5.1. Exceeding the specified limits may cause malfunction of the device

including erroneous writes to RAM and FRAM.

7.2 Peripheral- and Interface-Specific Design Information

7.2.1 ADC12_B Peripheral

7.2.1.1 Partial Schematic

Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used. The

internal reference module has a maximum drive current as specified in the IO(VREF+) specification of the

REF module.

Figure 7-5. ADC12_B Grounding and Noise Considerations

7.2.1.2 Design Requirements

As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should

be followed to eliminate ground loops, unwanted parasitic effects, and noise.

Ground loops are formed when return current from the ADC flows through paths that are common with

other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset

voltages that can add to or subtract from the reference or input voltages of the ADC. The general

guidelines in Section 7.1.1 combined with the connections shown in Section 7.2.1.1 prevent this.

In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital

switching or switching power supplies can corrupt the conversion result. TI recommends a noise-free

design using separate analog and digital ground planes with a single-point connection to achieve high

accuracy.

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The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are

selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage

enters the device. In this case, the 10-µF capacitor is used to buffer the reference pin and filter any low-

frequency ripple. A 470-nF bypass capacitor is used to filter out any high-frequency noise.

7.2.1.3 Detailed Design Procedure

For additional design information, see Designing With the MSP430FR58xx, FR59xx, FR68xx, and FR69xx

ADC.

7.2.1.4 Layout Guidelines

Components that are shown in the partial schematic (see Figure 7-5) should be placed as close as

possible to the respective device pins. Avoid long traces, because they add additional parasitic

capacitance, inductance, and resistance on the signal.

Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),

because the high-frequency switching can be coupled into the analog signal.

If differential mode is used for the ADC12_B, the analog differential input signals must be routed close

together to minimize the effect of noise on the resulting signal.

7.2.2 LCD_C Peripheral

7.2.2.1 Partial Schematic

Required LCD connections greatly vary by the type of display that is used (static or multiplexed), whether

external or internal biasing is used, and whether the on-chip charge pump is employed. Also, there is a

fair amount of flexibility as to how the segment (Sx) and common (COMx) signals are connected to the

MCU which can provide unique benefits. Because LCD connections are application specific, it is difficult to

provide a single one-fits-all schematic. However, for examples and how-to circuit design guidance, see

Designing With MSP430™ MCUs and Segment LCDs.

7.2.2.2 Design Requirements

Due to the flexibility of the LCD_C peripheral module to accommodate various segment-based LCDs,

selecting the correct display for the application in combination with determining specific design

requirements is often an iterative process. TI strongly recommends reviewing the LCD_C peripheral

module chapter in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide and

Designing With MSP430™ MCUs and Segment LCDs during the initial design requirements and decision

process.

7.2.2.3 Detailed Design Procedure

A major component in designing the LCD solution is determining the exact connections between the

LCD_C peripheral module and the display itself. One of the following basic design processes can be

employed for this step, although a balanced co-design approach is often recommended:

• PCB layout-driven design that optimizes signal routing

• Software-driven design that optimizes computational overhead

For a detailed discussion of the design procedure as well as for design information regarding the LCD

controller input voltage selection including internal and external options, contrast control, and bias

generation, see Designing With MSP430™ MCUs and Segment LCDs and the LCD_C controller chapter

in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.

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7.2.2.4 Layout Guidelines

LCD segment (Sx) and common (COMx) signal traces are continuously switching while the LCD is

enabled and should, therefore, be kept away from sensitive analog signals such as ADC inputs to prevent

any noise coupling. TI recommends keeping the LCD signal traces on one side of the PCB grouped

together in a bus-like fashion. A ground plane underneath the LCD traces and guard traces employed

alongside the LCD traces can provide shielding.

If the internal charge pump of the LCD module is used, the externally provided capacitor on the LCDCAP

pin should be as close as possible to the MCU. The capacitor should be connected to the device using a

short and direct trace and also have a solid connection to the ground plane that supplies the VSS pins of

the MCU.

For an example layouts and a more in-depth discussion of this topic see Designing With MSP430™ MCUs

and Segment LCDs.

Feature Set

Series

Processor Family

Temperature Range

MCU Platform

Memory Type

Distribution Format

Packaging

MSP 430 FR 69721 IRGC R

Optional: BSL

FRAM

AES

Oscillators

Processor Family MSP = Mixed Signal Processor

XMS = Experimental Silicon

MCU Platform 430 = TI’s 16-bit MSP430 Low-Power Microcontroller Platform

Memory Type FR = FRAM

Series 6 = FRAM 6 Series up to 16 MHz with LCD

Feature Set AES

9 = AES

8 = No AES

Oscillators

7 = HFXT and LFXT

2 = LFXT

FRAM (KB)

2 = 64

0 = 32

Optional - BSL

1 = I C

No value = UART

Temperature Range

Packaging http://www.ti.com/packaging

Distribution Format T = Small reel

R = Large reel

No markings = Tube or tray

I = –40°C to 85°C

136

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MSP430FR6872

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MSP430FR6870

MSP430FR6922

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8 Device and Documentation Support

8.1 Getting Started and Next Steps

For more information on the MSP430™ family of devices and the tools and libraries that are available to

help with your development, visit the Getting Started page.

8.2 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS.

These prefixes represent evolutionary stages of product development from engineering prototypes (XMS)

through fully qualified production devices (MSP).

XMS – Experimental device that is not necessarily representative of the final device's electrical

specifications

MSP – Fully qualified production device

XMS devices are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

MSP devices have been characterized fully, and the quality and reliability of the device have been

demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (XMS) have a greater failure rate than the standard production

devices. TI recommends that these devices not be used in any production system because their expected

end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the

temperature range, package type, and distribution format. Figure 8-1 provides a legend for reading the

complete device name.

Figure 8-1. Device Nomenclature

137

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MSP430FR68721

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8.3 Tools and Software

All MSP microcontrollers are supported by a wide variety of software and hardware development tools.

Tools are available from TI and various third parties. See them all at Development Kits and Software for

Low-Power MCUs.

Table 8-1 lists the debug features of the MSP430FR697x(1), MSP430FR687x(1), MSP430FR692x(1), and

MSP430FR682x(1) MCUs. See the Code Composer Studio for MSP430 User's Guide for details on the

available features.

Table 8-1. Hardware Debug Features

MSP430

ARCHITECTURE 4-WIRE

JTAG 2-WIRE

JTAG BREAK-

POINTS

RANGE

BREAK-

POINTS

CLOCK

CONTROL STATE

SEQUENCER TRACE

BUFFER

LPMx.5

DEBUGGING

SUPPORT

EnergyTrace++

TECHNOLOGY

MSP430Xv2 Yes Yes 3 Yes Yes No No Yes Yes

Design Kits and Evaluation Modules

MSP430FR6989 LaunchPad Development Kit The MSP-EXP430FR6989 LaunchPad Development Kit

is an easy-to-use Evaluation Module (EVM) for the MSP40FR6989 microcontroller (MCU). It

contains everything needed to start developing on the ultra-low-power MSP430FRx FRAM

microcontroller platform, including onboard emulation for programming, debugging, and

energy measurements.

MSP-TS430PM64F - MSP430 64-pin FRAM Target Socket Board The MSP-TS430PZ5X100 is a stand-

alone ZIF socket target board used to program and debug the MSP430 MCU in-system

through the JTAG interface or the Spy-Bi-Wire (2-wire JTAG) protocol.

MSP-FET430U64F - MSP430 64-pin FRAM TS Board and MSP-FET Bundle The MSP-FET430U64F is

a bundle containing the MSP-FET emulator and a stand-alone 64-pin ZIF socket target

board to program and debug the MSP430 in-system through the JTAG interface or the Spy-

Bi-Wire (2-wire JTAG) protocol. The TS development board supports the MSP430FR6972

FRAM device in a 64-pin LQFP package (TI package code: PM).

Software

MSP430Ware™ Software MSP430Ware software is a collection of code examples, data sheets, and

other design resources for all MSP430 devices delivered in a convenient package. In

addition to providing a complete collection of existing MSP430 MCU design resources,

MSP430Ware software also includes a high-level API called MSP Driver Library. This library

makes it easy to program MSP430 hardware. MSP430Ware software is available as a

component of CCS or as a stand-alone package.

MSP430FR592x, MSP430FR5x7x, MSP430FR6x2x, MSP430FR6x7x Code Examples C Code

examples are available for every MSP device that configures each of the integrated

peripherals for various application needs.

Capacitive Touch Software Library Free C libraries for enabling capacitive touch capabilities on

MSP430 MCUs. The MSP430 MCU version of the library features several capacitive touch

implementations including the RO and RC method.

MSP Driver Library The abstracted API of MSP Driver Library provides easy-to-use function calls that

free you from directly manipulating the bits and bytes of the MSP430 hardware. Thorough

documentation is delivered through a helpful API Guide, which includes details on each

function call and the recognized parameters. Developers can use Driver Library functions to

write complete projects with minimal overhead.

MSP EnergyTrace™ Technology EnergyTrace technology for MSP430 microcontrollers is an energy-

based code analysis tool that measures and displays the energy profile of the application

and helps to optimize it for ultra-low-power consumption.

ULP (Ultra-Low Power) Advisor ULP Advisor™ software is a tool for guiding developers to write more

efficient code to fully use the unique ultra-low-power features of MSP and MSP432

microcontrollers. Aimed at both experienced and new microcontroller developers, ULP

Advisor checks your code against a thorough ULP checklist to help minimize the energy

consumption of your application. At build time, ULP Advisor provides notifications and

remarks to identify areas of your code that can be further optimized for lower power.

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MSP430FR6820

IEC60730 Software Package The IEC60730 MSP430 software package was developed to help

customers comply with IEC 60730-1:2010 (Automatic Electrical Controls for Household and

Similar Use – Part 1: General Requirements) for up to Class B products, which includes

home appliances, arc detectors, power converters, power tools, e-bikes, and many others.

The IEC60730 MSP430 software package can be embedded in customer applications

running on MSP430s to help simplify the customer’s certification efforts of functional safety-

compliant consumer devices to IEC 60730-1:2010 Class B.

Fixed Point Math Library for MSP The MSP IQmath and Qmath Libraries are a collection of highly

optimized and high-precision mathematical functions for C programmers to seamlessly port a

floating-point algorithm into fixed-point code on MSP430 and MSP432 devices. These

routines are typically used in computationally intensive real-time applications where optimal

execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and

Qmath libraries, it is possible to achieve execution speeds considerably faster and energy

consumption considerably lower than equivalent code written using floating-point math.

Floating Point Math Library for MSP430 Continuing to innovate in the low-power and low-cost

microcontroller space, TI provides MSPMATHLIB. Leveraging the intelligent peripherals of

MSP devices, this floating-point math library of scalar functions is up to 26 times faster than

the standard MSP430 math functions. Mathlib is easy to integrate into your designs. This

library is free and is integrated in both Code Composer Studio IDE and IAR Embedded

Workbench IDE.

Development Tools

Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers Code

Composer Studio (CCS) integrated development environment (IDE) supports all MSP

microcontroller devices. CCS comprises a suite of embedded software utilities used to

develop and debug embedded applications. CCS includes an optimizing C/C++ compiler,

source code editor, project build environment, debugger, profiler, and many other features.

Command-Line Programmer MSP Flasher is an open-source shell-based interface for programming

MSP microcontrollers through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire

(SBW) communication. MSP Flasher can download binary files (.txt or .hex) directly to the

MSP microcontroller without an IDE.

MSP MCU Programmer and Debugger The MSP-FET is a powerful emulation development tool – often

called a debug probe – which lets users quickly begin application development on MSP low-

power MCUs. Creating MCU software usually requires downloading the resulting binary

program to the MSP device for validation and debugging.

MSP-GANG Production Programmer The MSP Gang Programmer is an MSP430 or MSP432 device

programmer that can program up to eight identical MSP430 or MSP432 flash or FRAM

devices at the same time. The MSP Gang Programmer connects to a host PC using a

standard RS-232 or USB connection and provides flexible programming options that let the

user fully customize the process.

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MSP430FR68721

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8.4 Documentation Support

The following documents describe the MSP430FR697x(1), MSP430FR687x(1), MSP430FR692x(1), and

MSP430FR682x(1) MCUs. Copies of these documents are available on the Internet at www.ti.com.

Receiving Notification of Document Updates

To receive notification of documentation updates—including silicon errata—go to the product folder for

your device on ti.com (for links to product folders, see Section 8.5). In the upper right corner, click the

"Alert me" button. This registers you to receive a weekly digest of product information that has changed (if

any). For change details, check the revision history of any revised document.

Errata

MSP430FR6972 Device Erratasheet Describes the known exceptions to the functional specifications.

MSP430FR69721 Device Erratasheet Describes the known exceptions to the functional specifications.

MSP430FR6970 Device Erratasheet Describes the known exceptions to the functional specifications.

MSP430FR6922 Device Erratasheet Describes the known exceptions to the functional specifications.

MSP430FR69221 Device Erratasheet Describes the known exceptions to the functional specifications.

MSP430FR6920 Device Erratasheet Describes the known exceptions to the functional specifications.

MSP430FR6872 Device Erratasheet Describes the known exceptions to the functional specifications.

MSP430FR68721 Device Erratasheet Describes the known exceptions to the functional specifications.

MSP430FR6870 Device Erratasheet Describes the known exceptions to the functional specifications.

MSP430FR6822 Device Erratasheet Describes the known exceptions to the functional specifications.

MSP430FR68221 Device Erratasheet Describes the known exceptions to the functional specifications.

MSP430FR6820 Device Erratasheet Describes the known exceptions to the functional specifications.

User's Guides

MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide Detailed information on

the modules and peripherals available in this device family.

MSP430 FRAM Device Bootloader (BSL) User's Guide The bootloader (BSL) on MSP430 MCUs lets

users communicate with embedded memory in the MSP430 MCU during the prototyping

phase, final production, and in service. Both the programmable memory (FRAM memory)

and the data memory (RAM) can be modified as required.

MSP430 Programming With the JTAG Interface This document describes the functions that are

required to erase, program, and verify the memory module of the MSP430 flash-based and

FRAM-based microcontroller families using the JTAG communication port. In addition, it

describes how to program the JTAG access security fuse that is available on all MSP430

devices. This document describes device access using both the standard 4-wire JTAG

interface and the 2-wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW).

MSP430 Hardware Tools User's Guide This manual describes the hardware of the TI MSP-FET430

Flash Emulation Tool (FET). The FET is the program development tool for the MSP430 ultra-

low-power microcontroller. Both available interface types, the parallel port interface and the

USB interface, are described.

Application Reports

Designing With MSP430 and Segment LCDs Segment liquid crystal displays (LCDs) are needed to

provide information to users in a wide variety of applications from smart meters to electronic

shelf labels (ESLs) to medical equipment. Several MSP430™ microcontroller families include

built-in low-power LCD driver circuitry that allows the MSP430 MCU to directly control the

segmented LCD glass. This application note helps explain how segmented LCDs work, the

different features of the various LCD modules across the MSP430 MCU family, LCD

hardware layout tips, guidance on writing efficient and easy-to-use LCD driver software, and

an overview of the portfolio of MSP430 devices that include different LCD features to aid in

device selection.

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MSP430FR6820

MSP430 FRAM Technology – How-To and Best Practices FRAM is a nonvolatile memory technology

that behaves like SRAM while enabling a whole host of new applications, but also changes

the way firmware should be designed. This application report outlines the how-to and best

practices of using FRAM technology in MSP430 from an embedded software development

perspective. It discusses how to implement a memory layout according to application-specific

code, constant, data space requirements, the use of FRAM to optimize application energy

consumption, and the use of the Memory Protection Unit (MPU) to maximize application

robustness by protecting the program code against unintended write accesses.

MSP430 32-kHz Crystal Oscillators Selection of the correct crystal, correct load circuit, and proper

board layout are important for a stable crystal oscillator. This application report summarizes

crystal oscillator function and explains the parameters to select the correct crystal for

MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout

are given. The document also contains detailed information on the possible oscillator tests to

ensure stable oscillator operation in mass production.

MSP430 System-Level ESD Considerations System-Level ESD has become increasingly demanding

with silicon technology scaling towards lower voltages and the need for designing cost-

effective and ultra-low-power components. This application report addresses three different

ESD topics to help board designers and OEMs understand and design robust system-level

designs.

8.5 Related Links

Table 8-2 lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 8-2. Related Links

PARTS PRODUCT FOLDER ORDER NOW TECHNICAL

DOCUMENTS TOOLS &

SOFTWARE SUPPORT &

COMMUNITY

MSP430FR6972 Click here Click here Click here Click here Click here

MSP430FR69721 Click here Click here Click here Click here Click here

MSP430FR6970 Click here Click here Click here Click here Click here

MSP430FR6872 Click here Click here Click here Click here Click here

MSP430FR68721 Click here Click here Click here Click here Click here

MSP430FR6870 Click here Click here Click here Click here Click here

MSP430FR6922 Click here Click here Click here Click here Click here

MSP430FR69221 Click here Click here Click here Click here Click here

MSP430FR6920 Click here Click here Click here Click here Click here

MSP430FR6822 Click here Click here Click here Click here Click here

MSP430FR68221 Click here Click here Click here Click here Click here

MSP430FR6820 Click here Click here Click here Click here Click here

8.6 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the

respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;

see TI's Terms of Use.

TI E2E™ Community

TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At

e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow

engineers.

TI Embedded Processors Wiki

Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded

processors from Texas Instruments and to foster innovation and growth of general knowledge about the

hardware and software surrounding these devices.

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MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

www.ti.com

SLASE23E –JANUARY 2015–REVISED AUGUST 2018

Submit Documentation Feedback

Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721

MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

8.7 Trademarks

EnergyTrace++, MSP430, MSP430Ware, EnergyTrace, ULP Advisor, Code Composer Studio, E2E are

trademarks of Texas Instruments.

Microsoft is a registered trademark of Microsoft Corporation.

All other trademarks are the property of their respective owners.

8.8 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.9 Export Control Notice

Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data

(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any

controlled product restricted by other applicable national regulations, received from disclosing party under

nondisclosure obligations (if any), or any direct product of such technology, to any destination to which

such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior

authorization from U.S. Department of Commerce and other competent Government authorities to the

extent required by those laws.

8.10 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

142

MSP430FR6972

MSP430FR69721

MSP430FR6970

MSP430FR6872

MSP430FR68721

MSP430FR6870

MSP430FR6922

MSP430FR69221

MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

SLASE23E –JANUARY 2015–REVISED AUGUST 2018

www.ti.com

Submit Documentation Feedback

Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721

MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

9 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the

most current data available for the designated devices. This data is subject to change without notice and

revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 16-Jan-2018

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

MSP430FR6820IG56R ACTIVE TSSOP DGG 56 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6820

MSP430FR6820IPMR ACTIVE LQFP PM 64 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6820

MSP430FR6820IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6820

MSP430FR68221IG56R ACTIVE TSSOP DGG 56 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR68221

MSP430FR68221IPMR ACTIVE LQFP PM 64 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR68221

MSP430FR68221IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR68221

MSP430FR6822IG56R ACTIVE TSSOP DGG 56 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6822

MSP430FR6822IPMR ACTIVE LQFP PM 64 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6822

MSP430FR6822IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6822

MSP430FR6870IPMR ACTIVE LQFP PM 64 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6870

MSP430FR6870IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6870

MSP430FR68721IPMR ACTIVE LQFP PM 64 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR68721

MSP430FR68721IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR68721

MSP430FR6872IPMR ACTIVE LQFP PM 64 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6872

MSP430FR6872IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6872

MSP430FR6920IG56R ACTIVE TSSOP DGG 56 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6920

MSP430FR6920IPMR ACTIVE LQFP PM 64 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6920

PACKAGE OPTION ADDENDUM

www.ti.com 16-Jan-2018

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

MSP430FR6920IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6920

MSP430FR69221IG56 ACTIVE TSSOP DGG 56 35 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR69221

MSP430FR69221IG56R ACTIVE TSSOP DGG 56 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR69221

MSP430FR69221IPM ACTIVE LQFP PM 64 160 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR69221

MSP430FR69221IPMR ACTIVE LQFP PM 64 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR69221

MSP430FR69221IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR69221

MSP430FR69221IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR69221

MSP430FR6922IG56 ACTIVE TSSOP DGG 56 35 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6922

MSP430FR6922IG56R ACTIVE TSSOP DGG 56 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6922

MSP430FR6922IPM ACTIVE LQFP PM 64 160 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6922

MSP430FR6922IPMR ACTIVE LQFP PM 64 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6922

MSP430FR6922IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6922

MSP430FR6922IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6922

MSP430FR6970IPMR ACTIVE LQFP PM 64 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6970

MSP430FR6970IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6970

MSP430FR69721IPM ACTIVE LQFP PM 64 160 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR69721

MSP430FR69721IPMR ACTIVE LQFP PM 64 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR69721

MSP430FR69721IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR69721

PACKAGE OPTION ADDENDUM

www.ti.com 16-Jan-2018

Addendum-Page 3

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

MSP430FR69721IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR69721

MSP430FR6972IPM ACTIVE LQFP PM 64 160 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6972

MSP430FR6972IPMR ACTIVE LQFP PM 64 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6972

MSP430FR6972IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6972

MSP430FR6972IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR6972

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

PACKAGE OPTION ADDENDUM

www.ti.com 16-Jan-2018

Addendum-Page 4

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

MSP430FR6820IG56R TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1

MSP430FR6820IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2

MSP430FR6820IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2

MSP430FR68221IG56R TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1

MSP430FR68221IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2

MSP430FR68221IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2

MSP430FR6822IG56R TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1

MSP430FR6822IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2

MSP430FR6822IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2

MSP430FR6870IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2

MSP430FR6870IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2

MSP430FR68721IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2

MSP430FR68721IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2

MSP430FR6872IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2

MSP430FR6872IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2

MSP430FR6920IG56R TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1

MSP430FR6920IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2

MSP430FR6920IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2018

Pack Materials-Page 1

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

MSP430FR69221IG56R TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1

MSP430FR69221IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2

MSP430FR69221IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2

MSP430FR69221IRGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2

MSP430FR6922IG56R TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1

MSP430FR6922IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2

MSP430FR6922IRGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2

MSP430FR6970IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2

MSP430FR6970IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2

MSP430FR69721IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2

MSP430FR69721IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2

MSP430FR69721IRGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2

MSP430FR6972IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2

MSP430FR6972IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2

MSP430FR6972IRGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

MSP430FR6820IG56R TSSOP DGG 56 2000 367.0 367.0 45.0

MSP430FR6820IPMR LQFP PM 64 1000 336.6 336.6 41.3

PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2018

Pack Materials-Page 2

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

MSP430FR6820IRGCR VQFN RGC 64 2000 367.0 367.0 38.0

MSP430FR68221IG56R TSSOP DGG 56 2000 367.0 367.0 45.0

MSP430FR68221IPMR LQFP PM 64 1000 336.6 336.6 41.3

MSP430FR68221IRGCR VQFN RGC 64 2000 367.0 367.0 38.0

MSP430FR6822IG56R TSSOP DGG 56 2000 367.0 367.0 45.0

MSP430FR6822IPMR LQFP PM 64 1000 336.6 336.6 41.3

MSP430FR6822IRGCR VQFN RGC 64 2000 367.0 367.0 38.0

MSP430FR6870IPMR LQFP PM 64 1000 336.6 336.6 41.3

MSP430FR6870IRGCR VQFN RGC 64 2000 367.0 367.0 38.0

MSP430FR68721IPMR LQFP PM 64 1000 336.6 336.6 41.3

MSP430FR68721IRGCR VQFN RGC 64 2000 367.0 367.0 38.0

MSP430FR6872IPMR LQFP PM 64 1000 336.6 336.6 41.3

MSP430FR6872IRGCR VQFN RGC 64 2000 367.0 367.0 38.0

MSP430FR6920IG56R TSSOP DGG 56 2000 367.0 367.0 45.0

MSP430FR6920IPMR LQFP PM 64 1000 336.6 336.6 41.3

MSP430FR6920IRGCR VQFN RGC 64 2000 367.0 367.0 38.0

MSP430FR69221IG56R TSSOP DGG 56 2000 367.0 367.0 45.0

MSP430FR69221IPMR LQFP PM 64 1000 336.6 336.6 41.3

MSP430FR69221IRGCR VQFN RGC 64 2000 367.0 367.0 38.0

MSP430FR69221IRGCT VQFN RGC 64 250 210.0 185.0 35.0

MSP430FR6922IG56R TSSOP DGG 56 2000 367.0 367.0 45.0

MSP430FR6922IPMR LQFP PM 64 1000 336.6 336.6 41.3

MSP430FR6922IRGCT VQFN RGC 64 250 210.0 185.0 35.0

MSP430FR6970IPMR LQFP PM 64 1000 336.6 336.6 41.3

MSP430FR6970IRGCR VQFN RGC 64 2000 367.0 367.0 38.0

MSP430FR69721IPMR LQFP PM 64 1000 336.6 336.6 41.3

MSP430FR69721IRGCR VQFN RGC 64 2000 367.0 367.0 38.0

MSP430FR69721IRGCT VQFN RGC 64 250 210.0 185.0 35.0

MSP430FR6972IPMR LQFP PM 64 1000 336.6 336.6 41.3

MSP430FR6972IRGCR VQFN RGC 64 2000 367.0 367.0 38.0

MSP430FR6972IRGCT VQFN RGC 64 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2018

Pack Materials-Page 3

www.ti.com

PACKAGE OUTLINE

TYP

8.3

7.9

1.2 MAX

54X 0.5

56X 0.27

0.17

13.5

(0.15) TYP

0 - 8

0.15

0.05

0.25

GAGE PLANE

0.75

0.50

NOTE 3

14.1

13.9

B6.2

6.0

4222167/A 07/2015

TSSOP - 1.2 mm max heightDGG0056A

SMALL OUTLINE PACKAGE

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

156

0.08 C A B

PIN 1 ID

AREA

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 1.200

www.ti.com

EXAMPLE BOARD LAYOUT

(7.5)

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

56X (1.5)

56X (0.3)

54X (0.5)

(R )

TYP

0.05

4222167/A 07/2015

TSSOP - 1.2 mm max heightDGG0056A

SMALL OUTLINE PACKAGE

SYMM

LAND PATTERN EXAMPLE

SCALE:6X

28 29

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

(7.5)

54X (0.5)

56X (0.3)

56X (1.5)

(R ) TYP0.05

4222167/A 07/2015

TSSOP - 1.2 mm max heightDGG0056A

SMALL OUTLINE PACKAGE

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

SYMM

28 29

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:6X

MECHANICAL DATA

MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PM (S-PQFP-G64) PLASTIC QUAD FLATPACK

4040152/C 11/96

17 0,13 NOM

0,25

0,45

0,75

Seating Plane

0,05 MIN

Gage Plane

0,27

0,17

10,20

11,80

12,20

9,80

7,50 TYP

1,60 MAX

1,45

1,35

0,08

0,50 M

0,08

0°–7°

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

D. May also be thermally enhanced plastic with leads connected to the die pads.

IMPORTANT NOTICE

Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its

semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers

should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated

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