Freescale Semiconductor
Data Sheet: Document Number: MSC8122
Rev. 16, 12/2008
© Freescale Semiconductor, Inc., 2004, 2008. All rights reserved.
MSC8122
FC PBGA–431
20 mm ×20 mm
• Four StarCore™ SC140 DSP extended cores, each with an SC140
DSP core, 224 Kbyte of internal SRAM M1 memory (1436 Kbyte
total), 16 way 16 Kbyte instruction cache (ICache), four-entry
write buffer, external cache support, programmable interrupt
controller (PIC), local interrupt controller (LIC), and low-power
Wai t and Stop processing modes.
• 475 Kbyte M2 memory for critical data and temporary data
buffering.
• 4 Kbyte boot ROM.
• M2-accessible multi-core MQBus con necting the M2 memory
with all four cores, operating at the core frequency, with data bus
access of up to 128-bit reads and up to 64-bit writes, central
efficient round-robin arbiter for core access to the bus, and atomic
operation control of M2 memory access by the cores and the local
bus.
• Internal PLL conf igured are reset by config uration signal values.
• 60x-compatible system bus with 64 or 32 bit data and 32-bit
address bus, support for multi-master designs, four-beat burst
transfers (eight- beat in 3 2-bit dat a mode), po rt size of 64/3 2/16 /8
bits cont rolled by the internal memory co ntroller,.access to
external memory or peripheral s, access by an extern al host to
internal resou rc es, slave support wi th direct access to internal
resources in cluding M1 and M2 memories, and on-device
arbitration for up to four master devices.
• Direct slave interface (DSI) using a 32/64-bit slave host interface
with 21 –25 bit add ressing and 32/ 64-bit data transf er s, direct
access by an ex ternal host to internal and exte rnal resources,
synchronous or asynchronous accesses with burst capability in
synchronous mode, dual or single s trobe mode, write and read
buffers to improve host bandwidth, byte enable signals for
1/2/4/8-byte write granularity, sliding window mode for access
using a re duced num ber of address pins, chip ID decoding to
allow one CS signal to contr ol multiple DS Ps, broad cast mod e to
write to multiple DSPs, and big-endian/little-endian/munged
support.
• Three mode signal multiplexing: 64-bit DSI and 32-bit system
bus, 32-bit DSI and 64-bit system bus, or 32-bit DSI and 32-bit
system bus .
• Flexible memory controller with three UPMs, a GPCM, a
page-mode SDRAM machine, glueless interface to a variety of
memo r ie s a nd de vices, b yte e na bles for 6 4- or 32-bit bus w idths,
8 memory banks for external memories, and 2 memory banks for
IPBus peripherals and internal memories.
• Multi-channel DMA controller with 16 time-multiplexed single
channels, up to four external peripherals, DONE or DRACK
protocol for two external peripherals,.service for up to 16 internal
requests from up to 8 internal FIFOs per channel, FIFO generated
watermarks and hungry requests, priority-based
time- multiplexing between chan nels using 16 in terna l priority
levels or round-robin time-multiplexing between channels,
flexible channel configuration with connection to local bus or
system bus, and flyby transfer support that bypasses the FIFO.
• Up to four independent TDM modules with programmable word
size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion,
up to 128 Mbps data rate for all channels, with glueless interface
to E1 or T1 framers, and can interface with H-MVIP/H.110
devices, TSI, and codecs such as AC-97.
• Ethernet controller with support for 10/100 Mbps MII/RMII/SMII
including full- and half-duplex operation, full-duplex flow
controls, out-of-sequence transmi t queues, program mable
maximu m frame length includi ng jumbo frame s and VLAN tags
and priority, retransmission after collision, CRC generation and
verification of inboun d/outbo un d pa c ke ts , address rec og nition
(including exact match, broadcast address, individual hash check,
group hash che ck, and promiscuous mode), pattern matching,
insertion with expansion or replacement for transmit frames,
VLAN tag insertion, RM ON statistics, local bus master DMA for
descriptor fetching and buffer access, and optional multiplexing
with GPIO (MII/RMII/SMII) or DSI/system bus signals lines
(MII/RMII).
• UART with full-duplex operation up to 6.2 5 Mbps.
• Up to 32 general-purpose input/output (GPIO) ports.
•I
2C interface that allows booting from EEPROM devices.
• Two timer modules, e a ch with sixte en c onfigurable 16-bit timers.
• Eight programmable hard war e semaphores.
• Global interrupt contro ller (GIC) with int errupt consolida tion and
routing to INT_OUT , NMI_OUT , and the cores; thirty-two virtual
maskable interrupts (8 per core) and four virtual NMI (one per
core) that can be generated by a simple write acce ss.
• Optional booting external memory, external ho st, UART, TDM,
or I2C.
Quad Digital Signal
Processor
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freesca le Sem ico nd uctor2
Table of Contents
1 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 FC-PBGA Ba ll La yout Diagrams. . . . . . . . . . . . . . . . . . .4
1.2 Signal List By Ball Location . . . . . . . . . . . . . . . . . . . . . . .7
2 Ele c t r i c a l C h a ra c t e r i s t i c s . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.1 Max imum Ra ting s . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.2 Recommended Operating Conditions. . . . . . . . . . . . . .14
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .14
2.4 DC Electrical Chara c te ristics . . . . . . . . . . . . . . . . . . . .15
2.5 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3 Hardware Design Considerations. . . . . . . . . . . . . . . . . . . . . .39
3.1 Start-up Sequencing Recommendations . . . . . . . . . . .39
3.2 Power Supply Design Considerations. . . . . . . . . . . . . .40
3.3 Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .41
3.4 External SDRAM Selection. . . . . . . . . . . . . . . . . . . . . .42
3.5 The rm a l C o n s i d e ra tion s . . . . . . . . . . . . . . . . . . . . . . . .4 3
4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6 Pro duct D o c u menta ti o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
7 Revisio n History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
List of Figures
Figure 1. MSC8122 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. StarCore SC140 DS P Extended Core Block Diagram . . 3
Figure 3. MSC8122 Package, Top View . . . . . . . . . . . . . . . . . . . . 5
Figure 4. MSC8122 Package, Bottom View. . . . . . . . . . . . . . . . . . 6
Figure 5. Overshoot/Undersho ot Voltage for VIH and VIL. . . . . . . 1 6
Figure 6. Start-Up Sequence: VDD and VDDH Raised Together . . 17
Figure 7. Start-Up Sequence: VDD Raised Before VDDH with CLKIN
Started with VDDH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. Power-Up Sequence for VDDH and VDD/VCCSYN . . . . . 18
Figure 9. Timing Diagram for a Reset Configuration Write . . . . . 21
Figure 10.Internal Tick Spacing for Memory Controller Signals. . . 22
Figure 11.SIU T iming Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12.CLKOUT and CLKIN Signals. . . . . . . . . . . . . . . . . . . . . 26
Figure 13.DMA Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14.Asynchronous Single- and Dual-Strobe Modes Read
Timing Diagr a m. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15.Asynchr onous Single- and Dual-Strobe Modes Write
Timing Diagr a m. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 16.Asynchr onous Broadc ast Write Timing Diagram. . . . . . 30
Figure 17.DSI Synchronous Mode Signals Timing Diagram . . . . . 31
Figure 18.TDM Inputs Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19.TDM Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 20.UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 21.UART Ou tp u t Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 22.Timer Ti min g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 23.MDIO Timing Rela tio n s h i p to MDC . . . . . . . . . . . . . . . . 34
Figure 24.MII Mode Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 25.RMII Mode Signal Timing . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 26.SMII Mode Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 27.GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 28.EE Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 29.Test Clock Input Timing Diagram. . . . . . . . . . . . . . . . . . 38
Figure 30.Boundary Scan (JTAG) T iming Diagram . . . . . . . . . . . . 38
Figure 31.Test Access Port Timing Dia gram . . . . . . . . . . . . . . . . . 39
Figure 32.TRST Timing Diag ram. . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 33.Core Power Supply Decoupling. . . . . . . . . . . . . . . . . . . 40
Figure 34.VCCSYN Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 35.MSC8122 Mechanical Information, 431-pin FC-PBGA
Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 3
Figure 1. MSC8122 Block Diagram
Figure 2. StarCore SC140 DSP Extended Core Block Diagram
MQBus SQBus
Local Bu s
128
128
Boot
ROM
64
PLL
JTAG
RS-232
Internal Local Bus
Interna l Sy stem Bus
IPBus
IP M as te r
64
64
UART
Memory
Controller
M2
RAM
GPIO P in s
Interrupts
Memory
Controller
System Bus
32/64
DSI Port
32
32/64
PLL/Clock
JTAG Port
SC140
Extended Core SC140
Extended Core SC140
Extended Core
System
Interface
32 Timers
4 TDMs
DMA
Bridge SIU
Registers
Direct
Slave
Interface
(DSI)
8 Ha rdware
Semaphores
GIC
GPIO
MII/RMII/SMII
Ethernet
SC140
Extende d Core
SC140
Power
Management
Core
Program
Sequencer Address
Register
File Data ALU
Register
File
Address
ALU
EOnCEJTAG
Xa
Xb
P
QBus
IRQs
IRQs
MQBus
SQBus
Local Bus
128 128
64
64 64
LIC
PIC
128
128
QBus
Interface
Instruction
Cache
M1
RAM
Notes: 1. The arrows show the data transfer direction.
QBus
Bank 1 QBus
Bank 3
2. The QBus interface includes a bus switch, write buffer, fetch unit, and a control unit that defines
four QBus banks. In addition, the QBC handles internal memory contentions.
QBC
SC140 Core
Data
ALU
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Pin Assignments
Freesca le Sem ico nd uctor4
1 Pin Assignments
This section includes diagrams of the MSC8122 package ball grid array layouts and pinout allocation tables.
1.1 FC-PBGA Ball Layout Diagrams
Top and bottom views of the FC-PBGA package are shown in Figure 3 and Figure 4 with their ball location index numbers.
Pin Assignments
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 5
Figure 3. MSC8122 Package, Top View
2345678910111213141516171819202122
BVDD GND GND NMI_
OUT GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GPIO0 VDD VDD GND
CGND VDD TDO S
RESET GPIO28 HCID1 GND VDD GND VDD GND VDD GND GND GPIO30 GPIO2 GPIO1 GPIO7 GPIO3 GPIO5 GPIO6
D TDI EE0 EE1 GND VDDH HCID2 HCID3 GND VDD GND VDD GND VDD VDD GPIO31 GPIO29 VDDH GPIO4 VDDH GND GPIO8
ETCK TRST TMS HRESET GPIO27 HCID0 GND VDD GND VDD GND VDD GND GND VDD GND GND GPIO9 GPIO13 GPIO10 GPIO1
2
FPO
RESET RST
CONF NMI HA29 HA22 GND VDD VDD VDD GND VDD GND VDD ETHRX_
CLK ETHTX_
CLK GPIO20 GPIO18 GPIO16 GPIO11 GPIO14 GPIO1
9
GHA24HA27HA25HA23HA17PWE0VDD VDD BADDR
31 BM0 ABB VDD INT_
OUT ETHCR
SVDD CS1 BCTL0 GPIO15 GND GPIO17 GPIO2
2
HHA20HA28 VDD HA19 TEST PSD
CAS PGTA VDD BM1 ARTRY AACK DBB HTA VDD TT4 CS4 GPIO24 GPIO21 VDD VDDH A31
JHA18HA26 VDD HA13 GND PSDA
MUX BADDR
27 VDD CLKIN BM2 DBG VDD GND VDD TT3 PSDA10 BCTL1 GPIO23 GND GPIO25 A30
K HA15 HA21 HA16 PWE3 PWE1 POE BADDR
30 Res. GND GND GND GND CLKOUT VDD TT2 ALE CS2 GND A26 A29 A28
LHA12HA14HA11VDDH VDDH BADDR
28 BADDR
29 GND GND GND VDDH GND GND CS3 VDDH A27 A25 A22
M HD28 HD31 VDDH GND GND GND VDD VDDH GND GND VDDH HB
RST VDDH VDDH GND VDDH A24 A21
N HD26 HD30 HD29 HD24 PWE2 VDDH HWBS
0HBCS GND GND HRDS BG HCS CS0 PSDWE GPIO26 A23 A20
P HD20 HD27 HD25 HD23 HWBS
3HWBS
2HWBS
1HCLKIN GND GNDSYN VCCSYN GND GND TA BR TEA PSD
VAL DP0 VDDH GND A19
R HD18 VDDH GND HD22 HWBS
6HWBS
4TSZ1 TSZ3 GBL VDD VDD VDD TT0 DP7 DP6 DP3 TS DP2 A17 A18 A16
T HD17 HD21 HD1 HD0 HWBS
7HWBS
5TSZ0 TSZ2 TBST VDD D16 TT1 D21 D23 DP5 DP4 DP1 D30 GND A15 A14
U HD16 HD19 HD2 D2 D3 D6 D8 D9 D11 D14 D15 D17 D19 D22 D25 D26 D28 D31 VDDH A12 A13
V HD3 VDDH GNDD0D1D4D5D7D10D12D13D18D20GNDD24D27D29A8A9A10A11
W HD6 HD5 HD4 GND GND VDDH VDDH GND HDST1 HDST0 VDDH GND HD40 VDDH HD33 VDDH HD32 GND GND A7 A6
Y HD7 HD15 VDDH HD9 VDD HD60 HD58 GND VDDH HD51 GND VDDH HD43 GND VDDH GND HD37 HD34 VDDH A4 A5
AA VDD HD14 HD12 HD10 HD63 HD59 GND VDDH HD54 HD52 VDDH GND VDDH HD46 GND HD42 HD38 HD35 A0 A2 A3
AB GND HD13 HD11 HD8 HD62 HD61 HD57 HD56 HD55 HD53 HD50 HD49 HD48 HD47 HD45 HD44 HD41 HD39 HD36 A1 VDD
Top View
MSC8122
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Pin Assignments
Freesca le Sem ico nd uctor6
Figure 4. MSC8122 Package, Bottom View
2221201918171615141312111098765432
BGND VDD VDD GPIO0 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND NMI_
OUT GND GND VDD
C GPIO6 GPIO5 GPIO3 GPIO7 GPIO1 GPIO2 GPIO30 GND GND VDD GND VDD GND VDD GND HCID1 GPIO28 S
RESET TDO VDD GND
D GPIO8 GND VDDH GPIO4 VDDH GPIO29 GPIO31 VDD VDD GND VDD GND VDD GND HCID3 HCID2 VDDH GND EE1 EE0 TDI
EGPIO12 GPIO10 GPIO13 GPIO9 GND GND VDD GND GND VDD GND VDD GND VDD GND HCID0 GPIO27 HRESET TMS TRST TCK
F GPIO19 GPIO14 GPIO11 GPIO16 GPIO18 GPIO20 ETHTX_
CLK ETHRX_
CLK VDD GND VDD GND VDD VDD VDD GND HA22 HA29 NMI RST
CONF PO
RESET
G GPIO22 GPIO17 GND GPIO15 BCTL0 CS1 VDD ETHCR
SINT_
OUT VDD ABB BM0 BADDR
31 VDD VDD PWE0 HA17 HA23 HA25 HA27 HA24
HA31 VDDH VDD GPIO21 GPIO24 CS4 TT4 VDD HTA DBB AACK ARTRY BM1 VDD PGTA PSD
CAS TEST HA19 VDD HA28 HA20
J A30 GPIO25 GND GPIO23 BCTL1 PSDA10 TT3 VDD GND VDD DBG BM2 CLKIN VDD BADDR
27 PSDA
MUX GND HA13 VDD HA26 HA18
KA28 A29 A26 GND CS2 ALE TT2 VDD CLKOUT GND GND GND GND Res. BADDR
30 POE PWE1 PWE3 HA16 HA21 HA15
LA22 A25 A27VDDH CS3 GND GND VDDH GND GND GND BADDR
29 BADDR
28 VDDH VDDH HA11 HA14 HA12
MA21 A24 VDDH GND VDDH VDDH HB
RST VDDH GND GND VDDH VDD GND GND GND VDDH HD31 HD28
N A20 A23 GPIO26 PSDWE CS0 HCS BG HRDS GND GND HBCS HWBS
0VDDH PWE2 HD24 HD29 HD30 HD26
PA19 GNDVDDH DP0 PSD
VAL TEA BR TA GND GND VCCSYN GNDSYN GND HCLKIN HWBS
1HWBS
2HWBS
3HD23 HD25 HD27 HD20
RA16 A18 A17 DP2 TS DP3 DP6 DP7 TT0 VDD VDD VDD GBL TSZ3 TSZ1 HWBS
4HWBS
6HD22 GND VDDH HD18
T A14 A15 GND D30 DP1 DP4 DP5 D23 D21 TT1 D16 VDD TBST TSZ2 TSZ0 HWBS
5HWBS
7HD0 HD1 HD21 HD17
UA13 A12VDDH D31 D28 D26 D25 D22 D19 D17 D15 D14 D11 D9 D8 D6 D3 D2 HD2 HD19 HD16
V A11 A10 A9 A8 D29 D27 D24 GND D20 D18 D13 D12 D10 D7 D5 D4 D1 D0 GND VDDH HD3
WA6 A7 GNDGNDHD32
VDDH HD33 VDDH HD40 GND VDDH HDST0 HDST1 GND VDDH VDDH GND GND HD4 HD5 HD6
YA5 A4VDDH HD34 HD37 GND VDDH GND HD43 VDDH GND HD51 VDDH GND HD58 HD60 VDD HD9 VDDH HD15 HD7
AA A3 A2 A0 HD35 HD38 HD42 GND HD46 VDDH GND VDDH HD52 HD54 VDDH GND HD59 HD63 HD10 HD12 HD14 VDD
AB VDD A1 HD36 HD39 HD41 HD44 HD45 HD47 HD48 HD49 HD50 HD53 HD55 HD56 HD57 HD61 HD62 HD8 HD11 HD13 GND
Bottom View
MSC8122
Pin Assignments
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 7
1.2 Signal List By Ball Location
Table 1 presents signal list sorted by ball number. -
Table 1. MSC8122 Signal Listing by Ball Designator
Des. Signal Name Des. Signal Name
B3 VDD C18 GPIO1/TIMER0/CHIP_ID1/IRQ5/ETHTXD1
B4 GND C19 GPIO7/TDM3RCLK/IRQ5/ETHTXD3
B5 GND C20 GPIO3/TDM3TSYN/IRQ1/ETHTXD2
B6 NMI_OUT C21 GPIO5/TDM3TDAT/IRQ3/ETHRXD3
B7 GND C22 GPIO6/TDM3RSYN/IRQ4/ETHRXD2
B8 VDD D2 TDI
B9 GND D3 EE0
B10 VDD D4 EE1
B11 GND D5 GND
B12 VDD D6 VDDH
B13 GND D7 HCID2
B14 VDD D8 HCID3/HA8
B15 GND D9 GND
B16 VDD D10 VDD
B17 GND D11 GND
B18 VDD D12 VDD
B19 GPIO0/CHIP_ID0/IRQ4/ETHTXD0 D13 GND
B20 VDD D14 VDD
B21 VDD D15 VDD
B22 GND D16 GPIO31/TIMER3/SCL
C2 GND D17 GPIO29/CHIP_ID3/ETHTX_EN
C3 VDD D18 VDDH
C4 TDO D19 GPIO4/TDM3TCLK/IRQ2/ETHTX_ER
C5 SRESET D20 VDDH
C6 GPIO28/UTXD/DREQ2 D21 GND
C7 HCID1 D22 GPIO8/TDM3RDAT/IRQ6/ETHCOL
C8 GND E2 TCK
C9 VDD E3 TRST
C10 GND E4 TMS
C11 VDD E5 HRESET
C12 GND E6 GPIO27/URXD/DREQ1
C13 VDD E7 HCID0
C14 GND E8 GND
C15 GND E9 VDD
C16 GPIO30/TIMER2/TMCLK/SDA E10 GND
C17 GPIO2/TIMER1/CHIP_ID2/IRQ6 E11 VDD
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Pin Assignments
Freesca le Sem ico nd uctor8
E12 GND G6 HA17
E13 VDD G7 PWE0/PSDDQM0/PBS0
E14 GND G8 VDD
E15 GND G9 VDD
E16 VDD G10 IRQ3/BADDR31
E17 GND G11 BM0/TC0/BNKSEL0
E18 GND G12 ABB/IRQ4
E19 GPIO9/TDM2TSYN/IRQ7/ETHMDIO G13 VDD
E20 GPIO13/TDM2RCLK/IRQ11/ETHMDC G14 IRQ7/INT_OUT
E21 GPIO10/TDM2TCLK/IRQ8/ETHRX_DV/ETHCRS_DV/NC G15 ETHCRS/ETHRXD
E22 GPIO12/TDM2RSYN/IRQ10/ETHRXD1/ETHSYNC G16 VDD
F2 PORESET G17 CS1
F3 RSTCONF G18 BCTL0
F4 NMI G19 GPIO15/TDM1TSYN/DREQ1
F5 HA29 G20 GND
F6 HA22 G21 GPIO17/TDM1TDAT/DACK1
F7 GND G22 GPIO22/TDM0TCLK/DONE2/DRACK2
F8 VDD H2 HA20
F9 VDD H3 HA28
F10 VDD H4 VDD
F11 GND H5 HA19
F12 VDD H6 TEST
F13 GND H7 PSDCAS/PGPL3
F14 VDD H8 PGTA/PUPMWAIT/PGPL4/PPBS
F15 ETHRX_CLK/ETHSYNC_IN H9 VDD
F16 ETHTX_CLK/ETHREF_CLK/ETHCLOCK H10 BM1/TC1/BNKSEL1
F17 GPIO20/TDM1RDAT H11 ARTRY
F18 GPIO18/TDM1RSYN/DREQ2 H12 AACK
F19 GPIO16/TDM1TCLK/DONE1/DRACK1 H13 DBB/IRQ5
F20 GPIO11/TDM2TDAT/IRQ9/ETHRX_ER/ETHTXD H14 HTA
F21 GPIO14/TDM2RDAT/IRQ12/ETHRXD0/NC H15 VDD
F22 GPIO19/TDM1RCLK/DACK2 H16 TT4/CS7
G2 HA24 H17 CS4
G3 HA27 H18 GPIO24/TDM0RSYN/IRQ14
G4 HA25 H19 GPIO21/TDM0TSYN
G5 HA23 H20 VDD
Table 1. MSC8122 Signal Listing by Ball Designator (continued)
Des. Signal Name Des. Signal Name
Pin Assignments
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 9
H21 VDDH K15 VDD
H22 A31 K16 TT2/CS5
J2 HA18 K17 ALE
J3 HA26 K18 CS2
J4 VDD K19 GND
J5 HA13 K20 A26
J6 GND K21 A29
J7 PSDAMUX/PGPL5 K22 A28
J8 BADDR27 L2 HA12
J9 VDD L3 HA14
J10 CLKIN L4 HA11
J11 BM2/TC2/BNKSEL2 L5 VDDH
J12 DBG L6 VDDH
J13 VDD L7 BADDR28
J14 GND L8 IRQ5/BADDR29
J15 VDD L9 GND
J16 TT3/CS6 L10 GND
J17 PSDA10/PGPL0 L14 GND
J18 BCTL1/CS5 L15 VDDH
J19 GPIO23/TDM0TDAT/IRQ13 L16 GND
J20 GND L17 GND
J21 GPIO25/TDM0RCLK/IRQ15 L18 CS3
J22 A30 L19 VDDH
K2 HA15 L20 A27
K3 HA21 L21 A25
K4 HA16 L22 A22
K5 PWE3/PSDDQM3/PBS3 M2 HD28
K6 PWE1/PSDDQM1/PBS1 M3 HD31
K7 POE/PSDRAS/PGPL2 M4 VDDH
K8 IRQ2/BADDR30 M5 GND
K9 Reserved M6 GND
K10 GND M7 GND
K11 GND M8 VDD
K12 GND M9 VDDH
K13 GND M10 GND
K14 CLKOUT M14 GND
Table 1. MSC8122 Signal Listing by Ball Designator (continued)
Des. Signal Name Des. Signal Name
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Pin Assignments
Freesca le Sem ico nd uctor10
M15 VDDH P12 VCCSYN
M16 HBRST P13 GND
M17 VDDH P14 GND
M18 VDDH P15 TA
M19 GND P16 BR
M20 VDDH P17 TEA
M21 A24 P18 PSDVAL
M22 A21 P19 DP0/DREQ1/EXT_BR2
N2 HD26 P20 VDDH
N3 HD30 P21 GND
N4 HD29 P22 A19
N5 HD24 R2 HD18
N6 PWE2/PSDDQM2/PBS2 R3 VDDH
N7 VDDH R4 GND
N8 HWBS0/HDBS0/HWBE0/HDBE0 R5 HD22
N9 HBCS R6 HWBS6/HDBS6/HWBE6/HDBE6/PWE6/PSDDQM6/PBS6
N10 GND R7 HWBS4/HDBS4/HWBE4/HDBE4/PWE4/PSDDQM4/PBS4
N14 GND R8 TSZ1
N15 HRDS/HRW/HRDE R9 TSZ3
N16 BG R10 IRQ1/GBL
N17 HCS R11 VDD
N18 CS0 R12 VDD
N19 PSDWE/PGPL1 R13 VDD
N20 GPIO26/TDM0RDAT R14 TT0/HA7
N21 A23 R15 IRQ7/DP7/DREQ4
N22 A20 R16 IRQ6/DP6/DREQ3
P2 HD20 R17 IRQ3/DP3/DREQ2/EXT_BR3
P3 HD27 R18 TS
P4 HD25 R19 IRQ2/DP2/DACK2/EXT_DBG2
P5 HD23 R20 A17
P6 HWBS3/HDBS3/HWBE3/HDBE3 R21 A18
P7 HWBS2/HDBS2/HWBE2/HDBE2 R22 A16
P8 HWBS1/HDBS1/HWBE1/HDBE1 T2 HD17
P9 HCLKIN T3 HD21
P10 GND T4 HD1/DSISYNC
P11 GNDSYN T5 HD0/SWTE
Table 1. MSC8122 Signal Listing by Ball Designator (continued)
Des. Signal Name Des. Signal Name
Pin Assignments
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 11
T6 HWBS7/HDBS7/HWBE7/HDBE7/PWE7/PSDDQM7/PBS7 U21 A12
T7 HWBS5/HDBS5/HWBE5/HDBE5/PWE5/PSDDQM5/PBS5 U22 A13
T8 TSZ0 V2 HD3/MODCK1
T9 TSZ2 V3 VDDH
T10 TBST V4 GND
T11 VDD V5 D0
T12 D16 V6 D1
T13 TT1 V7 D4
T14 D21 V8 D5
T15 D23 V9 D7
T16 IRQ5/DP5/DACK4/EXT_BG3 V10 D10
T17 IRQ4/DP4/DACK3/EXT_DBG3 V11 D12
T18 IRQ1/DP1/DACK1/EXT_BG2 V12 D13
T19 D30 V13 D18
T20 GND V14 D20
T21 A15 V15 GND
T22 A14 V16 D24
U2 HD16 V17 D27
U3 HD19 V18 D29
U4 HD2/DSI64 V19 A8
U5 D2 V20 A9
U6 D3 V21 A10
U7 D6 V22 A11
U8 D8 W2 HD6
U9 D9 W3 HD5/CNFGS
U10 D11 W4 HD4/MODCK2
U11 D14 W5 GND
U12 D15 W6 GND
U13 D17 W7 VDDH
U14 D19 W8 VDDH
U15 D22 W9 GND
U16 D25 W10 HDST1/HA10
U17 D26 W11 HDST0/HA9
U18 D28 W12 VDDH
U19 D31 W13 GND
U20 VDDH W14 HD40/D40/ETHRXD0
Table 1. MSC8122 Signal Listing by Ball Designator (continued)
Des. Signal Name Des. Signal Name