MX29F1610ARC-10 - Macronix International Co., Ltd.

GENERAL DESCRIPTION

The MX29F1610A is a 16-mega bit Flash memory

organized as either 1M wordx16 or 2M bytex8. The

MX29F1610A includes 16-128KB(131,072) blocks or 16-

64KW(65,536) blocks. MXIC's Flash memories offer the

most cost-effective and reliable read/write non-volatile

random access memory. The MX29F1610A is packaged

in 48-pin TSOP or 44-pin SOP. For 48-pin TSOP, CE2 and

RY/BY are extra pins compared with 44-pin SOP package.

This is to optimize the products (such as solid-state disk

drives or flash memory cards) control pin budget. All the

above three pins(CE2,RY/BY and PWD) plus one extra

VCC pin are not provided in 44-pin SOP. It is designed to

be reprogrammed and erased in-system or in-standard

EPROM programmers.

The standard MX29F1610A offers access times as fast as

90ns,allowing operation of high-speed microprocessors

without wait. To eliminate bus contention, the

MX29F1610A has separate chip enables(CE1 and CE2),

output enable (OE), and write enable (WE) controls.

MXIC's Flash memories augment EPROM functionality

with in-circuit electrical erasure and programming. The

MX29F1610A uses a command register to manage this

FEATURES

• 5V ± 10% write and erase

• JEDEC-standard EEPROM commands

• Endurance:100,000 cycles

• Fast access time: 90/100/120ns

• Sector erase architecture

- 16 equal sectors of 128k bytes each

- Sector erase time: 1.3 s typical

• Auto Erase and Auto Program Algorithms

- Automatically erases any one of the sectors

or the whole chip with Erase Suspend capability

- Automatically programs and verifies data at

specified addresses

• Status Register feature for detection of

program or erase cycle completion

• Low VCC write inhibit is equal to or less than 3.2V

• Software and hardware data protection

P/N: PM0506 REV.1.7,JUN. 15, 2001

• Page program operation

- Internal address and data latches for

128 bytes/64 words per page

- Page programming time: 0.9ms typical

- Byte programming time: 7us in average

• Low power dissipation

- 30mA typical active current

- 1uA typical standby current

• CMOS and TTL compatible inputs and outputs

• Sector Protection

- Hardware method that can protect any combination

of sectors from write or erase operations.

• Deep Power-Down Input

- 1uA ICC typical

• Industry standard surface mount packaging

- 48 lead TSOP, TYPE I

- 44 lead SOP

functionality. The command register allows for 100% TTL

level control inputs and fixed power supply levels during

erase and programming, while maintaining maximum

EPROM compatibility.

To allow for simple in-system reprogrammability, the

MX29F1610A does not require high input voltages for

programming. Five-volt-only commands determine the

operation of the device. Reading data out of the device

is similar to reading from an EPROM.

MXIC Flash technology reliably stores memory contents

even after 100,000 cycles. The MXIC's cell is designed

to optimize the erase and programming mechanisms. In

addition, the combination of advanced tunnel oxide

processing and low internal electric fields for erase and

programming operations produces reliable cycling. The

MX29F1610A uses a 5V ± 10% VCC supply to perform the

Auto Erase and Auto Program algorithms.

The highest degree of latch-up protection is achieved

with MXIC's proprietary non-epi process. Latch-up

protection is proved for stresses up to 100 milliamps on

address and data pin from -1V to VCC +1V.

PRELIMINARY

MX29F1610A

16M-BIT [2M x8/1M x16] CMOS

SINGLE VOLTAGE FLASH EEPROM

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

PIN CONFIGURATIONS

48 TSOP(TYPE I) (12mm x 20mm)

(NORMAL TYPE) (REVERSE TYPE)

44 SOP(500mil)

SYMBOL PIN NAME

A0 - A19 Address Input

Q0 - Q14 Data Input/Output

Q15/A - 1 Q15(Word mode)/LSB addr.(Byte mode)

CE1/CE2 Chip Enable Input

PWD Deep Power- Down Input

OE Output Enable Input

WE Write Enable Input

RY/BY Ready/Busy Output

WP Sector Write Protect Input

BYTE Word/Byte Selection Input

VCC Power Supply

GND Ground Pin

PIN DESCRIPTION

A18

A17

CE1

GND

Q10

Q11

A19

A10

A11

A12

A13

A14

A15

A16

BYTE

GND

Q15/A-1

Q14

Q13

Q12

VCC

MX29F1610A

RY/BY

A16

A15

A14

A13

A12

A11

A10

A19

A18

A17

VCC

PWD

BYTE

GND

Q15/A-1

Q14

Q13

Q12

VCC

Q11

Q10

GND

CE1

CE2

MX29F1610A

RY/BY

A16

A15

A14

A13

A12

A11

A10

A19

A18

A17

VCC

PWD

BYTE

GND

Q15/A-1

Q14

Q13

Q12

VCC

Q11

Q10

GND

CE1

CE2

MX29F1610A

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

BLOCK DIAGRAM

CONTROL

INPUT

LOGIC

PROGRAM/ERASE

HIGH V OLTAGE

RY/BY

COMMAND INTERFACE

(CIR)

MX29F1610A

FLASH

ARRAY

X-DECODER

ADDRESS

LATCH

AND

BUFFER Y-PASS GATE

Y-DECODER

ARRAY

SOURCE

HV COMMAND

DATA

DECODER

COMMAND

DATA LATCH

I/O BUFFER

PGM

DATA

PROGRAM

DATA LATCH

SENSE

AMPLIFIER

Q0-Q15/A-1

Q15/A-1

A0-A19

CE1/CE2

PWD

BYTE

PAGE

WRITE

STATE

MACHINE

(WSM)

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

SYMBOL TYPE NAME AND FUNCTION

A0 - A19 INPUT ADDRESS INPUTS: for memory addresses. Addresses are internally latched

during a write cycle.

Q0 - Q7 INPUT/OUTPUT LOW-BYTE DATA BUS: Input data and commands during Command Interface

appropriate read mode. Floated when the chip is de-selected or the outputs are

disabled.

Q8 - Q14 INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x 16 Data-Write operations. Outputs

array, identifier data in the appropriate read mode; not used for status register

reads. Floated when the chip is de-selected or the outputs are disabled

.Q15/A -1 INPUT/OUTPUT Selects between high-byte data INPUT/OUTPUT(BYTE = HIGH) and LSB

ADDRESS(BYTE = LOW)

CE1/CE2 INPUT CHIP ENABLE INPUTS: Activate the device's control logic, Input buffers,

decoders and sense amplifiers. With either CE1 or CE2 high, the device is de-

selected and power consumption reduces to Standby level upon completion of

any current program or erase operations. Both CE1,CE2 must be low to

select the device. CE2 is not provided in 44-pin SOP package.

All timing specifications are the same for both signals. Device selection occurs

with the latter falling edge of CE1 or CE2. The first rising edge of CE1 or CE2

disables the device.

PWD INPUT POWER-DOWN: Puts the device in deep power-down mode. PWD is active low;

PWD high gates normal operation. PWD also locks out erase or program

operation when active low providing data protection during power transitions.

OE INPUT OUTPUT ENABLES: Gates the device's data through the output buffers during

a read cycle OE is active low.

WE INPUT WRITE ENABLE: Controls writes to the Command Interface Register(CIR).

WE is active low.

RY/BY OPEN DRAIN READY/BUSY: Indicates the status of the internal Write State Machine(WSM).

OUTPUT When low it indicates that the WSM is performing a erase or program operation.

RY/BY high indicate that the WSM is ready for new commands, sector erase is

suspended or the device is in deep power-down mode. RY/BY is always active

and does not float to tristate off when the chip is deselected or data output are

disabled.

WP INPUT WRITE PROTECT: All sectors can be protected by writing a non-volatile protect-

bit for each sector. When WP is low, all prottect-bits status can not be changed,

i.e., the user can not execute Sector Protection and Sector Unprotect. The WP

input buffer is disabled when PWD transitions low(deep power-down mode).

BYTE INPUT BYTE ENABLE: BYTE Low places device in x8 mode. All data is then input or

output on Q0-7 and Q8-14 float. AddressQ15/A-1 selects between the high

and low byte. BYTE high places the device in x16 mode, and turns off the Q15/

A-1 input buffer. Address A0, then becomes the lowest order address.

VCC DEVICE POWER SUPPLY(5V±10%)

GND GROUND

Table1.PIN DESCRIPTIONS

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

BUS OPERATION

Flash memory reads, erases and writes in-system via the local CPU . All bus cycles to or from the flash memory conform

to standard microprocessor bus cycles.

Table 2.1 Bus Operations for Word-Wide Mode (BYTE = VIH)

NOTES :

1.X can be VIH or VIL for address or control pins except for RY/BY which is either VOL or VOH.

2.RY/BY output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode, RY/BY will be at VOH

if it is tied to VCC through a 1K ~ 100K resistor. When the RY/BY at VOH is independent of OE while a WSM operation is in progress.

3.PWD at GND ± 0.2V ensures the lowest deep power-down current.

4. A0 and A1 at VIL provide manufacturer ID codes. A0 at VIH and A1 at VIL provide device ID codes. A0 at VIL, A1 at VIH and with appropriate

sector addresses provide Sector Protect Code.(Refer to Table 4)

5. Commands for different Erase operations, Data program operations or Sector Protect operations can only be successfully completed through

proper command sequence.

6.While the WSM is running. RY/BY in Level-Mode stays at VOL until all operations are complete. RY/BY goes to VOH when the WSM is not

busy or in erase suspend mode.

7. RY/BY may be at VOL while the WSM is busy performing various operations. For example, a status register read during a write operation.

8. VID = 11.5V- 12.5V.

9. Q15/A-1 = VIL, Q0 - Q7 =D0-D7 out . Q15/A-1 = VIH, Q0 - Q7 = D8 -D15 out.

Table2.2 Bus Operations for Byte-Wide Mode (BYTE = VIL)

Mode Notes PWD CE1 CE2 OE WE A0 A1 A9 Q0-Q7 Q8-Q14 Q15/A-1 RY/BY

Read 1,2,7,9 VIH VIL VIL VIL VIH X X X DOUT HighZ VIL/VIH X

Output Disable 1,6,7 VIH VIL VIL VIH VIH X X X High Z HIghZ X X

Standby 1,6,7 VIH VIL VIH X X X X X High Z HighZ X X

VIH VIL

VIH VIH

Deep Power-Down 1,3 VIL X X X X X X X High Z HIghZ X VOH

Manufacturer ID 4,8 VIH VIL VIL VIL VIH VIL VIL VID C2H High Z VIL VOH

Device ID 4,8 VIH VIL VIL VIL VIH VIH VIL VID FAH/FBH High Z VIL VOH

MX29F1610A

Write 1,5,6 VIH VIL VIL VIH VIL X X X DIN HIghZ VIL/VIH X

Mode Notes PWD CE1 CE2 OE WE A0 A1 A9 Q0-Q7 Q8-Q14 Q15/A-1 RY/BY

Read 1,2,7 VIH VIL VIL VIL VIH X X X DOUT DOUT DOUT X

Output Disable 1,6,7 VIH VIL VIL VIH VIH X X X High Z High Z HighZ X

Standby 1,6,7 VIH VIL VIH X X X X X High Z HIgh Z HighZ X

VIH VIL

VIH VIH

Deep Power-Down 1,3 VIL X X X X X X X High Z High Z HighZ VOH

Manufacturer ID 4,8 VIH VIL VIL VIL VIH VIL VIL VID C2H 00H 0B VOH

Device ID 4,8 VIH VIL VIL VIL VIH VIH VIL VID FAH/FBH 00H 0B VOH

MX29F1610A

Write 1,5,6 VIH VIL VIL VIH VIL X X X DIN DIN DIN X

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

WRITE OPERATIONS

Commands are written to the COMMAND INTERFACE

timings. The CIR serves as the interface between the

microprocessor and the internal chip operation. The CIR

can decipher Read Array, Read Silicon ID, Erase and

Program command. In the event of a read command, the

CIR simply points the read path at either the array or the

silicon ID, depending on the specific read command

given. For a program or erase cycle, the CIR informs the

write state machine that a program or erase has been

requested. During a program cycle, the write state

machine will control the program sequences and the CIR

will only respond to status reads. During a sector/chip

erase cycle, the CIR will respond to status reads and

erase suspend. After the write state machine has

completed its task, it will allow the CIR to respond to its full

command set. The CIR stays at read status register

mode until the microprocessor issues another valid

command sequence.

Device operations are selected by writing commands into

the CIR. Table 3 below defines 16 Mbit flash family

command.

TABLE 3. COMMAND DEFINITIONS

Command Read/ Silicon Page/Byte Chip Sector Erase Erase Read Clear

Sequence Reset ID Read Program Erase Erase Suspend Resume Status Reg. Status Reg.

Bus Write 4 4 4 6 6 1 1 4 3

Cycles Req'd

First Bus Addr 5555H 5555H 5555H 5555H 5555H XXXX XXXX 5555H 5555H

Write Cycle Data AAH AAH AAH AAH AAH B0H D0H AAH AAH

Second Bus Addr 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH

Write Cycle Data 55H 55H 55H 55H 55H 55H 55H

Third Bus Addr 5555H 5555H 5555H 5555H 5555H 5555H 5555H

Write Cycle Data F0H 90H A0H 80H 80H 70H 50H

Fourth Bus Addr RA 00H/01H PA 5555H 5555H X

Read/Write Cycle Data RD C2H/FAH PD AAH AAH SRD

(FBH)

Fifth Bus Addr 2AAAH 2AAAH

Write Cycle Data 55H 55H

Sixth Bus Addr 5555H SA

Write Cycle Data 10H 30H

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

Command Sector Sector Verify Sector

Sequence Protection Unprotect Protect

Bus Write 6 6 4

Cycles Req'd

First Bus Addr 5555H 5555H 5555H

Write Cycle Data AAH AAH AAH

Second Bus Addr 2AAAH 2AAAH 2AAAH

Write Cycle Data 55H 55H 55H

Third Bus Addr 5555H 5555H 5555H

Write Cycle Data 60H 60H 90H

Fourth Bus Addr 5555H 5555H *

Read/Write Cycle Data AAH AAH C2H*

Fifth Bus Addr 2AAAH 2AAAH

Write Cycle Data 55H 55H

Sixth Bus Addr SA** SA**

Write Cycle Data 20H 40H

Notes:

1. Address bit A15 -- A19 = X = Don't care for all address commands except for Program Address(PA) and Sector

Address(SA).

5555H and 2AAAH address command codes stand for Hex number starting from A0 to A14.

2. Bus operations are defined in Table 2.

3. RA = Address of the memory location to be read.

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.

SA = Address of the sector to be erased. The combination of A16 -- A19 will uniquely select any sector.

4. RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.

SRD = Data read from status register.

5. Only Q0-Q7 command data is taken, Q8-Q15 = Don't care.

* Refer to Table 4, Figure 12.

6. The details of sector protection/unprotect algorithm are shown in Fig.10 and Fig.11.

COMMAND DEFINITIONS(continue Table 3.)

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

DEVICE OPERATION

SILICON ID READ

The Silicon ID Read mode allows the reading out of a binary

code from the device and will identify its manufacturer and

type. This mode is intended for use by programming

equipment for the purpose of automatically matching the

device to be programmed with its corresponding

programming algorithm. This mode is functional over the

entire temperature range of the device.

To activate this mode, the programming equipment must

force VID (11.5V~12.5V) on address pin A9. Two

identifier bytes may then be sequenced from the device

outputs by toggling address A0 from VIL to VIH. All

addresses are don't cares except A0 and A1.

The manufacturer and device codes may also be read via

the command register, for instances when the

MX29F1610A is erased or programmed in a system

without access to high voltage on the A9 pin. The

command sequence is illustrated in Table 3.

Byte 0 (A0=VIL) represents the manfacturer's code

(MXIC=C2H) and byte 1 (A0=VIH) the device identifier

code (MX29F1610A=FAH).

The Silicon ID Read mode will be terminated after the

following write command cycle.

Table 4. MX29F1610 Silion ID Codes and Verify Sector Protect Code

Type A19 A18 A17 A16 A1A0Code(HEX) DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ0

Manufacturer Code X X X X VIL VIL C2H* 1 1 0 0 0 0 1 0

MX29F1610A Device Code X X X X VIL VIH FAH 1 1 1 1 1 0 1 0/1

Verify Sector Protect Sector Address*** VIH VIL C2H** 1 1 0 0 0 0 1 0

* MX29F1610A Manufacturer Code = C2H, Device Code = FAH when BYTE = VIL

MX29F1610A Manufacturer Code = 00C2H, Device Code = 00FAH when BYTE = VIH

** Outputs C2H at protected sector address, 00H at unprotected scetor address.

***All sectors have protect-bit feature. Sector address = (A19, A18,A17,A16)

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

Any page to be programmed should have the page in the

erased state first, i.e. performing sector erase is

suggested before page programming can be performed.

The device is programmed on a page basis. If a

byte(word) of data within a page is to be changed, data for

the entire page can be loaded into the device. Any

byte(word) that is not loaded during the programming of

its page will be still in the erased state (i.e. FFH). Once

the bytes of a page are loaded into the device, they are

simultaneously programmed during the internal

programming period. After the first data byte(word) has

been loaded into the device, successive bytes(words)

are entered in the same manner. The time between byte

(word) loads must be less than 30us otherwise the load

period could be teminated. A6 to A19 specify the page

address, i.e., the device is page-aligned on 128 bytes(64

words)boundary. The page address must be valid during

each high to low transition of WE or CE. A-1 to A5 specify

the byte address within the page, A0 to A5 specify the

word address withih the page. The byte(word) may be

loaded in any order; sequential loading is not required. If

a high to low transition of CE or WE is not detected whithin

100us of the last low to high transition, the load period will

end and the internal programming period will start. The

Auto page program terminates when status on DQ7 is '1'

at which time the device stays at read status register

mode until the CIR contents are altered by a valid

command sequence.(Refer to table 3,6 and Figure 1,7,8)

The read or reset operation is initiated by writing the read/

reset command sequence into the command register.

Microprocessor read cycles retrieve array data from the

memory. The device remains enabled for reads until the

CIR contents are altered by a valid command sequence.

The device will automatically power-up in the read/reset

state. In this case, a command sequence is not required

to read data. Standard microprocessor read cycles will

retrieve array data. This default value ensures that no

spurious alteration of the memory content occurs during

the power transition. Refer to the AC Read

Characteristics and Waveforms for the specific timing

parameters.

The MX29F1610A is accessed like an EPROM. When CE

and OE are low and WE is high the data stored at the

memory location determined by the address pins is

asserted on the outputs. The outputs are put in the high

impedance state whenever CE or OE is high. This dual

line control gives designers flexibility in preventing bus

contention.

CE stands for the combination of CE1 and CE2 in

MX29F1610A 48-pin TSOP package. CE and stands for

CE in 44-pin SOP package.

Note that the read/reset command is not valid when

program or erase is in progress.

READ/RESET COMMAND BYTE-WIDE LOAD/WORD-WIDE LOAD

PROGRAM

PAGE PROGRAM

To initiate Page program mode, a three-cycle command

sequence is required. There are two " unlock" write

cycles. These are followed by writing the page program

command-A0H.

Any attempt to write to the device without the three-cycle

command sequence will not start the internal Write State

Machine(WSM), no data will be written to the device.

After three-cycle command sequence is given, a

byte(word) load is performed by applying a low pulse on

the WE or CE input with CE or WE low (respectively) and

OE high. The address is latched on the falling edge of CE

or WE, whichever occurs last. The data is latched by the

first rising edge of CE or WE. Maximum of 128 bytes of

data may be loaded into each page by the same

procedure as outlined in the page program section below.

Byte(word) loads are used to enter the 128 bytes(64

words) of a page to be programmed or the software codes

for data protection. A byte load(word load) is performed

by applying a low pulse on the WE or CE input with CE or

WE low (respectively) and OE high. The address is

latched on the falling edge of CE or WE, whichever occurs

last. The data is latched by the first rising edge of CE or

WE.

Either byte-wide load or word-wide load is

determined(Byte = VIL or VIH is latched) on the falling

edge of the WE(or CE) during the 3rd command write

cycle.

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

CHIP ERASE

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

"set-up" command-80H. Two more "unlock" write cycles

are then followed by the chip erase command-10H.

Chip erase does not require the user to program the

device prior to erase.

The automatic erase begins on the rising edge of the last

WE pulse in the command sequence and terminates

when the status on DQ7 is "1" at which time the device

stays at read status register mode. The device remains

enabled for read status register mode until the CIR

contents are altered by a valid command

sequence.(Refer to table 3,6 and Figure 2,7,9)

A19 A18 A17 A16 Address Range[A19, -1]

SA0 0 0 0 0 000000H--01FFFFH

SA1 0 0 0 1 020000H--03FFFFH

SA2 0 0 1 0 040000H--05FFFFH

SA3 0 0 1 1 060000H--07FFFFH

SA4 0 1 0 0 080000H--09FFFFH

... .... ... ... ................

SA15 1 1 1 1 1E0000H--1FFFFFH

Table 5. MX29F1610 Sector Address Table

(Byte-Wide Mode)

SECTOR ERASE

Sector erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

set-up command-80H. Two more "unlock" write cycles

are then followed by the sector erase command-30H.

The sector address is latched on the falling edge of WE,

while the command (data) is latched on the rising edge of

WE.

Sector erase does not require the user to program the

device prior to erase. The system is not required to

provide any controls or timings during these operations.

The automatic sector erase begins on the rising edge of

the last WE pulse in the command sequence and

terminates when the status on DQ7 is "1" at which time

the device stays at read status register mode. The device

remains enabled for read status register mode until the

CIR contents are altered by a valid command

sequence.(Refer to table 3,6 and Figure 3,4,7,9))

ERASE SUSPEND

This command only has meaning while the the WSM is

executing SECTOR erase operation, and therefore will

only be responded to during SECTOR erase operation.

After this command has been executed, the CIR will

initiate the WSM to suspend erase operations, and then

return to Read Status Register mode. The WSM will set

the DQ6 bit to a "1". Once the WSM has reached the

Suspend state,the WSM will set the DQ7 bit to a "1", At

this time, WSM allows the CIR to respond to the Read

Array, Read Status Register and Erase Resume

commands only. In this mode, the CIR will not resopnd to

any other comands. The WSM will continue to run, idling

in the SUSPEND state, regardless of the state of all input

control pins, with the exclusion of PWD. PWD low will

immediately shut down the WSM and the remainder of the

chip.

ERASE RESUME

This command will cause the CIR to clear the suspend

state and set the DQ6 to a '0', but only if an Erase Suspend

command was previously issued. Erase Resume will not

have any effect in all other conditions.

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

CLEAR STATUS REGISTER

The Eraes fail status bit (DQ5) and Program fail status bit

(DQ4) are set by the write state machine, and can only be

reset by the system software. These bits can indicate

various failure conditions(see Table 6). By allowing the

system software to control the resetting of these bits,

several operations may be performed (such as

cumulatively programming several pages or erasing

multiple blocks in squence). The status register may then

be read to determine if an error occurred during that

programming or erasure series. This adds flexibility to the

way the device may be programmed or erased.

Additionally, once the program(erase) fail bit happens,

the program (erase) operation can not be performed

further. The program(erase) fail bit must be reset by

system software before further page program or sector

(chip) erase are attempted. To clear the status register,

the Clear Status Register command is written to the CIR.

Then, any other command may be issued to the CIR.

Note again that before a read cycle can be initiated, a

Read command must be written to the CIR to specify

whether the read data is to come from the Array, Status

READ STATUS REGISTER

The MXIC's16 Mbit flash family contains a status register

which may be read to determine when a program or erase

operation is complete, and whether that operation

completed successfully. The status register may be read

at any time by writing the Read Status command to the

CIR. After writing this command, all subsequent read

operations output data from the status register until

another valid command sequence is written to the CIR.

A Read Array command must be written to the CIR to

return to the Read Array mode.

The status register bits are output on DQ2 - DQ7(table 6)

whether the device is in the byte-wide (x8) or word-wide

(x16) mode for the MX29F1610A. In the word-wide mode

the upper byte, DQ(8:15) is set to 00H during a Read

Status command. In the byte-wide mode, DQ(8:14) are

tri-stated and DQ15/A-1 retains the low order address

function. DQ0-DQ1 is set to 0H in either x8 or x16 mode.

It should be noted that the contents of the status register

are latched on the falling edge of OE or CE whichever

occurs last in the read cycle. This prevents possible bus

errors which might occur if the contents of the status

OE must be toggled with each subsequent status read, or

the completion of a program or erase operation will not be

evident.

The Status Register is the interface between the

microprocessor and the Write State Machine (WSM).

When the WSM is active, this register will indicate the

status of the WSM, and will also hold the bits indicating

whether or not the WSM was successful in performing the

desired operation. The WSM sets status bits four through

seven and clears bits six and seven, but cannot clear

status bits four and five. If Erase fail or Program fail status

bit is detected, the Status Register is not cleared until the

Clear Status Register command is written. The

MX29F1610A automatically outputs Status Register data

when read after Chip Erase, Sector Erase, Page Program

or Read Status Command write cycle. The internal state

machine is set for reading array data upon device power-

up, or after deep power-down mode.

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

STATUS NOTES DQ7 DQ6 DQ5 DQ4 DQ3

IN PROGRESS PROGRAM 1,2 0 0 0 0 0

ERASE 1,3 0 0 0 0 0

SUSPEND (NOT COMPLETE) 1,4 0 0 0 0 0

(COMPLETE) 1 1 0 0 0

COMPLETE PROGRAM 1,2 1 0 0 0 0

ERASE 1,3 1 0 0 0 0

FAIL PROGRAM 1,5 1 0 0 1 0

ERASE 1,5 1 0 1 0 0

AFTER CLEARING STATUS REGISTER 1000 0

TABLE 6. MX29F1610 STATUS REGISTER

NOTES:

1. DQ7 : WRITE STATE MACHINE STATUS

1 = READY, 0 = BUSY

DQ6 : ERASE SUSPEND STATUS

1 = SUSPEND, 0 = NO SUSPEND

DQ5 : ERASE FAIL STATUS

1 = FAIL IN ERASE, 0 = SUCCESSFUL ERASE

DQ4 : PROGRAM FAIL STATUS

1 = FAIL IN PROGRAM, 0 = SUCCESSFUL PROGRAM

DQ3=0 = RESERVED FOR FUTURE ENHANCEMENTS.

These bits are reserved for future use ; mask them out when polling the Status Register.

2. PROGRAM STATUS is for the status during Page Programming or Sector Unprotect mode.

3. ERASE STATUS is for the status during Sector/Chip Erase or Sector Protection mode.

4. SUSPEND STATUS is for Sector Erase mode .

5. FAIL STATUS bit(DQ4 or DQ5) is provided during Page Program or Sector/Chip Erase modes respectively.

6. DQ3 = 0 all the time.

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

SECTOR UNPROTECT

It is also possible to unprotect the sector , same as the first

five write command cycles in activating sector protection

mode followed by the Unprotect Sector command - 40H,

the automatic Unprotect operation begins on the rising

edge of the last WE pulse in the command sequence and

terminates when the Status on DQ7 is '1' at which time the

device stays at the read status register mode.(Refer to

table 3,6 and Figure 11,12)

The users have to write Verify Sector Protect command

to verify protect status after executing Sector Unprotect.

The device remains enabled for read status register

mode until the CIR contents are altered by a valid

command sequence.

Either Protect or Unprotect sector mode is accomplished

by keeping WP high, i.e. protect-bit status can only be

changed with a valid command sequence and WP at high.

Protect-bit status will not be changed during chip/sector

erase operations. Only unprotected sectors can be

programmed or erased regardless of the WP pin.

HARDWARE SECTOR PROTECTION

The MX29F1610A features sector protection. This feature

will disable both program and erase operations. The sector

protection feature is enabled using system software by the

user(Refer to table 3). The device is shipped with all

sectors unprotected. Alternatively, MXIC may protect all

sectors in the factory prior to shipping the device.

SECTOR PROTECTION

To activate this mode, a six-bus cycle operation is

required. There are two 'unlock' write cycles. These are

followed by writing the 'set-up' command. Two more

'unlock' write cycles are then followed by the Lock Sector

command - 20H. Sector address is latched on the falling

edge of CE or WE of the sixth cycle of the command

sequence. The automatic Lock operation begins on the

rising edge of the last WE pulse in the command

sequence and terminates when the Status on DQ7 is '1'

at which time the device stays at the read status register

mode.

The users have to write Verify Sector Protect command

to verify protect status after executing Sector Protector.

The device remains enabled for read status register

mode until the CIR contents are altered by a valid

command sequence (Refer to table 3,6 and Figure 10,12

VERIFY SECTOR PROTECT

To verify the Protect status, operation is initiated by

writing Silicon ID read command into the command

address XXX0H retrieves the Manufacturer code of C2H.

A read cycle from XXX1H returns the Device code FAH/

FBH. A read cycle from appropriate address returns

information as to which sectors are protected. To

terminate the operation, it is necessary to write the read/

reset command sequence into the CIR.

(Refer to table 3,4 and Figure 12)

A few retries are required if Protect status can not be

verified successfully after each operation.

DEEP POWER-DOWN MODE

The MXIC's16 Mbit flash family supports a typical ICC of

1uA in deep power-down mode. One of the target markets

for these devices is in protable equipment where the

power consumption of the machine is of prime

importance. When PWD is a logic low (GND ± 0.2V), all

circuits are turned off and the device typically draws 1uA

of ICC current.

During erase or program modes, PWD low will abort

either erase or program operation. The contents of the

memory are no longer valid as the data has been

corrupted by the PWD function.

PWD transitions to VIL or turning power off to the device

will clear the status register.

PWD pin is not provided in 44-pin SOP package.

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

RY/BY PIN AND PROGRAM/ERASE

POLLING

RY/BY is a dedicated, open-drain page program and sector

erase completion. It transitions to VOL after a program or

erase command sequence is written to the MX29F1610A,

and returns to VCC when the WSM has finished executing

the internal algorithm. Since RY/BY is an open-drain

output, several RY/BY pins can be tied together in parallel

with a pull-up resistor to VCC.

RY/BY can be connected to the interrupt input of the

system CPU or controller. It is active at all times, not

tristated if the CE or OE inputs are brought to VIH. RY/

BY is also VCC when the device is in erase suspend or

deep power-down modes.

RY/BY pin is not provided in 44-pin SOP package.

The MX29F1610A is designed to offer protection against

accidental erasure or programming caused by spurious

system level signals that may exist during power

transitions. During power up the device automatically

resets the internal state machine in the Read Array mode.

Also, with its control register architecture, alteration of the

memory contents only occurs after successful

completion of specific multi-bus cycle command

sequences.

The device also incorporates several features to prevent

inadvertent write cycles resulting from VCC power-up

and power-down transitions or system noise.

DATA PROTECTION

LOW VCC WRITE INHIBIT

To avoid initiation of a write cycle during VCC power-up

and power-down, a write cycle is locked out for VCC less

than VLKO(= 3.2V , typically 3.5V). If VCC < VLKO, the

command register is disabled and all internal program/

erase circuits are disabled. Under this condition the

device will reset to the read mode. Subsequent writes will

be ignored until the VCC level is greater than VLKO. It is

the user's responsibility to ensure that the control pins are

logically correct to prevent unintentional write when VCC

is above VLKO.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 10ns (typical) on CE or WE will

not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL,CE =

VIH or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

Figure 1. AUTOMATIC PAGE PROGRAM FLOW CHART

START

Write Data A0H Address 5555H

Write Data 55H Address 2AAAH

Write Data AAH Address 5555H

Loading End?

Page Program Completed

YES

SR7 = 1

Wait 100us

Read Status Register

Write Program Data/Address

SR4 = 0

Program Error

YES

YES To Continue Other Operations,

Do Clear S.R. Mode First

Program

another page?

Operation Done, Device Stays At Read S.R. Mode

Note : S.R. Stands for Status Register

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

Figure 2. AUTOMATIC CHIP ERASE FLOW CHART

START

Write Data 80H Address 5555H

Write Data 55H Address 2AAAH

Write Data AAH Address 5555H

Chip Erase Completed

YES

SR7 = 1

Read Status Register

SR5 = 0

Erase Error

Write Data AAH Address 5555H

Write Data 55H Address 2AAAH

Write Data 10H Address 5555H

Erase Suspend Flow (Figure 4.)

To Execute

Suspend Mode ?

YES

Operation Done,

Device Stays at

Read S.R. Mode

To Continue Other

Operations, Do Clear

S.R. Mode First

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

Figure 3. AUTOMATIC SECTOR ERASE FLOW CHART

START

Write Data 80H Address 5555H

Write Data 55H Address 2AAAH

Write Data AAH Address 5555H

Sector Erase Completed

YES

SR7 = 1

Read Status Register

SR5 = 0

Erase Error

Write Data AAH Address 5555H

Write Data 55H Address 2AAAH

Write Data 30H Sector Address

Erase Suspend Flow (Figure 4.)

To Execute

Suspend Erase ? YES

Operation Done,

Device Stays at

Read S.R. Mode

To Continue Other

Operations, Do Clear

S.R. Mode First

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

Figure 4. ERASE SUSPEND/ERASE RESUME FLOW CHART

START

Write Data B0H Address xxxxH

Erase has completed

YES

SR7 = 1

Read Status Register

SR6 = 1

Erase Error

Write Data AAH Address 5555H

Write Data 55H Address 2AAAH

Write Data F0H Address 5555H

YES

SR5 = 0

Write Data D0H Address xxxxH

YES

Reading End ?

Read Array

Continue Erase

To Continue Other

Operations, Do Clear

S.R. Mode First

Operation Done,

Device Stays at

Read S,R, Mode

Erase Suspend

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

RATING VALUE

Ambient Operating Temperature 0°C to 70°C

Storage Temperature -65°C to 125°C

Applied Input Voltage -0.5V to 7.0V

Applied Output Voltage -0.5V to 7.0V

VCC to Ground Potential -0.5V to 7.0V

A9 -0.5V to 13.5V

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL SPECIFICATIONS

NOTICE:

Stresses greater than those listed under ABSOLUTE

MAXIMUM RATINGS may cause permanent damage to the

device. This is stress rating only and functional operational

sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended period may

affect reliability.

NOTICE:

Specifications contained within the following tables are subject

to change.

CAPACITANCE TA = 25°C, f = 1.0 MHz

SYMBOL PARAMETER MIN. TYP. MAX. UNIT CONDITIONS

CIN1 Input Capacitance 14 pF VIN = 0V

CIN2 Control Pin Input Capacitance 16 pF VIN=0V

COUT Output Capacitance 16 pF VOUT = 0V

SWITCHING TEST WAVEFORMS

SWITCHING TEST CIRCUITS

2.0V

0.8V

2.4V

0.45V

TEST POINTS

INPUT

2.0V

0.8V

OUTPUT

AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".

Input pulse rise and fall times are < 10ns.

DEVICE

UNDER

TEST

DIODES = IN3064

OR EQUIVALENT

CL = 100 pF Including jig capacitance

1.2K ohm

1.6K ohm +5V

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

SYMBOL PARAMETER NOTES MIN. TYP. MAX. UNITS TEST CONDITIONS

IIL Input Load 1 ±10 uA VCC = VCC Max

Current VIN = VCC or GND

ILO Output Leakage 1 ±10 uA VCC = VCC Max

Current VIN = VCC or GND

ISB1 VCC Standby 1 1 100 uA VCC = VCC Max

Current(CMOS) CE1, CE2, PWD = VCC ± 0.2V

ISB2 VCC Standby 2 4 mA VCC = VCC Max

Current(TTL) CE1, CE2, PWD = VIH

IDP VCC Deep 1 1 20 uA PWD = GND ± 0.2V

Power-Down

Current

ICC1 VCC Read 1 50 60 mA VCC = VCC Max

Current CMOS: CE1, CE2 = GND ± 0.2V

BYTE = GND ± 0.2V or VCC ± 0.2V

Inputs = GND ± 0.2V or VCC ± 0.2V

TTL : CE1, CE2 = VIL,

BYTE = VIL or VIH

Inputs = VIL or VIH,

f = 10MHz, IOUT = 0 mA

ICC2 VCC Read 1 30 35 mA VCC = VCC Max,

Current CMOS: CE1, CE2 = GND ± 0.2V

BYTE = VCC ± 0.2V or GND ± 0.2V

Inputs = GND ± 0.2V or VCC ± 0.2V

TTL: CE1, CE2 = VIL,

BYTE = VIH or VIL

Inputs = VIL or VIH,

f = 5MHz, IOUT = 0mA

ICC3 VCC Erase 1,2 5 10 mA CE1, CE2 = VIH

Suspend Current BLock Erase Suspended

ICC4 VCC Program 1 30 50 mA Program in Progress

Current

ICC5 VCC Erase Current 1 30 50 mA Erase in Progress

VIL Input Low Voltage 3 -0.3 0.8 V

VIH Input High Voltage 4 2.4 VCC+0.3 V

VOL Output Low Voltage 0.45 V IOL = 2.1mA

VOH Output High Voltage 2.4 V IOH = -2mA

DC CHARACTERISTICS = 0°C to 70°C, VCC = 5V±10%

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

29F1610A-90 29F1610A-10 29F1610A-12

SYMBOL DESCRIPTIONS MIN. MAX. MIN. MAX. MIN. MAX. UNIT CONDITIONS

tACC Address to Output Delay 9 0 1 0 0 1 2 0 ns CE=OE=VIL

tCE CE to Output Delay 90 100 120 ns OE=VIL

tOE OE to Output Delay 50 55 60 ns CE=VIL

tDF OE High to Output Delay 0 35 0 5 5 0 5 5 n s CE=VIL

tOH Address to Output hold 0 0 0 ns CE=OE=VIL

tBACC BYTE to Output Delay 90 100 120 ns CE= OE=VIL

tBHZ BYTE Low to Output in High Z 50 55 55 ns CE=VIL

tDPR Deep Power-Down Recovery 0 0 0 ns

DC CHARACTERISTICS = 0°C to 70°C, VCC = 5V±10%(CONTINUE P.21)

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, T = 25 °C. These currents are valid for all product

versions (package and speeds).

2. ICC3 is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of ICC3

and ICC1/2.

3. VIL min. = -1.0V for pulse width is equal to or less than 50ns.

VIL min. = -2.0V for pulse width is equal to or less than 20ns.

4. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20ns. If VIH is over the specified maximum value, read operation

cannot be guaranteed.

AC CHARACTERISTICS READ OPERATIONS

TEST CONDITIONS:

• Input pulse levels: 0.45V/2.4V

• Input rise and fall times: 10ns

• Output load: 1TTL gate+100pF(Including scope and jig)

• Reference levels for measuring timing: 0.8V, 2.0V

NOTE:

1. tDF is defined as the time at which the output achieves the

open circuit condition and data is no longer driven.

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

Figure 5. READ TIMING WAVEFORMS

ADDRESSES

tACC

tCE

tDF

tOH

tDPR

tOE

ADDRESSES STABLE

Data out valid

Vcc

5.0V

GND

DATA OUT

CE (1)

PWD

Power-up Standby Device and

address selection Outputs Enabled Data valid Standby Power-down

Vcc

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

HIGH Z HIGH Z

NOTE:

1.CE is defined as the latter of CE1 or CE2 going Low or the first of CE1 or CE2 going High.

VCC

2.For real world application, BYTE pin should be either static high(word mode) or static low(byte mode);

dynamic switching of BYTE pin is not recommended.

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

Figure 6. BYTE TIMING WAVEFORMS

ADDRESSES

tACC

tCE

tDF

tOH

tOE

tDPR

ADDRESSES STABLE

DATAOUT

CE (1)

VIH

VCC

Power-up Standby VCC Power-down

Standby

Device and

address selection

Outputs Enable Data valid

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

HIGH Z HIGH Z

NOTE:

1.CE is defined as the latter of CE1 or CE2 going Low or the first of CE1 or CE2 going High.

2.For real world application, BYTE pin should be either static high(word mode) or static low(byte mode);

dynamic switching of BYTE pin is not recommended.

Data Output

PWD

VCC

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

29F1610A-90 29F1610A-10 29F1610A-12

SYMBOL DESCRIPTION MIN. MAX. MIN. MAX. MIN. MAX. UNIT

tWC Write Cycle Time 9 0 1 00 1 2 0 ns

tAS Address Setup Time 0 0 0 n s

tAH Address Hold Time 50 55 6 0 ns

tDS Data Setup Time 5 0 5 5 6 0 n s

tDH Data Hold Time 0 0 0 ns

tOES Output Enable Setup Time 0 0 0 ns

tCES CE Setup Time 0 0 0 n s

tGHWL Read Recover TimeBefore Write 0 0 0

tCS CE Setup Time 0 0 0 n s

tCH CE Hold Time 0 0 0 n s

tWP Write Pulse Width 5 0 55 6 0 n s

tWPH Write Pulse Width High 3 0 5 0 5 0 n s

tBALC Byte(Word) Address Load Cycle 0.3 3 0 0.3 3 0 0.3 30 us

tBAL Byte(Word) Address Load Time 1 0 0 1 00 1 00 us

tSRA Status Register Access Time 9 0 1 00 1 2 0 ns

tCESR CE Setup before S.R. Read 7 0 7 0 7 0 n s

tWHRL WE High to RY/BY Going Low 90 90 9 0 n s

tWHRLP WE High to RY/BY Going Low 90 90 9 0 u s

(in Page Program mode)

tPHWL PWD High Recovery to WE Going Low 0 0 0 ns

tVCS VCC Setup Time 5 0 5 0 5 0 u s

AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

Figure 7. COMMAND WRITE TIMING WAVEFORMS

tAS

tOES

tDS

tAH

DIN

tDH

tCH

tGHWL

VALID

ADDRESSES

DATA

HIGH Z

(D/Q)

VCC

PWD

tCS

tWPH

tWP

tWC

tVCS

tPHWL

NOTE:

1.BYTE pin is treated as Address pin. All timing specifications for BYTE pin are the same as those for address pin.

2.BYTE pin is sampled on the falling edge of WE or CE during the 3rd command write bus cycle; for real world application,

BYTE pin should be either static high(word mode) or static low(byte mode).

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

Figure 8. AUTOMATIC PAGE PROGRAM TIMING WAVEFORMS

tAS

tDS

tAH

tDH

tBALC

A15~A19

CE(1)

DATA

RY/BY

PWD

tWPH

tWP

tWC

tPHWL

AAH 55H A0H SRD

55H

AAH

2AH

55H

Word offset

Address

Page Address

A6~A14

A0~A5

tBAL

tCES

tSRA

tWHRLP

Write

Data

NOTE:

1.CE is defined as the latter of CE1 or CE2 going low, or the first of CE1 or CE2 going high.

Low/High

Byte Select

A-1

(byte mode only)

2.Please refer to page 9 for detail page program operation.

Last Low/High

Byte Select

Last Word

offset Address

Last Write

Data

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

Figure 9. AUTOMATIC SECTOR/CHIP ERASE TIMING WAVEFORMS

tAS

tDS

tAH

tDH

A16~A19

CE#

DATA

RY/BY

PWD

tWPH

tWP

tWC

tPHWL

AAH 55H 80H SRD

5555H 2AAAH 5555H

SA/*

A15

A0~A14

tCESR

tCES

tSRA

tWHRL

NOTES:

1.CE# is defined as the latter of CE1 or CE2 going low, or the first of CE1 or CE2 going high.

5555H 2AAAH */5555H

AAH 55H 30H/10H

2."*" means "don't care" in this diagram.

3."SA" means "Sector Adddress".

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

Figure 10. SECTOR PROTECTION ALGORITHM

(Only one sector can be protected at one time)

NOTE 1 : Address means A14-A0 for word and byte mode

NOTE 2 : Sector Address=(A19,A18,A17,A16)

START

Verify Sector

Protect/Unprotect Flow

Sector protect Flow

N=1

N=1024?

Pass?

Write RESET Command

Sector Unprotect Complete

and Device Return to Read Mode

Device Failed

YES

N=N+1

YES

NOTE 3 : Sector protection will be disabled when WP is low

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

Verify Sector Protect/Unprotect Flow

Sector Protect Flow

START

Write Command

Address=5555H

Data=AAH

Verify

Another

Sector?

Write Command

Address=2AAAH

Data=55H

Write Command

Address=5555H

Data=90H

Wait 1us

Read Data Ouput

DQ7-DQ0 with

Address=Sector

Address and A1=VIH

Data=C2:Protect

Data=00:Unprotect

YES

END

START

Write Command

Address=5555H

Data=AAH

SR7=1?

Write Command

Address=2AAAH

Data=55H

Write Command

Address=5555H

Data=60H

Write Command

Address=5555H

Data=AAH

Write Command

Address=2AAAH

Data=55H

Write Command

Address=Sector

Address;Data=20H

Read Status

YES

END

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

Figure 11. SECTOR UNPROTECT ALGORITHM

NOTE 1 : Address means A14-A0 for word and byte mode

NOTE 2 : During interation, sector address should be the sectors which have not passed the verify procedure after previous interation

START

Verify Sector

Protect/Unprotect Flow

Sector Unprotect Flow

N=1

N=1024?

Pass?

Write RESET Command

Sector Unprotect Complete

and Device Return to Read Mode

Device Failed

YES

N=N+1

YES

NOTE 3 : The sector(s), which had passed the sector unprotect verification must not enter the sector unprotect flow anymore

NOTE 4 : During loading sector addresses, DATA=BOH means the last sector address loaded to be unprotected

NOTE 5 : Sector Address=(A19, A18, A17, A16)

NOTE 6 : Sector Unprotect will be disabled when WP is low

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

Verify Sector Protect/Unprotect Flow

Sector Unprotect Flow

START

Write Command

Address=5555H

Data=AAH

Verify

Another

Sector?

Write Command

Address=2AAAH

Data=55H

Write Command

Address=5555H

Data=90H

Wait 1us

Read Data Ouput

DQ7-DQ0 with

Address=Sector

Address and A1=VIH

Data=C2:Protect

Data=00:Unprotect

Read Status

YES

END

START

Write Command

Address=5555H

Data=AAH

SR7=1?

Write Command

Address=2AAAH

Data=55H

Write Command

Address=5555H

Data=60H

Write Command

Address=5555H

Data=AAH

Write Command

Address=2AAAH

Data=55H

(NOTE 2)

Write Command

Address=Sector

Address;Data=40H

(NOTE 3)

Load Other Sector

Addresses If

Necessary;Data=40H

(NOTE 4)

Load The Last

Sector Address;

Data=B0H

Read Status

YES

END

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

Figure 12. VERIFY SECTOR PROTECT FLOW CHART

START

Write Data 90H, Address 5555H

Write Data 55H, Address 2AAAH

Write Data AAH, Address 5555H

Ptoect Status Read*

* 1. Protect Status:

Data Outputs C2H as Protected Sector Verified Code.

Data Outputs 00H as Unprotected Sector Verified Code.

2. Sepecified address will be

(A19,A18,A17,A16) = Sector address

(A1, A0)=(1,0) the rest of the address pins are don't care.

3. Silicon ID can be read via this Flow Chart.

Refer to Table 4.

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

Figure 13. COMMAND WRITE TIMING WAVEFORMS(Alternate CE Controlled)

tAS

tOES

tDS

tAH

DIN

tDH

tWH

tGHWL

VALID

ADDRESSES

DATA

HIGH Z

(D/Q)

VCC

PWD

tWS

tCPH

tCP

tWC

tVCS

tPHWL

NOTE:

1.BYTE pin is treated as Address pin. All timing specifications for BYTE pin are the same as those for address pin.

2.BYTE pin is sampled on the falling edge of WE or CE during the 3rd command write bus cycle; for real world application,

BYTE pin should be either static high(word mode) or static low(byte mode).

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

Figure 14. AUTOMATIC PAGE PROGRAM TIMING WAVEFORM(Alternate CE Controlled)

tAS

tDS

tAH

tDH

tBALC

A15~A19

CE(1)

DATA

RY/BY

PWD

tCPH

tCP

tWC

tPHWL

AAH 55H A0H SRD

55H

AAH

2AH

55H

Word offset

Address

Page Address

A6~A14

A0~A5

tBAL

tCES

tSRA

tWHRLP

Write

Data

NOTE:

1.CE is defined as the latter of CE1 or CE2 going low, or the first of CE1 or CE2 going high.

Low/High

Byte Select

A-1

((Byte Mode Only)

2.Please refer to page 9 for detail page program operation.

Last Word

Offset Address

Last Low/High

Byte Select

Last Write

Data

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

MIN. MAX.

Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V

Input Voltage with respect to GND on all I/O pins -1.0V Vcc + 1.0V

Current -100mA +100mA

Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.

LIMITS

PARAMETER MIN. TYP.(1) MAX.(2) UNITS

Sector Erase Time 1 8 s

Chip Erase Time 3 2 256 s

Page Programming Time 0.9 27 ms

Chip Programming Time 14 42 sec

Erase/Program Cycles 100,000 Cycles

Byte Program Time 7 300 us

LATCHUP CHARACTERISTICS

ERASE AND PROGRAMMING PERFORMANCE

Note: 1.All numbers are sampled, not 100% tested.

2.Typical values measured at 25°C,VCC=5.0V.

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

PACKAGE INFORMATION

48-PIN PLASTIC TSOP

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

44-PIN PLASTIC SOP

P/N: PM0506 REV.1.7, JUN. 15, 2001

MX29F1610A

Revision History

Revision# Description Page Date

1. 1 Update ISB1 typical value to 1uA--P20 May/13/1998

Add Control Pin Input Capacitance

1. 2 Change resistance value at switching test circuits P1 9 Nov/10/1998

Change IOH value at DC characteristics P2 0

1.3 Change Pin12 of MX29F1610B TSOP from NC to GND P2 MAR/31/1999

1.4 Remove the 70ns speed grade. P1 MAY/18/1999

Modify Erase and Programming Performance P35

1. 5 Added 100ns to access time P1,21,24 JUN/20/2000

1.6 Cancel the MX29F1610B Type section P1~3,8~14 NOV/16/2000

P21,24

1. 7 To modify "Package Information" P36~37 JUN/15/2001

MX29F1610A

MACRONIX INTERNATIONAL CO., LTD.

HEADQUARTERS:

TEL:+886-3-578-6688

FAX:+886-3-563-2888

EUROPE OFFICE:

TEL:+32-2-456-8020

FAX:+32-2-456-8021

JAPAN OFFICE:

TEL:+81-44-246-9100

FAX:+81-44-246-9105

SINGAPORE OFFICE:

TEL:+65-348-8385

FAX:+65-348-8096

TAIPEI OFFICE:

TEL:+886-2-2509-3300

FAX:+886-2-2509-2200

MACRONIX AMERICA, INC.

TEL:+1-408-453-8088

FAX:+1-408-453-8488

CHICAGO OFFICE:

TEL:+1-847-963-1900

FAX:+1-847-963-1909

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.