AN87C196KR - Intel - Datasheet.Live

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87C196KR/KQ 87C196JV/JT 87C196JR/JQ

ADVANCED 16-BIT CHMOS MICROCONTROLLER

Automotive

Yb40§Ctoa

125§C Ambient

YHigh Performance CHMOS 16-Bit CPU

YUp to 48 Kbytes of On-Chip EPROM

YUp to 1.5 Kbytes of On-Chip Register

RAM

YUp to 512 Bytes of Additional RAM

(Code RAM)

YRegister-Register Architecture

YUp to 8 Channel/10-Bit A/D with

Sample/Hold

YUp to 37 Prioritized Interrupt Sources

YUp to Seven 8-Bit (56) I/O Ports

YFull Duplex Serial I/O Port

YDedicated Baud Rate Generator

YInterprocessor Communication Slave

Port

YHigh Speed Peripheral Transaction

Server (PTS)

YTwo 16-Bit Software Timers

Y10 High Speed Capture/Compare (EPA)

YFull Duplex Synchronous Serial I/O

Port (SSIO)

YTwo Flexible 16-Bit Timer/Counters

YQuadrature Counting Inputs

YFlexible 8-/16-Bit External Bus

YProgrammable Bus (HLD/HLDA)

Y1.75 ms 16 x 16 Multiply

Y3ms 32/16 Divide

Y68-Pin and 52-Pin PLCC Packages

Device Pins/Package EPROM Reg RAM Code RAM I/O EPA SIO SSIO A/D

87C196KR 68-pin PLCC 16K 488 256 56 10 Y Y 8

87C196KQ 68-pin PLCC 12K 360 128 56 10 Y Y 8

87C196JV 52-pin PLCC 48K 1.5K 512 41 6 Y Y 6

87C196JT 52-pin PLCC 32K 1.0K 512 41 6 Y Y 6

87C196JR 52-pin PLCC 16K 488 256 41 6 Y Y 6

87C196JQ 52-pin PLCC 12K 360 128 41 6 Y Y 6

The 87C196KR/KQ JV/JT JR/JQ devices represent the fourth generation of MCSÉ96 Microcontroller prod-

ucts implemented on Intel’s advanced 1 micron process technology. These products are based on the

80C196KB device with improvements for automotive applications. The instruction set is a true super set of

80C196KB. The 87C196JR is a 52-pin version of the 87C196KR device, while the 87C196KQ/JQ are memory

scalars of the 87C196KR/JR.

The 87C196JV/JT A-step devices (JV-A, JT-A) are the newest members of the MCS 96 microcontroller family.

These devices are memory scalars of the 87C196JR D-step (JR-D) and are designed for strict functional and

electrical compatibility. The JT-A has 32 Kbytes of on-chip EPROM, 1.0 Kbytes of Register RAM and 512

bytes of Code RAM. The JV-A has 48 Kbytes of on-chip EPROM, 1.5 Kbytes of Register RAM and 512 bytes

of Code RAM.

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

The MCS 96 microcontroller family members are all

high performance microcontrollers with a 16-bit

CPU. The 87C196Kx/Jx family members listed

above are composed of the high-speed (16 MHz)

core as well as the following peripherals: up to 48

Kbytes of Programmable EPROM, up to 1.5 Kbytes

of Register RAM, 512 bytes of code RAM (16-bit

addressing modes) with the ability to execute from

this RAM space, an eight channel-10-Bit/g3 LSB

analog to digital converter with programmable S/H

times with conversion times k5ms at 16 MHz, an

asynchronous/synchronous serial I/O port (8096

compatible) with a dedicated 16-bit baud rate gener-

ator, an additional synchronous serial I/O port (8096

compatible) with a dedicated 16-bit baud rate gener-

ator, an additional synchronous serial I/O port with

full duplex master/slave transceivers, a flexible tim-

er/counter structure with prescaler, cascading, and

quadrature capabilities, 10 modularized multiplexed

high speed I/O for capture and compare (called

Event Processor Array) with 250 ns resolution and

double buffered inputs, a sophisticated prioritized in-

terrupt structure with programmable Peripheral

Transaction Server (PTS). The PTS has several

channel modes, including single/burst block trans-

fers from any memory location to any memory loca-

tion, a PWM and PWM toggle mode to be used in

conjunction with the EPA, and an A/D scan mode.

Additional SFR space is allocated for the EPA and

can be ‘‘windowed’’ into the lower Register RAM

area.

Please refer to the following datasheets for higher

frequency versions of devices contained within this

datasheet: 20 MHz 87C196JT: Order Ý272529;

20 MHz 87C196JV: Order Number 272580.

ARCHITECTURE

The 87C196KR/KQ/JV/JT/JR/JQ are members of

the MCS 96 microcontroller family, has the same ar-

chitecture and uses the same instruction set as the

80C196KB/KC. Many new features have been add-

ed including:

CPU FEATURES

#Powerdown and Idle Modes

#16 MHz Operating Frequency

#A High Performance Peripheral Transaction Serv-

er (PTS)

#Up to 37 Interrupt Vectors

#Up to 512 Bytes of Code RAM

#Up to 1.5 Kbytes of Register RAM

#‘‘Windowing’’ Allows 8-Bit Addressing to Some

16-Bit Addresses

#1.75 ms 16 x 16 Multiply

#3ms 32/16 Divide

#Oscillator Fail Detect

PERIPHERAL FEATURES

#Programmable A/D Conversion and S/H Times

#10 Capture/Compare I/O with 2 Flexible Timers

#Synchronous Serial I/O Port for Full Duplex Seri-

al I/O

#Total Utilization of ALL Available Pins (I/O Mux’d

with Control)

#2 16-Bit Timers with Prescale, Cascading and

Quadrature Counting Capabilities

#Up to 12 Externally Triggered Interrupts

NEW INSTRUCTIONS

XCH/XCHB

Exchange the contents of two locations, either Word

or Byte is supported.

BMOVi

Interruptable Block Move Instruction, allows the user

to be interrupted during long executing Block Moves.

TIJMP

Table Indirect JUMP. This instruction incorporates a

way to do complex CASE level branches through

one instruction. An example of such code savings:

several interrupt sources and only one interrupt vec-

tor. The TIJMP instruction will sort through the

sources and branch to the appropriate sub-code lev-

el in one instruction. This instruction was added es-

pecially for the EPA structure, but has other code

saving advantages.

EPTS/DPTS

Enable and Disable PTS Interrupts (Works like EI

and DI).

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

SFR OPERATION

An additional 256 bytes of SFR registers were add-

ed to the 8XC196KR devices. These locations were

added to support the wide range of on-chip peripher-

als that the 8XC196KR has. This memory space

(1F00– 1FFFH) has the ability to be addressed as

direct 8-bit addresses through the ‘‘windowing’’

technique. Any 32-, 64- or 128-byte section can be

relocated in the upper 32, 64 or 128 bytes of the

internal register RAM (080– FFH) address space.

270827–1

Figure 1. Block Diagram

270827–15

Figure 2. The 8XC196KR Family Nomenclature

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

270827–2

270827–3

Figure 3. Package Diagrams

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

PIN DESCRIPTIONS

Symbol Name and Function

VCC Main supply voltage (a5V).

VSS,V

SS,V

SS Digital circuit ground (0V). There are three VSS pins, all of which MUST be

connected to a single ground plane.

VREF Reference for the A/D converter (a5V). VREF is also the supply voltage to the

analog portion of the A/D converter and the logic used to read Port 0. Must be

connected for A/D and Port 0 to function.

VPP Programming voltage for the EPROM parts. It should be a12.5V for

programming. It is also the timing pin for the return from powerdown circuit.

Connect this pin with a 1 mF capacitor to VSS anda1MXresistor to VCC. If this

function is not used, VPP may be tied to VCC.

ANGND Reference ground for the A/D converter. Must be held at nominally the same

potential as VSS.

XTAL1 Input of the oscillator inverter and the internal clock generator.

XTAL2 Output of the oscillator inverter.

P2.7/CLKOUT Output of the internal clock generator. The frequency is (/2 the oscillator

frequency. It has a 50% duty cycle. Also LSIO pin.

RESET Reset input to the chip. Input low for at least 16 state times will reset the chip. The

subsequent low to high transition resynchronizes CLKOUT and commences a 10-

state time sequence in which the PSW is cleared, bytes are read from 2018H and

201AH loading the CCBs, and a jump to location 2080H is executed. Input high for

normal operation. RESET has an internal pullup.

P5.7/BUSWIDTH Input for bus width selection. If CCR bit 1 is a one and CCR1 bit 2 is a one, this pin

dynamically controls the Bus width of the bus cycle in progress. If BUSWIDTH is

low, an 8-bit cycle occurs. If BUSWIDTH is high, a 16-bit cycle occurs. If CCR bit 1

is ‘‘0’’ and CCR1 bit 2 is ‘‘1’’, all bus cycles are 8-bit, if CCR bit 1 is ‘‘1’’ and CCR1

bit 2 is ‘‘0’’, all bus cycles are 16-bit. CCR bit 1 e‘‘0’’ and CCR1 bit 2 e‘‘0’’ is

illegal. Also an LSIO pin when not used as BUSWIDTH.

NMI A positive transition causes a non-maskable interrupt vector through memory

location 203EH. Used by Intel (GND this pin).

P5.1/INST Output high during an external memory read indicates the read is an instruction

fetch. INST is valid throughout the bus cycle. INST is active only during external

memory fetches, during internal [EP]ROM fetches INST is held low. Also LSIO

when not INST.

EA Input for memory select (External Access). EA equal to a high causes memory

accesses to locations 2000H through 5FFFH to be directed to on-chip EPROM/

ROM. EA equal to a low causes accesses to these locations to be directed to off-

chip memory. EA ea

12.5V causes execution to begin in the Programming

Mode. EA latched at reset.

P5.0/ALE/ADV Address Latch Enable or Address Valid output, as selected by CCR. Both pin

options provide a latch to demultiplex the address from the address/data bus.

When the pin is ADV, it goes inactive (high) at the end of the bus cycle. ADV can

be used as a chip select for external memory. ALE/ADV is active only during

external memory accesses. Also LSIO when not used as ALE.

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

PIN DESCRIPTIONS (Continued)

Symbol Name and Function

P5.3/RD Read signal output to external memory. RD is active only during external memory

reads or LSIO when not used as RD.

P5.2/WR/WRL Write and Write Low output to external memory, as selected by the CCR, WR will

go low for every external write, while WRL will go low only for external writes

where an even byte is being written. WR/WRL is active during external memory

writes. Also an LSIO pin when not used as WR/WRL.

P5.5/BHE/WRH Byte High Enable or Write High output, as selected by the CCR. BHE e0 selects

the bank of memory that is connected to the high byte of the data bus. A0 e0

selects that bank of memory that is connectd to the low byte. Thus accesses to a

16-bit wide memory can be to the low byte only (A0 e0, BHE e1), to the high

byte only (A0 e1, BHE e0) or both bytes (A0 e0, BHE e0). If the WRH

function is selected, the pin will go low if the bus cycle is writing to an odd memory

location. BHE/WRH is only valid during 16-bit external memory write cycles. Also

an LSIO pin when not BHE/WRH.

P5.6/READY Ready input to lengthen external memory cycles, for interfacing with slow or

dynamic memory, or for bus sharing. If the pin is high, CPU operation continues in

a normal manner. If the pin is low prior to the falling edge of CLKOUT, the memory

controller goes into a wait state mode until the next positive transition in CLKOUT

occurs with READY high. When external memory is not used, READY has no

effect. The max number of wait states inserted into the bus cycle is controlled by

the CCR/CCR1. Also an LSIO pin when READY is not selected.

P5.4/SLPINT Dual functional I/O pin. As a bidirectional port pin or as a system function. The

system function is a Slave Port Interrupt Output Pin.

P6.2/T1CLK Dual function I/O pin. Primary function is that of a bidirectional I/O pin, however it

may also be used as a TIMER1 Clock input. The TIMER1 will increment or

decrement on both positive and negative edges of this pin.

P6.3/T1DIR Dual function I/Opin. Primary function is that of a bidirectional I/O pin, however it

may also be used as a TIMER1 Direction input. The TIMER1 will increment when

this pin is high and decrements when this pin is low.

PORT1/EPA0– 7 Dual function I/O port pins. Primary function is that of bidirectional I/O. System

function is that of High Speed capture and compare. EPA0 and EPA2 have yet

P6.0– 6.1/EPA8– 9

another function of T2CLK and T2DIR of the TIMER2 timer/counter.

PORT 0/ACH0– 7 8-bit high impedance input-only port. These pins can be used as digital inputs

and/or as analog inputs to the on-chip A/D converter. These pins are also used

as inputs to EPROM parts to select the Programming Mode.

P6.4– 6.7/SSIO Dual function I/O ports that have a system function as Synchronous Serial I/O.

Two pins are clocks and two pins are data, providing full duplex capability.

PORT 2 8-bit multi-functional port. All of its pins are shared with other functions.

PORT 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with

the multiplexed address/data bus which has strong internal pullups.

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS**

Storage Temperature ÀÀÀÀÀÀÀÀÀÀb60§Ctoa

150§C

Voltage from VPP or EA to

VSS or ANGND ÀÀÀÀÀÀÀÀÀÀÀÀÀÀb0.5V to a13.0V

Voltage from Any Other Pin

to VSS or ANGND ÀÀÀÀÀÀÀÀÀÀÀÀÀb0.5V to a7.0V

This includes VPP on ROM and CPU devices.

Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0.5W

NOTICE: This is a production data sheet. The specifi-

cations are subject to change without notice.

WARNING: Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage.

These are stress ratings only. Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability.

OPERATING CONDITIONS

Symbol Parameter Min Max Units

TAAmbient Temperature under Bias b40 a125 §C

VCC Digital Supply Voltage 4.50 5.50 V

VREF Analog Supply Voltage 4.50 5.50 V

FOSC Oscillator Frequency 4 16 MHz(4)

NOTE:

ANGND and VSS should be nominally at the same potential.

DC CHARACTERISTICS (Under Listed Operating Conditions)

Symbol Parameter Min Typ Max Units Test Conditions

ICC VCC Supply Current 75 mA XTAL1 e16 MHz,

(b40§Ctoa

125§C (JV e80) VCC eVPP eVREF e5.5V

Ambient) 50 (While Device in Reset)

ICC1 Active Mode Supply 50 mA

Current (Typical) (JV e55)

IREF A/D Reference 25mA

Supply Current

IIDLE Idle Mode Current 15 30 mA XTAL1 e16 MHz,

(JV e32) VCC eVPP eVREF e5.5V

IPD Powerdown Mode 50 TBD mAVCC eVPP eVREF e5.5V

Current (Note 6)

VIL Input Low Voltage b0.5V 0.3 VCC V

(All Pins)

VIH Input High Voltage 0.7 VCC VCC a0.5 V (Note 7)

(All Pins)

VOL Output Low Voltage 0.3 V IOL e200 mA (Notes 3, 5)

(Outputs Configured 0.45 V IOL e3.2 mA

as Push/Pull) 1.5 V IOL e7.0 mA

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

DC CHARACTERISTICS (Under Listed Operating Conditions) (Continued)

Symbol Parameter Min Typ Max Units Test Conditions

VOH Output High Voltage VCC b0.3 V IOH eb

200 mA (Notes 3, 5)

(Outputs Configured VCC b0.7 V IOH eb

3.2 mA

as Push/Pull) VCC b1.5 V IOH eb

7.0 mA

ILI Input Leakage Current g8mAV

SS sVIN sVCC

(Std. Inputs) JT/JV: g10 (Note 2)

ILI1 Input Leakage Current g1mAV

SS sVIN sVREF

(Port 0ÐA/D Inputs) JT/JV: g2

IIH Input High Current a175 mAV

SS sVIN sVCC

(NMI Pin)

VOH2 Output High Voltage VCC b1V V IOH eb

15 mA (Notes 1, 8)

in RESET

IOH2 Output High Current b6b35 mAV

OH2 eVCC b1.0V

(KR, KQ) in RESET b15 b60 mAV

OH2 eVCC b2.5V

b20 b70 mAV

OH2 eVCC b4.0V

IOH2 Output High b30 b120 mAV

OH2 eVCC b1.0V

(JV, JT, Current in b75 b240 mAV

OH2 eVCC b2.5V

JR-D, JQ-D) RESET b90 b280 mAV

OH2 eVCC b4.0V

RRST Reset Pullup Resistor 6K 65K X

VOL3 Output Low Voltage 0.3 V IOL3 e4 mA (Note 9)

in RESET 0.5 V IOL3 e6mA

(RESET Pin only) 0.8 V IOL3 e10 mA

CSPin Capacitance 10 pF FTEST e1.0 MHz

(Any Pin to VSS)

RWPU Weak Pullup Resistance 150K X(Note 6)

(Approx)

NOTES:

1. All BD (bidirectional) pins except P5.1/INST and P2.7/CLKOUT which are excluded due to their not being weakly pulled

high in reset. BD pins include Port1, Port2, Port3, Port4, Port5 and Port6.

2. Standard Input pins include XTAL1, EA, RESET and Ports 1, 2, 3, 4, 5, 6 when configured as inputs.

3. All Bidirectional I/O pins when configured as Outputs (Push/Pull).

4. Device is Static and should operate below 1 Hz, but only tested down to 4 MHz.

5. Maximum IOL/IOH currents per pin will be characterized and published at a later date. Target values are g10 mA.

6. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and

VREF eVCC e5.0V.

7. VIH max for Port0 is VREF a0.5V.

8. Refer to ‘‘VOH2/IOH2 Specification’’ errata Ý1 in errata section of this datasheet.

9. This specification is not tested in production and is based upon theoretical estimates and/or product characterization.

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

KR/KQ/JR/JQ ICC vs Frequency

270827–4

NOTES:

ICC Max e3.88 cFreq a13.43

IIDLE Max e1.65 cFreq a2.2

JT ICC vs Frequency

270827–19

NOTES:

ICC Max e3.25 cFreq a23

IIDLE Max e1.25 cFreq a15

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

AC CHARACTERISTICS (Over Specified Operating Conditions)

Test Conditions: Capacitance Load on All Pins e100 pF, Rise and Fall Times e10 ns, FOSC e16 MHz.

The system must meet these specifications to work with the 87C196KR/KQ/JV/JT/JR/JQ

Symbol Parameter Min Max Units

TAVYV Address Valid to READY Setup 2 TOSC b75 ns

TLLYV ALE Low to READY Setup TOSC b70 ns

TYLYH Non READY Time No Upper Limit ns

TCLYX READY Hold after CLKOUT Low 0 TOSC b30 ns(1)

TLLYX READY Hold after ALE Low TOSC b15 2 TOSC b40 ns(1)

TAVGV Address Valid to Buswidth Setup 2 TOSC b75 ns

TLLGV ALE Low to Buswidth Setup TOSC b60 ns

TCLGX Buswidth Hold after CLKOUT Low 0 ns

TAVDV Address Valid to Input Data Valid 3 TOSC b55 ns

TRLDV RD Active to Input Data Valid TOSC b22 ns

TCLDV CLKOUT Low to Input Data Valid TOSC b50 ns

TRHDZ End of RD to Input Data Float TOSC ns

TRXDX Data Hold after RD Inactive 0 ns

NOTE:

1. If max is exceeded, additional wait states will occur.

The 87C196KR/KQ/JV/JT/JR/JQ will meet these specifications.

Symbol Parameter Min Max Units

FXTAL Oscillator Frequency 4.0 16.0 MHz(1)

TOSC Oscillator Period (1/Fxtal) 62.5 250 ns

TXHCH XTAL1 High to CLKOUT 20 110 ns(2)

High or Low

TCLCL CLKOUT Period 2 TOSC ns

TCHCL CLKOUT High Period TOSC b10 TOSC a15 ns

TCLLH CLKOUT Falling Edge b10 15 ns

to ALE Rising

TLLCH ALE/ADV Falling Edge b20 15 ns

to CLKOUT Rising

TLHLH ALE/ADV Cycle Time 4 TOSC ns

TLHLL ALE/ADV High Period TOSC b10 TOSC a10 ns

TAVLL Address Setup to ALE/ADV TOSC b15 ns

Falling Edge

TLLAX Address Hold after ALE/ADV TOSC b40 ns

Falling Edge

TLLRL ALE/ADV Falling Edge to TOSC b30 ns

RD Falling Edge

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

AC CHARACTERISTICS (Over Specified Operating Conditions) (Continued)

Test Conditions: Capacitance Load on All Pins e100 pF, Rise and Fall Times e10 ns, FOSC e16 MHz.

The 87C196KR/KQ/JV/JT/JR/JQ will meet these specifications.

Symbol Parameter Min Max Units

TRLCL RD Low to CLKOUT 4 30 ns

Falling Edge

TRLRH RD Low Period TOSC b5ns

RHLH RD Rising Edge to TOSC TOSC a25 ns(3)

ALE/ADV Rising Edge

TRLAZ RD Low to Address Float 5 ns(5)

TLLWL ALE/ADV Falling Edge TOSC b10 ns

to WR Falling Edge

TCLWL CLKOUT Low to b525ns

WR Falling Edge

TQVWH Data Stable to WR Rising Edge TOSC b23 ns

TCHWH CLKOUT High to WR b10 15 ns

Rising Edge

TWLWH WR Low Period TOSC b20 ns

TWHQX Data Hold after WR Rising Edge TOSC b25 ns

TWHLH WR Rising Edge to ALE/ADV TOSC b10 TOSC a15 ns(3)

Rising Edge

TWHBX BHE, INST Hold after WR TOSC b10 ns

Rising Edge

TWHAX AD8– 15 Hold after WR Rising Edge TOSC b30(4) ns

TRHBX BHE, INST Hold after RD Rising Edge TOSC b10 ns

TRHAX AD8– 15 Hold after RD Rising Edge TOSC b30(4) ns

NOTES:

1. Testing performed at 4.0 MHz, however, the device is static by design and will typically operate below 1 Hz.

2. Typical specifications, not guaranteed.

3. Assuming back-to-back bus cycles.

4. 8-bit bus only.

5. TRLAZ (max) e5 ns by design.

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

System Bus Timing

270827–5

READY/BUSWIDTH TIMING

270827–6

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

EXTERNAL CLOCK DRIVE

Symbol Parameter Min Max Units

1/TXLXL Oscillator Frequency 4.0 16 MHz

TXLXL Oscillator Period (TOSC) 62.5 250 ns

TXHXX High Time 0.35 TOSC 0.65 TOSC ns

TXLXX Low Time 0.35 TOSC 0.65 TOSC ns

TXLXH Rise Time 10 ns

TXHXL Fall Time 10 ns

EXTERNAL CLOCK DRIVE WAVEFORMS

270827–7

AC TESTING INPUT, OUTPUT WAVEFORMS

270827–8

NOTE:

AC Testing Inputs are driven at 3.5V for a logic ‘‘1’’ and

0.45V for a logic ‘‘0’’. Timing measurements are made

at 2.0V for a logic ‘‘1’’ and 0.8V for logic ‘‘0’’.

FLOAT WAVEFORMS

270827–9

NOTE:

For timing purposes a port pin is no longer floating

when a 150 mV change from load voltage occurs and

begins to float when a 150 mV change from the loading

VOH/VOL level occurs IOL/IOH s15 mA.

THERMAL CHARACTERISTICS

Device and Package iJA iJC

AN87C196KR/KQ 41§C/W 14§C/W

(68-Lead PLCC)

AN87C196JV/JT/JR/JQ 42§C/W 15§C/W

(52-Lead PLCC)

NOTES:

1. iJA eThermal resistance between junction and the surround-

ing environment (ambient). Measurements are taken 1

ft. away from case in air flow environment.

iJC eThermal resistance between junction and package sur-

face (case).

2. All values of iJA and iJC may fluctuate depending on the en-

vironment (with or without airflow, and how much airflow) and

device power dissipation at temperature of operation. Typical

variations are g2§C/W.

3. Values listed are at a maximum power dissipation of 0.50W.

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

EXPLANATION OF AC SYMBOLS

Each symbol is two pairs of letters prefixed by ‘‘t’’ for time. The characters in a pair indicate a signal and its

condition, respectively. Symbols represent the time between the two signal/condition points.

Conditions:

HÐ High

LÐ Low

VÐ Valid

XÐ No Longer Valid

ZÐ Floating

Signals:

AÐ Address

BÐ BHE

CÐ CLKOUT

DÐ DATA

GÐ Buswidth

HÐ HOLD

HAÐ HLDA

LÐ ALE/ADV

RÐ RD

WÐ WR/WRH/WRI

XÐ XTAL1

YÐ READY

EPROM SPECIFICATIONS

AC EPROM PROGRAMMING CHARACTERISTICS

Operating Conditions: Load Capacitance e150 pF; TCe25§Cg5§C, VREF e5.0V g0.5V, VSS,

ANGND e0V. VPP e12.5V g0.25V; EA e12.5V g0.25V; FOSC e5.0 MHz

Symbol Parameter Min Max Units

TAVLL Address Setup Time 0 TOSC

TLLAX Address Hold Time 100 TOSC

TDVPL Data Setup Time 0 TOSC

TPLDX Data Hold Time 400 TOSC

TLLLH PALE Pulse Width 50 TOSC

TPLPH PROG Pulse Width(3) 50 TOSC

TLHPL PALE High to PROG Low 220 TOSC

TPHLL PROG High to Next PALE Low 220 TOSC

TPHDX Word Dump Hold Time 50 TOSC

TPHPL PROG High to Next PROG Low 220 TOSC

TPLDV PROG Low to Word Dump Valid 50 TOSC

TSHLL RESET High to First PALE Low 1100 TOSC

TPHIL PROG High to AINC Low 0 TOSC

TILIH AINC Pulse Width 240 TOSC

TILVH PVER Hold after AINC Low 50 TOSC

TILPL AINC Low to PROG Low 170 TOSC

TPHVL PROG High to PVER Valid 220 TOSC

NOTES:

1. Run time programming is done with FOSC e6.0 MHz to 10.0 MHz, VCC,V

PD,V

REF e5V g0.5V, TCe25§Cg5§C and

VPP e12.5V g0.25V. For run-time programming over a full operating range, contact factory.

2. Programming Specifications are not tested, but guaranteed by design.

3. This specification is for the word dump mode. For programming pulses use 300 TOSC a100 ms.

DC EPROM PROGRAMMING CHARACTERISTICS

Symbol Parameter Min Max Units

IPP VPP Programming Supply Current 100 mA

NOTE:

VPP must be within 1V of VCC while VCC k4.5V. VPP must not have a low impedance path to ground or VSS while VCC l

4.5V.

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

EPROM PROGRAMMING WAVEFORMS

SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE

270827–10

SLAVE PROGRAMMING MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT

270827–11

SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE

AND AUTO INCREMENT

270827–12

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

A TO D CONVERTER SPECIFICATIONS

The speed of the A/D converter in the 10-bit or 8-bit

modes can be adjusted by setting the ADÐTIME

special function register to the appropriate value.

The ADÐTIME register only programs the speed at

which the conversions are performed, not the speed

at which it can convert correctly.

The converter is ratiometric, so absolute accuracy is

dependent on the accuracy and stability of VREF.

VREF must not exceed VCC by more than 0.5V since

it supplies both the resistor ladder and the digital

portion of the converter and input port pins.

For testing purposes, after a conversion is started,

the device is placed in the IDLE mode until the con-

version is complete. Testing is performed at VREF e

5.12V and 16 MHz operating frequency.

There is an ADÐTEST register that allows for con-

version on ANGND and VREF as well as zero offset

adjustment. The absolute error listed is without do-

ing any adjustments.

A/D OPERATING CONDITIONS(1)

Symbol Description Min Max Units

TAAutomotive Ambient Temperature b40 a125 §C

VCC Digital Supply Voltage 4.50 5.50 V

VREF Analog Supply Voltage 4.50 5.50(2, 3) V

TSAM Sample Time 2.0 ms(4)

TCONV Conversion Time 16.5 19.5 ms(4)

FOSC Oscillator Frequency 4 16 MHz

NOTES:

1. ANGND and VSS should nominally be at the same potential.

2. VREF must not exceed VCC by more than a0.5V.

3. Testing is performed at VREF e5.12V.

4. The value of ADÐTIME must be selected to meet these specifications.

Parameter Typical*(1) Min Max Units**

Resolution 1024 1024 Level

10 10 Bits

Absolute Error 0 b3 LSBs

Full Scale Error g2 LSBs

Zero Offset Error g2 LSBs

Non-Linearity g3 LSBs

Differential Non-Linearity lb0.5 a0.5 LSBs

Channel-to-Channel Matching 0 g1 LSBs

Repeatability g0.25 0 LSBs(1)

Temperature Coefficients:

Offset 0.009 LSB/C(1)

Fullscale 0.009 LSB/C(1)

Differential Non-Linearity 0.009 LSB/C(1)

Off Isolation b60 dB(1, 2, 3)

Feedthrough b60 dB(1, 2)

VCC Power Supply Rejection b60 dB(1, 2)

Input Resistance 750 1.2K X(1)

DC Input Leakage 0 g1mA

JT/JV eg2

NOTES:

*These values are expected for most parts at 25§C but are not tested or guaranteed.

**An ‘‘LSB’’, as used here, has a value of approximately 5 mV. (See Automotive Handbook for A/D glossary of terms).

1. These values are not tested in production and are based on theoretical estimates and/or laboratory test.

2. DC to 100 KHz

3. Multiplexer Break-Before-Make Guaranteed.

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

HOLD/HLDA Timings

Symbol Description Min Max Units Notes

THVCH HOLD Setup 65 ns (Note 1)

TCLHAL CLKOUT Low to HLDA Low b15 15 ns

TCLBRL CLKOUT Low to BREQ Low b15 15 ns

TAZHAL HLDA Low to Address Float 25 ns

TBZHAL HLDA Low to BHE, INST, RD,WRWeakly Driven 25 ns

TCLHAH CLKOUT Low to HLDA High b15 15 ns

TCLBRH CLKOUT Low to BREQ High b15 15 ns

THAHAX HLDA High to Address Valid b15 ns

THAHBV HLDA High to BHE, INST, RD, WR Valid b10 ns

TCLLH CLKOUT Low to ALE High b10 15 ns

NOTE:

1. To guarantee recognition at next clock.

DC SPECIFICATIONS IN HOLD

Parameter Min Max Units

Weak Pullups on ADV, RD, 50K 250K VCC e5.5V, VIN e0.45V

WR,WRL, BHE

Weak Pulldowns on 10K 50K VCC e5.5V, VIN e2.4

ALE, INST

270827–16

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

AC CHARACTERISTICSÐSLAVE PORT

SLAVE PORT WAVEFORMÐ(SLPL e0)

270827–17

SLAVE PORT TIMINGÐ(SLPL e0)(1, 2, 3)

Symbol Parameter Min Max Units

TSAVWL Address Valid to WR Low 50 ns

TSRHAV RD High to Address Valid 60 ns

TSRLRH RD Low Period TOSC ns

TSWLWH WR Low Period TOSC ns

TSRLDV RD Low to Output Data Valid 60 ns

TSDVWH Input Data Setup to WR High 20 ns

TSWHQX WR High to Data Invalid 30 ns

TSRHDZ RD High to Data Float 15 ns

NOTES:

1. Test Conditions: FOSC e16 MHz, TOSC e60 ns. Rise/Fall Time e10 ns. Capacitive Pin Load e100 pF.

2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests.

3. Specifications above are advanced information and are subject to change.

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

AC CHARACTERISTICSÐSLAVE PORT (Continued)

SLAVE PORT WAVEFORMÐ(SLPL e1)

270827–18

SLAVE PORT TIMINGÐ(SLPL e1)(1, 2, 3)

Symbol Parameter Min Max Units

TSELLL CS Low to ALE Low 20 ns

TSRHEH RD or WR High to CS High 60 ns

TSLLRL ALE Low to RD Low TOSC ns

TSRLRH RD Low Period TOSC ns

TSWLWH WR Low Period TOSC ns

TSAVLL Address Valid to ALE Low 20 ns

TSLLAX ALE Low to Address Invalid 20 ns

TSRLDV RD Low to Output Data Valid 60 ns

TSDVWH Input Data Setup to WR High 20 ns

TSWHQX WR High to Data Invalid 30 ns

TSRHDZ RD High to Data Float 15 ns

NOTES:

1. Test Conditions: FOSC e16 MHz, TOSC e60 ns. Rise/Fall Time e10 ns. Capacitive Pin Load e100 pF.

2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests.

3. Specifications above are advanced information and are subject to change.

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

AC CHARACTERISTICSÐSERIAL PORTÐSHIFT REGISTER MODE

SERIAL PORT TIMINGÐSHIFT REGISTER MODE

Test Conditions: TAeb

40§Ctoa

125§C; VCC e5.0V g10%; VSS e0.0V; Load Capacitance e100 pF

Symbol Parameter Min Max Units

TXLXL Serial Port Clock Period 8 TOSC ns

TXLXH Serial Port Clock Falling 4 TOSC b50 4 TOSC a50 ns

Edge to Rising Edge

TQVXH Output Data Setup 3 TOSC ns

to Clock Rising Edge

TXHQX Output Data Hold 2 TOSC b50 ns

after Clock Rising Edge

TXHQV Next Output Data Valid 2 TOSC a50 ns

after Clock Rising Edge

TDVXH Input Data Setup 2 TOSC a200 ns

to Clock Rising Edge

TXHDX(1) Input Data Hold 0 ns

after Clock Rising Edge

TXHQZ(1) Last Clock Rising to 5 TOSC ns

Output Float

NOTES:

1. Parameter not tested.

WAVEFORMÐSERIAL PORTÐSHIFT REGISTER MODE 0

SERIAL PORT WAVEFORMÐSHIFT REGISTER MODE

270827–13

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

52-LEAD DEVICES

Intel offers 52-lead versions of the 87C196KR de-

vice: the 87C196JV/JT/JR/JQ devices. The first

samples and production units use the 87C196KR die

and bond it out in a 52-lead package.

It is important to point out some functionality differ-

ences because of future devices or to remain soft-

ware consistent with the 68-lead device. Because of

the absence of pins on the 52-lead device some

functions are not supported.

52-Lead Unsupported Functions:

Analog Channels 0 and 1

INST Pin Functionality

SLPINT Pin Support

HLD/HLDA Functionality

External Clocking/Direction of Timer1

WRH or BHE Functions

Dynamic Buswidth

Dynamic Wait State Control

The following is a list of recommended practices

when using the 52-lead device:

(1) External Memory. Use an 8-bit bus mode only.

There is neither a WRH or BUSWIDTH pin. The

bus cannot dynamically switch from 8- to 16-bit

or vice versa. Set the CCB bytes to an 8-bit only

mode, using WR function only.

(2) Wait State Control. Use the CCB bytes to con-

figure the maximum number of wait states. If the

READY pin is selected to be a system function,

the device will lockup waiting for READY. If the

READY pin is configured as LSIO (default after

RESET), the internal logic will receive a logic

‘‘0’’ level and insert the CCB defined number of

wait states in the bus cycle. DON’T USE IRC e

‘‘111’’.

(3) NMI Support. The NMI is not bonded out. Make

the NMI vector at location 203Eh vector to a

Return instruction. This is for glitch safety pro-

tection only.

(4) Auto-Programming Mode. The 52-lead device

will ONLY support the 16-bit zero wait state bus

during auto-programming.

(5) EPA4 through EPA7. Since the JR and JQ de-

vices use the KR silicon, these functions are in

the device, just not bonded out. A programmer

can use these as compare only channels or for

other functions like software timer, start an A/D

conversion, or reset timers.

(6) Slave Port Support. The Slave port cannot be

easily used on 52-lead devices due to

P5.4/SLPINT and P5.1/SLPCS not being bond-

ed-out.

(7) Port Functions. Some port pins have been re-

moved. P5.7, P5.6, P5.5, P5.1, P6.2, P6.3, P1.4

through P1.7, P2.3, P2.5, P0.0 and P0.1. The

PxREG, PxSSEL, and PxIO registers can still be

updated and read. The programmer should not

use the corresponding bits associated with the

removed port pins to conditionally branch in

software. Treat these bits as RESERVED.

Additionally, these port pins should be setup in-

ternally by software as follows:

1. Written to PxREG as ‘‘1’’ or ‘‘0’’.

2. Configured as Push/Pull, PxIO as ‘‘0’’.

3. Configured as LSIO.

This configuration will effectively strap the pin

either high or low.

DO NOT Configure as

Open Drain output ‘’1’’, or as an Input pin.

This device is CMOS.

87C196KR/KQ/JV/JT/JR/JQ ERRATA

1. VOH2/IOH2 Specification (Note C)

In the DC Characteristics section of this data-

sheet, VOH2 indicates the strength of the internal

weak pullups that are active during and after re-

set until the user writes to the PxMODE register.

C-step devices do not meet this specification.

The new specification for C-step devices is VOH2

(min) eVCC b1V at IOH2 eb

6mA. Note that

JR/JQ D-step devices are not affected by this

errata and meet the published specification.

2. 1B00h– 1BDFh External Addressing

(Notes C, D)

Affected devices cannot access external memory

locations 1B00h– 1BDFh. A bus cycle does not

occur when these addresses are accessed. If at-

tempting to read from 1B00h– 1BDFh a value of

FFh is returned even though a read cycle is not

generated. Writing to these locations will not gen-

erate an external bus cycle either. This errata has

been corrected on JV and JT devices.

3. Port3 Push-Pull Operation (Note C)

If Port3 is operating as a push-pull LSIO (Low-

Speed I/O) port and an address/data bus cycle

occurs, Port3 will continue to drive the address/

data bus with its LSIO data during the bus cycle.

It is rather unlikely that this errata would affect an

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

application because the application would have

to use Port3 for both LSIO and as an external

addr/data bus. If an application uses external

memory, Port3 should not be selected as push-

pull LSIO.

NOTES:

‘‘C’’ ePresent on C-step devices

‘‘D’’ ePresent on D-step devices

‘‘V’’ ePresent on JV A-step devices

‘‘T’’ ePresent on JT A-step devices

Devices can be identified by a special mark fol-

lowing the eight-digit FPO number on the top of

the package. The following chart specifies what

these markings are for various device steppings:

Device Topside Marking

KR, KQ C-step ‘‘C’’

JR, JQ D-step ‘‘D’’

JV, JT A-step ‘‘A’’

87C196KR/KQ/JV/JT/JR/JQ DESIGN

CONSIDERATIONS

1. EPA Timer RESET/Write Conflict

If the user writes to the EPA timer at the same

time that the timer is reset, it is indeterminate

which will take precedence. Users should not

write to a timer if using EPA signals to reset it.

2. Valid Time Matches

The timer must increment/decrement to the

compare value for a match to occur. A match

does not occur if the timer is loaded with a value

equal to an EPA compare value. Matches also do

not occur if a timer is reset and 0 is the EPA

compare value.

3. P6ÐPIN.4– .7 Not Updated Immediately

Values written to P6ÐREG are temporarily held

in a buffer. If P6ÐMODE is cleared, the buffer is

loaded into P6ÐREG.x. If P6ÐMODE is set, the

value stays in the buffer and is loaded into P6Ð

REG.x when P6ÐMODE.x is cleared. Since read-

ing P6ÐREG returns the current value in P6Ð

REG and not the buffer, changes to P6ÐREG

cannot be read until/unless P6ÐMODE.x is

cleared.

4. Write Cycle during Reset

If RESET occurs during a write cycle, the con-

tents of the external memory device may be cor-

rupted.

5. Indirect Shift Instruction

The upper 3 bits of the byte register holding the

shift count are not masked completely. If the shift

count register has the value 32 cn, where n e

1, 3, 5, or 7, the operand will be shifted 32 times.

This should have resulted in no shift taking place.

6. P2.7 (CLKOUT)

P2.7 (CLKOUT) does not operate in open drain

mode.

7. CLKOUT

The CLKOUT signal is active on P2.7 during

RESET for the KR, KQ, JV, JT, JR and JQ de-

vices. Note that CLKOUT is not active on P2.7

in RESET for the KT.

8. EPA Overruns

EPA ‘‘lock-up’’ can occur if overruns are not han-

dled correctly, refer to Intel Techbit ÝDB0459

‘‘Understanding EPA Capture Overruns’’,

dated

12-9-93. Applies to EPA channels with interrupts

and overruns enabled (ON/RT bit in

EPAÐCONTROL register set to ‘‘1’’).

9. Indirect Addressing with Auto-Increment

For the special case of a pointer pointing to itself

using auto-increment, an incorrect access of the

incremented pointer address will occur instead of

an access to the original pointer address. All oth-

er indirect auto-increment accesses will note be

affected. Please refer to Techbit ÝMC0593.

Incorrect sequence:

ld ax,#ax ; Results in ax being

incremented by 1 and the

ldb bx,[ax]0 ;contents of the address

pointed to by axa1tobe

loaded into bx.

Correct sequence:

ld ax,#bx ; where ax ibx. Results in

the contents of the address

ldb cx,[ax]0 ;pointed to by ax to be

loaded into bx and ax

incremented by 1.

10. JV Additional Register RAM

The 8XC196JV has a total of 1.5 Kbytes of reg-

ister RAM. The RAM is located in two memory

ranges: 0000h– 03FFh and 1C00h– 1DFFh.

87C196JR/JQ C-step to

JR/JQ D-step –or– JV/JT A-step

DESIGN CONSIDERATIONS

This section documents differences between the

87C197JV A-step (JV-A)/87C196JT A-step (JT-A)/

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

87C196JR D-step (JR-D) and the 87C196JR C-step

(JR-C). For a list of design considerations between

68-lead and 52-lead devices, please refer to the

52-lead Device Design Considerations section of

this datasheet. Since the 87C196JV/JT/JQ are sim-

ply memory scalars of the 87C196JR, the term ‘‘JR’’

in this section will refer to JV, JT, JR and JQ ver-

sions of the device unless otherwise noted.

The JR-C is simply a 87C196KR C-step (KR-C) de-

vice packaged within a 52-lead package. This reduc-

tion in pin count necessitated not bonding-out cer-

tain pins of the KR-C device. The fact that these

‘‘removed pins’’ were still present on the device but

not available to the outside world allowed the pro-

grammer to take advantage of some of the 68-lead

KR features.

The JR-D is a fully-optimized 52-lead device based

on the 87C196KR C-step device. The KR-C design

data base was used to assure that the JR-D would

be fully compatible with the KR-C, JR-C and other

Kx family members. The main differences between

the JR-D and the JR-C is that several of the unused

(not bonded-out) functions on the JR-C were re-

moved altogether on the JR-D.

Following is a list of differences between the JR-C

and the JR-D:

1. Port3 Push-Pull Operation

It was discovered on JR-C that if Port3 is select-

ed for push-pull operation (P34ÐDRV register)

during low speed I/O (LSIO), the port was driving

data when the system bus was attempting to in-

put data. It is rather unlikely that this errata would

affect an application because the application

would have to use Port3 for both LSIO and as an

external addr/data bus. Nonetheless, this errata

was corrected on the JR-D.

2. VOH2 Strengthened

The DC Characteristics section of the Automotive

KR datasheet contains a parameter, VOH2 (Out-

put High Voltage in RESET (BD ports)), which is

specified at VCC– 1V min at IOH2 eb

15 mA.

This specification indicates the strength of the in-

ternal weak pull-ups that are active during and

after reset. These weak pull-ups stay active until

the user writes to PxMODE (previously known as

PxSSEL) and configures the port pin as desired.

These pull-ups do not meet this VOH2 spec on

the JR-C. The weak pull-ups on specified JR-D

ports have been enhanced to meet the published

specification of IOH2 eb

15 mA.

3. ONCE Mode

ONCE mode is entered by holding a single pin

low on the rising edge of RESETÝ. On the KR,

this pin is P5.4/SLPINT. The JR-C does not sup-

port ONCE mode since P5.4/SLPINT (ONCE

mode entry pin) is not bonded-out on these de-

vices. To provide ONCE mode on the JR-D, the

ONCE mode entry function was moved from

P5.4/SLPINT to P2.6/HLDA. This will allow the

JR-D to enter ONCE mode using P2.6 instead of

removed pin P5.4.

4. Port0

On the JR-C, P0.0 and P0.1 are not bonded out.

However, these inputs are present in the device

and reading them will provide an indeterminate

result.

On the JR-D, the analog inputs for these two

channels at the miltiplexer are tied to VREF.

Therefore, initiating an analog conversion on

ACH0 or ACH1 will result in a value equal to full

scale (3FFh). On the JR-D, the digital inputs for

these two channels are tied to ground, therefore

reading P0.0 or P0.1 will result in a digital ‘‘0’’.

5. Port1

On the JR-C, P1.4, P1.5, P1.6 and P1.7 are not

bonded out but are present internally on the de-

vice. This allows the programmer to write to the

port registers and clear, set or read the pin even

though it is not available to the outside world.

However, to maintain compatibility with D-step

and future devices, it is recommended that the

corresponding bits associated with the removed

pins NOT be used to conditionally branch in soft-

ware. These bits should be treated as reserved.

On the JR-D, unused port logic for these four port

pins has been removed from the device and is

not available to the programmer. Corresponding

bits in the port registers have been ‘‘hard-wired’’

to provide the following results when read:

P1ÐPIN.x (x e4,5,6,7) 1

P1ÐREG.x (x e4,5,6,7) 1

P1ÐDIR.x (x e4,5,6,7) 1

P1ÐMODE.x (x e4,5,6,7) 0

Writing to these bits will have no effect.

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

6. Port2

On the JR-C, P2.3 and P2.5 are not bonded out

but are present internally on the device. This al-

lows the programmer to write to the port registers

and clear, set or read the pin even though it is not

available to the outside world. However, to main-

tain compatibility with D-step and future devices,

it is recommended that the corresponding bits as-

sociated with the removed pins not be used to

conditionally branch in software. These bits

should be treated as reserved.

On the JR-D, unused port logic for these two port

pins has been removed from the device and is

not available to the programmer. Corresponding

bits in the port registers have been ‘‘hardwired’’

to provide the following results when read:

P2ÐPIN.x (x e3,5) 1

P2ÐREG.x (x e3,5) 1

P2ÐDIR.x (x e3,5) 1

P2ÐMODE.x (x e3,5) 0

Writing to these bits will have no effect.

7. Port5

On the JR-C, P5.1, P5.4, P5.5, P5.6 and P5.7 are

not bonded out but are present internally on the

device. This allows the programmer to write to

the port registers and clear, set or read the pin

even though it is not available to the outside

world. However, to maintain compatibility with D-

step and future devices, it is recommended that

the corresponding bits associated with the re-

moved pins not be used to conditionally branch in

software. These bits should be treated as re-

served.

On the JR-D, unused port logic for these five port

pins has been removed from the device and is

not available to the programmer. Corresponding

bits in the port registers have been ‘‘hardwired’’

to provide the following results when read:

P5ÐPIN.x (x e1,4,5,6,7) 1

P5ÐREG.x (x e1,4,5,6,7) 1

P5ÐDIR.x (x e1,4,5,6,7) 1

P5ÐMODE.x (x e1,4,6) 0

P5ÐMODE.x (x e5) (EAÝe0) 1

P5ÐMODE.x (x e5) (EAÝe1) 0

P5ÐMODE.x (x e7) 1

Writing to these bits will have no effect.

8. Port6

On the JR-C, P6.2 and P6.3 are not bonded out

but are present internally on the device. This al-

lows the programmer to write to the port registers

and clear, set or read the pin even though it is not

available to the outside world. However, to main-

tain compatibility with D-step and future devices,

it is recommended that the corresponding bits as-

sociated with the removed pins not be used to

conditionally branch in software. These bits

should be treated as reserved.

On the JR-D, unused port logic for these two port

pins has been removed from the device and is

not available to the programmer. Corresponding

bits in the port registers have been ‘‘hardwired’’

to provide the following results when read:

P6ÐPIN.x (x e2,3) 1

P6ÐREG.x (x e2,3) 1

P6ÐDIR.x (x e2,3) 1

P6ÐMODE.x (x e2,3) 0

Writing to these bits will have no effect.

9. 8XC196JQ Internal to External Memory

Roll-over Point

8XC196JQ devices are simply 8XC196JR devic-

es with less memory. Both the JQ-C and JQ-D

are fabricated from the JR-C and JR-D respect-

fully. The difference between JQ and JR devices

is that memory locations beyond the supported

boundaries on the JQ are not tested in produc-

tion and should not be used. Any software which

relies upon reading or writing these locations may

not function correctly. Following are the support-

ed memory maps for these devices:

87C196KR/KQ 87C196JV/JT 87C196JR/JQ

JQ C and D-Step JR C and D-Step

Internal (Code) RAM 400h to 47Fh 400h to 4FFh

Internal ROM/EPROM 2000h to 4FFFh 2000h to 5FFFh

It is important to note that the internal to exter-

nal memory roll-over point for both the JR and

JQ devices is the same (6000h and above goes

external). Two guidelines the programmer

should follow to insure no problems are encoun-

tered when using JQ devices are:

a) For JQ devices, the program must contain a

jump to a location greater than 5FFFh before

the 12K boundary (4FFFh) is reached. This

is necessary only if greater than 12K of pro-

gram memory is required with a JQ device

and portions of the program execute from in-

ternal ROM/EPROM.

b) For JQ devices with EAÝtied to ground, use

only internal program memory from 2000h to

4FFFh. Do not use the unsupported loca-

tions from 5000h to 5FFFh.

10. EPA Channels 4 through 7

The JR C-step device is simply a 68-lead KR-C

device packaged in a 52-lead package. The re-

duced pin-out is achieved by not bonding-out

the unsupported pins. EPA4– EPA7 are among

these pins that are not bonded-out. The fact

that EPA4– EPA7 are still present allows the

programmer to use these channels as software

timers, to start A/D conversions, reset timers,

etc. All of the port pin logic is still present and it

is possible to use the EPA to toggle these pins

internally. Please refer to the 52-Lead Device

section in this datasheet for further information.

On the JR D-step, the EPA4– EPA7 logic has

NOT been removed from the device. This al-

lows the programmer to still use these channels

(as on the C-step) for software timers, etc. The

only difference is that the associated port pin

logic has been removed and does not exist in-

ternally. To maintain C-step to D-step compati-

bility, programmers should make sure that their

software does not rely upon the removed pins.

DATASHEET REVISION HISTORY

This is the -006 version of the 87C196KR Data-

sheet. The following differences exist between the

-005 version and the -006 version:

1. The 87C196JV datasheet status has been

moved from ‘‘Product Preview’’ to that of ‘‘no

marking.’’

2. A ‘‘by design’’ note was added to the TRLAZ

specification.

3. In the Design Considerations section, the Ý7.

CLKOUT design consideration was corrected.

4. Only the two most current revision histories of

this datasheet were retained in the datasheet re-

vision history section.

The following differences exist between the -004

version and the -005 version:

1. The 87C196JT and 87C196JV 16 MHz devices

were added to the list of products covered by this

datasheet The 87C196JT and 87C196JV are

simply higher memory versions of the 87C196JR

device. For 20 MHz datasheets of these devices,

please refer to the following datasheets:

20 MHz 87C196JT: order Ý272529-001

20 MHz 87C196JV: order Ý272580-001

2. The status of the datasheet has been moved

from ‘‘Advanced Information’’ to that of no-mark-

ing. Datasheets with no markings reflect specifi-

cations that have reached full production status.

Although the 87C196JV device is included within

this datasheet, its specifications are actually at

the design phase of development. Do not finalize

a design with this information. Revised informa-

tion will be published when the 87C196JV device

becomes available.

3. The title of the datasheet as well as the features

and design considerations list has been revised

to include the 87C196JT and 87C196JV devices.

4. Notes were added as appropriate to call out

where 87C196JV specifications are expected to

differ from those of other products listed within

this datasheet. Specifications which are expected

to differ are ICC,I

CC1,I

IDLE, and ILI and DC Input

Leakage on A/D channels.

5. The VOH2 (min) specification was supplemented

with more comprehensive IOH2 (min/max) speci-

fications.

6. A VOL3 (RESET pin only) specification was add-

ed to indicate the strength of the RESET pull-

down device.

7. All 87C196KR A-step errata was removed from

the Errata section of this datasheet.

8. For the JT, the DC input leakage (max), as speci-

fied in the previous JT datasheet (272374-002),

has been corrected to 2 mA to match the ILI

specification of 2 mA. These specifications both

specify the same parameter.

9. CerQuad package references have been re-

moved.