1
FEATURES
VCC GND
4
8
IO5
IO6
IO4
5
6
7
IO2
IO1
IO3
23
1
APPLICATIONS
DESCRIPTION/ORDERING INFORMATION
TPD6E004LOW-CAPACITANCE 6-CHANNEL ± 15-kV ESD PROTECTION ARRAYFOR HIGH-SPEED DATA INTERFACES
SLLS799A – FEBRUARY 2008 – REVISED FEBRUARY 2008www.ti.com
RSE PACKAGE2
•ESD Protection Exceeds JESD
(BOTTOM VIEW)
– ± 15-kV Human-Body Model (HBM)– ± 8-kV IEC 61000-4-2 Contact Discharge– ± 12-kV IEC 61000-4-2 Air-Gap Discharge•Low 1.6-pF IO Capacitance•0.9-V to 5.5-V Supply-Voltage Range•6-Channel Device•Space-Saving QFN (RSE) Package
•USB
•Ethernet
•FireWire
•Video
•Cell Phones•SVGA Video Connections•Glucose Metersabc
abc
The TPD6E004 is a low-capacitance ± 15-kV ESD-protection diode array designed to protect sensitive electronicsattached to communication lines. Each channel consists of a pair of diodes that steers ESD current pulses to V
CCor GND. The TPD6E004 protects against ESD pulses up to ± 15-kV Human-Body Model (HBM), ± 8-kV ContactDischarge, and ± 12-kV Air-Gap Discharge, as specified in IEC 61000-4-2. This device has a typical 1.6-pFcapacitance per channel, making it ideal for use in high-speed data IO interfaces.
The TPD6E004 is a six-channel ESD structure designed for wthernet and FireWire applications.
The TPD6E004 is available in the RSE package and is specified for – 40 °C to 85 °C operation.
ORDERING INFORMATION
T
A
PACKAGE
(1) (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
QFN – RSE– 40 °C to 85 °C 1.5 mm ×1.5 mm, Reel of 3000 TPD6E004RSER 2VPitch = 0.5 mm, Height = 0.55 mm
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
IO5 IO6
GND
IO2 IO3 IO4IO1
VCC
ABSOLUTE MAXIMUM RATINGS
(1)
TPD6E004
LOW-CAPACITANCE 6-CHANNEL ± 15-kV ESD PROTECTION ARRAYFOR HIGH-SPEED DATA INTERFACES
SLLS799A – FEBRUARY 2008 – REVISED FEBRUARY 2008
LOGIC BLOCK DIAGRAM
PIN DESCRIPTION
RSE NO. NAME FUNCTION
1-3, 5-7 IOx ESD-protected channel4 GND Ground8 V
CC
Power-supply input. Bypass V
CC
to GND with a 0.1- µF ceramic capacitor.
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
– 0.3 5.5 VV
IO
– 0.3 V
CC
+ 0.3 VT
stg
Storage temperature range – 65 150 °CT
J
Junction temperature 150 °CInfrared (15 s) 220Bump temperature (soldering) °CVapor phase (60 s) 215Lead temperature (soldering, 10 s) 300 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of thespecifications is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
2Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPD6E004
www.ti.com
ELECTRICAL CHARACTERISTICS
ESD PROTECTION
TPD6E004LOW-CAPACITANCE 6-CHANNEL ± 15-kV ESD PROTECTION ARRAYFOR HIGH-SPEED DATA INTERFACES
SLLS799A – FEBRUARY 2008 – REVISED FEBRUARY 2008
V
CC
= 5 V ± 10%, T
A
= T
MIN
to T
MAX
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
CC
Supply voltage 0.9 5.5 VI
CC
Supply current 500 nAV
F
Diode forward voltage I
F
= 1 mA 0.8 VI
I
Channel leakage current ± 1 nAV
BR
Break-down Voltage I
I
= 10 µA 6 8 VC
I/O
Channel input capacitance V
CC
= 5 V, Bias of V
CC
/2, f = 10MHz 1.6 2 pF
(1) Typical values are at V
CC
= 5 V and T
A
= 25 °C.
PARAMETER TYP UNIT
HBM ± 15 kVIEC 61000-4-2 Contact Discharge ± 8 kVIEC 61000-4-2 Air-Gap Discharge ± 12 kV
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPD6E004
www.ti.com
TYPICAL OPERATING CHARACTERISTICS
0
20
40
60
80
100
120
140
160
1.05 1.15 1.25 1.35 1.45 1.55
IO Voltage (V)
IO Current (mA)
0
10
20
30
40
50
60
70
–40 25 55 85
Temperature (°C)
Leakage Current (pA)
1 2 3 4 5
IO Voltage (V)
0.0
1.0
2.0
3.0
4.0
5.0
IO Capacitance (pF)
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0
IO Voltage (V)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
IO Current (µA)
TPD6E004
LOW-CAPACITANCE 6-CHANNEL ± 15-kV ESD PROTECTION ARRAYFOR HIGH-SPEED DATA INTERFACES
SLLS799A – FEBRUARY 2008 – REVISED FEBRUARY 2008
Figure 1. Forward Diode Voltage (Upper Clamp Diode) Figure 2. Leakage Current vs Temperature (V
IO
= 2.5 V)(V
CC
= 0 V, DC Sweep Across the IO Pin)
Figure 3. Reverse Diode Curve Current IO to GND Figure 4. IO Capacitance vs Input Voltage(V
CC
= Open) (V
CC
= 5 V)
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Product Folder Link(s): TPD6E004
www.ti.com
–20
0
20
40
60
80
100
120
140
160
180
200
220
0 25 50 75 100 125 150 175 200 225 250
Time (ns)
Amplitude (V)
TPD6E004LOW-CAPACITANCE 6-CHANNEL ± 15-kV ESD PROTECTION ARRAYFOR HIGH-SPEED DATA INTERFACES
SLLS799A – FEBRUARY 2008 – REVISED FEBRUARY 2008
TYPICAL OPERATING CHARACTERISTICS (continued)
Figure 5. IEC ESD Clamping Waveforms +8-kV Contact,Average of 10 Waveforms
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPD6E004
www.ti.com
APPLICATION INFORMATION
0.1µF
USB
Controller
RT
VBUS
D+
D–
GND
VBUS
D+
D–
GND
IO5
IO6
GND
IO2
IO3
IO4
D1
IO1
VCC
OpenOpen
Detailed Description
TPD6E004
LOW-CAPACITANCE 6-CHANNEL ± 15-kV ESD PROTECTION ARRAYFOR HIGH-SPEED DATA INTERFACES
SLLS799A – FEBRUARY 2008 – REVISED FEBRUARY 2008
When placed near the connector, the TPD6E004 ESD solution offers little or no signal distortion during normaloperation due to low IO capacitance and ultra-low leakage current specifications. The TPD6E004 ensures thatthe core circuitry is protected and the system is functioning properly in the event of an ESD strike. For properoperation, the following layout/design guidelines should be followed:1. Place the TPD6E004 solution close to the connector. This allows the TPD6E004 to take away the energyassociated with ESD strike before it reaches the internal circuitry of the system board.2. Place a 0.1- µF capacitor very close to the V
CC
pin. This limits any momentary voltage surge at the IO pinduring the ESD strike event.3. Make sure that there is enough metallization for the V
CC
and GND loop. During normal operation, theTPD6E004 consumes nA leakage current. But during the ESD event, V
CC
and GND may see 15 A to 30 A ofcurrent, depending on the ESD level. Sufficient current path enables safe discharge of all the energyassociated with the ESD strike.4. Leave the unused IO pins floating.5. The V
CC
pin can be connected in two different ways:a. If the V
CC
pin is connected to the system power supply (a 0.1- µF capacitor at V
CC
is recommended forESD bypass), the TPD6E004 works as a transient voltage suppressor for any signal swing above V
CC
+V
d
.b. If the V
CC
pin is not connected to system power supply (a 0.1- µF capacitor is still recommended at theV
CC
pin for ESD bypass), the TPD6E004 can tolerate higher signal swing in the range up to V
BR
. Notethat initially the bypass capacitor is charged by the signals through clamp diode.
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Product Folder Link(s): TPD6E004
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