testing of all parameters.
POST OFFICE BOX 655303
−
DALLAS, TEXAS 75265
1
•
Single Chip With Easy Interface Between
UART and Serial-Port Connector of IBM
PC/AT and Compatibles
GD65232, GD75232
MULTIPLE RS-232 DRIVERS AND RECEIVERS
SLLS206. − MAY 1995 − REVISED AUGUST 2012
GD65232, GD75232 . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
•
Meet or Exceed the Requirements of
TIA/EIA-232-F and ITU v.28 Standards
•
Designed to Support Data Rates up to
120 kbit/s
•
Pinout Compatible With SN75C185 and
SN75185
•
ESD Performance Tested Per JESD 22:
HBM; 1500V, CDM: 500V, MM; 200V
description/ordering information
The GD65232 and GD75232 combine three
drivers and five receivers from the
VDD 1
RA1 2
RA2 3
RA3 4
DY1 5
DY2 6
RA4 7
DY3 8
RA5 9
VSS 10
20 VCC
19 RY1
18 RY2
17 RY3
16 DA1
15 DA2
14 RY4
13 DA3
12 RY5
11 GND
Texas Instruments trade-standard SN75188 and SN75189 bipolar quadruple drivers and receivers,
respectively. The pinout matches the flow-through design of the SN75C185 to decrease the part count,
reduce the board space required, and allow easy interconnection of the UART and serial-port connector of an
IBM PC/AT and compatibles. The bipolar circuits and processing of the GD65232 and GD75232 provide a
rugged, low-cost solution for this function at the expense of quiescent power and external passive
components relative to the SN75C185.
The GD65232 and GD75232 comply with the requirements of the TIA/EIA-232-F and ITU (formerly CCITT) V.28
standards. T hese stand ard s are f or dat a interc hang e bet ween a host c om puter a nd a per ipher al at signal ing
rates up to 20 k bit/s . The switchi ng speeds of thes e dev ices are fast enough to support r at es up to 12 0 kbit/s
with lower c apacit ive loads ( shorter cables). Int erop era bilit y at the high er sign aling r ates cannot be expec ted
unless the designer has design control of the cable and the interface circuits at both ends. For interoperability
at signa ling r at es up to 120 kbit/s, use of TIA/EIA-423-B ( ITU V.10) a nd T I A/ EIA-422-B ( IT U V.11) standards
is recommended. ORDERING INFORMATION
TA PACKAGE† ORDERABLE
PART NUMBER TOP-SIDE
MARKING
−40°C to 85°C
PDIP (N) Tube of 20 GD65232N GD65232N
SOIC (DW)
Tube of 25
GD65232DW
GD65232
Reel of 2000 GD65232DWR
SSOP (DB) Reel of 2000 GD65232DBR GD65232
TSSOP (PW) Tube of 70 GD65232PW
GD65232
Reel of 2000 GD65232PWR
0°C to 70°C
PDIP (N) Tube of 20 GD75232N GD75232N
SOIC (DW)
Tube of 25
GD75232DW
GD75232
Reel of 2000 GD75232DWR
SSOP (DB)
Reel of 2000
GD75232DBR
GD75232
TSSOP (PW) Tube of 70 GD75232PW
GD75232
Reel of 2000
GD75232PWR
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at ww w.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaim ers thereto appears at the end of this data sheet.
IBM is a trademark of International Business Machines Corporation.
PRODUCTION DATA inf orma tio n
is current as of
publication date.
Products conform
to
specifications per the terms
of
Texas
Instruments
standard warranty. Production processing does not necessarily include
Copyright 2004, Texas Instruments Incorporated
SLLS206. − M AY 1995 − REVISED $8*867
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
RA1
RA2
RA3
DY1
DY2
RA4
DY3
RA5
RY1
RY2
RY3
DA1
DA2
RY4
DA3
RY5
schematic (each driver)
Output
DYx
320 Ω
68.5 Ω3.3 kΩ
10.4 kΩ
To Other Drivers
VSS
To Other
Drivers
GND
4.2 kΩ
Input
DAx
VDD
75.8 Ω
9.4 kΩ11.6 kΩ
To Other Drivers
Resistor values shown are nominal.
SLLS206. − M AY 1995 − REVISED $8*867
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematic (each receiver)
Input
RAx
10 kΩ
3.8 kΩ
9 kΩ5 kΩ1.66 kΩ
GND
Output
RYx
VCC
To Other Receivers
Resistor values shown are nominal.
2 kΩ
To Other Receivers
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage (see Note 1): VCC 10 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VDD 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VSS −15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI: Driver −15 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver −30 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Driver output voltage range, VO −15 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver low-level output current, IOL 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Notes 2 and 3): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to the network ground terminal.
2. Maximum power dissipation is a function of TJ(max), qJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/qJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
SLLS206. − M AY 1995 − REVISED $8*867
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
VDD Supply voltage (see Note 4) 7.5 9 15 V
VSS Supply voltage (see Note 4) −7.5 −9 −15 V
VCC Supply voltage (see Note 4) 4.5 5 5.5 V
VIH High-level input voltage (driver only) 1.9 V
VIL Low-level input voltage (driver only) 0.8 V
IOH
High-level output current
Driver −6
mA
I
OH
High-level output current
Receiver −0.5
mA
IOL
Low-level output current
Driver 6
mA
I
OL
Low-level output current
Receiver 16
mA
TA
Operating free-air temperature
GD65232 −40 85
°C
T
A
Operating free-air temperature
GD75232 0 70 °
C
NOTE 4: When powering up the GD65232 and GD75232, the following sequence should be used:
1. VSS
2. VDD
3. VCC
4. I/Os
Applying VCC before VDD may allow large currents to flow, causing damage to the device. When powering down the GD65232 and
GD75232, the reverse sequence should be used.
supply currents over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN MAX UNIT
VDD = 9 V, VSS = −9 V 15
All inputs at 1.9 V, No load VDD = 12 V, VSS = −12 V 19
IDD
Supply current from VDD
All inputs at 1.9 V,
No load
VDD = 15 V, VSS = −15 V 25
mA
IDD Supply current from VDD VDD = 9 V, VSS = −9 V 4.5 mA
All inputs at 0.8 V, No load VDD = 12 V, VSS = −12 V 5.5
All inputs at 0.8 V,
No load
VDD = 15 V, VSS = −15 V 9
VDD = 9 V, VSS = −9 V −15
All inputs at 1.9 V, No load VDD = 12 V, VSS = −12 V −19
ISS
Supply current from VSS
All inputs at 1.9 V,
No load
VDD = 15 V, VSS = −15 V −25
mA
ISS Supply current from VSS VDD = 9 V, VSS = −9 V −3.2 mA
All inputs at 0.8 V, No load VDD = 12 V, VSS = −12 V −3.2
All inputs at 0.8 V,
No load
VDD = 15 V, VSS = −15 V −3.2
ICC
Supply current from VCC
All inputs at 5 V,
No load,
VCC = 5 V
GD65232 38
mA
I
CC
Supply current from V
CC
All inputs at 5 V,
No load,
V
CC
= 5 V
GD75232 30
mA
SLLS206. − M AY 1995 − REVISED $8*867
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DRIVER SECTION
electrical characteristics over recommended operating free-air temperature range, VDD = 9 V,
VSS = −9 V, VCC = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage VIL = 0.8 V, RL = 3 kΩ,See Figure 1 6 7.5 V
VOL Low-level output voltage (see Note 5) VIH = 1.9 V, RL = 3 kΩ, See Figure 1 −7.5 −6 V
IIH High-level input current VI = 5 V, See Figure 2 10 µA
IIL Low-level input current VI = 0, See Figure 2 −1.6 mA
IOS(H) High-level short-circuit output current
(see Note 6) VIL = 0.8 V, VO = 0, See Figure 1 −4.5 −12 −19.5 mA
IOS(L) Low-level short-circuit output current VIH = 2 V, VO = 0, See Figure 1 4.5 12 19.5 mA
roOutput resistance (see Note 7) VCC = VDD = VSS = 0, VO = −2 V to 2 V 300 Ω
NOTES: 5. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic
levels only (e.g., if −10 V is maximum, the typical value is a more negative voltage).
6. Output short-circuit conditions must maintain the total power dissipation below absolute maximum ratings.
7. Test conditions are those specified by TIA/EIA-232-F and as listed above.
switching characteristics, VCC = 5 V, VDD = 12 V, VSS = −12 V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time,
low- to high-level output RL = 3 kΩ to 7 kΩ, CL = 15 pF, See Figure 3 315 500 ns
tPHL Propagation delay time,
high- to low-level output RL = 3 kΩ to 7 kΩ, CL = 15 pF, See Figure 3 75 175 ns
tTLH
Transition time,
RL = 3 kΩ to 7 kΩ
CL = 15 pF, See Figure 3 60 100 ns
tTLH
Transition time,
low- to high-level output RL = 3 kΩ to 7 kΩCL = 2500 pF, See Figure 3 and Note 8 1.7 2.5 µs
tTHL
Transition time,
RL = 3 kΩ to 7 kΩ
CL = 15 pF, See Figure 3 40 75 ns
t
THL
Transition time,
high- to low-level output
R
L
= 3 k
Ω
to 7 k
ΩCL = 2500 pF, See Figure 3 and Note 8 1.5 2.5 µs
NOTE 8: Measured between ±3-V and ±3-V points of the output waveform (TIA/EIA-232-F conditions); all unused inputs are tied either high
or low.
SLLS206. − M AY 1995 − REVISED $8*867
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RECEIVER SECTION
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIT+
Positive-going input threshold voltage
TA = 25°C, See Figure 5 1.75 1.9 2.3
V
VIT+ Positive-going input threshold voltage TA = 0°C to 70°C, See Figure 5 1.55 2.3 V
VIT− Negative-going input threshold voltage 0.75 0.97 1.25 V
Vhys Input hysteresis voltage (VIT+ − VIT−) 0.5 V
VOH
High-level output voltage
IOH = −0.5 mA
VIH = 0.75 V 2.6 4 5
V
VOH High-level output voltage IOH = −0.5 mA Inputs open 2.6 V
VOL Low-level output voltage IOL = 10 mA, VI = 3 V 0.2 0.45 V
VI = 25 V,
See Figure 5
GD65232 3.6 11
I
IH
High-level input current VI = 25 V, See Figure 5 GD75232 3.6 8.3 mA
IIH
High-level input current
VI = 3 V, See Figure 5 0.43
mA
VI = −25 V,
See Figure 5
GD65232 −3.6 −11
I
IL
Low-level input current VI = −25 V, See Figure 5 GD75232 −3.6 −8.3 mA
IIL
Low-level input current
VI = −3 V, See Figure 5 −0.43
mA
IOS Short-circuit output current See Figure 4 −3.4 −12 mA
†All typical values are at TA = 25°C, VCC = 5 V, VDD = 9 V, and VSS = −9 V.
switching characteristics, VCC = 5 V, VDD = 12 V, VSS = −12 V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low- to high-level output 107 250 ns
tPHL Propagation delay time, high- to low-level output
CL = 50 pF,
RL = 5 kΩ
See Figure 6
42 150 ns
tTLH Transition time, low- to high-level output
C
L
= 50 pF,
R
L
= 5 k
Ω,
See Figure 6
175 350 ns
tTHL Transition time, high- to low-level output 16 60 ns
tPLH Propagation delay time, low- to high-level output 100 160 ns
tPHL Propagation delay time, high- to low-level output
CL = 15 pF,
RL = 1.5 kΩ
See Figure 6
60 100 ns
tTLH Transition time, low- to high-level output
C
L
= 15 pF,
R
L
= 1.5 k
Ω,
See Figure 6
90 175 ns
tTHL Transition time, high- to low-level output 15 50 ns
SLLS206. − M AY 1995 − REVISED $8*867
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
IOS(L)
−IOS(H)
VSS
VDD
VCC
VI
VO
VDD or GND
VSS or GND
RL = 3 kΩ
Figure 1. Driver Test Circuit for VOH, VOL, IOS(H), and IOS(L)
−IIL
IIH
VSS
VI
VI
VDD
VCC
Figure 2. Driver Test Circuit for IIH and IIL
Pulse
Generator
See Note A CL
(see Note B)
RL
3 V
0 V
Input
tPHL tPLH
tTHL tTLH
VO
H
VO
L
TEST CIRCUIT VOLTAGE W AVEFORMS
Input
Output
VSS
NOTES: A. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns.
B. C
L
includes probe and jig capacitance.
VDD
VCC
1.5 V 1.5 V
90% 50%
10%
50%
10%
90%
Figure 3. Driver Test Circuit and Voltage Waveforms
SLLS206. − M AY 1995 − REVISED $8*867
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VI
VSS
VDD
VCC
Figure 4. Receiver Test Circuit for IOS
VIT,
VIIOL
VOH −IOH
VOL
VSS
VDD
VCC
Figure 5. Receiver Test Circuit for VIT, VOH, and VOL
Pulse
Generator
See Note A CL
(see Note B)
RL
4 V
0 V
Input
tPHL tPLH
tTHL tTLH
VO
H
VO
L
TEST CIRCUIT VOLTAGE W AVEFORMS
Input
Output
VSS
NOTES: A. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns.
B. C
L
includes probe and jig capacitance.
VDD
VCC
50% 50%
90% 50%
10%
50%
10%
90%
Figure 6. Receiver Propagation and Transition Times
SLLS206. − M AY 1995 − REVISED $8*867
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
DRIVER SECTION
Figure 7
− Output Voltage − V
VOLTAGE TRANSFER CHARACTERISTICS
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
VDD = 6 V, VSS = −6 V
VI − Input Voltage − V
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
VDD = 12 V, VSS = −12 V
ÎÎÎÎÎÎÎ
VDD = 9 V, VSS = −9 V
ÎÎÎÎ
ÎÎÎÎ
RL = 3 kΩ
TA = 25°C
VO
12
9
6
3
0
−3
−6
−9
−12 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Figure 8
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
ÎÎÎÎÎ
VOH (VI = 0.8 V)
VO − Output Voltage − V
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
VOL (VI = 1.9 V)
ÎÎÎÎÎ
ÎÎÎÎÎ
3-kΩ
Load Line
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
VDD = 9 V
VSS = −9 V
TA = 25°C
− Output Current − mAIO
20
16
12
8
4
0
−4
−8
−12
−16
−20
−16 −12 −8 −4 0 4 8 12 16
Figure 9
SHORT-CIRCUIT OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
VDD = 9 V
VSS = −9 V
VO = 0
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
IOS(H) (VI = 0.8 V)
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
IOS(L) (VI = 1.9 V)
− Short-Circuit Output Current − mAIOS
12
9
6
3
0
−3
−6
−9
−12 0 10203040506070
SLEW RATE
vs
LOAD CAPACITANCE
Figure 10
SR − Slew Rate − V/
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
VDD = 9 V
VSS = −9 V
RL = 3 kΩ
TA = 25°C
CL − Load Capacitance − pF
µs
1000
100
10
10
1100 1000 10000
SLLS20. − M AY 1995 − REVISED $8*867
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 11
INPUT THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
VIT+
VIT−
− Input Threshold Voltage − VVIT
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4 010203040506070
Figure 12
INPUT THRESHOLD VOLTAGE
vs
SUPPLY VOLTAGE
VCC − Supply Voltage − V
− Input Threshold Voltage − VVIT
VIT+
VIT−
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
02345678910
Figure 13
Amplitude − V
NOISE REJECTION
ÎÎÎÎÎ
CC = 300 pF
tw − Pulse Duration − ns
ÁÁÁÁ
ÁÁÁÁ
ÎÎÎÎÎ
ÎÎÎÎÎ
CC = 500 pF
ÁÁÁÁ
NOTE A: This figure shows the maximum amplitude of a
positive-going pulse that, starting from 0 V, does not cause
a change of the output level.
6
5
4
3
2
1
010 40 100 400 1000 4000 10000
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
VCC = 5 V
TA = 25°C
See Note A
ÎÎÎÎÎ
CC = 100 pF
ÎÎÎÎ
CC = 12 pF
Figure 14
MAXIMUM SUPPLY VOLTAGE
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
RL ≥ 3 kΩ (from each output to GND)
− Maximum Supply Voltage − VVDD
16
14
12
10
8
6
4
2
00 10203040506070
SLLS206. − M AY 1995 − REVISED $8*867
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Diodes placed in series with the VDD and V SS leads protect the GD65232 and GD75232 in the fault condition in which
the device outputs are shorted to ±15 V and the power supplies are at low and provide low-impedance paths to ground
(see Figure 15).
VDD
VSS
±15 V Output
GD65232,
GD75232 GD65232,
GD75232
VSS
VDD
Figure 15. Power-Supply Protection to Meet Power-Off Fault Conditions of TIA/EIA-232-F
GD65232,
GD75232
5 V
TL16C450
ACE −12 V
TIA/EIA-232-F
DB9S
Connector
11
12
13
14
15
16
17
18
19
20
10
9
8
7
6
5
4
3
2
1
43
37
40
13
36
11
41
42
RI
DTR
CTS
SO
RTS
SI
DSR
DCD
12 V
5
9
6
1
C3
C2
C1
GND
RY5
DA3
RY4
DA2
DA1
RY3
RY2
RY1
VCC
RA5
DY3
RA4
DY2
DY1
RA3
RA2
RA1
VDD
VSS RI
DTR
CTS
TX
RTS
RX
DSR
DCD
Figure 16. Typical Connection
PACKAGE OPTION ADDENDUM
www.ti.com 29-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
GD65232DW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
GD65232DWE4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
GD65232DWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
GD65232DWR ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
GD65232DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
GD65232DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
GD65232PWR ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
GD65232PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
GD65232PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
GD75232DBR ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
GD75232DBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
GD75232DBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
GD75232DW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
GD75232DWE4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
GD75232DWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
GD75232DWR ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
GD75232DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 29-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
GD75232DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
GD75232N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
GD75232NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
GD75232PW ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
GD75232PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
GD75232PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
GD75232PWR ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
GD75232PWRE4 ACTIVE TSSOP PW 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
GD75232PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 29-Aug-2012
Addendum-Page 3
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
GD65232DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
GD65232PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
GD75232DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
GD75232DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
GD75232PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
GD75232PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
GD75232PWRG4 TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
GD65232DWR SOIC DW 20 2000 367.0 367.0 45.0
GD65232PWR TSSOP PW 20 2000 367.0 367.0 38.0
GD75232DBR SSOP DB 20 2000 367.0 367.0 38.0
GD75232DWR SOIC DW 20 2000 367.0 367.0 45.0
GD75232PWR TSSOP PW 20 2000 367.0 367.0 38.0
GD75232PWR TSSOP PW 20 2000 364.0 364.0 27.0
GD75232PWRG4 TSSOP PW 20 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Aug-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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