LTC7840
1
Rev 0
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TYPICAL APPLICATION
FEATURES DESCRIPTION
2-Phase Dual Output
Nonsynchronous Boost Controller
with Hiccup Mode
The LT C
®
7840 is a dual phase dual output, constant fre-
quency current mode, nonsynchronous boost controller
that drives N-channel power MOSFETs. The nonsynchro-
nous topology makes the output voltage dependent on
the choice of external components.
A wide 5.5V to 60V input supply range can accommodate
high input voltage surges. The LTC7840 can be config-
ured as a dual phase single output or dual output control-
ler. It can be also configured for the SEPIC and flyback
topologies. The switching frequency is programmed by
the voltage on the FREQ pin or synchronized to an external
clock. The LTC7840 features a precise 1.2V internal refer-
ence. It has two RUN pins and two power good output
indicators.
The LTC7840 has an internal 10V LDO with undervoltage
lockout protection for its on-chip gate driver. The maxi-
mum duty cycle and blanking time can be programmed
by the voltage on D
MAX
and BLANK pins, respectively. The
hiccup mode protects the system in the event of faults.
The LTC7840 is available in a 28-lead thermally enhanced
TSSOP package (FE28) or a 28-lead QFN package (UFD28).
Efficiency vs Output Current
APPLICATIONS
n Wide VIN Range: 5.5V to 60V
n Configurable for Dual Phase Single/Dual Output
Operation
n Peak Current Mode Control with Smooth Quadratic
Slope Compensation and Dynamic Slope Recovery
n Adjustable Max Duty Cycle
n Adjustable Min On-Time
n Hiccup Mode for Overcurrent Protection
n Adjustable Current Sense Limit
n Output Overvoltage Protection
n Programmable and Phase-Lockable Operating
Frequency (from 50kHz to 425kHz)
n Adjustable Soft-Start Current Ramping
n ±1% Internal Voltage Reference
n Internal 10V LDO Regulator for Gate Driver
n Two RUN Pins and Dual Power Good Monitors
n Flexible Topology for Boost, SEPIC and Flyback
n Automotive System, Telecom System and Industrial
Power Supplies All registered trademarks and trademarks are the property of their respective owners.
RUN1
VFB1
FREQ
SS1
ITH1
INTVCC
SGND
DRVCC
PGND
LTC7840
7840 TA01a
PINS NOT SHOWN:
CLKOUT,
SYNC,
PGOOD2
1nF
0.1µF
10µF
VFB2 RUN2 PGOOD1
33nF
100pF
73.2k
12.1k 84.5k
33µF
63V
10µH
11.8k
12.1k
475k
15k
ITH2
47nF
100pF
46.4k
2.37M
SS2
BLANK
DMAX
2.2µF
2mΩ
66µF
80V
8mΩ
200µF
400V
VOUT1
48V
V
OUT
240V
0.7A
100µH
VIN
12V
GATE1
SENSE1+
ILIM1
SENSE1–
GATE2
SENSE2+
ILIM2
SENSE2–
VIN
IOUT (A)
0
EFFICIENCY (%)
94
76
74
72
92
88
84
80
90
86
82
78
70 1.00.6
7840 TA01b
1.2
0.80.40.2
VIN = 24V
VIN = 12V
VIN = 9V
VOUT = 240V
Efficiency vs Output Current
LTC7840
2
Rev 0
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PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage (VIN) ......................... –0.3V to 65V
RUN1, RUN2 Voltage .................................... –0.3V to 6V
SENSE1+, SENSE2+ Voltage ...................–0.3V to INTVCC
DMAX, BLANK Voltage ...........................–0.3V to INTVCC
PGOOD1, PGOOD2 Voltage .......................... –0.3V to 6V
VFB1, VFB2 Voltage ..............................–0.3V to INTVCC
SS1, SS2 Voltage ..................................–0.3V to INTVCC
ITH1, ITH2 Voltage ................................ –0.3V to INTVCC
(Notes 1, 2)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
FE PACKAGE
28-LEAD PLASTIC TSSOP
TJMAX = 150°C, θJA = 30°C/W
EXPOSED PAD (PIN 29) IS SGND, MUST BE SOLDERED TO PCB
28
27
26
25
24
23
22
21
20
19
18
17
16
15
BLANK
CLKOUT
SYNC
DMAX
FREQ
SS1
VFB1
ITH1
RUN1
RUN2
SS2
VFB2
ITH2
SENSE2+
SENSE1+
SENSE1–
ILIM1
INTVCC
SGND
VIN
DRVCC
GATE1
PGND
GATE2
PGOOD1
PGOOD2
ILIM2
SENSE2–
29
SGND
9 10
TOP VIEW
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
TJMAX = 150°C, θJA = 47°C/W
EXPOSED PAD (PIN 29) IS SGND, MUST BE SOLDERED TO PCB
11 12 13
28 27 26 25 24
14
23
6
5
4
3
2
1
DMAX
FREQ
SS1
VFB1
ITH1
RUN1
RUN2
SS2
INTVCC
SGND
VIN
DRVCC
GATE1
PGND
GATE2
PGOOD1
SYNC
CLKOUT
BLANK
SENSE1+
SENSE1–
ILIM1
VFB2
ITH2
SENSE2+
SENSE2–
ILIM2
PGOOD2
7
17
18
19
20
21
22
16
815
29
SGND
ILIM1, ILIM2 Voltage .............................–0.3V to INTVCC
FREQ, SYNC Voltage ............................. –0.3V to INTVCC
DRVCC Peak Output Current ................................100mA
Operating Junction Temperature Range (Note 3)
LTC7840E .......................................... –40°C to 125°C
LTC7840I ........................................... –40°C to 125°C
LTC7840H .......................................... –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
Reflow Peak Body Temperature ............................ 260°C
LTC7840
3
Rev 0
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ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC7840EFE#PBF LTC7840EFE#TRPBF LTC7840 FE 28-Lead Plastic TSSOP –40°C to 125°C
LTC7840IFE#PBF LTC7840IFE#TRPBF LTC7840 FE 28-Lead Plastic TSSOP –40°C to 125°C
LTC7840HFE#PBF LTC7840HFE#TRPBF LTC7840 FE 28-Lead Plastic TSSOP –40°C to 150°C
LTC7840EUFD#PBF LTC7840EUFD#TRPBF 7840 28-Lead Plastic (4mm × 5mm) QFN –40°C to 125°C
LTC7840IUFD#PBF LTC7840IUFD#TRPBF 7840 28-Lead Plastic (4mm × 5mm) QFN –40°C to 125°C
LTC7840HUFD#PBF LTC7840HUFD#TRPBF 7840 28-Lead Plastic (4mm × 5mm) QFN –40°C to 150°C
Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
LTC7840
4
Rev 0
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ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loops
VIN Input Voltage Range 5.5 60 V
IQInput DC Supply Current
Normal Operation
Shutdown
(Note 5)
VIN = 12V, VRUN = 2V, No Switching
VRUN = 0V
3
40
5
80
mA
µA
UVLO_DRVCC DRVCC Undervoltage Lockout Threshold DRVCC Rising
DRVCC Falling
4.4
3.9
V
V
UVLO_INTVCC INTVCC Undervoltage Lockout Threshold INTVCC Rising
INTVCC Falling
3.3
3
V
V
VFB1, VFB2 Regulated Feedback Voltage ITH1,2 Voltage = 1V (Note 6) l1.188 1.2 1.212 V
IFB1, IFB2 Feedback Current (Note 6) ±5 ±50 nA
DMAX Maximum Duty Cycle VDMAX = 0V (Note 8)
VDMAX = Float
VDMAX = INTVCC
96
84
75
%
%
%
VOVL Feedback Overvoltage Lockout Measured at VFB1, VFB2 8.5 10.5 12.5 %
VREFLNREG Reference Voltage Line Regulation VIN = 5.5V to 60V (Note 6) 0.002 0.01 %/V
VLOADREG Output Voltage Load Regulation (Note 6)
In Servo Loop; ∆ITH Voltage = 1V to 0.7V
In Servo Loop; ∆ITH Voltage = 1V to 1.3V
l
l
0.01
–0.01
0.1
–0.1
%
%
gm1, gm2 EA Transconductance ITH1,2 Voltage = 1V; Sink/Source 5µA (Note 6) 0.8 mmho
ILIM1, ILIM2 Current Limit Setting Current IILIM1,2 Voltage = 0.3V 9.5 10 10.5 µA
VITH1,
VITH2(PSKIP)
Pulse Skip Mode ITH Voltage ITH Voltage Rising (Note 6)
Hysteresis
0.5
40
V
mV
ISS1,2 Soft Start Charge Current VTK/SS1,2 = 0V 10 µA
VRUN1, VRUN2 RUN Pin On Threshold VRUN1,2 Rising l1.1 1.22 1.35 V
VRUN1,2 HYS RUN Pin ON Hysteresis 80 mV
IRUN1,2 HYS RUN Pin Current Hysteresis 4.5 µA
Current Sensing
ISENSE+ Current Sense Pin Bias Current –10 µA
ISENSE– Current Sense Pin Bias Current VITH = 1.4V –20 µA
VSENSE(MAX) Maximum Current Sense Threshold ILIM1,2 = Float l70 75 80 mV
IMISMATCH Channel-to-Channel Current Mismatch ILIM = Float 5 %
Gate Drivers
RUP1,2 Driver Pull-Up RDS(ON) GATE High 2 Ω
RDOWN1,2 Driver Pull-Down RDS(ON) GATE Low 1.0 Ω
tON(MIN)1 Minimum On-Time VBLANK = 0V (Note 7) 120 ns
tON(MIN)2 Minimum On-Time VBLANK = Float (Note 7) 160 ns
tON(MIN)3 Minimum On-Time VBLANK = INTVCC (Note 7) 200 ns
DRVCC Linear Regulator
DRVCC Internal LDO Output Voltage for Gate
Driver
12V < VIN < 60V 9.6 10 10.4 V
∆DRVCC(Load) DRVCC Load Regulation ICC = 0 to 20mA 0.5 2 %
(Notes 2, 3) The l denotes the specifications which apply over the specified
operating junction temperature range, otherwise specifications are at TA = 25°C. VIN=12V, VRUN=2V and SS1,2 = open, unless
otherwise noted.
LTC7840
5
Rev 0
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ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed in under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 3: The LTC7840E is guaranteed to meet specifications from
0°C to 85°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC7840I is guaranteed over the full –40°C to 125°C operating junction
temperature range and the LTC7840H is guaranteed over the full –40°C to
150°C operating temperature range. High junction temperature degrades
operating lifetimes. Operating lifetime is degraded at junction temperature
greater than 125°C. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors.
Note 4: The LTC7840 includes over-temperature protection that is intended
to protect the devices during momentary overload conditions. Continuous
operation above the specified maximum operating junction temperature
may impair device reliability.
Note 5: Supply current in normal operation is dominated by the current
needed to charge the external MOSFET gates. This current will vary with
the supply voltage and the external MOSFETs used. See Applications
Information.
Note 6: The LTC7840 is tested in a feedback loop that servos VITH1,2 to a
specified voltage and measures the resultant VFB1,FB2.
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current ≥30% of IMAX (see Minimum On-Time
Considerations in the Applications Information section).
Note 8: The maximum duty cycle limit is derived from an internal
clock that runs at 12x the programmed switching frequency. See the
Applications Information section for additional information.
Note 9: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
(Notes 2, 3) The l denotes the specifications which apply over the specified
operating junction temperature range, otherwise specifications are at TA = 25°C. VIN=12V, VRUN=2V and SS1,2 = open, unless
otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
INTVCC Linear Regulator
INTVCC Internal LDO Output Voltage for Control
Circuit
3.65 3.8 3.95 V
Oscillator and Phase-Locked Loop
fNOM Nominal Frequency VFREQ = 1.03V
(Note 3)
l
185
160
200
200
215
240
kHz
kHz
fRANGE Frequency Range 50 425 kHz
fSYNC SYNC Frequency Range 50 450 kHz
VSYNC SYNC Input Threshold VSYNC Rising
VSYNC Falling
1.6
0.3
V
V
Φ2 – Φ1 Channel 2 to Channel 1 Phase Delay 180 Deg
Power Good Output
VPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V
IPGOOD PGOOD Leakage Current VPGOOD = 3V 1 µA
VPG PGOOD Trip Level VFB1,FB2P with Respect to Set Output Voltage
VFB1,FB2P Ramping Up
VFB1,FB2P Ramping Down
10
–10
%
%
TDELAY VPGOOD High to Low Delay Time (Note 9) 135 µs
LTC7840
6
Rev 0
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TYPICAL PERFORMANCE CHARACTERISTICS
Output Efficiency
Dual Phase Single Output Load
Transient (0.2A to 0.8A)
(Circuit on Last Page)
Switch Node Voltage and Inductor
Current at Light Load (300mA)
Output Voltage Tracking Up and
Down with External Ramp DRVCC Line Regulation
DRVCC Load Regulation
Quiescent Current vs Input
Voltage Quiescent Current vs Temperature
IOUT (A)
0
EFFICIENCY (%)
94
76
74
72
92
88
84
80
90
86
82
78
70 1.00.6
7840 G01
1.2
0.80.40.2
VIN = 24V
VIN = 12V
VIN = 9V
VOUT = 240V
V
IN
= 12V
V
OUT
= 36V
20µs/DIV
500mA/DIV
INDUCTOR CURRENT
500mA/DIV
7840 G02
V
IN
= 12V
V
OUT
=48V
2µs/DIV
V
SW
20V/DIV
I
L
2A/DIV
7840 G03
V
IN
= 12V
R
LOAD
= 240Ω
50ms/DIV
7840 G04
SS1, SS2
1V/DIV
V
OUT1 (36V)
10V/DIV
V
OUT2 (24V)
10V/DIV
INPUT VOLTAGE (V)
5
16
27
38
49
60
0
2
4
6
8
10
12
DRV
CC
(V)
7840 G05
DRV
CC
LOAD CURRENT
0
10
20
30
40
50
60
70
80
90
100
9.95
10.00
10.05
10.10
10.15
10.20
DRV
CC
(V)
7840 G06
INPUT VOLTAGE (V)
5
16
27
38
49
60
0
1
2
3
4
5
QUIESCENT CURRENT (mA)
7840 G07
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
1
2
3
QUIESCENT CURRENT (mA)
7840 G08
LTC7840
7
Rev 0
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Shutdown Current vs Input
Voltage
TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown Current vs Temperature
DRVCC UVLO Threshold vs
Temperature
INTVCC UVLO Threshold vs
Temperature Feedback Voltage vs Temperature
Current Sense Threshold vs ITH
Voltage (ILIM Pin Float)
Current Sense Threshold vs
Temperature RUN Threshold vs Temperature
RUN Source Current vs
Temperature
INPUT VOLTAGE (V)
5
16
27
38
49
60
0
10
20
30
40
50
60
SHUTDOWN CURRENT (µA)
7840 G09
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
10
20
30
40
50
60
SHUTDOWN CURRENT (µA)
7840 G10
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
3.50
3.75
4.00
4.25
4.50
4.75
7840 G11
RISING
FALLING
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
2.8
2.9
3.0
3.1
3.2
3.3
3.4
INTV
CC
VOLTAGE (V)
7840 G12
RISING
FALLING
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
1.190
1.195
1.200
1.205
1.210
V
FB
(V)
7840 G13
ITH VOLTAGE (V)
0.7
0.8
1.0
1.1
1.2
1.3
1.4
0
25
50
75
V
SENSE
(mV)
7840 G14
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
25
50
75
100
V
SENSE
(mV)
7840 G15
ILIM = GND
ILIM = 0.3V
ILIM = INTVCC
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
1.10
1.15
1.20
1.25
1.30
V
RUN
(V)
7840 G16
RISING
FALLING
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
2
4
6
8
I
RUN
(µA)
7840 G17
RUN = 0.5V
RUN = 2V
LTC7840
8
Rev 0
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TYPICAL PERFORMANCE CHARACTERISTICS
SS Pin Pull-Down Current vs
Temperature
Switching Frequency vs
Temperature
Switching Frequency vs Input
Voltage
Switching Frequency vs FREQ Pin
Voltage
FREQ Pin Pull-Up Current vs
Temperature
ILIM Pin Pull-Up Current vs
Temperature
Minimum On-Time vs
Temperature
Hiccup Mode Overcurrent
Protection and Recovery
(1µF SS Capacitor)
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
SOFT–START PULL–DOWN CURRENT (µA)
7840 G19
FREQ = GND
FREQ = 1.03V
FREQ = INTVCC
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
100
200
300
400
500
600
7840 G20
SWITCHING FREQUENCY (kHz)
INPUT VOLTAGE (V)
5
16
27
38
49
60
0
100
200
300
400
500
SWITCHING FREQUENCY (kHz)
7840 G21
VFREQ = GND
VFREQ = 1.03V
VFREQ = INTVCC
V
FREQ
(V)
0
0.5
1
1.5
2
2.5
3
0
100
200
300
400
500
7840 G22
SWITCHING FREQUENCY (kHz)
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
9
9.5
10
10.5
11
FREQ PULL–UP CURRENT (µA)
7840 G23
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
9
9.5
10
10.5
11
ILIM PULL–UP CURRENT (µA)
7840 G24
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
50
100
150
200
250
MINIMUM ON–TIME (ns)
7840 G25
BLANK = GND
BLANK = FLOAT
BLANK = INTVCC
2s/DIV
SS
5V/DIV
V
OUT
50V/DIV
GATE
10V/DIV
ITH
2V/DIV
7840 G26
SS Pin Pull-Up Current vs
Temperature
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
9.5
9.6
9.7
9.8
9.9
10.0
10.1
10.2
SOFT–START PULL–UP CURRENT (µA)
7840 G18
LTC7840
9
Rev 0
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PIN FUNCTIONS
RUN1 (Pin 9/Pin 6): Channel 1 Run Control Input. A
voltage above 1.22V on this pin turns on the Channel 1.
However, forcing this pin below 1.14V causes the Channel
1 to shut down. There is a 1.0µA pull-up current for this
pin. Once the Run pin rises above 1.22V, an additional
4.5µA pull-up current is added to the pin.
RUN2 (Pin 10/Pin 7): Channel 2 Run Control Input. A
voltage above 1.22V on this pin turns on the Channel 2.
However, forcing this pin below 1.14V causes the Channel
2 to shut down. There is a 1.0µA pull-up current for this
pin. Once the Run pin rises above 1.22V, an additional
4.5µA pull-up current is added to the pin.
INTVCC (Pin 25/Pin 22): Internal 3.8V LDO Output. The
low voltage analog and digital circuits are powered from
this voltage. Bypass this pin to SGND with 1nF low ESR
ceramic capacitor.
ILIM1 (Pin 26/Pin 23): Channel 1 Current Comparator’s
Sense Voltage Range Input Pin. There is a precise 10µA
current flowing out of this pin. A resistor to SGND can
set the voltage on this pin to program the maximum cur-
rent sense threshold to any voltage lower than 75mV.
Alternatively, a DC voltage which is lower than 0.5V can
be added to this pin to adjust the maximum current sense
threshold. Floating this pin makes the current compara-
tor’s maximum sense voltage be 75mV.
ILIM2 (Pin 16/Pin 13): Channel 2 Current Comparator’s
Sense Voltage Range Input Pin. There is a precise 10µA
current flowing out of this pin. A resistor to SGND can
set the voltage on this pin to program the maximum cur-
rent sense threshold to any voltage lower than 75mV.
Alternatively, a DC voltage which is lower than 0.5V can
be added to this pin to adjust the maximum current sense
threshold. Floating this pin makes the current compara-
tor’s maximum sense voltage be 75mV.
DMAX (Pin 4/Pin 1): Maximum Duty Cycle. This pin pro-
grams the maximum duty cycle. Floating this pin provides
84% duty cycle. Connecting this pin to INTVCC provides
75% duty cycle, while connecting this pin to SGND pro-
vides 96% duty cycle.
VFB1 (Pin 7/Pin 4): Channel 1 Error Amplifier Feedback
Input. This pin connects to the center tap of an external
resistor divider across the Channel 1 output.
VFB2 (Pin 12/Pin 9): Channel 2 Error Amplifier Feedback
Input. This pin connects to the center tap of an external
resistor divider across the Channel 2 output.
FREQ (Pin 5/Pin 2): Oscillator Frequency Control Input.
There is a precise 10µA current flowing out of this pin. A
resistor to ground sets a voltage which in turn programs
the frequency. Alternatively, this pin can be driven with a
DC voltage to vary the frequency of the internal oscillator.
GATE1 (Pin 21/Pin 18): Channel 1 Gate Drive Output. The
LTC7840 provides a 10V gate drive referred to PGND to
drive a high voltage MOSFET.
GATE2 (Pin 19/Pin 16): Channel 2 Gate Drive Output. The
LTC7840 provides a 10V gate drive referred to PGND to
drive a high voltage MOSFET.
DRVCC (Pin 22/Pin 19): Internal 10V LDO Output. The
gate drivers are powered from this voltage. Bypass this
pin to PGND with a minimum of 4.7µF low ESR ceramic
capacitor.
ITH1 (Pin 8/Pin 5): Channel 1 Current Control Threshold
and Error Amplifier Compensation Point. Channel 1’s cur-
rent comparator’s tripping threshold increases with this
control voltage.
ITH2 (Pin 13/Pin 10): Channel 2 Current Control Threshold
and Error Amplifier Compensation Point. Channel 2’s cur-
rent comparator’s tripping threshold increases with this
control voltage.
SGND (Pin 24/Pin 21 and Exposed Pad): Signal Ground
Pin. All small-signal components and compensation com-
ponents should connect to this ground.
PGND (Pin 20/Pin 17): Power Ground Pin. Connect
this pin closely to the sources of the bottom N-channel
MOSFETs and the negative terminals of the V
IN
and DRV
CC
bypassing capacitors.
(TSSOP/QFN)
LTC7840
10
Rev 0
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PIN FUNCTIONS
BLANK (Pin 1/Pin 26): Blanking Time Pin. Floating this
pin provides a nominal minimum on-time of 160ns.
Connecting this pin to INTVCC provides a minimum on-
time of 200ns, while connecting this pin to SGND provides
a minimum on-time of 120ns.
SENSE1+ (Pin 28/Pin 25): Positive Terminal of Channel
1 Current Comparator. This pin is normally connected to
a sense resistor in series with the source of the power
MOSFET.
SENSE2+ (Pin 14/Pin 11): Positive Terminal of Channel
2 Current Comparator. This pin is normally connected to
a sense resistor in series with the source of the power
MOSFET.
SENSE1- (Pin 27/Pin 24): Negative Terminal of Channel
1 Current Comparator. This pin is normally connected to
the bottom of the sense resistor.
SENSE2- (Pin 15/Pin 12): Negative Terminal of Channel
2 Current Comparator. This pin is normally connected to
the bottom of the sense resistor.
SS1 (Pin 6/Pin 3): Soft Start Inputs. A capacitor to SGND
at this pin sets the ramp rate for Channel 1’s output volt-
age. An internal soft start current of 10µA charges this pin.
The Hiccup Mode timing is also set by this pin. At least
0.1µF capacitor is needed between this pin and SGND.
SS2 (Pin 11/Pin 8): Soft Start Inputs. A capacitor to SGND
at this pin sets the ramp rate for Channel 2’s output volt-
age. An internal soft start current of 10µA charges this pin.
The Hiccup Mode timing is also set by this pin. At least
0.1µF capacitor is needed between this pin and SGND.
SYNC (Pin 3/Pin 28): PLL Synchronization Input. Applying
an external clock between 50 kHz and 450 kHz will force
the operating frequency to synchronize to the clock. The
PLL compensation network is integrated into the IC. This
pin has an internal 100kΩ pull down resistor. An external
clock signal with amplitude greater than 1.6V is consid-
ered active high, while with amplitude less than 0.3V is
considered active low.
PGOOD1 (Pin 18/Pin 15): Power Good Indicator Output
for Channel 1. Open drain logic that is pulled to ground
when Channel 1’s output exceeds its ±10% regulation
window after the internal 135µs power bad mask timer
expires.
PGOOD2 (Pin 17/Pin 14): Power Good Indicator Output
for Channel 2. Open drain logic that is pulled to ground
when Channel 2’s output exceeds its ±10% regulation
window after the internal 135µs power bad mask timer
expires.
VIN (Pin 23/Pin 20): Main Input Supply. Bypass this pin
to PGND with a capacitor (0.1µF to 1 µF).
CLKOUT (Pin 2/Pin 27): Clock Output Pin. Clock output
used for daisy-chaining multiple LTC7840 ICs in multi-
phase systems. The phase shift from Channel 1 to Clock
Output is 90°.
(TSSOP/QFN)
LTC7840
11
Rev 0
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BLOCK DIAGRAM
7840 BD
OC
OT
UVLO1,2
DMAX
OT
UVLO1,2
SD
SD
RUN
OV
OV
UV
UV
PSKIP
PSKIP
HICCUP
BLANK
SS
ITH
DMAX
BIAS
OVER
TEMP
OSC
CLK1
CLK2
OT
UVLO1 3.8V
LDO
10V
LDO
UVLO1
UVLO2
UVLO2
DRVCC
(10V)
INTVCC
(3.8V)
GATE
VIN
(UP TO 60V) VIN
VOUT
CDRVCC
CIN
CINTVCC
L
COUT
+
ILIM
INTVCC (3.8V)
RILIM
RSENSE
SENSE–
PGOOD
SENSE+
VFB
RUN
D
M
LOGIC
BLANK
LOGIC
SYNC
DETECT
PLL-SYNC
BLOGIC
BLOGIC RUN
10µA
INTERNAL
(4.5V)
1µA/5.5µA
INTVCC (3.8V)
10µA
1.25µA
OV
PSKIP
SS
ILIM
ADJUSTMENT
ACTIVE
CLAMP
SLOPE
COMPENSATION
7.5k
7.5k
+
–
+–
ITRIP
ICMP
V TO I
+–
1.32V
+–
1.22V
1.08V
+ + –
1.2V
+–
0.5V
PGND
SGND
PWM LATCH
EA
R1
R2
RC
CC
CSS
CLKOUT
FREQ
SYNC
RFREQ
START-UP
QR1
R2
S*
* DUPLICATE FOR SECOND CHANNEL
LTC7840
12
Rev 0
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OPERATION
The Control Loop
The LTC7840 is a constant frequency, current mode,
boost controller with two channels operating 180º out-of-
phase. During normal operation, each external MOSFET
is turned on when the clock for that channel sets the RS
latch, and turned off when the main current comparator,
ICMP, resets the RS latch. The peak inductor current at
which ICMP resets the RS latch is controlled by the volt-
age on the ITH pin, which is the output of each error ampli-
fier EA. The error amplifier compares the output feedback
signal at the VFB pin to the internal 1.2V reference and
generates an error signal at the I
TH
pin. When the load cur-
rent increases, it causes a slight decrease in the feedback
relative to the 1.2V reference, which in turn causes the
ITH voltage to increase until the average inductor current
matches the new load current. After the MOSFET is turned
off, the inductor current flows through the boost diode
into the output capacitor and load, until the beginning of
the next clock cycle.
Cascaded LDOs Supply Power to the Gate Driver and
Control Circuitry
The LTC7840 contains two cascaded PMOS output stage
low dropout regulators (LDOs), one for the gate driver
Figure1. Cascaded LDOs Provide Gate Driver and Control Circuitry Power
supply (DRVCC) and one for the low voltage analog and
digital control circuitry (INTVCC). A block diagram of this
power supply architecture is shown in Figure1.
The output of either LDO cannot be biased from external
power supply. Otherwise, two possible failure modes will
be caused. As shown in Figure1, there are body diodes
in parallel with the PMOS output transistors in the two
LDO regulators. If the DRV
CC
or INTV
CC
supply comes
up before the VIN supply, high current will flow from the
external DRVCC or INTVCC supply through the body diode
to the input capacitor and VIN pin. This high current flow
could cause catastrophic failure of the IC.
If the VIN supply comes up before the DRVCC or INTVCC
supply, or if the DRVCC or INTVCC pins are biased to any
voltage lower than the regulated voltage by low-imped-
ance voltage sources, the LDO will attempt to pull up its
output voltage and this current will result in excessive
power dissipation and possible thermal overload of the
LTC7840.
Also, in multi-chip parallel applications, the output pins
of LDOs should not be connected together. When two
or more LDO outputs are tied together, the highest volt-
age regulator supplies all of the gate driver and control
–
+
SGND
R2 R1
1.218V
LTC7840
INTVCC
INTVCC
GATE
–
+
SGND
R4 R3
1.218V
P-CH
P-CH
ANALOG
CIRCUITS LOGIC
DRVCC
VIN
CIN
CDRVCC
CINTCC
7840 F01
PGND
INTVCC
SGND
NOTE: PLACE CDRVCC AND CINTVCC CAPACITORS AS CLOSE AS POSSIBLE TO DEVICE PINS
LTC7840
13
Rev 0
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circuit current, but the other regulators are off. This would
place a thermal burden on the highest output voltage LDO
and could cause the maximum die temperature to be
exceeded. In multi-chip parallel applications, each LDO
output should be independently bypassed to its respective
GND pin as close as possible to each IC.
The Gate Driver Supply LDO (DRVCC)
The 10V output (DRVCC) of the first LDO is powered from
VIN and supplies power to the power MOSFET gate driv-
ers. The DRVCC pin should be bypassed to PGND with
a minimum of 4.7µF ceramic capacitor (X5R or better)
placed as close as possible to the IC pin. If two power
MOSFETs are connected in parallel for each channel in
order to increase the output power level, or if a single
MOSFET with a Qg greater than 50nC is used, then it is
recommended that the bypass capacitor be increased to
a minimum of 10µF.
An under voltage lockout (UVLO) circuit senses the DRV
CC
regulator output in order to protect the power MOSFETs
from operating with the inadequate gate drive. For the
LTC7840, the rising UVLO threshold is 4.4V and the hys-
teresis is typically 500mV. In low VIN applications, the
low threshold MOSFET (<3.5V) may be used. In high VIN
applications, higher UVLO may be programmed as shown
in Figure5. The LTC7840 is optimized for high voltage
power MOSFETs with RDS(ON) ratings at a VGS of 6V.
The Low Voltage Analog and Digital Supply LDO
(INTVCC)
The second LDO within the LTC7840 is powered from
DRV
CC
and serves as the supply to the low voltage analog
and digital control circuitry. The output (INTVCC) voltage
of this LDO is 3.8V. The INTVCC pin should be bypassed to
SGND with a 1nF ceramic capacitor (X5R or better) placed
as close as possible to the IC pin. This LDO is not intended
to be used as a supply for external circuitry.
Thermal Considerations and Package Options
The LTC7840 is offered in two package options. The
28-lead thermally enhanced TSSOP package (FE28) has a
thermal resistance RTH(JA) of 30ºC/W, and the 4mm x 5mm
28-lead QFN package (UFD28) has a thermal resistance of
47ºC/W. The TSSOP package has a lead pitch of 0.65mm,
whereas the QFN package has a lead pitchof0.5mm.
The DRVCC LDO can supply up to 100mA current. As a
result, care must be taken to ensure that the maximum
junction temperature of the IC should not be exceeded.
The junction temperature can be estimated by the follow-
ing equations:
IQ(TOT) = IQ + QG(TOT) • f
PDISS = VIN • (IQ + QG(TOT) • f
TJ = TA + PDISS • RTH(JA)
The total quiescent current (IQ(TOT)) consists of the static
supply current (IQ) and the current required to charge
the gate capacitance of the power MOSFETs. The value
of Q
G(TOT)
should come from the plot of V
GS
vs Q
G
in
the Typical Performance Characteristics section of the
MOSFET data sheet. The value listed in the electrical
specifications may be measured at a higher VGS, such as
15V, whereas the value of interest is at the 10V DRVCC
gate drive voltage.
As an example of the required thermal analysis, consider a
2-phase boost converter with a 5.5V to 24V input voltage
range and an output voltage of 72V at 1.5A. The switching
frequency is 150kHz and the maximum ambient tempera-
ture is 70°C. The power MOSFET used for this application
is the Renesas HAT2267H, which has a typical RDS(ON)
of 13mΩ at VGS = 10V. From the plot of VGS vs QG, the
total gate charge at VGS = 10V is 30nC (the temperature
coefficient of the gate charge is low). One power MOSFET
is used for each phase. For the QFN package option:
IQ(TOT) = 3mA + 2 • 30nC • 150kHz = 12mA
PDISS = 24V • 12mA = 288mW
TJ = 70°C + 288mW • 30°C/W = 78.64°C
In this example, the junction temperature rise is only
8.64°C. These equations demonstrate how the gate
charge current typically dominates the quiescent current
of the IC, and how the choice of package option and board
heat sinking can have a significant effect on the thermal
performance of the solution.
OPERATION
LTC7840
14
Rev 0
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To prevent the maximum junction temperature from being
exceeded, the input supply current to the IC should be
checked when operating in continuous mode (heavy
load) at maximum VIN. A trade-off between the operat-
ing frequency and the size of the power MOSFETs may
need to be made in order to maintain a reliable junction
temperature. As an option, an external regulator shown in
Figure3 can be used to reduce the total power dissipation
on the IC. Finally, it is important to verify the calculations
by performing a thermal analysis of the final PCB using
an infrared camera or thermal probe.
Thermal Shutdown Protection
In the event of an overtemperature condition (external
or internal), an internal thermal monitor will shut down
the gate drivers and reset the soft-start capacitor if the
die temperature exceeds 170°C. This thermal sensor has
a hysteresis of 10°C to prevent erratic behavior at hot
temperatures. The LTC7840’s internal thermal sensor is
intended to protect the device during momentary over-
temperature conditions. Continuous operation above the
specified maximum operating junction temperature, how-
ever, may result in device degradation.
Operation at Low Supply Voltage
The LTC7840 has a minimum input voltage of 5.5V, mak-
ing it a good choice for applications that require high
voltage power MOSFETs with 6V R
DS(ON)
ratings. The gate
driver for the LTC7840 consists of PMOS pull-up and
NMOS pull-down devices, allowing the full DRV
CC
voltage
to be applied to the gates during power MOSFET switch-
ing. Nonetheless, care should be taken to determine the
minimum gate drive supply voltage (DRVCC) in order to
choose the optimum power MOSFETs. Important param-
eters that can affect the minimum gate drive voltage are
the minimum input voltage (VIN(MIN)), the LDO dropout
voltage, the QG of the power MOSFETs, and the operating
frequency.
If the input voltage VIN is low enough for the DRVCC LDO
to be in dropout, then the minimum gate drive supply
voltage is:
VDRVCC = VIN(MIN) – VDROPOUT
The LDO dropout voltage is a function of the total gate
drive current and the quiescent current of the IC (typically
3mA). A curve of dropout voltage vs output current for
the LDO is shown in Figure2.
The total Q-current (IQ(TOT)) flowing in the LDO is the sum
of the controller quiescent current (3mA) and the total
gate charge drive current.
IQ(TOT) = IQ + QG(TOT) • f
After the calculations have been completed, it is impor-
tant to measure the gate drive waveforms and the gate
driver supply voltage (DRVCC to PGND) over all operating
conditions (low VIN, nominal VIN and high VIN, as well
as from light load to full load) to ensure adequate power
MOSFET enhancement. Consult the power MOSFET data
sheet to determine the actual RDS(ON) for the measured
VGS, and verify your thermal calculations by measuring
the component temperatures using an infrared camera
or thermal probe.
Figure2.
–40°C
25°C
85°C
150°C
125°C
DRV
CC
LOAD (mA)
0
10
20
30
40
50
0
100
200
300
400
500
600
700
800
900
1000
DROPOUT VOLTAGE (mV)
7840 F02
DRVCC LDO Dropout Voltage vs Current
OPERATION
LTC7840
15
Rev 0
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Operation at High Supply Voltage
At high input voltages, the LTC7840’s internal LDO can
dissipate a significant amount of power, which could
cause the maximum junction temperature to be exceeded.
Conditions such as a high operating frequency, or the use
of more than one power MOSFET per channel, could push
the junction temperature rise to high levels. If the thermal
equations above indicate too high a rise in the junction
temperature, an external bias supply can always be used
to reduce the power dissipation on the IC, as shown in
Figure3.
For example, a 12V system rail that is available would be
more suitable than the 24V main input power rail to power
the LTC7840. Also, the bias power can be generated with
a separate switching or LDO regulator. An example of an
LDO regulator is shown in Figure3. The output voltage
of the LDO regulator can be set by selecting an appropri-
ate zener diode to be higher than 10V but low enough to
divide the power dissipation between LTC7840 and Q1
in Figure3.
Figure3.
VIN
R1
Q1
D1
CDRVCC
7840 F03
LTC7840
VIN
DRVCC
Using the LTC7840 with an External Bias Supply
Programming the Output Voltage
The output voltage is set by a resistor divider according
to the following formula:
VOUT =1.2V 1+R2
R1
⎛
⎝
⎜⎞
⎠
⎟
The external resistor divider is connected to the output
as shown in Figure4. Resistor R1 is normally chosen so
OPERATION
that the output voltage error caused by the current flowing
out of the VFB pin during normal operation is negligible
compared to the current in the divider. For an output volt-
age error due to the error amp input bias current of less
than 0.5%, this translates to a maximum value of R1 of
about 30k.
Figure4.
LTC7840
FB
SGND
R2
R1
7840 F04
VOUT
Programming the Output Voltage with a
Resistor Divider
Shutdown and Start-Up
(RUN1, RUN2 and SS1, SS2 Pins)
The two channels of the LTC7840 can be independently
shut down using the RUN1 and RUN2 pins. Pulling either
of these pins below 1.14V shuts down the main control
loop for that channel. Pulling both pins low disables both
channels and most internal circuits, including the DRVCC
and INTVCC regulator. Releasing either RUN pin allows
an internal 1µA current to pull up the pin and enable the
controller. Alternatively, the RUN pins may be externally
pulled up or driven directly by logic. Be careful not to
exceed the absolute maximum rating of 6V on these pins.
Thirdly, the RUN1 and RUN2 pins can also be used to
detect VIN undervoltage condition. The circuit shown in
Figure5 provides an example. When the voltage on either
RUN pin exceeds 1.22V, the pull up current is switched
from 1µA to 5.5µA to provide some hysteresis. The user
can program both the rising threshold and the amount
of hysteresis by adjusting the values of the resistors in
the external divider, as shown in the following equations:
VIN ON
( )
=1.22V 1+
R
A
RB
⎛
⎝
⎜⎞
⎠
⎟–1µA •RA
VIN OFF
( )
=1.22V 1+RA
RB
⎛
⎝
⎜⎞
⎠
⎟– 5.5µA •RA
LTC7840
16
Rev 0
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OPERATION
Figure5.
–
+
RUN
COMPARATOR
1.22V
7840 F05
VIN LTC7840
RUN
10V
INTERNAL 4.5V
1µA
RA
4.5µA
SGND
BIAS AND
START-UP
CONTROL
RB
Programming the Input Voltage Turn-On
and Turn-Off Thresholds Using the RUN Pin
The start-up of each channel’s output voltage, VOUT, is
controlled by the voltage on its SS pin. When the voltage
on the SS pin is less than the 1.2V internal reference, the
LTC7840 regulates the VFB voltage to the SS pin voltage
instead of the 1.2V reference. This allows the SS pin to
be used to program the soft-start period by connecting
an external capacitor from the SS pin to SGND. An inter-
nal 10µA pull-up current charges this capacitor, creating
a voltage ramp on the SS pin. As the SS voltage rises
linearly from 0V to 1.2V (and beyond), the output volt-
age VOUT rises smoothly from zero to its final value. The
soft-start-up time can be estimated by:
1.2V
10µA
tSTART-UP = CSS •
= 0.12 • CSS
The SS pin has an internal open-drain NMOS pull-down
transistor that turns on when the RUN pin is pulled low,
when the voltage on the INTVCC pin or DRVCC pin is below
its undervoltage lockout threshold, or during an overtem-
perature condition.
Frequency Selection and Phase-Locked Loop
(FREQ and SYNC Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage. The switching fre-
quency of the LTC7840’s controller can be selected using
the FREQ pin. If the SYNC pin is not being driven by an
external clock source, the FREQ pin can be used to pro-
gram the controller’s operating frequency from 50kHz to
425kHz. There is a precision 10µA current flowing out of
the FREQ pin, so the user can program the controller’s
switching frequency with a single resistor to SGND. The
curve in Figure6 shows the relationship between the volt-
age on the FREQ pin and switching frequency.
A phase-locked loop (PLL) is integrated on the LTC7840
to synchronize the internal oscillator to an external clock
source that is connected to the SYNC pin. The PLL loop
filter network is also integrated inside the LTC7840. The
phase-locked loop is capable of locking to any frequency
within the range of 50kHz to 450kHz. The frequency set-
ting resistor should always be present to set the control-
ler’s initial switching frequency to the same value as the
synchronized frequency before locking to the external
clock. The lock-in time can be minimized by this way. It
also ensures that the operating frequency remains essen-
tially constant in the event the sync signal is lost. The
SYNC pin has an internal 100k resistor to ground.
Figure6.
V
FREQ
(V)
0
0.5
1
1.5
2
2.5
3
0
100
200
300
400
500
OSCILLATOR FREQUENCY (kHz)
7840 F06
Switching Frequency vs FREQ Pin Voltage
Power Good (PGOOD1, PGOOD2 Pins)
When either feedback voltage is not within ±10% of the
1.2V reference voltage, its respective PGOOD pin is pulled
low. A PGOOD pin will also pull low when its channel is in
the soft-start or UVLO. Both PGOOD pins pull low when
LTC7840
17
Rev 0
For more information www.analog.com
OPERATION
the RUN pin is below 1.14V. The PGOOD pins will flag
power good immediately when their feedback voltages
are within ±10% of the reference window. However, there
is an internal 135µs power bad mask when feedback volt-
ages go out of the ±10% window. The PGOOD pins are
allowed to be pulled up by external resistors to sources
of up to 6V.
Multichip Operations (CLKOUT Pin)
The LTC7840 uses CLKOUT pin to allow multiple ICs to
be daisy-chained together for higher current multi-phase
applications. For a 4-phase design, the CLKOUT signal
of the master controller is connected to the SYNC input
of the slave controller in order to synchronize additional
power stages for a single high current output. Input
capacitance ESR requirements and efficiency losses are
substantially reduced because the peak current drawn from
the input capacitor is effectively divided by the number of
phases used, and power loss is proportional to the RMS
current squared. A two stage, single output voltage imple-
mentation can reduce input path power loss by 75% and
radically reduce the required RMS current rating of the input
capacitor(s).
In LTC7840, Channel 1 and Channel 2 have 180º phase
shift, whereas, CLKOUT signal has 90º phase shift relative
to Channel 1. The duty cycle of CLKOUT signal is 50%.
Using the LTC7840 Transconductance (gm) Error
Amplifier in Multi-Phase Applications
The LTC7840 error amplifier is a transconductance, or g
m
amplifier, meaning that it has high DC gain but high output
impedance (the output of the error amplifier is a current
proportional to the differential input voltage). This style
of error amplifier greatly eases the task of implement-
ing a multi-phase solution, because the amplifiers from
two or more chips can be connected in parallel. In this
case the FB pins of multiple LTC7840s can be connected
together, as well as the ITH pins, as shown in Figure7. The
gm of the composite error amplifier is simply n times the
transconductance of one amplifier, or gm(TOT) = n • 800μS,
where n is the number of amplifiers connected in paral-
lel. The transfer function from the ITH pin to the current
comparator inputs was carefully designed to be accurate,
both from channel-to-channel and chip-to-chip. This way
the peak inductor current matching is kept accurate.
Figure7.
FREQ
VFB1
VFB2
CLKOUT
SYNC
LTC7840
MASTER
SGND
ITH
VOUT
DRVCC
SS1
SS2
RUN1
RUN2
ON/OFF
CONTROL
ALL RUN PINS
CONNNECTED
TOGETHER
INDIVIDUAL
DRVCC PINS
LOCALLY
DECOUPLED
FREQ
VFB1
VFB2
†
†
CLKOUT
SYNC
LTC7840
SLAVE
SGND
ITH
DRVCC
SS1
SS2
RUN1
RUN2
7840 F06
ALL SS PINS
CONNNECTED
TOGETHER
ALL FB PINS
CONNECTED
TOGETHER
ALL ITH PINS
CONNECTED
TOGETHER
* R = 100Ω
† CX = 100pF
**
LTC7840 Error Amplifier Configuration for Multi-Phase Operation
LTC7840
18
Rev 0
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OPERATION
A buffered version of the output of the error amplifier
determines the threshold at the input of the current com-
parator. The ITH voltage that represents zero peak current
is 0.7V and the voltage that represents current limit is
from 1.4V (at zero duty cycle) to 2.1V (at 100% duty
cycle). There is a circuit in the LTC7840 to recover the
slope compensation signal, so that the maximum peak
inductor current keeps constant over the duty cycle.
In multi-phase applications that use more than one
LTC7840 controller, it is possible for ground currents on
the PCB to disturb the control lines between the ICs, result-
ing in erratic behavior. In these applications the FB pins
should be connected to each other through 100Ω resis-
tors and each slave FB pin should be decoupled locally
with a 100pF capacitor to ground, as shown inFigure7.
Pulse-Skipping Operation at Light Load
As the load current decreases, the loop will make the ITH
voltage drop and the peak inductor current will reduce
accordingly. If the load current keeps decreasing, the
controller will enter discontinuous mode (DCM) auto-
matically. The peak inductor current can reduce until the
minimum on-time of the controller is reached. Any further
decrease in the load current will cause ITH voltage to con-
tinue going down until it reaches 0.5V, then the controller
will enter pulse-skipping mode in order to maintain output
regulation. The internal pulse-skip-mode comparator has
a 50mV hysteresis.
Programmable Blanking and the Minimum On-Time
The BLANK pin on the LTC7840 allows the user to pro-
gram the amount of leading edge blanking at the SENSE
pins. Connecting the BLANK pin to SGND results in a
minimum on-time of 120ns, floating the pin increases
this time to 160ns, and connecting the BLANK pin to the
INTVCC supply results in a minimum on-time of 200ns.
The majority of the minimum on-time consists of this
leading edge blanking, due to the inherently low propaga-
tion delay of the current comparator and logic circuitry.
The purpose of leading edge blanking is to filter out
noise on the SENSE pins at the leading edge of the
power MOSFET turn-on. During the turn-on of the power
MOSFET the gate drive current, the discharge of any para-
sitic capacitance on the SW node, the recovery of the
boost diode charge, and parasitic series inductance in
the high di/dt path all contribute to overshoot and high
frequency noise that could cause false-tripping of the
current comparator. Due to the wide range of LTC7840
applications, fixing one value of the internal leading edge
blanking time would have required the longest delay time
to have been used. Providing a means to program the
blank time allows users to optimize the SENSE pin filtering
for each application. Figure8 illustrates the effect of the
programmable leading edge blank time on the minimum
on-time of a boost converter.
Programmable Maximum Duty Cycle
In order to maintain constant frequency and a low output
ripple voltage, a single-ended boost (or flyback or SEPIC)
converter is required to turn off the switch every cycle
for some minimum amount of time. This off-time allows
the transfer of energy from the inductor to the output
capacitor and load, and prevents excessive ripple current
and voltage. For inductor-based topologies like boost and
SEPIC converters, having a maximum duty cycle as close
as possible to 100% may be desirable, especially in low
VIN to high VOUT applications. However, for transformer-
based solutions, having a maximum duty cycle near 100%
is undesirable, due to the need for V • sec reset during the
primary switch off-time.
In order to satisfy these different applications require-
ments, the LTC7840 has a simple way to program the
maximum duty cycle. Connecting the DMAX pin to SGND
limits the maximum duty cycle to 96%. Floating this pin
limits the duty cycle to 84% and connecting the DMAX pin
to INTVCC limits the duty cycle to 75%. Figure9 illustrates
the effect of limiting the maximum duty cycle on the SW
node waveform of a boost converter.
The LTC7840 contains an oscillator that runs at 12× the
programmed switching frequency. A digital counter is
used to divide down the fundamental oscillator frequency.
Since the maximum duty cycle limit is obtained from this
digital counter, the percentage maximum duty cycle does
not vary with process tolerances or temperature.
LTC7840
19
Rev 0
For more information www.analog.com
Figure8. Leading Edge Blanking Effects
on the Minimum On-Time
Figure9. SW Node Waveforms with Different Duty Cycle Limits
500ns/DIV
MINIMUM ON-TIME AT LIGHT LOAD WITH BLANK = SGND
VIN = 24V
VOUT = 48V
VIN = 24V
VOUT = 48V
VIN = 24V
VOUT = 48V
500ns/DIV
MINIMUM ON-TIME AT LIGHT LOAD WITH BLANK = FLOAT
500ns/DIV 7840 F08
MINIMUM ON-TIME AT LIGHT LOAD WITH BLANK = INTVCC
SW
50V/DIV
GATE
5V/DIV
I
L
500mA/DIV
SW
50V/DIV
GATE
5V/DIV
I
L
500mA/DIV
SW
50V/DIV
GATE
5V/DIV
I
L
500mA/DIV
SW NODE
20V/DIV
SW NODE
20V/DIV
1µs/DIV
96% MAXIMUM DUTY CYCLE WITH D
MAX
= SGND
INDUCTOR
CURRENT
1A/DIV
1µs/DIV
84% MAXIMUM DUTY CYCLE WITH DMAX = FLOAT
INDUCTOR
CURRENT
1A/DIV
SW NODE
20V/DIV
INDUCTOR
CURRENT
1A/DIV
1µs/DIV 7840 F09
75% MAXIMUM DUTY CYCLE WITH DMAX = INTVCC
OPERATION
LTC7840
20
Rev 0
For more information www.analog.com
OPERATION
The SENSE+ and SENSE– Pins
Since the LTC7840 contains leading edge blanking, an
external RC filter is not required for proper operation.
However, if an external filter is used, the filter components
should be placed close to the SENSE+ and SENSE– pins
on the IC, as shown in Figure10. The positive and nega-
tive sense node traces should then run parallel to each
other to a Kelvin connection underneath the sense resis-
tor, as shown in Figure11. Sensing current elsewhere on
the board can add parasitic inductance and capacitance
to the current sense element, degrading the information
at the sense pins and making the programmed current
limit unpredictable. Avoid the temptation to connect the
SENSE– line to the ground plane using a PCB via; this
could result in unpredictable behavior.
The sense resistor should be connected to the source
of the power MOSFET and the ground node using short,
wide PCB traces, as shown in Figure11. Ideally, the bot-
tom terminal of the sense resistors will be immediately
adjacent to the negative terminal of the output capacitor,
since this path is a part of the high di/dt loop formed by
the switch, boost diode, output capacitor and sense resis-
tor. Placement of the inductors is less critical, since the
current in the inductors is a triangle waveform.
Figure10.
SENSE–
SENSE+
LTC7840
GATE
VOUT
RSENSE
7840 F10
FILTER COMPONENTS
PLACED NEAR
SENSE PINS
VIN
PGND
DRVCC
VIN
Proper Current Sense Filter Component Placement
Figure11.
MOSFET SOURCE
TO SENSE
FILTER NEXT
TO CONTROLLER
RSENSE
GND
7840 F11
Connecting the SENSE+ and SENSE– Traces
to the Sense Resistor Using a Kelvin Connection
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>10%) as well as other more serious condi-
tions that may overvoltage the output. In such cases, the
external power MOSFET is turned off until the overvoltage
condition is cleared.
Overcurrent Protection
(ILIM1, ILIM2 Pins and Hiccup Mode)
The LTC7840 has ILIM1 and ILIM2 pins to set the maxi-
mum inductor current limit of each channel respectively,
as described in the ILIM1 and ILIM2 pins function. The
voltage on each ILIM pin is used to generate the internal
ITH clamp voltage. Along with the increase of load cur-
rent, ITH voltage will rise to allow higher inductor current
flowing to the load. If the load current keeps increasing,
the ITH voltage will finally reach the clamp voltage and
the inductor current cannot go up any more. This situa-
tion is thought as an overcurrent event by the controller.
If this event lasts for 16 continuous switching periods,
the controller will enter hiccup mode. The ITH voltage is
pulled down to GND and the external power MOSFET is
turned off. The inductor current will gradually reduce to
zero. At this moment, the soft-start capacitor connected
LTC7840
21
Rev 0
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between the SS pin and SGND is discharged by a 1.25µA
current. When the voltage on SS pin reaches 0V, the ITH
pin is released and the controller retries to soft-start, as
described in the Shutdown and Start-Up section. The
hiccup mode is disabled during the soft-start period. To
realize the function of the hiccup mode, a minimum 0.1µF
soft-start capacitor has to be connected between the SS
pin and SGND. The sleep time can be estimated by:
1.5V
1.25µA
tSLEEP = CSS • = 1.2 • CSS
Compared with the start-up time estimated in the
Shutdown and Start-Up section, the sleep time is roughly
10 times the start-up time.
If the overcurrent situation is removed continuously for
two or more switching periods before the 16 switching
period timer expires, the 16 switching period timer will
reset to zero and the output will soft recover by using the
internal soft-start, thus reducing output overshoot. In the
absence of this feature, the output capacitors would have
been charged at current limit, and in applications with
minimal output capacitance, this may have resulted in
output overshoot.
Figure12.
2s/DIV
SS
5V/DIV
V
OUT
50V/DIV
GATE
10V/DIV
ITH
2V/DIV
7840 F12
Hiccup Mode Overcurrent Protection and Recovery
OPERATION
LTC7840
22
Rev 0
For more information www.analog.com
The LTC7840 is a dual-phase constant frequency current
mode nonsynchronous step-up controller. This topology
makes the output voltage not limited by the IC voltage.
The LTC7840 can be configured in many ways as:
• a dual-phase dual-output boost converter with each
phase operating independently;
• a dual-phase dual-output boost converter with one
phase’s output connected to the other phase’s input.
As a result of this two-step-up configuration, a much
higher output voltage can be obtained;
• a dual-phase single-output boost converter;
• SEPIC topology;
• Other applications.
A wide 5.5V to 60V input voltage range can accommo-
date high input voltage surges. With the selectable lead-
ing edge blanking time, the noise on the SENSE pins at
the leading edge of the power MOSFET turn-on is filtered
out maximally. The programmable maximum duty cycle
provides the flexibility to the user for configuring different
topologies with LTC7840. The maximum current limit can
be adjusted by the user based on the sense resistor value.
For light load application, once ITH drops below 0.5V,
the controller is forced to skip cycles to maintain output
regulation. Each channel of the LTC7840 has a power
good indicator output to reflect if this channel’s output
voltage is within the regulation window. The LTC7840 can
be configured for single-phase, dual-phase and 4-phase
operation. The SYNC pin allows the IC to be synchro-
nized to an external clock. Without the external clock, the
switching frequency of the controller can be set by the
voltage on the FREQ pin. The LTC7840 provides overcur-
rent protection by the hiccup mode. The controller also
has output overvoltage protection.
In general, the external component selection is driven by
the characteristics of the load and the input supply. Next,
power MOSFETs are selected. Finally, input and output
capacitors are selected.
APPLICATIONS INFORMATION
Duty Cycle Considerations
For a boost converter operating in a continuous conduc-
tion mode (CCM), the duty cycle of the main switch is:
D=VO+VF– VIN
VO+VF
⎛
⎝
⎜⎞
⎠
⎟=tON • f
where VF is the forward voltage of the boost diode. The
minimum on-time for a given application operating in
CCM is:
tON(MIN) =1
f
VO+VF– VIN(MAX)
VO+VF
⎛
⎝
⎜⎞
⎠
⎟
For a given input voltage range and output voltage, it is
important to know how close the minimum on-time of the
application comes to the minimum on-time of the control
IC. The LTC7840 minimum on-time can be programmed
from 120ns to 200ns using the BLANK pin.
Minimum On-Time Limitations
In a boost converter, two steady-state conditions can
result in operation at the minimum on-time of the con-
troller. The first condition is when the input voltage is
close to the output voltage. When VIN approaches VOUT
the voltage across the inductor approaches zero during
the switch off-time. Under this operating condition the
converter can become unstable and the output can experi-
ence high ripple voltage oscillation at audible frequencies.
For applications where the input voltage can approach
or exceed the output voltage, consider using a SEPIC or
buck-boost topology instead of a boost converter.
The second condition that can result in operation at the
minimum on-time of the controller is at light load, in deep
discontinuous mode. As the load current is decreased, the
on-time of the switch decreases, until the minimum on-
time limit of the controller is reached. Any further decrease
in the output current will result in pulse-skipping, a typi-
cally benign condition where cycles are skipped in order
to maintain output regulation.
LTC7840
23
Rev 0
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Maximum Duty Cycle Limitations
Another operating extreme occurs at high duty cycle,
when the input voltage is low and the output voltage is
high. In this case:
DMAX =
V
O
+V
F
– V
IN(MIN)
VO+VF
⎛
⎝
⎜
⎞
⎠
⎟
A single-ended boost converter needs a minimum off-
time every cycle in order to allow energy transfer from
the input inductor to the output capacitor. This minimum
off-time translates to a maximum duty cycle for the con-
verter. The equation above can be rearranged to obtain
the maximum output voltage for a given minimum input
or maximum duty cycle.
VO(MAX) =
V
IN
1– DMAX
– VF
The equation for D
MAX
above can be used as an initial
guideline for determining the maximum duty cycle of the
application circuit. However, losses in the inductor, input
and output capacitors, the power MOSFETs, the sense
resistors and the controller (gate drive losses) all contrib-
ute to an increasing of the duty cycle. The effect of these
losses will be to decrease the maximum output voltage
for a given minimum input voltage.
After the initial calculations have been completed for an
application circuit, it is important to build a prototype of
the circuit and measure it over the entire input voltage
range, from light load to full load, and over temperature,
in order to verify proper operation of the circuit.
Peak and Average Input Currents
The control circuit in the LTC7840 measures the input
current (by means of resistors in the sources of the power
MOSFETs), so the output current needs to be reflected
back to the input in order to dimension the power
MOSFETs properly. Based on the fact that, ideally, the
output power is equal to the input power, the maximum
average input current is:
IIN(MAX) =
I
O(MAX)
1– D
MAX
The peak current in each inductor is:
IIN(PK) =1
n• 1+χ
2
⎛
⎝
⎜⎞
⎠
⎟•
I
O(MAX)
1– DMAX
where n represents the number of phases and χ repre-
sents the percentage peak-to-peak ripple current in the
inductor. For example, if the design goal is to have 30%
ripple current in the inductor, then χ = 0.30, and the peak
current is 15% greater than the average.
Inductor Selection
Given an input voltage range, operating frequency and
ripple current, the inductor value can be determined using
the following equation:
L=
V
IN(MIN)
∆I
L
• f • DMAX
where:
∆IL=χ
n•
I
O(MAX)
1– D
MAX
Choosing a larger value of ∆IL allows the use of a lower
value inductor but results in higher output voltage ripple,
greater core losses, and higher ripple current ratings for
the input and output capacitors. A reasonable starting
point is 30% ripple current in the inductor (χ = 0.3), or:
∆IL=0.3
n•
I
O(MAX)
1– DMAX
The inductor saturation current rating needs to be higher
than the worst-case peak inductor current during an
overload condition. If IO(MAX) is the maximum rated load
APPLICATIONS INFORMATION
LTC7840
24
Rev 0
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current, then the maximum current limit value (I
O(CL)
)
would normally be chosen to be some factor (e.g., 30%)
greater than IO(MAX).
IO(CL) = 1.3 • IO(MAX)
Reflecting this back to the input, where the current is being
measured, and accounting for the ripple current, gives a
minimum saturation current rating for the inductor of:
I
L(SAT) ≥1
n• 1+χ
2
⎛
⎝
⎜⎞
⎠
⎟•
1.3 •I
O(MAX)
1– D
MAX
The saturation current rating for the inductor should be
determined at the minimum input voltage (which results
in the highest duty cycle and maximum input current),
maximum output current and the maximum expected core
temperature. The saturation current ratings for most com-
mercially available inductors drop at high temperature.
To verify safe operation, it is a good idea to characterize
the inductor’s core/winding temperature under the fol-
lowing conditions: 1) worst-case operating conditions,
2) maximum allowable ambient temperature and 3) with
the power supply mounted in the final enclosure. Thermal
characterization can be done by placing a thermocouple
in intimate contact with the winding/core structure, or by
burying the thermocouple within the windings themselves.
Remember that a single-ended boost converter is not
short-circuit protected, and that under a shorted output
condition, the output current is limited only by the input
supply capability. For applications requiring a step-up
converter that is short-circuit protected, consider using
a SEPIC or forward converter topology.
Power MOSFET Selection
The peak-to-peak gate drive level is set by the DRVCC
voltage is 10V for the LTC7840 under normal operating
conditions. Selection criteria for the power MOSFETs
include the RDS(ON), gate charge QG, drain-to-source
breakdown voltage BVDSS, maximum continuous drain
current ID(MAX), and thermal resistances RTH(JA) and
RTH(JC)—both junction-to-ambient and junction-to-case.
APPLICATIONS INFORMATION
The gate driver for the LTC7840 consists of PMOS pull-
up and NMOS pull-down devices, allowing the full DRVCC
voltage to be applied to the gates during power MOSFET
switching. Nonetheless, care must be taken to ensure
that the minimum gate drive voltage is still sufficient to
full enhance the power MOSFET. Check the MOSFET data
sheet carefully to verify that the RDS(ON) of the MOSFET
is specified for a voltage less than or equal to the nominal
DRVCC voltage of 10V.
Also pay close attention to the BVDSS specifications for
the MOSFETs relative to the maximum actual switch volt-
age in the application. Check the switching waveforms of
the MOSFET directly on the drain terminal using a single
probe and a high bandwidth oscilloscope. Ensure that the
drain voltage ringing does not approach the BVDSS of the
MOSFET. Excessive ringing at high frequency is normally
an indicator of too much series inductance in the high di/
dt current path that includes the MOSFET, the boost diode,
the output capacitor, the sense resistor and the PCB traces
connecting these components.
The GATE of MOSFET Q1 could experience transient volt-
age spikes during turn-on and turn-off of the MOSFET,
due to parasitic lead inductance and improper PCB layout.
These voltage spikes could exceed the absolute maxi-
mum voltage ratings of LTC7840’s GATE pin. The GATE
pins are rated for an absolute maximum voltage of –0.3V
minimum and 11V maximum. Hence it is recommended
to add an external buffer close to the GATE of the MOSFET
as shown in Figure13.
Figure13.
LTC7840
GATE1, 2
VOUT
RSENSE
COUT
7840 F13
L
Q2A
PBS4140DPN
Q1
Q2B
10Ω
PGND
SGND
DRVCC
VIN
External Buffer Circuit
LTC7840
25
Rev 0
For more information www.analog.com
Finally, check the MOSFET manufacturer’s data sheet for
an avalanche energy rating (EAS). Some MOSFETs are not
rated for body diode avalanche and will fail catastrophi-
cally if the VDS exceeds the device BVDSS, even if only by
a fraction of a volt. Avalanche-rated MOSFETs are better
able to sustain high frequency drain-to-source ringing
near the device BVDSS during the turn-off transition.
Calculating Power MOSFET Switching and Conduction
Losses and Junction Temperatures
In order to calculate the junction temperature of the
power MOSFET, the power dissipated by the device must
be known. This power dissipation is a function of the
duty cycle, the load current and the junction temperature
itself (due to the positive temperature coefficient of its
R
DS(ON)
). As a result, some iterative calculation is nor-
mally required to determine a reasonably accurate value.
The power dissipated by the MOSFET in a multi-phase
boost converter with n phases is:
PFET =IO(MAX)
n • 1– DMAX
( )
⎛
⎝
⎜⎞
⎠
⎟
2
•RDS(ON) •DMAX •ρT
+k • VOUT2•IO(MAX)
n • 1– DMAX
( )
• CRSS • f
The first term in the equation above represents the I2R
losses in the device, and the second term, the switch-
ing losses. The constant, k = 1.7, is an empirical factor
inversely related to the gate drive current and has the
dimension of 1/current.
The ρT term accounts for the temperature coefficient of
the RDS(ON) of the MOSFET, which is typically 0.4%/ºC.
Figure14 illustrates the variation of normalized RDS(ON)
over temperature for a typical power MOSFET.
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
TJ = TA + PFET • RTH(JA)
The RTH(JA) to be used in this equation normally includes
the RTH(JC) for the device plus the thermal resistance from
the case to the ambient temperature (RTH(CA)). This value
of TJ can then be compared to the original, assumed value
used in the iterative calculation process.
It is tempting to choose a power MOSFET with a very low
RDS(ON) in order to reduce conduction losses. In doing
so, however, the gate charge Q
G
is usually significantly
higher, which increases switching and gate drive losses.
Since the switching losses increase with the square of
the output voltage, applications with a low output voltage
generally have higher MOSFET conduction losses, and
high output voltage applications generally have higher
MOSFET switching losses. At high output voltages, the
highest efficiency is usually obtained by using a MOSFET
with a higher RDS(ON) and lower QG. The equation above
can easily be split into two components (conduction and
switching) and entered into a spreadsheet, in order to
compare the performance of different MOSFETs.
APPLICATIONS INFORMATION
Figure14.
JUNCTION TEMPERATURE (°C)
–50
ρT
NORMALIZED ON RESISTANCE
1.0
1.5
150
7840 F14
0.5
0050 100
2.0
Normalized Power MOSFET RDS(ON) vs Temperature
LTC7840
26
Rev 0
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Programming the Current Limit
The LTC7840 has ILIM1 and ILIM2 pins to adjust the cur-
rent comparator’s maximum sense voltage for Channel1
and Channel 2 respectively. There is a precise 10µA cur-
rent flowing out of ILIM pin. A resistor to SGND can set
the voltage on ILIM pin to program the peak current sense
threshold to any voltage lower than 75mV. Alternatively,
a DC voltage which is lower than 0.5V can be added to
ILIM pin to adjust the maximum current sense threshold.
Floating ILIM pin or adding any voltage higher than 0.5V
make the current comparator’s maximum sense voltage
be 75mV.
For a boost converter where the current limit value is
chosen to be 30% higher than the maximum load current,
the peak current in the MOSFET and sense resistor is:
I
SW(MAX) =IR(SENSE) =1
n• 1+χ
2
⎛
⎝
⎜⎞
⎠
⎟•
1.3 • I
O(MAX)
1– D
MAX
The sense resistor value is then:
RSENSE =VSENSE(MAX) • n • 1– DMAX
( )
1.3 • 1+χ
2
⎛
⎝
⎞
⎠• IO(MAX)
Again, the factor n is the number of phases used, and χ
represents the percentage ripple current in the inductor.
The number 1.3 represents the factor by which the cur-
rent limit exceeds the maximum load current, I
O(MAX)
. For
example, if the current limit needs to exceed the maxi-
mum load current by 50%, then the 1.3 factor should be
replaced with 1.5.
The average power dissipated in the sense resistor can
easily be calculated as:
PR(SENSE) =1.3 •IO(MAX)
n • 1– DMAX
( )
⎛
⎝
⎜⎞
⎠
⎟
2
•RSENSE •DMAX
APPLICATIONS INFORMATION
This equation assumes no temperature coefficient for the
sense resistor. If the resistor chosen has a significant tem-
perature coefficient, then substitute the worst-case high
resistance value into the equation.
The resistor temperature can be calculated using the
equation:
TD = TA + PR(SENSE) • RTH(JA)
Selecting the Output Diodes
To maximize efficiency, a fast switching diode with low
forward drop and low reverse leakage is required. The
output diode in a boost converter conducts current dur-
ing the switch off-time. The peak reverse voltage that the
diode must withstand is equal to the regulator output volt-
age. The average forward current in normal operation is
equal to the output current, and the peak current is equal
to the peak inductor current:
IIN =
I
OUT
• V
OUT
V
IN
Although the average diode current is equal to the output
current, in very high duty cycle applications (low VIN to
high VOUT) the peak diode current can be several times
higher than the average, as shown in Figure15. In this
case check the diode manufacturer’s data sheet to ensure
that its peak current rating exceeds the peak current in
the equation above. In addition, when calculating the
power dissipation in the diode, use the value of the for-
ward voltage (VF) measured at the peak current, not the
average output current. Excess power will be dissipated
in the series resistance of the diode, which would not be
accounted for if the average output current and forward
voltage were used in the equations. Finally, this additional
power dissipation is important when deciding on a diode
current rating, package type, and method of heat sinking.
LTC7840
27
Rev 0
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SW NODE
50V/DIV
INDUCTOR
CURRENT
1A/DIV
DIODE
CURRENT
1A/DIV
1µs/DIV 7840 F15
VIN = 12V
VOUT = 72V
Figure15. Diode Current Waveform for a High
Duty Cycle Application
To a close approximation, the power dissipated by the
diode is:
PD = ID(PEAK) • VF(PEAK) • (1 – DMAX)
The diode junction temperature is:
TJ = TA + PD • RTH(JA)
The RTH(JA) to be used in this equation normally includes
the RTH(JC) for the device plus the thermal resistance from
the board to the ambient temperature in the enclosure.
Once the proper diode has been selected and the circuit
performance has been verified, measure the temperature
of the power components using a thermal probe or infra-
red camera over all operating conditions to ensure a good
thermal design.
Finally, remember to keep the diode lead lengths short and
to observe proper switch-node layout (see Board Layout
Checklist) to avoid excessive ringing and increased
dissipation.
Output Capacitor Selection
Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
must be considered when choosing the correct combina-
tion of output capacitors for a boost converter applica-
tion. The effects of these three parameters on the output
voltage ripple waveform are illustrated in Figure16 for a
typical boost converter.
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step and the charging/discharging ∆V.
For the purpose of simplicity we will choose 2% for the
maximum output ripple, to be divided equally between the
ESR step and the charging/discharging ∆V. This percent-
age ripple will change, depending on the requirements
of the application, and the equations provided below can
easily be modified.
One of the key benefits of multi-phase operation is a reduc-
tion in the peak current supplied to the output capacitor
by the boost diodes. As a result, the ESR requirement
of the capacitor is relaxed. For a 1% contribution to the
total ripple voltage, the ESR of the output capacitor can
be determined using the following equation:
ESRCOUT ≤
0.01• V
OUT
ID(PEAK)
where:
ID(PEAK) =1
n• 1+χ
2
⎛
⎝
⎜⎞
⎠
⎟•
I
O(MAX)
1– D
MAX
The factor n represents the number of phases and the
factor χ represents the percentage inductor ripple current.
APPLICATIONS INFORMATION
Figure16. Switching Waveforms for a Boost Converter
SW1
100V/DIV
SW2
100V/DIV
VOUT
100mV/DIV
AC COUPLED
IL1
2A/DIV
IL2
2A/DIV
1µs/DIV 7840 F16
VIN = 24V
VOUT = 72V
350mA LOAD
LTC7840
28
Rev 0
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For the bulk capacitance, which we assume contributes
1% to the total output ripple, the minimum required
capacitance is approximately:
C
OUT ≥
I
O(MAX)
0.01• n • VOUT • f
For many designs it will be necessary to use one type of
capacitor to obtain the required ESR, and another type to
satisfy the bulk capacitance. For example, using a low ESR
ceramic capacitor can minimize the ESR step, while an
electrolytic capacitor can be used to supply the required
bulk C.
The voltage rating of the output capacitor must be greater
than the maximum output voltage, with sufficient derating
to account for the maximum capacitor temperature.
Because the ripple current in the output capacitor is a
square wave, the ripple current requirements for this
capacitor depend on the duty cycle, the number of phases
and the maximum output current. Figure17 illustrates the
normalized output capacitor ripple current as a function of
duty cycle. In order to choose a ripple current rating for
the output capacitor, first establish the duty cycle range,
based on the output voltage and range of input voltage.
APPLICATIONS INFORMATION
Referring to Figure17, choose the worst-case high nor-
malized ripple current, as a percentage of the maximum
load current.
The output ripple current is divided between the various
capacitors connected in parallel at the output voltage.
Although ceramic capacitors are generally known for low
ESR (especially X5R and X7R), these capacitors suffer
from a relatively high voltage coefficient. Therefore, it is
not safe to assume that the entire ripple current flows in
the ceramic capacitor. Aluminum electrolytic capacitors
are generally chosen because of their high bulk capaci-
tance, but they have a relatively high ESR. As a result,
some amount of ripple current will flow in this capaci-
tor. If the ripple current flowing into a capacitor exceeds
its RMS rating, the capacitor will heat up, reducing its
effective capacitance and adversely affecting its reliabil-
ity. After the output capacitor configuration has been
determined using the equations provided, measure the
individual capacitor case temperatures in order to verify
good thermal performance.
Input Capacitor Selection
The input capacitor voltage rating in a boost converter
should comfortably exceed the maximum input voltage.
Although ceramic capacitors can be relatively tolerant of
overvoltage conditions, aluminum electrolytic capacitors
are not. Be sure to characterize the input voltage for any
possible overvoltage transients that could apply excess
stress to the input capacitors.
The value of the input capacitor is a function of the
source impedance, and in general, the higher the source
impedance, the higher the required input capacitance.
The required amount of input capacitance is also greatly
affected by the duty cycle. High output current applica-
tions that also experience high duty cycles can place great
demands on the input supply, both in terms of DC current
and ripple current.
The input ripple current in a multi-phase boost converter
is relatively low (compared with the output ripple current),
because this current is continuous and is being divided
Figure17. Normalized Output Capacitor
Ripple Current (RMS) for a Boost Converter
0.1
IORIPPLE/IOUT
0.9
7840 F17
0.3 0.5 0.7 0.8
0.2 0.4 0.6
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
DUTY CYCLE OR (1-VIN/VOUT)
1-PHASE
2-PHASE
LTC7840
29
Rev 0
For more information www.analog.com
between two or more inductors. Nonetheless, significant
stress can be placed on the input capacitor, especially
in high duty cycle applications. Figure18 illustrates the
normalized input ripple current, where:
I
NORM =
V
IN
L • f
Figure18.
DUTY CYCLE
0
ΔIIN/INORM
1.00
0.90
0.80
0.60
0.70
0.50
0.40
0.30
0.20
0.10
00.8
7840 F18
0.2 0.4 0.6 1.0
1-PHASE
2-PHASE
Normalized Input Peak-to-Peak Ripple Current
Soft Start (SS Pin) Capacitor Selection
The LTC7840 has hiccup mode to protect the system in
the event of overcurrent. Because the hiccup mode timing
is set by discharging the soft start capacitor, at least 0.1µF
capacitor must be tied between SS pin and SGND. At start
up, an 10µA current flowing out of SS pin to charge the
soft start capacitor. The hiccup mode is disabled until the
voltage on SS pin ramps up to 1.32V (10% higher than
the 1.2V internal reference). For a properly configured
system, the output’s feedback voltage tracks the voltage
on SS pin until it reaches 1.2V. At this moment, the con-
verter’s output voltage reaches the regulated value and the
system enters the steady state. If the target output voltage
is high or if heavy loaded, the soft start capacitor needs to
be larger to slow down the ramp up speed, otherwise, the
converter’s output voltage cannot follow the voltage on SS
pin in time. At the same time, the system keeps operating
at the maximum current limit. This situation is thought
as overcurrent event by the controller. Once the voltage
on SS pin reaches 1.32V, the hiccup mode is enabled to
make the converter enter the sleep mode even though
the output voltage hasn’t reached the target value. In this
case, the system cannot start up normally.
Checking the Load Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD • (ESR), where ESR is the effective
series resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT, generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stabilityproblem.
The availability of the ITH pin not only allows optimization
of control loop behavior but also provides a DC coupled
and AC filtered closed loop response test point. The DC
step, rise time and settling at this test point truly reflects
the closed loop response. Assuming a predominantly sec-
ond order system, phase margin and/or damping factor
can be estimated using the percentage of overshoot seen
at this pin. The bandwidth can also be estimated by exam-
ining the rise time at the pin.
The ITH series RC • CC filter sets the dominant pole-zero
loop compensation. The transfer function for boost and
flyback converters contains a right half plane zero that nor-
mally requires the loop crossover frequency to be reduced
significantly in order to maintain good phase margin.
The RC • CC filter values can typically be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type(s) and value(s) have been
determined. The output capacitor configuration needs to
be selected in advance because the effective ESR and bulk
capacitance have a significant effect on the loop gain and
phase. An output current pulse of 20% to 80% of full-load
current having a rise time of 1μs to 10μs will produce out-
put voltage and ITH pin waveforms that will give a sense
APPLICATIONS INFORMATION
LTC7840
30
Rev 0
For more information www.analog.com
of the overall loop stability without breaking the feedback
loop. Placing a power MOSFET and load resistor directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a fast load step condition. The initial output voltage step
resulting from the step change in the output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This is
why it is better to look at the ITH pin signal which is in the
feedback loop and is the filtered and compensated con-
trol loop response. The gain of the loop will be increased
by increasing RC and the bandwidth of the loop will be
increased by decreasing C
C
. If R
C
is increased by the same
factor that C
C
is decreased, the zero frequency will be kept
the same, thereby keeping the phase shift the same in the
most critical frequency range of the feedback loop. The
output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. Figure19 illustrates the load
step response of a properly compensated boost converter.
Figure19.
V
IN
= 12V
V
OUT
=36V
20µs/DIV
7840 F19
LOAD CURRENT
500mA/DIV
INDUCTOR CURRENT
500mA/DIV
Load Step Response of a Properly
Compensated Boost Converter
APPLICATIONS INFORMATION
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the converter:
1. For lower power applications a 2-layer PC board is suf-
ficient. However, for higher power levels, a multilayer
PC board is recommended. Using a solid ground plane
and proper component placement under the circuit is
the easiest way to ensure that switching noise does
not affect the operation.
2. In order to help dissipate the power from the MOSFETs
and diodes, keep the ground plane on the layers clos-
est to the power components. Use power planes for
the MOSFETs and diodes in order to maximize the heat
spreading from these components into the PCB.
3. Place all power components in a tight area. This will
minimize the size of high current loops. The high di/
dt loops formed by the sense resistor, power MOSFET,
the boost diode and the output capacitor should be
kept as small as possible to avoid EMI.
4. Orient the input and output capacitors and current
sense resistors in a way that minimizes the distance
between the pads connected to the ground plane. Keep
the capacitors for INTVCC, DRVCC and VIN as close as
possible to LTC7840.
5. Place the DRVCC decoupling capacitor as close as pos-
sible to the DRVCC and PGND pins, on the same layer
as the IC. A low ESR (X5R or better) 4.7μF to 10μF
ceramic capacitor should be used.
6. Use a local via to ground plane for all pads that
connect to the ground. Use multiple vias for power
components.
LTC7840
31
Rev 0
For more information www.analog.com
7. Place the small-signal components away from high
frequency switching nodes on the board. The pinout
of the LTC7840 was carefully designed in order to
make component placement easy. All of the power
components can be placed on one side of the IC, away
from all of the small-signal components.
8. The exposed area on the bottom of the package is
internally connected to SGND.
9. The MOSFETs should also be placed on the same
layer of the board as the sense resistors. The MOSFET
source should connect to the sense resistor using a
short, wide PCB trace.
10. The output resistor divider should be located as close
as possible to the IC, with the bottom resistor con-
nected between VFB pin and SGND. The PCB trace
connecting the top resistor to the upper terminal of
the output capacitor should avoid any high frequency
switching nodes.
11. Since the inductor acts like a current source in a peak
current mode control topology, its placement on the
board is less critical than the high di/dt components.
12. The SENSE
+
and SENSE
–
PCB traces should be routed
parallel to one another with minimum spacing in
between all the way to the sense resistor. These traces
should avoid any high frequency switching nodes in
the layout. These PCB traces should also be Kelvin-
connected to the interior of the sense resistor pads,
in order to avoid sensing errors due to parasitic PCB
resistance IR drops.
13. If an external RC filter is used between the sense resis-
tor and the SENSE
+
and SENSE
–
pins, these filter com-
ponents should be placed as close as possible to the
SENSE+ and SENSE– pins of the IC. Ensure that the
SENSE
–
line is connected to the ground only at the
point where the current sense resistor is grounded.
14. Keep the MOSFET drain nodes (SW1, SW2) away
from sensitive small-signal nodes, especially from the
opposite channel’s current-sensing signals. The SW
nodes can have slew rates in excess of 1V/ns relative
to ground and should therefore be kept on the “output
side” of the LTC7840.
15. Check the stress on the power MOSFETs by indepen-
dently measuring the drain-to-source voltages directly
across the devices terminals. Beware of inductive ring-
ing that could exceed the maximum voltage rating of
the MOSFET. If this ringing cannot be avoided and
exceeds the maximum rating of the device, choose
a higher voltage rated MOSFET or consider using a
snubber.
16. When synchronizing the LTC7840 to an external clock,
use a low impedance source such as a logic gate to
drive the SYNC pin and keep the lead as short as
possible.
APPLICATIONS INFORMATION
LTC7840
32
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
Design Example
A two-stage step up converter is shown in Figure20. The
two channels of LTC7840 are connected in cascade, i.e.,
the output of Channel1 is tied to the input of Channel2.
The output voltage of Channel1 is 48V and the output
voltage of Channel2 is 240V. The input voltage range
of Channel1 is 9V to 36V. The maximum output current
of Channel2 is 0.7A when the input voltage of Channel
1 is 12V.
1. The duty cycle range is:
DMAX1 =VO1 +VF– VIN1
VO1 +VF
⎛
⎝
⎜⎞
⎠
⎟
=48V +0.5V – 12V
48V +0.5V
⎛
⎝
⎜⎞
⎠
⎟=75.3%
DMIN1 =48V +0.5V – 36V
48V +0.5V
⎛
⎝
⎜⎞
⎠
⎟=25.8%
DMAX2 =VO2 +VF– VO1
VO2 +VF
⎛
⎝
⎜⎞
⎠
⎟
=240V +0.5V – 48V
240V +0.5V
⎛
⎝
⎜⎞
⎠
⎟=80%
2. The operating frequency is chosen to be 150kHz so
the period is 6.67μs. From Figure6, the resistor from
the FREQ pin to SGND is 73.2k.
3. Channel 2 maximum DC input current is:
IIN2(MAX) =
I
O2(MAX)
1– D
MAX2
=0.7A
1– 0.8 =3.5A
Channel 1 maximum DC input current is:
IIN1(MAX) =IO1(MAX)
1– DMAX1
=IIN2(MAX)
1– DMAX1
=3.5A
1– 0.753
=14.17A
4. A ripple current of 40% is chosen so the peak current
in each inductor is:
IL1(PK) =1+
χ
2
⎛
⎝
⎜⎞
⎠
⎟•IIN1(MAX) =1+
0.4
2
⎛
⎝
⎜⎞
⎠
⎟• 14.17A
=17A
I
L2(PK) =1+χ
2
⎛
⎝
⎜⎞
⎠
⎟•IIN2(MAX) =1+0.4
2
⎛
⎝
⎜⎞
⎠
⎟• 3.5A
=4.2A
Figure20. 12V Input, 240V/0.7A Output Two-Stage Boost Converter
SW1
RUN1
ITH1
INTVCC
SGND
DRVCC
PGND
LTC7840
7840 F20
1nF
0.1µF
10µF
0805
VFB2
RUN2 PGOOD1 PGOOD2
33nF
100pF
73.2k
12.1k
84.5k
4.7µFx4
100V
1210
+
33µF
63V
10µH
SER2918H-103KL V8P10
IDD04SG60C
11.8k
12.1k
475k
0805
15k
ITH2
47nF
100pF
46.4k
2.37M
1206
SS2
2.2µF
+
2mΩ
2010
1mΩ
2010
10nF 33µFx2
80V
4.7µFx7
100V
1210
+
8mΩ
2010
100µF
x2
400V
33µF
80V
VOUT1
48V
VOUT
240V
0.7A
2.2µFx4
450V
2220
100µH
PCV-2-104-05L
VIN
12V
BLANK
CLKOUT
SYNC
DMAX
BSC047N08
STB45N40DM2AG
10Ω
10nF
10Ω
+
SW2
GATE2
SENSE2+
SENSE2–
VIN GATE1
SENSE1+
ILIM1
SENSE1–
GATE2
SENSE2+
ILIM2
SENSE2–
VFB1
FREQ
SS1
LTC7840
33
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
5. The inductor peak-to-peak ripple current is:
∆
I
L1 =
40% • I
IN1 MAX
( )
=
0.4 • 14.17A
=
5.67A
∆IL2 =40% • IIN2 MAX
( )
=0.4 • 3.5A =1.4A
6. The inductor value is therefore:
L1=
V
IN1
∆IL1 • f • DMAX1 =
12V
5.67A • 150kHz • 0.75
3
=10.62µH
L
2=VIN2
∆IL2 • f • DMAX2 =48V
1.4A • 150kHz • 0.8
=183µH
7. For a current limit value 30% higher than the maxi-
mum load current, the saturation current rating of the
inductors must therefore exceed:
IL1(SAT) ≥1.3 • IL1 PK
( )
=1.3 • 17A =22.1A
IL2(SAT) ≥1.3 • IL2 PK
( )
=1.3 • 4.2A =5.46A
In order to obtain higher efficiency with acceptable
ripple, the Channel1 inductor value chosen is 10µH
and the part number is SER2918H-103KL. This
inductor has a saturation current rating of 28A. The
Channel2 inductor chosen is 100µH and the part
number is PCV-2-104-05L.
8. The power MOSFET of Channel1 chosen for this
application is an Infineon BSC047N08. This MOSFET
has a typical R
DS(ON)
of 3.9mΩ at V
GS
= 10V. The
BVDSS is rated at a minimum of 80V and the maxi-
mum continuous drain current is 100A. The typical
gate charge is 52nC for VGS = 0V to 10V. The power
MOSFET of Channel2 chosen for this application is an
STMicroelectronics STB45N40DM2AG. This MOSFET
has a typical RDS(ON) of 63mΩ at VGS=10V. The
BVDSS is rated at a minimum of 400V and the maxi-
mum continuous drain current is 38A. The typical
gate charge is 56nC for VGS = 10V.
9. The total IC quiescent current, IC power dissipation and
maximum junction temperature are approximately:
IQ(TOT) = IQ + QG1(TOT) • f + QG2(TOT) • f
= 3mA + 52nC • 150kHz + 56nC • 150kHz
= 19.2mA
PDISS = 12V • 19.2mA = 230.4mW
TJ = 70°C + 230.4mW • 30°C/W = 76.9°C
10. For a current limit set at 30% above the maximum
load current, the peak switch and sense resistor cur-
rents are:
ISW1(PK) = IR1(PK) = 1.3 • IL1(PK) = 1.3 • 17A = 22.1A
ISW2(PK) = IR2(PK) = 1.3 • IL2(PK) = 1.3 • 4.2A =5.46A
11. The maximum current sense threshold for the
LTC7840 is 75mV when ILIM1 and ILIM2 pins are
floating. This threshold keeps constant over duty
cycle. The sense resistor is calculated to be:
R
SENSE1 =
V
SENSE(MAX)
ISW1 PK
( )
=75mV
22.1A =3.4mΩ
R
SENSE2 =VSENSE(MAX)
I
SW2 PK
( )
=75mV
5.46A =13.7m
Ω
For this application, a 2mΩ surface mount resistor
is used for Channel 1 and an 8mΩ surface mount
resistor is used for Channel 2.
12. The power dissipation in the sense resistors at current
limit is:
PR1(SENSE) =1.3 • IIN1(MAX)
( )
2• RSENSE1 • DMAX1
=1.3 • 14.17A
( )
2• 2mΩ• 0.753
=0.51W
PR2(SENSE) =1.3 • IIN2(MAX)
( )
2• RSENSE2 • DMAX2
=1.3 • 3.5A
( )
2• 8mΩ• 0.8
=0.13W
LTC7840
34
Rev 0
For more information www.analog.com
13. The average current in the boost diodes is half the
output current:
I
D1 =
I
O1(MAX)
2=3.5A
2=1.75A
I
D2 =IO2(MAX)
2
=0.7A
2
=0.35A
14. The peak current in each boost diode is:
ID1(PK) = IL1(PK) = 17A
ID2(PK) = IL2(PK) = 4.2A
The diode chosen for Channel 1 is the V8P10, manu-
factured by Vishay General Semiconductor. This sur-
face mount diode has a maximum average forward
current of 8A at 25°C and a maximum reverse voltage
of 100V. The maximum forward voltage at 25°C is
0.522V at 25°C and 0.466V at 125°C when forward
current is 4A. The diode chosen for Channel 2 is the
IDD04SG60C, manufactured by Infineon. This diode
has a maximum average forward current of 4A when
temperature is lower than 130°C and a maximum
reverse voltage of 600V at 25°C. The maximum for-
ward voltage at 25°C is 2.1V at 25°C and 2.8V at
125°C when forward current is 4A.
The power dissipated by the diode is approximately:
PD1 = ID1(PK) • VF1(PK) • (1 – DMAX1)
= 17A • 0.466V • (1 – 0.753) = 1.96W
PD2 = ID2(PK) • VF2(PK) • (1 – DMAX2)
= 4.2A • 2.8V • (1 – 0.8) = 2.35W
15. Two types of output capacitors are connected in paral
-
lel for this application; a low ESR ceramic capacitor
and an aluminum electrolytic for bulk storage. For a
1% contribution to the total ripple voltage, the maxi-
mum ESR of the composite output capacitance is
approximately:
E
SRCOUT1 ≤
0.01• V
OUT1
ID1(PK)
=
0.01• 48V
17A =0.028Ω
E
SRCOUT2 ≤0.01• VOUT2
I
D2(PK)
=0.01• 240V
4.2A =0.57
Ω
For the bulk capacitance, which we assume con-
tributes 1% to the total output ripple, the minimum
required capacitance is approximately:
C
OUT1 ≥
I
O1(MAX)
0.01• VOUT1 • f =
3.5A
0.01• 48V • 150kHz
=48.6µF
C
OUT2 ≥IO2 MAX
( )
0.01• VOUT2 • f =0.7A
0.01• 240V • 150kH
z
=1.94µF
For this application, in order to obtain both low ESR
and an adequate ripple current rating, Channel 1 has
two 33µF, 80V aluminum electrolytic capacitors con-
nected in parallel with seven 4.7µF, 100V ceramic
capacitors. Channel 2 has two 100µF, 400V aluminum
electrolytic capacitors connected in parallel with four
2.2µF, 450V ceramic capacitors.
APPLICATIONS INFORMATION
LTC7840
35
Rev 0
For more information www.analog.com
TYPICAL APPLICATIONS
Figure21. Dual Output 12V/2A, 48V/1A Converter with Channel 1 Configured as SEPIC and Channel 2 Configured as Boost Converter
+
VIN
9V
10Ω
10Ω
BSC014N06NS
BSC047N08
VFB1
FREQ
SS1
ITH1 INTVCC
SGND
DRVCC
PGND
LTC7840
7840 TA02
1nF
10nF
10nF
0.22µF
4.7µF
6.8µFx4
50V
X7R 1812
RUN1
RUN2
VFB2 ILIM2
ILIM1
6.8nF
330pF
158k
12.1k
13k
118k
15.4k
ITH2
33nF
100pF
15k
475k
SS2
0.1µF
••
5mΩ
2010
6.8µFx2
50V
X7R 1812
+
330µF
16V
+
2mΩ
2010
33µFx2
80V
4.7µFx7
100V
1210
VOUT1
12V/2A
VOUT2
48V/1A
10µH
SER2918H-103KL
6.8µH
WURTH 744870006
MBR560MFS
33µF
63V
4.7µFx4
100V
1210
VIN
GATE1
SENSE1+
SENSE1–
GATE2
SENSE2+
SENSE2–
V8P10
BLANK
CLKOUT
SYNC
DMAX
PGOOD1 PGOOD2
LTC7840
36
Rev 0
For more information www.analog.com
PACKAGE DESCRIPTION
FE28 (EA) TSSOP REV L 0117
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 4 5678 9 10 11 12 13 14
192022 21 151618 17
9.60 – 9.80*
(.378 – .386)
7.56
(.298)
3.05
(.120)
28 2726 25 24 23
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
2
RECOMMENDED SOLDER PAD LAYOUT
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
7.56
(.298)
3.05
(.120)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev L)
Exposed Pad Variation EA
LTC7840
37
Rev 0
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
4.00 ±0.10
(2 SIDES)
2.50 REF
5.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
27 28
1
2
BOTTOM VIEW—EXPOSED PAD
3.50 REF
0.75 ±0.05 R = 0.115
TYP
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UFD28) QFN 0816 REV C
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.50 REF
3.50 REF
4.10 ±0.05
5.50 ±0.05
2.65 ±0.05
3.10 ±0.05
4.50 ±0.05
PACKAGE OUTLINE
2.65 ±0.10
3.65 ±0.10
3.65 ±0.05
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev C)
PACKAGE DESCRIPTION
LTC7840
38
Rev 0
For more information www.analog.com
ANALOG DEVICES, INC. 2018
D16991-0-7/18(0)
www.analog.com
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LTC3788/LTC3788-1 Dual Output, Low IQ Multiphase Synchronous
Boost Controller
4.5V (Down to 2.5V after Start-Up) ≤ VIN ≤ 38V, VOUT up to 60V, 50kHZ to
900kHz Fixed Operating Frequency, 5mm x 5mm QFN-32, SSOP-28
LTC3787 Single Output, Low IQ Multiphase Synchronous
Boost Controller
4.5V (Down to 2.5V after Start-Up) ≤ VIN ≤ 38V, VOUT up to 60V, 50kHZ to
900kHz Fixed Operating Frequency, 4mm x 5mm QFN-28, SSOP-28
LTC3769 60V Low IQ Synchronous Boost Controller 4.5V (Down to 2.3V after Start-up) ≤ VIN ≤ 60V, VOUT up to 60V, 50kHZ to 900kHz
Fixed Operating Frequency, 4mm x 4mm QFN-24, TSSOP-20
LTC3784 60V Single Output, Low IQ Multiphase
Synchronous Boost Controller
4.5V (Down to 2.3V after Start-Up) ≤ VIN ≤ 60V, VOUT up to 60V, 50kHZ to
900kHz Fixed Operating Frequency, 4mm x 5mm QFN-28, SSOP-28
LTC3862/LTC3862-2 Single Output, Multiphase Non-synchronous
Current Mode Step-Up DC/DC Controller
4V ≤ VIN ≤ 36V, 5V or 10V Gate Drive, 75kHZ to 500kHz Fixed Operating
Frequency, SSOP-24, TSSOP-24, 5mm x 5mm QFN-24
LT3757/LT3758 Boost, Flyback, SEPIC and Inverting Controller 2.9V ≤ VIN ≤ 40V/100V, 100kHz to 1MHz Fixed Operating Frequency, 3mm x 3mm
DFN-10 and MSOP-10E
LTC1871, LTC1871-1,
LTC1871-7
Wide Input Range, No Rsense Low IQ Boost,
Flyback and SEPIC Controller
2.5V ≤ VIN ≤ 36V, 50kHz to 1MHz Fixed Operating Frequency, MSOP-10
LTC7815 Low IQ, Up to 2.25MHz, Triple Output Buck/
Buck/Boost Synchronous DC/DC Controller
All Outputs Remain in Regulation Through Cold Crank, 4.5V (Down to 2.5V after
Start-up) ≤ VIN ≤ 38V, VOUT(BUCKS) Up to 24V, VOUT(BOOST) Up to 60V, IQ = 28µA
LTC3789 High Efficiency Synchronous 4-Switch Buck-
Boost DC/DC Controller
4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 38V, SSOP-28, 4mm x 5mm QFN-28, SSOP-28
LT8710 Synchronous SEPIC/ Inverting/Boost Controller
with Output Current Control
4V ≤ VIN ≤ 80V, SSOP-28, TSSOP-20
12V Input, 24V/2A Output 2-Phase Boost Converter
+
VIN
12V
RUN1
RUN2
INTVCC
SGND
DRVCC
PGND
LTC7840
7840 TA04
4.7µFx4
50V
PGOOD1
PGOOD2
1nF
4.7µF
VFB1
VFB2
82µH
WURTH
7447709820
12.1k
226k
ITH1
ITH2
6.8nF
100pF 14.2k
SS1
SS2
0.47µF
10nF
10nF
+
20mΩ
68µF
35V
4.7µFx4
50V
+
20mΩ
68µF
35V
VOUT
24V/2A
82µH
WURTH 7447709820
FREQ
100k
68µF
63V
4.7µFx4
100V
1210
10Ω
10Ω
BSC047N08NS
BSC047N08NS
B560C-13-F
B560C-13-F
BLANK
CLKOUT
SYNC
DMAX
ILIM2
ILIM1
VIN
GATE1
SENSE1+
SENSE1–
GATE2
SENSE2+
SENSE2–